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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
[deliverable/linux.git] / drivers / net / epic100.c
1 /* epic100.c: A SMC 83c170 EPIC/100 Fast Ethernet driver for Linux. */
2 /*
3 Written/copyright 1997-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 This driver is for the SMC83c170/175 "EPIC" series, as used on the
13 SMC EtherPower II 9432 PCI adapter, and several CardBus cards.
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 Information and updates available at
21 http://www.scyld.com/network/epic100.html
22 [this link no longer provides anything useful -jgarzik]
23
24 ---------------------------------------------------------------------
25
26 */
27
28 #define DRV_NAME "epic100"
29 #define DRV_VERSION "2.1"
30 #define DRV_RELDATE "Sept 11, 2006"
31
32 /* The user-configurable values.
33 These may be modified when a driver module is loaded.*/
34
35 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
36
37 /* Used to pass the full-duplex flag, etc. */
38 #define MAX_UNITS 8 /* More are supported, limit only on options */
39 static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
40 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
41
42 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
43 Setting to > 1518 effectively disables this feature. */
44 static int rx_copybreak;
45
46 /* Operational parameters that are set at compile time. */
47
48 /* Keep the ring sizes a power of two for operational efficiency.
49 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
50 Making the Tx ring too large decreases the effectiveness of channel
51 bonding and packet priority.
52 There are no ill effects from too-large receive rings. */
53 #define TX_RING_SIZE 256
54 #define TX_QUEUE_LEN 240 /* Limit ring entries actually used. */
55 #define RX_RING_SIZE 256
56 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct epic_tx_desc)
57 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct epic_rx_desc)
58
59 /* Operational parameters that usually are not changed. */
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (2*HZ)
62
63 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
64
65 /* Bytes transferred to chip before transmission starts. */
66 /* Initial threshold, increased on underflow, rounded down to 4 byte units. */
67 #define TX_FIFO_THRESH 256
68 #define RX_FIFO_THRESH 1 /* 0-3, 0==32, 64,96, or 3==128 bytes */
69
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/string.h>
73 #include <linux/timer.h>
74 #include <linux/errno.h>
75 #include <linux/ioport.h>
76 #include <linux/slab.h>
77 #include <linux/interrupt.h>
78 #include <linux/pci.h>
79 #include <linux/delay.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/init.h>
84 #include <linux/spinlock.h>
85 #include <linux/ethtool.h>
86 #include <linux/mii.h>
87 #include <linux/crc32.h>
88 #include <linux/bitops.h>
89 #include <asm/io.h>
90 #include <asm/uaccess.h>
91
92 /* These identify the driver base version and may not be removed. */
93 static char version[] __devinitdata =
94 DRV_NAME ".c:v1.11 1/7/2001 Written by Donald Becker <becker@scyld.com>\n";
95 static char version2[] __devinitdata =
96 " http://www.scyld.com/network/epic100.html\n";
97 static char version3[] __devinitdata =
98 " (unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
99
100 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
101 MODULE_DESCRIPTION("SMC 83c170 EPIC series Ethernet driver");
102 MODULE_LICENSE("GPL");
103
104 module_param(debug, int, 0);
105 module_param(rx_copybreak, int, 0);
106 module_param_array(options, int, NULL, 0);
107 module_param_array(full_duplex, int, NULL, 0);
108 MODULE_PARM_DESC(debug, "EPIC/100 debug level (0-5)");
109 MODULE_PARM_DESC(options, "EPIC/100: Bits 0-3: media type, bit 4: full duplex");
110 MODULE_PARM_DESC(rx_copybreak, "EPIC/100 copy breakpoint for copy-only-tiny-frames");
111 MODULE_PARM_DESC(full_duplex, "EPIC/100 full duplex setting(s) (1)");
112
113 /*
114 Theory of Operation
115
116 I. Board Compatibility
117
118 This device driver is designed for the SMC "EPIC/100", the SMC
119 single-chip Ethernet controllers for PCI. This chip is used on
120 the SMC EtherPower II boards.
121
122 II. Board-specific settings
123
124 PCI bus devices are configured by the system at boot time, so no jumpers
125 need to be set on the board. The system BIOS will assign the
126 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
127 Note: Kernel versions earlier than 1.3.73 do not support shared PCI
128 interrupt lines.
129
130 III. Driver operation
131
132 IIIa. Ring buffers
133
134 IVb. References
135
136 http://www.smsc.com/main/datasheets/83c171.pdf
137 http://www.smsc.com/main/datasheets/83c175.pdf
138 http://scyld.com/expert/NWay.html
139 http://www.national.com/pf/DP/DP83840A.html
140
141 IVc. Errata
142
143 */
144
145
146 enum chip_capability_flags { MII_PWRDWN=1, TYPE2_INTR=2, NO_MII=4 };
147
148 #define EPIC_TOTAL_SIZE 0x100
149 #define USE_IO_OPS 1
150
151 typedef enum {
152 SMSC_83C170_0,
153 SMSC_83C170,
154 SMSC_83C175,
155 } chip_t;
156
157
158 struct epic_chip_info {
159 const char *name;
160 int drv_flags; /* Driver use, intended as capability flags. */
161 };
162
163
164 /* indexed by chip_t */
165 static const struct epic_chip_info pci_id_tbl[] = {
166 { "SMSC EPIC/100 83c170", TYPE2_INTR | NO_MII | MII_PWRDWN },
167 { "SMSC EPIC/100 83c170", TYPE2_INTR },
168 { "SMSC EPIC/C 83c175", TYPE2_INTR | MII_PWRDWN },
169 };
170
171
172 static struct pci_device_id epic_pci_tbl[] = {
173 { 0x10B8, 0x0005, 0x1092, 0x0AB4, 0, 0, SMSC_83C170_0 },
174 { 0x10B8, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMSC_83C170 },
175 { 0x10B8, 0x0006, PCI_ANY_ID, PCI_ANY_ID,
176 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, SMSC_83C175 },
177 { 0,}
178 };
179 MODULE_DEVICE_TABLE (pci, epic_pci_tbl);
180
181
182 #ifndef USE_IO_OPS
183 #undef inb
184 #undef inw
185 #undef inl
186 #undef outb
187 #undef outw
188 #undef outl
189 #define inb readb
190 #define inw readw
191 #define inl readl
192 #define outb writeb
193 #define outw writew
194 #define outl writel
195 #endif
196
197 /* Offsets to registers, using the (ugh) SMC names. */
198 enum epic_registers {
199 COMMAND=0, INTSTAT=4, INTMASK=8, GENCTL=0x0C, NVCTL=0x10, EECTL=0x14,
200 PCIBurstCnt=0x18,
201 TEST1=0x1C, CRCCNT=0x20, ALICNT=0x24, MPCNT=0x28, /* Rx error counters. */
202 MIICtrl=0x30, MIIData=0x34, MIICfg=0x38,
203 LAN0=64, /* MAC address. */
204 MC0=80, /* Multicast filter table. */
205 RxCtrl=96, TxCtrl=112, TxSTAT=0x74,
206 PRxCDAR=0x84, RxSTAT=0xA4, EarlyRx=0xB0, PTxCDAR=0xC4, TxThresh=0xDC,
207 };
208
209 /* Interrupt register bits, using my own meaningful names. */
210 enum IntrStatus {
211 TxIdle=0x40000, RxIdle=0x20000, IntrSummary=0x010000,
212 PCIBusErr170=0x7000, PCIBusErr175=0x1000, PhyEvent175=0x8000,
213 RxStarted=0x0800, RxEarlyWarn=0x0400, CntFull=0x0200, TxUnderrun=0x0100,
214 TxEmpty=0x0080, TxDone=0x0020, RxError=0x0010,
215 RxOverflow=0x0008, RxFull=0x0004, RxHeader=0x0002, RxDone=0x0001,
216 };
217 enum CommandBits {
218 StopRx=1, StartRx=2, TxQueued=4, RxQueued=8,
219 StopTxDMA=0x20, StopRxDMA=0x40, RestartTx=0x80,
220 };
221
222 #define EpicRemoved 0xffffffff /* Chip failed or removed (CardBus) */
223
224 #define EpicNapiEvent (TxEmpty | TxDone | \
225 RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
226 #define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
227
228 static const u16 media2miictl[16] = {
229 0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
230 0, 0, 0, 0, 0, 0, 0, 0 };
231
232 /* The EPIC100 Rx and Tx buffer descriptors. */
233
234 struct epic_tx_desc {
235 u32 txstatus;
236 u32 bufaddr;
237 u32 buflength;
238 u32 next;
239 };
240
241 struct epic_rx_desc {
242 u32 rxstatus;
243 u32 bufaddr;
244 u32 buflength;
245 u32 next;
246 };
247
248 enum desc_status_bits {
249 DescOwn=0x8000,
250 };
251
252 #define PRIV_ALIGN 15 /* Required alignment mask */
253 struct epic_private {
254 struct epic_rx_desc *rx_ring;
255 struct epic_tx_desc *tx_ring;
256 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
257 struct sk_buff* tx_skbuff[TX_RING_SIZE];
258 /* The addresses of receive-in-place skbuffs. */
259 struct sk_buff* rx_skbuff[RX_RING_SIZE];
260
261 dma_addr_t tx_ring_dma;
262 dma_addr_t rx_ring_dma;
263
264 /* Ring pointers. */
265 spinlock_t lock; /* Group with Tx control cache line. */
266 spinlock_t napi_lock;
267 unsigned int reschedule_in_poll;
268 unsigned int cur_tx, dirty_tx;
269
270 unsigned int cur_rx, dirty_rx;
271 u32 irq_mask;
272 unsigned int rx_buf_sz; /* Based on MTU+slack. */
273
274 struct pci_dev *pci_dev; /* PCI bus location. */
275 int chip_id, chip_flags;
276
277 struct net_device_stats stats;
278 struct timer_list timer; /* Media selection timer. */
279 int tx_threshold;
280 unsigned char mc_filter[8];
281 signed char phys[4]; /* MII device addresses. */
282 u16 advertising; /* NWay media advertisement */
283 int mii_phy_cnt;
284 struct mii_if_info mii;
285 unsigned int tx_full:1; /* The Tx queue is full. */
286 unsigned int default_port:4; /* Last dev->if_port value. */
287 };
288
289 static int epic_open(struct net_device *dev);
290 static int read_eeprom(long ioaddr, int location);
291 static int mdio_read(struct net_device *dev, int phy_id, int location);
292 static void mdio_write(struct net_device *dev, int phy_id, int loc, int val);
293 static void epic_restart(struct net_device *dev);
294 static void epic_timer(unsigned long data);
295 static void epic_tx_timeout(struct net_device *dev);
296 static void epic_init_ring(struct net_device *dev);
297 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev);
298 static int epic_rx(struct net_device *dev, int budget);
299 static int epic_poll(struct net_device *dev, int *budget);
300 static irqreturn_t epic_interrupt(int irq, void *dev_instance);
301 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
302 static const struct ethtool_ops netdev_ethtool_ops;
303 static int epic_close(struct net_device *dev);
304 static struct net_device_stats *epic_get_stats(struct net_device *dev);
305 static void set_rx_mode(struct net_device *dev);
306
307
308
309 static int __devinit epic_init_one (struct pci_dev *pdev,
310 const struct pci_device_id *ent)
311 {
312 static int card_idx = -1;
313 long ioaddr;
314 int chip_idx = (int) ent->driver_data;
315 int irq;
316 struct net_device *dev;
317 struct epic_private *ep;
318 int i, ret, option = 0, duplex = 0;
319 void *ring_space;
320 dma_addr_t ring_dma;
321
322 /* when built into the kernel, we only print version if device is found */
323 #ifndef MODULE
324 static int printed_version;
325 if (!printed_version++)
326 printk (KERN_INFO "%s" KERN_INFO "%s" KERN_INFO "%s",
327 version, version2, version3);
328 #endif
329
330 card_idx++;
331
332 ret = pci_enable_device(pdev);
333 if (ret)
334 goto out;
335 irq = pdev->irq;
336
337 if (pci_resource_len(pdev, 0) < EPIC_TOTAL_SIZE) {
338 dev_err(&pdev->dev, "no PCI region space\n");
339 ret = -ENODEV;
340 goto err_out_disable;
341 }
342
343 pci_set_master(pdev);
344
345 ret = pci_request_regions(pdev, DRV_NAME);
346 if (ret < 0)
347 goto err_out_disable;
348
349 ret = -ENOMEM;
350
351 dev = alloc_etherdev(sizeof (*ep));
352 if (!dev) {
353 dev_err(&pdev->dev, "no memory for eth device\n");
354 goto err_out_free_res;
355 }
356 SET_MODULE_OWNER(dev);
357 SET_NETDEV_DEV(dev, &pdev->dev);
358
359 #ifdef USE_IO_OPS
360 ioaddr = pci_resource_start (pdev, 0);
361 #else
362 ioaddr = pci_resource_start (pdev, 1);
363 ioaddr = (long) ioremap (ioaddr, pci_resource_len (pdev, 1));
364 if (!ioaddr) {
365 dev_err(&pdev->dev, "ioremap failed\n");
366 goto err_out_free_netdev;
367 }
368 #endif
369
370 pci_set_drvdata(pdev, dev);
371 ep = dev->priv;
372 ep->mii.dev = dev;
373 ep->mii.mdio_read = mdio_read;
374 ep->mii.mdio_write = mdio_write;
375 ep->mii.phy_id_mask = 0x1f;
376 ep->mii.reg_num_mask = 0x1f;
377
378 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
379 if (!ring_space)
380 goto err_out_iounmap;
381 ep->tx_ring = (struct epic_tx_desc *)ring_space;
382 ep->tx_ring_dma = ring_dma;
383
384 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
385 if (!ring_space)
386 goto err_out_unmap_tx;
387 ep->rx_ring = (struct epic_rx_desc *)ring_space;
388 ep->rx_ring_dma = ring_dma;
389
390 if (dev->mem_start) {
391 option = dev->mem_start;
392 duplex = (dev->mem_start & 16) ? 1 : 0;
393 } else if (card_idx >= 0 && card_idx < MAX_UNITS) {
394 if (options[card_idx] >= 0)
395 option = options[card_idx];
396 if (full_duplex[card_idx] >= 0)
397 duplex = full_duplex[card_idx];
398 }
399
400 dev->base_addr = ioaddr;
401 dev->irq = irq;
402
403 spin_lock_init(&ep->lock);
404 spin_lock_init(&ep->napi_lock);
405 ep->reschedule_in_poll = 0;
406
407 /* Bring the chip out of low-power mode. */
408 outl(0x4200, ioaddr + GENCTL);
409 /* Magic?! If we don't set this bit the MII interface won't work. */
410 /* This magic is documented in SMSC app note 7.15 */
411 for (i = 16; i > 0; i--)
412 outl(0x0008, ioaddr + TEST1);
413
414 /* Turn on the MII transceiver. */
415 outl(0x12, ioaddr + MIICfg);
416 if (chip_idx == 1)
417 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
418 outl(0x0200, ioaddr + GENCTL);
419
420 /* Note: the '175 does not have a serial EEPROM. */
421 for (i = 0; i < 3; i++)
422 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(inw(ioaddr + LAN0 + i*4));
423
424 if (debug > 2) {
425 dev_printk(KERN_DEBUG, &pdev->dev, "EEPROM contents:\n");
426 for (i = 0; i < 64; i++)
427 printk(" %4.4x%s", read_eeprom(ioaddr, i),
428 i % 16 == 15 ? "\n" : "");
429 }
430
431 ep->pci_dev = pdev;
432 ep->chip_id = chip_idx;
433 ep->chip_flags = pci_id_tbl[chip_idx].drv_flags;
434 ep->irq_mask =
435 (ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
436 | CntFull | TxUnderrun | EpicNapiEvent;
437
438 /* Find the connected MII xcvrs.
439 Doing this in open() would allow detecting external xcvrs later, but
440 takes much time and no cards have external MII. */
441 {
442 int phy, phy_idx = 0;
443 for (phy = 1; phy < 32 && phy_idx < sizeof(ep->phys); phy++) {
444 int mii_status = mdio_read(dev, phy, MII_BMSR);
445 if (mii_status != 0xffff && mii_status != 0x0000) {
446 ep->phys[phy_idx++] = phy;
447 dev_info(&pdev->dev,
448 "MII transceiver #%d control "
449 "%4.4x status %4.4x.\n",
450 phy, mdio_read(dev, phy, 0), mii_status);
451 }
452 }
453 ep->mii_phy_cnt = phy_idx;
454 if (phy_idx != 0) {
455 phy = ep->phys[0];
456 ep->mii.advertising = mdio_read(dev, phy, MII_ADVERTISE);
457 dev_info(&pdev->dev,
458 "Autonegotiation advertising %4.4x link "
459 "partner %4.4x.\n",
460 ep->mii.advertising, mdio_read(dev, phy, 5));
461 } else if ( ! (ep->chip_flags & NO_MII)) {
462 dev_warn(&pdev->dev,
463 "***WARNING***: No MII transceiver found!\n");
464 /* Use the known PHY address of the EPII. */
465 ep->phys[0] = 3;
466 }
467 ep->mii.phy_id = ep->phys[0];
468 }
469
470 /* Turn off the MII xcvr (175 only!), leave the chip in low-power mode. */
471 if (ep->chip_flags & MII_PWRDWN)
472 outl(inl(ioaddr + NVCTL) & ~0x483C, ioaddr + NVCTL);
473 outl(0x0008, ioaddr + GENCTL);
474
475 /* The lower four bits are the media type. */
476 if (duplex) {
477 ep->mii.force_media = ep->mii.full_duplex = 1;
478 dev_info(&pdev->dev, "Forced full duplex requested.\n");
479 }
480 dev->if_port = ep->default_port = option;
481
482 /* The Epic-specific entries in the device structure. */
483 dev->open = &epic_open;
484 dev->hard_start_xmit = &epic_start_xmit;
485 dev->stop = &epic_close;
486 dev->get_stats = &epic_get_stats;
487 dev->set_multicast_list = &set_rx_mode;
488 dev->do_ioctl = &netdev_ioctl;
489 dev->ethtool_ops = &netdev_ethtool_ops;
490 dev->watchdog_timeo = TX_TIMEOUT;
491 dev->tx_timeout = &epic_tx_timeout;
492 dev->poll = epic_poll;
493 dev->weight = 64;
494
495 ret = register_netdev(dev);
496 if (ret < 0)
497 goto err_out_unmap_rx;
498
499 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, ",
500 dev->name, pci_id_tbl[chip_idx].name, ioaddr, dev->irq);
501 for (i = 0; i < 5; i++)
502 printk("%2.2x:", dev->dev_addr[i]);
503 printk("%2.2x.\n", dev->dev_addr[i]);
504
505 out:
506 return ret;
507
508 err_out_unmap_rx:
509 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
510 err_out_unmap_tx:
511 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
512 err_out_iounmap:
513 #ifndef USE_IO_OPS
514 iounmap(ioaddr);
515 err_out_free_netdev:
516 #endif
517 free_netdev(dev);
518 err_out_free_res:
519 pci_release_regions(pdev);
520 err_out_disable:
521 pci_disable_device(pdev);
522 goto out;
523 }
524
525 /* Serial EEPROM section. */
526
527 /* EEPROM_Ctrl bits. */
528 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
529 #define EE_CS 0x02 /* EEPROM chip select. */
530 #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
531 #define EE_WRITE_0 0x01
532 #define EE_WRITE_1 0x09
533 #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
534 #define EE_ENB (0x0001 | EE_CS)
535
536 /* Delay between EEPROM clock transitions.
537 This serves to flush the operation to the PCI bus.
538 */
539
540 #define eeprom_delay() inl(ee_addr)
541
542 /* The EEPROM commands include the alway-set leading bit. */
543 #define EE_WRITE_CMD (5 << 6)
544 #define EE_READ64_CMD (6 << 6)
545 #define EE_READ256_CMD (6 << 8)
546 #define EE_ERASE_CMD (7 << 6)
547
548 static void epic_disable_int(struct net_device *dev, struct epic_private *ep)
549 {
550 long ioaddr = dev->base_addr;
551
552 outl(0x00000000, ioaddr + INTMASK);
553 }
554
555 static inline void __epic_pci_commit(long ioaddr)
556 {
557 #ifndef USE_IO_OPS
558 inl(ioaddr + INTMASK);
559 #endif
560 }
561
562 static inline void epic_napi_irq_off(struct net_device *dev,
563 struct epic_private *ep)
564 {
565 long ioaddr = dev->base_addr;
566
567 outl(ep->irq_mask & ~EpicNapiEvent, ioaddr + INTMASK);
568 __epic_pci_commit(ioaddr);
569 }
570
571 static inline void epic_napi_irq_on(struct net_device *dev,
572 struct epic_private *ep)
573 {
574 long ioaddr = dev->base_addr;
575
576 /* No need to commit possible posted write */
577 outl(ep->irq_mask | EpicNapiEvent, ioaddr + INTMASK);
578 }
579
580 static int __devinit read_eeprom(long ioaddr, int location)
581 {
582 int i;
583 int retval = 0;
584 long ee_addr = ioaddr + EECTL;
585 int read_cmd = location |
586 (inl(ee_addr) & 0x40 ? EE_READ64_CMD : EE_READ256_CMD);
587
588 outl(EE_ENB & ~EE_CS, ee_addr);
589 outl(EE_ENB, ee_addr);
590
591 /* Shift the read command bits out. */
592 for (i = 12; i >= 0; i--) {
593 short dataval = (read_cmd & (1 << i)) ? EE_WRITE_1 : EE_WRITE_0;
594 outl(EE_ENB | dataval, ee_addr);
595 eeprom_delay();
596 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
597 eeprom_delay();
598 }
599 outl(EE_ENB, ee_addr);
600
601 for (i = 16; i > 0; i--) {
602 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
603 eeprom_delay();
604 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
605 outl(EE_ENB, ee_addr);
606 eeprom_delay();
607 }
608
609 /* Terminate the EEPROM access. */
610 outl(EE_ENB & ~EE_CS, ee_addr);
611 return retval;
612 }
613
614 #define MII_READOP 1
615 #define MII_WRITEOP 2
616 static int mdio_read(struct net_device *dev, int phy_id, int location)
617 {
618 long ioaddr = dev->base_addr;
619 int read_cmd = (phy_id << 9) | (location << 4) | MII_READOP;
620 int i;
621
622 outl(read_cmd, ioaddr + MIICtrl);
623 /* Typical operation takes 25 loops. */
624 for (i = 400; i > 0; i--) {
625 barrier();
626 if ((inl(ioaddr + MIICtrl) & MII_READOP) == 0) {
627 /* Work around read failure bug. */
628 if (phy_id == 1 && location < 6
629 && inw(ioaddr + MIIData) == 0xffff) {
630 outl(read_cmd, ioaddr + MIICtrl);
631 continue;
632 }
633 return inw(ioaddr + MIIData);
634 }
635 }
636 return 0xffff;
637 }
638
639 static void mdio_write(struct net_device *dev, int phy_id, int loc, int value)
640 {
641 long ioaddr = dev->base_addr;
642 int i;
643
644 outw(value, ioaddr + MIIData);
645 outl((phy_id << 9) | (loc << 4) | MII_WRITEOP, ioaddr + MIICtrl);
646 for (i = 10000; i > 0; i--) {
647 barrier();
648 if ((inl(ioaddr + MIICtrl) & MII_WRITEOP) == 0)
649 break;
650 }
651 return;
652 }
653
654
655 static int epic_open(struct net_device *dev)
656 {
657 struct epic_private *ep = dev->priv;
658 long ioaddr = dev->base_addr;
659 int i;
660 int retval;
661
662 /* Soft reset the chip. */
663 outl(0x4001, ioaddr + GENCTL);
664
665 if ((retval = request_irq(dev->irq, &epic_interrupt, IRQF_SHARED, dev->name, dev)))
666 return retval;
667
668 epic_init_ring(dev);
669
670 outl(0x4000, ioaddr + GENCTL);
671 /* This magic is documented in SMSC app note 7.15 */
672 for (i = 16; i > 0; i--)
673 outl(0x0008, ioaddr + TEST1);
674
675 /* Pull the chip out of low-power mode, enable interrupts, and set for
676 PCI read multiple. The MIIcfg setting and strange write order are
677 required by the details of which bits are reset and the transceiver
678 wiring on the Ositech CardBus card.
679 */
680 #if 0
681 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
682 #endif
683 if (ep->chip_flags & MII_PWRDWN)
684 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
685
686 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
687 outl(0x4432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
688 inl(ioaddr + GENCTL);
689 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
690 #else
691 outl(0x4412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
692 inl(ioaddr + GENCTL);
693 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
694 #endif
695
696 udelay(20); /* Looks like EPII needs that if you want reliable RX init. FIXME: pci posting bug? */
697
698 for (i = 0; i < 3; i++)
699 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
700
701 ep->tx_threshold = TX_FIFO_THRESH;
702 outl(ep->tx_threshold, ioaddr + TxThresh);
703
704 if (media2miictl[dev->if_port & 15]) {
705 if (ep->mii_phy_cnt)
706 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
707 if (dev->if_port == 1) {
708 if (debug > 1)
709 printk(KERN_INFO "%s: Using the 10base2 transceiver, MII "
710 "status %4.4x.\n",
711 dev->name, mdio_read(dev, ep->phys[0], MII_BMSR));
712 }
713 } else {
714 int mii_lpa = mdio_read(dev, ep->phys[0], MII_LPA);
715 if (mii_lpa != 0xffff) {
716 if ((mii_lpa & LPA_100FULL) || (mii_lpa & 0x01C0) == LPA_10FULL)
717 ep->mii.full_duplex = 1;
718 else if (! (mii_lpa & LPA_LPACK))
719 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
720 if (debug > 1)
721 printk(KERN_INFO "%s: Setting %s-duplex based on MII xcvr %d"
722 " register read of %4.4x.\n", dev->name,
723 ep->mii.full_duplex ? "full" : "half",
724 ep->phys[0], mii_lpa);
725 }
726 }
727
728 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
729 outl(ep->rx_ring_dma, ioaddr + PRxCDAR);
730 outl(ep->tx_ring_dma, ioaddr + PTxCDAR);
731
732 /* Start the chip's Rx process. */
733 set_rx_mode(dev);
734 outl(StartRx | RxQueued, ioaddr + COMMAND);
735
736 netif_start_queue(dev);
737
738 /* Enable interrupts by setting the interrupt mask. */
739 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
740 | CntFull | TxUnderrun
741 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
742
743 if (debug > 1)
744 printk(KERN_DEBUG "%s: epic_open() ioaddr %lx IRQ %d status %4.4x "
745 "%s-duplex.\n",
746 dev->name, ioaddr, dev->irq, (int)inl(ioaddr + GENCTL),
747 ep->mii.full_duplex ? "full" : "half");
748
749 /* Set the timer to switch to check for link beat and perhaps switch
750 to an alternate media type. */
751 init_timer(&ep->timer);
752 ep->timer.expires = jiffies + 3*HZ;
753 ep->timer.data = (unsigned long)dev;
754 ep->timer.function = &epic_timer; /* timer handler */
755 add_timer(&ep->timer);
756
757 return 0;
758 }
759
760 /* Reset the chip to recover from a PCI transaction error.
761 This may occur at interrupt time. */
762 static void epic_pause(struct net_device *dev)
763 {
764 long ioaddr = dev->base_addr;
765 struct epic_private *ep = dev->priv;
766
767 netif_stop_queue (dev);
768
769 /* Disable interrupts by clearing the interrupt mask. */
770 outl(0x00000000, ioaddr + INTMASK);
771 /* Stop the chip's Tx and Rx DMA processes. */
772 outw(StopRx | StopTxDMA | StopRxDMA, ioaddr + COMMAND);
773
774 /* Update the error counts. */
775 if (inw(ioaddr + COMMAND) != 0xffff) {
776 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
777 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
778 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
779 }
780
781 /* Remove the packets on the Rx queue. */
782 epic_rx(dev, RX_RING_SIZE);
783 }
784
785 static void epic_restart(struct net_device *dev)
786 {
787 long ioaddr = dev->base_addr;
788 struct epic_private *ep = dev->priv;
789 int i;
790
791 /* Soft reset the chip. */
792 outl(0x4001, ioaddr + GENCTL);
793
794 printk(KERN_DEBUG "%s: Restarting the EPIC chip, Rx %d/%d Tx %d/%d.\n",
795 dev->name, ep->cur_rx, ep->dirty_rx, ep->dirty_tx, ep->cur_tx);
796 udelay(1);
797
798 /* This magic is documented in SMSC app note 7.15 */
799 for (i = 16; i > 0; i--)
800 outl(0x0008, ioaddr + TEST1);
801
802 #if defined(__powerpc__) || defined(__sparc__) /* Big endian */
803 outl(0x0432 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
804 #else
805 outl(0x0412 | (RX_FIFO_THRESH<<8), ioaddr + GENCTL);
806 #endif
807 outl(dev->if_port == 1 ? 0x13 : 0x12, ioaddr + MIICfg);
808 if (ep->chip_flags & MII_PWRDWN)
809 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
810
811 for (i = 0; i < 3; i++)
812 outl(cpu_to_le16(((u16*)dev->dev_addr)[i]), ioaddr + LAN0 + i*4);
813
814 ep->tx_threshold = TX_FIFO_THRESH;
815 outl(ep->tx_threshold, ioaddr + TxThresh);
816 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
817 outl(ep->rx_ring_dma + (ep->cur_rx%RX_RING_SIZE)*
818 sizeof(struct epic_rx_desc), ioaddr + PRxCDAR);
819 outl(ep->tx_ring_dma + (ep->dirty_tx%TX_RING_SIZE)*
820 sizeof(struct epic_tx_desc), ioaddr + PTxCDAR);
821
822 /* Start the chip's Rx process. */
823 set_rx_mode(dev);
824 outl(StartRx | RxQueued, ioaddr + COMMAND);
825
826 /* Enable interrupts by setting the interrupt mask. */
827 outl((ep->chip_flags & TYPE2_INTR ? PCIBusErr175 : PCIBusErr170)
828 | CntFull | TxUnderrun
829 | RxError | RxHeader | EpicNapiEvent, ioaddr + INTMASK);
830
831 printk(KERN_DEBUG "%s: epic_restart() done, cmd status %4.4x, ctl %4.4x"
832 " interrupt %4.4x.\n",
833 dev->name, (int)inl(ioaddr + COMMAND), (int)inl(ioaddr + GENCTL),
834 (int)inl(ioaddr + INTSTAT));
835 return;
836 }
837
838 static void check_media(struct net_device *dev)
839 {
840 struct epic_private *ep = dev->priv;
841 long ioaddr = dev->base_addr;
842 int mii_lpa = ep->mii_phy_cnt ? mdio_read(dev, ep->phys[0], MII_LPA) : 0;
843 int negotiated = mii_lpa & ep->mii.advertising;
844 int duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
845
846 if (ep->mii.force_media)
847 return;
848 if (mii_lpa == 0xffff) /* Bogus read */
849 return;
850 if (ep->mii.full_duplex != duplex) {
851 ep->mii.full_duplex = duplex;
852 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d link"
853 " partner capability of %4.4x.\n", dev->name,
854 ep->mii.full_duplex ? "full" : "half", ep->phys[0], mii_lpa);
855 outl(ep->mii.full_duplex ? 0x7F : 0x79, ioaddr + TxCtrl);
856 }
857 }
858
859 static void epic_timer(unsigned long data)
860 {
861 struct net_device *dev = (struct net_device *)data;
862 struct epic_private *ep = dev->priv;
863 long ioaddr = dev->base_addr;
864 int next_tick = 5*HZ;
865
866 if (debug > 3) {
867 printk(KERN_DEBUG "%s: Media monitor tick, Tx status %8.8x.\n",
868 dev->name, (int)inl(ioaddr + TxSTAT));
869 printk(KERN_DEBUG "%s: Other registers are IntMask %4.4x "
870 "IntStatus %4.4x RxStatus %4.4x.\n",
871 dev->name, (int)inl(ioaddr + INTMASK),
872 (int)inl(ioaddr + INTSTAT), (int)inl(ioaddr + RxSTAT));
873 }
874
875 check_media(dev);
876
877 ep->timer.expires = jiffies + next_tick;
878 add_timer(&ep->timer);
879 }
880
881 static void epic_tx_timeout(struct net_device *dev)
882 {
883 struct epic_private *ep = dev->priv;
884 long ioaddr = dev->base_addr;
885
886 if (debug > 0) {
887 printk(KERN_WARNING "%s: Transmit timeout using MII device, "
888 "Tx status %4.4x.\n",
889 dev->name, (int)inw(ioaddr + TxSTAT));
890 if (debug > 1) {
891 printk(KERN_DEBUG "%s: Tx indices: dirty_tx %d, cur_tx %d.\n",
892 dev->name, ep->dirty_tx, ep->cur_tx);
893 }
894 }
895 if (inw(ioaddr + TxSTAT) & 0x10) { /* Tx FIFO underflow. */
896 ep->stats.tx_fifo_errors++;
897 outl(RestartTx, ioaddr + COMMAND);
898 } else {
899 epic_restart(dev);
900 outl(TxQueued, dev->base_addr + COMMAND);
901 }
902
903 dev->trans_start = jiffies;
904 ep->stats.tx_errors++;
905 if (!ep->tx_full)
906 netif_wake_queue(dev);
907 }
908
909 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
910 static void epic_init_ring(struct net_device *dev)
911 {
912 struct epic_private *ep = dev->priv;
913 int i;
914
915 ep->tx_full = 0;
916 ep->dirty_tx = ep->cur_tx = 0;
917 ep->cur_rx = ep->dirty_rx = 0;
918 ep->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
919
920 /* Initialize all Rx descriptors. */
921 for (i = 0; i < RX_RING_SIZE; i++) {
922 ep->rx_ring[i].rxstatus = 0;
923 ep->rx_ring[i].buflength = cpu_to_le32(ep->rx_buf_sz);
924 ep->rx_ring[i].next = ep->rx_ring_dma +
925 (i+1)*sizeof(struct epic_rx_desc);
926 ep->rx_skbuff[i] = NULL;
927 }
928 /* Mark the last entry as wrapping the ring. */
929 ep->rx_ring[i-1].next = ep->rx_ring_dma;
930
931 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
932 for (i = 0; i < RX_RING_SIZE; i++) {
933 struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
934 ep->rx_skbuff[i] = skb;
935 if (skb == NULL)
936 break;
937 skb->dev = dev; /* Mark as being used by this device. */
938 skb_reserve(skb, 2); /* 16 byte align the IP header. */
939 ep->rx_ring[i].bufaddr = pci_map_single(ep->pci_dev,
940 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
941 ep->rx_ring[i].rxstatus = cpu_to_le32(DescOwn);
942 }
943 ep->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
944
945 /* The Tx buffer descriptor is filled in as needed, but we
946 do need to clear the ownership bit. */
947 for (i = 0; i < TX_RING_SIZE; i++) {
948 ep->tx_skbuff[i] = NULL;
949 ep->tx_ring[i].txstatus = 0x0000;
950 ep->tx_ring[i].next = ep->tx_ring_dma +
951 (i+1)*sizeof(struct epic_tx_desc);
952 }
953 ep->tx_ring[i-1].next = ep->tx_ring_dma;
954 return;
955 }
956
957 static int epic_start_xmit(struct sk_buff *skb, struct net_device *dev)
958 {
959 struct epic_private *ep = dev->priv;
960 int entry, free_count;
961 u32 ctrl_word;
962 unsigned long flags;
963
964 if (skb_padto(skb, ETH_ZLEN))
965 return 0;
966
967 /* Caution: the write order is important here, set the field with the
968 "ownership" bit last. */
969
970 /* Calculate the next Tx descriptor entry. */
971 spin_lock_irqsave(&ep->lock, flags);
972 free_count = ep->cur_tx - ep->dirty_tx;
973 entry = ep->cur_tx % TX_RING_SIZE;
974
975 ep->tx_skbuff[entry] = skb;
976 ep->tx_ring[entry].bufaddr = pci_map_single(ep->pci_dev, skb->data,
977 skb->len, PCI_DMA_TODEVICE);
978 if (free_count < TX_QUEUE_LEN/2) {/* Typical path */
979 ctrl_word = cpu_to_le32(0x100000); /* No interrupt */
980 } else if (free_count == TX_QUEUE_LEN/2) {
981 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
982 } else if (free_count < TX_QUEUE_LEN - 1) {
983 ctrl_word = cpu_to_le32(0x100000); /* No Tx-done intr. */
984 } else {
985 /* Leave room for an additional entry. */
986 ctrl_word = cpu_to_le32(0x140000); /* Tx-done intr. */
987 ep->tx_full = 1;
988 }
989 ep->tx_ring[entry].buflength = ctrl_word | cpu_to_le32(skb->len);
990 ep->tx_ring[entry].txstatus =
991 ((skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN) << 16)
992 | cpu_to_le32(DescOwn);
993
994 ep->cur_tx++;
995 if (ep->tx_full)
996 netif_stop_queue(dev);
997
998 spin_unlock_irqrestore(&ep->lock, flags);
999 /* Trigger an immediate transmit demand. */
1000 outl(TxQueued, dev->base_addr + COMMAND);
1001
1002 dev->trans_start = jiffies;
1003 if (debug > 4)
1004 printk(KERN_DEBUG "%s: Queued Tx packet size %d to slot %d, "
1005 "flag %2.2x Tx status %8.8x.\n",
1006 dev->name, (int)skb->len, entry, ctrl_word,
1007 (int)inl(dev->base_addr + TxSTAT));
1008
1009 return 0;
1010 }
1011
1012 static void epic_tx_error(struct net_device *dev, struct epic_private *ep,
1013 int status)
1014 {
1015 struct net_device_stats *stats = &ep->stats;
1016
1017 #ifndef final_version
1018 /* There was an major error, log it. */
1019 if (debug > 1)
1020 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1021 dev->name, status);
1022 #endif
1023 stats->tx_errors++;
1024 if (status & 0x1050)
1025 stats->tx_aborted_errors++;
1026 if (status & 0x0008)
1027 stats->tx_carrier_errors++;
1028 if (status & 0x0040)
1029 stats->tx_window_errors++;
1030 if (status & 0x0010)
1031 stats->tx_fifo_errors++;
1032 }
1033
1034 static void epic_tx(struct net_device *dev, struct epic_private *ep)
1035 {
1036 unsigned int dirty_tx, cur_tx;
1037
1038 /*
1039 * Note: if this lock becomes a problem we can narrow the locked
1040 * region at the cost of occasionally grabbing the lock more times.
1041 */
1042 cur_tx = ep->cur_tx;
1043 for (dirty_tx = ep->dirty_tx; cur_tx - dirty_tx > 0; dirty_tx++) {
1044 struct sk_buff *skb;
1045 int entry = dirty_tx % TX_RING_SIZE;
1046 int txstatus = le32_to_cpu(ep->tx_ring[entry].txstatus);
1047
1048 if (txstatus & DescOwn)
1049 break; /* It still hasn't been Txed */
1050
1051 if (likely(txstatus & 0x0001)) {
1052 ep->stats.collisions += (txstatus >> 8) & 15;
1053 ep->stats.tx_packets++;
1054 ep->stats.tx_bytes += ep->tx_skbuff[entry]->len;
1055 } else
1056 epic_tx_error(dev, ep, txstatus);
1057
1058 /* Free the original skb. */
1059 skb = ep->tx_skbuff[entry];
1060 pci_unmap_single(ep->pci_dev, ep->tx_ring[entry].bufaddr,
1061 skb->len, PCI_DMA_TODEVICE);
1062 dev_kfree_skb_irq(skb);
1063 ep->tx_skbuff[entry] = NULL;
1064 }
1065
1066 #ifndef final_version
1067 if (cur_tx - dirty_tx > TX_RING_SIZE) {
1068 printk(KERN_WARNING
1069 "%s: Out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1070 dev->name, dirty_tx, cur_tx, ep->tx_full);
1071 dirty_tx += TX_RING_SIZE;
1072 }
1073 #endif
1074 ep->dirty_tx = dirty_tx;
1075 if (ep->tx_full && cur_tx - dirty_tx < TX_QUEUE_LEN - 4) {
1076 /* The ring is no longer full, allow new TX entries. */
1077 ep->tx_full = 0;
1078 netif_wake_queue(dev);
1079 }
1080 }
1081
1082 /* The interrupt handler does all of the Rx thread work and cleans up
1083 after the Tx thread. */
1084 static irqreturn_t epic_interrupt(int irq, void *dev_instance)
1085 {
1086 struct net_device *dev = dev_instance;
1087 struct epic_private *ep = dev->priv;
1088 long ioaddr = dev->base_addr;
1089 unsigned int handled = 0;
1090 int status;
1091
1092 status = inl(ioaddr + INTSTAT);
1093 /* Acknowledge all of the current interrupt sources ASAP. */
1094 outl(status & EpicNormalEvent, ioaddr + INTSTAT);
1095
1096 if (debug > 4) {
1097 printk(KERN_DEBUG "%s: Interrupt, status=%#8.8x new "
1098 "intstat=%#8.8x.\n", dev->name, status,
1099 (int)inl(ioaddr + INTSTAT));
1100 }
1101
1102 if ((status & IntrSummary) == 0)
1103 goto out;
1104
1105 handled = 1;
1106
1107 if ((status & EpicNapiEvent) && !ep->reschedule_in_poll) {
1108 spin_lock(&ep->napi_lock);
1109 if (netif_rx_schedule_prep(dev)) {
1110 epic_napi_irq_off(dev, ep);
1111 __netif_rx_schedule(dev);
1112 } else
1113 ep->reschedule_in_poll++;
1114 spin_unlock(&ep->napi_lock);
1115 }
1116 status &= ~EpicNapiEvent;
1117
1118 /* Check uncommon events all at once. */
1119 if (status & (CntFull | TxUnderrun | PCIBusErr170 | PCIBusErr175)) {
1120 if (status == EpicRemoved)
1121 goto out;
1122
1123 /* Always update the error counts to avoid overhead later. */
1124 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1125 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1126 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1127
1128 if (status & TxUnderrun) { /* Tx FIFO underflow. */
1129 ep->stats.tx_fifo_errors++;
1130 outl(ep->tx_threshold += 128, ioaddr + TxThresh);
1131 /* Restart the transmit process. */
1132 outl(RestartTx, ioaddr + COMMAND);
1133 }
1134 if (status & PCIBusErr170) {
1135 printk(KERN_ERR "%s: PCI Bus Error! status %4.4x.\n",
1136 dev->name, status);
1137 epic_pause(dev);
1138 epic_restart(dev);
1139 }
1140 /* Clear all error sources. */
1141 outl(status & 0x7f18, ioaddr + INTSTAT);
1142 }
1143
1144 out:
1145 if (debug > 3) {
1146 printk(KERN_DEBUG "%s: exit interrupt, intr_status=%#4.4x.\n",
1147 dev->name, status);
1148 }
1149
1150 return IRQ_RETVAL(handled);
1151 }
1152
1153 static int epic_rx(struct net_device *dev, int budget)
1154 {
1155 struct epic_private *ep = dev->priv;
1156 int entry = ep->cur_rx % RX_RING_SIZE;
1157 int rx_work_limit = ep->dirty_rx + RX_RING_SIZE - ep->cur_rx;
1158 int work_done = 0;
1159
1160 if (debug > 4)
1161 printk(KERN_DEBUG " In epic_rx(), entry %d %8.8x.\n", entry,
1162 ep->rx_ring[entry].rxstatus);
1163
1164 if (rx_work_limit > budget)
1165 rx_work_limit = budget;
1166
1167 /* If we own the next entry, it's a new packet. Send it up. */
1168 while ((ep->rx_ring[entry].rxstatus & cpu_to_le32(DescOwn)) == 0) {
1169 int status = le32_to_cpu(ep->rx_ring[entry].rxstatus);
1170
1171 if (debug > 4)
1172 printk(KERN_DEBUG " epic_rx() status was %8.8x.\n", status);
1173 if (--rx_work_limit < 0)
1174 break;
1175 if (status & 0x2006) {
1176 if (debug > 2)
1177 printk(KERN_DEBUG "%s: epic_rx() error status was %8.8x.\n",
1178 dev->name, status);
1179 if (status & 0x2000) {
1180 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1181 "multiple buffers, status %4.4x!\n", dev->name, status);
1182 ep->stats.rx_length_errors++;
1183 } else if (status & 0x0006)
1184 /* Rx Frame errors are counted in hardware. */
1185 ep->stats.rx_errors++;
1186 } else {
1187 /* Malloc up new buffer, compatible with net-2e. */
1188 /* Omit the four octet CRC from the length. */
1189 short pkt_len = (status >> 16) - 4;
1190 struct sk_buff *skb;
1191
1192 if (pkt_len > PKT_BUF_SZ - 4) {
1193 printk(KERN_ERR "%s: Oversized Ethernet frame, status %x "
1194 "%d bytes.\n",
1195 dev->name, status, pkt_len);
1196 pkt_len = 1514;
1197 }
1198 /* Check if the packet is long enough to accept without copying
1199 to a minimally-sized skbuff. */
1200 if (pkt_len < rx_copybreak
1201 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1202 skb->dev = dev;
1203 skb_reserve(skb, 2); /* 16 byte align the IP header */
1204 pci_dma_sync_single_for_cpu(ep->pci_dev,
1205 ep->rx_ring[entry].bufaddr,
1206 ep->rx_buf_sz,
1207 PCI_DMA_FROMDEVICE);
1208 eth_copy_and_sum(skb, ep->rx_skbuff[entry]->data, pkt_len, 0);
1209 skb_put(skb, pkt_len);
1210 pci_dma_sync_single_for_device(ep->pci_dev,
1211 ep->rx_ring[entry].bufaddr,
1212 ep->rx_buf_sz,
1213 PCI_DMA_FROMDEVICE);
1214 } else {
1215 pci_unmap_single(ep->pci_dev,
1216 ep->rx_ring[entry].bufaddr,
1217 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1218 skb_put(skb = ep->rx_skbuff[entry], pkt_len);
1219 ep->rx_skbuff[entry] = NULL;
1220 }
1221 skb->protocol = eth_type_trans(skb, dev);
1222 netif_receive_skb(skb);
1223 dev->last_rx = jiffies;
1224 ep->stats.rx_packets++;
1225 ep->stats.rx_bytes += pkt_len;
1226 }
1227 work_done++;
1228 entry = (++ep->cur_rx) % RX_RING_SIZE;
1229 }
1230
1231 /* Refill the Rx ring buffers. */
1232 for (; ep->cur_rx - ep->dirty_rx > 0; ep->dirty_rx++) {
1233 entry = ep->dirty_rx % RX_RING_SIZE;
1234 if (ep->rx_skbuff[entry] == NULL) {
1235 struct sk_buff *skb;
1236 skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
1237 if (skb == NULL)
1238 break;
1239 skb->dev = dev; /* Mark as being used by this device. */
1240 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1241 ep->rx_ring[entry].bufaddr = pci_map_single(ep->pci_dev,
1242 skb->data, ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1243 work_done++;
1244 }
1245 ep->rx_ring[entry].rxstatus = cpu_to_le32(DescOwn);
1246 }
1247 return work_done;
1248 }
1249
1250 static void epic_rx_err(struct net_device *dev, struct epic_private *ep)
1251 {
1252 long ioaddr = dev->base_addr;
1253 int status;
1254
1255 status = inl(ioaddr + INTSTAT);
1256
1257 if (status == EpicRemoved)
1258 return;
1259 if (status & RxOverflow) /* Missed a Rx frame. */
1260 ep->stats.rx_errors++;
1261 if (status & (RxOverflow | RxFull))
1262 outw(RxQueued, ioaddr + COMMAND);
1263 }
1264
1265 static int epic_poll(struct net_device *dev, int *budget)
1266 {
1267 struct epic_private *ep = dev->priv;
1268 int work_done = 0, orig_budget;
1269 long ioaddr = dev->base_addr;
1270
1271 orig_budget = (*budget > dev->quota) ? dev->quota : *budget;
1272
1273 rx_action:
1274
1275 epic_tx(dev, ep);
1276
1277 work_done += epic_rx(dev, *budget);
1278
1279 epic_rx_err(dev, ep);
1280
1281 *budget -= work_done;
1282 dev->quota -= work_done;
1283
1284 if (netif_running(dev) && (work_done < orig_budget)) {
1285 unsigned long flags;
1286 int more;
1287
1288 /* A bit baroque but it avoids a (space hungry) spin_unlock */
1289
1290 spin_lock_irqsave(&ep->napi_lock, flags);
1291
1292 more = ep->reschedule_in_poll;
1293 if (!more) {
1294 __netif_rx_complete(dev);
1295 outl(EpicNapiEvent, ioaddr + INTSTAT);
1296 epic_napi_irq_on(dev, ep);
1297 } else
1298 ep->reschedule_in_poll--;
1299
1300 spin_unlock_irqrestore(&ep->napi_lock, flags);
1301
1302 if (more)
1303 goto rx_action;
1304 }
1305
1306 return (work_done >= orig_budget);
1307 }
1308
1309 static int epic_close(struct net_device *dev)
1310 {
1311 long ioaddr = dev->base_addr;
1312 struct epic_private *ep = dev->priv;
1313 struct sk_buff *skb;
1314 int i;
1315
1316 netif_stop_queue(dev);
1317
1318 if (debug > 1)
1319 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1320 dev->name, (int)inl(ioaddr + INTSTAT));
1321
1322 del_timer_sync(&ep->timer);
1323
1324 epic_disable_int(dev, ep);
1325
1326 free_irq(dev->irq, dev);
1327
1328 epic_pause(dev);
1329
1330 /* Free all the skbuffs in the Rx queue. */
1331 for (i = 0; i < RX_RING_SIZE; i++) {
1332 skb = ep->rx_skbuff[i];
1333 ep->rx_skbuff[i] = NULL;
1334 ep->rx_ring[i].rxstatus = 0; /* Not owned by Epic chip. */
1335 ep->rx_ring[i].buflength = 0;
1336 if (skb) {
1337 pci_unmap_single(ep->pci_dev, ep->rx_ring[i].bufaddr,
1338 ep->rx_buf_sz, PCI_DMA_FROMDEVICE);
1339 dev_kfree_skb(skb);
1340 }
1341 ep->rx_ring[i].bufaddr = 0xBADF00D0; /* An invalid address. */
1342 }
1343 for (i = 0; i < TX_RING_SIZE; i++) {
1344 skb = ep->tx_skbuff[i];
1345 ep->tx_skbuff[i] = NULL;
1346 if (!skb)
1347 continue;
1348 pci_unmap_single(ep->pci_dev, ep->tx_ring[i].bufaddr,
1349 skb->len, PCI_DMA_TODEVICE);
1350 dev_kfree_skb(skb);
1351 }
1352
1353 /* Green! Leave the chip in low-power mode. */
1354 outl(0x0008, ioaddr + GENCTL);
1355
1356 return 0;
1357 }
1358
1359 static struct net_device_stats *epic_get_stats(struct net_device *dev)
1360 {
1361 struct epic_private *ep = dev->priv;
1362 long ioaddr = dev->base_addr;
1363
1364 if (netif_running(dev)) {
1365 /* Update the error counts. */
1366 ep->stats.rx_missed_errors += inb(ioaddr + MPCNT);
1367 ep->stats.rx_frame_errors += inb(ioaddr + ALICNT);
1368 ep->stats.rx_crc_errors += inb(ioaddr + CRCCNT);
1369 }
1370
1371 return &ep->stats;
1372 }
1373
1374 /* Set or clear the multicast filter for this adaptor.
1375 Note that we only use exclusion around actually queueing the
1376 new frame, not around filling ep->setup_frame. This is non-deterministic
1377 when re-entered but still correct. */
1378
1379 static void set_rx_mode(struct net_device *dev)
1380 {
1381 long ioaddr = dev->base_addr;
1382 struct epic_private *ep = dev->priv;
1383 unsigned char mc_filter[8]; /* Multicast hash filter */
1384 int i;
1385
1386 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1387 outl(0x002C, ioaddr + RxCtrl);
1388 /* Unconditionally log net taps. */
1389 memset(mc_filter, 0xff, sizeof(mc_filter));
1390 } else if ((dev->mc_count > 0) || (dev->flags & IFF_ALLMULTI)) {
1391 /* There is apparently a chip bug, so the multicast filter
1392 is never enabled. */
1393 /* Too many to filter perfectly -- accept all multicasts. */
1394 memset(mc_filter, 0xff, sizeof(mc_filter));
1395 outl(0x000C, ioaddr + RxCtrl);
1396 } else if (dev->mc_count == 0) {
1397 outl(0x0004, ioaddr + RxCtrl);
1398 return;
1399 } else { /* Never executed, for now. */
1400 struct dev_mc_list *mclist;
1401
1402 memset(mc_filter, 0, sizeof(mc_filter));
1403 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1404 i++, mclist = mclist->next) {
1405 unsigned int bit_nr =
1406 ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x3f;
1407 mc_filter[bit_nr >> 3] |= (1 << bit_nr);
1408 }
1409 }
1410 /* ToDo: perhaps we need to stop the Tx and Rx process here? */
1411 if (memcmp(mc_filter, ep->mc_filter, sizeof(mc_filter))) {
1412 for (i = 0; i < 4; i++)
1413 outw(((u16 *)mc_filter)[i], ioaddr + MC0 + i*4);
1414 memcpy(ep->mc_filter, mc_filter, sizeof(mc_filter));
1415 }
1416 return;
1417 }
1418
1419 static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1420 {
1421 struct epic_private *np = dev->priv;
1422
1423 strcpy (info->driver, DRV_NAME);
1424 strcpy (info->version, DRV_VERSION);
1425 strcpy (info->bus_info, pci_name(np->pci_dev));
1426 }
1427
1428 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1429 {
1430 struct epic_private *np = dev->priv;
1431 int rc;
1432
1433 spin_lock_irq(&np->lock);
1434 rc = mii_ethtool_gset(&np->mii, cmd);
1435 spin_unlock_irq(&np->lock);
1436
1437 return rc;
1438 }
1439
1440 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1441 {
1442 struct epic_private *np = dev->priv;
1443 int rc;
1444
1445 spin_lock_irq(&np->lock);
1446 rc = mii_ethtool_sset(&np->mii, cmd);
1447 spin_unlock_irq(&np->lock);
1448
1449 return rc;
1450 }
1451
1452 static int netdev_nway_reset(struct net_device *dev)
1453 {
1454 struct epic_private *np = dev->priv;
1455 return mii_nway_restart(&np->mii);
1456 }
1457
1458 static u32 netdev_get_link(struct net_device *dev)
1459 {
1460 struct epic_private *np = dev->priv;
1461 return mii_link_ok(&np->mii);
1462 }
1463
1464 static u32 netdev_get_msglevel(struct net_device *dev)
1465 {
1466 return debug;
1467 }
1468
1469 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1470 {
1471 debug = value;
1472 }
1473
1474 static int ethtool_begin(struct net_device *dev)
1475 {
1476 unsigned long ioaddr = dev->base_addr;
1477 /* power-up, if interface is down */
1478 if (! netif_running(dev)) {
1479 outl(0x0200, ioaddr + GENCTL);
1480 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1481 }
1482 return 0;
1483 }
1484
1485 static void ethtool_complete(struct net_device *dev)
1486 {
1487 unsigned long ioaddr = dev->base_addr;
1488 /* power-down, if interface is down */
1489 if (! netif_running(dev)) {
1490 outl(0x0008, ioaddr + GENCTL);
1491 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1492 }
1493 }
1494
1495 static const struct ethtool_ops netdev_ethtool_ops = {
1496 .get_drvinfo = netdev_get_drvinfo,
1497 .get_settings = netdev_get_settings,
1498 .set_settings = netdev_set_settings,
1499 .nway_reset = netdev_nway_reset,
1500 .get_link = netdev_get_link,
1501 .get_msglevel = netdev_get_msglevel,
1502 .set_msglevel = netdev_set_msglevel,
1503 .get_sg = ethtool_op_get_sg,
1504 .get_tx_csum = ethtool_op_get_tx_csum,
1505 .begin = ethtool_begin,
1506 .complete = ethtool_complete
1507 };
1508
1509 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1510 {
1511 struct epic_private *np = dev->priv;
1512 long ioaddr = dev->base_addr;
1513 struct mii_ioctl_data *data = if_mii(rq);
1514 int rc;
1515
1516 /* power-up, if interface is down */
1517 if (! netif_running(dev)) {
1518 outl(0x0200, ioaddr + GENCTL);
1519 outl((inl(ioaddr + NVCTL) & ~0x003C) | 0x4800, ioaddr + NVCTL);
1520 }
1521
1522 /* all non-ethtool ioctls (the SIOC[GS]MIIxxx ioctls) */
1523 spin_lock_irq(&np->lock);
1524 rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
1525 spin_unlock_irq(&np->lock);
1526
1527 /* power-down, if interface is down */
1528 if (! netif_running(dev)) {
1529 outl(0x0008, ioaddr + GENCTL);
1530 outl((inl(ioaddr + NVCTL) & ~0x483C) | 0x0000, ioaddr + NVCTL);
1531 }
1532 return rc;
1533 }
1534
1535
1536 static void __devexit epic_remove_one (struct pci_dev *pdev)
1537 {
1538 struct net_device *dev = pci_get_drvdata(pdev);
1539 struct epic_private *ep = dev->priv;
1540
1541 pci_free_consistent(pdev, TX_TOTAL_SIZE, ep->tx_ring, ep->tx_ring_dma);
1542 pci_free_consistent(pdev, RX_TOTAL_SIZE, ep->rx_ring, ep->rx_ring_dma);
1543 unregister_netdev(dev);
1544 #ifndef USE_IO_OPS
1545 iounmap((void*) dev->base_addr);
1546 #endif
1547 pci_release_regions(pdev);
1548 free_netdev(dev);
1549 pci_disable_device(pdev);
1550 pci_set_drvdata(pdev, NULL);
1551 /* pci_power_off(pdev, -1); */
1552 }
1553
1554
1555 #ifdef CONFIG_PM
1556
1557 static int epic_suspend (struct pci_dev *pdev, pm_message_t state)
1558 {
1559 struct net_device *dev = pci_get_drvdata(pdev);
1560 long ioaddr = dev->base_addr;
1561
1562 if (!netif_running(dev))
1563 return 0;
1564 epic_pause(dev);
1565 /* Put the chip into low-power mode. */
1566 outl(0x0008, ioaddr + GENCTL);
1567 /* pci_power_off(pdev, -1); */
1568 return 0;
1569 }
1570
1571
1572 static int epic_resume (struct pci_dev *pdev)
1573 {
1574 struct net_device *dev = pci_get_drvdata(pdev);
1575
1576 if (!netif_running(dev))
1577 return 0;
1578 epic_restart(dev);
1579 /* pci_power_on(pdev); */
1580 return 0;
1581 }
1582
1583 #endif /* CONFIG_PM */
1584
1585
1586 static struct pci_driver epic_driver = {
1587 .name = DRV_NAME,
1588 .id_table = epic_pci_tbl,
1589 .probe = epic_init_one,
1590 .remove = __devexit_p(epic_remove_one),
1591 #ifdef CONFIG_PM
1592 .suspend = epic_suspend,
1593 .resume = epic_resume,
1594 #endif /* CONFIG_PM */
1595 };
1596
1597
1598 static int __init epic_init (void)
1599 {
1600 /* when a module, this is printed whether or not devices are found in probe */
1601 #ifdef MODULE
1602 printk (KERN_INFO "%s" KERN_INFO "%s" KERN_INFO "%s",
1603 version, version2, version3);
1604 #endif
1605
1606 return pci_register_driver(&epic_driver);
1607 }
1608
1609
1610 static void __exit epic_cleanup (void)
1611 {
1612 pci_unregister_driver (&epic_driver);
1613 }
1614
1615
1616 module_init(epic_init);
1617 module_exit(epic_cleanup);
Linux kernel - Deliverables
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