projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: rt5645: Add struct dmi_system_id "Google Ultima" for chrome platform
[deliverable/linux.git] / drivers / net / ethernet / 3com / 3c59x.c
1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2 /*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20 */
21
22 /*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32 #define DRV_NAME "3c59x"
33
34
35
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45 #ifndef __arm__
46 static int rx_copybreak = 200;
47 #else
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
51 #endif
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
58
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63 #define tx_interrupt_mitigation 1
64
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
67 #ifdef VORTEX_DEBUG
68 static int vortex_debug = VORTEX_DEBUG;
69 #else
70 static int vortex_debug = 1;
71 #endif
72
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
78 #include <linux/in.h>
79 #include <linux/ioport.h>
80 #include <linux/interrupt.h>
81 #include <linux/pci.h>
82 #include <linux/mii.h>
83 #include <linux/init.h>
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/highmem.h>
89 #include <linux/eisa.h>
90 #include <linux/bitops.h>
91 #include <linux/jiffies.h>
92 #include <linux/gfp.h>
93 #include <asm/irq.h> /* For nr_irqs only. */
94 #include <asm/io.h>
95 #include <asm/uaccess.h>
96
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100 #define RUN_AT(x) (jiffies + (x))
101
102 #include <linux/delay.h>
103
104
105 static const char version[] =
106 DRV_NAME ": Donald Becker and others.\n";
107
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
111
112
113 /* Operational parameter that usually are not changed. */
114
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
121
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
126
127 #define PFX DRV_NAME ": "
128
129
130
131 /*
132 Theory of Operation
133
134 I. Board Compatibility
135
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145 II. Board-specific settings
146
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
150
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
154
155 III. Driver operation
156
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
160
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
165 revisions.
166
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
175
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
179 single frame.
180
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
187
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
193
194 IV. Notes
195
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
201
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
204 limit of 4K.
205 */
206
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209 */
210 enum pci_flags_bit {
211 PCI_USES_MASTER=4,
212 };
213
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221 enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_TX,
239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268 };
269
270
271 /* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275 static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280 } vortex_info_tbl[] = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
291
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
315
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
320 {"3c905C Tornado",
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
324 {"3c980 Cyclone",
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
326
327 {"3c980C Python-T",
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
362 {"3c920 Tornado",
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
369 {"3c905B-T4",
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
373
374 {NULL,}, /* NULL terminated list. */
375 };
376
377
378 static const struct pci_device_id vortex_pci_tbl[] = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427 };
428 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431 /* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
438 #define EL3_CMD 0x0e
439 #define EL3_STATUS 0x0e
440
441 /* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447 enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459 /* The SetRxFilter command accepts the following classes: */
460 enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463 /* Bits in the general status register. */
464 enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471 };
472
473 /* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475 enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479 };
480 enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484 };
485 enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489 };
490 /* EEPROM locations. */
491 enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497 enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499 };
500 enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502 };
503
504 #define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507 #define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511 #define RAM_SIZE(v) BFEXT(v, 0, 3)
512 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
513 #define RAM_SPEED(v) BFEXT(v, 4, 2)
514 #define ROM_SIZE(v) BFEXT(v, 6, 2)
515 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
516 #define XCVR(v) BFEXT(v, 20, 4)
517 #define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519 enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521 };
522 enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527 };
528 enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531 };
532 /* Boomerang bus master control registers. */
533 enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536 };
537
538 /* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543 struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
548 };
549 /* Values for the Rx status entry. */
550 enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555 };
556
557 #ifdef MAX_SKB_FRAGS
558 #define DO_ZEROCOPY 1
559 #else
560 #define DO_ZEROCOPY 0
561 #endif
562
563 struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
566 #if DO_ZEROCOPY
567 struct {
568 __le32 addr;
569 __le32 length;
570 } frag[1+MAX_SKB_FRAGS];
571 #else
572 __le32 addr;
573 __le32 length;
574 #endif
575 };
576
577 /* Values for the Tx status entry. */
578 enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582 };
583
584 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
585 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587 struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
593 };
594
595 struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 large_frames:1, /* accept large frames */
636 handling_irq:1; /* private in_irq indicator */
637 /* {get|set}_wol operations are already serialized by rtnl.
638 * no additional locking is required for the enable_wol and acpi_set_WOL()
639 */
640 int drv_flags;
641 u16 status_enable;
642 u16 intr_enable;
643 u16 available_media; /* From Wn3_Options. */
644 u16 capabilities, info1, info2; /* Various, from EEPROM. */
645 u16 advertising; /* NWay media advertisement */
646 unsigned char phys[2]; /* MII device addresses. */
647 u16 deferred; /* Resend these interrupts when we
648 * bale from the ISR */
649 u16 io_size; /* Size of PCI region (for release_region) */
650
651 /* Serialises access to hardware other than MII and variables below.
652 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
653 spinlock_t lock;
654
655 spinlock_t mii_lock; /* Serialises access to MII */
656 struct mii_if_info mii; /* MII lib hooks/info */
657 spinlock_t window_lock; /* Serialises access to windowed regs */
658 int window; /* Register window */
659 };
660
661 static void window_set(struct vortex_private *vp, int window)
662 {
663 if (window != vp->window) {
664 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
665 vp->window = window;
666 }
667 }
668
669 #define DEFINE_WINDOW_IO(size) \
670 static u ## size \
671 window_read ## size(struct vortex_private *vp, int window, int addr) \
672 { \
673 unsigned long flags; \
674 u ## size ret; \
675 spin_lock_irqsave(&vp->window_lock, flags); \
676 window_set(vp, window); \
677 ret = ioread ## size(vp->ioaddr + addr); \
678 spin_unlock_irqrestore(&vp->window_lock, flags); \
679 return ret; \
680 } \
681 static void \
682 window_write ## size(struct vortex_private *vp, u ## size value, \
683 int window, int addr) \
684 { \
685 unsigned long flags; \
686 spin_lock_irqsave(&vp->window_lock, flags); \
687 window_set(vp, window); \
688 iowrite ## size(value, vp->ioaddr + addr); \
689 spin_unlock_irqrestore(&vp->window_lock, flags); \
690 }
691 DEFINE_WINDOW_IO(8)
692 DEFINE_WINDOW_IO(16)
693 DEFINE_WINDOW_IO(32)
694
695 #ifdef CONFIG_PCI
696 #define DEVICE_PCI(dev) ((dev_is_pci(dev)) ? to_pci_dev((dev)) : NULL)
697 #else
698 #define DEVICE_PCI(dev) NULL
699 #endif
700
701 #define VORTEX_PCI(vp) \
702 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
703
704 #ifdef CONFIG_EISA
705 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
706 #else
707 #define DEVICE_EISA(dev) NULL
708 #endif
709
710 #define VORTEX_EISA(vp) \
711 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
712
713 /* The action to take with a media selection timer tick.
714 Note that we deviate from the 3Com order by checking 10base2 before AUI.
715 */
716 enum xcvr_types {
717 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
718 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
719 };
720
721 static const struct media_table {
722 char *name;
723 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
724 mask:8, /* The transceiver-present bit in Wn3_Config.*/
725 next:8; /* The media type to try next. */
726 int wait; /* Time before we check media status. */
727 } media_tbl[] = {
728 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
729 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
730 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
731 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
732 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
733 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
734 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
735 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
736 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
737 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
738 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
739 };
740
741 static struct {
742 const char str[ETH_GSTRING_LEN];
743 } ethtool_stats_keys[] = {
744 { "tx_deferred" },
745 { "tx_max_collisions" },
746 { "tx_multiple_collisions" },
747 { "tx_single_collisions" },
748 { "rx_bad_ssd" },
749 };
750
751 /* number of ETHTOOL_GSTATS u64's */
752 #define VORTEX_NUM_STATS 5
753
754 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
755 int chip_idx, int card_idx);
756 static int vortex_up(struct net_device *dev);
757 static void vortex_down(struct net_device *dev, int final);
758 static int vortex_open(struct net_device *dev);
759 static void mdio_sync(struct vortex_private *vp, int bits);
760 static int mdio_read(struct net_device *dev, int phy_id, int location);
761 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
762 static void vortex_timer(unsigned long arg);
763 static void rx_oom_timer(unsigned long arg);
764 static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
765 struct net_device *dev);
766 static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
767 struct net_device *dev);
768 static int vortex_rx(struct net_device *dev);
769 static int boomerang_rx(struct net_device *dev);
770 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
771 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
772 static int vortex_close(struct net_device *dev);
773 static void dump_tx_ring(struct net_device *dev);
774 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
775 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
776 static void set_rx_mode(struct net_device *dev);
777 #ifdef CONFIG_PCI
778 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
779 #endif
780 static void vortex_tx_timeout(struct net_device *dev);
781 static void acpi_set_WOL(struct net_device *dev);
782 static const struct ethtool_ops vortex_ethtool_ops;
783 static void set_8021q_mode(struct net_device *dev, int enable);
784
785 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
786 /* Option count limit only -- unlimited interfaces are supported. */
787 #define MAX_UNITS 8
788 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
789 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
794 static int global_options = -1;
795 static int global_full_duplex = -1;
796 static int global_enable_wol = -1;
797 static int global_use_mmio = -1;
798
799 /* Variables to work-around the Compaq PCI BIOS32 problem. */
800 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
801 static struct net_device *compaq_net_device;
802
803 static int vortex_cards_found;
804
805 module_param(debug, int, 0);
806 module_param(global_options, int, 0);
807 module_param_array(options, int, NULL, 0);
808 module_param(global_full_duplex, int, 0);
809 module_param_array(full_duplex, int, NULL, 0);
810 module_param_array(hw_checksums, int, NULL, 0);
811 module_param_array(flow_ctrl, int, NULL, 0);
812 module_param(global_enable_wol, int, 0);
813 module_param_array(enable_wol, int, NULL, 0);
814 module_param(rx_copybreak, int, 0);
815 module_param(max_interrupt_work, int, 0);
816 module_param(compaq_ioaddr, int, 0);
817 module_param(compaq_irq, int, 0);
818 module_param(compaq_device_id, int, 0);
819 module_param(watchdog, int, 0);
820 module_param(global_use_mmio, int, 0);
821 module_param_array(use_mmio, int, NULL, 0);
822 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
823 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
824 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
825 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
826 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
827 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
828 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
829 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
830 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
831 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
832 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
833 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
834 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
835 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
836 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
837 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
838 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
839
840 #ifdef CONFIG_NET_POLL_CONTROLLER
841 static void poll_vortex(struct net_device *dev)
842 {
843 struct vortex_private *vp = netdev_priv(dev);
844 unsigned long flags;
845 local_irq_save(flags);
846 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
847 local_irq_restore(flags);
848 }
849 #endif
850
851 #ifdef CONFIG_PM
852
853 static int vortex_suspend(struct device *dev)
854 {
855 struct pci_dev *pdev = to_pci_dev(dev);
856 struct net_device *ndev = pci_get_drvdata(pdev);
857
858 if (!ndev || !netif_running(ndev))
859 return 0;
860
861 netif_device_detach(ndev);
862 vortex_down(ndev, 1);
863
864 return 0;
865 }
866
867 static int vortex_resume(struct device *dev)
868 {
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct net_device *ndev = pci_get_drvdata(pdev);
871 int err;
872
873 if (!ndev || !netif_running(ndev))
874 return 0;
875
876 err = vortex_up(ndev);
877 if (err)
878 return err;
879
880 netif_device_attach(ndev);
881
882 return 0;
883 }
884
885 static const struct dev_pm_ops vortex_pm_ops = {
886 .suspend = vortex_suspend,
887 .resume = vortex_resume,
888 .freeze = vortex_suspend,
889 .thaw = vortex_resume,
890 .poweroff = vortex_suspend,
891 .restore = vortex_resume,
892 };
893
894 #define VORTEX_PM_OPS (&vortex_pm_ops)
895
896 #else /* !CONFIG_PM */
897
898 #define VORTEX_PM_OPS NULL
899
900 #endif /* !CONFIG_PM */
901
902 #ifdef CONFIG_EISA
903 static struct eisa_device_id vortex_eisa_ids[] = {
904 { "TCM5920", CH_3C592 },
905 { "TCM5970", CH_3C597 },
906 { "" }
907 };
908 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
909
910 static int __init vortex_eisa_probe(struct device *device)
911 {
912 void __iomem *ioaddr;
913 struct eisa_device *edev;
914
915 edev = to_eisa_device(device);
916
917 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
918 return -EBUSY;
919
920 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
921
922 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
923 edev->id.driver_data, vortex_cards_found)) {
924 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
925 return -ENODEV;
926 }
927
928 vortex_cards_found++;
929
930 return 0;
931 }
932
933 static int vortex_eisa_remove(struct device *device)
934 {
935 struct eisa_device *edev;
936 struct net_device *dev;
937 struct vortex_private *vp;
938 void __iomem *ioaddr;
939
940 edev = to_eisa_device(device);
941 dev = eisa_get_drvdata(edev);
942
943 if (!dev) {
944 pr_err("vortex_eisa_remove called for Compaq device!\n");
945 BUG();
946 }
947
948 vp = netdev_priv(dev);
949 ioaddr = vp->ioaddr;
950
951 unregister_netdev(dev);
952 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
953 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
954
955 free_netdev(dev);
956 return 0;
957 }
958
959 static struct eisa_driver vortex_eisa_driver = {
960 .id_table = vortex_eisa_ids,
961 .driver = {
962 .name = "3c59x",
963 .probe = vortex_eisa_probe,
964 .remove = vortex_eisa_remove
965 }
966 };
967
968 #endif /* CONFIG_EISA */
969
970 /* returns count found (>= 0), or negative on error */
971 static int __init vortex_eisa_init(void)
972 {
973 int eisa_found = 0;
974 int orig_cards_found = vortex_cards_found;
975
976 #ifdef CONFIG_EISA
977 int err;
978
979 err = eisa_driver_register (&vortex_eisa_driver);
980 if (!err) {
981 /*
982 * Because of the way EISA bus is probed, we cannot assume
983 * any device have been found when we exit from
984 * eisa_driver_register (the bus root driver may not be
985 * initialized yet). So we blindly assume something was
986 * found, and let the sysfs magic happened...
987 */
988 eisa_found = 1;
989 }
990 #endif
991
992 /* Special code to work-around the Compaq PCI BIOS32 problem. */
993 if (compaq_ioaddr) {
994 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
995 compaq_irq, compaq_device_id, vortex_cards_found++);
996 }
997
998 return vortex_cards_found - orig_cards_found + eisa_found;
999 }
1000
1001 /* returns count (>= 0), or negative on error */
1002 static int vortex_init_one(struct pci_dev *pdev,
1003 const struct pci_device_id *ent)
1004 {
1005 int rc, unit, pci_bar;
1006 struct vortex_chip_info *vci;
1007 void __iomem *ioaddr;
1008
1009 /* wake up and enable device */
1010 rc = pci_enable_device(pdev);
1011 if (rc < 0)
1012 goto out;
1013
1014 rc = pci_request_regions(pdev, DRV_NAME);
1015 if (rc < 0)
1016 goto out_disable;
1017
1018 unit = vortex_cards_found;
1019
1020 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1021 /* Determine the default if the user didn't override us */
1022 vci = &vortex_info_tbl[ent->driver_data];
1023 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1024 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1025 pci_bar = use_mmio[unit] ? 1 : 0;
1026 else
1027 pci_bar = global_use_mmio ? 1 : 0;
1028
1029 ioaddr = pci_iomap(pdev, pci_bar, 0);
1030 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1031 ioaddr = pci_iomap(pdev, 0, 0);
1032 if (!ioaddr) {
1033 rc = -ENOMEM;
1034 goto out_release;
1035 }
1036
1037 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1038 ent->driver_data, unit);
1039 if (rc < 0)
1040 goto out_iounmap;
1041
1042 vortex_cards_found++;
1043 goto out;
1044
1045 out_iounmap:
1046 pci_iounmap(pdev, ioaddr);
1047 out_release:
1048 pci_release_regions(pdev);
1049 out_disable:
1050 pci_disable_device(pdev);
1051 out:
1052 return rc;
1053 }
1054
1055 static const struct net_device_ops boomrang_netdev_ops = {
1056 .ndo_open = vortex_open,
1057 .ndo_stop = vortex_close,
1058 .ndo_start_xmit = boomerang_start_xmit,
1059 .ndo_tx_timeout = vortex_tx_timeout,
1060 .ndo_get_stats = vortex_get_stats,
1061 #ifdef CONFIG_PCI
1062 .ndo_do_ioctl = vortex_ioctl,
1063 #endif
1064 .ndo_set_rx_mode = set_rx_mode,
1065 .ndo_change_mtu = eth_change_mtu,
1066 .ndo_set_mac_address = eth_mac_addr,
1067 .ndo_validate_addr = eth_validate_addr,
1068 #ifdef CONFIG_NET_POLL_CONTROLLER
1069 .ndo_poll_controller = poll_vortex,
1070 #endif
1071 };
1072
1073 static const struct net_device_ops vortex_netdev_ops = {
1074 .ndo_open = vortex_open,
1075 .ndo_stop = vortex_close,
1076 .ndo_start_xmit = vortex_start_xmit,
1077 .ndo_tx_timeout = vortex_tx_timeout,
1078 .ndo_get_stats = vortex_get_stats,
1079 #ifdef CONFIG_PCI
1080 .ndo_do_ioctl = vortex_ioctl,
1081 #endif
1082 .ndo_set_rx_mode = set_rx_mode,
1083 .ndo_change_mtu = eth_change_mtu,
1084 .ndo_set_mac_address = eth_mac_addr,
1085 .ndo_validate_addr = eth_validate_addr,
1086 #ifdef CONFIG_NET_POLL_CONTROLLER
1087 .ndo_poll_controller = poll_vortex,
1088 #endif
1089 };
1090
1091 /*
1092 * Start up the PCI/EISA device which is described by *gendev.
1093 * Return 0 on success.
1094 *
1095 * NOTE: pdev can be NULL, for the case of a Compaq device
1096 */
1097 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1098 int chip_idx, int card_idx)
1099 {
1100 struct vortex_private *vp;
1101 int option;
1102 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1103 int i, step;
1104 struct net_device *dev;
1105 static int printed_version;
1106 int retval, print_info;
1107 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1108 const char *print_name = "3c59x";
1109 struct pci_dev *pdev = NULL;
1110 struct eisa_device *edev = NULL;
1111
1112 if (!printed_version) {
1113 pr_info("%s", version);
1114 printed_version = 1;
1115 }
1116
1117 if (gendev) {
1118 if ((pdev = DEVICE_PCI(gendev))) {
1119 print_name = pci_name(pdev);
1120 }
1121
1122 if ((edev = DEVICE_EISA(gendev))) {
1123 print_name = dev_name(&edev->dev);
1124 }
1125 }
1126
1127 dev = alloc_etherdev(sizeof(*vp));
1128 retval = -ENOMEM;
1129 if (!dev)
1130 goto out;
1131
1132 SET_NETDEV_DEV(dev, gendev);
1133 vp = netdev_priv(dev);
1134
1135 option = global_options;
1136
1137 /* The lower four bits are the media type. */
1138 if (dev->mem_start) {
1139 /*
1140 * The 'options' param is passed in as the third arg to the
1141 * LILO 'ether=' argument for non-modular use
1142 */
1143 option = dev->mem_start;
1144 }
1145 else if (card_idx < MAX_UNITS) {
1146 if (options[card_idx] >= 0)
1147 option = options[card_idx];
1148 }
1149
1150 if (option > 0) {
1151 if (option & 0x8000)
1152 vortex_debug = 7;
1153 if (option & 0x4000)
1154 vortex_debug = 2;
1155 if (option & 0x0400)
1156 vp->enable_wol = 1;
1157 }
1158
1159 print_info = (vortex_debug > 1);
1160 if (print_info)
1161 pr_info("See Documentation/networking/vortex.txt\n");
1162
1163 pr_info("%s: 3Com %s %s at %p.\n",
1164 print_name,
1165 pdev ? "PCI" : "EISA",
1166 vci->name,
1167 ioaddr);
1168
1169 dev->base_addr = (unsigned long)ioaddr;
1170 dev->irq = irq;
1171 dev->mtu = mtu;
1172 vp->ioaddr = ioaddr;
1173 vp->large_frames = mtu > 1500;
1174 vp->drv_flags = vci->drv_flags;
1175 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1176 vp->io_size = vci->io_size;
1177 vp->card_idx = card_idx;
1178 vp->window = -1;
1179
1180 /* module list only for Compaq device */
1181 if (gendev == NULL) {
1182 compaq_net_device = dev;
1183 }
1184
1185 /* PCI-only startup logic */
1186 if (pdev) {
1187 /* enable bus-mastering if necessary */
1188 if (vci->flags & PCI_USES_MASTER)
1189 pci_set_master(pdev);
1190
1191 if (vci->drv_flags & IS_VORTEX) {
1192 u8 pci_latency;
1193 u8 new_latency = 248;
1194
1195 /* Check the PCI latency value. On the 3c590 series the latency timer
1196 must be set to the maximum value to avoid data corruption that occurs
1197 when the timer expires during a transfer. This bug exists the Vortex
1198 chip only. */
1199 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1200 if (pci_latency < new_latency) {
1201 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1202 print_name, pci_latency, new_latency);
1203 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1204 }
1205 }
1206 }
1207
1208 spin_lock_init(&vp->lock);
1209 spin_lock_init(&vp->mii_lock);
1210 spin_lock_init(&vp->window_lock);
1211 vp->gendev = gendev;
1212 vp->mii.dev = dev;
1213 vp->mii.mdio_read = mdio_read;
1214 vp->mii.mdio_write = mdio_write;
1215 vp->mii.phy_id_mask = 0x1f;
1216 vp->mii.reg_num_mask = 0x1f;
1217
1218 /* Makes sure rings are at least 16 byte aligned. */
1219 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1220 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1221 &vp->rx_ring_dma);
1222 retval = -ENOMEM;
1223 if (!vp->rx_ring)
1224 goto free_device;
1225
1226 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1227 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1228
1229 /* if we are a PCI driver, we store info in pdev->driver_data
1230 * instead of a module list */
1231 if (pdev)
1232 pci_set_drvdata(pdev, dev);
1233 if (edev)
1234 eisa_set_drvdata(edev, dev);
1235
1236 vp->media_override = 7;
1237 if (option >= 0) {
1238 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1239 if (vp->media_override != 7)
1240 vp->medialock = 1;
1241 vp->full_duplex = (option & 0x200) ? 1 : 0;
1242 vp->bus_master = (option & 16) ? 1 : 0;
1243 }
1244
1245 if (global_full_duplex > 0)
1246 vp->full_duplex = 1;
1247 if (global_enable_wol > 0)
1248 vp->enable_wol = 1;
1249
1250 if (card_idx < MAX_UNITS) {
1251 if (full_duplex[card_idx] > 0)
1252 vp->full_duplex = 1;
1253 if (flow_ctrl[card_idx] > 0)
1254 vp->flow_ctrl = 1;
1255 if (enable_wol[card_idx] > 0)
1256 vp->enable_wol = 1;
1257 }
1258
1259 vp->mii.force_media = vp->full_duplex;
1260 vp->options = option;
1261 /* Read the station address from the EEPROM. */
1262 {
1263 int base;
1264
1265 if (vci->drv_flags & EEPROM_8BIT)
1266 base = 0x230;
1267 else if (vci->drv_flags & EEPROM_OFFSET)
1268 base = EEPROM_Read + 0x30;
1269 else
1270 base = EEPROM_Read;
1271
1272 for (i = 0; i < 0x40; i++) {
1273 int timer;
1274 window_write16(vp, base + i, 0, Wn0EepromCmd);
1275 /* Pause for at least 162 us. for the read to take place. */
1276 for (timer = 10; timer >= 0; timer--) {
1277 udelay(162);
1278 if ((window_read16(vp, 0, Wn0EepromCmd) &
1279 0x8000) == 0)
1280 break;
1281 }
1282 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1283 }
1284 }
1285 for (i = 0; i < 0x18; i++)
1286 checksum ^= eeprom[i];
1287 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1288 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1289 while (i < 0x21)
1290 checksum ^= eeprom[i++];
1291 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1292 }
1293 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1294 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1295 for (i = 0; i < 3; i++)
1296 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1297 if (print_info)
1298 pr_cont(" %pM", dev->dev_addr);
1299 /* Unfortunately an all zero eeprom passes the checksum and this
1300 gets found in the wild in failure cases. Crypto is hard 8) */
1301 if (!is_valid_ether_addr(dev->dev_addr)) {
1302 retval = -EINVAL;
1303 pr_err("*** EEPROM MAC address is invalid.\n");
1304 goto free_ring; /* With every pack */
1305 }
1306 for (i = 0; i < 6; i++)
1307 window_write8(vp, dev->dev_addr[i], 2, i);
1308
1309 if (print_info)
1310 pr_cont(", IRQ %d\n", dev->irq);
1311 /* Tell them about an invalid IRQ. */
1312 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1313 pr_warn(" *** Warning: IRQ %d is unlikely to work! ***\n",
1314 dev->irq);
1315
1316 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1317 if (print_info) {
1318 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1319 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1320 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1321 }
1322
1323
1324 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1325 unsigned short n;
1326
1327 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1328 if (!vp->cb_fn_base) {
1329 retval = -ENOMEM;
1330 goto free_ring;
1331 }
1332
1333 if (print_info) {
1334 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1335 print_name,
1336 (unsigned long long)pci_resource_start(pdev, 2),
1337 vp->cb_fn_base);
1338 }
1339
1340 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1341 if (vp->drv_flags & INVERT_LED_PWR)
1342 n |= 0x10;
1343 if (vp->drv_flags & INVERT_MII_PWR)
1344 n |= 0x4000;
1345 window_write16(vp, n, 2, Wn2_ResetOptions);
1346 if (vp->drv_flags & WNO_XCVR_PWR) {
1347 window_write16(vp, 0x0800, 0, 0);
1348 }
1349 }
1350
1351 /* Extract our information from the EEPROM data. */
1352 vp->info1 = eeprom[13];
1353 vp->info2 = eeprom[15];
1354 vp->capabilities = eeprom[16];
1355
1356 if (vp->info1 & 0x8000) {
1357 vp->full_duplex = 1;
1358 if (print_info)
1359 pr_info("Full duplex capable\n");
1360 }
1361
1362 {
1363 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1364 unsigned int config;
1365 vp->available_media = window_read16(vp, 3, Wn3_Options);
1366 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1367 vp->available_media = 0x40;
1368 config = window_read32(vp, 3, Wn3_Config);
1369 if (print_info) {
1370 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1371 config, window_read16(vp, 3, Wn3_Options));
1372 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1373 8 << RAM_SIZE(config),
1374 RAM_WIDTH(config) ? "word" : "byte",
1375 ram_split[RAM_SPLIT(config)],
1376 AUTOSELECT(config) ? "autoselect/" : "",
1377 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1378 media_tbl[XCVR(config)].name);
1379 }
1380 vp->default_media = XCVR(config);
1381 if (vp->default_media == XCVR_NWAY)
1382 vp->has_nway = 1;
1383 vp->autoselect = AUTOSELECT(config);
1384 }
1385
1386 if (vp->media_override != 7) {
1387 pr_info("%s: Media override to transceiver type %d (%s).\n",
1388 print_name, vp->media_override,
1389 media_tbl[vp->media_override].name);
1390 dev->if_port = vp->media_override;
1391 } else
1392 dev->if_port = vp->default_media;
1393
1394 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1395 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1396 int phy, phy_idx = 0;
1397 mii_preamble_required++;
1398 if (vp->drv_flags & EXTRA_PREAMBLE)
1399 mii_preamble_required++;
1400 mdio_sync(vp, 32);
1401 mdio_read(dev, 24, MII_BMSR);
1402 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1403 int mii_status, phyx;
1404
1405 /*
1406 * For the 3c905CX we look at index 24 first, because it bogusly
1407 * reports an external PHY at all indices
1408 */
1409 if (phy == 0)
1410 phyx = 24;
1411 else if (phy <= 24)
1412 phyx = phy - 1;
1413 else
1414 phyx = phy;
1415 mii_status = mdio_read(dev, phyx, MII_BMSR);
1416 if (mii_status && mii_status != 0xffff) {
1417 vp->phys[phy_idx++] = phyx;
1418 if (print_info) {
1419 pr_info(" MII transceiver found at address %d, status %4x.\n",
1420 phyx, mii_status);
1421 }
1422 if ((mii_status & 0x0040) == 0)
1423 mii_preamble_required++;
1424 }
1425 }
1426 mii_preamble_required--;
1427 if (phy_idx == 0) {
1428 pr_warn(" ***WARNING*** No MII transceivers found!\n");
1429 vp->phys[0] = 24;
1430 } else {
1431 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1432 if (vp->full_duplex) {
1433 /* Only advertise the FD media types. */
1434 vp->advertising &= ~0x02A0;
1435 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1436 }
1437 }
1438 vp->mii.phy_id = vp->phys[0];
1439 }
1440
1441 if (vp->capabilities & CapBusMaster) {
1442 vp->full_bus_master_tx = 1;
1443 if (print_info) {
1444 pr_info(" Enabling bus-master transmits and %s receives.\n",
1445 (vp->info2 & 1) ? "early" : "whole-frame" );
1446 }
1447 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1448 vp->bus_master = 0; /* AKPM: vortex only */
1449 }
1450
1451 /* The 3c59x-specific entries in the device structure. */
1452 if (vp->full_bus_master_tx) {
1453 dev->netdev_ops = &boomrang_netdev_ops;
1454 /* Actually, it still should work with iommu. */
1455 if (card_idx < MAX_UNITS &&
1456 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1457 hw_checksums[card_idx] == 1)) {
1458 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1459 }
1460 } else
1461 dev->netdev_ops = &vortex_netdev_ops;
1462
1463 if (print_info) {
1464 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1465 print_name,
1466 (dev->features & NETIF_F_SG) ? "en":"dis",
1467 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1468 }
1469
1470 dev->ethtool_ops = &vortex_ethtool_ops;
1471 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1472
1473 if (pdev) {
1474 vp->pm_state_valid = 1;
1475 pci_save_state(pdev);
1476 acpi_set_WOL(dev);
1477 }
1478 retval = register_netdev(dev);
1479 if (retval == 0)
1480 return 0;
1481
1482 free_ring:
1483 pci_free_consistent(pdev,
1484 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1485 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1486 vp->rx_ring,
1487 vp->rx_ring_dma);
1488 free_device:
1489 free_netdev(dev);
1490 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1491 out:
1492 return retval;
1493 }
1494
1495 static void
1496 issue_and_wait(struct net_device *dev, int cmd)
1497 {
1498 struct vortex_private *vp = netdev_priv(dev);
1499 void __iomem *ioaddr = vp->ioaddr;
1500 int i;
1501
1502 iowrite16(cmd, ioaddr + EL3_CMD);
1503 for (i = 0; i < 2000; i++) {
1504 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1505 return;
1506 }
1507
1508 /* OK, that didn't work. Do it the slow way. One second */
1509 for (i = 0; i < 100000; i++) {
1510 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1511 if (vortex_debug > 1)
1512 pr_info("%s: command 0x%04x took %d usecs\n",
1513 dev->name, cmd, i * 10);
1514 return;
1515 }
1516 udelay(10);
1517 }
1518 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1519 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1520 }
1521
1522 static void
1523 vortex_set_duplex(struct net_device *dev)
1524 {
1525 struct vortex_private *vp = netdev_priv(dev);
1526
1527 pr_info("%s: setting %s-duplex.\n",
1528 dev->name, (vp->full_duplex) ? "full" : "half");
1529
1530 /* Set the full-duplex bit. */
1531 window_write16(vp,
1532 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1533 (vp->large_frames ? 0x40 : 0) |
1534 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1535 0x100 : 0),
1536 3, Wn3_MAC_Ctrl);
1537 }
1538
1539 static void vortex_check_media(struct net_device *dev, unsigned int init)
1540 {
1541 struct vortex_private *vp = netdev_priv(dev);
1542 unsigned int ok_to_print = 0;
1543
1544 if (vortex_debug > 3)
1545 ok_to_print = 1;
1546
1547 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1548 vp->full_duplex = vp->mii.full_duplex;
1549 vortex_set_duplex(dev);
1550 } else if (init) {
1551 vortex_set_duplex(dev);
1552 }
1553 }
1554
1555 static int
1556 vortex_up(struct net_device *dev)
1557 {
1558 struct vortex_private *vp = netdev_priv(dev);
1559 void __iomem *ioaddr = vp->ioaddr;
1560 unsigned int config;
1561 int i, mii_reg1, mii_reg5, err = 0;
1562
1563 if (VORTEX_PCI(vp)) {
1564 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1565 if (vp->pm_state_valid)
1566 pci_restore_state(VORTEX_PCI(vp));
1567 err = pci_enable_device(VORTEX_PCI(vp));
1568 if (err) {
1569 pr_warn("%s: Could not enable device\n", dev->name);
1570 goto err_out;
1571 }
1572 }
1573
1574 /* Before initializing select the active media port. */
1575 config = window_read32(vp, 3, Wn3_Config);
1576
1577 if (vp->media_override != 7) {
1578 pr_info("%s: Media override to transceiver %d (%s).\n",
1579 dev->name, vp->media_override,
1580 media_tbl[vp->media_override].name);
1581 dev->if_port = vp->media_override;
1582 } else if (vp->autoselect) {
1583 if (vp->has_nway) {
1584 if (vortex_debug > 1)
1585 pr_info("%s: using NWAY device table, not %d\n",
1586 dev->name, dev->if_port);
1587 dev->if_port = XCVR_NWAY;
1588 } else {
1589 /* Find first available media type, starting with 100baseTx. */
1590 dev->if_port = XCVR_100baseTx;
1591 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1592 dev->if_port = media_tbl[dev->if_port].next;
1593 if (vortex_debug > 1)
1594 pr_info("%s: first available media type: %s\n",
1595 dev->name, media_tbl[dev->if_port].name);
1596 }
1597 } else {
1598 dev->if_port = vp->default_media;
1599 if (vortex_debug > 1)
1600 pr_info("%s: using default media %s\n",
1601 dev->name, media_tbl[dev->if_port].name);
1602 }
1603
1604 init_timer(&vp->timer);
1605 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1606 vp->timer.data = (unsigned long)dev;
1607 vp->timer.function = vortex_timer; /* timer handler */
1608 add_timer(&vp->timer);
1609
1610 init_timer(&vp->rx_oom_timer);
1611 vp->rx_oom_timer.data = (unsigned long)dev;
1612 vp->rx_oom_timer.function = rx_oom_timer;
1613
1614 if (vortex_debug > 1)
1615 pr_debug("%s: Initial media type %s.\n",
1616 dev->name, media_tbl[dev->if_port].name);
1617
1618 vp->full_duplex = vp->mii.force_media;
1619 config = BFINS(config, dev->if_port, 20, 4);
1620 if (vortex_debug > 6)
1621 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1622 window_write32(vp, config, 3, Wn3_Config);
1623
1624 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1625 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1626 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1627 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1628 vp->mii.full_duplex = vp->full_duplex;
1629
1630 vortex_check_media(dev, 1);
1631 }
1632 else
1633 vortex_set_duplex(dev);
1634
1635 issue_and_wait(dev, TxReset);
1636 /*
1637 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1638 */
1639 issue_and_wait(dev, RxReset|0x04);
1640
1641
1642 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1643
1644 if (vortex_debug > 1) {
1645 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1646 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1647 }
1648
1649 /* Set the station address and mask in window 2 each time opened. */
1650 for (i = 0; i < 6; i++)
1651 window_write8(vp, dev->dev_addr[i], 2, i);
1652 for (; i < 12; i+=2)
1653 window_write16(vp, 0, 2, i);
1654
1655 if (vp->cb_fn_base) {
1656 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1657 if (vp->drv_flags & INVERT_LED_PWR)
1658 n |= 0x10;
1659 if (vp->drv_flags & INVERT_MII_PWR)
1660 n |= 0x4000;
1661 window_write16(vp, n, 2, Wn2_ResetOptions);
1662 }
1663
1664 if (dev->if_port == XCVR_10base2)
1665 /* Start the thinnet transceiver. We should really wait 50ms...*/
1666 iowrite16(StartCoax, ioaddr + EL3_CMD);
1667 if (dev->if_port != XCVR_NWAY) {
1668 window_write16(vp,
1669 (window_read16(vp, 4, Wn4_Media) &
1670 ~(Media_10TP|Media_SQE)) |
1671 media_tbl[dev->if_port].media_bits,
1672 4, Wn4_Media);
1673 }
1674
1675 /* Switch to the stats window, and clear all stats by reading. */
1676 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1677 for (i = 0; i < 10; i++)
1678 window_read8(vp, 6, i);
1679 window_read16(vp, 6, 10);
1680 window_read16(vp, 6, 12);
1681 /* New: On the Vortex we must also clear the BadSSD counter. */
1682 window_read8(vp, 4, 12);
1683 /* ..and on the Boomerang we enable the extra statistics bits. */
1684 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1685
1686 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1687 vp->cur_rx = vp->dirty_rx = 0;
1688 /* Initialize the RxEarly register as recommended. */
1689 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1690 iowrite32(0x0020, ioaddr + PktStatus);
1691 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1692 }
1693 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1694 vp->cur_tx = vp->dirty_tx = 0;
1695 if (vp->drv_flags & IS_BOOMERANG)
1696 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1697 /* Clear the Rx, Tx rings. */
1698 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1699 vp->rx_ring[i].status = 0;
1700 for (i = 0; i < TX_RING_SIZE; i++)
1701 vp->tx_skbuff[i] = NULL;
1702 iowrite32(0, ioaddr + DownListPtr);
1703 }
1704 /* Set receiver mode: presumably accept b-case and phys addr only. */
1705 set_rx_mode(dev);
1706 /* enable 802.1q tagged frames */
1707 set_8021q_mode(dev, 1);
1708 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1709
1710 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1711 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1712 /* Allow status bits to be seen. */
1713 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1714 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1715 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1716 (vp->bus_master ? DMADone : 0);
1717 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1718 (vp->full_bus_master_rx ? 0 : RxComplete) |
1719 StatsFull | HostError | TxComplete | IntReq
1720 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1721 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1722 /* Ack all pending events, and set active indicator mask. */
1723 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1724 ioaddr + EL3_CMD);
1725 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1726 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1727 iowrite32(0x8000, vp->cb_fn_base + 4);
1728 netif_start_queue (dev);
1729 err_out:
1730 return err;
1731 }
1732
1733 static int
1734 vortex_open(struct net_device *dev)
1735 {
1736 struct vortex_private *vp = netdev_priv(dev);
1737 int i;
1738 int retval;
1739
1740 /* Use the now-standard shared IRQ implementation. */
1741 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1742 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1743 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1744 goto err;
1745 }
1746
1747 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1748 if (vortex_debug > 2)
1749 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1750 for (i = 0; i < RX_RING_SIZE; i++) {
1751 struct sk_buff *skb;
1752 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1753 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1754 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1755
1756 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1757 GFP_KERNEL);
1758 vp->rx_skbuff[i] = skb;
1759 if (skb == NULL)
1760 break; /* Bad news! */
1761
1762 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1763 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1764 }
1765 if (i != RX_RING_SIZE) {
1766 int j;
1767 pr_emerg("%s: no memory for rx ring\n", dev->name);
1768 for (j = 0; j < i; j++) {
1769 if (vp->rx_skbuff[j]) {
1770 dev_kfree_skb(vp->rx_skbuff[j]);
1771 vp->rx_skbuff[j] = NULL;
1772 }
1773 }
1774 retval = -ENOMEM;
1775 goto err_free_irq;
1776 }
1777 /* Wrap the ring. */
1778 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1779 }
1780
1781 retval = vortex_up(dev);
1782 if (!retval)
1783 goto out;
1784
1785 err_free_irq:
1786 free_irq(dev->irq, dev);
1787 err:
1788 if (vortex_debug > 1)
1789 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1790 out:
1791 return retval;
1792 }
1793
1794 static void
1795 vortex_timer(unsigned long data)
1796 {
1797 struct net_device *dev = (struct net_device *)data;
1798 struct vortex_private *vp = netdev_priv(dev);
1799 void __iomem *ioaddr = vp->ioaddr;
1800 int next_tick = 60*HZ;
1801 int ok = 0;
1802 int media_status;
1803
1804 if (vortex_debug > 2) {
1805 pr_debug("%s: Media selection timer tick happened, %s.\n",
1806 dev->name, media_tbl[dev->if_port].name);
1807 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1808 }
1809
1810 media_status = window_read16(vp, 4, Wn4_Media);
1811 switch (dev->if_port) {
1812 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1813 if (media_status & Media_LnkBeat) {
1814 netif_carrier_on(dev);
1815 ok = 1;
1816 if (vortex_debug > 1)
1817 pr_debug("%s: Media %s has link beat, %x.\n",
1818 dev->name, media_tbl[dev->if_port].name, media_status);
1819 } else {
1820 netif_carrier_off(dev);
1821 if (vortex_debug > 1) {
1822 pr_debug("%s: Media %s has no link beat, %x.\n",
1823 dev->name, media_tbl[dev->if_port].name, media_status);
1824 }
1825 }
1826 break;
1827 case XCVR_MII: case XCVR_NWAY:
1828 {
1829 ok = 1;
1830 vortex_check_media(dev, 0);
1831 }
1832 break;
1833 default: /* Other media types handled by Tx timeouts. */
1834 if (vortex_debug > 1)
1835 pr_debug("%s: Media %s has no indication, %x.\n",
1836 dev->name, media_tbl[dev->if_port].name, media_status);
1837 ok = 1;
1838 }
1839
1840 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1841 next_tick = 5*HZ;
1842
1843 if (vp->medialock)
1844 goto leave_media_alone;
1845
1846 if (!ok) {
1847 unsigned int config;
1848
1849 spin_lock_irq(&vp->lock);
1850
1851 do {
1852 dev->if_port = media_tbl[dev->if_port].next;
1853 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1854 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1855 dev->if_port = vp->default_media;
1856 if (vortex_debug > 1)
1857 pr_debug("%s: Media selection failing, using default %s port.\n",
1858 dev->name, media_tbl[dev->if_port].name);
1859 } else {
1860 if (vortex_debug > 1)
1861 pr_debug("%s: Media selection failed, now trying %s port.\n",
1862 dev->name, media_tbl[dev->if_port].name);
1863 next_tick = media_tbl[dev->if_port].wait;
1864 }
1865 window_write16(vp,
1866 (media_status & ~(Media_10TP|Media_SQE)) |
1867 media_tbl[dev->if_port].media_bits,
1868 4, Wn4_Media);
1869
1870 config = window_read32(vp, 3, Wn3_Config);
1871 config = BFINS(config, dev->if_port, 20, 4);
1872 window_write32(vp, config, 3, Wn3_Config);
1873
1874 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1875 ioaddr + EL3_CMD);
1876 if (vortex_debug > 1)
1877 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1878 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1879
1880 spin_unlock_irq(&vp->lock);
1881 }
1882
1883 leave_media_alone:
1884 if (vortex_debug > 2)
1885 pr_debug("%s: Media selection timer finished, %s.\n",
1886 dev->name, media_tbl[dev->if_port].name);
1887
1888 mod_timer(&vp->timer, RUN_AT(next_tick));
1889 if (vp->deferred)
1890 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1891 }
1892
1893 static void vortex_tx_timeout(struct net_device *dev)
1894 {
1895 struct vortex_private *vp = netdev_priv(dev);
1896 void __iomem *ioaddr = vp->ioaddr;
1897
1898 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1899 dev->name, ioread8(ioaddr + TxStatus),
1900 ioread16(ioaddr + EL3_STATUS));
1901 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1902 window_read16(vp, 4, Wn4_NetDiag),
1903 window_read16(vp, 4, Wn4_Media),
1904 ioread32(ioaddr + PktStatus),
1905 window_read16(vp, 4, Wn4_FIFODiag));
1906 /* Slight code bloat to be user friendly. */
1907 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1908 pr_err("%s: Transmitter encountered 16 collisions --"
1909 " network cable problem?\n", dev->name);
1910 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1911 pr_err("%s: Interrupt posted but not delivered --"
1912 " IRQ blocked by another device?\n", dev->name);
1913 /* Bad idea here.. but we might as well handle a few events. */
1914 {
1915 /*
1916 * Block interrupts because vortex_interrupt does a bare spin_lock()
1917 */
1918 unsigned long flags;
1919 local_irq_save(flags);
1920 if (vp->full_bus_master_tx)
1921 boomerang_interrupt(dev->irq, dev);
1922 else
1923 vortex_interrupt(dev->irq, dev);
1924 local_irq_restore(flags);
1925 }
1926 }
1927
1928 if (vortex_debug > 0)
1929 dump_tx_ring(dev);
1930
1931 issue_and_wait(dev, TxReset);
1932
1933 dev->stats.tx_errors++;
1934 if (vp->full_bus_master_tx) {
1935 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1936 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1937 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1938 ioaddr + DownListPtr);
1939 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1940 netif_wake_queue (dev);
1941 if (vp->drv_flags & IS_BOOMERANG)
1942 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1943 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1944 } else {
1945 dev->stats.tx_dropped++;
1946 netif_wake_queue(dev);
1947 }
1948
1949 /* Issue Tx Enable */
1950 iowrite16(TxEnable, ioaddr + EL3_CMD);
1951 dev->trans_start = jiffies; /* prevent tx timeout */
1952 }
1953
1954 /*
1955 * Handle uncommon interrupt sources. This is a separate routine to minimize
1956 * the cache impact.
1957 */
1958 static void
1959 vortex_error(struct net_device *dev, int status)
1960 {
1961 struct vortex_private *vp = netdev_priv(dev);
1962 void __iomem *ioaddr = vp->ioaddr;
1963 int do_tx_reset = 0, reset_mask = 0;
1964 unsigned char tx_status = 0;
1965
1966 if (vortex_debug > 2) {
1967 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1968 }
1969
1970 if (status & TxComplete) { /* Really "TxError" for us. */
1971 tx_status = ioread8(ioaddr + TxStatus);
1972 /* Presumably a tx-timeout. We must merely re-enable. */
1973 if (vortex_debug > 2 ||
1974 (tx_status != 0x88 && vortex_debug > 0)) {
1975 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1976 dev->name, tx_status);
1977 if (tx_status == 0x82) {
1978 pr_err("Probably a duplex mismatch. See "
1979 "Documentation/networking/vortex.txt\n");
1980 }
1981 dump_tx_ring(dev);
1982 }
1983 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1984 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1985 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1986 iowrite8(0, ioaddr + TxStatus);
1987 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1988 do_tx_reset = 1;
1989 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1990 do_tx_reset = 1;
1991 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1992 } else { /* Merely re-enable the transmitter. */
1993 iowrite16(TxEnable, ioaddr + EL3_CMD);
1994 }
1995 }
1996
1997 if (status & RxEarly) /* Rx early is unused. */
1998 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1999
2000 if (status & StatsFull) { /* Empty statistics. */
2001 static int DoneDidThat;
2002 if (vortex_debug > 4)
2003 pr_debug("%s: Updating stats.\n", dev->name);
2004 update_stats(ioaddr, dev);
2005 /* HACK: Disable statistics as an interrupt source. */
2006 /* This occurs when we have the wrong media type! */
2007 if (DoneDidThat == 0 &&
2008 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2009 pr_warn("%s: Updating statistics failed, disabling stats as an interrupt source\n",
2010 dev->name);
2011 iowrite16(SetIntrEnb |
2012 (window_read16(vp, 5, 10) & ~StatsFull),
2013 ioaddr + EL3_CMD);
2014 vp->intr_enable &= ~StatsFull;
2015 DoneDidThat++;
2016 }
2017 }
2018 if (status & IntReq) { /* Restore all interrupt sources. */
2019 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2020 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2021 }
2022 if (status & HostError) {
2023 u16 fifo_diag;
2024 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2025 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2026 dev->name, fifo_diag);
2027 /* Adapter failure requires Tx/Rx reset and reinit. */
2028 if (vp->full_bus_master_tx) {
2029 int bus_status = ioread32(ioaddr + PktStatus);
2030 /* 0x80000000 PCI master abort. */
2031 /* 0x40000000 PCI target abort. */
2032 if (vortex_debug)
2033 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2034
2035 /* In this case, blow the card away */
2036 /* Must not enter D3 or we can't legally issue the reset! */
2037 vortex_down(dev, 0);
2038 issue_and_wait(dev, TotalReset | 0xff);
2039 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2040 } else if (fifo_diag & 0x0400)
2041 do_tx_reset = 1;
2042 if (fifo_diag & 0x3000) {
2043 /* Reset Rx fifo and upload logic */
2044 issue_and_wait(dev, RxReset|0x07);
2045 /* Set the Rx filter to the current state. */
2046 set_rx_mode(dev);
2047 /* enable 802.1q VLAN tagged frames */
2048 set_8021q_mode(dev, 1);
2049 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2050 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2051 }
2052 }
2053
2054 if (do_tx_reset) {
2055 issue_and_wait(dev, TxReset|reset_mask);
2056 iowrite16(TxEnable, ioaddr + EL3_CMD);
2057 if (!vp->full_bus_master_tx)
2058 netif_wake_queue(dev);
2059 }
2060 }
2061
2062 static netdev_tx_t
2063 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2064 {
2065 struct vortex_private *vp = netdev_priv(dev);
2066 void __iomem *ioaddr = vp->ioaddr;
2067
2068 /* Put out the doubleword header... */
2069 iowrite32(skb->len, ioaddr + TX_FIFO);
2070 if (vp->bus_master) {
2071 /* Set the bus-master controller to transfer the packet. */
2072 int len = (skb->len + 3) & ~3;
2073 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2074 PCI_DMA_TODEVICE);
2075 spin_lock_irq(&vp->window_lock);
2076 window_set(vp, 7);
2077 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2078 iowrite16(len, ioaddr + Wn7_MasterLen);
2079 spin_unlock_irq(&vp->window_lock);
2080 vp->tx_skb = skb;
2081 skb_tx_timestamp(skb);
2082 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2083 /* netif_wake_queue() will be called at the DMADone interrupt. */
2084 } else {
2085 /* ... and the packet rounded to a doubleword. */
2086 skb_tx_timestamp(skb);
2087 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2088 dev_consume_skb_any (skb);
2089 if (ioread16(ioaddr + TxFree) > 1536) {
2090 netif_start_queue (dev); /* AKPM: redundant? */
2091 } else {
2092 /* Interrupt us when the FIFO has room for max-sized packet. */
2093 netif_stop_queue(dev);
2094 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2095 }
2096 }
2097
2098
2099 /* Clear the Tx status stack. */
2100 {
2101 int tx_status;
2102 int i = 32;
2103
2104 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2105 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2106 if (vortex_debug > 2)
2107 pr_debug("%s: Tx error, status %2.2x.\n",
2108 dev->name, tx_status);
2109 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2110 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2111 if (tx_status & 0x30) {
2112 issue_and_wait(dev, TxReset);
2113 }
2114 iowrite16(TxEnable, ioaddr + EL3_CMD);
2115 }
2116 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2117 }
2118 }
2119 return NETDEV_TX_OK;
2120 }
2121
2122 static netdev_tx_t
2123 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2124 {
2125 struct vortex_private *vp = netdev_priv(dev);
2126 void __iomem *ioaddr = vp->ioaddr;
2127 /* Calculate the next Tx descriptor entry. */
2128 int entry = vp->cur_tx % TX_RING_SIZE;
2129 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2130 unsigned long flags;
2131 dma_addr_t dma_addr;
2132
2133 if (vortex_debug > 6) {
2134 pr_debug("boomerang_start_xmit()\n");
2135 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2136 dev->name, vp->cur_tx);
2137 }
2138
2139 /*
2140 * We can't allow a recursion from our interrupt handler back into the
2141 * tx routine, as they take the same spin lock, and that causes
2142 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2143 * a bit
2144 */
2145 if (vp->handling_irq)
2146 return NETDEV_TX_BUSY;
2147
2148 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2149 if (vortex_debug > 0)
2150 pr_warn("%s: BUG! Tx Ring full, refusing to send buffer\n",
2151 dev->name);
2152 netif_stop_queue(dev);
2153 return NETDEV_TX_BUSY;
2154 }
2155
2156 vp->tx_skbuff[entry] = skb;
2157
2158 vp->tx_ring[entry].next = 0;
2159 #if DO_ZEROCOPY
2160 if (skb->ip_summed != CHECKSUM_PARTIAL)
2161 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2162 else
2163 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2164
2165 if (!skb_shinfo(skb)->nr_frags) {
2166 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data, skb->len,
2167 PCI_DMA_TODEVICE);
2168 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2169 goto out_dma_err;
2170
2171 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2172 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2173 } else {
2174 int i;
2175
2176 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data,
2177 skb_headlen(skb), PCI_DMA_TODEVICE);
2178 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2179 goto out_dma_err;
2180
2181 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2182 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2183
2184 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2185 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2186
2187 dma_addr = skb_frag_dma_map(&VORTEX_PCI(vp)->dev, frag,
2188 0,
2189 frag->size,
2190 DMA_TO_DEVICE);
2191 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr)) {
2192 for(i = i-1; i >= 0; i--)
2193 dma_unmap_page(&VORTEX_PCI(vp)->dev,
2194 le32_to_cpu(vp->tx_ring[entry].frag[i+1].addr),
2195 le32_to_cpu(vp->tx_ring[entry].frag[i+1].length),
2196 DMA_TO_DEVICE);
2197
2198 pci_unmap_single(VORTEX_PCI(vp),
2199 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2200 le32_to_cpu(vp->tx_ring[entry].frag[0].length),
2201 PCI_DMA_TODEVICE);
2202
2203 goto out_dma_err;
2204 }
2205
2206 vp->tx_ring[entry].frag[i+1].addr =
2207 cpu_to_le32(dma_addr);
2208
2209 if (i == skb_shinfo(skb)->nr_frags-1)
2210 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2211 else
2212 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2213 }
2214 }
2215 #else
2216 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE);
2217 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2218 goto out_dma_err;
2219 vp->tx_ring[entry].addr = cpu_to_le32(dma_addr);
2220 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2221 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2222 #endif
2223
2224 spin_lock_irqsave(&vp->lock, flags);
2225 /* Wait for the stall to complete. */
2226 issue_and_wait(dev, DownStall);
2227 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2228 if (ioread32(ioaddr + DownListPtr) == 0) {
2229 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2230 vp->queued_packet++;
2231 }
2232
2233 vp->cur_tx++;
2234 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2235 netif_stop_queue (dev);
2236 } else { /* Clear previous interrupt enable. */
2237 #if defined(tx_interrupt_mitigation)
2238 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2239 * were selected, this would corrupt DN_COMPLETE. No?
2240 */
2241 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2242 #endif
2243 }
2244 skb_tx_timestamp(skb);
2245 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2246 spin_unlock_irqrestore(&vp->lock, flags);
2247 out:
2248 return NETDEV_TX_OK;
2249 out_dma_err:
2250 dev_err(&VORTEX_PCI(vp)->dev, "Error mapping dma buffer\n");
2251 goto out;
2252 }
2253
2254 /* The interrupt handler does all of the Rx thread work and cleans up
2255 after the Tx thread. */
2256
2257 /*
2258 * This is the ISR for the vortex series chips.
2259 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2260 */
2261
2262 static irqreturn_t
2263 vortex_interrupt(int irq, void *dev_id)
2264 {
2265 struct net_device *dev = dev_id;
2266 struct vortex_private *vp = netdev_priv(dev);
2267 void __iomem *ioaddr;
2268 int status;
2269 int work_done = max_interrupt_work;
2270 int handled = 0;
2271
2272 ioaddr = vp->ioaddr;
2273 spin_lock(&vp->lock);
2274
2275 status = ioread16(ioaddr + EL3_STATUS);
2276
2277 if (vortex_debug > 6)
2278 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2279
2280 if ((status & IntLatch) == 0)
2281 goto handler_exit; /* No interrupt: shared IRQs cause this */
2282 handled = 1;
2283
2284 if (status & IntReq) {
2285 status |= vp->deferred;
2286 vp->deferred = 0;
2287 }
2288
2289 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2290 goto handler_exit;
2291
2292 if (vortex_debug > 4)
2293 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2294 dev->name, status, ioread8(ioaddr + Timer));
2295
2296 spin_lock(&vp->window_lock);
2297 window_set(vp, 7);
2298
2299 do {
2300 if (vortex_debug > 5)
2301 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2302 dev->name, status);
2303 if (status & RxComplete)
2304 vortex_rx(dev);
2305
2306 if (status & TxAvailable) {
2307 if (vortex_debug > 5)
2308 pr_debug(" TX room bit was handled.\n");
2309 /* There's room in the FIFO for a full-sized packet. */
2310 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2311 netif_wake_queue (dev);
2312 }
2313
2314 if (status & DMADone) {
2315 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2316 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2317 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2318 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2319 if (ioread16(ioaddr + TxFree) > 1536) {
2320 /*
2321 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2322 * insufficient FIFO room, the TxAvailable test will succeed and call
2323 * netif_wake_queue()
2324 */
2325 netif_wake_queue(dev);
2326 } else { /* Interrupt when FIFO has room for max-sized packet. */
2327 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2328 netif_stop_queue(dev);
2329 }
2330 }
2331 }
2332 /* Check for all uncommon interrupts at once. */
2333 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2334 if (status == 0xffff)
2335 break;
2336 if (status & RxEarly)
2337 vortex_rx(dev);
2338 spin_unlock(&vp->window_lock);
2339 vortex_error(dev, status);
2340 spin_lock(&vp->window_lock);
2341 window_set(vp, 7);
2342 }
2343
2344 if (--work_done < 0) {
2345 pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2346 dev->name, status);
2347 /* Disable all pending interrupts. */
2348 do {
2349 vp->deferred |= status;
2350 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2351 ioaddr + EL3_CMD);
2352 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2353 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2354 /* The timer will reenable interrupts. */
2355 mod_timer(&vp->timer, jiffies + 1*HZ);
2356 break;
2357 }
2358 /* Acknowledge the IRQ. */
2359 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2360 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2361
2362 spin_unlock(&vp->window_lock);
2363
2364 if (vortex_debug > 4)
2365 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2366 dev->name, status);
2367 handler_exit:
2368 spin_unlock(&vp->lock);
2369 return IRQ_RETVAL(handled);
2370 }
2371
2372 /*
2373 * This is the ISR for the boomerang series chips.
2374 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2375 */
2376
2377 static irqreturn_t
2378 boomerang_interrupt(int irq, void *dev_id)
2379 {
2380 struct net_device *dev = dev_id;
2381 struct vortex_private *vp = netdev_priv(dev);
2382 void __iomem *ioaddr;
2383 int status;
2384 int work_done = max_interrupt_work;
2385
2386 ioaddr = vp->ioaddr;
2387
2388
2389 /*
2390 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2391 * and boomerang_start_xmit
2392 */
2393 spin_lock(&vp->lock);
2394 vp->handling_irq = 1;
2395
2396 status = ioread16(ioaddr + EL3_STATUS);
2397
2398 if (vortex_debug > 6)
2399 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2400
2401 if ((status & IntLatch) == 0)
2402 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2403
2404 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2405 if (vortex_debug > 1)
2406 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2407 goto handler_exit;
2408 }
2409
2410 if (status & IntReq) {
2411 status |= vp->deferred;
2412 vp->deferred = 0;
2413 }
2414
2415 if (vortex_debug > 4)
2416 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2417 dev->name, status, ioread8(ioaddr + Timer));
2418 do {
2419 if (vortex_debug > 5)
2420 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2421 dev->name, status);
2422 if (status & UpComplete) {
2423 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2424 if (vortex_debug > 5)
2425 pr_debug("boomerang_interrupt->boomerang_rx\n");
2426 boomerang_rx(dev);
2427 }
2428
2429 if (status & DownComplete) {
2430 unsigned int dirty_tx = vp->dirty_tx;
2431
2432 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2433 while (vp->cur_tx - dirty_tx > 0) {
2434 int entry = dirty_tx % TX_RING_SIZE;
2435 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2436 if (ioread32(ioaddr + DownListPtr) ==
2437 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2438 break; /* It still hasn't been processed. */
2439 #else
2440 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2441 break; /* It still hasn't been processed. */
2442 #endif
2443
2444 if (vp->tx_skbuff[entry]) {
2445 struct sk_buff *skb = vp->tx_skbuff[entry];
2446 #if DO_ZEROCOPY
2447 int i;
2448 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2449 pci_unmap_single(VORTEX_PCI(vp),
2450 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2451 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2452 PCI_DMA_TODEVICE);
2453 #else
2454 pci_unmap_single(VORTEX_PCI(vp),
2455 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2456 #endif
2457 dev_kfree_skb_irq(skb);
2458 vp->tx_skbuff[entry] = NULL;
2459 } else {
2460 pr_debug("boomerang_interrupt: no skb!\n");
2461 }
2462 /* dev->stats.tx_packets++; Counted below. */
2463 dirty_tx++;
2464 }
2465 vp->dirty_tx = dirty_tx;
2466 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2467 if (vortex_debug > 6)
2468 pr_debug("boomerang_interrupt: wake queue\n");
2469 netif_wake_queue (dev);
2470 }
2471 }
2472
2473 /* Check for all uncommon interrupts at once. */
2474 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2475 vortex_error(dev, status);
2476
2477 if (--work_done < 0) {
2478 pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2479 dev->name, status);
2480 /* Disable all pending interrupts. */
2481 do {
2482 vp->deferred |= status;
2483 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2484 ioaddr + EL3_CMD);
2485 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2486 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2487 /* The timer will reenable interrupts. */
2488 mod_timer(&vp->timer, jiffies + 1*HZ);
2489 break;
2490 }
2491 /* Acknowledge the IRQ. */
2492 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2493 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2494 iowrite32(0x8000, vp->cb_fn_base + 4);
2495
2496 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2497
2498 if (vortex_debug > 4)
2499 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2500 dev->name, status);
2501 handler_exit:
2502 vp->handling_irq = 0;
2503 spin_unlock(&vp->lock);
2504 return IRQ_HANDLED;
2505 }
2506
2507 static int vortex_rx(struct net_device *dev)
2508 {
2509 struct vortex_private *vp = netdev_priv(dev);
2510 void __iomem *ioaddr = vp->ioaddr;
2511 int i;
2512 short rx_status;
2513
2514 if (vortex_debug > 5)
2515 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2516 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2517 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2518 if (rx_status & 0x4000) { /* Error, update stats. */
2519 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2520 if (vortex_debug > 2)
2521 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2522 dev->stats.rx_errors++;
2523 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2524 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2525 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2526 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2527 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2528 } else {
2529 /* The packet length: up to 4.5K!. */
2530 int pkt_len = rx_status & 0x1fff;
2531 struct sk_buff *skb;
2532
2533 skb = netdev_alloc_skb(dev, pkt_len + 5);
2534 if (vortex_debug > 4)
2535 pr_debug("Receiving packet size %d status %4.4x.\n",
2536 pkt_len, rx_status);
2537 if (skb != NULL) {
2538 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2539 /* 'skb_put()' points to the start of sk_buff data area. */
2540 if (vp->bus_master &&
2541 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2542 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2543 pkt_len, PCI_DMA_FROMDEVICE);
2544 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2545 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2546 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2547 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2548 ;
2549 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2550 } else {
2551 ioread32_rep(ioaddr + RX_FIFO,
2552 skb_put(skb, pkt_len),
2553 (pkt_len + 3) >> 2);
2554 }
2555 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2556 skb->protocol = eth_type_trans(skb, dev);
2557 netif_rx(skb);
2558 dev->stats.rx_packets++;
2559 /* Wait a limited time to go to next packet. */
2560 for (i = 200; i >= 0; i--)
2561 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2562 break;
2563 continue;
2564 } else if (vortex_debug > 0)
2565 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2566 dev->name, pkt_len);
2567 dev->stats.rx_dropped++;
2568 }
2569 issue_and_wait(dev, RxDiscard);
2570 }
2571
2572 return 0;
2573 }
2574
2575 static int
2576 boomerang_rx(struct net_device *dev)
2577 {
2578 struct vortex_private *vp = netdev_priv(dev);
2579 int entry = vp->cur_rx % RX_RING_SIZE;
2580 void __iomem *ioaddr = vp->ioaddr;
2581 int rx_status;
2582 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2583
2584 if (vortex_debug > 5)
2585 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2586
2587 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2588 if (--rx_work_limit < 0)
2589 break;
2590 if (rx_status & RxDError) { /* Error, update stats. */
2591 unsigned char rx_error = rx_status >> 16;
2592 if (vortex_debug > 2)
2593 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2594 dev->stats.rx_errors++;
2595 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2596 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2597 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2598 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2599 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2600 } else {
2601 /* The packet length: up to 4.5K!. */
2602 int pkt_len = rx_status & 0x1fff;
2603 struct sk_buff *skb;
2604 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2605
2606 if (vortex_debug > 4)
2607 pr_debug("Receiving packet size %d status %4.4x.\n",
2608 pkt_len, rx_status);
2609
2610 /* Check if the packet is long enough to just accept without
2611 copying to a properly sized skbuff. */
2612 if (pkt_len < rx_copybreak &&
2613 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2614 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2615 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2616 /* 'skb_put()' points to the start of sk_buff data area. */
2617 memcpy(skb_put(skb, pkt_len),
2618 vp->rx_skbuff[entry]->data,
2619 pkt_len);
2620 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2621 vp->rx_copy++;
2622 } else {
2623 /* Pass up the skbuff already on the Rx ring. */
2624 skb = vp->rx_skbuff[entry];
2625 vp->rx_skbuff[entry] = NULL;
2626 skb_put(skb, pkt_len);
2627 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2628 vp->rx_nocopy++;
2629 }
2630 skb->protocol = eth_type_trans(skb, dev);
2631 { /* Use hardware checksum info. */
2632 int csum_bits = rx_status & 0xee000000;
2633 if (csum_bits &&
2634 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2635 csum_bits == (IPChksumValid | UDPChksumValid))) {
2636 skb->ip_summed = CHECKSUM_UNNECESSARY;
2637 vp->rx_csumhits++;
2638 }
2639 }
2640 netif_rx(skb);
2641 dev->stats.rx_packets++;
2642 }
2643 entry = (++vp->cur_rx) % RX_RING_SIZE;
2644 }
2645 /* Refill the Rx ring buffers. */
2646 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2647 struct sk_buff *skb;
2648 entry = vp->dirty_rx % RX_RING_SIZE;
2649 if (vp->rx_skbuff[entry] == NULL) {
2650 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2651 if (skb == NULL) {
2652 static unsigned long last_jif;
2653 if (time_after(jiffies, last_jif + 10 * HZ)) {
2654 pr_warn("%s: memory shortage\n",
2655 dev->name);
2656 last_jif = jiffies;
2657 }
2658 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2659 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2660 break; /* Bad news! */
2661 }
2662
2663 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2664 vp->rx_skbuff[entry] = skb;
2665 }
2666 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2667 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2668 }
2669 return 0;
2670 }
2671
2672 /*
2673 * If we've hit a total OOM refilling the Rx ring we poll once a second
2674 * for some memory. Otherwise there is no way to restart the rx process.
2675 */
2676 static void
2677 rx_oom_timer(unsigned long arg)
2678 {
2679 struct net_device *dev = (struct net_device *)arg;
2680 struct vortex_private *vp = netdev_priv(dev);
2681
2682 spin_lock_irq(&vp->lock);
2683 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2684 boomerang_rx(dev);
2685 if (vortex_debug > 1) {
2686 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2687 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2688 }
2689 spin_unlock_irq(&vp->lock);
2690 }
2691
2692 static void
2693 vortex_down(struct net_device *dev, int final_down)
2694 {
2695 struct vortex_private *vp = netdev_priv(dev);
2696 void __iomem *ioaddr = vp->ioaddr;
2697
2698 netif_stop_queue (dev);
2699
2700 del_timer_sync(&vp->rx_oom_timer);
2701 del_timer_sync(&vp->timer);
2702
2703 /* Turn off statistics ASAP. We update dev->stats below. */
2704 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2705
2706 /* Disable the receiver and transmitter. */
2707 iowrite16(RxDisable, ioaddr + EL3_CMD);
2708 iowrite16(TxDisable, ioaddr + EL3_CMD);
2709
2710 /* Disable receiving 802.1q tagged frames */
2711 set_8021q_mode(dev, 0);
2712
2713 if (dev->if_port == XCVR_10base2)
2714 /* Turn off thinnet power. Green! */
2715 iowrite16(StopCoax, ioaddr + EL3_CMD);
2716
2717 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2718
2719 update_stats(ioaddr, dev);
2720 if (vp->full_bus_master_rx)
2721 iowrite32(0, ioaddr + UpListPtr);
2722 if (vp->full_bus_master_tx)
2723 iowrite32(0, ioaddr + DownListPtr);
2724
2725 if (final_down && VORTEX_PCI(vp)) {
2726 vp->pm_state_valid = 1;
2727 pci_save_state(VORTEX_PCI(vp));
2728 acpi_set_WOL(dev);
2729 }
2730 }
2731
2732 static int
2733 vortex_close(struct net_device *dev)
2734 {
2735 struct vortex_private *vp = netdev_priv(dev);
2736 void __iomem *ioaddr = vp->ioaddr;
2737 int i;
2738
2739 if (netif_device_present(dev))
2740 vortex_down(dev, 1);
2741
2742 if (vortex_debug > 1) {
2743 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2744 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2745 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2746 " tx_queued %d Rx pre-checksummed %d.\n",
2747 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2748 }
2749
2750 #if DO_ZEROCOPY
2751 if (vp->rx_csumhits &&
2752 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2753 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2754 pr_warn("%s supports hardware checksums, and we're not using them!\n",
2755 dev->name);
2756 }
2757 #endif
2758
2759 free_irq(dev->irq, dev);
2760
2761 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2762 for (i = 0; i < RX_RING_SIZE; i++)
2763 if (vp->rx_skbuff[i]) {
2764 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2765 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2766 dev_kfree_skb(vp->rx_skbuff[i]);
2767 vp->rx_skbuff[i] = NULL;
2768 }
2769 }
2770 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2771 for (i = 0; i < TX_RING_SIZE; i++) {
2772 if (vp->tx_skbuff[i]) {
2773 struct sk_buff *skb = vp->tx_skbuff[i];
2774 #if DO_ZEROCOPY
2775 int k;
2776
2777 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2778 pci_unmap_single(VORTEX_PCI(vp),
2779 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2780 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2781 PCI_DMA_TODEVICE);
2782 #else
2783 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2784 #endif
2785 dev_kfree_skb(skb);
2786 vp->tx_skbuff[i] = NULL;
2787 }
2788 }
2789 }
2790
2791 return 0;
2792 }
2793
2794 static void
2795 dump_tx_ring(struct net_device *dev)
2796 {
2797 if (vortex_debug > 0) {
2798 struct vortex_private *vp = netdev_priv(dev);
2799 void __iomem *ioaddr = vp->ioaddr;
2800
2801 if (vp->full_bus_master_tx) {
2802 int i;
2803 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2804
2805 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2806 vp->full_bus_master_tx,
2807 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2808 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2809 pr_err(" Transmit list %8.8x vs. %p.\n",
2810 ioread32(ioaddr + DownListPtr),
2811 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2812 issue_and_wait(dev, DownStall);
2813 for (i = 0; i < TX_RING_SIZE; i++) {
2814 unsigned int length;
2815
2816 #if DO_ZEROCOPY
2817 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2818 #else
2819 length = le32_to_cpu(vp->tx_ring[i].length);
2820 #endif
2821 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2822 i, &vp->tx_ring[i], length,
2823 le32_to_cpu(vp->tx_ring[i].status));
2824 }
2825 if (!stalled)
2826 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2827 }
2828 }
2829 }
2830
2831 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2832 {
2833 struct vortex_private *vp = netdev_priv(dev);
2834 void __iomem *ioaddr = vp->ioaddr;
2835 unsigned long flags;
2836
2837 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2838 spin_lock_irqsave (&vp->lock, flags);
2839 update_stats(ioaddr, dev);
2840 spin_unlock_irqrestore (&vp->lock, flags);
2841 }
2842 return &dev->stats;
2843 }
2844
2845 /* Update statistics.
2846 Unlike with the EL3 we need not worry about interrupts changing
2847 the window setting from underneath us, but we must still guard
2848 against a race condition with a StatsUpdate interrupt updating the
2849 table. This is done by checking that the ASM (!) code generated uses
2850 atomic updates with '+='.
2851 */
2852 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2853 {
2854 struct vortex_private *vp = netdev_priv(dev);
2855
2856 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2857 /* Switch to the stats window, and read everything. */
2858 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2859 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2860 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2861 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2862 dev->stats.tx_packets += window_read8(vp, 6, 6);
2863 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2864 0x30) << 4;
2865 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2866 /* Don't bother with register 9, an extension of registers 6&7.
2867 If we do use the 6&7 values the atomic update assumption above
2868 is invalid. */
2869 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2870 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2871 /* Extra stats for get_ethtool_stats() */
2872 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2873 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2874 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2875 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2876
2877 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2878 + vp->xstats.tx_single_collisions
2879 + vp->xstats.tx_max_collisions;
2880
2881 {
2882 u8 up = window_read8(vp, 4, 13);
2883 dev->stats.rx_bytes += (up & 0x0f) << 16;
2884 dev->stats.tx_bytes += (up & 0xf0) << 12;
2885 }
2886 }
2887
2888 static int vortex_nway_reset(struct net_device *dev)
2889 {
2890 struct vortex_private *vp = netdev_priv(dev);
2891
2892 return mii_nway_restart(&vp->mii);
2893 }
2894
2895 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2896 {
2897 struct vortex_private *vp = netdev_priv(dev);
2898
2899 return mii_ethtool_gset(&vp->mii, cmd);
2900 }
2901
2902 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2903 {
2904 struct vortex_private *vp = netdev_priv(dev);
2905
2906 return mii_ethtool_sset(&vp->mii, cmd);
2907 }
2908
2909 static u32 vortex_get_msglevel(struct net_device *dev)
2910 {
2911 return vortex_debug;
2912 }
2913
2914 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2915 {
2916 vortex_debug = dbg;
2917 }
2918
2919 static int vortex_get_sset_count(struct net_device *dev, int sset)
2920 {
2921 switch (sset) {
2922 case ETH_SS_STATS:
2923 return VORTEX_NUM_STATS;
2924 default:
2925 return -EOPNOTSUPP;
2926 }
2927 }
2928
2929 static void vortex_get_ethtool_stats(struct net_device *dev,
2930 struct ethtool_stats *stats, u64 *data)
2931 {
2932 struct vortex_private *vp = netdev_priv(dev);
2933 void __iomem *ioaddr = vp->ioaddr;
2934 unsigned long flags;
2935
2936 spin_lock_irqsave(&vp->lock, flags);
2937 update_stats(ioaddr, dev);
2938 spin_unlock_irqrestore(&vp->lock, flags);
2939
2940 data[0] = vp->xstats.tx_deferred;
2941 data[1] = vp->xstats.tx_max_collisions;
2942 data[2] = vp->xstats.tx_multiple_collisions;
2943 data[3] = vp->xstats.tx_single_collisions;
2944 data[4] = vp->xstats.rx_bad_ssd;
2945 }
2946
2947
2948 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2949 {
2950 switch (stringset) {
2951 case ETH_SS_STATS:
2952 memcpy(data, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
2953 break;
2954 default:
2955 WARN_ON(1);
2956 break;
2957 }
2958 }
2959
2960 static void vortex_get_drvinfo(struct net_device *dev,
2961 struct ethtool_drvinfo *info)
2962 {
2963 struct vortex_private *vp = netdev_priv(dev);
2964
2965 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2966 if (VORTEX_PCI(vp)) {
2967 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2968 sizeof(info->bus_info));
2969 } else {
2970 if (VORTEX_EISA(vp))
2971 strlcpy(info->bus_info, dev_name(vp->gendev),
2972 sizeof(info->bus_info));
2973 else
2974 snprintf(info->bus_info, sizeof(info->bus_info),
2975 "EISA 0x%lx %d", dev->base_addr, dev->irq);
2976 }
2977 }
2978
2979 static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2980 {
2981 struct vortex_private *vp = netdev_priv(dev);
2982
2983 if (!VORTEX_PCI(vp))
2984 return;
2985
2986 wol->supported = WAKE_MAGIC;
2987
2988 wol->wolopts = 0;
2989 if (vp->enable_wol)
2990 wol->wolopts |= WAKE_MAGIC;
2991 }
2992
2993 static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2994 {
2995 struct vortex_private *vp = netdev_priv(dev);
2996
2997 if (!VORTEX_PCI(vp))
2998 return -EOPNOTSUPP;
2999
3000 if (wol->wolopts & ~WAKE_MAGIC)
3001 return -EINVAL;
3002
3003 if (wol->wolopts & WAKE_MAGIC)
3004 vp->enable_wol = 1;
3005 else
3006 vp->enable_wol = 0;
3007 acpi_set_WOL(dev);
3008
3009 return 0;
3010 }
3011
3012 static const struct ethtool_ops vortex_ethtool_ops = {
3013 .get_drvinfo = vortex_get_drvinfo,
3014 .get_strings = vortex_get_strings,
3015 .get_msglevel = vortex_get_msglevel,
3016 .set_msglevel = vortex_set_msglevel,
3017 .get_ethtool_stats = vortex_get_ethtool_stats,
3018 .get_sset_count = vortex_get_sset_count,
3019 .get_settings = vortex_get_settings,
3020 .set_settings = vortex_set_settings,
3021 .get_link = ethtool_op_get_link,
3022 .nway_reset = vortex_nway_reset,
3023 .get_wol = vortex_get_wol,
3024 .set_wol = vortex_set_wol,
3025 .get_ts_info = ethtool_op_get_ts_info,
3026 };
3027
3028 #ifdef CONFIG_PCI
3029 /*
3030 * Must power the device up to do MDIO operations
3031 */
3032 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3033 {
3034 int err;
3035 struct vortex_private *vp = netdev_priv(dev);
3036 pci_power_t state = 0;
3037
3038 if(VORTEX_PCI(vp))
3039 state = VORTEX_PCI(vp)->current_state;
3040
3041 /* The kernel core really should have pci_get_power_state() */
3042
3043 if(state != 0)
3044 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3045 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3046 if(state != 0)
3047 pci_set_power_state(VORTEX_PCI(vp), state);
3048
3049 return err;
3050 }
3051 #endif
3052
3053
3054 /* Pre-Cyclone chips have no documented multicast filter, so the only
3055 multicast setting is to receive all multicast frames. At least
3056 the chip has a very clean way to set the mode, unlike many others. */
3057 static void set_rx_mode(struct net_device *dev)
3058 {
3059 struct vortex_private *vp = netdev_priv(dev);
3060 void __iomem *ioaddr = vp->ioaddr;
3061 int new_mode;
3062
3063 if (dev->flags & IFF_PROMISC) {
3064 if (vortex_debug > 3)
3065 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3066 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3067 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3068 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3069 } else
3070 new_mode = SetRxFilter | RxStation | RxBroadcast;
3071
3072 iowrite16(new_mode, ioaddr + EL3_CMD);
3073 }
3074
3075 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3076 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3077 Note that this must be done after each RxReset due to some backwards
3078 compatibility logic in the Cyclone and Tornado ASICs */
3079
3080 /* The Ethernet Type used for 802.1q tagged frames */
3081 #define VLAN_ETHER_TYPE 0x8100
3082
3083 static void set_8021q_mode(struct net_device *dev, int enable)
3084 {
3085 struct vortex_private *vp = netdev_priv(dev);
3086 int mac_ctrl;
3087
3088 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3089 /* cyclone and tornado chipsets can recognize 802.1q
3090 * tagged frames and treat them correctly */
3091
3092 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3093 if (enable)
3094 max_pkt_size += 4; /* 802.1Q VLAN tag */
3095
3096 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3097
3098 /* set VlanEtherType to let the hardware checksumming
3099 treat tagged frames correctly */
3100 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3101 } else {
3102 /* on older cards we have to enable large frames */
3103
3104 vp->large_frames = dev->mtu > 1500 || enable;
3105
3106 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3107 if (vp->large_frames)
3108 mac_ctrl |= 0x40;
3109 else
3110 mac_ctrl &= ~0x40;
3111 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3112 }
3113 }
3114 #else
3115
3116 static void set_8021q_mode(struct net_device *dev, int enable)
3117 {
3118 }
3119
3120
3121 #endif
3122
3123 /* MII transceiver control section.
3124 Read and write the MII registers using software-generated serial
3125 MDIO protocol. See the MII specifications or DP83840A data sheet
3126 for details. */
3127
3128 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3129 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3130 "overclocking" issues. */
3131 static void mdio_delay(struct vortex_private *vp)
3132 {
3133 window_read32(vp, 4, Wn4_PhysicalMgmt);
3134 }
3135
3136 #define MDIO_SHIFT_CLK 0x01
3137 #define MDIO_DIR_WRITE 0x04
3138 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3139 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3140 #define MDIO_DATA_READ 0x02
3141 #define MDIO_ENB_IN 0x00
3142
3143 /* Generate the preamble required for initial synchronization and
3144 a few older transceivers. */
3145 static void mdio_sync(struct vortex_private *vp, int bits)
3146 {
3147 /* Establish sync by sending at least 32 logic ones. */
3148 while (-- bits >= 0) {
3149 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3150 mdio_delay(vp);
3151 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3152 4, Wn4_PhysicalMgmt);
3153 mdio_delay(vp);
3154 }
3155 }
3156
3157 static int mdio_read(struct net_device *dev, int phy_id, int location)
3158 {
3159 int i;
3160 struct vortex_private *vp = netdev_priv(dev);
3161 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3162 unsigned int retval = 0;
3163
3164 spin_lock_bh(&vp->mii_lock);
3165
3166 if (mii_preamble_required)
3167 mdio_sync(vp, 32);
3168
3169 /* Shift the read command bits out. */
3170 for (i = 14; i >= 0; i--) {
3171 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3172 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3173 mdio_delay(vp);
3174 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3175 4, Wn4_PhysicalMgmt);
3176 mdio_delay(vp);
3177 }
3178 /* Read the two transition, 16 data, and wire-idle bits. */
3179 for (i = 19; i > 0; i--) {
3180 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3181 mdio_delay(vp);
3182 retval = (retval << 1) |
3183 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3184 MDIO_DATA_READ) ? 1 : 0);
3185 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3186 4, Wn4_PhysicalMgmt);
3187 mdio_delay(vp);
3188 }
3189
3190 spin_unlock_bh(&vp->mii_lock);
3191
3192 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3193 }
3194
3195 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3196 {
3197 struct vortex_private *vp = netdev_priv(dev);
3198 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3199 int i;
3200
3201 spin_lock_bh(&vp->mii_lock);
3202
3203 if (mii_preamble_required)
3204 mdio_sync(vp, 32);
3205
3206 /* Shift the command bits out. */
3207 for (i = 31; i >= 0; i--) {
3208 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3209 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3210 mdio_delay(vp);
3211 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3212 4, Wn4_PhysicalMgmt);
3213 mdio_delay(vp);
3214 }
3215 /* Leave the interface idle. */
3216 for (i = 1; i >= 0; i--) {
3217 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3218 mdio_delay(vp);
3219 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3220 4, Wn4_PhysicalMgmt);
3221 mdio_delay(vp);
3222 }
3223
3224 spin_unlock_bh(&vp->mii_lock);
3225 }
3226
3227 /* ACPI: Advanced Configuration and Power Interface. */
3228 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3229 static void acpi_set_WOL(struct net_device *dev)
3230 {
3231 struct vortex_private *vp = netdev_priv(dev);
3232 void __iomem *ioaddr = vp->ioaddr;
3233
3234 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3235
3236 if (vp->enable_wol) {
3237 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3238 window_write16(vp, 2, 7, 0x0c);
3239 /* The RxFilter must accept the WOL frames. */
3240 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3241 iowrite16(RxEnable, ioaddr + EL3_CMD);
3242
3243 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3244 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3245
3246 vp->enable_wol = 0;
3247 return;
3248 }
3249
3250 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3251 return;
3252
3253 /* Change the power state to D3; RxEnable doesn't take effect. */
3254 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3255 }
3256 }
3257
3258
3259 static void vortex_remove_one(struct pci_dev *pdev)
3260 {
3261 struct net_device *dev = pci_get_drvdata(pdev);
3262 struct vortex_private *vp;
3263
3264 if (!dev) {
3265 pr_err("vortex_remove_one called for Compaq device!\n");
3266 BUG();
3267 }
3268
3269 vp = netdev_priv(dev);
3270
3271 if (vp->cb_fn_base)
3272 pci_iounmap(pdev, vp->cb_fn_base);
3273
3274 unregister_netdev(dev);
3275
3276 pci_set_power_state(pdev, PCI_D0); /* Go active */
3277 if (vp->pm_state_valid)
3278 pci_restore_state(pdev);
3279 pci_disable_device(pdev);
3280
3281 /* Should really use issue_and_wait() here */
3282 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3283 vp->ioaddr + EL3_CMD);
3284
3285 pci_iounmap(pdev, vp->ioaddr);
3286
3287 pci_free_consistent(pdev,
3288 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3289 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3290 vp->rx_ring,
3291 vp->rx_ring_dma);
3292
3293 pci_release_regions(pdev);
3294
3295 free_netdev(dev);
3296 }
3297
3298
3299 static struct pci_driver vortex_driver = {
3300 .name = "3c59x",
3301 .probe = vortex_init_one,
3302 .remove = vortex_remove_one,
3303 .id_table = vortex_pci_tbl,
3304 .driver.pm = VORTEX_PM_OPS,
3305 };
3306
3307
3308 static int vortex_have_pci;
3309 static int vortex_have_eisa;
3310
3311
3312 static int __init vortex_init(void)
3313 {
3314 int pci_rc, eisa_rc;
3315
3316 pci_rc = pci_register_driver(&vortex_driver);
3317 eisa_rc = vortex_eisa_init();
3318
3319 if (pci_rc == 0)
3320 vortex_have_pci = 1;
3321 if (eisa_rc > 0)
3322 vortex_have_eisa = 1;
3323
3324 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3325 }
3326
3327
3328 static void __exit vortex_eisa_cleanup(void)
3329 {
3330 void __iomem *ioaddr;
3331
3332 #ifdef CONFIG_EISA
3333 /* Take care of the EISA devices */
3334 eisa_driver_unregister(&vortex_eisa_driver);
3335 #endif
3336
3337 if (compaq_net_device) {
3338 ioaddr = ioport_map(compaq_net_device->base_addr,
3339 VORTEX_TOTAL_SIZE);
3340
3341 unregister_netdev(compaq_net_device);
3342 iowrite16(TotalReset, ioaddr + EL3_CMD);
3343 release_region(compaq_net_device->base_addr,
3344 VORTEX_TOTAL_SIZE);
3345
3346 free_netdev(compaq_net_device);
3347 }
3348 }
3349
3350
3351 static void __exit vortex_cleanup(void)
3352 {
3353 if (vortex_have_pci)
3354 pci_unregister_driver(&vortex_driver);
3355 if (vortex_have_eisa)
3356 vortex_eisa_cleanup();
3357 }
3358
3359
3360 module_init(vortex_init);
3361 module_exit(vortex_cleanup);
Linux kernel - Deliverables
This page took 0.104622 seconds and 5 git commands to generate.