1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Keyur Chudgar <kchudgar@apm.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/of_gpio.h>
22 #include <linux/gpio.h>
23 #include "xgene_enet_main.h"
24 #include "xgene_enet_hw.h"
25 #include "xgene_enet_xgmac.h"
27 static void xgene_enet_wr_csr(struct xgene_enet_pdata
*pdata
,
30 void __iomem
*addr
= pdata
->eth_csr_addr
+ offset
;
35 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata
*pdata
,
38 void __iomem
*addr
= pdata
->eth_ring_if_addr
+ offset
;
43 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata
*pdata
,
46 void __iomem
*addr
= pdata
->eth_diag_csr_addr
+ offset
;
51 static bool xgene_enet_wr_indirect(void __iomem
*addr
, void __iomem
*wr
,
52 void __iomem
*cmd
, void __iomem
*cmd_done
,
53 u32 wr_addr
, u32 wr_data
)
58 iowrite32(wr_addr
, addr
);
59 iowrite32(wr_data
, wr
);
60 iowrite32(XGENE_ENET_WR_CMD
, cmd
);
62 /* wait for write command to complete */
63 while (!(done
= ioread32(cmd_done
)) && wait
--)
74 static void xgene_enet_wr_mac(struct xgene_enet_pdata
*pdata
,
75 u32 wr_addr
, u32 wr_data
)
77 void __iomem
*addr
, *wr
, *cmd
, *cmd_done
;
79 addr
= pdata
->mcx_mac_addr
+ MAC_ADDR_REG_OFFSET
;
80 wr
= pdata
->mcx_mac_addr
+ MAC_WRITE_REG_OFFSET
;
81 cmd
= pdata
->mcx_mac_addr
+ MAC_COMMAND_REG_OFFSET
;
82 cmd_done
= pdata
->mcx_mac_addr
+ MAC_COMMAND_DONE_REG_OFFSET
;
84 if (!xgene_enet_wr_indirect(addr
, wr
, cmd
, cmd_done
, wr_addr
, wr_data
))
85 netdev_err(pdata
->ndev
, "MCX mac write failed, addr: %04x\n",
89 static void xgene_enet_wr_pcs(struct xgene_enet_pdata
*pdata
,
90 u32 wr_addr
, u32 wr_data
)
92 void __iomem
*addr
, *wr
, *cmd
, *cmd_done
;
94 addr
= pdata
->pcs_addr
+ PCS_ADDR_REG_OFFSET
;
95 wr
= pdata
->pcs_addr
+ PCS_WRITE_REG_OFFSET
;
96 cmd
= pdata
->pcs_addr
+ PCS_COMMAND_REG_OFFSET
;
97 cmd_done
= pdata
->pcs_addr
+ PCS_COMMAND_DONE_REG_OFFSET
;
99 if (!xgene_enet_wr_indirect(addr
, wr
, cmd
, cmd_done
, wr_addr
, wr_data
))
100 netdev_err(pdata
->ndev
, "PCS write failed, addr: %04x\n",
104 static void xgene_enet_rd_csr(struct xgene_enet_pdata
*pdata
,
105 u32 offset
, u32
*val
)
107 void __iomem
*addr
= pdata
->eth_csr_addr
+ offset
;
109 *val
= ioread32(addr
);
112 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata
*pdata
,
113 u32 offset
, u32
*val
)
115 void __iomem
*addr
= pdata
->eth_diag_csr_addr
+ offset
;
117 *val
= ioread32(addr
);
120 static bool xgene_enet_rd_indirect(void __iomem
*addr
, void __iomem
*rd
,
121 void __iomem
*cmd
, void __iomem
*cmd_done
,
122 u32 rd_addr
, u32
*rd_data
)
127 iowrite32(rd_addr
, addr
);
128 iowrite32(XGENE_ENET_RD_CMD
, cmd
);
130 /* wait for read command to complete */
131 while (!(done
= ioread32(cmd_done
)) && wait
--)
137 *rd_data
= ioread32(rd
);
143 static void xgene_enet_rd_mac(struct xgene_enet_pdata
*pdata
,
144 u32 rd_addr
, u32
*rd_data
)
146 void __iomem
*addr
, *rd
, *cmd
, *cmd_done
;
148 addr
= pdata
->mcx_mac_addr
+ MAC_ADDR_REG_OFFSET
;
149 rd
= pdata
->mcx_mac_addr
+ MAC_READ_REG_OFFSET
;
150 cmd
= pdata
->mcx_mac_addr
+ MAC_COMMAND_REG_OFFSET
;
151 cmd_done
= pdata
->mcx_mac_addr
+ MAC_COMMAND_DONE_REG_OFFSET
;
153 if (!xgene_enet_rd_indirect(addr
, rd
, cmd
, cmd_done
, rd_addr
, rd_data
))
154 netdev_err(pdata
->ndev
, "MCX mac read failed, addr: %04x\n",
158 static bool xgene_enet_rd_pcs(struct xgene_enet_pdata
*pdata
,
159 u32 rd_addr
, u32
*rd_data
)
161 void __iomem
*addr
, *rd
, *cmd
, *cmd_done
;
164 addr
= pdata
->pcs_addr
+ PCS_ADDR_REG_OFFSET
;
165 rd
= pdata
->pcs_addr
+ PCS_READ_REG_OFFSET
;
166 cmd
= pdata
->pcs_addr
+ PCS_COMMAND_REG_OFFSET
;
167 cmd_done
= pdata
->pcs_addr
+ PCS_COMMAND_DONE_REG_OFFSET
;
169 success
= xgene_enet_rd_indirect(addr
, rd
, cmd
, cmd_done
, rd_addr
, rd_data
);
171 netdev_err(pdata
->ndev
, "PCS read failed, addr: %04x\n",
177 static int xgene_enet_ecc_init(struct xgene_enet_pdata
*pdata
)
179 struct net_device
*ndev
= pdata
->ndev
;
183 xgene_enet_wr_diag_csr(pdata
, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR
, 0x0);
185 usleep_range(100, 110);
186 xgene_enet_rd_diag_csr(pdata
, ENET_BLOCK_MEM_RDY_ADDR
, &data
);
187 } while ((data
!= 0xffffffff) && wait
--);
189 if (data
!= 0xffffffff) {
190 netdev_err(ndev
, "Failed to release memory from shutdown\n");
197 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata
*pdata
)
199 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIWQASSOC_ADDR
, 0);
200 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIFPQASSOC_ADDR
, 0);
201 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIQMLITEWQASSOC_ADDR
, 0);
202 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR
, 0);
205 static void xgene_xgmac_reset(struct xgene_enet_pdata
*pdata
)
207 xgene_enet_wr_mac(pdata
, AXGMAC_CONFIG_0
, HSTMACRST
);
208 xgene_enet_wr_mac(pdata
, AXGMAC_CONFIG_0
, 0);
211 static void xgene_pcs_reset(struct xgene_enet_pdata
*pdata
)
215 if (!xgene_enet_rd_pcs(pdata
, PCS_CONTROL_1
, &data
))
218 xgene_enet_wr_pcs(pdata
, PCS_CONTROL_1
, data
| PCS_CTRL_PCS_RST
);
219 xgene_enet_wr_pcs(pdata
, PCS_CONTROL_1
, data
& ~PCS_CTRL_PCS_RST
);
222 static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata
*pdata
)
225 u8
*dev_addr
= pdata
->ndev
->dev_addr
;
227 addr0
= (dev_addr
[3] << 24) | (dev_addr
[2] << 16) |
228 (dev_addr
[1] << 8) | dev_addr
[0];
229 addr1
= (dev_addr
[5] << 24) | (dev_addr
[4] << 16);
231 xgene_enet_wr_mac(pdata
, HSTMACADR_LSW_ADDR
, addr0
);
232 xgene_enet_wr_mac(pdata
, HSTMACADR_MSW_ADDR
, addr1
);
235 static void xgene_xgmac_set_mss(struct xgene_enet_pdata
*pdata
)
237 xgene_enet_wr_csr(pdata
, XG_TSIF_MSS_REG0_ADDR
, pdata
->mss
);
240 static u32
xgene_enet_link_status(struct xgene_enet_pdata
*pdata
)
244 xgene_enet_rd_csr(pdata
, XG_LINK_STATUS_ADDR
, &data
);
249 static void xgene_xgmac_init(struct xgene_enet_pdata
*pdata
)
253 xgene_xgmac_reset(pdata
);
255 xgene_enet_rd_mac(pdata
, AXGMAC_CONFIG_1
, &data
);
258 xgene_enet_wr_mac(pdata
, AXGMAC_CONFIG_1
, data
);
260 xgene_xgmac_set_mac_addr(pdata
);
261 xgene_xgmac_set_mss(pdata
);
263 xgene_enet_rd_csr(pdata
, XG_RSIF_CONFIG_REG_ADDR
, &data
);
264 data
|= CFG_RSIF_FPBUFF_TIMEOUT_EN
;
265 xgene_enet_wr_csr(pdata
, XG_RSIF_CONFIG_REG_ADDR
, data
);
267 xgene_enet_rd_csr(pdata
, XG_ENET_SPARE_CFG_REG_ADDR
, &data
);
269 xgene_enet_wr_csr(pdata
, XG_ENET_SPARE_CFG_REG_ADDR
, data
);
270 xgene_enet_wr_csr(pdata
, XG_ENET_SPARE_CFG_REG_1_ADDR
, 0x82);
271 xgene_enet_wr_csr(pdata
, XGENET_RX_DV_GATE_REG_0_ADDR
, 0);
272 xgene_enet_wr_csr(pdata
, XG_CFG_BYPASS_ADDR
, RESUME_TX
);
275 static void xgene_xgmac_rx_enable(struct xgene_enet_pdata
*pdata
)
279 xgene_enet_rd_mac(pdata
, AXGMAC_CONFIG_1
, &data
);
280 xgene_enet_wr_mac(pdata
, AXGMAC_CONFIG_1
, data
| HSTRFEN
);
283 static void xgene_xgmac_tx_enable(struct xgene_enet_pdata
*pdata
)
287 xgene_enet_rd_mac(pdata
, AXGMAC_CONFIG_1
, &data
);
288 xgene_enet_wr_mac(pdata
, AXGMAC_CONFIG_1
, data
| HSTTFEN
);
291 static void xgene_xgmac_rx_disable(struct xgene_enet_pdata
*pdata
)
295 xgene_enet_rd_mac(pdata
, AXGMAC_CONFIG_1
, &data
);
296 xgene_enet_wr_mac(pdata
, AXGMAC_CONFIG_1
, data
& ~HSTRFEN
);
299 static void xgene_xgmac_tx_disable(struct xgene_enet_pdata
*pdata
)
303 xgene_enet_rd_mac(pdata
, AXGMAC_CONFIG_1
, &data
);
304 xgene_enet_wr_mac(pdata
, AXGMAC_CONFIG_1
, data
& ~HSTTFEN
);
307 static int xgene_enet_reset(struct xgene_enet_pdata
*pdata
)
309 struct device
*dev
= &pdata
->pdev
->dev
;
311 if (!xgene_ring_mgr_init(pdata
))
315 clk_prepare_enable(pdata
->clk
);
317 clk_disable_unprepare(pdata
->clk
);
319 clk_prepare_enable(pdata
->clk
);
323 if (acpi_has_method(ACPI_HANDLE(&pdata
->pdev
->dev
), "_RST")) {
324 acpi_evaluate_object(ACPI_HANDLE(&pdata
->pdev
->dev
),
326 } else if (acpi_has_method(ACPI_HANDLE(&pdata
->pdev
->dev
),
328 acpi_evaluate_object(ACPI_HANDLE(&pdata
->pdev
->dev
),
334 xgene_enet_ecc_init(pdata
);
335 xgene_enet_config_ring_if_assoc(pdata
);
340 static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata
*pdata
,
341 u32 dst_ring_num
, u16 bufpool_id
)
345 xgene_enet_rd_csr(pdata
, XCLE_BYPASS_REG0_ADDR
, &cb
);
346 cb
|= CFG_CLE_BYPASS_EN0
;
347 CFG_CLE_IP_PROTOCOL0_SET(&cb
, 3);
348 xgene_enet_wr_csr(pdata
, XCLE_BYPASS_REG0_ADDR
, cb
);
350 fpsel
= xgene_enet_ring_bufnum(bufpool_id
) - 0x20;
351 xgene_enet_rd_csr(pdata
, XCLE_BYPASS_REG1_ADDR
, &cb
);
352 CFG_CLE_DSTQID0_SET(&cb
, dst_ring_num
);
353 CFG_CLE_FPSEL0_SET(&cb
, fpsel
);
354 xgene_enet_wr_csr(pdata
, XCLE_BYPASS_REG1_ADDR
, cb
);
357 static void xgene_enet_shutdown(struct xgene_enet_pdata
*pdata
)
359 struct device
*dev
= &pdata
->pdev
->dev
;
360 struct xgene_enet_desc_ring
*ring
;
365 for (i
= 0; i
< pdata
->rxq_cnt
; i
++) {
366 ring
= pdata
->rx_ring
[i
]->buf_pool
;
368 val
= xgene_enet_ring_bufnum(ring
->id
);
369 pb
|= BIT(val
- 0x20);
371 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIFPRESET_ADDR
, pb
);
374 for (i
= 0; i
< pdata
->txq_cnt
; i
++) {
375 ring
= pdata
->tx_ring
[i
];
377 val
= xgene_enet_ring_bufnum(ring
->id
);
380 xgene_enet_wr_ring_if(pdata
, ENET_CFGSSQMIWQRESET_ADDR
, pb
);
383 if (!IS_ERR(pdata
->clk
))
384 clk_disable_unprepare(pdata
->clk
);
388 static void xgene_enet_clear(struct xgene_enet_pdata
*pdata
,
389 struct xgene_enet_desc_ring
*ring
)
393 val
= xgene_enet_ring_bufnum(ring
->id
);
395 if (xgene_enet_is_bufpool(ring
->id
)) {
396 addr
= ENET_CFGSSQMIFPRESET_ADDR
;
397 data
= BIT(val
- 0x20);
399 addr
= ENET_CFGSSQMIWQRESET_ADDR
;
403 xgene_enet_wr_ring_if(pdata
, addr
, data
);
406 static void xgene_enet_link_state(struct work_struct
*work
)
408 struct xgene_enet_pdata
*pdata
= container_of(to_delayed_work(work
),
409 struct xgene_enet_pdata
, link_work
);
410 struct gpio_desc
*sfp_rdy
= pdata
->sfp_rdy
;
411 struct net_device
*ndev
= pdata
->ndev
;
412 u32 link_status
, poll_interval
;
414 link_status
= xgene_enet_link_status(pdata
);
415 if (link_status
&& !IS_ERR(sfp_rdy
) && !gpiod_get_value(sfp_rdy
))
419 if (!netif_carrier_ok(ndev
)) {
420 netif_carrier_on(ndev
);
421 xgene_xgmac_rx_enable(pdata
);
422 xgene_xgmac_tx_enable(pdata
);
423 netdev_info(ndev
, "Link is Up - 10Gbps\n");
425 poll_interval
= PHY_POLL_LINK_ON
;
427 if (netif_carrier_ok(ndev
)) {
428 xgene_xgmac_rx_disable(pdata
);
429 xgene_xgmac_tx_disable(pdata
);
430 netif_carrier_off(ndev
);
431 netdev_info(ndev
, "Link is Down\n");
433 poll_interval
= PHY_POLL_LINK_OFF
;
435 xgene_pcs_reset(pdata
);
438 schedule_delayed_work(&pdata
->link_work
, poll_interval
);
441 const struct xgene_mac_ops xgene_xgmac_ops
= {
442 .init
= xgene_xgmac_init
,
443 .reset
= xgene_xgmac_reset
,
444 .rx_enable
= xgene_xgmac_rx_enable
,
445 .tx_enable
= xgene_xgmac_tx_enable
,
446 .rx_disable
= xgene_xgmac_rx_disable
,
447 .tx_disable
= xgene_xgmac_tx_disable
,
448 .set_mac_addr
= xgene_xgmac_set_mac_addr
,
449 .set_mss
= xgene_xgmac_set_mss
,
450 .link_state
= xgene_enet_link_state
453 const struct xgene_port_ops xgene_xgport_ops
= {
454 .reset
= xgene_enet_reset
,
455 .clear
= xgene_enet_clear
,
456 .cle_bypass
= xgene_enet_xgcle_bypass
,
457 .shutdown
= xgene_enet_shutdown
,