2 * Broadcom BCM7xxx System Port Ethernet MAC driver
4 * Copyright (C) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/platform_device.h>
21 #include <linux/of_net.h>
22 #include <linux/of_mdio.h>
23 #include <linux/phy.h>
24 #include <linux/phy_fixed.h>
28 #include "bcmsysport.h"
30 /* I/O accessors register helpers */
31 #define BCM_SYSPORT_IO_MACRO(name, offset) \
32 static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \
34 u32 reg = __raw_readl(priv->base + offset + off); \
37 static inline void name##_writel(struct bcm_sysport_priv *priv, \
40 __raw_writel(val, priv->base + offset + off); \
43 BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
44 BCM_SYSPORT_IO_MACRO(intrl2_1
, SYS_PORT_INTRL2_1_OFFSET
);
45 BCM_SYSPORT_IO_MACRO(umac
, SYS_PORT_UMAC_OFFSET
);
46 BCM_SYSPORT_IO_MACRO(tdma
, SYS_PORT_TDMA_OFFSET
);
47 BCM_SYSPORT_IO_MACRO(rdma
, SYS_PORT_RDMA_OFFSET
);
48 BCM_SYSPORT_IO_MACRO(rxchk
, SYS_PORT_RXCHK_OFFSET
);
49 BCM_SYSPORT_IO_MACRO(txchk
, SYS_PORT_TXCHK_OFFSET
);
50 BCM_SYSPORT_IO_MACRO(rbuf
, SYS_PORT_RBUF_OFFSET
);
51 BCM_SYSPORT_IO_MACRO(tbuf
, SYS_PORT_TBUF_OFFSET
);
52 BCM_SYSPORT_IO_MACRO(topctrl
, SYS_PORT_TOPCTRL_OFFSET
);
54 /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
55 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
57 #define BCM_SYSPORT_INTR_L2(which) \
58 static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
61 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
62 priv->irq##which##_mask &= ~(mask); \
64 static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
67 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
68 priv->irq##which##_mask |= (mask); \
71 BCM_SYSPORT_INTR_L2(0)
72 BCM_SYSPORT_INTR_L2(1)
74 /* Register accesses to GISB/RBUS registers are expensive (few hundred
75 * nanoseconds), so keep the check for 64-bits explicit here to save
76 * one register write per-packet on 32-bits platforms.
78 static inline void dma_desc_set_addr(struct bcm_sysport_priv
*priv
,
82 #ifdef CONFIG_PHYS_ADDR_T_64BIT
83 __raw_writel(upper_32_bits(addr
) & DESC_ADDR_HI_MASK
,
84 d
+ DESC_ADDR_HI_STATUS_LEN
);
86 __raw_writel(lower_32_bits(addr
), d
+ DESC_ADDR_LO
);
89 static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv
*priv
,
90 struct dma_desc
*desc
,
93 /* Ports are latched, so write upper address first */
94 tdma_writel(priv
, desc
->addr_status_len
, TDMA_WRITE_PORT_HI(port
));
95 tdma_writel(priv
, desc
->addr_lo
, TDMA_WRITE_PORT_LO(port
));
98 /* Ethtool operations */
99 static int bcm_sysport_set_settings(struct net_device
*dev
,
100 struct ethtool_cmd
*cmd
)
102 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
104 if (!netif_running(dev
))
107 return phy_ethtool_sset(priv
->phydev
, cmd
);
110 static int bcm_sysport_get_settings(struct net_device
*dev
,
111 struct ethtool_cmd
*cmd
)
113 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
115 if (!netif_running(dev
))
118 return phy_ethtool_gset(priv
->phydev
, cmd
);
121 static int bcm_sysport_set_rx_csum(struct net_device
*dev
,
122 netdev_features_t wanted
)
124 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
127 priv
->rx_csum_en
= !!(wanted
& NETIF_F_RXCSUM
);
128 reg
= rxchk_readl(priv
, RXCHK_CONTROL
);
129 if (priv
->rx_csum_en
)
134 /* If UniMAC forwards CRC, we need to skip over it to get
135 * a valid CHK bit to be set in the per-packet status word
137 if (priv
->rx_csum_en
&& priv
->crc_fwd
)
138 reg
|= RXCHK_SKIP_FCS
;
140 reg
&= ~RXCHK_SKIP_FCS
;
142 rxchk_writel(priv
, reg
, RXCHK_CONTROL
);
147 static int bcm_sysport_set_tx_csum(struct net_device
*dev
,
148 netdev_features_t wanted
)
150 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
153 /* Hardware transmit checksum requires us to enable the Transmit status
154 * block prepended to the packet contents
156 priv
->tsb_en
= !!(wanted
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
));
157 reg
= tdma_readl(priv
, TDMA_CONTROL
);
162 tdma_writel(priv
, reg
, TDMA_CONTROL
);
167 static int bcm_sysport_set_features(struct net_device
*dev
,
168 netdev_features_t features
)
170 netdev_features_t changed
= features
^ dev
->features
;
171 netdev_features_t wanted
= dev
->wanted_features
;
174 if (changed
& NETIF_F_RXCSUM
)
175 ret
= bcm_sysport_set_rx_csum(dev
, wanted
);
176 if (changed
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
))
177 ret
= bcm_sysport_set_tx_csum(dev
, wanted
);
182 /* Hardware counters must be kept in sync because the order/offset
183 * is important here (order in structure declaration = order in hardware)
185 static const struct bcm_sysport_stats bcm_sysport_gstrings_stats
[] = {
187 STAT_NETDEV(rx_packets
),
188 STAT_NETDEV(tx_packets
),
189 STAT_NETDEV(rx_bytes
),
190 STAT_NETDEV(tx_bytes
),
191 STAT_NETDEV(rx_errors
),
192 STAT_NETDEV(tx_errors
),
193 STAT_NETDEV(rx_dropped
),
194 STAT_NETDEV(tx_dropped
),
195 STAT_NETDEV(multicast
),
196 /* UniMAC RSV counters */
197 STAT_MIB_RX("rx_64_octets", mib
.rx
.pkt_cnt
.cnt_64
),
198 STAT_MIB_RX("rx_65_127_oct", mib
.rx
.pkt_cnt
.cnt_127
),
199 STAT_MIB_RX("rx_128_255_oct", mib
.rx
.pkt_cnt
.cnt_255
),
200 STAT_MIB_RX("rx_256_511_oct", mib
.rx
.pkt_cnt
.cnt_511
),
201 STAT_MIB_RX("rx_512_1023_oct", mib
.rx
.pkt_cnt
.cnt_1023
),
202 STAT_MIB_RX("rx_1024_1518_oct", mib
.rx
.pkt_cnt
.cnt_1518
),
203 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib
.rx
.pkt_cnt
.cnt_mgv
),
204 STAT_MIB_RX("rx_1522_2047_oct", mib
.rx
.pkt_cnt
.cnt_2047
),
205 STAT_MIB_RX("rx_2048_4095_oct", mib
.rx
.pkt_cnt
.cnt_4095
),
206 STAT_MIB_RX("rx_4096_9216_oct", mib
.rx
.pkt_cnt
.cnt_9216
),
207 STAT_MIB_RX("rx_pkts", mib
.rx
.pkt
),
208 STAT_MIB_RX("rx_bytes", mib
.rx
.bytes
),
209 STAT_MIB_RX("rx_multicast", mib
.rx
.mca
),
210 STAT_MIB_RX("rx_broadcast", mib
.rx
.bca
),
211 STAT_MIB_RX("rx_fcs", mib
.rx
.fcs
),
212 STAT_MIB_RX("rx_control", mib
.rx
.cf
),
213 STAT_MIB_RX("rx_pause", mib
.rx
.pf
),
214 STAT_MIB_RX("rx_unknown", mib
.rx
.uo
),
215 STAT_MIB_RX("rx_align", mib
.rx
.aln
),
216 STAT_MIB_RX("rx_outrange", mib
.rx
.flr
),
217 STAT_MIB_RX("rx_code", mib
.rx
.cde
),
218 STAT_MIB_RX("rx_carrier", mib
.rx
.fcr
),
219 STAT_MIB_RX("rx_oversize", mib
.rx
.ovr
),
220 STAT_MIB_RX("rx_jabber", mib
.rx
.jbr
),
221 STAT_MIB_RX("rx_mtu_err", mib
.rx
.mtue
),
222 STAT_MIB_RX("rx_good_pkts", mib
.rx
.pok
),
223 STAT_MIB_RX("rx_unicast", mib
.rx
.uc
),
224 STAT_MIB_RX("rx_ppp", mib
.rx
.ppp
),
225 STAT_MIB_RX("rx_crc", mib
.rx
.rcrc
),
226 /* UniMAC TSV counters */
227 STAT_MIB_TX("tx_64_octets", mib
.tx
.pkt_cnt
.cnt_64
),
228 STAT_MIB_TX("tx_65_127_oct", mib
.tx
.pkt_cnt
.cnt_127
),
229 STAT_MIB_TX("tx_128_255_oct", mib
.tx
.pkt_cnt
.cnt_255
),
230 STAT_MIB_TX("tx_256_511_oct", mib
.tx
.pkt_cnt
.cnt_511
),
231 STAT_MIB_TX("tx_512_1023_oct", mib
.tx
.pkt_cnt
.cnt_1023
),
232 STAT_MIB_TX("tx_1024_1518_oct", mib
.tx
.pkt_cnt
.cnt_1518
),
233 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib
.tx
.pkt_cnt
.cnt_mgv
),
234 STAT_MIB_TX("tx_1522_2047_oct", mib
.tx
.pkt_cnt
.cnt_2047
),
235 STAT_MIB_TX("tx_2048_4095_oct", mib
.tx
.pkt_cnt
.cnt_4095
),
236 STAT_MIB_TX("tx_4096_9216_oct", mib
.tx
.pkt_cnt
.cnt_9216
),
237 STAT_MIB_TX("tx_pkts", mib
.tx
.pkts
),
238 STAT_MIB_TX("tx_multicast", mib
.tx
.mca
),
239 STAT_MIB_TX("tx_broadcast", mib
.tx
.bca
),
240 STAT_MIB_TX("tx_pause", mib
.tx
.pf
),
241 STAT_MIB_TX("tx_control", mib
.tx
.cf
),
242 STAT_MIB_TX("tx_fcs_err", mib
.tx
.fcs
),
243 STAT_MIB_TX("tx_oversize", mib
.tx
.ovr
),
244 STAT_MIB_TX("tx_defer", mib
.tx
.drf
),
245 STAT_MIB_TX("tx_excess_defer", mib
.tx
.edf
),
246 STAT_MIB_TX("tx_single_col", mib
.tx
.scl
),
247 STAT_MIB_TX("tx_multi_col", mib
.tx
.mcl
),
248 STAT_MIB_TX("tx_late_col", mib
.tx
.lcl
),
249 STAT_MIB_TX("tx_excess_col", mib
.tx
.ecl
),
250 STAT_MIB_TX("tx_frags", mib
.tx
.frg
),
251 STAT_MIB_TX("tx_total_col", mib
.tx
.ncl
),
252 STAT_MIB_TX("tx_jabber", mib
.tx
.jbr
),
253 STAT_MIB_TX("tx_bytes", mib
.tx
.bytes
),
254 STAT_MIB_TX("tx_good_pkts", mib
.tx
.pok
),
255 STAT_MIB_TX("tx_unicast", mib
.tx
.uc
),
256 /* UniMAC RUNT counters */
257 STAT_RUNT("rx_runt_pkts", mib
.rx_runt_cnt
),
258 STAT_RUNT("rx_runt_valid_fcs", mib
.rx_runt_fcs
),
259 STAT_RUNT("rx_runt_inval_fcs_align", mib
.rx_runt_fcs_align
),
260 STAT_RUNT("rx_runt_bytes", mib
.rx_runt_bytes
),
261 /* RXCHK misc statistics */
262 STAT_RXCHK("rxchk_bad_csum", mib
.rxchk_bad_csum
, RXCHK_BAD_CSUM_CNTR
),
263 STAT_RXCHK("rxchk_other_pkt_disc", mib
.rxchk_other_pkt_disc
,
264 RXCHK_OTHER_DISC_CNTR
),
265 /* RBUF misc statistics */
266 STAT_RBUF("rbuf_ovflow_cnt", mib
.rbuf_ovflow_cnt
, RBUF_OVFL_DISC_CNTR
),
267 STAT_RBUF("rbuf_err_cnt", mib
.rbuf_err_cnt
, RBUF_ERR_PKT_CNTR
),
270 #define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
272 static void bcm_sysport_get_drvinfo(struct net_device
*dev
,
273 struct ethtool_drvinfo
*info
)
275 strlcpy(info
->driver
, KBUILD_MODNAME
, sizeof(info
->driver
));
276 strlcpy(info
->version
, "0.1", sizeof(info
->version
));
277 strlcpy(info
->bus_info
, "platform", sizeof(info
->bus_info
));
278 info
->n_stats
= BCM_SYSPORT_STATS_LEN
;
281 static u32
bcm_sysport_get_msglvl(struct net_device
*dev
)
283 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
285 return priv
->msg_enable
;
288 static void bcm_sysport_set_msglvl(struct net_device
*dev
, u32 enable
)
290 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
292 priv
->msg_enable
= enable
;
295 static int bcm_sysport_get_sset_count(struct net_device
*dev
, int string_set
)
297 switch (string_set
) {
299 return BCM_SYSPORT_STATS_LEN
;
305 static void bcm_sysport_get_strings(struct net_device
*dev
,
306 u32 stringset
, u8
*data
)
312 for (i
= 0; i
< BCM_SYSPORT_STATS_LEN
; i
++) {
313 memcpy(data
+ i
* ETH_GSTRING_LEN
,
314 bcm_sysport_gstrings_stats
[i
].stat_string
,
323 static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv
*priv
)
327 for (i
= 0; i
< BCM_SYSPORT_STATS_LEN
; i
++) {
328 const struct bcm_sysport_stats
*s
;
333 s
= &bcm_sysport_gstrings_stats
[i
];
335 case BCM_SYSPORT_STAT_NETDEV
:
337 case BCM_SYSPORT_STAT_MIB_RX
:
338 case BCM_SYSPORT_STAT_MIB_TX
:
339 case BCM_SYSPORT_STAT_RUNT
:
340 if (s
->type
!= BCM_SYSPORT_STAT_MIB_RX
)
341 offset
= UMAC_MIB_STAT_OFFSET
;
342 val
= umac_readl(priv
, UMAC_MIB_START
+ j
+ offset
);
344 case BCM_SYSPORT_STAT_RXCHK
:
345 val
= rxchk_readl(priv
, s
->reg_offset
);
347 rxchk_writel(priv
, 0, s
->reg_offset
);
349 case BCM_SYSPORT_STAT_RBUF
:
350 val
= rbuf_readl(priv
, s
->reg_offset
);
352 rbuf_writel(priv
, 0, s
->reg_offset
);
357 p
= (char *)priv
+ s
->stat_offset
;
361 netif_dbg(priv
, hw
, priv
->netdev
, "updated MIB counters\n");
364 static void bcm_sysport_get_stats(struct net_device
*dev
,
365 struct ethtool_stats
*stats
, u64
*data
)
367 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
370 if (netif_running(dev
))
371 bcm_sysport_update_mib_counters(priv
);
373 for (i
= 0; i
< BCM_SYSPORT_STATS_LEN
; i
++) {
374 const struct bcm_sysport_stats
*s
;
377 s
= &bcm_sysport_gstrings_stats
[i
];
378 if (s
->type
== BCM_SYSPORT_STAT_NETDEV
)
379 p
= (char *)&dev
->stats
;
387 static void bcm_sysport_free_cb(struct bcm_sysport_cb
*cb
)
389 dev_kfree_skb_any(cb
->skb
);
391 dma_unmap_addr_set(cb
, dma_addr
, 0);
394 static int bcm_sysport_rx_refill(struct bcm_sysport_priv
*priv
,
395 struct bcm_sysport_cb
*cb
)
397 struct device
*kdev
= &priv
->pdev
->dev
;
398 struct net_device
*ndev
= priv
->netdev
;
402 cb
->skb
= netdev_alloc_skb(priv
->netdev
, RX_BUF_LENGTH
);
404 netif_err(priv
, rx_err
, ndev
, "SKB alloc failed\n");
408 mapping
= dma_map_single(kdev
, cb
->skb
->data
,
409 RX_BUF_LENGTH
, DMA_FROM_DEVICE
);
410 ret
= dma_mapping_error(kdev
, mapping
);
412 bcm_sysport_free_cb(cb
);
413 netif_err(priv
, rx_err
, ndev
, "DMA mapping failure\n");
417 dma_unmap_addr_set(cb
, dma_addr
, mapping
);
418 dma_desc_set_addr(priv
, priv
->rx_bd_assign_ptr
, mapping
);
420 priv
->rx_bd_assign_index
++;
421 priv
->rx_bd_assign_index
&= (priv
->num_rx_bds
- 1);
422 priv
->rx_bd_assign_ptr
= priv
->rx_bds
+
423 (priv
->rx_bd_assign_index
* DESC_SIZE
);
425 netif_dbg(priv
, rx_status
, ndev
, "RX refill\n");
430 static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv
*priv
)
432 struct bcm_sysport_cb
*cb
;
436 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
437 cb
= &priv
->rx_cbs
[priv
->rx_bd_assign_index
];
441 ret
= bcm_sysport_rx_refill(priv
, cb
);
449 /* Poll the hardware for up to budget packets to process */
450 static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv
*priv
,
453 struct device
*kdev
= &priv
->pdev
->dev
;
454 struct net_device
*ndev
= priv
->netdev
;
455 unsigned int processed
= 0, to_process
;
456 struct bcm_sysport_cb
*cb
;
458 unsigned int p_index
;
462 /* Determine how much we should process since last call */
463 p_index
= rdma_readl(priv
, RDMA_PROD_INDEX
);
464 p_index
&= RDMA_PROD_INDEX_MASK
;
466 if (p_index
< priv
->rx_c_index
)
467 to_process
= (RDMA_CONS_INDEX_MASK
+ 1) -
468 priv
->rx_c_index
+ p_index
;
470 to_process
= p_index
- priv
->rx_c_index
;
472 netif_dbg(priv
, rx_status
, ndev
,
473 "p_index=%d rx_c_index=%d to_process=%d\n",
474 p_index
, priv
->rx_c_index
, to_process
);
476 while ((processed
< to_process
) &&
477 (processed
< budget
)) {
479 cb
= &priv
->rx_cbs
[priv
->rx_read_ptr
];
481 dma_unmap_single(kdev
, dma_unmap_addr(cb
, dma_addr
),
482 RX_BUF_LENGTH
, DMA_FROM_DEVICE
);
484 /* Extract the Receive Status Block prepended */
485 rsb
= (struct bcm_rsb
*)skb
->data
;
486 len
= (rsb
->rx_status_len
>> DESC_LEN_SHIFT
) & DESC_LEN_MASK
;
487 status
= (rsb
->rx_status_len
>> DESC_STATUS_SHIFT
) &
492 if (priv
->rx_read_ptr
== priv
->num_rx_bds
)
493 priv
->rx_read_ptr
= 0;
495 netif_dbg(priv
, rx_status
, ndev
,
496 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
497 p_index
, priv
->rx_c_index
, priv
->rx_read_ptr
,
500 if (unlikely(!skb
)) {
501 netif_err(priv
, rx_err
, ndev
, "out of memory!\n");
502 ndev
->stats
.rx_dropped
++;
503 ndev
->stats
.rx_errors
++;
507 if (unlikely(!(status
& DESC_EOP
) || !(status
& DESC_SOP
))) {
508 netif_err(priv
, rx_status
, ndev
, "fragmented packet!\n");
509 ndev
->stats
.rx_dropped
++;
510 ndev
->stats
.rx_errors
++;
511 bcm_sysport_free_cb(cb
);
515 if (unlikely(status
& (RX_STATUS_ERR
| RX_STATUS_OVFLOW
))) {
516 netif_err(priv
, rx_err
, ndev
, "error packet\n");
517 if (RX_STATUS_OVFLOW
)
518 ndev
->stats
.rx_over_errors
++;
519 ndev
->stats
.rx_dropped
++;
520 ndev
->stats
.rx_errors
++;
521 bcm_sysport_free_cb(cb
);
527 /* Hardware validated our checksum */
528 if (likely(status
& DESC_L4_CSUM
))
529 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
531 /* Hardware pre-pends packets with 2bytes between Ethernet
532 * and IP header plus we have the Receive Status Block, strip
533 * off all of this from the SKB.
535 skb_pull(skb
, sizeof(*rsb
) + 2);
536 len
-= (sizeof(*rsb
) + 2);
538 /* UniMAC may forward CRC */
540 skb_trim(skb
, len
- ETH_FCS_LEN
);
544 skb
->protocol
= eth_type_trans(skb
, ndev
);
545 ndev
->stats
.rx_packets
++;
546 ndev
->stats
.rx_bytes
+= len
;
548 napi_gro_receive(&priv
->napi
, skb
);
550 bcm_sysport_rx_refill(priv
, cb
);
556 static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv
*priv
,
557 struct bcm_sysport_cb
*cb
,
558 unsigned int *bytes_compl
,
559 unsigned int *pkts_compl
)
561 struct device
*kdev
= &priv
->pdev
->dev
;
562 struct net_device
*ndev
= priv
->netdev
;
565 ndev
->stats
.tx_bytes
+= cb
->skb
->len
;
566 *bytes_compl
+= cb
->skb
->len
;
567 dma_unmap_single(kdev
, dma_unmap_addr(cb
, dma_addr
),
568 dma_unmap_len(cb
, dma_len
),
570 ndev
->stats
.tx_packets
++;
572 bcm_sysport_free_cb(cb
);
574 } else if (dma_unmap_addr(cb
, dma_addr
)) {
575 ndev
->stats
.tx_bytes
+= dma_unmap_len(cb
, dma_len
);
576 dma_unmap_page(kdev
, dma_unmap_addr(cb
, dma_addr
),
577 dma_unmap_len(cb
, dma_len
), DMA_TO_DEVICE
);
578 dma_unmap_addr_set(cb
, dma_addr
, 0);
582 /* Reclaim queued SKBs for transmission completion, lockless version */
583 static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv
*priv
,
584 struct bcm_sysport_tx_ring
*ring
)
586 struct net_device
*ndev
= priv
->netdev
;
587 unsigned int c_index
, last_c_index
, last_tx_cn
, num_tx_cbs
;
588 unsigned int pkts_compl
= 0, bytes_compl
= 0;
589 struct bcm_sysport_cb
*cb
;
590 struct netdev_queue
*txq
;
593 txq
= netdev_get_tx_queue(ndev
, ring
->index
);
595 /* Compute how many descriptors have been processed since last call */
596 hw_ind
= tdma_readl(priv
, TDMA_DESC_RING_PROD_CONS_INDEX(ring
->index
));
597 c_index
= (hw_ind
>> RING_CONS_INDEX_SHIFT
) & RING_CONS_INDEX_MASK
;
598 ring
->p_index
= (hw_ind
& RING_PROD_INDEX_MASK
);
600 last_c_index
= ring
->c_index
;
601 num_tx_cbs
= ring
->size
;
603 c_index
&= (num_tx_cbs
- 1);
605 if (c_index
>= last_c_index
)
606 last_tx_cn
= c_index
- last_c_index
;
608 last_tx_cn
= num_tx_cbs
- last_c_index
+ c_index
;
610 netif_dbg(priv
, tx_done
, ndev
,
611 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n",
612 ring
->index
, c_index
, last_tx_cn
, last_c_index
);
614 while (last_tx_cn
-- > 0) {
615 cb
= ring
->cbs
+ last_c_index
;
616 bcm_sysport_tx_reclaim_one(priv
, cb
, &bytes_compl
, &pkts_compl
);
620 last_c_index
&= (num_tx_cbs
- 1);
623 ring
->c_index
= c_index
;
625 if (netif_tx_queue_stopped(txq
) && pkts_compl
)
626 netif_tx_wake_queue(txq
);
628 netif_dbg(priv
, tx_done
, ndev
,
629 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
630 ring
->index
, ring
->c_index
, pkts_compl
, bytes_compl
);
635 /* Locked version of the per-ring TX reclaim routine */
636 static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv
*priv
,
637 struct bcm_sysport_tx_ring
*ring
)
639 unsigned int released
;
642 spin_lock_irqsave(&ring
->lock
, flags
);
643 released
= __bcm_sysport_tx_reclaim(priv
, ring
);
644 spin_unlock_irqrestore(&ring
->lock
, flags
);
649 static int bcm_sysport_tx_poll(struct napi_struct
*napi
, int budget
)
651 struct bcm_sysport_tx_ring
*ring
=
652 container_of(napi
, struct bcm_sysport_tx_ring
, napi
);
653 unsigned int work_done
= 0;
655 work_done
= bcm_sysport_tx_reclaim(ring
->priv
, ring
);
657 if (work_done
< budget
) {
659 /* re-enable TX interrupt */
660 intrl2_1_mask_clear(ring
->priv
, BIT(ring
->index
));
666 static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv
*priv
)
670 for (q
= 0; q
< priv
->netdev
->num_tx_queues
; q
++)
671 bcm_sysport_tx_reclaim(priv
, &priv
->tx_rings
[q
]);
674 static int bcm_sysport_poll(struct napi_struct
*napi
, int budget
)
676 struct bcm_sysport_priv
*priv
=
677 container_of(napi
, struct bcm_sysport_priv
, napi
);
678 unsigned int work_done
= 0;
680 work_done
= bcm_sysport_desc_rx(priv
, budget
);
682 priv
->rx_c_index
+= work_done
;
683 priv
->rx_c_index
&= RDMA_CONS_INDEX_MASK
;
684 rdma_writel(priv
, priv
->rx_c_index
, RDMA_CONS_INDEX
);
686 if (work_done
< budget
) {
688 /* re-enable RX interrupts */
689 intrl2_0_mask_clear(priv
, INTRL2_0_RDMA_MBDONE
);
696 /* RX and misc interrupt routine */
697 static irqreturn_t
bcm_sysport_rx_isr(int irq
, void *dev_id
)
699 struct net_device
*dev
= dev_id
;
700 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
702 priv
->irq0_stat
= intrl2_0_readl(priv
, INTRL2_CPU_STATUS
) &
703 ~intrl2_0_readl(priv
, INTRL2_CPU_MASK_STATUS
);
704 intrl2_0_writel(priv
, priv
->irq0_stat
, INTRL2_CPU_CLEAR
);
706 if (unlikely(priv
->irq0_stat
== 0)) {
707 netdev_warn(priv
->netdev
, "spurious RX interrupt\n");
711 if (priv
->irq0_stat
& INTRL2_0_RDMA_MBDONE
) {
712 if (likely(napi_schedule_prep(&priv
->napi
))) {
713 /* disable RX interrupts */
714 intrl2_0_mask_set(priv
, INTRL2_0_RDMA_MBDONE
);
715 __napi_schedule(&priv
->napi
);
719 /* TX ring is full, perform a full reclaim since we do not know
720 * which one would trigger this interrupt
722 if (priv
->irq0_stat
& INTRL2_0_TX_RING_FULL
)
723 bcm_sysport_tx_reclaim_all(priv
);
728 /* TX interrupt service routine */
729 static irqreturn_t
bcm_sysport_tx_isr(int irq
, void *dev_id
)
731 struct net_device
*dev
= dev_id
;
732 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
733 struct bcm_sysport_tx_ring
*txr
;
736 priv
->irq1_stat
= intrl2_1_readl(priv
, INTRL2_CPU_STATUS
) &
737 ~intrl2_1_readl(priv
, INTRL2_CPU_MASK_STATUS
);
738 intrl2_1_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
740 if (unlikely(priv
->irq1_stat
== 0)) {
741 netdev_warn(priv
->netdev
, "spurious TX interrupt\n");
745 for (ring
= 0; ring
< dev
->num_tx_queues
; ring
++) {
746 if (!(priv
->irq1_stat
& BIT(ring
)))
749 txr
= &priv
->tx_rings
[ring
];
751 if (likely(napi_schedule_prep(&txr
->napi
))) {
752 intrl2_1_mask_set(priv
, BIT(ring
));
753 __napi_schedule(&txr
->napi
);
760 static int bcm_sysport_insert_tsb(struct sk_buff
*skb
, struct net_device
*dev
)
762 struct sk_buff
*nskb
;
769 /* Re-allocate SKB if needed */
770 if (unlikely(skb_headroom(skb
) < sizeof(*tsb
))) {
771 nskb
= skb_realloc_headroom(skb
, sizeof(*tsb
));
774 dev
->stats
.tx_errors
++;
775 dev
->stats
.tx_dropped
++;
781 tsb
= (struct bcm_tsb
*)skb_push(skb
, sizeof(*tsb
));
782 /* Zero-out TSB by default */
783 memset(tsb
, 0, sizeof(*tsb
));
785 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
786 ip_ver
= htons(skb
->protocol
);
789 ip_proto
= ip_hdr(skb
)->protocol
;
792 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
798 /* Get the checksum offset and the L4 (transport) offset */
799 csum_start
= skb_checksum_start_offset(skb
) - sizeof(*tsb
);
800 csum_info
= (csum_start
+ skb
->csum_offset
) & L4_CSUM_PTR_MASK
;
801 csum_info
|= (csum_start
<< L4_PTR_SHIFT
);
803 if (ip_proto
== IPPROTO_TCP
|| ip_proto
== IPPROTO_UDP
) {
804 csum_info
|= L4_LENGTH_VALID
;
805 if (ip_proto
== IPPROTO_UDP
&& ip_ver
== ETH_P_IP
)
810 tsb
->l4_ptr_dest_map
= csum_info
;
816 static netdev_tx_t
bcm_sysport_xmit(struct sk_buff
*skb
,
817 struct net_device
*dev
)
819 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
820 struct device
*kdev
= &priv
->pdev
->dev
;
821 struct bcm_sysport_tx_ring
*ring
;
822 struct bcm_sysport_cb
*cb
;
823 struct netdev_queue
*txq
;
824 struct dma_desc
*desc
;
825 unsigned int skb_len
;
832 queue
= skb_get_queue_mapping(skb
);
833 txq
= netdev_get_tx_queue(dev
, queue
);
834 ring
= &priv
->tx_rings
[queue
];
836 /* lock against tx reclaim in BH context and TX ring full interrupt */
837 spin_lock_irqsave(&ring
->lock
, flags
);
838 if (unlikely(ring
->desc_count
== 0)) {
839 netif_tx_stop_queue(txq
);
840 netdev_err(dev
, "queue %d awake and ring full!\n", queue
);
841 ret
= NETDEV_TX_BUSY
;
845 /* Insert TSB and checksum infos */
847 ret
= bcm_sysport_insert_tsb(skb
, dev
);
854 /* The Ethernet switch we are interfaced with needs packets to be at
855 * least 64 bytes (including FCS) otherwise they will be discarded when
856 * they enter the switch port logic. When Broadcom tags are enabled, we
857 * need to make sure that packets are at least 68 bytes
858 * (including FCS and tag) because the length verification is done after
859 * the Broadcom tag is stripped off the ingress packet.
861 if (skb_padto(skb
, ETH_ZLEN
+ ENET_BRCM_TAG_LEN
)) {
866 skb_len
= skb
->len
< ETH_ZLEN
+ ENET_BRCM_TAG_LEN
?
867 ETH_ZLEN
+ ENET_BRCM_TAG_LEN
: skb
->len
;
869 mapping
= dma_map_single(kdev
, skb
->data
, skb_len
, DMA_TO_DEVICE
);
870 if (dma_mapping_error(kdev
, mapping
)) {
871 netif_err(priv
, tx_err
, dev
, "DMA map failed at %p (len=%d)\n",
877 /* Remember the SKB for future freeing */
878 cb
= &ring
->cbs
[ring
->curr_desc
];
880 dma_unmap_addr_set(cb
, dma_addr
, mapping
);
881 dma_unmap_len_set(cb
, dma_len
, skb_len
);
883 /* Fetch a descriptor entry from our pool */
884 desc
= ring
->desc_cpu
;
886 desc
->addr_lo
= lower_32_bits(mapping
);
887 len_status
= upper_32_bits(mapping
) & DESC_ADDR_HI_MASK
;
888 len_status
|= (skb_len
<< DESC_LEN_SHIFT
);
889 len_status
|= (DESC_SOP
| DESC_EOP
| TX_STATUS_APP_CRC
) <<
891 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
892 len_status
|= (DESC_L4_CSUM
<< DESC_STATUS_SHIFT
);
895 if (ring
->curr_desc
== ring
->size
)
899 /* Ensure write completion of the descriptor status/length
900 * in DRAM before the System Port WRITE_PORT register latches
904 desc
->addr_status_len
= len_status
;
907 /* Write this descriptor address to the RING write port */
908 tdma_port_write_desc_addr(priv
, desc
, ring
->index
);
910 /* Check ring space and update SW control flow */
911 if (ring
->desc_count
== 0)
912 netif_tx_stop_queue(txq
);
914 netif_dbg(priv
, tx_queued
, dev
, "ring=%d desc_count=%d, curr_desc=%d\n",
915 ring
->index
, ring
->desc_count
, ring
->curr_desc
);
919 spin_unlock_irqrestore(&ring
->lock
, flags
);
923 static void bcm_sysport_tx_timeout(struct net_device
*dev
)
925 netdev_warn(dev
, "transmit timeout!\n");
927 dev
->trans_start
= jiffies
;
928 dev
->stats
.tx_errors
++;
930 netif_tx_wake_all_queues(dev
);
933 /* phylib adjust link callback */
934 static void bcm_sysport_adj_link(struct net_device
*dev
)
936 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
937 struct phy_device
*phydev
= priv
->phydev
;
938 unsigned int changed
= 0;
939 u32 cmd_bits
= 0, reg
;
941 if (priv
->old_link
!= phydev
->link
) {
943 priv
->old_link
= phydev
->link
;
946 if (priv
->old_duplex
!= phydev
->duplex
) {
948 priv
->old_duplex
= phydev
->duplex
;
951 switch (phydev
->speed
) {
953 cmd_bits
= CMD_SPEED_2500
;
956 cmd_bits
= CMD_SPEED_1000
;
959 cmd_bits
= CMD_SPEED_100
;
962 cmd_bits
= CMD_SPEED_10
;
967 cmd_bits
<<= CMD_SPEED_SHIFT
;
969 if (phydev
->duplex
== DUPLEX_HALF
)
970 cmd_bits
|= CMD_HD_EN
;
972 if (priv
->old_pause
!= phydev
->pause
) {
974 priv
->old_pause
= phydev
->pause
;
978 cmd_bits
|= CMD_RX_PAUSE_IGNORE
| CMD_TX_PAUSE_IGNORE
;
981 reg
= umac_readl(priv
, UMAC_CMD
);
982 reg
&= ~((CMD_SPEED_MASK
<< CMD_SPEED_SHIFT
) |
983 CMD_HD_EN
| CMD_RX_PAUSE_IGNORE
|
984 CMD_TX_PAUSE_IGNORE
);
986 umac_writel(priv
, reg
, UMAC_CMD
);
988 phy_print_status(priv
->phydev
);
992 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv
*priv
,
995 struct bcm_sysport_tx_ring
*ring
= &priv
->tx_rings
[index
];
996 struct device
*kdev
= &priv
->pdev
->dev
;
1001 /* Simple descriptors partitioning for now */
1004 /* We just need one DMA descriptor which is DMA-able, since writing to
1005 * the port will allocate a new descriptor in its internal linked-list
1007 p
= dma_zalloc_coherent(kdev
, 1, &ring
->desc_dma
, GFP_KERNEL
);
1009 netif_err(priv
, hw
, priv
->netdev
, "DMA alloc failed\n");
1013 ring
->cbs
= kzalloc(sizeof(struct bcm_sysport_cb
) * size
, GFP_KERNEL
);
1015 netif_err(priv
, hw
, priv
->netdev
, "CB allocation failed\n");
1019 /* Initialize SW view of the ring */
1020 spin_lock_init(&ring
->lock
);
1022 netif_napi_add(priv
->netdev
, &ring
->napi
, bcm_sysport_tx_poll
, 64);
1023 ring
->index
= index
;
1025 ring
->alloc_size
= ring
->size
;
1027 ring
->desc_count
= ring
->size
;
1028 ring
->curr_desc
= 0;
1030 /* Initialize HW ring */
1031 tdma_writel(priv
, RING_EN
, TDMA_DESC_RING_HEAD_TAIL_PTR(index
));
1032 tdma_writel(priv
, 0, TDMA_DESC_RING_COUNT(index
));
1033 tdma_writel(priv
, 1, TDMA_DESC_RING_INTR_CONTROL(index
));
1034 tdma_writel(priv
, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index
));
1035 tdma_writel(priv
, RING_IGNORE_STATUS
, TDMA_DESC_RING_MAPPING(index
));
1036 tdma_writel(priv
, 0, TDMA_DESC_RING_PCP_DEI_VID(index
));
1038 /* Program the number of descriptors as MAX_THRESHOLD and half of
1039 * its size for the hysteresis trigger
1041 tdma_writel(priv
, ring
->size
|
1042 1 << RING_HYST_THRESH_SHIFT
,
1043 TDMA_DESC_RING_MAX_HYST(index
));
1045 /* Enable the ring queue in the arbiter */
1046 reg
= tdma_readl(priv
, TDMA_TIER1_ARB_0_QUEUE_EN
);
1047 reg
|= (1 << index
);
1048 tdma_writel(priv
, reg
, TDMA_TIER1_ARB_0_QUEUE_EN
);
1050 napi_enable(&ring
->napi
);
1052 netif_dbg(priv
, hw
, priv
->netdev
,
1053 "TDMA cfg, size=%d, desc_cpu=%p\n",
1054 ring
->size
, ring
->desc_cpu
);
1059 static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv
*priv
,
1062 struct bcm_sysport_tx_ring
*ring
= &priv
->tx_rings
[index
];
1063 struct device
*kdev
= &priv
->pdev
->dev
;
1066 /* Caller should stop the TDMA engine */
1067 reg
= tdma_readl(priv
, TDMA_STATUS
);
1068 if (!(reg
& TDMA_DISABLED
))
1069 netdev_warn(priv
->netdev
, "TDMA not stopped!\n");
1071 napi_disable(&ring
->napi
);
1072 netif_napi_del(&ring
->napi
);
1074 bcm_sysport_tx_reclaim(priv
, ring
);
1079 if (ring
->desc_dma
) {
1080 dma_free_coherent(kdev
, 1, ring
->desc_cpu
, ring
->desc_dma
);
1084 ring
->alloc_size
= 0;
1086 netif_dbg(priv
, hw
, priv
->netdev
, "TDMA fini done\n");
1090 static inline int rdma_enable_set(struct bcm_sysport_priv
*priv
,
1091 unsigned int enable
)
1093 unsigned int timeout
= 1000;
1096 reg
= rdma_readl(priv
, RDMA_CONTROL
);
1101 rdma_writel(priv
, reg
, RDMA_CONTROL
);
1103 /* Poll for RMDA disabling completion */
1105 reg
= rdma_readl(priv
, RDMA_STATUS
);
1106 if (!!(reg
& RDMA_DISABLED
) == !enable
)
1108 usleep_range(1000, 2000);
1109 } while (timeout
-- > 0);
1111 netdev_err(priv
->netdev
, "timeout waiting for RDMA to finish\n");
1117 static inline int tdma_enable_set(struct bcm_sysport_priv
*priv
,
1118 unsigned int enable
)
1120 unsigned int timeout
= 1000;
1123 reg
= tdma_readl(priv
, TDMA_CONTROL
);
1128 tdma_writel(priv
, reg
, TDMA_CONTROL
);
1130 /* Poll for TMDA disabling completion */
1132 reg
= tdma_readl(priv
, TDMA_STATUS
);
1133 if (!!(reg
& TDMA_DISABLED
) == !enable
)
1136 usleep_range(1000, 2000);
1137 } while (timeout
-- > 0);
1139 netdev_err(priv
->netdev
, "timeout waiting for TDMA to finish\n");
1144 static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv
*priv
)
1149 /* Initialize SW view of the RX ring */
1150 priv
->num_rx_bds
= NUM_RX_DESC
;
1151 priv
->rx_bds
= priv
->base
+ SYS_PORT_RDMA_OFFSET
;
1152 priv
->rx_bd_assign_ptr
= priv
->rx_bds
;
1153 priv
->rx_bd_assign_index
= 0;
1154 priv
->rx_c_index
= 0;
1155 priv
->rx_read_ptr
= 0;
1156 priv
->rx_cbs
= kzalloc(priv
->num_rx_bds
*
1157 sizeof(struct bcm_sysport_cb
), GFP_KERNEL
);
1158 if (!priv
->rx_cbs
) {
1159 netif_err(priv
, hw
, priv
->netdev
, "CB allocation failed\n");
1163 ret
= bcm_sysport_alloc_rx_bufs(priv
);
1165 netif_err(priv
, hw
, priv
->netdev
, "SKB allocation failed\n");
1169 /* Initialize HW, ensure RDMA is disabled */
1170 reg
= rdma_readl(priv
, RDMA_STATUS
);
1171 if (!(reg
& RDMA_DISABLED
))
1172 rdma_enable_set(priv
, 0);
1174 rdma_writel(priv
, 0, RDMA_WRITE_PTR_LO
);
1175 rdma_writel(priv
, 0, RDMA_WRITE_PTR_HI
);
1176 rdma_writel(priv
, 0, RDMA_PROD_INDEX
);
1177 rdma_writel(priv
, 0, RDMA_CONS_INDEX
);
1178 rdma_writel(priv
, priv
->num_rx_bds
<< RDMA_RING_SIZE_SHIFT
|
1179 RX_BUF_LENGTH
, RDMA_RING_BUF_SIZE
);
1180 /* Operate the queue in ring mode */
1181 rdma_writel(priv
, 0, RDMA_START_ADDR_HI
);
1182 rdma_writel(priv
, 0, RDMA_START_ADDR_LO
);
1183 rdma_writel(priv
, 0, RDMA_END_ADDR_HI
);
1184 rdma_writel(priv
, NUM_HW_RX_DESC_WORDS
- 1, RDMA_END_ADDR_LO
);
1186 rdma_writel(priv
, 1, RDMA_MBDONE_INTR
);
1188 netif_dbg(priv
, hw
, priv
->netdev
,
1189 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
1190 priv
->num_rx_bds
, priv
->rx_bds
);
1195 static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv
*priv
)
1197 struct bcm_sysport_cb
*cb
;
1201 /* Caller should ensure RDMA is disabled */
1202 reg
= rdma_readl(priv
, RDMA_STATUS
);
1203 if (!(reg
& RDMA_DISABLED
))
1204 netdev_warn(priv
->netdev
, "RDMA not stopped!\n");
1206 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
1207 cb
= &priv
->rx_cbs
[i
];
1208 if (dma_unmap_addr(cb
, dma_addr
))
1209 dma_unmap_single(&priv
->pdev
->dev
,
1210 dma_unmap_addr(cb
, dma_addr
),
1211 RX_BUF_LENGTH
, DMA_FROM_DEVICE
);
1212 bcm_sysport_free_cb(cb
);
1215 kfree(priv
->rx_cbs
);
1216 priv
->rx_cbs
= NULL
;
1218 netif_dbg(priv
, hw
, priv
->netdev
, "RDMA fini done\n");
1221 static void bcm_sysport_set_rx_mode(struct net_device
*dev
)
1223 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
1226 reg
= umac_readl(priv
, UMAC_CMD
);
1227 if (dev
->flags
& IFF_PROMISC
)
1230 reg
&= ~CMD_PROMISC
;
1231 umac_writel(priv
, reg
, UMAC_CMD
);
1233 /* No support for ALLMULTI */
1234 if (dev
->flags
& IFF_ALLMULTI
)
1238 static inline void umac_enable_set(struct bcm_sysport_priv
*priv
,
1239 unsigned int enable
)
1243 reg
= umac_readl(priv
, UMAC_CMD
);
1245 reg
|= CMD_RX_EN
| CMD_TX_EN
;
1247 reg
&= ~(CMD_RX_EN
| CMD_TX_EN
);
1248 umac_writel(priv
, reg
, UMAC_CMD
);
1250 /* UniMAC stops on a packet boundary, wait for a full-sized packet
1251 * to be processed (1 msec).
1254 usleep_range(1000, 2000);
1257 static inline int umac_reset(struct bcm_sysport_priv
*priv
)
1259 unsigned int timeout
= 0;
1263 umac_writel(priv
, 0, UMAC_CMD
);
1264 while (timeout
++ < 1000) {
1265 reg
= umac_readl(priv
, UMAC_CMD
);
1266 if (!(reg
& CMD_SW_RESET
))
1272 if (timeout
== 1000) {
1273 dev_err(&priv
->pdev
->dev
,
1274 "timeout waiting for MAC to come out of reset\n");
1281 static void umac_set_hw_addr(struct bcm_sysport_priv
*priv
,
1282 unsigned char *addr
)
1284 umac_writel(priv
, (addr
[0] << 24) | (addr
[1] << 16) |
1285 (addr
[2] << 8) | addr
[3], UMAC_MAC0
);
1286 umac_writel(priv
, (addr
[4] << 8) | addr
[5], UMAC_MAC1
);
1289 static void topctrl_flush(struct bcm_sysport_priv
*priv
)
1291 topctrl_writel(priv
, RX_FLUSH
, RX_FLUSH_CNTL
);
1292 topctrl_writel(priv
, TX_FLUSH
, TX_FLUSH_CNTL
);
1294 topctrl_writel(priv
, 0, RX_FLUSH_CNTL
);
1295 topctrl_writel(priv
, 0, TX_FLUSH_CNTL
);
1298 static int bcm_sysport_open(struct net_device
*dev
)
1300 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
1306 ret
= umac_reset(priv
);
1308 netdev_err(dev
, "UniMAC reset failed\n");
1312 /* Flush TX and RX FIFOs at TOPCTRL level */
1313 topctrl_flush(priv
);
1315 /* Disable the UniMAC RX/TX */
1316 umac_enable_set(priv
, 0);
1318 /* Enable RBUF 2bytes alignment and Receive Status Block */
1319 reg
= rbuf_readl(priv
, RBUF_CONTROL
);
1320 reg
|= RBUF_4B_ALGN
| RBUF_RSB_EN
;
1321 rbuf_writel(priv
, reg
, RBUF_CONTROL
);
1323 /* Set maximum frame length */
1324 umac_writel(priv
, UMAC_MAX_MTU_SIZE
, UMAC_MAX_FRAME_LEN
);
1326 /* Set MAC address */
1327 umac_set_hw_addr(priv
, dev
->dev_addr
);
1329 /* Read CRC forward */
1330 priv
->crc_fwd
= !!(umac_readl(priv
, UMAC_CMD
) & CMD_CRC_FWD
);
1332 priv
->phydev
= of_phy_connect(dev
, priv
->phy_dn
, bcm_sysport_adj_link
,
1333 0, priv
->phy_interface
);
1334 if (!priv
->phydev
) {
1335 netdev_err(dev
, "could not attach to PHY\n");
1339 /* Reset house keeping link status */
1340 priv
->old_duplex
= -1;
1341 priv
->old_link
= -1;
1342 priv
->old_pause
= -1;
1344 /* mask all interrupts and request them */
1345 intrl2_0_writel(priv
, 0xffffffff, INTRL2_CPU_MASK_SET
);
1346 intrl2_0_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
1347 intrl2_0_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1348 intrl2_1_writel(priv
, 0xffffffff, INTRL2_CPU_MASK_SET
);
1349 intrl2_1_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
1350 intrl2_1_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1352 ret
= request_irq(priv
->irq0
, bcm_sysport_rx_isr
, 0, dev
->name
, dev
);
1354 netdev_err(dev
, "failed to request RX interrupt\n");
1355 goto out_phy_disconnect
;
1358 ret
= request_irq(priv
->irq1
, bcm_sysport_tx_isr
, 0, dev
->name
, dev
);
1360 netdev_err(dev
, "failed to request TX interrupt\n");
1364 /* Initialize both hardware and software ring */
1365 for (i
= 0; i
< dev
->num_tx_queues
; i
++) {
1366 ret
= bcm_sysport_init_tx_ring(priv
, i
);
1368 netdev_err(dev
, "failed to initialize TX ring %d\n",
1370 goto out_free_tx_ring
;
1374 /* Initialize linked-list */
1375 tdma_writel(priv
, TDMA_LL_RAM_INIT_BUSY
, TDMA_STATUS
);
1377 /* Initialize RX ring */
1378 ret
= bcm_sysport_init_rx_ring(priv
);
1380 netdev_err(dev
, "failed to initialize RX ring\n");
1381 goto out_free_rx_ring
;
1385 ret
= rdma_enable_set(priv
, 1);
1387 goto out_free_rx_ring
;
1389 /* Enable RX interrupt and TX ring full interrupt */
1390 intrl2_0_mask_clear(priv
, INTRL2_0_RDMA_MBDONE
| INTRL2_0_TX_RING_FULL
);
1393 ret
= tdma_enable_set(priv
, 1);
1395 goto out_clear_rx_int
;
1398 napi_enable(&priv
->napi
);
1400 /* Turn on UniMAC TX/RX */
1401 umac_enable_set(priv
, 1);
1403 phy_start(priv
->phydev
);
1405 /* Enable TX interrupts for the 32 TXQs */
1406 intrl2_1_mask_clear(priv
, 0xffffffff);
1408 /* Last call before we start the real business */
1409 netif_tx_start_all_queues(dev
);
1414 intrl2_0_mask_set(priv
, INTRL2_0_RDMA_MBDONE
| INTRL2_0_TX_RING_FULL
);
1416 bcm_sysport_fini_rx_ring(priv
);
1418 for (i
= 0; i
< dev
->num_tx_queues
; i
++)
1419 bcm_sysport_fini_tx_ring(priv
, i
);
1420 free_irq(priv
->irq1
, dev
);
1422 free_irq(priv
->irq0
, dev
);
1424 phy_disconnect(priv
->phydev
);
1428 static int bcm_sysport_stop(struct net_device
*dev
)
1430 struct bcm_sysport_priv
*priv
= netdev_priv(dev
);
1435 /* stop all software from updating hardware */
1436 netif_tx_stop_all_queues(dev
);
1437 napi_disable(&priv
->napi
);
1438 phy_stop(priv
->phydev
);
1440 /* mask all interrupts */
1441 intrl2_0_mask_set(priv
, 0xffffffff);
1442 intrl2_0_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
1443 intrl2_1_mask_set(priv
, 0xffffffff);
1444 intrl2_1_writel(priv
, 0xffffffff, INTRL2_CPU_CLEAR
);
1446 /* Disable UniMAC RX */
1447 reg
= umac_readl(priv
, UMAC_CMD
);
1449 umac_writel(priv
, reg
, UMAC_CMD
);
1451 ret
= tdma_enable_set(priv
, 0);
1453 netdev_err(dev
, "timeout disabling RDMA\n");
1457 /* Wait for a maximum packet size to be drained */
1458 usleep_range(2000, 3000);
1460 ret
= rdma_enable_set(priv
, 0);
1462 netdev_err(dev
, "timeout disabling TDMA\n");
1466 /* Disable UniMAC TX */
1467 reg
= umac_readl(priv
, UMAC_CMD
);
1469 umac_writel(priv
, reg
, UMAC_CMD
);
1471 /* Free RX/TX rings SW structures */
1472 for (i
= 0; i
< dev
->num_tx_queues
; i
++)
1473 bcm_sysport_fini_tx_ring(priv
, i
);
1474 bcm_sysport_fini_rx_ring(priv
);
1476 free_irq(priv
->irq0
, dev
);
1477 free_irq(priv
->irq1
, dev
);
1479 /* Disconnect from PHY */
1480 phy_disconnect(priv
->phydev
);
1485 static struct ethtool_ops bcm_sysport_ethtool_ops
= {
1486 .get_settings
= bcm_sysport_get_settings
,
1487 .set_settings
= bcm_sysport_set_settings
,
1488 .get_drvinfo
= bcm_sysport_get_drvinfo
,
1489 .get_msglevel
= bcm_sysport_get_msglvl
,
1490 .set_msglevel
= bcm_sysport_set_msglvl
,
1491 .get_link
= ethtool_op_get_link
,
1492 .get_strings
= bcm_sysport_get_strings
,
1493 .get_ethtool_stats
= bcm_sysport_get_stats
,
1494 .get_sset_count
= bcm_sysport_get_sset_count
,
1497 static const struct net_device_ops bcm_sysport_netdev_ops
= {
1498 .ndo_start_xmit
= bcm_sysport_xmit
,
1499 .ndo_tx_timeout
= bcm_sysport_tx_timeout
,
1500 .ndo_open
= bcm_sysport_open
,
1501 .ndo_stop
= bcm_sysport_stop
,
1502 .ndo_set_features
= bcm_sysport_set_features
,
1503 .ndo_set_rx_mode
= bcm_sysport_set_rx_mode
,
1506 #define REV_FMT "v%2x.%02x"
1508 static int bcm_sysport_probe(struct platform_device
*pdev
)
1510 struct bcm_sysport_priv
*priv
;
1511 struct device_node
*dn
;
1512 struct net_device
*dev
;
1513 const void *macaddr
;
1518 dn
= pdev
->dev
.of_node
;
1519 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1521 /* Read the Transmit/Receive Queue properties */
1522 if (of_property_read_u32(dn
, "systemport,num-txq", &txq
))
1523 txq
= TDMA_NUM_RINGS
;
1524 if (of_property_read_u32(dn
, "systemport,num-rxq", &rxq
))
1527 dev
= alloc_etherdev_mqs(sizeof(*priv
), txq
, rxq
);
1531 /* Initialize private members */
1532 priv
= netdev_priv(dev
);
1534 priv
->irq0
= platform_get_irq(pdev
, 0);
1535 priv
->irq1
= platform_get_irq(pdev
, 1);
1536 if (priv
->irq0
<= 0 || priv
->irq1
<= 0) {
1537 dev_err(&pdev
->dev
, "invalid interrupts\n");
1542 priv
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
1543 if (IS_ERR(priv
->base
)) {
1544 ret
= PTR_ERR(priv
->base
);
1551 priv
->phy_interface
= of_get_phy_mode(dn
);
1552 /* Default to GMII interface mode */
1553 if (priv
->phy_interface
< 0)
1554 priv
->phy_interface
= PHY_INTERFACE_MODE_GMII
;
1556 /* In the case of a fixed PHY, the DT node associated
1557 * to the PHY is the Ethernet MAC DT node.
1559 if (of_phy_is_fixed_link(dn
)) {
1560 ret
= of_phy_register_fixed_link(dn
);
1562 dev_err(&pdev
->dev
, "failed to register fixed PHY\n");
1569 /* Initialize netdevice members */
1570 macaddr
= of_get_mac_address(dn
);
1571 if (!macaddr
|| !is_valid_ether_addr(macaddr
)) {
1572 dev_warn(&pdev
->dev
, "using random Ethernet MAC\n");
1573 random_ether_addr(dev
->dev_addr
);
1575 ether_addr_copy(dev
->dev_addr
, macaddr
);
1578 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1579 dev_set_drvdata(&pdev
->dev
, dev
);
1580 dev
->ethtool_ops
= &bcm_sysport_ethtool_ops
;
1581 dev
->netdev_ops
= &bcm_sysport_netdev_ops
;
1582 netif_napi_add(dev
, &priv
->napi
, bcm_sysport_poll
, 64);
1584 /* HW supported features, none enabled by default */
1585 dev
->hw_features
|= NETIF_F_RXCSUM
| NETIF_F_HIGHDMA
|
1586 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
;
1588 /* Set the needed headroom once and for all */
1589 BUILD_BUG_ON(sizeof(struct bcm_tsb
) != 8);
1590 dev
->needed_headroom
+= sizeof(struct bcm_tsb
);
1592 /* We are interfaced to a switch which handles the multicast
1593 * filtering for us, so we do not support programming any
1594 * multicast hash table in this Ethernet MAC.
1596 dev
->flags
&= ~IFF_MULTICAST
;
1598 ret
= register_netdev(dev
);
1600 dev_err(&pdev
->dev
, "failed to register net_device\n");
1604 priv
->rev
= topctrl_readl(priv
, REV_CNTL
) & REV_MASK
;
1605 dev_info(&pdev
->dev
,
1606 "Broadcom SYSTEMPORT" REV_FMT
1607 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
1608 (priv
->rev
>> 8) & 0xff, priv
->rev
& 0xff,
1609 priv
->base
, priv
->irq0
, priv
->irq1
, txq
, rxq
);
1617 static int bcm_sysport_remove(struct platform_device
*pdev
)
1619 struct net_device
*dev
= dev_get_drvdata(&pdev
->dev
);
1621 /* Not much to do, ndo_close has been called
1622 * and we use managed allocations
1624 unregister_netdev(dev
);
1626 dev_set_drvdata(&pdev
->dev
, NULL
);
1631 static const struct of_device_id bcm_sysport_of_match
[] = {
1632 { .compatible
= "brcm,systemport-v1.00" },
1633 { .compatible
= "brcm,systemport" },
1637 static struct platform_driver bcm_sysport_driver
= {
1638 .probe
= bcm_sysport_probe
,
1639 .remove
= bcm_sysport_remove
,
1641 .name
= "brcm-systemport",
1642 .owner
= THIS_MODULE
,
1643 .of_match_table
= bcm_sysport_of_match
,
1646 module_platform_driver(bcm_sysport_driver
);
1648 MODULE_AUTHOR("Broadcom Corporation");
1649 MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
1650 MODULE_ALIAS("platform:brcm-systemport");
1651 MODULE_LICENSE("GPL");