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Merge git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bgmac.c
1 /*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9 #include "bgmac.h"
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/bcm47xx_nvram.h>
21
22 static const struct bcma_device_id bgmac_bcma_tbl[] = {
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
25 {},
26 };
27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
28
29 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
30 u32 value, int timeout)
31 {
32 u32 val;
33 int i;
34
35 for (i = 0; i < timeout / 10; i++) {
36 val = bcma_read32(core, reg);
37 if ((val & mask) == value)
38 return true;
39 udelay(10);
40 }
41 pr_err("Timeout waiting for reg 0x%X\n", reg);
42 return false;
43 }
44
45 /**************************************************
46 * DMA
47 **************************************************/
48
49 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
50 {
51 u32 val;
52 int i;
53
54 if (!ring->mmio_base)
55 return;
56
57 /* Suspend DMA TX ring first.
58 * bgmac_wait_value doesn't support waiting for any of few values, so
59 * implement whole loop here.
60 */
61 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
62 BGMAC_DMA_TX_SUSPEND);
63 for (i = 0; i < 10000 / 10; i++) {
64 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
65 val &= BGMAC_DMA_TX_STAT;
66 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
67 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
68 val == BGMAC_DMA_TX_STAT_STOPPED) {
69 i = 0;
70 break;
71 }
72 udelay(10);
73 }
74 if (i)
75 bgmac_err(bgmac, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
76 ring->mmio_base, val);
77
78 /* Remove SUSPEND bit */
79 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
80 if (!bgmac_wait_value(bgmac->core,
81 ring->mmio_base + BGMAC_DMA_TX_STATUS,
82 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
83 10000)) {
84 bgmac_warn(bgmac, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
85 ring->mmio_base);
86 udelay(300);
87 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
88 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
89 bgmac_err(bgmac, "Reset of DMA TX ring 0x%X failed\n",
90 ring->mmio_base);
91 }
92 }
93
94 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
95 struct bgmac_dma_ring *ring)
96 {
97 u32 ctl;
98
99 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
100 if (bgmac->core->id.rev >= 4) {
101 ctl &= ~BGMAC_DMA_TX_BL_MASK;
102 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
103
104 ctl &= ~BGMAC_DMA_TX_MR_MASK;
105 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
106
107 ctl &= ~BGMAC_DMA_TX_PC_MASK;
108 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
109
110 ctl &= ~BGMAC_DMA_TX_PT_MASK;
111 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
112 }
113 ctl |= BGMAC_DMA_TX_ENABLE;
114 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
115 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
116 }
117
118 static void
119 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
120 int i, int len, u32 ctl0)
121 {
122 struct bgmac_slot_info *slot;
123 struct bgmac_dma_desc *dma_desc;
124 u32 ctl1;
125
126 if (i == BGMAC_TX_RING_SLOTS - 1)
127 ctl0 |= BGMAC_DESC_CTL0_EOT;
128
129 ctl1 = len & BGMAC_DESC_CTL1_LEN;
130
131 slot = &ring->slots[i];
132 dma_desc = &ring->cpu_base[i];
133 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
134 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
135 dma_desc->ctl0 = cpu_to_le32(ctl0);
136 dma_desc->ctl1 = cpu_to_le32(ctl1);
137 }
138
139 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
140 struct bgmac_dma_ring *ring,
141 struct sk_buff *skb)
142 {
143 struct device *dma_dev = bgmac->core->dma_dev;
144 struct net_device *net_dev = bgmac->net_dev;
145 int index = ring->end % BGMAC_TX_RING_SLOTS;
146 struct bgmac_slot_info *slot = &ring->slots[index];
147 int nr_frags;
148 u32 flags;
149 int i;
150
151 if (skb->len > BGMAC_DESC_CTL1_LEN) {
152 bgmac_err(bgmac, "Too long skb (%d)\n", skb->len);
153 goto err_drop;
154 }
155
156 if (skb->ip_summed == CHECKSUM_PARTIAL)
157 skb_checksum_help(skb);
158
159 nr_frags = skb_shinfo(skb)->nr_frags;
160
161 /* ring->end - ring->start will return the number of valid slots,
162 * even when ring->end overflows
163 */
164 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
165 bgmac_err(bgmac, "TX ring is full, queue should be stopped!\n");
166 netif_stop_queue(net_dev);
167 return NETDEV_TX_BUSY;
168 }
169
170 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
171 DMA_TO_DEVICE);
172 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
173 goto err_dma_head;
174
175 flags = BGMAC_DESC_CTL0_SOF;
176 if (!nr_frags)
177 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
178
179 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
180 flags = 0;
181
182 for (i = 0; i < nr_frags; i++) {
183 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
184 int len = skb_frag_size(frag);
185
186 index = (index + 1) % BGMAC_TX_RING_SLOTS;
187 slot = &ring->slots[index];
188 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
189 len, DMA_TO_DEVICE);
190 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
191 goto err_dma;
192
193 if (i == nr_frags - 1)
194 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
195
196 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
197 }
198
199 slot->skb = skb;
200 ring->end += nr_frags + 1;
201 netdev_sent_queue(net_dev, skb->len);
202
203 wmb();
204
205 /* Increase ring->end to point empty slot. We tell hardware the first
206 * slot it should *not* read.
207 */
208 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
209 ring->index_base +
210 (ring->end % BGMAC_TX_RING_SLOTS) *
211 sizeof(struct bgmac_dma_desc));
212
213 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
214 netif_stop_queue(net_dev);
215
216 return NETDEV_TX_OK;
217
218 err_dma:
219 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
220 DMA_TO_DEVICE);
221
222 while (i > 0) {
223 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
224 struct bgmac_slot_info *slot = &ring->slots[index];
225 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
226 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
227
228 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
229 }
230
231 err_dma_head:
232 bgmac_err(bgmac, "Mapping error of skb on ring 0x%X\n",
233 ring->mmio_base);
234
235 err_drop:
236 dev_kfree_skb(skb);
237 return NETDEV_TX_OK;
238 }
239
240 /* Free transmitted packets */
241 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
242 {
243 struct device *dma_dev = bgmac->core->dma_dev;
244 int empty_slot;
245 bool freed = false;
246 unsigned bytes_compl = 0, pkts_compl = 0;
247
248 /* The last slot that hardware didn't consume yet */
249 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
250 empty_slot &= BGMAC_DMA_TX_STATDPTR;
251 empty_slot -= ring->index_base;
252 empty_slot &= BGMAC_DMA_TX_STATDPTR;
253 empty_slot /= sizeof(struct bgmac_dma_desc);
254
255 while (ring->start != ring->end) {
256 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
257 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
258 u32 ctl1;
259 int len;
260
261 if (slot_idx == empty_slot)
262 break;
263
264 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
265 len = ctl1 & BGMAC_DESC_CTL1_LEN;
266 if (ctl1 & BGMAC_DESC_CTL0_SOF)
267 /* Unmap no longer used buffer */
268 dma_unmap_single(dma_dev, slot->dma_addr, len,
269 DMA_TO_DEVICE);
270 else
271 dma_unmap_page(dma_dev, slot->dma_addr, len,
272 DMA_TO_DEVICE);
273
274 if (slot->skb) {
275 bytes_compl += slot->skb->len;
276 pkts_compl++;
277
278 /* Free memory! :) */
279 dev_kfree_skb(slot->skb);
280 slot->skb = NULL;
281 }
282
283 slot->dma_addr = 0;
284 ring->start++;
285 freed = true;
286 }
287
288 if (!pkts_compl)
289 return;
290
291 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
292
293 if (netif_queue_stopped(bgmac->net_dev))
294 netif_wake_queue(bgmac->net_dev);
295 }
296
297 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
298 {
299 if (!ring->mmio_base)
300 return;
301
302 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
303 if (!bgmac_wait_value(bgmac->core,
304 ring->mmio_base + BGMAC_DMA_RX_STATUS,
305 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
306 10000))
307 bgmac_err(bgmac, "Reset of ring 0x%X RX failed\n",
308 ring->mmio_base);
309 }
310
311 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
312 struct bgmac_dma_ring *ring)
313 {
314 u32 ctl;
315
316 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
317 if (bgmac->core->id.rev >= 4) {
318 ctl &= ~BGMAC_DMA_RX_BL_MASK;
319 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
320
321 ctl &= ~BGMAC_DMA_RX_PC_MASK;
322 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
323
324 ctl &= ~BGMAC_DMA_RX_PT_MASK;
325 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
326 }
327 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
328 ctl |= BGMAC_DMA_RX_ENABLE;
329 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
330 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
331 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
332 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
333 }
334
335 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
336 struct bgmac_slot_info *slot)
337 {
338 struct device *dma_dev = bgmac->core->dma_dev;
339 dma_addr_t dma_addr;
340 struct bgmac_rx_header *rx;
341 void *buf;
342
343 /* Alloc skb */
344 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
345 if (!buf)
346 return -ENOMEM;
347
348 /* Poison - if everything goes fine, hardware will overwrite it */
349 rx = buf + BGMAC_RX_BUF_OFFSET;
350 rx->len = cpu_to_le16(0xdead);
351 rx->flags = cpu_to_le16(0xbeef);
352
353 /* Map skb for the DMA */
354 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
355 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
356 if (dma_mapping_error(dma_dev, dma_addr)) {
357 bgmac_err(bgmac, "DMA mapping error\n");
358 put_page(virt_to_head_page(buf));
359 return -ENOMEM;
360 }
361
362 /* Update the slot */
363 slot->buf = buf;
364 slot->dma_addr = dma_addr;
365
366 return 0;
367 }
368
369 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
370 struct bgmac_dma_ring *ring)
371 {
372 dma_wmb();
373
374 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
375 ring->index_base +
376 ring->end * sizeof(struct bgmac_dma_desc));
377 }
378
379 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
380 struct bgmac_dma_ring *ring, int desc_idx)
381 {
382 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
383 u32 ctl0 = 0, ctl1 = 0;
384
385 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
386 ctl0 |= BGMAC_DESC_CTL0_EOT;
387 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
388 /* Is there any BGMAC device that requires extension? */
389 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
390 * B43_DMA64_DCTL1_ADDREXT_MASK;
391 */
392
393 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
394 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
395 dma_desc->ctl0 = cpu_to_le32(ctl0);
396 dma_desc->ctl1 = cpu_to_le32(ctl1);
397
398 ring->end = desc_idx;
399 }
400
401 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
402 struct bgmac_slot_info *slot)
403 {
404 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
405
406 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
407 DMA_FROM_DEVICE);
408 rx->len = cpu_to_le16(0xdead);
409 rx->flags = cpu_to_le16(0xbeef);
410 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
411 DMA_FROM_DEVICE);
412 }
413
414 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
415 int weight)
416 {
417 u32 end_slot;
418 int handled = 0;
419
420 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
421 end_slot &= BGMAC_DMA_RX_STATDPTR;
422 end_slot -= ring->index_base;
423 end_slot &= BGMAC_DMA_RX_STATDPTR;
424 end_slot /= sizeof(struct bgmac_dma_desc);
425
426 while (ring->start != end_slot) {
427 struct device *dma_dev = bgmac->core->dma_dev;
428 struct bgmac_slot_info *slot = &ring->slots[ring->start];
429 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
430 struct sk_buff *skb;
431 void *buf = slot->buf;
432 dma_addr_t dma_addr = slot->dma_addr;
433 u16 len, flags;
434
435 do {
436 /* Prepare new skb as replacement */
437 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
438 bgmac_dma_rx_poison_buf(dma_dev, slot);
439 break;
440 }
441
442 /* Unmap buffer to make it accessible to the CPU */
443 dma_unmap_single(dma_dev, dma_addr,
444 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
445
446 /* Get info from the header */
447 len = le16_to_cpu(rx->len);
448 flags = le16_to_cpu(rx->flags);
449
450 /* Check for poison and drop or pass the packet */
451 if (len == 0xdead && flags == 0xbeef) {
452 bgmac_err(bgmac, "Found poisoned packet at slot %d, DMA issue!\n",
453 ring->start);
454 put_page(virt_to_head_page(buf));
455 break;
456 }
457
458 if (len > BGMAC_RX_ALLOC_SIZE) {
459 bgmac_err(bgmac, "Found oversized packet at slot %d, DMA issue!\n",
460 ring->start);
461 put_page(virt_to_head_page(buf));
462 break;
463 }
464
465 /* Omit CRC. */
466 len -= ETH_FCS_LEN;
467
468 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
469 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
470 BGMAC_RX_BUF_OFFSET + len);
471 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
472 BGMAC_RX_BUF_OFFSET);
473
474 skb_checksum_none_assert(skb);
475 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
476 napi_gro_receive(&bgmac->napi, skb);
477 handled++;
478 } while (0);
479
480 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
481
482 if (++ring->start >= BGMAC_RX_RING_SLOTS)
483 ring->start = 0;
484
485 if (handled >= weight) /* Should never be greater */
486 break;
487 }
488
489 bgmac_dma_rx_update_index(bgmac, ring);
490
491 return handled;
492 }
493
494 /* Does ring support unaligned addressing? */
495 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
496 struct bgmac_dma_ring *ring,
497 enum bgmac_dma_ring_type ring_type)
498 {
499 switch (ring_type) {
500 case BGMAC_DMA_RING_TX:
501 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
502 0xff0);
503 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
504 return true;
505 break;
506 case BGMAC_DMA_RING_RX:
507 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
508 0xff0);
509 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
510 return true;
511 break;
512 }
513 return false;
514 }
515
516 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
517 struct bgmac_dma_ring *ring)
518 {
519 struct device *dma_dev = bgmac->core->dma_dev;
520 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
521 struct bgmac_slot_info *slot;
522 int i;
523
524 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
525 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
526
527 slot = &ring->slots[i];
528 dev_kfree_skb(slot->skb);
529
530 if (!slot->dma_addr)
531 continue;
532
533 if (slot->skb)
534 dma_unmap_single(dma_dev, slot->dma_addr,
535 len, DMA_TO_DEVICE);
536 else
537 dma_unmap_page(dma_dev, slot->dma_addr,
538 len, DMA_TO_DEVICE);
539 }
540 }
541
542 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
543 struct bgmac_dma_ring *ring)
544 {
545 struct device *dma_dev = bgmac->core->dma_dev;
546 struct bgmac_slot_info *slot;
547 int i;
548
549 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
550 slot = &ring->slots[i];
551 if (!slot->dma_addr)
552 continue;
553
554 dma_unmap_single(dma_dev, slot->dma_addr,
555 BGMAC_RX_BUF_SIZE,
556 DMA_FROM_DEVICE);
557 put_page(virt_to_head_page(slot->buf));
558 slot->dma_addr = 0;
559 }
560 }
561
562 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
563 struct bgmac_dma_ring *ring,
564 int num_slots)
565 {
566 struct device *dma_dev = bgmac->core->dma_dev;
567 int size;
568
569 if (!ring->cpu_base)
570 return;
571
572 /* Free ring of descriptors */
573 size = num_slots * sizeof(struct bgmac_dma_desc);
574 dma_free_coherent(dma_dev, size, ring->cpu_base,
575 ring->dma_base);
576 }
577
578 static void bgmac_dma_cleanup(struct bgmac *bgmac)
579 {
580 int i;
581
582 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
583 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
584
585 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
586 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
587 }
588
589 static void bgmac_dma_free(struct bgmac *bgmac)
590 {
591 int i;
592
593 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
594 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
595 BGMAC_TX_RING_SLOTS);
596
597 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
598 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
599 BGMAC_RX_RING_SLOTS);
600 }
601
602 static int bgmac_dma_alloc(struct bgmac *bgmac)
603 {
604 struct device *dma_dev = bgmac->core->dma_dev;
605 struct bgmac_dma_ring *ring;
606 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
607 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
608 int size; /* ring size: different for Tx and Rx */
609 int err;
610 int i;
611
612 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
613 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
614
615 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
616 bgmac_err(bgmac, "Core does not report 64-bit DMA\n");
617 return -ENOTSUPP;
618 }
619
620 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
621 ring = &bgmac->tx_ring[i];
622 ring->mmio_base = ring_base[i];
623
624 /* Alloc ring of descriptors */
625 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
626 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
627 &ring->dma_base,
628 GFP_KERNEL);
629 if (!ring->cpu_base) {
630 bgmac_err(bgmac, "Allocation of TX ring 0x%X failed\n",
631 ring->mmio_base);
632 goto err_dma_free;
633 }
634
635 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
636 BGMAC_DMA_RING_TX);
637 if (ring->unaligned)
638 ring->index_base = lower_32_bits(ring->dma_base);
639 else
640 ring->index_base = 0;
641
642 /* No need to alloc TX slots yet */
643 }
644
645 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
646 ring = &bgmac->rx_ring[i];
647 ring->mmio_base = ring_base[i];
648
649 /* Alloc ring of descriptors */
650 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
651 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
652 &ring->dma_base,
653 GFP_KERNEL);
654 if (!ring->cpu_base) {
655 bgmac_err(bgmac, "Allocation of RX ring 0x%X failed\n",
656 ring->mmio_base);
657 err = -ENOMEM;
658 goto err_dma_free;
659 }
660
661 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
662 BGMAC_DMA_RING_RX);
663 if (ring->unaligned)
664 ring->index_base = lower_32_bits(ring->dma_base);
665 else
666 ring->index_base = 0;
667 }
668
669 return 0;
670
671 err_dma_free:
672 bgmac_dma_free(bgmac);
673 return -ENOMEM;
674 }
675
676 static int bgmac_dma_init(struct bgmac *bgmac)
677 {
678 struct bgmac_dma_ring *ring;
679 int i, err;
680
681 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
682 ring = &bgmac->tx_ring[i];
683
684 if (!ring->unaligned)
685 bgmac_dma_tx_enable(bgmac, ring);
686 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
687 lower_32_bits(ring->dma_base));
688 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
689 upper_32_bits(ring->dma_base));
690 if (ring->unaligned)
691 bgmac_dma_tx_enable(bgmac, ring);
692
693 ring->start = 0;
694 ring->end = 0; /* Points the slot that should *not* be read */
695 }
696
697 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
698 int j;
699
700 ring = &bgmac->rx_ring[i];
701
702 if (!ring->unaligned)
703 bgmac_dma_rx_enable(bgmac, ring);
704 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
705 lower_32_bits(ring->dma_base));
706 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
707 upper_32_bits(ring->dma_base));
708 if (ring->unaligned)
709 bgmac_dma_rx_enable(bgmac, ring);
710
711 ring->start = 0;
712 ring->end = 0;
713 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
714 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
715 if (err)
716 goto error;
717
718 bgmac_dma_rx_setup_desc(bgmac, ring, j);
719 }
720
721 bgmac_dma_rx_update_index(bgmac, ring);
722 }
723
724 return 0;
725
726 error:
727 bgmac_dma_cleanup(bgmac);
728 return err;
729 }
730
731 /**************************************************
732 * PHY ops
733 **************************************************/
734
735 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
736 {
737 struct bcma_device *core;
738 u16 phy_access_addr;
739 u16 phy_ctl_addr;
740 u32 tmp;
741
742 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
743 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
744 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
745 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
746 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
747 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
748 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
749 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
750 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
751 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
752 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
753
754 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
755 core = bgmac->core->bus->drv_gmac_cmn.core;
756 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
757 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
758 } else {
759 core = bgmac->core;
760 phy_access_addr = BGMAC_PHY_ACCESS;
761 phy_ctl_addr = BGMAC_PHY_CNTL;
762 }
763
764 tmp = bcma_read32(core, phy_ctl_addr);
765 tmp &= ~BGMAC_PC_EPA_MASK;
766 tmp |= phyaddr;
767 bcma_write32(core, phy_ctl_addr, tmp);
768
769 tmp = BGMAC_PA_START;
770 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
771 tmp |= reg << BGMAC_PA_REG_SHIFT;
772 bcma_write32(core, phy_access_addr, tmp);
773
774 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
775 bgmac_err(bgmac, "Reading PHY %d register 0x%X failed\n",
776 phyaddr, reg);
777 return 0xffff;
778 }
779
780 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
781 }
782
783 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
784 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
785 {
786 struct bcma_device *core;
787 u16 phy_access_addr;
788 u16 phy_ctl_addr;
789 u32 tmp;
790
791 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
792 core = bgmac->core->bus->drv_gmac_cmn.core;
793 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
794 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
795 } else {
796 core = bgmac->core;
797 phy_access_addr = BGMAC_PHY_ACCESS;
798 phy_ctl_addr = BGMAC_PHY_CNTL;
799 }
800
801 tmp = bcma_read32(core, phy_ctl_addr);
802 tmp &= ~BGMAC_PC_EPA_MASK;
803 tmp |= phyaddr;
804 bcma_write32(core, phy_ctl_addr, tmp);
805
806 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
807 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
808 bgmac_warn(bgmac, "Error setting MDIO int\n");
809
810 tmp = BGMAC_PA_START;
811 tmp |= BGMAC_PA_WRITE;
812 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
813 tmp |= reg << BGMAC_PA_REG_SHIFT;
814 tmp |= value;
815 bcma_write32(core, phy_access_addr, tmp);
816
817 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
818 bgmac_err(bgmac, "Writing to PHY %d register 0x%X failed\n",
819 phyaddr, reg);
820 return -ETIMEDOUT;
821 }
822
823 return 0;
824 }
825
826 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
827 static void bgmac_phy_init(struct bgmac *bgmac)
828 {
829 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
830 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
831 u8 i;
832
833 if (ci->id == BCMA_CHIP_ID_BCM5356) {
834 for (i = 0; i < 5; i++) {
835 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
836 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
837 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
838 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
839 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
840 }
841 }
842 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
843 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
844 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
845 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
846 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
847 for (i = 0; i < 5; i++) {
848 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
849 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
850 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
851 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
852 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
853 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
854 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
855 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
856 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
857 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
858 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
859 }
860 }
861 }
862
863 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
864 static void bgmac_phy_reset(struct bgmac *bgmac)
865 {
866 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
867 return;
868
869 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
870 udelay(100);
871 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
872 bgmac_err(bgmac, "PHY reset failed\n");
873 bgmac_phy_init(bgmac);
874 }
875
876 /**************************************************
877 * Chip ops
878 **************************************************/
879
880 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
881 * nothing to change? Try if after stabilizng driver.
882 */
883 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
884 bool force)
885 {
886 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
887 u32 new_val = (cmdcfg & mask) | set;
888
889 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
890 udelay(2);
891
892 if (new_val != cmdcfg || force)
893 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
894
895 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
896 udelay(2);
897 }
898
899 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
900 {
901 u32 tmp;
902
903 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
904 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
905 tmp = (addr[4] << 8) | addr[5];
906 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
907 }
908
909 static void bgmac_set_rx_mode(struct net_device *net_dev)
910 {
911 struct bgmac *bgmac = netdev_priv(net_dev);
912
913 if (net_dev->flags & IFF_PROMISC)
914 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
915 else
916 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
917 }
918
919 #if 0 /* We don't use that regs yet */
920 static void bgmac_chip_stats_update(struct bgmac *bgmac)
921 {
922 int i;
923
924 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
925 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
926 bgmac->mib_tx_regs[i] =
927 bgmac_read(bgmac,
928 BGMAC_TX_GOOD_OCTETS + (i * 4));
929 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
930 bgmac->mib_rx_regs[i] =
931 bgmac_read(bgmac,
932 BGMAC_RX_GOOD_OCTETS + (i * 4));
933 }
934
935 /* TODO: what else? how to handle BCM4706? Specs are needed */
936 }
937 #endif
938
939 static void bgmac_clear_mib(struct bgmac *bgmac)
940 {
941 int i;
942
943 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
944 return;
945
946 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
947 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
948 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
949 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
950 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
951 }
952
953 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
954 static void bgmac_mac_speed(struct bgmac *bgmac)
955 {
956 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
957 u32 set = 0;
958
959 switch (bgmac->mac_speed) {
960 case SPEED_10:
961 set |= BGMAC_CMDCFG_ES_10;
962 break;
963 case SPEED_100:
964 set |= BGMAC_CMDCFG_ES_100;
965 break;
966 case SPEED_1000:
967 set |= BGMAC_CMDCFG_ES_1000;
968 break;
969 case SPEED_2500:
970 set |= BGMAC_CMDCFG_ES_2500;
971 break;
972 default:
973 bgmac_err(bgmac, "Unsupported speed: %d\n", bgmac->mac_speed);
974 }
975
976 if (bgmac->mac_duplex == DUPLEX_HALF)
977 set |= BGMAC_CMDCFG_HD;
978
979 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
980 }
981
982 static void bgmac_miiconfig(struct bgmac *bgmac)
983 {
984 struct bcma_device *core = bgmac->core;
985 struct bcma_chipinfo *ci = &core->bus->chipinfo;
986 u8 imode;
987
988 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
989 ci->id == BCMA_CHIP_ID_BCM53018) {
990 bcma_awrite32(core, BCMA_IOCTL,
991 bcma_aread32(core, BCMA_IOCTL) | 0x40 |
992 BGMAC_BCMA_IOCTL_SW_CLKEN);
993 bgmac->mac_speed = SPEED_2500;
994 bgmac->mac_duplex = DUPLEX_FULL;
995 bgmac_mac_speed(bgmac);
996 } else {
997 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
998 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
999 if (imode == 0 || imode == 1) {
1000 bgmac->mac_speed = SPEED_100;
1001 bgmac->mac_duplex = DUPLEX_FULL;
1002 bgmac_mac_speed(bgmac);
1003 }
1004 }
1005 }
1006
1007 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
1008 static void bgmac_chip_reset(struct bgmac *bgmac)
1009 {
1010 struct bcma_device *core = bgmac->core;
1011 struct bcma_bus *bus = core->bus;
1012 struct bcma_chipinfo *ci = &bus->chipinfo;
1013 u32 flags;
1014 u32 iost;
1015 int i;
1016
1017 if (bcma_core_is_enabled(core)) {
1018 if (!bgmac->stats_grabbed) {
1019 /* bgmac_chip_stats_update(bgmac); */
1020 bgmac->stats_grabbed = true;
1021 }
1022
1023 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
1024 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
1025
1026 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1027 udelay(1);
1028
1029 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
1030 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
1031
1032 /* TODO: Clear software multicast filter list */
1033 }
1034
1035 iost = bcma_aread32(core, BCMA_IOST);
1036 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1037 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1038 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
1039 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
1040
1041 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
1042 if (ci->id != BCMA_CHIP_ID_BCM4707) {
1043 flags = 0;
1044 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
1045 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
1046 if (!bgmac->has_robosw)
1047 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
1048 }
1049 bcma_core_enable(core, flags);
1050 }
1051
1052 /* Request Misc PLL for corerev > 2 */
1053 if (core->id.rev > 2 &&
1054 ci->id != BCMA_CHIP_ID_BCM4707 &&
1055 ci->id != BCMA_CHIP_ID_BCM53018) {
1056 bgmac_set(bgmac, BCMA_CLKCTLST,
1057 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
1058 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
1059 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1060 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1061 1000);
1062 }
1063
1064 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1065 ci->id == BCMA_CHIP_ID_BCM4749 ||
1066 ci->id == BCMA_CHIP_ID_BCM53572) {
1067 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
1068 u8 et_swtype = 0;
1069 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
1070 BGMAC_CHIPCTL_1_IF_TYPE_MII;
1071 char buf[4];
1072
1073 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
1074 if (kstrtou8(buf, 0, &et_swtype))
1075 bgmac_err(bgmac, "Failed to parse et_swtype (%s)\n",
1076 buf);
1077 et_swtype &= 0x0f;
1078 et_swtype <<= 4;
1079 sw_type = et_swtype;
1080 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
1081 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
1082 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1083 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1084 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
1085 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
1086 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
1087 }
1088 bcma_chipco_chipctl_maskset(cc, 1,
1089 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
1090 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
1091 sw_type);
1092 }
1093
1094 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
1095 bcma_awrite32(core, BCMA_IOCTL,
1096 bcma_aread32(core, BCMA_IOCTL) &
1097 ~BGMAC_BCMA_IOCTL_SW_RESET);
1098
1099 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1100 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1101 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1102 * be keps until taking MAC out of the reset.
1103 */
1104 bgmac_cmdcfg_maskset(bgmac,
1105 ~(BGMAC_CMDCFG_TE |
1106 BGMAC_CMDCFG_RE |
1107 BGMAC_CMDCFG_RPI |
1108 BGMAC_CMDCFG_TAI |
1109 BGMAC_CMDCFG_HD |
1110 BGMAC_CMDCFG_ML |
1111 BGMAC_CMDCFG_CFE |
1112 BGMAC_CMDCFG_RL |
1113 BGMAC_CMDCFG_RED |
1114 BGMAC_CMDCFG_PE |
1115 BGMAC_CMDCFG_TPI |
1116 BGMAC_CMDCFG_PAD_EN |
1117 BGMAC_CMDCFG_PF),
1118 BGMAC_CMDCFG_PROM |
1119 BGMAC_CMDCFG_NLC |
1120 BGMAC_CMDCFG_CFE |
1121 BGMAC_CMDCFG_SR(core->id.rev),
1122 false);
1123 bgmac->mac_speed = SPEED_UNKNOWN;
1124 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1125
1126 bgmac_clear_mib(bgmac);
1127 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
1128 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
1129 BCMA_GMAC_CMN_PC_MTE);
1130 else
1131 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1132 bgmac_miiconfig(bgmac);
1133 bgmac_phy_init(bgmac);
1134
1135 netdev_reset_queue(bgmac->net_dev);
1136 }
1137
1138 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1139 {
1140 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1141 }
1142
1143 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1144 {
1145 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1146 bgmac_read(bgmac, BGMAC_INT_MASK);
1147 }
1148
1149 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1150 static void bgmac_enable(struct bgmac *bgmac)
1151 {
1152 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1153 u32 cmdcfg;
1154 u32 mode;
1155 u32 rxq_ctl;
1156 u32 fl_ctl;
1157 u16 bp_clk;
1158 u8 mdp;
1159
1160 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1161 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1162 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
1163 udelay(2);
1164 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1165 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1166
1167 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1168 BGMAC_DS_MM_SHIFT;
1169 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1170 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1171 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1172 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1173 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1174
1175 switch (ci->id) {
1176 case BCMA_CHIP_ID_BCM5357:
1177 case BCMA_CHIP_ID_BCM4749:
1178 case BCMA_CHIP_ID_BCM53572:
1179 case BCMA_CHIP_ID_BCM4716:
1180 case BCMA_CHIP_ID_BCM47162:
1181 fl_ctl = 0x03cb04cb;
1182 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1183 ci->id == BCMA_CHIP_ID_BCM4749 ||
1184 ci->id == BCMA_CHIP_ID_BCM53572)
1185 fl_ctl = 0x2300e1;
1186 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1187 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1188 break;
1189 }
1190
1191 if (ci->id != BCMA_CHIP_ID_BCM4707 &&
1192 ci->id != BCMA_CHIP_ID_BCM53018) {
1193 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1194 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1195 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
1196 1000000;
1197 mdp = (bp_clk * 128 / 1000) - 3;
1198 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1199 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1200 }
1201 }
1202
1203 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1204 static void bgmac_chip_init(struct bgmac *bgmac)
1205 {
1206 /* 1 interrupt per received frame */
1207 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1208
1209 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1210 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1211
1212 bgmac_set_rx_mode(bgmac->net_dev);
1213
1214 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1215
1216 if (bgmac->loopback)
1217 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1218 else
1219 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1220
1221 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1222
1223 bgmac_chip_intrs_on(bgmac);
1224
1225 bgmac_enable(bgmac);
1226 }
1227
1228 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1229 {
1230 struct bgmac *bgmac = netdev_priv(dev_id);
1231
1232 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1233 int_status &= bgmac->int_mask;
1234
1235 if (!int_status)
1236 return IRQ_NONE;
1237
1238 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1239 if (int_status)
1240 bgmac_err(bgmac, "Unknown IRQs: 0x%08X\n", int_status);
1241
1242 /* Disable new interrupts until handling existing ones */
1243 bgmac_chip_intrs_off(bgmac);
1244
1245 napi_schedule(&bgmac->napi);
1246
1247 return IRQ_HANDLED;
1248 }
1249
1250 static int bgmac_poll(struct napi_struct *napi, int weight)
1251 {
1252 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1253 int handled = 0;
1254
1255 /* Ack */
1256 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1257
1258 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1259 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1260
1261 /* Poll again if more events arrived in the meantime */
1262 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1263 return weight;
1264
1265 if (handled < weight) {
1266 napi_complete(napi);
1267 bgmac_chip_intrs_on(bgmac);
1268 }
1269
1270 return handled;
1271 }
1272
1273 /**************************************************
1274 * net_device_ops
1275 **************************************************/
1276
1277 static int bgmac_open(struct net_device *net_dev)
1278 {
1279 struct bgmac *bgmac = netdev_priv(net_dev);
1280 int err = 0;
1281
1282 bgmac_chip_reset(bgmac);
1283
1284 err = bgmac_dma_init(bgmac);
1285 if (err)
1286 return err;
1287
1288 /* Specs say about reclaiming rings here, but we do that in DMA init */
1289 bgmac_chip_init(bgmac);
1290
1291 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1292 KBUILD_MODNAME, net_dev);
1293 if (err < 0) {
1294 bgmac_err(bgmac, "IRQ request error: %d!\n", err);
1295 bgmac_dma_cleanup(bgmac);
1296 return err;
1297 }
1298 napi_enable(&bgmac->napi);
1299
1300 phy_start(bgmac->phy_dev);
1301
1302 netif_carrier_on(net_dev);
1303 return 0;
1304 }
1305
1306 static int bgmac_stop(struct net_device *net_dev)
1307 {
1308 struct bgmac *bgmac = netdev_priv(net_dev);
1309
1310 netif_carrier_off(net_dev);
1311
1312 phy_stop(bgmac->phy_dev);
1313
1314 napi_disable(&bgmac->napi);
1315 bgmac_chip_intrs_off(bgmac);
1316 free_irq(bgmac->core->irq, net_dev);
1317
1318 bgmac_chip_reset(bgmac);
1319 bgmac_dma_cleanup(bgmac);
1320
1321 return 0;
1322 }
1323
1324 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1325 struct net_device *net_dev)
1326 {
1327 struct bgmac *bgmac = netdev_priv(net_dev);
1328 struct bgmac_dma_ring *ring;
1329
1330 /* No QOS support yet */
1331 ring = &bgmac->tx_ring[0];
1332 return bgmac_dma_tx_add(bgmac, ring, skb);
1333 }
1334
1335 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1336 {
1337 struct bgmac *bgmac = netdev_priv(net_dev);
1338 int ret;
1339
1340 ret = eth_prepare_mac_addr_change(net_dev, addr);
1341 if (ret < 0)
1342 return ret;
1343 bgmac_write_mac_address(bgmac, (u8 *)addr);
1344 eth_commit_mac_addr_change(net_dev, addr);
1345 return 0;
1346 }
1347
1348 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1349 {
1350 struct bgmac *bgmac = netdev_priv(net_dev);
1351
1352 if (!netif_running(net_dev))
1353 return -EINVAL;
1354
1355 return phy_mii_ioctl(bgmac->phy_dev, ifr, cmd);
1356 }
1357
1358 static const struct net_device_ops bgmac_netdev_ops = {
1359 .ndo_open = bgmac_open,
1360 .ndo_stop = bgmac_stop,
1361 .ndo_start_xmit = bgmac_start_xmit,
1362 .ndo_set_rx_mode = bgmac_set_rx_mode,
1363 .ndo_set_mac_address = bgmac_set_mac_address,
1364 .ndo_validate_addr = eth_validate_addr,
1365 .ndo_do_ioctl = bgmac_ioctl,
1366 };
1367
1368 /**************************************************
1369 * ethtool_ops
1370 **************************************************/
1371
1372 static int bgmac_get_settings(struct net_device *net_dev,
1373 struct ethtool_cmd *cmd)
1374 {
1375 struct bgmac *bgmac = netdev_priv(net_dev);
1376
1377 return phy_ethtool_gset(bgmac->phy_dev, cmd);
1378 }
1379
1380 static int bgmac_set_settings(struct net_device *net_dev,
1381 struct ethtool_cmd *cmd)
1382 {
1383 struct bgmac *bgmac = netdev_priv(net_dev);
1384
1385 return phy_ethtool_sset(bgmac->phy_dev, cmd);
1386 }
1387
1388 static void bgmac_get_drvinfo(struct net_device *net_dev,
1389 struct ethtool_drvinfo *info)
1390 {
1391 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1392 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1393 }
1394
1395 static const struct ethtool_ops bgmac_ethtool_ops = {
1396 .get_settings = bgmac_get_settings,
1397 .set_settings = bgmac_set_settings,
1398 .get_drvinfo = bgmac_get_drvinfo,
1399 };
1400
1401 /**************************************************
1402 * MII
1403 **************************************************/
1404
1405 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1406 {
1407 return bgmac_phy_read(bus->priv, mii_id, regnum);
1408 }
1409
1410 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1411 u16 value)
1412 {
1413 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1414 }
1415
1416 static void bgmac_adjust_link(struct net_device *net_dev)
1417 {
1418 struct bgmac *bgmac = netdev_priv(net_dev);
1419 struct phy_device *phy_dev = bgmac->phy_dev;
1420 bool update = false;
1421
1422 if (phy_dev->link) {
1423 if (phy_dev->speed != bgmac->mac_speed) {
1424 bgmac->mac_speed = phy_dev->speed;
1425 update = true;
1426 }
1427
1428 if (phy_dev->duplex != bgmac->mac_duplex) {
1429 bgmac->mac_duplex = phy_dev->duplex;
1430 update = true;
1431 }
1432 }
1433
1434 if (update) {
1435 bgmac_mac_speed(bgmac);
1436 phy_print_status(phy_dev);
1437 }
1438 }
1439
1440 static int bgmac_fixed_phy_register(struct bgmac *bgmac)
1441 {
1442 struct fixed_phy_status fphy_status = {
1443 .link = 1,
1444 .speed = SPEED_1000,
1445 .duplex = DUPLEX_FULL,
1446 };
1447 struct phy_device *phy_dev;
1448 int err;
1449
1450 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
1451 if (!phy_dev || IS_ERR(phy_dev)) {
1452 bgmac_err(bgmac, "Failed to register fixed PHY device\n");
1453 return -ENODEV;
1454 }
1455
1456 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1457 PHY_INTERFACE_MODE_MII);
1458 if (err) {
1459 bgmac_err(bgmac, "Connecting PHY failed\n");
1460 return err;
1461 }
1462
1463 bgmac->phy_dev = phy_dev;
1464
1465 return err;
1466 }
1467
1468 static int bgmac_mii_register(struct bgmac *bgmac)
1469 {
1470 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1471 struct mii_bus *mii_bus;
1472 struct phy_device *phy_dev;
1473 char bus_id[MII_BUS_ID_SIZE + 3];
1474 int i, err = 0;
1475
1476 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1477 ci->id == BCMA_CHIP_ID_BCM53018)
1478 return bgmac_fixed_phy_register(bgmac);
1479
1480 mii_bus = mdiobus_alloc();
1481 if (!mii_bus)
1482 return -ENOMEM;
1483
1484 mii_bus->name = "bgmac mii bus";
1485 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1486 bgmac->core->core_unit);
1487 mii_bus->priv = bgmac;
1488 mii_bus->read = bgmac_mii_read;
1489 mii_bus->write = bgmac_mii_write;
1490 mii_bus->parent = &bgmac->core->dev;
1491 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1492
1493 mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1494 if (!mii_bus->irq) {
1495 err = -ENOMEM;
1496 goto err_free_bus;
1497 }
1498 for (i = 0; i < PHY_MAX_ADDR; i++)
1499 mii_bus->irq[i] = PHY_POLL;
1500
1501 err = mdiobus_register(mii_bus);
1502 if (err) {
1503 bgmac_err(bgmac, "Registration of mii bus failed\n");
1504 goto err_free_irq;
1505 }
1506
1507 bgmac->mii_bus = mii_bus;
1508
1509 /* Connect to the PHY */
1510 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1511 bgmac->phyaddr);
1512 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1513 PHY_INTERFACE_MODE_MII);
1514 if (IS_ERR(phy_dev)) {
1515 bgmac_err(bgmac, "PHY connecton failed\n");
1516 err = PTR_ERR(phy_dev);
1517 goto err_unregister_bus;
1518 }
1519 bgmac->phy_dev = phy_dev;
1520
1521 return err;
1522
1523 err_unregister_bus:
1524 mdiobus_unregister(mii_bus);
1525 err_free_irq:
1526 kfree(mii_bus->irq);
1527 err_free_bus:
1528 mdiobus_free(mii_bus);
1529 return err;
1530 }
1531
1532 static void bgmac_mii_unregister(struct bgmac *bgmac)
1533 {
1534 struct mii_bus *mii_bus = bgmac->mii_bus;
1535
1536 mdiobus_unregister(mii_bus);
1537 kfree(mii_bus->irq);
1538 mdiobus_free(mii_bus);
1539 }
1540
1541 /**************************************************
1542 * BCMA bus ops
1543 **************************************************/
1544
1545 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1546 static int bgmac_probe(struct bcma_device *core)
1547 {
1548 struct bcma_chipinfo *ci = &core->bus->chipinfo;
1549 struct net_device *net_dev;
1550 struct bgmac *bgmac;
1551 struct ssb_sprom *sprom = &core->bus->sprom;
1552 u8 *mac = core->core_unit ? sprom->et1mac : sprom->et0mac;
1553 int err;
1554
1555 /* We don't support 2nd, 3rd, ... units, SPROM has to be adjusted */
1556 if (core->core_unit > 1) {
1557 pr_err("Unsupported core_unit %d\n", core->core_unit);
1558 return -ENOTSUPP;
1559 }
1560
1561 if (!is_valid_ether_addr(mac)) {
1562 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1563 eth_random_addr(mac);
1564 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1565 }
1566
1567 /* Allocation and references */
1568 net_dev = alloc_etherdev(sizeof(*bgmac));
1569 if (!net_dev)
1570 return -ENOMEM;
1571 net_dev->netdev_ops = &bgmac_netdev_ops;
1572 net_dev->irq = core->irq;
1573 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1574 bgmac = netdev_priv(net_dev);
1575 bgmac->net_dev = net_dev;
1576 bgmac->core = core;
1577 bcma_set_drvdata(core, bgmac);
1578
1579 /* Defaults */
1580 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1581
1582 /* On BCM4706 we need common core to access PHY */
1583 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1584 !core->bus->drv_gmac_cmn.core) {
1585 bgmac_err(bgmac, "GMAC CMN core not found (required for BCM4706)\n");
1586 err = -ENODEV;
1587 goto err_netdev_free;
1588 }
1589 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1590
1591 bgmac->phyaddr = core->core_unit ? sprom->et1phyaddr :
1592 sprom->et0phyaddr;
1593 bgmac->phyaddr &= BGMAC_PHY_MASK;
1594 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1595 bgmac_err(bgmac, "No PHY found\n");
1596 err = -ENODEV;
1597 goto err_netdev_free;
1598 }
1599 bgmac_info(bgmac, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1600 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1601
1602 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1603 bgmac_err(bgmac, "PCI setup not implemented\n");
1604 err = -ENOTSUPP;
1605 goto err_netdev_free;
1606 }
1607
1608 bgmac_chip_reset(bgmac);
1609
1610 /* For Northstar, we have to take all GMAC core out of reset */
1611 if (ci->id == BCMA_CHIP_ID_BCM4707 ||
1612 ci->id == BCMA_CHIP_ID_BCM53018) {
1613 struct bcma_device *ns_core;
1614 int ns_gmac;
1615
1616 /* Northstar has 4 GMAC cores */
1617 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
1618 /* As Northstar requirement, we have to reset all GMACs
1619 * before accessing one. bgmac_chip_reset() call
1620 * bcma_core_enable() for this core. Then the other
1621 * three GMACs didn't reset. We do it here.
1622 */
1623 ns_core = bcma_find_core_unit(core->bus,
1624 BCMA_CORE_MAC_GBIT,
1625 ns_gmac);
1626 if (ns_core && !bcma_core_is_enabled(ns_core))
1627 bcma_core_enable(ns_core, 0);
1628 }
1629 }
1630
1631 err = bgmac_dma_alloc(bgmac);
1632 if (err) {
1633 bgmac_err(bgmac, "Unable to alloc memory for DMA\n");
1634 goto err_netdev_free;
1635 }
1636
1637 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1638 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1639 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1640
1641 /* TODO: reset the external phy. Specs are needed */
1642 bgmac_phy_reset(bgmac);
1643
1644 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1645 BGMAC_BFL_ENETROBO);
1646 if (bgmac->has_robosw)
1647 bgmac_warn(bgmac, "Support for Roboswitch not implemented\n");
1648
1649 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1650 bgmac_warn(bgmac, "Support for ADMtek ethernet switch not implemented\n");
1651
1652 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1653
1654 err = bgmac_mii_register(bgmac);
1655 if (err) {
1656 bgmac_err(bgmac, "Cannot register MDIO\n");
1657 goto err_dma_free;
1658 }
1659
1660 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1661 net_dev->hw_features = net_dev->features;
1662 net_dev->vlan_features = net_dev->features;
1663
1664 err = register_netdev(bgmac->net_dev);
1665 if (err) {
1666 bgmac_err(bgmac, "Cannot register net device\n");
1667 goto err_mii_unregister;
1668 }
1669
1670 netif_carrier_off(net_dev);
1671
1672 return 0;
1673
1674 err_mii_unregister:
1675 bgmac_mii_unregister(bgmac);
1676 err_dma_free:
1677 bgmac_dma_free(bgmac);
1678
1679 err_netdev_free:
1680 bcma_set_drvdata(core, NULL);
1681 free_netdev(net_dev);
1682
1683 return err;
1684 }
1685
1686 static void bgmac_remove(struct bcma_device *core)
1687 {
1688 struct bgmac *bgmac = bcma_get_drvdata(core);
1689
1690 unregister_netdev(bgmac->net_dev);
1691 bgmac_mii_unregister(bgmac);
1692 netif_napi_del(&bgmac->napi);
1693 bgmac_dma_free(bgmac);
1694 bcma_set_drvdata(core, NULL);
1695 free_netdev(bgmac->net_dev);
1696 }
1697
1698 static struct bcma_driver bgmac_bcma_driver = {
1699 .name = KBUILD_MODNAME,
1700 .id_table = bgmac_bcma_tbl,
1701 .probe = bgmac_probe,
1702 .remove = bgmac_remove,
1703 };
1704
1705 static int __init bgmac_init(void)
1706 {
1707 int err;
1708
1709 err = bcma_driver_register(&bgmac_bcma_driver);
1710 if (err)
1711 return err;
1712 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1713
1714 return 0;
1715 }
1716
1717 static void __exit bgmac_exit(void)
1718 {
1719 bcma_driver_unregister(&bgmac_bcma_driver);
1720 }
1721
1722 module_init(bgmac_init)
1723 module_exit(bgmac_exit)
1724
1725 MODULE_AUTHOR("Rafał Miłecki");
1726 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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