1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/ethtool.h>
21 #include <linux/netdevice.h>
22 #include <linux/types.h>
23 #include <linux/sched.h>
24 #include <linux/crc32.h>
26 #include "bnx2x_cmn.h"
27 #include "bnx2x_dump.h"
28 #include "bnx2x_init.h"
30 /* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
34 #define MAX_QUEUE_NAME_LEN 4
38 char string
[ETH_GSTRING_LEN
];
39 } bnx2x_q_stats_arr
[] = {
40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi
), 8, "[%s]: rx_bytes" },
41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi
),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi
),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi
),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi
), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt
),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed
),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err
), 4, "[%s]: rx_csum_offload_errors" },
54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi
), 8, "[%s]: tx_bytes" },
55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi
),
56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi
),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi
),
60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi
),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi
),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi
), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt
),
67 4, "[%s]: driver_filtered_tx_pkt" }
70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
76 #define STATS_FLAGS_PORT 1
77 #define STATS_FLAGS_FUNC 2
78 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string
[ETH_GSTRING_LEN
];
80 } bnx2x_stats_arr
[] = {
81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi
),
82 8, STATS_FLAGS_BOTH
, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi
),
84 8, STATS_FLAGS_BOTH
, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi
),
86 8, STATS_FLAGS_BOTH
, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi
),
88 8, STATS_FLAGS_BOTH
, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi
),
90 8, STATS_FLAGS_BOTH
, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi
),
92 8, STATS_FLAGS_PORT
, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi
),
94 8, STATS_FLAGS_PORT
, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi
),
96 8, STATS_FLAGS_PORT
, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi
),
98 8, STATS_FLAGS_PORT
, "rx_oversize_packets" },
99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi
),
100 8, STATS_FLAGS_PORT
, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi
),
102 8, STATS_FLAGS_PORT
, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi
),
104 8, STATS_FLAGS_BOTH
, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard
),
106 4, STATS_FLAGS_PORT
, "rx_filtered_packets" },
107 { STATS_OFFSET32(mf_tag_discard
),
108 4, STATS_FLAGS_PORT
, "rx_mf_tag_discard" },
109 { STATS_OFFSET32(pfc_frames_received_hi
),
110 8, STATS_FLAGS_PORT
, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi
),
112 8, STATS_FLAGS_PORT
, "pfc_frames_sent" },
113 { STATS_OFFSET32(brb_drop_hi
),
114 8, STATS_FLAGS_PORT
, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi
),
116 8, STATS_FLAGS_PORT
, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi
),
118 8, STATS_FLAGS_PORT
, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi
),
120 8, STATS_FLAGS_PORT
, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max
),
122 4, STATS_FLAGS_PORT
, "rx_constant_pause_events" },
123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt
),
124 4, STATS_FLAGS_BOTH
, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed
),
126 4, STATS_FLAGS_BOTH
, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err
),
128 4, STATS_FLAGS_BOTH
, "rx_csum_offload_errors" },
130 { STATS_OFFSET32(total_bytes_transmitted_hi
),
131 8, STATS_FLAGS_BOTH
, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi
),
133 8, STATS_FLAGS_PORT
, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi
),
135 8, STATS_FLAGS_BOTH
, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi
),
137 8, STATS_FLAGS_BOTH
, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi
),
139 8, STATS_FLAGS_BOTH
, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi
),
141 8, STATS_FLAGS_PORT
, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi
),
143 8, STATS_FLAGS_PORT
, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi
),
145 8, STATS_FLAGS_PORT
, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi
),
147 8, STATS_FLAGS_PORT
, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi
),
149 8, STATS_FLAGS_PORT
, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi
),
151 8, STATS_FLAGS_PORT
, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi
),
153 8, STATS_FLAGS_PORT
, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi
),
155 8, STATS_FLAGS_PORT
, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi
),
157 8, STATS_FLAGS_PORT
, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi
),
159 8, STATS_FLAGS_PORT
, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi
),
161 8, STATS_FLAGS_PORT
, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi
),
163 8, STATS_FLAGS_PORT
, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi
),
165 8, STATS_FLAGS_PORT
, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi
),
167 8, STATS_FLAGS_PORT
, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi
),
169 8, STATS_FLAGS_PORT
, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi
),
171 8, STATS_FLAGS_PORT
, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi
),
173 8, STATS_FLAGS_FUNC
, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi
),
175 8, STATS_FLAGS_FUNC
, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi
),
177 8, STATS_FLAGS_FUNC
, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error
),
179 4, STATS_FLAGS_FUNC
, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error
),
181 4, STATS_FLAGS_FUNC
, "unrecoverable_errors" },
182 { STATS_OFFSET32(driver_filtered_tx_pkt
),
183 4, STATS_FLAGS_FUNC
, "driver_filtered_tx_pkt" },
184 { STATS_OFFSET32(eee_tx_lpi
),
185 4, STATS_FLAGS_PORT
, "Tx LPI entry count"}
188 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
190 static int bnx2x_get_port_type(struct bnx2x
*bp
)
193 u32 phy_idx
= bnx2x_get_cur_phy_idx(bp
);
194 switch (bp
->link_params
.phy
[phy_idx
].media_type
) {
195 case ETH_PHY_SFPP_10G_FIBER
:
196 case ETH_PHY_SFP_1G_FIBER
:
197 case ETH_PHY_XFP_FIBER
:
200 port_type
= PORT_FIBRE
;
202 case ETH_PHY_DA_TWINAX
:
208 case ETH_PHY_NOT_PRESENT
:
209 port_type
= PORT_NONE
;
211 case ETH_PHY_UNSPECIFIED
:
213 port_type
= PORT_OTHER
;
219 static int bnx2x_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
221 struct bnx2x
*bp
= netdev_priv(dev
);
222 int cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
224 /* Dual Media boards present all available port types */
225 cmd
->supported
= bp
->port
.supported
[cfg_idx
] |
226 (bp
->port
.supported
[cfg_idx
^ 1] &
227 (SUPPORTED_TP
| SUPPORTED_FIBRE
));
228 cmd
->advertising
= bp
->port
.advertising
[cfg_idx
];
229 if (bp
->link_params
.phy
[bnx2x_get_cur_phy_idx(bp
)].media_type
==
230 ETH_PHY_SFP_1G_FIBER
) {
231 cmd
->supported
&= ~(SUPPORTED_10000baseT_Full
);
232 cmd
->advertising
&= ~(ADVERTISED_10000baseT_Full
);
235 if ((bp
->state
== BNX2X_STATE_OPEN
) && bp
->link_vars
.link_up
&&
236 !(bp
->flags
& MF_FUNC_DIS
)) {
237 cmd
->duplex
= bp
->link_vars
.duplex
;
239 if (IS_MF(bp
) && !BP_NOMCP(bp
))
240 ethtool_cmd_speed_set(cmd
, bnx2x_get_mf_speed(bp
));
242 ethtool_cmd_speed_set(cmd
, bp
->link_vars
.line_speed
);
244 cmd
->duplex
= DUPLEX_UNKNOWN
;
245 ethtool_cmd_speed_set(cmd
, SPEED_UNKNOWN
);
248 cmd
->port
= bnx2x_get_port_type(bp
);
250 cmd
->phy_address
= bp
->mdio
.prtad
;
251 cmd
->transceiver
= XCVR_INTERNAL
;
253 if (bp
->link_params
.req_line_speed
[cfg_idx
] == SPEED_AUTO_NEG
)
254 cmd
->autoneg
= AUTONEG_ENABLE
;
256 cmd
->autoneg
= AUTONEG_DISABLE
;
258 /* Publish LP advertised speeds and FC */
259 if (bp
->link_vars
.link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
260 u32 status
= bp
->link_vars
.link_status
;
262 cmd
->lp_advertising
|= ADVERTISED_Autoneg
;
263 if (status
& LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE
)
264 cmd
->lp_advertising
|= ADVERTISED_Pause
;
265 if (status
& LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE
)
266 cmd
->lp_advertising
|= ADVERTISED_Asym_Pause
;
268 if (status
& LINK_STATUS_LINK_PARTNER_10THD_CAPABLE
)
269 cmd
->lp_advertising
|= ADVERTISED_10baseT_Half
;
270 if (status
& LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE
)
271 cmd
->lp_advertising
|= ADVERTISED_10baseT_Full
;
272 if (status
& LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE
)
273 cmd
->lp_advertising
|= ADVERTISED_100baseT_Half
;
274 if (status
& LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE
)
275 cmd
->lp_advertising
|= ADVERTISED_100baseT_Full
;
276 if (status
& LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE
)
277 cmd
->lp_advertising
|= ADVERTISED_1000baseT_Half
;
278 if (status
& LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
)
279 cmd
->lp_advertising
|= ADVERTISED_1000baseT_Full
;
280 if (status
& LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE
)
281 cmd
->lp_advertising
|= ADVERTISED_2500baseX_Full
;
282 if (status
& LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
)
283 cmd
->lp_advertising
|= ADVERTISED_10000baseT_Full
;
284 if (status
& LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE
)
285 cmd
->lp_advertising
|= ADVERTISED_20000baseKR2_Full
;
291 DP(BNX2X_MSG_ETHTOOL
, "ethtool_cmd: cmd %d\n"
292 " supported 0x%x advertising 0x%x speed %u\n"
293 " duplex %d port %d phy_address %d transceiver %d\n"
294 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
295 cmd
->cmd
, cmd
->supported
, cmd
->advertising
,
296 ethtool_cmd_speed(cmd
),
297 cmd
->duplex
, cmd
->port
, cmd
->phy_address
, cmd
->transceiver
,
298 cmd
->autoneg
, cmd
->maxtxpkt
, cmd
->maxrxpkt
);
303 static int bnx2x_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
305 struct bnx2x
*bp
= netdev_priv(dev
);
306 u32 advertising
, cfg_idx
, old_multi_phy_config
, new_multi_phy_config
;
312 DP(BNX2X_MSG_ETHTOOL
, "ethtool_cmd: cmd %d\n"
313 " supported 0x%x advertising 0x%x speed %u\n"
314 " duplex %d port %d phy_address %d transceiver %d\n"
315 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
316 cmd
->cmd
, cmd
->supported
, cmd
->advertising
,
317 ethtool_cmd_speed(cmd
),
318 cmd
->duplex
, cmd
->port
, cmd
->phy_address
, cmd
->transceiver
,
319 cmd
->autoneg
, cmd
->maxtxpkt
, cmd
->maxrxpkt
);
321 speed
= ethtool_cmd_speed(cmd
);
323 /* If received a request for an unknown duplex, assume full*/
324 if (cmd
->duplex
== DUPLEX_UNKNOWN
)
325 cmd
->duplex
= DUPLEX_FULL
;
329 u32 line_speed
= bp
->link_vars
.line_speed
;
331 /* use 10G if no link detected */
335 if (bp
->common
.bc_ver
< REQ_BC_VER_4_SET_MF_BW
) {
336 DP(BNX2X_MSG_ETHTOOL
,
337 "To set speed BC %X or higher is required, please upgrade BC\n",
338 REQ_BC_VER_4_SET_MF_BW
);
342 part
= (speed
* 100) / line_speed
;
344 if (line_speed
< speed
|| !part
) {
345 DP(BNX2X_MSG_ETHTOOL
,
346 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
350 if (bp
->state
!= BNX2X_STATE_OPEN
)
351 /* store value for following "load" */
352 bp
->pending_max
= part
;
354 bnx2x_update_max_mf_config(bp
, part
);
359 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
360 old_multi_phy_config
= bp
->link_params
.multi_phy_config
;
361 if (cmd
->port
!= bnx2x_get_port_type(bp
)) {
364 if (!(bp
->port
.supported
[0] & SUPPORTED_TP
||
365 bp
->port
.supported
[1] & SUPPORTED_TP
)) {
366 DP(BNX2X_MSG_ETHTOOL
,
367 "Unsupported port type\n");
370 bp
->link_params
.multi_phy_config
&=
371 ~PORT_HW_CFG_PHY_SELECTION_MASK
;
372 if (bp
->link_params
.multi_phy_config
&
373 PORT_HW_CFG_PHY_SWAPPED_ENABLED
)
374 bp
->link_params
.multi_phy_config
|=
375 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
;
377 bp
->link_params
.multi_phy_config
|=
378 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
;
382 if (!(bp
->port
.supported
[0] & SUPPORTED_FIBRE
||
383 bp
->port
.supported
[1] & SUPPORTED_FIBRE
)) {
384 DP(BNX2X_MSG_ETHTOOL
,
385 "Unsupported port type\n");
388 bp
->link_params
.multi_phy_config
&=
389 ~PORT_HW_CFG_PHY_SELECTION_MASK
;
390 if (bp
->link_params
.multi_phy_config
&
391 PORT_HW_CFG_PHY_SWAPPED_ENABLED
)
392 bp
->link_params
.multi_phy_config
|=
393 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
;
395 bp
->link_params
.multi_phy_config
|=
396 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
;
399 DP(BNX2X_MSG_ETHTOOL
, "Unsupported port type\n");
403 /* Save new config in case command complete successfully */
404 new_multi_phy_config
= bp
->link_params
.multi_phy_config
;
405 /* Get the new cfg_idx */
406 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
407 /* Restore old config in case command failed */
408 bp
->link_params
.multi_phy_config
= old_multi_phy_config
;
409 DP(BNX2X_MSG_ETHTOOL
, "cfg_idx = %x\n", cfg_idx
);
411 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
412 u32 an_supported_speed
= bp
->port
.supported
[cfg_idx
];
413 if (bp
->link_params
.phy
[EXT_PHY1
].type
==
414 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
)
415 an_supported_speed
|= (SUPPORTED_100baseT_Half
|
416 SUPPORTED_100baseT_Full
);
417 if (!(bp
->port
.supported
[cfg_idx
] & SUPPORTED_Autoneg
)) {
418 DP(BNX2X_MSG_ETHTOOL
, "Autoneg not supported\n");
422 /* advertise the requested speed and duplex if supported */
423 if (cmd
->advertising
& ~an_supported_speed
) {
424 DP(BNX2X_MSG_ETHTOOL
,
425 "Advertisement parameters are not supported\n");
429 bp
->link_params
.req_line_speed
[cfg_idx
] = SPEED_AUTO_NEG
;
430 bp
->link_params
.req_duplex
[cfg_idx
] = cmd
->duplex
;
431 bp
->port
.advertising
[cfg_idx
] = (ADVERTISED_Autoneg
|
433 if (cmd
->advertising
) {
435 bp
->link_params
.speed_cap_mask
[cfg_idx
] = 0;
436 if (cmd
->advertising
& ADVERTISED_10baseT_Half
) {
437 bp
->link_params
.speed_cap_mask
[cfg_idx
] |=
438 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
;
440 if (cmd
->advertising
& ADVERTISED_10baseT_Full
)
441 bp
->link_params
.speed_cap_mask
[cfg_idx
] |=
442 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
;
444 if (cmd
->advertising
& ADVERTISED_100baseT_Full
)
445 bp
->link_params
.speed_cap_mask
[cfg_idx
] |=
446 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
;
448 if (cmd
->advertising
& ADVERTISED_100baseT_Half
) {
449 bp
->link_params
.speed_cap_mask
[cfg_idx
] |=
450 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
;
452 if (cmd
->advertising
& ADVERTISED_1000baseT_Half
) {
453 bp
->link_params
.speed_cap_mask
[cfg_idx
] |=
454 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
;
456 if (cmd
->advertising
& (ADVERTISED_1000baseT_Full
|
457 ADVERTISED_1000baseKX_Full
))
458 bp
->link_params
.speed_cap_mask
[cfg_idx
] |=
459 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
;
461 if (cmd
->advertising
& (ADVERTISED_10000baseT_Full
|
462 ADVERTISED_10000baseKX4_Full
|
463 ADVERTISED_10000baseKR_Full
))
464 bp
->link_params
.speed_cap_mask
[cfg_idx
] |=
465 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
;
467 if (cmd
->advertising
& ADVERTISED_20000baseKR2_Full
)
468 bp
->link_params
.speed_cap_mask
[cfg_idx
] |=
469 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
;
471 } else { /* forced speed */
472 /* advertise the requested speed and duplex if supported */
475 if (cmd
->duplex
== DUPLEX_FULL
) {
476 if (!(bp
->port
.supported
[cfg_idx
] &
477 SUPPORTED_10baseT_Full
)) {
478 DP(BNX2X_MSG_ETHTOOL
,
479 "10M full not supported\n");
483 advertising
= (ADVERTISED_10baseT_Full
|
486 if (!(bp
->port
.supported
[cfg_idx
] &
487 SUPPORTED_10baseT_Half
)) {
488 DP(BNX2X_MSG_ETHTOOL
,
489 "10M half not supported\n");
493 advertising
= (ADVERTISED_10baseT_Half
|
499 if (cmd
->duplex
== DUPLEX_FULL
) {
500 if (!(bp
->port
.supported
[cfg_idx
] &
501 SUPPORTED_100baseT_Full
)) {
502 DP(BNX2X_MSG_ETHTOOL
,
503 "100M full not supported\n");
507 advertising
= (ADVERTISED_100baseT_Full
|
510 if (!(bp
->port
.supported
[cfg_idx
] &
511 SUPPORTED_100baseT_Half
)) {
512 DP(BNX2X_MSG_ETHTOOL
,
513 "100M half not supported\n");
517 advertising
= (ADVERTISED_100baseT_Half
|
523 if (cmd
->duplex
!= DUPLEX_FULL
) {
524 DP(BNX2X_MSG_ETHTOOL
,
525 "1G half not supported\n");
529 if (!(bp
->port
.supported
[cfg_idx
] &
530 SUPPORTED_1000baseT_Full
)) {
531 DP(BNX2X_MSG_ETHTOOL
,
532 "1G full not supported\n");
536 advertising
= (ADVERTISED_1000baseT_Full
|
541 if (cmd
->duplex
!= DUPLEX_FULL
) {
542 DP(BNX2X_MSG_ETHTOOL
,
543 "2.5G half not supported\n");
547 if (!(bp
->port
.supported
[cfg_idx
]
548 & SUPPORTED_2500baseX_Full
)) {
549 DP(BNX2X_MSG_ETHTOOL
,
550 "2.5G full not supported\n");
554 advertising
= (ADVERTISED_2500baseX_Full
|
559 if (cmd
->duplex
!= DUPLEX_FULL
) {
560 DP(BNX2X_MSG_ETHTOOL
,
561 "10G half not supported\n");
564 phy_idx
= bnx2x_get_cur_phy_idx(bp
);
565 if (!(bp
->port
.supported
[cfg_idx
]
566 & SUPPORTED_10000baseT_Full
) ||
567 (bp
->link_params
.phy
[phy_idx
].media_type
==
568 ETH_PHY_SFP_1G_FIBER
)) {
569 DP(BNX2X_MSG_ETHTOOL
,
570 "10G full not supported\n");
574 advertising
= (ADVERTISED_10000baseT_Full
|
579 DP(BNX2X_MSG_ETHTOOL
, "Unsupported speed %u\n", speed
);
583 bp
->link_params
.req_line_speed
[cfg_idx
] = speed
;
584 bp
->link_params
.req_duplex
[cfg_idx
] = cmd
->duplex
;
585 bp
->port
.advertising
[cfg_idx
] = advertising
;
588 DP(BNX2X_MSG_ETHTOOL
, "req_line_speed %d\n"
589 " req_duplex %d advertising 0x%x\n",
590 bp
->link_params
.req_line_speed
[cfg_idx
],
591 bp
->link_params
.req_duplex
[cfg_idx
],
592 bp
->port
.advertising
[cfg_idx
]);
595 bp
->link_params
.multi_phy_config
= new_multi_phy_config
;
596 if (netif_running(dev
)) {
597 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
604 #define DUMP_ALL_PRESETS 0x1FFF
605 #define DUMP_MAX_PRESETS 13
607 static int __bnx2x_get_preset_regs_len(struct bnx2x
*bp
, u32 preset
)
610 return dump_num_registers
[0][preset
-1];
611 else if (CHIP_IS_E1H(bp
))
612 return dump_num_registers
[1][preset
-1];
613 else if (CHIP_IS_E2(bp
))
614 return dump_num_registers
[2][preset
-1];
615 else if (CHIP_IS_E3A0(bp
))
616 return dump_num_registers
[3][preset
-1];
617 else if (CHIP_IS_E3B0(bp
))
618 return dump_num_registers
[4][preset
-1];
623 static int __bnx2x_get_regs_len(struct bnx2x
*bp
)
628 /* Calculate the total preset regs length */
629 for (preset_idx
= 1; preset_idx
<= DUMP_MAX_PRESETS
; preset_idx
++)
630 regdump_len
+= __bnx2x_get_preset_regs_len(bp
, preset_idx
);
635 static int bnx2x_get_regs_len(struct net_device
*dev
)
637 struct bnx2x
*bp
= netdev_priv(dev
);
643 regdump_len
= __bnx2x_get_regs_len(bp
);
645 regdump_len
+= sizeof(struct dump_header
);
650 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
651 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
652 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
653 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
654 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
656 #define IS_REG_IN_PRESET(presets, idx) \
657 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
659 /******* Paged registers info selectors ********/
660 static const u32
*__bnx2x_get_page_addr_ar(struct bnx2x
*bp
)
664 else if (CHIP_IS_E3(bp
))
670 static u32
__bnx2x_get_page_reg_num(struct bnx2x
*bp
)
673 return PAGE_MODE_VALUES_E2
;
674 else if (CHIP_IS_E3(bp
))
675 return PAGE_MODE_VALUES_E3
;
680 static const u32
*__bnx2x_get_page_write_ar(struct bnx2x
*bp
)
683 return page_write_regs_e2
;
684 else if (CHIP_IS_E3(bp
))
685 return page_write_regs_e3
;
690 static u32
__bnx2x_get_page_write_num(struct bnx2x
*bp
)
693 return PAGE_WRITE_REGS_E2
;
694 else if (CHIP_IS_E3(bp
))
695 return PAGE_WRITE_REGS_E3
;
700 static const struct reg_addr
*__bnx2x_get_page_read_ar(struct bnx2x
*bp
)
703 return page_read_regs_e2
;
704 else if (CHIP_IS_E3(bp
))
705 return page_read_regs_e3
;
710 static u32
__bnx2x_get_page_read_num(struct bnx2x
*bp
)
713 return PAGE_READ_REGS_E2
;
714 else if (CHIP_IS_E3(bp
))
715 return PAGE_READ_REGS_E3
;
720 static bool bnx2x_is_reg_in_chip(struct bnx2x
*bp
,
721 const struct reg_addr
*reg_info
)
724 return IS_E1_REG(reg_info
->chips
);
725 else if (CHIP_IS_E1H(bp
))
726 return IS_E1H_REG(reg_info
->chips
);
727 else if (CHIP_IS_E2(bp
))
728 return IS_E2_REG(reg_info
->chips
);
729 else if (CHIP_IS_E3A0(bp
))
730 return IS_E3A0_REG(reg_info
->chips
);
731 else if (CHIP_IS_E3B0(bp
))
732 return IS_E3B0_REG(reg_info
->chips
);
737 static bool bnx2x_is_wreg_in_chip(struct bnx2x
*bp
,
738 const struct wreg_addr
*wreg_info
)
741 return IS_E1_REG(wreg_info
->chips
);
742 else if (CHIP_IS_E1H(bp
))
743 return IS_E1H_REG(wreg_info
->chips
);
744 else if (CHIP_IS_E2(bp
))
745 return IS_E2_REG(wreg_info
->chips
);
746 else if (CHIP_IS_E3A0(bp
))
747 return IS_E3A0_REG(wreg_info
->chips
);
748 else if (CHIP_IS_E3B0(bp
))
749 return IS_E3B0_REG(wreg_info
->chips
);
755 * bnx2x_read_pages_regs - read "paged" registers
760 * Reads "paged" memories: memories that may only be read by first writing to a
761 * specific address ("write address") and then reading from a specific address
762 * ("read address"). There may be more than one write address per "page" and
763 * more than one read address per write address.
765 static void bnx2x_read_pages_regs(struct bnx2x
*bp
, u32
*p
, u32 preset
)
769 /* addresses of the paged registers */
770 const u32
*page_addr
= __bnx2x_get_page_addr_ar(bp
);
771 /* number of paged registers */
772 int num_pages
= __bnx2x_get_page_reg_num(bp
);
773 /* write addresses */
774 const u32
*write_addr
= __bnx2x_get_page_write_ar(bp
);
775 /* number of write addresses */
776 int write_num
= __bnx2x_get_page_write_num(bp
);
777 /* read addresses info */
778 const struct reg_addr
*read_addr
= __bnx2x_get_page_read_ar(bp
);
779 /* number of read addresses */
780 int read_num
= __bnx2x_get_page_read_num(bp
);
783 for (i
= 0; i
< num_pages
; i
++) {
784 for (j
= 0; j
< write_num
; j
++) {
785 REG_WR(bp
, write_addr
[j
], page_addr
[i
]);
787 for (k
= 0; k
< read_num
; k
++) {
788 if (IS_REG_IN_PRESET(read_addr
[k
].presets
,
790 size
= read_addr
[k
].size
;
791 for (n
= 0; n
< size
; n
++) {
792 addr
= read_addr
[k
].addr
+ n
*4;
793 *p
++ = REG_RD(bp
, addr
);
801 static int __bnx2x_get_preset_regs(struct bnx2x
*bp
, u32
*p
, u32 preset
)
804 const struct wreg_addr
*wreg_addr_p
= NULL
;
807 wreg_addr_p
= &wreg_addr_e1
;
808 else if (CHIP_IS_E1H(bp
))
809 wreg_addr_p
= &wreg_addr_e1h
;
810 else if (CHIP_IS_E2(bp
))
811 wreg_addr_p
= &wreg_addr_e2
;
812 else if (CHIP_IS_E3A0(bp
))
813 wreg_addr_p
= &wreg_addr_e3
;
814 else if (CHIP_IS_E3B0(bp
))
815 wreg_addr_p
= &wreg_addr_e3b0
;
817 /* Read the idle_chk registers */
818 for (i
= 0; i
< IDLE_REGS_COUNT
; i
++) {
819 if (bnx2x_is_reg_in_chip(bp
, &idle_reg_addrs
[i
]) &&
820 IS_REG_IN_PRESET(idle_reg_addrs
[i
].presets
, preset
)) {
821 for (j
= 0; j
< idle_reg_addrs
[i
].size
; j
++)
822 *p
++ = REG_RD(bp
, idle_reg_addrs
[i
].addr
+ j
*4);
826 /* Read the regular registers */
827 for (i
= 0; i
< REGS_COUNT
; i
++) {
828 if (bnx2x_is_reg_in_chip(bp
, ®_addrs
[i
]) &&
829 IS_REG_IN_PRESET(reg_addrs
[i
].presets
, preset
)) {
830 for (j
= 0; j
< reg_addrs
[i
].size
; j
++)
831 *p
++ = REG_RD(bp
, reg_addrs
[i
].addr
+ j
*4);
835 /* Read the CAM registers */
836 if (bnx2x_is_wreg_in_chip(bp
, wreg_addr_p
) &&
837 IS_REG_IN_PRESET(wreg_addr_p
->presets
, preset
)) {
838 for (i
= 0; i
< wreg_addr_p
->size
; i
++) {
839 *p
++ = REG_RD(bp
, wreg_addr_p
->addr
+ i
*4);
841 /* In case of wreg_addr register, read additional
842 registers from read_regs array
844 for (j
= 0; j
< wreg_addr_p
->read_regs_count
; j
++) {
845 addr
= *(wreg_addr_p
->read_regs
);
846 *p
++ = REG_RD(bp
, addr
+ j
*4);
851 /* Paged registers are supported in E2 & E3 only */
852 if (CHIP_IS_E2(bp
) || CHIP_IS_E3(bp
)) {
853 /* Read "paged" registers */
854 bnx2x_read_pages_regs(bp
, p
, preset
);
860 static void __bnx2x_get_regs(struct bnx2x
*bp
, u32
*p
)
864 /* Read all registers, by reading all preset registers */
865 for (preset_idx
= 1; preset_idx
<= DUMP_MAX_PRESETS
; preset_idx
++) {
866 /* Skip presets with IOR */
867 if ((preset_idx
== 2) ||
872 __bnx2x_get_preset_regs(bp
, p
, preset_idx
);
873 p
+= __bnx2x_get_preset_regs_len(bp
, preset_idx
);
877 static void bnx2x_get_regs(struct net_device
*dev
,
878 struct ethtool_regs
*regs
, void *_p
)
881 struct bnx2x
*bp
= netdev_priv(dev
);
882 struct dump_header dump_hdr
= {0};
885 memset(p
, 0, regs
->len
);
887 if (!netif_running(bp
->dev
))
890 /* Disable parity attentions as long as following dump may
891 * cause false alarms by reading never written registers. We
892 * will re-enable parity attentions right after the dump.
895 bnx2x_disable_blocks_parity(bp
);
897 dump_hdr
.header_size
= (sizeof(struct dump_header
) / 4) - 1;
898 dump_hdr
.preset
= DUMP_ALL_PRESETS
;
899 dump_hdr
.version
= BNX2X_DUMP_VERSION
;
901 /* dump_meta_data presents OR of CHIP and PATH. */
902 if (CHIP_IS_E1(bp
)) {
903 dump_hdr
.dump_meta_data
= DUMP_CHIP_E1
;
904 } else if (CHIP_IS_E1H(bp
)) {
905 dump_hdr
.dump_meta_data
= DUMP_CHIP_E1H
;
906 } else if (CHIP_IS_E2(bp
)) {
907 dump_hdr
.dump_meta_data
= DUMP_CHIP_E2
|
908 (BP_PATH(bp
) ? DUMP_PATH_1
: DUMP_PATH_0
);
909 } else if (CHIP_IS_E3A0(bp
)) {
910 dump_hdr
.dump_meta_data
= DUMP_CHIP_E3A0
|
911 (BP_PATH(bp
) ? DUMP_PATH_1
: DUMP_PATH_0
);
912 } else if (CHIP_IS_E3B0(bp
)) {
913 dump_hdr
.dump_meta_data
= DUMP_CHIP_E3B0
|
914 (BP_PATH(bp
) ? DUMP_PATH_1
: DUMP_PATH_0
);
917 memcpy(p
, &dump_hdr
, sizeof(struct dump_header
));
918 p
+= dump_hdr
.header_size
+ 1;
920 /* Actually read the registers */
921 __bnx2x_get_regs(bp
, p
);
923 /* Re-enable parity attentions */
924 bnx2x_clear_blocks_parity(bp
);
925 bnx2x_enable_blocks_parity(bp
);
928 static int bnx2x_get_preset_regs_len(struct net_device
*dev
, u32 preset
)
930 struct bnx2x
*bp
= netdev_priv(dev
);
933 regdump_len
= __bnx2x_get_preset_regs_len(bp
, preset
);
935 regdump_len
+= sizeof(struct dump_header
);
940 static int bnx2x_set_dump(struct net_device
*dev
, struct ethtool_dump
*val
)
942 struct bnx2x
*bp
= netdev_priv(dev
);
944 /* Use the ethtool_dump "flag" field as the dump preset index */
945 if (val
->flag
< 1 || val
->flag
> DUMP_MAX_PRESETS
)
948 bp
->dump_preset_idx
= val
->flag
;
952 static int bnx2x_get_dump_flag(struct net_device
*dev
,
953 struct ethtool_dump
*dump
)
955 struct bnx2x
*bp
= netdev_priv(dev
);
957 dump
->version
= BNX2X_DUMP_VERSION
;
958 dump
->flag
= bp
->dump_preset_idx
;
959 /* Calculate the requested preset idx length */
960 dump
->len
= bnx2x_get_preset_regs_len(dev
, bp
->dump_preset_idx
);
961 DP(BNX2X_MSG_ETHTOOL
, "Get dump preset %d length=%d\n",
962 bp
->dump_preset_idx
, dump
->len
);
966 static int bnx2x_get_dump_data(struct net_device
*dev
,
967 struct ethtool_dump
*dump
,
971 struct bnx2x
*bp
= netdev_priv(dev
);
972 struct dump_header dump_hdr
= {0};
974 /* Disable parity attentions as long as following dump may
975 * cause false alarms by reading never written registers. We
976 * will re-enable parity attentions right after the dump.
979 bnx2x_disable_blocks_parity(bp
);
981 dump_hdr
.header_size
= (sizeof(struct dump_header
) / 4) - 1;
982 dump_hdr
.preset
= bp
->dump_preset_idx
;
983 dump_hdr
.version
= BNX2X_DUMP_VERSION
;
985 DP(BNX2X_MSG_ETHTOOL
, "Get dump data of preset %d\n", dump_hdr
.preset
);
987 /* dump_meta_data presents OR of CHIP and PATH. */
988 if (CHIP_IS_E1(bp
)) {
989 dump_hdr
.dump_meta_data
= DUMP_CHIP_E1
;
990 } else if (CHIP_IS_E1H(bp
)) {
991 dump_hdr
.dump_meta_data
= DUMP_CHIP_E1H
;
992 } else if (CHIP_IS_E2(bp
)) {
993 dump_hdr
.dump_meta_data
= DUMP_CHIP_E2
|
994 (BP_PATH(bp
) ? DUMP_PATH_1
: DUMP_PATH_0
);
995 } else if (CHIP_IS_E3A0(bp
)) {
996 dump_hdr
.dump_meta_data
= DUMP_CHIP_E3A0
|
997 (BP_PATH(bp
) ? DUMP_PATH_1
: DUMP_PATH_0
);
998 } else if (CHIP_IS_E3B0(bp
)) {
999 dump_hdr
.dump_meta_data
= DUMP_CHIP_E3B0
|
1000 (BP_PATH(bp
) ? DUMP_PATH_1
: DUMP_PATH_0
);
1003 memcpy(p
, &dump_hdr
, sizeof(struct dump_header
));
1004 p
+= dump_hdr
.header_size
+ 1;
1006 /* Actually read the registers */
1007 __bnx2x_get_preset_regs(bp
, p
, dump_hdr
.preset
);
1009 /* Re-enable parity attentions */
1010 bnx2x_clear_blocks_parity(bp
);
1011 bnx2x_enable_blocks_parity(bp
);
1016 static void bnx2x_get_drvinfo(struct net_device
*dev
,
1017 struct ethtool_drvinfo
*info
)
1019 struct bnx2x
*bp
= netdev_priv(dev
);
1021 strlcpy(info
->driver
, DRV_MODULE_NAME
, sizeof(info
->driver
));
1022 strlcpy(info
->version
, DRV_MODULE_VERSION
, sizeof(info
->version
));
1024 bnx2x_fill_fw_str(bp
, info
->fw_version
, sizeof(info
->fw_version
));
1026 strlcpy(info
->bus_info
, pci_name(bp
->pdev
), sizeof(info
->bus_info
));
1027 info
->n_stats
= BNX2X_NUM_STATS
;
1028 info
->testinfo_len
= BNX2X_NUM_TESTS(bp
);
1029 info
->eedump_len
= bp
->common
.flash_size
;
1030 info
->regdump_len
= bnx2x_get_regs_len(dev
);
1033 static void bnx2x_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1035 struct bnx2x
*bp
= netdev_priv(dev
);
1037 if (bp
->flags
& NO_WOL_FLAG
) {
1041 wol
->supported
= WAKE_MAGIC
;
1043 wol
->wolopts
= WAKE_MAGIC
;
1047 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1050 static int bnx2x_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1052 struct bnx2x
*bp
= netdev_priv(dev
);
1054 if (wol
->wolopts
& ~WAKE_MAGIC
) {
1055 DP(BNX2X_MSG_ETHTOOL
, "WOL not supported\n");
1059 if (wol
->wolopts
& WAKE_MAGIC
) {
1060 if (bp
->flags
& NO_WOL_FLAG
) {
1061 DP(BNX2X_MSG_ETHTOOL
, "WOL not supported\n");
1071 static u32
bnx2x_get_msglevel(struct net_device
*dev
)
1073 struct bnx2x
*bp
= netdev_priv(dev
);
1075 return bp
->msg_enable
;
1078 static void bnx2x_set_msglevel(struct net_device
*dev
, u32 level
)
1080 struct bnx2x
*bp
= netdev_priv(dev
);
1082 if (capable(CAP_NET_ADMIN
)) {
1083 /* dump MCP trace */
1084 if (IS_PF(bp
) && (level
& BNX2X_MSG_MCP
))
1085 bnx2x_fw_dump_lvl(bp
, KERN_INFO
);
1086 bp
->msg_enable
= level
;
1090 static int bnx2x_nway_reset(struct net_device
*dev
)
1092 struct bnx2x
*bp
= netdev_priv(dev
);
1097 if (netif_running(dev
)) {
1098 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
1099 bnx2x_force_link_reset(bp
);
1106 static u32
bnx2x_get_link(struct net_device
*dev
)
1108 struct bnx2x
*bp
= netdev_priv(dev
);
1110 if (bp
->flags
& MF_FUNC_DIS
|| (bp
->state
!= BNX2X_STATE_OPEN
))
1113 return bp
->link_vars
.link_up
;
1116 static int bnx2x_get_eeprom_len(struct net_device
*dev
)
1118 struct bnx2x
*bp
= netdev_priv(dev
);
1120 return bp
->common
.flash_size
;
1123 /* Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1124 * had we done things the other way around, if two pfs from the same port would
1125 * attempt to access nvram at the same time, we could run into a scenario such
1127 * pf A takes the port lock.
1128 * pf B succeeds in taking the same lock since they are from the same port.
1129 * pf A takes the per pf misc lock. Performs eeprom access.
1130 * pf A finishes. Unlocks the per pf misc lock.
1131 * Pf B takes the lock and proceeds to perform it's own access.
1132 * pf A unlocks the per port lock, while pf B is still working (!).
1133 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1134 * access corrupted by pf B)
1136 static int bnx2x_acquire_nvram_lock(struct bnx2x
*bp
)
1138 int port
= BP_PORT(bp
);
1142 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1143 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_NVRAM
);
1145 /* adjust timeout for emulation/FPGA */
1146 count
= BNX2X_NVRAM_TIMEOUT_COUNT
;
1147 if (CHIP_REV_IS_SLOW(bp
))
1150 /* request access to nvram interface */
1151 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
1152 (MCPR_NVM_SW_ARB_ARB_REQ_SET1
<< port
));
1154 for (i
= 0; i
< count
*10; i
++) {
1155 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_SW_ARB
);
1156 if (val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
))
1162 if (!(val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
))) {
1163 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1164 "cannot get access to nvram interface\n");
1171 static int bnx2x_release_nvram_lock(struct bnx2x
*bp
)
1173 int port
= BP_PORT(bp
);
1177 /* adjust timeout for emulation/FPGA */
1178 count
= BNX2X_NVRAM_TIMEOUT_COUNT
;
1179 if (CHIP_REV_IS_SLOW(bp
))
1182 /* relinquish nvram interface */
1183 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
1184 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1
<< port
));
1186 for (i
= 0; i
< count
*10; i
++) {
1187 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_SW_ARB
);
1188 if (!(val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
)))
1194 if (val
& (MCPR_NVM_SW_ARB_ARB_ARB1
<< port
)) {
1195 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1196 "cannot free access to nvram interface\n");
1200 /* release HW lock: protect against other PFs in PF Direct Assignment */
1201 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_NVRAM
);
1205 static void bnx2x_enable_nvram_access(struct bnx2x
*bp
)
1209 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
);
1211 /* enable both bits, even on read */
1212 REG_WR(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
,
1213 (val
| MCPR_NVM_ACCESS_ENABLE_EN
|
1214 MCPR_NVM_ACCESS_ENABLE_WR_EN
));
1217 static void bnx2x_disable_nvram_access(struct bnx2x
*bp
)
1221 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
);
1223 /* disable both bits, even after read */
1224 REG_WR(bp
, MCP_REG_MCPR_NVM_ACCESS_ENABLE
,
1225 (val
& ~(MCPR_NVM_ACCESS_ENABLE_EN
|
1226 MCPR_NVM_ACCESS_ENABLE_WR_EN
)));
1229 static int bnx2x_nvram_read_dword(struct bnx2x
*bp
, u32 offset
, __be32
*ret_val
,
1235 /* build the command word */
1236 cmd_flags
|= MCPR_NVM_COMMAND_DOIT
;
1238 /* need to clear DONE bit separately */
1239 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, MCPR_NVM_COMMAND_DONE
);
1241 /* address of the NVRAM to read from */
1242 REG_WR(bp
, MCP_REG_MCPR_NVM_ADDR
,
1243 (offset
& MCPR_NVM_ADDR_NVM_ADDR_VALUE
));
1245 /* issue a read command */
1246 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, cmd_flags
);
1248 /* adjust timeout for emulation/FPGA */
1249 count
= BNX2X_NVRAM_TIMEOUT_COUNT
;
1250 if (CHIP_REV_IS_SLOW(bp
))
1253 /* wait for completion */
1256 for (i
= 0; i
< count
; i
++) {
1258 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_COMMAND
);
1260 if (val
& MCPR_NVM_COMMAND_DONE
) {
1261 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_READ
);
1262 /* we read nvram data in cpu order
1263 * but ethtool sees it as an array of bytes
1264 * converting to big-endian will do the work
1266 *ret_val
= cpu_to_be32(val
);
1272 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1273 "nvram read timeout expired\n");
1277 static int bnx2x_nvram_read(struct bnx2x
*bp
, u32 offset
, u8
*ret_buf
,
1284 if ((offset
& 0x03) || (buf_size
& 0x03) || (buf_size
== 0)) {
1285 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1286 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1291 if (offset
+ buf_size
> bp
->common
.flash_size
) {
1292 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1293 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1294 offset
, buf_size
, bp
->common
.flash_size
);
1298 /* request access to nvram interface */
1299 rc
= bnx2x_acquire_nvram_lock(bp
);
1303 /* enable access to nvram interface */
1304 bnx2x_enable_nvram_access(bp
);
1306 /* read the first word(s) */
1307 cmd_flags
= MCPR_NVM_COMMAND_FIRST
;
1308 while ((buf_size
> sizeof(u32
)) && (rc
== 0)) {
1309 rc
= bnx2x_nvram_read_dword(bp
, offset
, &val
, cmd_flags
);
1310 memcpy(ret_buf
, &val
, 4);
1312 /* advance to the next dword */
1313 offset
+= sizeof(u32
);
1314 ret_buf
+= sizeof(u32
);
1315 buf_size
-= sizeof(u32
);
1320 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
1321 rc
= bnx2x_nvram_read_dword(bp
, offset
, &val
, cmd_flags
);
1322 memcpy(ret_buf
, &val
, 4);
1325 /* disable access to nvram interface */
1326 bnx2x_disable_nvram_access(bp
);
1327 bnx2x_release_nvram_lock(bp
);
1332 static int bnx2x_nvram_read32(struct bnx2x
*bp
, u32 offset
, u32
*buf
,
1337 rc
= bnx2x_nvram_read(bp
, offset
, (u8
*)buf
, buf_size
);
1340 __be32
*be
= (__be32
*)buf
;
1342 while ((buf_size
-= 4) >= 0)
1343 *buf
++ = be32_to_cpu(*be
++);
1349 static bool bnx2x_is_nvm_accessible(struct bnx2x
*bp
)
1353 struct net_device
*dev
= pci_get_drvdata(bp
->pdev
);
1355 if (bp
->pdev
->pm_cap
)
1356 rc
= pci_read_config_word(bp
->pdev
,
1357 bp
->pdev
->pm_cap
+ PCI_PM_CTRL
, &pm
);
1359 if ((rc
&& !netif_running(dev
)) ||
1360 (!rc
&& ((pm
& PCI_PM_CTRL_STATE_MASK
) != (__force u16
)PCI_D0
)))
1366 static int bnx2x_get_eeprom(struct net_device
*dev
,
1367 struct ethtool_eeprom
*eeprom
, u8
*eebuf
)
1369 struct bnx2x
*bp
= netdev_priv(dev
);
1371 if (!bnx2x_is_nvm_accessible(bp
)) {
1372 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1373 "cannot access eeprom when the interface is down\n");
1377 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
, "ethtool_eeprom: cmd %d\n"
1378 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1379 eeprom
->cmd
, eeprom
->magic
, eeprom
->offset
, eeprom
->offset
,
1380 eeprom
->len
, eeprom
->len
);
1382 /* parameters already validated in ethtool_get_eeprom */
1384 return bnx2x_nvram_read(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
1387 static int bnx2x_get_module_eeprom(struct net_device
*dev
,
1388 struct ethtool_eeprom
*ee
,
1391 struct bnx2x
*bp
= netdev_priv(dev
);
1392 int rc
= -EINVAL
, phy_idx
;
1393 u8
*user_data
= data
;
1394 unsigned int start_addr
= ee
->offset
, xfer_size
= 0;
1396 if (!bnx2x_is_nvm_accessible(bp
)) {
1397 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1398 "cannot access eeprom when the interface is down\n");
1402 phy_idx
= bnx2x_get_cur_phy_idx(bp
);
1404 /* Read A0 section */
1405 if (start_addr
< ETH_MODULE_SFF_8079_LEN
) {
1406 /* Limit transfer size to the A0 section boundary */
1407 if (start_addr
+ ee
->len
> ETH_MODULE_SFF_8079_LEN
)
1408 xfer_size
= ETH_MODULE_SFF_8079_LEN
- start_addr
;
1410 xfer_size
= ee
->len
;
1411 bnx2x_acquire_phy_lock(bp
);
1412 rc
= bnx2x_read_sfp_module_eeprom(&bp
->link_params
.phy
[phy_idx
],
1418 bnx2x_release_phy_lock(bp
);
1420 DP(BNX2X_MSG_ETHTOOL
, "Failed reading A0 section\n");
1424 user_data
+= xfer_size
;
1425 start_addr
+= xfer_size
;
1428 /* Read A2 section */
1429 if ((start_addr
>= ETH_MODULE_SFF_8079_LEN
) &&
1430 (start_addr
< ETH_MODULE_SFF_8472_LEN
)) {
1431 xfer_size
= ee
->len
- xfer_size
;
1432 /* Limit transfer size to the A2 section boundary */
1433 if (start_addr
+ xfer_size
> ETH_MODULE_SFF_8472_LEN
)
1434 xfer_size
= ETH_MODULE_SFF_8472_LEN
- start_addr
;
1435 start_addr
-= ETH_MODULE_SFF_8079_LEN
;
1436 bnx2x_acquire_phy_lock(bp
);
1437 rc
= bnx2x_read_sfp_module_eeprom(&bp
->link_params
.phy
[phy_idx
],
1443 bnx2x_release_phy_lock(bp
);
1445 DP(BNX2X_MSG_ETHTOOL
, "Failed reading A2 section\n");
1452 static int bnx2x_get_module_info(struct net_device
*dev
,
1453 struct ethtool_modinfo
*modinfo
)
1455 struct bnx2x
*bp
= netdev_priv(dev
);
1457 u8 sff8472_comp
, diag_type
;
1459 if (!bnx2x_is_nvm_accessible(bp
)) {
1460 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1461 "cannot access eeprom when the interface is down\n");
1464 phy_idx
= bnx2x_get_cur_phy_idx(bp
);
1465 bnx2x_acquire_phy_lock(bp
);
1466 rc
= bnx2x_read_sfp_module_eeprom(&bp
->link_params
.phy
[phy_idx
],
1469 SFP_EEPROM_SFF_8472_COMP_ADDR
,
1470 SFP_EEPROM_SFF_8472_COMP_SIZE
,
1472 bnx2x_release_phy_lock(bp
);
1474 DP(BNX2X_MSG_ETHTOOL
, "Failed reading SFF-8472 comp field\n");
1478 bnx2x_acquire_phy_lock(bp
);
1479 rc
= bnx2x_read_sfp_module_eeprom(&bp
->link_params
.phy
[phy_idx
],
1482 SFP_EEPROM_DIAG_TYPE_ADDR
,
1483 SFP_EEPROM_DIAG_TYPE_SIZE
,
1485 bnx2x_release_phy_lock(bp
);
1487 DP(BNX2X_MSG_ETHTOOL
, "Failed reading Diag Type field\n");
1491 if (!sff8472_comp
||
1492 (diag_type
& SFP_EEPROM_DIAG_ADDR_CHANGE_REQ
)) {
1493 modinfo
->type
= ETH_MODULE_SFF_8079
;
1494 modinfo
->eeprom_len
= ETH_MODULE_SFF_8079_LEN
;
1496 modinfo
->type
= ETH_MODULE_SFF_8472
;
1497 modinfo
->eeprom_len
= ETH_MODULE_SFF_8472_LEN
;
1502 static int bnx2x_nvram_write_dword(struct bnx2x
*bp
, u32 offset
, u32 val
,
1507 /* build the command word */
1508 cmd_flags
|= MCPR_NVM_COMMAND_DOIT
| MCPR_NVM_COMMAND_WR
;
1510 /* need to clear DONE bit separately */
1511 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, MCPR_NVM_COMMAND_DONE
);
1513 /* write the data */
1514 REG_WR(bp
, MCP_REG_MCPR_NVM_WRITE
, val
);
1516 /* address of the NVRAM to write to */
1517 REG_WR(bp
, MCP_REG_MCPR_NVM_ADDR
,
1518 (offset
& MCPR_NVM_ADDR_NVM_ADDR_VALUE
));
1520 /* issue the write command */
1521 REG_WR(bp
, MCP_REG_MCPR_NVM_COMMAND
, cmd_flags
);
1523 /* adjust timeout for emulation/FPGA */
1524 count
= BNX2X_NVRAM_TIMEOUT_COUNT
;
1525 if (CHIP_REV_IS_SLOW(bp
))
1528 /* wait for completion */
1530 for (i
= 0; i
< count
; i
++) {
1532 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_COMMAND
);
1533 if (val
& MCPR_NVM_COMMAND_DONE
) {
1540 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1541 "nvram write timeout expired\n");
1545 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1547 static int bnx2x_nvram_write1(struct bnx2x
*bp
, u32 offset
, u8
*data_buf
,
1551 u32 cmd_flags
, align_offset
, val
;
1554 if (offset
+ buf_size
> bp
->common
.flash_size
) {
1555 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1556 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1557 offset
, buf_size
, bp
->common
.flash_size
);
1561 /* request access to nvram interface */
1562 rc
= bnx2x_acquire_nvram_lock(bp
);
1566 /* enable access to nvram interface */
1567 bnx2x_enable_nvram_access(bp
);
1569 cmd_flags
= (MCPR_NVM_COMMAND_FIRST
| MCPR_NVM_COMMAND_LAST
);
1570 align_offset
= (offset
& ~0x03);
1571 rc
= bnx2x_nvram_read_dword(bp
, align_offset
, &val_be
, cmd_flags
);
1574 /* nvram data is returned as an array of bytes
1575 * convert it back to cpu order
1577 val
= be32_to_cpu(val_be
);
1579 val
&= ~le32_to_cpu((__force __le32
)
1580 (0xff << BYTE_OFFSET(offset
)));
1581 val
|= le32_to_cpu((__force __le32
)
1582 (*data_buf
<< BYTE_OFFSET(offset
)));
1584 rc
= bnx2x_nvram_write_dword(bp
, align_offset
, val
,
1588 /* disable access to nvram interface */
1589 bnx2x_disable_nvram_access(bp
);
1590 bnx2x_release_nvram_lock(bp
);
1595 static int bnx2x_nvram_write(struct bnx2x
*bp
, u32 offset
, u8
*data_buf
,
1603 if (buf_size
== 1) /* ethtool */
1604 return bnx2x_nvram_write1(bp
, offset
, data_buf
, buf_size
);
1606 if ((offset
& 0x03) || (buf_size
& 0x03) || (buf_size
== 0)) {
1607 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1608 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1613 if (offset
+ buf_size
> bp
->common
.flash_size
) {
1614 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1615 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1616 offset
, buf_size
, bp
->common
.flash_size
);
1620 /* request access to nvram interface */
1621 rc
= bnx2x_acquire_nvram_lock(bp
);
1625 /* enable access to nvram interface */
1626 bnx2x_enable_nvram_access(bp
);
1629 cmd_flags
= MCPR_NVM_COMMAND_FIRST
;
1630 while ((written_so_far
< buf_size
) && (rc
== 0)) {
1631 if (written_so_far
== (buf_size
- sizeof(u32
)))
1632 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
1633 else if (((offset
+ 4) % BNX2X_NVRAM_PAGE_SIZE
) == 0)
1634 cmd_flags
|= MCPR_NVM_COMMAND_LAST
;
1635 else if ((offset
% BNX2X_NVRAM_PAGE_SIZE
) == 0)
1636 cmd_flags
|= MCPR_NVM_COMMAND_FIRST
;
1638 memcpy(&val
, data_buf
, 4);
1640 /* Notice unlike bnx2x_nvram_read_dword() this will not
1641 * change val using be32_to_cpu(), which causes data to flip
1642 * if the eeprom is read and then written back. This is due
1643 * to tools utilizing this functionality that would break
1644 * if this would be resolved.
1646 rc
= bnx2x_nvram_write_dword(bp
, offset
, val
, cmd_flags
);
1648 /* advance to the next dword */
1649 offset
+= sizeof(u32
);
1650 data_buf
+= sizeof(u32
);
1651 written_so_far
+= sizeof(u32
);
1655 /* disable access to nvram interface */
1656 bnx2x_disable_nvram_access(bp
);
1657 bnx2x_release_nvram_lock(bp
);
1662 static int bnx2x_set_eeprom(struct net_device
*dev
,
1663 struct ethtool_eeprom
*eeprom
, u8
*eebuf
)
1665 struct bnx2x
*bp
= netdev_priv(dev
);
1666 int port
= BP_PORT(bp
);
1670 if (!bnx2x_is_nvm_accessible(bp
)) {
1671 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1672 "cannot access eeprom when the interface is down\n");
1676 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
, "ethtool_eeprom: cmd %d\n"
1677 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1678 eeprom
->cmd
, eeprom
->magic
, eeprom
->offset
, eeprom
->offset
,
1679 eeprom
->len
, eeprom
->len
);
1681 /* parameters already validated in ethtool_set_eeprom */
1683 /* PHY eeprom can be accessed only by the PMF */
1684 if ((eeprom
->magic
>= 0x50485900) && (eeprom
->magic
<= 0x504859FF) &&
1686 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
1687 "wrong magic or interface is not pmf\n");
1693 dev_info
.port_hw_config
[port
].external_phy_config
);
1695 if (eeprom
->magic
== 0x50485950) {
1696 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1697 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
1699 bnx2x_acquire_phy_lock(bp
);
1700 rc
|= bnx2x_link_reset(&bp
->link_params
,
1702 if (XGXS_EXT_PHY_TYPE(ext_phy_config
) ==
1703 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
)
1704 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
1705 MISC_REGISTERS_GPIO_HIGH
, port
);
1706 bnx2x_release_phy_lock(bp
);
1707 bnx2x_link_report(bp
);
1709 } else if (eeprom
->magic
== 0x50485952) {
1710 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1711 if (bp
->state
== BNX2X_STATE_OPEN
) {
1712 bnx2x_acquire_phy_lock(bp
);
1713 rc
|= bnx2x_link_reset(&bp
->link_params
,
1716 rc
|= bnx2x_phy_init(&bp
->link_params
,
1718 bnx2x_release_phy_lock(bp
);
1719 bnx2x_calc_fc_adv(bp
);
1721 } else if (eeprom
->magic
== 0x53985943) {
1722 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1723 if (XGXS_EXT_PHY_TYPE(ext_phy_config
) ==
1724 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
) {
1726 /* DSP Remove Download Mode */
1727 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
1728 MISC_REGISTERS_GPIO_LOW
, port
);
1730 bnx2x_acquire_phy_lock(bp
);
1732 bnx2x_sfx7101_sp_sw_reset(bp
,
1733 &bp
->link_params
.phy
[EXT_PHY1
]);
1735 /* wait 0.5 sec to allow it to run */
1737 bnx2x_ext_phy_hw_reset(bp
, port
);
1739 bnx2x_release_phy_lock(bp
);
1742 rc
= bnx2x_nvram_write(bp
, eeprom
->offset
, eebuf
, eeprom
->len
);
1747 static int bnx2x_get_coalesce(struct net_device
*dev
,
1748 struct ethtool_coalesce
*coal
)
1750 struct bnx2x
*bp
= netdev_priv(dev
);
1752 memset(coal
, 0, sizeof(struct ethtool_coalesce
));
1754 coal
->rx_coalesce_usecs
= bp
->rx_ticks
;
1755 coal
->tx_coalesce_usecs
= bp
->tx_ticks
;
1760 static int bnx2x_set_coalesce(struct net_device
*dev
,
1761 struct ethtool_coalesce
*coal
)
1763 struct bnx2x
*bp
= netdev_priv(dev
);
1765 bp
->rx_ticks
= (u16
)coal
->rx_coalesce_usecs
;
1766 if (bp
->rx_ticks
> BNX2X_MAX_COALESCE_TOUT
)
1767 bp
->rx_ticks
= BNX2X_MAX_COALESCE_TOUT
;
1769 bp
->tx_ticks
= (u16
)coal
->tx_coalesce_usecs
;
1770 if (bp
->tx_ticks
> BNX2X_MAX_COALESCE_TOUT
)
1771 bp
->tx_ticks
= BNX2X_MAX_COALESCE_TOUT
;
1773 if (netif_running(dev
))
1774 bnx2x_update_coalesce(bp
);
1779 static void bnx2x_get_ringparam(struct net_device
*dev
,
1780 struct ethtool_ringparam
*ering
)
1782 struct bnx2x
*bp
= netdev_priv(dev
);
1784 ering
->rx_max_pending
= MAX_RX_AVAIL
;
1786 if (bp
->rx_ring_size
)
1787 ering
->rx_pending
= bp
->rx_ring_size
;
1789 ering
->rx_pending
= MAX_RX_AVAIL
;
1791 ering
->tx_max_pending
= IS_MF_FCOE_AFEX(bp
) ? 0 : MAX_TX_AVAIL
;
1792 ering
->tx_pending
= bp
->tx_ring_size
;
1795 static int bnx2x_set_ringparam(struct net_device
*dev
,
1796 struct ethtool_ringparam
*ering
)
1798 struct bnx2x
*bp
= netdev_priv(dev
);
1800 DP(BNX2X_MSG_ETHTOOL
,
1801 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1802 ering
->rx_pending
, ering
->tx_pending
);
1804 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
1805 DP(BNX2X_MSG_ETHTOOL
,
1806 "Handling parity error recovery. Try again later\n");
1810 if ((ering
->rx_pending
> MAX_RX_AVAIL
) ||
1811 (ering
->rx_pending
< (bp
->disable_tpa
? MIN_RX_SIZE_NONTPA
:
1812 MIN_RX_SIZE_TPA
)) ||
1813 (ering
->tx_pending
> (IS_MF_FCOE_AFEX(bp
) ? 0 : MAX_TX_AVAIL
)) ||
1814 (ering
->tx_pending
<= MAX_SKB_FRAGS
+ 4)) {
1815 DP(BNX2X_MSG_ETHTOOL
, "Command parameters not supported\n");
1819 bp
->rx_ring_size
= ering
->rx_pending
;
1820 bp
->tx_ring_size
= ering
->tx_pending
;
1822 return bnx2x_reload_if_running(dev
);
1825 static void bnx2x_get_pauseparam(struct net_device
*dev
,
1826 struct ethtool_pauseparam
*epause
)
1828 struct bnx2x
*bp
= netdev_priv(dev
);
1829 int cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
1832 epause
->autoneg
= (bp
->link_params
.req_flow_ctrl
[cfg_idx
] ==
1833 BNX2X_FLOW_CTRL_AUTO
);
1835 if (!epause
->autoneg
)
1836 cfg_reg
= bp
->link_params
.req_flow_ctrl
[cfg_idx
];
1838 cfg_reg
= bp
->link_params
.req_fc_auto_adv
;
1840 epause
->rx_pause
= ((cfg_reg
& BNX2X_FLOW_CTRL_RX
) ==
1841 BNX2X_FLOW_CTRL_RX
);
1842 epause
->tx_pause
= ((cfg_reg
& BNX2X_FLOW_CTRL_TX
) ==
1843 BNX2X_FLOW_CTRL_TX
);
1845 DP(BNX2X_MSG_ETHTOOL
, "ethtool_pauseparam: cmd %d\n"
1846 " autoneg %d rx_pause %d tx_pause %d\n",
1847 epause
->cmd
, epause
->autoneg
, epause
->rx_pause
, epause
->tx_pause
);
1850 static int bnx2x_set_pauseparam(struct net_device
*dev
,
1851 struct ethtool_pauseparam
*epause
)
1853 struct bnx2x
*bp
= netdev_priv(dev
);
1854 u32 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
1858 DP(BNX2X_MSG_ETHTOOL
, "ethtool_pauseparam: cmd %d\n"
1859 " autoneg %d rx_pause %d tx_pause %d\n",
1860 epause
->cmd
, epause
->autoneg
, epause
->rx_pause
, epause
->tx_pause
);
1862 bp
->link_params
.req_flow_ctrl
[cfg_idx
] = BNX2X_FLOW_CTRL_AUTO
;
1864 if (epause
->rx_pause
)
1865 bp
->link_params
.req_flow_ctrl
[cfg_idx
] |= BNX2X_FLOW_CTRL_RX
;
1867 if (epause
->tx_pause
)
1868 bp
->link_params
.req_flow_ctrl
[cfg_idx
] |= BNX2X_FLOW_CTRL_TX
;
1870 if (bp
->link_params
.req_flow_ctrl
[cfg_idx
] == BNX2X_FLOW_CTRL_AUTO
)
1871 bp
->link_params
.req_flow_ctrl
[cfg_idx
] = BNX2X_FLOW_CTRL_NONE
;
1873 if (epause
->autoneg
) {
1874 if (!(bp
->port
.supported
[cfg_idx
] & SUPPORTED_Autoneg
)) {
1875 DP(BNX2X_MSG_ETHTOOL
, "autoneg not supported\n");
1879 if (bp
->link_params
.req_line_speed
[cfg_idx
] == SPEED_AUTO_NEG
) {
1880 bp
->link_params
.req_flow_ctrl
[cfg_idx
] =
1881 BNX2X_FLOW_CTRL_AUTO
;
1883 bp
->link_params
.req_fc_auto_adv
= 0;
1884 if (epause
->rx_pause
)
1885 bp
->link_params
.req_fc_auto_adv
|= BNX2X_FLOW_CTRL_RX
;
1887 if (epause
->tx_pause
)
1888 bp
->link_params
.req_fc_auto_adv
|= BNX2X_FLOW_CTRL_TX
;
1890 if (!bp
->link_params
.req_fc_auto_adv
)
1891 bp
->link_params
.req_fc_auto_adv
|= BNX2X_FLOW_CTRL_NONE
;
1894 DP(BNX2X_MSG_ETHTOOL
,
1895 "req_flow_ctrl 0x%x\n", bp
->link_params
.req_flow_ctrl
[cfg_idx
]);
1897 if (netif_running(dev
)) {
1898 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
1905 static const char bnx2x_tests_str_arr
[BNX2X_NUM_TESTS_SF
][ETH_GSTRING_LEN
] = {
1906 "register_test (offline) ",
1907 "memory_test (offline) ",
1908 "int_loopback_test (offline)",
1909 "ext_loopback_test (offline)",
1910 "nvram_test (online) ",
1911 "interrupt_test (online) ",
1912 "link_test (online) "
1916 BNX2X_PRI_FLAG_ISCSI
,
1917 BNX2X_PRI_FLAG_FCOE
,
1918 BNX2X_PRI_FLAG_STORAGE
,
1922 static const char bnx2x_private_arr
[BNX2X_PRI_FLAG_LEN
][ETH_GSTRING_LEN
] = {
1923 "iSCSI offload support",
1924 "FCoE offload support",
1925 "Storage only interface"
1928 static u32
bnx2x_eee_to_adv(u32 eee_adv
)
1932 if (eee_adv
& SHMEM_EEE_100M_ADV
)
1933 modes
|= ADVERTISED_100baseT_Full
;
1934 if (eee_adv
& SHMEM_EEE_1G_ADV
)
1935 modes
|= ADVERTISED_1000baseT_Full
;
1936 if (eee_adv
& SHMEM_EEE_10G_ADV
)
1937 modes
|= ADVERTISED_10000baseT_Full
;
1942 static u32
bnx2x_adv_to_eee(u32 modes
, u32 shift
)
1945 if (modes
& ADVERTISED_100baseT_Full
)
1946 eee_adv
|= SHMEM_EEE_100M_ADV
;
1947 if (modes
& ADVERTISED_1000baseT_Full
)
1948 eee_adv
|= SHMEM_EEE_1G_ADV
;
1949 if (modes
& ADVERTISED_10000baseT_Full
)
1950 eee_adv
|= SHMEM_EEE_10G_ADV
;
1952 return eee_adv
<< shift
;
1955 static int bnx2x_get_eee(struct net_device
*dev
, struct ethtool_eee
*edata
)
1957 struct bnx2x
*bp
= netdev_priv(dev
);
1960 if (!SHMEM2_HAS(bp
, eee_status
[BP_PORT(bp
)])) {
1961 DP(BNX2X_MSG_ETHTOOL
, "BC Version does not support EEE\n");
1965 eee_cfg
= bp
->link_vars
.eee_status
;
1968 bnx2x_eee_to_adv((eee_cfg
& SHMEM_EEE_SUPPORTED_MASK
) >>
1969 SHMEM_EEE_SUPPORTED_SHIFT
);
1972 bnx2x_eee_to_adv((eee_cfg
& SHMEM_EEE_ADV_STATUS_MASK
) >>
1973 SHMEM_EEE_ADV_STATUS_SHIFT
);
1974 edata
->lp_advertised
=
1975 bnx2x_eee_to_adv((eee_cfg
& SHMEM_EEE_LP_ADV_STATUS_MASK
) >>
1976 SHMEM_EEE_LP_ADV_STATUS_SHIFT
);
1978 /* SHMEM value is in 16u units --> Convert to 1u units. */
1979 edata
->tx_lpi_timer
= (eee_cfg
& SHMEM_EEE_TIMER_MASK
) << 4;
1981 edata
->eee_enabled
= (eee_cfg
& SHMEM_EEE_REQUESTED_BIT
) ? 1 : 0;
1982 edata
->eee_active
= (eee_cfg
& SHMEM_EEE_ACTIVE_BIT
) ? 1 : 0;
1983 edata
->tx_lpi_enabled
= (eee_cfg
& SHMEM_EEE_LPI_REQUESTED_BIT
) ? 1 : 0;
1988 static int bnx2x_set_eee(struct net_device
*dev
, struct ethtool_eee
*edata
)
1990 struct bnx2x
*bp
= netdev_priv(dev
);
1997 if (!SHMEM2_HAS(bp
, eee_status
[BP_PORT(bp
)])) {
1998 DP(BNX2X_MSG_ETHTOOL
, "BC Version does not support EEE\n");
2002 eee_cfg
= bp
->link_vars
.eee_status
;
2004 if (!(eee_cfg
& SHMEM_EEE_SUPPORTED_MASK
)) {
2005 DP(BNX2X_MSG_ETHTOOL
, "Board does not support EEE!\n");
2009 advertised
= bnx2x_adv_to_eee(edata
->advertised
,
2010 SHMEM_EEE_ADV_STATUS_SHIFT
);
2011 if ((advertised
!= (eee_cfg
& SHMEM_EEE_ADV_STATUS_MASK
))) {
2012 DP(BNX2X_MSG_ETHTOOL
,
2013 "Direct manipulation of EEE advertisement is not supported\n");
2017 if (edata
->tx_lpi_timer
> EEE_MODE_TIMER_MASK
) {
2018 DP(BNX2X_MSG_ETHTOOL
,
2019 "Maximal Tx Lpi timer supported is %x(u)\n",
2020 EEE_MODE_TIMER_MASK
);
2023 if (edata
->tx_lpi_enabled
&&
2024 (edata
->tx_lpi_timer
< EEE_MODE_NVRAM_AGGRESSIVE_TIME
)) {
2025 DP(BNX2X_MSG_ETHTOOL
,
2026 "Minimal Tx Lpi timer supported is %d(u)\n",
2027 EEE_MODE_NVRAM_AGGRESSIVE_TIME
);
2031 /* All is well; Apply changes*/
2032 if (edata
->eee_enabled
)
2033 bp
->link_params
.eee_mode
|= EEE_MODE_ADV_LPI
;
2035 bp
->link_params
.eee_mode
&= ~EEE_MODE_ADV_LPI
;
2037 if (edata
->tx_lpi_enabled
)
2038 bp
->link_params
.eee_mode
|= EEE_MODE_ENABLE_LPI
;
2040 bp
->link_params
.eee_mode
&= ~EEE_MODE_ENABLE_LPI
;
2042 bp
->link_params
.eee_mode
&= ~EEE_MODE_TIMER_MASK
;
2043 bp
->link_params
.eee_mode
|= (edata
->tx_lpi_timer
&
2044 EEE_MODE_TIMER_MASK
) |
2045 EEE_MODE_OVERRIDE_NVRAM
|
2046 EEE_MODE_OUTPUT_TIME
;
2048 /* Restart link to propagate changes */
2049 if (netif_running(dev
)) {
2050 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2051 bnx2x_force_link_reset(bp
);
2059 BNX2X_CHIP_E1_OFST
= 0,
2060 BNX2X_CHIP_E1H_OFST
,
2063 BNX2X_CHIP_E3B0_OFST
,
2067 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2068 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2069 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2070 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2071 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2073 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2074 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2076 static int bnx2x_test_registers(struct bnx2x
*bp
)
2078 int idx
, i
, rc
= -ENODEV
;
2080 int port
= BP_PORT(bp
);
2081 static const struct {
2087 /* 0 */ { BNX2X_CHIP_MASK_ALL
,
2088 BRB1_REG_PAUSE_LOW_THRESHOLD_0
, 4, 0x000003ff },
2089 { BNX2X_CHIP_MASK_ALL
,
2090 DORQ_REG_DB_ADDR0
, 4, 0xffffffff },
2091 { BNX2X_CHIP_MASK_E1X
,
2092 HC_REG_AGG_INT_0
, 4, 0x000003ff },
2093 { BNX2X_CHIP_MASK_ALL
,
2094 PBF_REG_MAC_IF0_ENABLE
, 4, 0x00000001 },
2095 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
| BNX2X_CHIP_MASK_E3
,
2096 PBF_REG_P0_INIT_CRD
, 4, 0x000007ff },
2097 { BNX2X_CHIP_MASK_E3B0
,
2098 PBF_REG_INIT_CRD_Q0
, 4, 0x000007ff },
2099 { BNX2X_CHIP_MASK_ALL
,
2100 PRS_REG_CID_PORT_0
, 4, 0x00ffffff },
2101 { BNX2X_CHIP_MASK_ALL
,
2102 PXP2_REG_PSWRQ_CDU0_L2P
, 4, 0x000fffff },
2103 { BNX2X_CHIP_MASK_ALL
,
2104 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR
, 8, 0x0003ffff },
2105 { BNX2X_CHIP_MASK_ALL
,
2106 PXP2_REG_PSWRQ_TM0_L2P
, 4, 0x000fffff },
2107 /* 10 */ { BNX2X_CHIP_MASK_ALL
,
2108 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR
, 8, 0x0003ffff },
2109 { BNX2X_CHIP_MASK_ALL
,
2110 PXP2_REG_PSWRQ_TSDM0_L2P
, 4, 0x000fffff },
2111 { BNX2X_CHIP_MASK_ALL
,
2112 QM_REG_CONNNUM_0
, 4, 0x000fffff },
2113 { BNX2X_CHIP_MASK_ALL
,
2114 TM_REG_LIN0_MAX_ACTIVE_CID
, 4, 0x0003ffff },
2115 { BNX2X_CHIP_MASK_ALL
,
2116 SRC_REG_KEYRSS0_0
, 40, 0xffffffff },
2117 { BNX2X_CHIP_MASK_ALL
,
2118 SRC_REG_KEYRSS0_7
, 40, 0xffffffff },
2119 { BNX2X_CHIP_MASK_ALL
,
2120 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00
, 4, 0x00000001 },
2121 { BNX2X_CHIP_MASK_ALL
,
2122 XCM_REG_WU_DA_CNT_CMD00
, 4, 0x00000003 },
2123 { BNX2X_CHIP_MASK_ALL
,
2124 XCM_REG_GLB_DEL_ACK_MAX_CNT_0
, 4, 0x000000ff },
2125 { BNX2X_CHIP_MASK_ALL
,
2126 NIG_REG_LLH0_T_BIT
, 4, 0x00000001 },
2127 /* 20 */ { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
2128 NIG_REG_EMAC0_IN_EN
, 4, 0x00000001 },
2129 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
2130 NIG_REG_BMAC0_IN_EN
, 4, 0x00000001 },
2131 { BNX2X_CHIP_MASK_ALL
,
2132 NIG_REG_XCM0_OUT_EN
, 4, 0x00000001 },
2133 { BNX2X_CHIP_MASK_ALL
,
2134 NIG_REG_BRB0_OUT_EN
, 4, 0x00000001 },
2135 { BNX2X_CHIP_MASK_ALL
,
2136 NIG_REG_LLH0_XCM_MASK
, 4, 0x00000007 },
2137 { BNX2X_CHIP_MASK_ALL
,
2138 NIG_REG_LLH0_ACPI_PAT_6_LEN
, 68, 0x000000ff },
2139 { BNX2X_CHIP_MASK_ALL
,
2140 NIG_REG_LLH0_ACPI_PAT_0_CRC
, 68, 0xffffffff },
2141 { BNX2X_CHIP_MASK_ALL
,
2142 NIG_REG_LLH0_DEST_MAC_0_0
, 160, 0xffffffff },
2143 { BNX2X_CHIP_MASK_ALL
,
2144 NIG_REG_LLH0_DEST_IP_0_1
, 160, 0xffffffff },
2145 { BNX2X_CHIP_MASK_ALL
,
2146 NIG_REG_LLH0_IPV4_IPV6_0
, 160, 0x00000001 },
2147 /* 30 */ { BNX2X_CHIP_MASK_ALL
,
2148 NIG_REG_LLH0_DEST_UDP_0
, 160, 0x0000ffff },
2149 { BNX2X_CHIP_MASK_ALL
,
2150 NIG_REG_LLH0_DEST_TCP_0
, 160, 0x0000ffff },
2151 { BNX2X_CHIP_MASK_ALL
,
2152 NIG_REG_LLH0_VLAN_ID_0
, 160, 0x00000fff },
2153 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
2154 NIG_REG_XGXS_SERDES0_MODE_SEL
, 4, 0x00000001 },
2155 { BNX2X_CHIP_MASK_ALL
,
2156 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
, 4, 0x00000001},
2157 { BNX2X_CHIP_MASK_ALL
,
2158 NIG_REG_STATUS_INTERRUPT_PORT0
, 4, 0x07ffffff },
2159 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
2160 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST
, 24, 0x00000001 },
2161 { BNX2X_CHIP_MASK_E1X
| BNX2X_CHIP_MASK_E2
,
2162 NIG_REG_SERDES0_CTRL_PHY_ADDR
, 16, 0x0000001f },
2164 { BNX2X_CHIP_MASK_ALL
, 0xffffffff, 0, 0x00000000 }
2167 if (!bnx2x_is_nvm_accessible(bp
)) {
2168 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2169 "cannot access eeprom when the interface is down\n");
2174 hw
= BNX2X_CHIP_MASK_E1
;
2175 else if (CHIP_IS_E1H(bp
))
2176 hw
= BNX2X_CHIP_MASK_E1H
;
2177 else if (CHIP_IS_E2(bp
))
2178 hw
= BNX2X_CHIP_MASK_E2
;
2179 else if (CHIP_IS_E3B0(bp
))
2180 hw
= BNX2X_CHIP_MASK_E3B0
;
2182 hw
= BNX2X_CHIP_MASK_E3
;
2184 /* Repeat the test twice:
2185 * First by writing 0x00000000, second by writing 0xffffffff
2187 for (idx
= 0; idx
< 2; idx
++) {
2194 wr_val
= 0xffffffff;
2198 for (i
= 0; reg_tbl
[i
].offset0
!= 0xffffffff; i
++) {
2199 u32 offset
, mask
, save_val
, val
;
2200 if (!(hw
& reg_tbl
[i
].hw
))
2203 offset
= reg_tbl
[i
].offset0
+ port
*reg_tbl
[i
].offset1
;
2204 mask
= reg_tbl
[i
].mask
;
2206 save_val
= REG_RD(bp
, offset
);
2208 REG_WR(bp
, offset
, wr_val
& mask
);
2210 val
= REG_RD(bp
, offset
);
2212 /* Restore the original register's value */
2213 REG_WR(bp
, offset
, save_val
);
2215 /* verify value is as expected */
2216 if ((val
& mask
) != (wr_val
& mask
)) {
2217 DP(BNX2X_MSG_ETHTOOL
,
2218 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2219 offset
, val
, wr_val
, mask
);
2231 static int bnx2x_test_memory(struct bnx2x
*bp
)
2233 int i
, j
, rc
= -ENODEV
;
2235 static const struct {
2239 { CCM_REG_XX_DESCR_TABLE
, CCM_REG_XX_DESCR_TABLE_SIZE
},
2240 { CFC_REG_ACTIVITY_COUNTER
, CFC_REG_ACTIVITY_COUNTER_SIZE
},
2241 { CFC_REG_LINK_LIST
, CFC_REG_LINK_LIST_SIZE
},
2242 { DMAE_REG_CMD_MEM
, DMAE_REG_CMD_MEM_SIZE
},
2243 { TCM_REG_XX_DESCR_TABLE
, TCM_REG_XX_DESCR_TABLE_SIZE
},
2244 { UCM_REG_XX_DESCR_TABLE
, UCM_REG_XX_DESCR_TABLE_SIZE
},
2245 { XCM_REG_XX_DESCR_TABLE
, XCM_REG_XX_DESCR_TABLE_SIZE
},
2250 static const struct {
2253 u32 hw_mask
[BNX2X_CHIP_MAX_OFST
];
2255 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS
,
2256 {0x3ffc0, 0, 0, 0} },
2257 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS
,
2259 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS
,
2261 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS
,
2262 {0x3ffc0, 0, 0, 0} },
2263 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS
,
2264 {0x3ffc0, 0, 0, 0} },
2265 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS
,
2266 {0x3ffc1, 0, 0, 0} },
2268 { NULL
, 0xffffffff, {0, 0, 0, 0} }
2271 if (!bnx2x_is_nvm_accessible(bp
)) {
2272 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2273 "cannot access eeprom when the interface is down\n");
2278 index
= BNX2X_CHIP_E1_OFST
;
2279 else if (CHIP_IS_E1H(bp
))
2280 index
= BNX2X_CHIP_E1H_OFST
;
2281 else if (CHIP_IS_E2(bp
))
2282 index
= BNX2X_CHIP_E2_OFST
;
2284 index
= BNX2X_CHIP_E3_OFST
;
2286 /* pre-Check the parity status */
2287 for (i
= 0; prty_tbl
[i
].offset
!= 0xffffffff; i
++) {
2288 val
= REG_RD(bp
, prty_tbl
[i
].offset
);
2289 if (val
& ~(prty_tbl
[i
].hw_mask
[index
])) {
2290 DP(BNX2X_MSG_ETHTOOL
,
2291 "%s is 0x%x\n", prty_tbl
[i
].name
, val
);
2296 /* Go through all the memories */
2297 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++)
2298 for (j
= 0; j
< mem_tbl
[i
].size
; j
++)
2299 REG_RD(bp
, mem_tbl
[i
].offset
+ j
*4);
2301 /* Check the parity status */
2302 for (i
= 0; prty_tbl
[i
].offset
!= 0xffffffff; i
++) {
2303 val
= REG_RD(bp
, prty_tbl
[i
].offset
);
2304 if (val
& ~(prty_tbl
[i
].hw_mask
[index
])) {
2305 DP(BNX2X_MSG_ETHTOOL
,
2306 "%s is 0x%x\n", prty_tbl
[i
].name
, val
);
2317 static void bnx2x_wait_for_link(struct bnx2x
*bp
, u8 link_up
, u8 is_serdes
)
2322 while (bnx2x_link_test(bp
, is_serdes
) && cnt
--)
2325 if (cnt
<= 0 && bnx2x_link_test(bp
, is_serdes
))
2326 DP(BNX2X_MSG_ETHTOOL
, "Timeout waiting for link up\n");
2329 while (!bp
->link_vars
.link_up
&& cnt
--)
2332 if (cnt
<= 0 && !bp
->link_vars
.link_up
)
2333 DP(BNX2X_MSG_ETHTOOL
,
2334 "Timeout waiting for link init\n");
2338 static int bnx2x_run_loopback(struct bnx2x
*bp
, int loopback_mode
)
2340 unsigned int pkt_size
, num_pkts
, i
;
2341 struct sk_buff
*skb
;
2342 unsigned char *packet
;
2343 struct bnx2x_fastpath
*fp_rx
= &bp
->fp
[0];
2344 struct bnx2x_fastpath
*fp_tx
= &bp
->fp
[0];
2345 struct bnx2x_fp_txdata
*txdata
= fp_tx
->txdata_ptr
[0];
2346 u16 tx_start_idx
, tx_idx
;
2347 u16 rx_start_idx
, rx_idx
;
2348 u16 pkt_prod
, bd_prod
;
2349 struct sw_tx_bd
*tx_buf
;
2350 struct eth_tx_start_bd
*tx_start_bd
;
2352 union eth_rx_cqe
*cqe
;
2353 u8 cqe_fp_flags
, cqe_fp_type
;
2354 struct sw_rx_bd
*rx_buf
;
2358 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
,
2361 /* check the loopback mode */
2362 switch (loopback_mode
) {
2363 case BNX2X_PHY_LOOPBACK
:
2364 if (bp
->link_params
.loopback_mode
!= LOOPBACK_XGXS
) {
2365 DP(BNX2X_MSG_ETHTOOL
, "PHY loopback not supported\n");
2369 case BNX2X_MAC_LOOPBACK
:
2370 if (CHIP_IS_E3(bp
)) {
2371 int cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2372 if (bp
->port
.supported
[cfg_idx
] &
2373 (SUPPORTED_10000baseT_Full
|
2374 SUPPORTED_20000baseMLD2_Full
|
2375 SUPPORTED_20000baseKR2_Full
))
2376 bp
->link_params
.loopback_mode
= LOOPBACK_XMAC
;
2378 bp
->link_params
.loopback_mode
= LOOPBACK_UMAC
;
2380 bp
->link_params
.loopback_mode
= LOOPBACK_BMAC
;
2382 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2384 case BNX2X_EXT_LOOPBACK
:
2385 if (bp
->link_params
.loopback_mode
!= LOOPBACK_EXT
) {
2386 DP(BNX2X_MSG_ETHTOOL
,
2387 "Can't configure external loopback\n");
2392 DP(BNX2X_MSG_ETHTOOL
, "Command parameters not supported\n");
2396 /* prepare the loopback packet */
2397 pkt_size
= (((bp
->dev
->mtu
< ETH_MAX_PACKET_SIZE
) ?
2398 bp
->dev
->mtu
: ETH_MAX_PACKET_SIZE
) + ETH_HLEN
);
2399 skb
= netdev_alloc_skb(bp
->dev
, fp_rx
->rx_buf_size
);
2401 DP(BNX2X_MSG_ETHTOOL
, "Can't allocate skb\n");
2403 goto test_loopback_exit
;
2405 packet
= skb_put(skb
, pkt_size
);
2406 memcpy(packet
, bp
->dev
->dev_addr
, ETH_ALEN
);
2407 memset(packet
+ ETH_ALEN
, 0, ETH_ALEN
);
2408 memset(packet
+ 2*ETH_ALEN
, 0x77, (ETH_HLEN
- 2*ETH_ALEN
));
2409 for (i
= ETH_HLEN
; i
< pkt_size
; i
++)
2410 packet
[i
] = (unsigned char) (i
& 0xff);
2411 mapping
= dma_map_single(&bp
->pdev
->dev
, skb
->data
,
2412 skb_headlen(skb
), DMA_TO_DEVICE
);
2413 if (unlikely(dma_mapping_error(&bp
->pdev
->dev
, mapping
))) {
2416 DP(BNX2X_MSG_ETHTOOL
, "Unable to map SKB\n");
2417 goto test_loopback_exit
;
2420 /* send the loopback packet */
2422 tx_start_idx
= le16_to_cpu(*txdata
->tx_cons_sb
);
2423 rx_start_idx
= le16_to_cpu(*fp_rx
->rx_cons_sb
);
2425 netdev_tx_sent_queue(txq
, skb
->len
);
2427 pkt_prod
= txdata
->tx_pkt_prod
++;
2428 tx_buf
= &txdata
->tx_buf_ring
[TX_BD(pkt_prod
)];
2429 tx_buf
->first_bd
= txdata
->tx_bd_prod
;
2433 bd_prod
= TX_BD(txdata
->tx_bd_prod
);
2434 tx_start_bd
= &txdata
->tx_desc_ring
[bd_prod
].start_bd
;
2435 tx_start_bd
->addr_hi
= cpu_to_le32(U64_HI(mapping
));
2436 tx_start_bd
->addr_lo
= cpu_to_le32(U64_LO(mapping
));
2437 tx_start_bd
->nbd
= cpu_to_le16(2); /* start + pbd */
2438 tx_start_bd
->nbytes
= cpu_to_le16(skb_headlen(skb
));
2439 tx_start_bd
->vlan_or_ethertype
= cpu_to_le16(pkt_prod
);
2440 tx_start_bd
->bd_flags
.as_bitfield
= ETH_TX_BD_FLAGS_START_BD
;
2441 SET_FLAG(tx_start_bd
->general_data
,
2442 ETH_TX_START_BD_HDR_NBDS
,
2444 SET_FLAG(tx_start_bd
->general_data
,
2445 ETH_TX_START_BD_PARSE_NBDS
,
2448 /* turn on parsing and get a BD */
2449 bd_prod
= TX_BD(NEXT_TX_IDX(bd_prod
));
2451 if (CHIP_IS_E1x(bp
)) {
2452 u16 global_data
= 0;
2453 struct eth_tx_parse_bd_e1x
*pbd_e1x
=
2454 &txdata
->tx_desc_ring
[bd_prod
].parse_bd_e1x
;
2455 memset(pbd_e1x
, 0, sizeof(struct eth_tx_parse_bd_e1x
));
2456 SET_FLAG(global_data
,
2457 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE
, UNICAST_ADDRESS
);
2458 pbd_e1x
->global_data
= cpu_to_le16(global_data
);
2460 u32 parsing_data
= 0;
2461 struct eth_tx_parse_bd_e2
*pbd_e2
=
2462 &txdata
->tx_desc_ring
[bd_prod
].parse_bd_e2
;
2463 memset(pbd_e2
, 0, sizeof(struct eth_tx_parse_bd_e2
));
2464 SET_FLAG(parsing_data
,
2465 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE
, UNICAST_ADDRESS
);
2466 pbd_e2
->parsing_data
= cpu_to_le32(parsing_data
);
2470 txdata
->tx_db
.data
.prod
+= 2;
2472 DOORBELL(bp
, txdata
->cid
, txdata
->tx_db
.raw
);
2478 txdata
->tx_bd_prod
+= 2; /* start + pbd */
2482 tx_idx
= le16_to_cpu(*txdata
->tx_cons_sb
);
2483 if (tx_idx
!= tx_start_idx
+ num_pkts
)
2484 goto test_loopback_exit
;
2486 /* Unlike HC IGU won't generate an interrupt for status block
2487 * updates that have been performed while interrupts were
2490 if (bp
->common
.int_block
== INT_BLOCK_IGU
) {
2491 /* Disable local BHes to prevent a dead-lock situation between
2492 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2493 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2496 bnx2x_tx_int(bp
, txdata
);
2500 rx_idx
= le16_to_cpu(*fp_rx
->rx_cons_sb
);
2501 if (rx_idx
!= rx_start_idx
+ num_pkts
)
2502 goto test_loopback_exit
;
2504 cqe
= &fp_rx
->rx_comp_ring
[RCQ_BD(fp_rx
->rx_comp_cons
)];
2505 cqe_fp_flags
= cqe
->fast_path_cqe
.type_error_flags
;
2506 cqe_fp_type
= cqe_fp_flags
& ETH_FAST_PATH_RX_CQE_TYPE
;
2507 if (!CQE_TYPE_FAST(cqe_fp_type
) || (cqe_fp_flags
& ETH_RX_ERROR_FALGS
))
2508 goto test_loopback_rx_exit
;
2510 len
= le16_to_cpu(cqe
->fast_path_cqe
.pkt_len_or_gro_seg_len
);
2511 if (len
!= pkt_size
)
2512 goto test_loopback_rx_exit
;
2514 rx_buf
= &fp_rx
->rx_buf_ring
[RX_BD(fp_rx
->rx_bd_cons
)];
2515 dma_sync_single_for_cpu(&bp
->pdev
->dev
,
2516 dma_unmap_addr(rx_buf
, mapping
),
2517 fp_rx
->rx_buf_size
, DMA_FROM_DEVICE
);
2518 data
= rx_buf
->data
+ NET_SKB_PAD
+ cqe
->fast_path_cqe
.placement_offset
;
2519 for (i
= ETH_HLEN
; i
< pkt_size
; i
++)
2520 if (*(data
+ i
) != (unsigned char) (i
& 0xff))
2521 goto test_loopback_rx_exit
;
2525 test_loopback_rx_exit
:
2527 fp_rx
->rx_bd_cons
= NEXT_RX_IDX(fp_rx
->rx_bd_cons
);
2528 fp_rx
->rx_bd_prod
= NEXT_RX_IDX(fp_rx
->rx_bd_prod
);
2529 fp_rx
->rx_comp_cons
= NEXT_RCQ_IDX(fp_rx
->rx_comp_cons
);
2530 fp_rx
->rx_comp_prod
= NEXT_RCQ_IDX(fp_rx
->rx_comp_prod
);
2532 /* Update producers */
2533 bnx2x_update_rx_prod(bp
, fp_rx
, fp_rx
->rx_bd_prod
, fp_rx
->rx_comp_prod
,
2534 fp_rx
->rx_sge_prod
);
2537 bp
->link_params
.loopback_mode
= LOOPBACK_NONE
;
2542 static int bnx2x_test_loopback(struct bnx2x
*bp
)
2549 if (!netif_running(bp
->dev
))
2550 return BNX2X_LOOPBACK_FAILED
;
2552 bnx2x_netif_stop(bp
, 1);
2553 bnx2x_acquire_phy_lock(bp
);
2555 res
= bnx2x_run_loopback(bp
, BNX2X_PHY_LOOPBACK
);
2557 DP(BNX2X_MSG_ETHTOOL
, " PHY loopback failed (res %d)\n", res
);
2558 rc
|= BNX2X_PHY_LOOPBACK_FAILED
;
2561 res
= bnx2x_run_loopback(bp
, BNX2X_MAC_LOOPBACK
);
2563 DP(BNX2X_MSG_ETHTOOL
, " MAC loopback failed (res %d)\n", res
);
2564 rc
|= BNX2X_MAC_LOOPBACK_FAILED
;
2567 bnx2x_release_phy_lock(bp
);
2568 bnx2x_netif_start(bp
);
2573 static int bnx2x_test_ext_loopback(struct bnx2x
*bp
)
2577 (bp
->link_vars
.link_status
& LINK_STATUS_SERDES_LINK
) > 0;
2582 if (!netif_running(bp
->dev
))
2583 return BNX2X_EXT_LOOPBACK_FAILED
;
2585 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, false);
2586 rc
= bnx2x_nic_load(bp
, LOAD_LOOPBACK_EXT
);
2588 DP(BNX2X_MSG_ETHTOOL
,
2589 "Can't perform self-test, nic_load (for external lb) failed\n");
2592 bnx2x_wait_for_link(bp
, 1, is_serdes
);
2594 bnx2x_netif_stop(bp
, 1);
2596 rc
= bnx2x_run_loopback(bp
, BNX2X_EXT_LOOPBACK
);
2598 DP(BNX2X_MSG_ETHTOOL
, "EXT loopback failed (res %d)\n", rc
);
2600 bnx2x_netif_start(bp
);
2606 u32 sram_start_addr
;
2608 #define CODE_IMAGE_TYPE_MASK 0xf0800003
2609 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2610 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2611 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2615 #define CODE_ENTRY_MAX 16
2616 #define CODE_ENTRY_EXTENDED_DIR_IDX 15
2617 #define MAX_IMAGES_IN_EXTENDED_DIR 64
2618 #define NVRAM_DIR_OFFSET 0x14
2620 #define EXTENDED_DIR_EXISTS(code) \
2621 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2622 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2624 #define CRC32_RESIDUAL 0xdebb20e3
2625 #define CRC_BUFF_SIZE 256
2627 static int bnx2x_nvram_crc(struct bnx2x
*bp
,
2633 int rc
= 0, done
= 0;
2635 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2636 "NVRAM CRC from 0x%08x to 0x%08x\n", offset
, offset
+ size
);
2638 while (done
< size
) {
2639 int count
= min_t(int, size
- done
, CRC_BUFF_SIZE
);
2641 rc
= bnx2x_nvram_read(bp
, offset
+ done
, buff
, count
);
2646 crc
= crc32_le(crc
, buff
, count
);
2650 if (crc
!= CRC32_RESIDUAL
)
2656 static int bnx2x_test_nvram_dir(struct bnx2x
*bp
,
2657 struct code_entry
*entry
,
2660 size_t size
= entry
->code_attribute
& CODE_IMAGE_LENGTH_MASK
;
2661 u32 type
= entry
->code_attribute
& CODE_IMAGE_TYPE_MASK
;
2664 /* Zero-length images and AFEX profiles do not have CRC */
2665 if (size
== 0 || type
== CODE_IMAGE_VNTAG_PROFILES_DATA
)
2668 rc
= bnx2x_nvram_crc(bp
, entry
->nvm_start_addr
, size
, buff
);
2670 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2671 "image %x has failed crc test (rc %d)\n", type
, rc
);
2676 static int bnx2x_test_dir_entry(struct bnx2x
*bp
, u32 addr
, u8
*buff
)
2679 struct code_entry entry
;
2681 rc
= bnx2x_nvram_read32(bp
, addr
, (u32
*)&entry
, sizeof(entry
));
2685 return bnx2x_test_nvram_dir(bp
, &entry
, buff
);
2688 static int bnx2x_test_nvram_ext_dirs(struct bnx2x
*bp
, u8
*buff
)
2690 u32 rc
, cnt
, dir_offset
= NVRAM_DIR_OFFSET
;
2691 struct code_entry entry
;
2694 rc
= bnx2x_nvram_read32(bp
,
2696 sizeof(entry
) * CODE_ENTRY_EXTENDED_DIR_IDX
,
2697 (u32
*)&entry
, sizeof(entry
));
2701 if (!EXTENDED_DIR_EXISTS(entry
.code_attribute
))
2704 rc
= bnx2x_nvram_read32(bp
, entry
.nvm_start_addr
,
2709 dir_offset
= entry
.nvm_start_addr
+ 8;
2711 for (i
= 0; i
< cnt
&& i
< MAX_IMAGES_IN_EXTENDED_DIR
; i
++) {
2712 rc
= bnx2x_test_dir_entry(bp
, dir_offset
+
2713 sizeof(struct code_entry
) * i
,
2722 static int bnx2x_test_nvram_dirs(struct bnx2x
*bp
, u8
*buff
)
2724 u32 rc
, dir_offset
= NVRAM_DIR_OFFSET
;
2727 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
, "NVRAM DIRS CRC test-set\n");
2729 for (i
= 0; i
< CODE_ENTRY_EXTENDED_DIR_IDX
; i
++) {
2730 rc
= bnx2x_test_dir_entry(bp
, dir_offset
+
2731 sizeof(struct code_entry
) * i
,
2737 return bnx2x_test_nvram_ext_dirs(bp
, buff
);
2745 static int bnx2x_test_nvram_tbl(struct bnx2x
*bp
,
2746 const struct crc_pair
*nvram_tbl
, u8
*buf
)
2750 for (i
= 0; nvram_tbl
[i
].size
; i
++) {
2751 int rc
= bnx2x_nvram_crc(bp
, nvram_tbl
[i
].offset
,
2752 nvram_tbl
[i
].size
, buf
);
2754 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2755 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2764 static int bnx2x_test_nvram(struct bnx2x
*bp
)
2766 const struct crc_pair nvram_tbl
[] = {
2767 { 0, 0x14 }, /* bootstrap */
2768 { 0x14, 0xec }, /* dir */
2769 { 0x100, 0x350 }, /* manuf_info */
2770 { 0x450, 0xf0 }, /* feature_info */
2771 { 0x640, 0x64 }, /* upgrade_key_info */
2772 { 0x708, 0x70 }, /* manuf_key_info */
2775 const struct crc_pair nvram_tbl2
[] = {
2776 { 0x7e8, 0x350 }, /* manuf_info2 */
2777 { 0xb38, 0xf0 }, /* feature_info */
2788 buf
= kmalloc(CRC_BUFF_SIZE
, GFP_KERNEL
);
2790 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
, "kmalloc failed\n");
2792 goto test_nvram_exit
;
2795 rc
= bnx2x_nvram_read32(bp
, 0, &magic
, sizeof(magic
));
2797 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2798 "magic value read (rc %d)\n", rc
);
2799 goto test_nvram_exit
;
2802 if (magic
!= 0x669955aa) {
2803 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2804 "wrong magic value (0x%08x)\n", magic
);
2806 goto test_nvram_exit
;
2809 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
, "Port 0 CRC test-set\n");
2810 rc
= bnx2x_test_nvram_tbl(bp
, nvram_tbl
, buf
);
2812 goto test_nvram_exit
;
2814 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_57811xx(bp
)) {
2815 u32 hide
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
2816 SHARED_HW_CFG_HIDE_PORT1
;
2819 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2820 "Port 1 CRC test-set\n");
2821 rc
= bnx2x_test_nvram_tbl(bp
, nvram_tbl2
, buf
);
2823 goto test_nvram_exit
;
2827 rc
= bnx2x_test_nvram_dirs(bp
, buf
);
2834 /* Send an EMPTY ramrod on the first queue */
2835 static int bnx2x_test_intr(struct bnx2x
*bp
)
2837 struct bnx2x_queue_state_params params
= {NULL
};
2839 if (!netif_running(bp
->dev
)) {
2840 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
2841 "cannot access eeprom when the interface is down\n");
2845 params
.q_obj
= &bp
->sp_objs
->q_obj
;
2846 params
.cmd
= BNX2X_Q_CMD_EMPTY
;
2848 __set_bit(RAMROD_COMP_WAIT
, ¶ms
.ramrod_flags
);
2850 return bnx2x_queue_state_change(bp
, ¶ms
);
2853 static void bnx2x_self_test(struct net_device
*dev
,
2854 struct ethtool_test
*etest
, u64
*buf
)
2856 struct bnx2x
*bp
= netdev_priv(dev
);
2857 u8 is_serdes
, link_up
;
2860 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
2862 "Handling parity error recovery. Try again later\n");
2863 etest
->flags
|= ETH_TEST_FL_FAILED
;
2867 DP(BNX2X_MSG_ETHTOOL
,
2868 "Self-test command parameters: offline = %d, external_lb = %d\n",
2869 (etest
->flags
& ETH_TEST_FL_OFFLINE
),
2870 (etest
->flags
& ETH_TEST_FL_EXTERNAL_LB
)>>2);
2872 memset(buf
, 0, sizeof(u64
) * BNX2X_NUM_TESTS(bp
));
2874 if (bnx2x_test_nvram(bp
) != 0) {
2879 etest
->flags
|= ETH_TEST_FL_FAILED
;
2882 if (!netif_running(dev
)) {
2883 DP(BNX2X_MSG_ETHTOOL
, "Interface is down\n");
2887 is_serdes
= (bp
->link_vars
.link_status
& LINK_STATUS_SERDES_LINK
) > 0;
2888 link_up
= bp
->link_vars
.link_up
;
2889 /* offline tests are not supported in MF mode */
2890 if ((etest
->flags
& ETH_TEST_FL_OFFLINE
) && !IS_MF(bp
)) {
2891 int port
= BP_PORT(bp
);
2894 /* save current value of input enable for TX port IF */
2895 val
= REG_RD(bp
, NIG_REG_EGRESS_UMP0_IN_EN
+ port
*4);
2896 /* disable input for TX port IF */
2897 REG_WR(bp
, NIG_REG_EGRESS_UMP0_IN_EN
+ port
*4, 0);
2899 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, false);
2900 rc
= bnx2x_nic_load(bp
, LOAD_DIAG
);
2902 etest
->flags
|= ETH_TEST_FL_FAILED
;
2903 DP(BNX2X_MSG_ETHTOOL
,
2904 "Can't perform self-test, nic_load (for offline) failed\n");
2908 /* wait until link state is restored */
2909 bnx2x_wait_for_link(bp
, 1, is_serdes
);
2911 if (bnx2x_test_registers(bp
) != 0) {
2913 etest
->flags
|= ETH_TEST_FL_FAILED
;
2915 if (bnx2x_test_memory(bp
) != 0) {
2917 etest
->flags
|= ETH_TEST_FL_FAILED
;
2920 buf
[2] = bnx2x_test_loopback(bp
); /* internal LB */
2922 etest
->flags
|= ETH_TEST_FL_FAILED
;
2924 if (etest
->flags
& ETH_TEST_FL_EXTERNAL_LB
) {
2925 buf
[3] = bnx2x_test_ext_loopback(bp
); /* external LB */
2927 etest
->flags
|= ETH_TEST_FL_FAILED
;
2928 etest
->flags
|= ETH_TEST_FL_EXTERNAL_LB_DONE
;
2931 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, false);
2933 /* restore input for TX port IF */
2934 REG_WR(bp
, NIG_REG_EGRESS_UMP0_IN_EN
+ port
*4, val
);
2935 rc
= bnx2x_nic_load(bp
, LOAD_NORMAL
);
2937 etest
->flags
|= ETH_TEST_FL_FAILED
;
2938 DP(BNX2X_MSG_ETHTOOL
,
2939 "Can't perform self-test, nic_load (for online) failed\n");
2942 /* wait until link state is restored */
2943 bnx2x_wait_for_link(bp
, link_up
, is_serdes
);
2946 if (bnx2x_test_intr(bp
) != 0) {
2951 etest
->flags
|= ETH_TEST_FL_FAILED
;
2956 while (bnx2x_link_test(bp
, is_serdes
) && --cnt
)
2965 etest
->flags
|= ETH_TEST_FL_FAILED
;
2969 #define IS_PORT_STAT(i) \
2970 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2971 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2972 #define HIDE_PORT_STAT(bp) \
2973 ((IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS)) || \
2976 /* ethtool statistics are displayed for all regular ethernet queues and the
2977 * fcoe L2 queue if not disabled
2979 static int bnx2x_num_stat_queues(struct bnx2x
*bp
)
2981 return BNX2X_NUM_ETH_QUEUES(bp
);
2984 static int bnx2x_get_sset_count(struct net_device
*dev
, int stringset
)
2986 struct bnx2x
*bp
= netdev_priv(dev
);
2987 int i
, num_strings
= 0;
2989 switch (stringset
) {
2992 num_strings
= bnx2x_num_stat_queues(bp
) *
2996 if (HIDE_PORT_STAT(bp
)) {
2997 for (i
= 0; i
< BNX2X_NUM_STATS
; i
++)
2998 if (IS_FUNC_STAT(i
))
3001 num_strings
+= BNX2X_NUM_STATS
;
3006 return BNX2X_NUM_TESTS(bp
);
3008 case ETH_SS_PRIV_FLAGS
:
3009 return BNX2X_PRI_FLAG_LEN
;
3016 static u32
bnx2x_get_private_flags(struct net_device
*dev
)
3018 struct bnx2x
*bp
= netdev_priv(dev
);
3021 flags
|= (!(bp
->flags
& NO_ISCSI_FLAG
) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI
;
3022 flags
|= (!(bp
->flags
& NO_FCOE_FLAG
) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE
;
3023 flags
|= (!!IS_MF_STORAGE_ONLY(bp
)) << BNX2X_PRI_FLAG_STORAGE
;
3028 static void bnx2x_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
3030 struct bnx2x
*bp
= netdev_priv(dev
);
3032 char queue_name
[MAX_QUEUE_NAME_LEN
+1];
3034 switch (stringset
) {
3038 for_each_eth_queue(bp
, i
) {
3039 memset(queue_name
, 0, sizeof(queue_name
));
3040 sprintf(queue_name
, "%d", i
);
3041 for (j
= 0; j
< BNX2X_NUM_Q_STATS
; j
++)
3042 snprintf(buf
+ (k
+ j
)*ETH_GSTRING_LEN
,
3044 bnx2x_q_stats_arr
[j
].string
,
3046 k
+= BNX2X_NUM_Q_STATS
;
3050 for (i
= 0, j
= 0; i
< BNX2X_NUM_STATS
; i
++) {
3051 if (HIDE_PORT_STAT(bp
) && IS_PORT_STAT(i
))
3053 strcpy(buf
+ (k
+ j
)*ETH_GSTRING_LEN
,
3054 bnx2x_stats_arr
[i
].string
);
3061 /* First 4 tests cannot be done in MF mode */
3066 memcpy(buf
, bnx2x_tests_str_arr
+ start
,
3067 ETH_GSTRING_LEN
* BNX2X_NUM_TESTS(bp
));
3070 case ETH_SS_PRIV_FLAGS
:
3071 memcpy(buf
, bnx2x_private_arr
,
3072 ETH_GSTRING_LEN
* BNX2X_PRI_FLAG_LEN
);
3077 static void bnx2x_get_ethtool_stats(struct net_device
*dev
,
3078 struct ethtool_stats
*stats
, u64
*buf
)
3080 struct bnx2x
*bp
= netdev_priv(dev
);
3081 u32
*hw_stats
, *offset
;
3085 for_each_eth_queue(bp
, i
) {
3086 hw_stats
= (u32
*)&bp
->fp_stats
[i
].eth_q_stats
;
3087 for (j
= 0; j
< BNX2X_NUM_Q_STATS
; j
++) {
3088 if (bnx2x_q_stats_arr
[j
].size
== 0) {
3089 /* skip this counter */
3093 offset
= (hw_stats
+
3094 bnx2x_q_stats_arr
[j
].offset
);
3095 if (bnx2x_q_stats_arr
[j
].size
== 4) {
3096 /* 4-byte counter */
3097 buf
[k
+ j
] = (u64
) *offset
;
3100 /* 8-byte counter */
3101 buf
[k
+ j
] = HILO_U64(*offset
, *(offset
+ 1));
3103 k
+= BNX2X_NUM_Q_STATS
;
3107 hw_stats
= (u32
*)&bp
->eth_stats
;
3108 for (i
= 0, j
= 0; i
< BNX2X_NUM_STATS
; i
++) {
3109 if (HIDE_PORT_STAT(bp
) && IS_PORT_STAT(i
))
3111 if (bnx2x_stats_arr
[i
].size
== 0) {
3112 /* skip this counter */
3117 offset
= (hw_stats
+ bnx2x_stats_arr
[i
].offset
);
3118 if (bnx2x_stats_arr
[i
].size
== 4) {
3119 /* 4-byte counter */
3120 buf
[k
+ j
] = (u64
) *offset
;
3124 /* 8-byte counter */
3125 buf
[k
+ j
] = HILO_U64(*offset
, *(offset
+ 1));
3130 static int bnx2x_set_phys_id(struct net_device
*dev
,
3131 enum ethtool_phys_id_state state
)
3133 struct bnx2x
*bp
= netdev_priv(dev
);
3135 if (!bnx2x_is_nvm_accessible(bp
)) {
3136 DP(BNX2X_MSG_ETHTOOL
| BNX2X_MSG_NVM
,
3137 "cannot access eeprom when the interface is down\n");
3142 case ETHTOOL_ID_ACTIVE
:
3143 return 1; /* cycle on/off once per second */
3146 bnx2x_acquire_phy_lock(bp
);
3147 bnx2x_set_led(&bp
->link_params
, &bp
->link_vars
,
3148 LED_MODE_ON
, SPEED_1000
);
3149 bnx2x_release_phy_lock(bp
);
3152 case ETHTOOL_ID_OFF
:
3153 bnx2x_acquire_phy_lock(bp
);
3154 bnx2x_set_led(&bp
->link_params
, &bp
->link_vars
,
3155 LED_MODE_FRONT_PANEL_OFF
, 0);
3156 bnx2x_release_phy_lock(bp
);
3159 case ETHTOOL_ID_INACTIVE
:
3160 bnx2x_acquire_phy_lock(bp
);
3161 bnx2x_set_led(&bp
->link_params
, &bp
->link_vars
,
3163 bp
->link_vars
.line_speed
);
3164 bnx2x_release_phy_lock(bp
);
3170 static int bnx2x_get_rss_flags(struct bnx2x
*bp
, struct ethtool_rxnfc
*info
)
3172 switch (info
->flow_type
) {
3175 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3176 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3179 if (bp
->rss_conf_obj
.udp_rss_v4
)
3180 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3181 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3183 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3186 if (bp
->rss_conf_obj
.udp_rss_v6
)
3187 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3188 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3190 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3194 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3204 static int bnx2x_get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
3205 u32
*rules __always_unused
)
3207 struct bnx2x
*bp
= netdev_priv(dev
);
3209 switch (info
->cmd
) {
3210 case ETHTOOL_GRXRINGS
:
3211 info
->data
= BNX2X_NUM_ETH_QUEUES(bp
);
3214 return bnx2x_get_rss_flags(bp
, info
);
3216 DP(BNX2X_MSG_ETHTOOL
, "Command parameters not supported\n");
3221 static int bnx2x_set_rss_flags(struct bnx2x
*bp
, struct ethtool_rxnfc
*info
)
3223 int udp_rss_requested
;
3225 DP(BNX2X_MSG_ETHTOOL
,
3226 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3227 info
->flow_type
, info
->data
);
3229 switch (info
->flow_type
) {
3232 /* For TCP only 4-tupple hash is supported */
3233 if (info
->data
^ (RXH_IP_SRC
| RXH_IP_DST
|
3234 RXH_L4_B_0_1
| RXH_L4_B_2_3
)) {
3235 DP(BNX2X_MSG_ETHTOOL
,
3236 "Command parameters not supported\n");
3243 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3244 if (info
->data
== (RXH_IP_SRC
| RXH_IP_DST
|
3245 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3246 udp_rss_requested
= 1;
3247 else if (info
->data
== (RXH_IP_SRC
| RXH_IP_DST
))
3248 udp_rss_requested
= 0;
3251 if ((info
->flow_type
== UDP_V4_FLOW
) &&
3252 (bp
->rss_conf_obj
.udp_rss_v4
!= udp_rss_requested
)) {
3253 bp
->rss_conf_obj
.udp_rss_v4
= udp_rss_requested
;
3254 DP(BNX2X_MSG_ETHTOOL
,
3255 "rss re-configured, UDP 4-tupple %s\n",
3256 udp_rss_requested
? "enabled" : "disabled");
3257 return bnx2x_rss(bp
, &bp
->rss_conf_obj
, false, true);
3258 } else if ((info
->flow_type
== UDP_V6_FLOW
) &&
3259 (bp
->rss_conf_obj
.udp_rss_v6
!= udp_rss_requested
)) {
3260 bp
->rss_conf_obj
.udp_rss_v6
= udp_rss_requested
;
3261 DP(BNX2X_MSG_ETHTOOL
,
3262 "rss re-configured, UDP 4-tupple %s\n",
3263 udp_rss_requested
? "enabled" : "disabled");
3264 return bnx2x_rss(bp
, &bp
->rss_conf_obj
, false, true);
3270 /* For IP only 2-tupple hash is supported */
3271 if (info
->data
^ (RXH_IP_SRC
| RXH_IP_DST
)) {
3272 DP(BNX2X_MSG_ETHTOOL
,
3273 "Command parameters not supported\n");
3279 case AH_ESP_V4_FLOW
:
3283 case AH_ESP_V6_FLOW
:
3288 /* RSS is not supported for these protocols */
3290 DP(BNX2X_MSG_ETHTOOL
,
3291 "Command parameters not supported\n");
3301 static int bnx2x_set_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
)
3303 struct bnx2x
*bp
= netdev_priv(dev
);
3305 switch (info
->cmd
) {
3307 return bnx2x_set_rss_flags(bp
, info
);
3309 DP(BNX2X_MSG_ETHTOOL
, "Command parameters not supported\n");
3314 static u32
bnx2x_get_rxfh_indir_size(struct net_device
*dev
)
3316 return T_ETH_INDIRECTION_TABLE_SIZE
;
3319 static int bnx2x_get_rxfh_indir(struct net_device
*dev
, u32
*indir
)
3321 struct bnx2x
*bp
= netdev_priv(dev
);
3322 u8 ind_table
[T_ETH_INDIRECTION_TABLE_SIZE
] = {0};
3325 /* Get the current configuration of the RSS indirection table */
3326 bnx2x_get_rss_ind_table(&bp
->rss_conf_obj
, ind_table
);
3329 * We can't use a memcpy() as an internal storage of an
3330 * indirection table is a u8 array while indir->ring_index
3331 * points to an array of u32.
3333 * Indirection table contains the FW Client IDs, so we need to
3334 * align the returned table to the Client ID of the leading RSS
3337 for (i
= 0; i
< T_ETH_INDIRECTION_TABLE_SIZE
; i
++)
3338 indir
[i
] = ind_table
[i
] - bp
->fp
->cl_id
;
3343 static int bnx2x_set_rxfh_indir(struct net_device
*dev
, const u32
*indir
)
3345 struct bnx2x
*bp
= netdev_priv(dev
);
3348 for (i
= 0; i
< T_ETH_INDIRECTION_TABLE_SIZE
; i
++) {
3350 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3351 * as an internal storage of an indirection table is a u8 array
3352 * while indir->ring_index points to an array of u32.
3354 * Indirection table contains the FW Client IDs, so we need to
3355 * align the received table to the Client ID of the leading RSS
3358 bp
->rss_conf_obj
.ind_table
[i
] = indir
[i
] + bp
->fp
->cl_id
;
3361 return bnx2x_config_rss_eth(bp
, false);
3365 * bnx2x_get_channels - gets the number of RSS queues.
3368 * @channels: returns the number of max / current queues
3370 static void bnx2x_get_channels(struct net_device
*dev
,
3371 struct ethtool_channels
*channels
)
3373 struct bnx2x
*bp
= netdev_priv(dev
);
3375 channels
->max_combined
= BNX2X_MAX_RSS_COUNT(bp
);
3376 channels
->combined_count
= BNX2X_NUM_ETH_QUEUES(bp
);
3380 * bnx2x_change_num_queues - change the number of RSS queues.
3382 * @bp: bnx2x private structure
3384 * Re-configure interrupt mode to get the new number of MSI-X
3385 * vectors and re-add NAPI objects.
3387 static void bnx2x_change_num_queues(struct bnx2x
*bp
, int num_rss
)
3389 bnx2x_disable_msi(bp
);
3390 bp
->num_ethernet_queues
= num_rss
;
3391 bp
->num_queues
= bp
->num_ethernet_queues
+ bp
->num_cnic_queues
;
3392 BNX2X_DEV_INFO("set number of queues to %d\n", bp
->num_queues
);
3393 bnx2x_set_int_mode(bp
);
3397 * bnx2x_set_channels - sets the number of RSS queues.
3400 * @channels: includes the number of queues requested
3402 static int bnx2x_set_channels(struct net_device
*dev
,
3403 struct ethtool_channels
*channels
)
3405 struct bnx2x
*bp
= netdev_priv(dev
);
3407 DP(BNX2X_MSG_ETHTOOL
,
3408 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3409 channels
->rx_count
, channels
->tx_count
, channels
->other_count
,
3410 channels
->combined_count
);
3412 /* We don't support separate rx / tx channels.
3413 * We don't allow setting 'other' channels.
3415 if (channels
->rx_count
|| channels
->tx_count
|| channels
->other_count
3416 || (channels
->combined_count
== 0) ||
3417 (channels
->combined_count
> BNX2X_MAX_RSS_COUNT(bp
))) {
3418 DP(BNX2X_MSG_ETHTOOL
, "command parameters not supported\n");
3422 /* Check if there was a change in the active parameters */
3423 if (channels
->combined_count
== BNX2X_NUM_ETH_QUEUES(bp
)) {
3424 DP(BNX2X_MSG_ETHTOOL
, "No change in active parameters\n");
3428 /* Set the requested number of queues in bp context.
3429 * Note that the actual number of queues created during load may be
3430 * less than requested if memory is low.
3432 if (unlikely(!netif_running(dev
))) {
3433 bnx2x_change_num_queues(bp
, channels
->combined_count
);
3436 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, true);
3437 bnx2x_change_num_queues(bp
, channels
->combined_count
);
3438 return bnx2x_nic_load(bp
, LOAD_NORMAL
);
3441 static const struct ethtool_ops bnx2x_ethtool_ops
= {
3442 .get_settings
= bnx2x_get_settings
,
3443 .set_settings
= bnx2x_set_settings
,
3444 .get_drvinfo
= bnx2x_get_drvinfo
,
3445 .get_regs_len
= bnx2x_get_regs_len
,
3446 .get_regs
= bnx2x_get_regs
,
3447 .get_dump_flag
= bnx2x_get_dump_flag
,
3448 .get_dump_data
= bnx2x_get_dump_data
,
3449 .set_dump
= bnx2x_set_dump
,
3450 .get_wol
= bnx2x_get_wol
,
3451 .set_wol
= bnx2x_set_wol
,
3452 .get_msglevel
= bnx2x_get_msglevel
,
3453 .set_msglevel
= bnx2x_set_msglevel
,
3454 .nway_reset
= bnx2x_nway_reset
,
3455 .get_link
= bnx2x_get_link
,
3456 .get_eeprom_len
= bnx2x_get_eeprom_len
,
3457 .get_eeprom
= bnx2x_get_eeprom
,
3458 .set_eeprom
= bnx2x_set_eeprom
,
3459 .get_coalesce
= bnx2x_get_coalesce
,
3460 .set_coalesce
= bnx2x_set_coalesce
,
3461 .get_ringparam
= bnx2x_get_ringparam
,
3462 .set_ringparam
= bnx2x_set_ringparam
,
3463 .get_pauseparam
= bnx2x_get_pauseparam
,
3464 .set_pauseparam
= bnx2x_set_pauseparam
,
3465 .self_test
= bnx2x_self_test
,
3466 .get_sset_count
= bnx2x_get_sset_count
,
3467 .get_priv_flags
= bnx2x_get_private_flags
,
3468 .get_strings
= bnx2x_get_strings
,
3469 .set_phys_id
= bnx2x_set_phys_id
,
3470 .get_ethtool_stats
= bnx2x_get_ethtool_stats
,
3471 .get_rxnfc
= bnx2x_get_rxnfc
,
3472 .set_rxnfc
= bnx2x_set_rxnfc
,
3473 .get_rxfh_indir_size
= bnx2x_get_rxfh_indir_size
,
3474 .get_rxfh_indir
= bnx2x_get_rxfh_indir
,
3475 .set_rxfh_indir
= bnx2x_set_rxfh_indir
,
3476 .get_channels
= bnx2x_get_channels
,
3477 .set_channels
= bnx2x_set_channels
,
3478 .get_module_info
= bnx2x_get_module_info
,
3479 .get_module_eeprom
= bnx2x_get_module_eeprom
,
3480 .get_eee
= bnx2x_get_eee
,
3481 .set_eee
= bnx2x_set_eee
,
3482 .get_ts_info
= ethtool_op_get_ts_info
,
3485 static const struct ethtool_ops bnx2x_vf_ethtool_ops
= {
3486 .get_settings
= bnx2x_get_settings
,
3487 .set_settings
= bnx2x_set_settings
,
3488 .get_drvinfo
= bnx2x_get_drvinfo
,
3489 .get_msglevel
= bnx2x_get_msglevel
,
3490 .set_msglevel
= bnx2x_set_msglevel
,
3491 .get_link
= bnx2x_get_link
,
3492 .get_coalesce
= bnx2x_get_coalesce
,
3493 .get_ringparam
= bnx2x_get_ringparam
,
3494 .set_ringparam
= bnx2x_set_ringparam
,
3495 .get_sset_count
= bnx2x_get_sset_count
,
3496 .get_strings
= bnx2x_get_strings
,
3497 .get_ethtool_stats
= bnx2x_get_ethtool_stats
,
3498 .get_rxnfc
= bnx2x_get_rxnfc
,
3499 .set_rxnfc
= bnx2x_set_rxnfc
,
3500 .get_rxfh_indir_size
= bnx2x_get_rxfh_indir_size
,
3501 .get_rxfh_indir
= bnx2x_get_rxfh_indir
,
3502 .set_rxfh_indir
= bnx2x_set_rxfh_indir
,
3503 .get_channels
= bnx2x_get_channels
,
3504 .set_channels
= bnx2x_set_channels
,
3507 void bnx2x_set_ethtool_ops(struct bnx2x
*bp
, struct net_device
*netdev
)
3510 SET_ETHTOOL_OPS(netdev
, &bnx2x_ethtool_ops
);
3512 SET_ETHTOOL_OPS(netdev
, &bnx2x_vf_ethtool_ops
);