1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
47 #include <net/checksum.h>
48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h>
50 #include <linux/crc32.h>
51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h>
53 #include <linux/zlib.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77 /* Time in jiffies before concluding the transmitter is hung */
78 #define TX_TIMEOUT (5*HZ)
80 static char version
[] __devinitdata
=
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
84 MODULE_AUTHOR("Eliezer Tamir");
85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_MODULE_VERSION
);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1
);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1H
);
93 MODULE_FIRMWARE(FW_FILE_NAME_E2
);
95 static int multi_mode
= 1;
96 module_param(multi_mode
, int, 0);
97 MODULE_PARM_DESC(multi_mode
, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
101 module_param(num_queues
, int, 0);
102 MODULE_PARM_DESC(num_queues
, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
105 static int disable_tpa
;
106 module_param(disable_tpa
, int, 0);
107 MODULE_PARM_DESC(disable_tpa
, " Disable the TPA (LRO) feature");
109 #define INT_MODE_INTx 1
110 #define INT_MODE_MSI 2
112 module_param(int_mode
, int, 0);
113 MODULE_PARM_DESC(int_mode
, " Force interrupt mode other than MSI-X "
116 static int dropless_fc
;
117 module_param(dropless_fc
, int, 0);
118 MODULE_PARM_DESC(dropless_fc
, " Pause on exhausted host ring");
121 module_param(poll
, int, 0);
122 MODULE_PARM_DESC(poll
, " Use polling (for debug)");
124 static int mrrs
= -1;
125 module_param(mrrs
, int, 0);
126 MODULE_PARM_DESC(mrrs
, " Force Max Read Req Size (0..3) (for debug)");
129 module_param(debug
, int, 0);
130 MODULE_PARM_DESC(debug
, " Default debug msglevel");
134 struct workqueue_struct
*bnx2x_wq
;
136 enum bnx2x_board_type
{
150 /* indexed by board_type, above */
153 } board_info
[] __devinitdata
= {
154 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
155 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
162 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
163 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
165 "Ethernet Multi Function"}
168 #ifndef PCI_DEVICE_ID_NX2_57710
169 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
171 #ifndef PCI_DEVICE_ID_NX2_57711
172 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
174 #ifndef PCI_DEVICE_ID_NX2_57711E
175 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
177 #ifndef PCI_DEVICE_ID_NX2_57712
178 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
180 #ifndef PCI_DEVICE_ID_NX2_57712_MF
181 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
183 #ifndef PCI_DEVICE_ID_NX2_57800
184 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
186 #ifndef PCI_DEVICE_ID_NX2_57800_MF
187 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
189 #ifndef PCI_DEVICE_ID_NX2_57810
190 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
192 #ifndef PCI_DEVICE_ID_NX2_57810_MF
193 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
195 #ifndef PCI_DEVICE_ID_NX2_57840
196 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
198 #ifndef PCI_DEVICE_ID_NX2_57840_MF
199 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
201 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl
) = {
202 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57710
), BCM57710
},
203 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711
), BCM57711
},
204 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711E
), BCM57711E
},
205 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712
), BCM57712
},
206 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_MF
), BCM57712_MF
},
207 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800
), BCM57800
},
208 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_MF
), BCM57800_MF
},
209 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810
), BCM57810
},
210 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_MF
), BCM57810_MF
},
211 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840
), BCM57840
},
212 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
216 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
218 /****************************************************************************
219 * General service functions
220 ****************************************************************************/
222 static inline void __storm_memset_dma_mapping(struct bnx2x
*bp
,
223 u32 addr
, dma_addr_t mapping
)
225 REG_WR(bp
, addr
, U64_LO(mapping
));
226 REG_WR(bp
, addr
+ 4, U64_HI(mapping
));
229 static inline void storm_memset_spq_addr(struct bnx2x
*bp
,
230 dma_addr_t mapping
, u16 abs_fid
)
232 u32 addr
= XSEM_REG_FAST_MEMORY
+
233 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid
);
235 __storm_memset_dma_mapping(bp
, addr
, mapping
);
238 static inline void storm_memset_vf_to_pf(struct bnx2x
*bp
, u16 abs_fid
,
241 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_VF_TO_PF_OFFSET(abs_fid
),
243 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_VF_TO_PF_OFFSET(abs_fid
),
245 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_VF_TO_PF_OFFSET(abs_fid
),
247 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_VF_TO_PF_OFFSET(abs_fid
),
251 static inline void storm_memset_func_en(struct bnx2x
*bp
, u16 abs_fid
,
254 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(abs_fid
),
256 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(abs_fid
),
258 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(abs_fid
),
260 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(abs_fid
),
264 static inline void storm_memset_eq_data(struct bnx2x
*bp
,
265 struct event_ring_data
*eq_data
,
268 size_t size
= sizeof(struct event_ring_data
);
270 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_DATA_OFFSET(pfid
);
272 __storm_memset_struct(bp
, addr
, size
, (u32
*)eq_data
);
275 static inline void storm_memset_eq_prod(struct bnx2x
*bp
, u16 eq_prod
,
278 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_PROD_OFFSET(pfid
);
279 REG_WR16(bp
, addr
, eq_prod
);
283 * locking is done by mcp
285 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
287 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
288 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
289 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
290 PCICFG_VENDOR_ID_OFFSET
);
293 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
297 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
298 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
299 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
300 PCICFG_VENDOR_ID_OFFSET
);
305 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
306 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
307 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
308 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
309 #define DMAE_DP_DST_NONE "dst_addr [none]"
311 static void bnx2x_dp_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
,
314 u32 src_type
= dmae
->opcode
& DMAE_COMMAND_SRC
;
316 switch (dmae
->opcode
& DMAE_COMMAND_DST
) {
317 case DMAE_CMD_DST_PCI
:
318 if (src_type
== DMAE_CMD_SRC_PCI
)
319 DP(msglvl
, "DMAE: opcode 0x%08x\n"
320 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
321 "comp_addr [%x:%08x], comp_val 0x%08x\n",
322 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
323 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
324 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
327 DP(msglvl
, "DMAE: opcode 0x%08x\n"
328 "src [%08x], len [%d*4], dst [%x:%08x]\n"
329 "comp_addr [%x:%08x], comp_val 0x%08x\n",
330 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
331 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
332 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
335 case DMAE_CMD_DST_GRC
:
336 if (src_type
== DMAE_CMD_SRC_PCI
)
337 DP(msglvl
, "DMAE: opcode 0x%08x\n"
338 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
339 "comp_addr [%x:%08x], comp_val 0x%08x\n",
340 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
341 dmae
->len
, dmae
->dst_addr_lo
>> 2,
342 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
345 DP(msglvl
, "DMAE: opcode 0x%08x\n"
346 "src [%08x], len [%d*4], dst [%08x]\n"
347 "comp_addr [%x:%08x], comp_val 0x%08x\n",
348 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
349 dmae
->len
, dmae
->dst_addr_lo
>> 2,
350 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
354 if (src_type
== DMAE_CMD_SRC_PCI
)
355 DP(msglvl
, "DMAE: opcode 0x%08x\n"
356 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
357 "comp_addr [%x:%08x] comp_val 0x%08x\n",
358 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
359 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
362 DP(msglvl
, "DMAE: opcode 0x%08x\n"
363 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
364 "comp_addr [%x:%08x] comp_val 0x%08x\n",
365 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
366 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
373 /* copy command into DMAE command memory and set DMAE command go */
374 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
)
379 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
380 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
381 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
383 DP(BNX2X_MSG_OFF
, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
384 idx
, i
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
386 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
389 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
)
391 return opcode
| ((comp_type
<< DMAE_COMMAND_C_DST_SHIFT
) |
395 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
)
397 return opcode
& ~DMAE_CMD_SRC_RESET
;
400 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
401 bool with_comp
, u8 comp_type
)
405 opcode
|= ((src_type
<< DMAE_COMMAND_SRC_SHIFT
) |
406 (dst_type
<< DMAE_COMMAND_DST_SHIFT
));
408 opcode
|= (DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
);
410 opcode
|= (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
);
411 opcode
|= ((BP_VN(bp
) << DMAE_CMD_E1HVN_SHIFT
) |
412 (BP_VN(bp
) << DMAE_COMMAND_DST_VN_SHIFT
));
413 opcode
|= (DMAE_COM_SET_ERR
<< DMAE_COMMAND_ERR_POLICY_SHIFT
);
416 opcode
|= DMAE_CMD_ENDIANITY_B_DW_SWAP
;
418 opcode
|= DMAE_CMD_ENDIANITY_DW_SWAP
;
421 opcode
= bnx2x_dmae_opcode_add_comp(opcode
, comp_type
);
425 static void bnx2x_prep_dmae_with_comp(struct bnx2x
*bp
,
426 struct dmae_command
*dmae
,
427 u8 src_type
, u8 dst_type
)
429 memset(dmae
, 0, sizeof(struct dmae_command
));
432 dmae
->opcode
= bnx2x_dmae_opcode(bp
, src_type
, dst_type
,
433 true, DMAE_COMP_PCI
);
435 /* fill in the completion parameters */
436 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
437 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
438 dmae
->comp_val
= DMAE_COMP_VAL
;
441 /* issue a dmae command over the init-channel and wailt for completion */
442 static int bnx2x_issue_dmae_with_comp(struct bnx2x
*bp
,
443 struct dmae_command
*dmae
)
445 u32
*wb_comp
= bnx2x_sp(bp
, wb_comp
);
446 int cnt
= CHIP_REV_IS_SLOW(bp
) ? (400000) : 4000;
449 DP(BNX2X_MSG_OFF
, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
450 bp
->slowpath
->wb_data
[0], bp
->slowpath
->wb_data
[1],
451 bp
->slowpath
->wb_data
[2], bp
->slowpath
->wb_data
[3]);
454 * Lock the dmae channel. Disable BHs to prevent a dead-lock
455 * as long as this code is called both from syscall context and
456 * from ndo_set_rx_mode() flow that may be called from BH.
458 spin_lock_bh(&bp
->dmae_lock
);
460 /* reset completion */
463 /* post the command on the channel used for initializations */
464 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
466 /* wait for completion */
468 while ((*wb_comp
& ~DMAE_PCI_ERR_FLAG
) != DMAE_COMP_VAL
) {
469 DP(BNX2X_MSG_OFF
, "wb_comp 0x%08x\n", *wb_comp
);
472 (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
&&
473 bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
474 BNX2X_ERR("DMAE timeout!\n");
481 if (*wb_comp
& DMAE_PCI_ERR_FLAG
) {
482 BNX2X_ERR("DMAE PCI error!\n");
486 DP(BNX2X_MSG_OFF
, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
487 bp
->slowpath
->wb_data
[0], bp
->slowpath
->wb_data
[1],
488 bp
->slowpath
->wb_data
[2], bp
->slowpath
->wb_data
[3]);
491 spin_unlock_bh(&bp
->dmae_lock
);
495 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
498 struct dmae_command dmae
;
500 if (!bp
->dmae_ready
) {
501 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
504 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n",
507 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
509 bnx2x_init_str_wr(bp
, dst_addr
, data
, len32
);
513 /* set opcode and fixed command fields */
514 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_PCI
, DMAE_DST_GRC
);
516 /* fill in addresses and len */
517 dmae
.src_addr_lo
= U64_LO(dma_addr
);
518 dmae
.src_addr_hi
= U64_HI(dma_addr
);
519 dmae
.dst_addr_lo
= dst_addr
>> 2;
520 dmae
.dst_addr_hi
= 0;
523 bnx2x_dp_dmae(bp
, &dmae
, BNX2X_MSG_OFF
);
525 /* issue the command and wait for completion */
526 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
529 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
531 struct dmae_command dmae
;
533 if (!bp
->dmae_ready
) {
534 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
537 if (CHIP_IS_E1(bp
)) {
539 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n",
541 for (i
= 0; i
< len32
; i
++)
542 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
544 for (i
= 0; i
< len32
; i
++)
545 data
[i
] = REG_RD(bp
, src_addr
+ i
*4);
550 /* set opcode and fixed command fields */
551 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_GRC
, DMAE_DST_PCI
);
553 /* fill in addresses and len */
554 dmae
.src_addr_lo
= src_addr
>> 2;
555 dmae
.src_addr_hi
= 0;
556 dmae
.dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
557 dmae
.dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
560 bnx2x_dp_dmae(bp
, &dmae
, BNX2X_MSG_OFF
);
562 /* issue the command and wait for completion */
563 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
566 static void bnx2x_write_dmae_phys_len(struct bnx2x
*bp
, dma_addr_t phys_addr
,
569 int dmae_wr_max
= DMAE_LEN32_WR_MAX(bp
);
572 while (len
> dmae_wr_max
) {
573 bnx2x_write_dmae(bp
, phys_addr
+ offset
,
574 addr
+ offset
, dmae_wr_max
);
575 offset
+= dmae_wr_max
* 4;
579 bnx2x_write_dmae(bp
, phys_addr
+ offset
, addr
+ offset
, len
);
582 /* used only for slowpath so not inlined */
583 static void bnx2x_wb_wr(struct bnx2x
*bp
, int reg
, u32 val_hi
, u32 val_lo
)
587 wb_write
[0] = val_hi
;
588 wb_write
[1] = val_lo
;
589 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
593 static u64
bnx2x_wb_rd(struct bnx2x
*bp
, int reg
)
597 REG_RD_DMAE(bp
, reg
, wb_data
, 2);
599 return HILO_U64(wb_data
[0], wb_data
[1]);
603 static int bnx2x_mc_assert(struct bnx2x
*bp
)
607 u32 row0
, row1
, row2
, row3
;
610 last_idx
= REG_RD8(bp
, BAR_XSTRORM_INTMEM
+
611 XSTORM_ASSERT_LIST_INDEX_OFFSET
);
613 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
615 /* print the asserts */
616 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
618 row0
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
619 XSTORM_ASSERT_LIST_OFFSET(i
));
620 row1
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
621 XSTORM_ASSERT_LIST_OFFSET(i
) + 4);
622 row2
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
623 XSTORM_ASSERT_LIST_OFFSET(i
) + 8);
624 row3
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
625 XSTORM_ASSERT_LIST_OFFSET(i
) + 12);
627 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
628 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
629 " 0x%08x 0x%08x 0x%08x\n",
630 i
, row3
, row2
, row1
, row0
);
638 last_idx
= REG_RD8(bp
, BAR_TSTRORM_INTMEM
+
639 TSTORM_ASSERT_LIST_INDEX_OFFSET
);
641 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
643 /* print the asserts */
644 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
646 row0
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
647 TSTORM_ASSERT_LIST_OFFSET(i
));
648 row1
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
649 TSTORM_ASSERT_LIST_OFFSET(i
) + 4);
650 row2
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
651 TSTORM_ASSERT_LIST_OFFSET(i
) + 8);
652 row3
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
653 TSTORM_ASSERT_LIST_OFFSET(i
) + 12);
655 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
656 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
657 " 0x%08x 0x%08x 0x%08x\n",
658 i
, row3
, row2
, row1
, row0
);
666 last_idx
= REG_RD8(bp
, BAR_CSTRORM_INTMEM
+
667 CSTORM_ASSERT_LIST_INDEX_OFFSET
);
669 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
671 /* print the asserts */
672 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
674 row0
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
675 CSTORM_ASSERT_LIST_OFFSET(i
));
676 row1
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
677 CSTORM_ASSERT_LIST_OFFSET(i
) + 4);
678 row2
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
679 CSTORM_ASSERT_LIST_OFFSET(i
) + 8);
680 row3
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
681 CSTORM_ASSERT_LIST_OFFSET(i
) + 12);
683 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
684 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
685 " 0x%08x 0x%08x 0x%08x\n",
686 i
, row3
, row2
, row1
, row0
);
694 last_idx
= REG_RD8(bp
, BAR_USTRORM_INTMEM
+
695 USTORM_ASSERT_LIST_INDEX_OFFSET
);
697 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
699 /* print the asserts */
700 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
702 row0
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
703 USTORM_ASSERT_LIST_OFFSET(i
));
704 row1
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
705 USTORM_ASSERT_LIST_OFFSET(i
) + 4);
706 row2
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
707 USTORM_ASSERT_LIST_OFFSET(i
) + 8);
708 row3
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
709 USTORM_ASSERT_LIST_OFFSET(i
) + 12);
711 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
712 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
713 " 0x%08x 0x%08x 0x%08x\n",
714 i
, row3
, row2
, row1
, row0
);
724 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
)
730 u32 trace_shmem_base
;
732 BNX2X_ERR("NO MCP - can not dump\n");
735 netdev_printk(lvl
, bp
->dev
, "bc %d.%d.%d\n",
736 (bp
->common
.bc_ver
& 0xff0000) >> 16,
737 (bp
->common
.bc_ver
& 0xff00) >> 8,
738 (bp
->common
.bc_ver
& 0xff));
740 val
= REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
);
741 if (val
== REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
))
742 printk("%s" "MCP PC at 0x%x\n", lvl
, val
);
744 if (BP_PATH(bp
) == 0)
745 trace_shmem_base
= bp
->common
.shmem_base
;
747 trace_shmem_base
= SHMEM2_RD(bp
, other_shmem_base_addr
);
748 addr
= trace_shmem_base
- 0x0800 + 4;
749 mark
= REG_RD(bp
, addr
);
750 mark
= (CHIP_IS_E1x(bp
) ? MCP_REG_MCPR_SCRATCH
: MCP_A_REG_MCPR_SCRATCH
)
751 + ((mark
+ 0x3) & ~0x3) - 0x08000000;
752 printk("%s" "begin fw dump (mark 0x%x)\n", lvl
, mark
);
755 for (offset
= mark
; offset
<= trace_shmem_base
; offset
+= 0x8*4) {
756 for (word
= 0; word
< 8; word
++)
757 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
759 pr_cont("%s", (char *)data
);
761 for (offset
= addr
+ 4; offset
<= mark
; offset
+= 0x8*4) {
762 for (word
= 0; word
< 8; word
++)
763 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
765 pr_cont("%s", (char *)data
);
767 printk("%s" "end of fw dump\n", lvl
);
770 static inline void bnx2x_fw_dump(struct bnx2x
*bp
)
772 bnx2x_fw_dump_lvl(bp
, KERN_ERR
);
775 void bnx2x_panic_dump(struct bnx2x
*bp
)
779 struct hc_sp_status_block_data sp_sb_data
;
780 int func
= BP_FUNC(bp
);
781 #ifdef BNX2X_STOP_ON_ERROR
782 u16 start
= 0, end
= 0;
786 bp
->stats_state
= STATS_STATE_DISABLED
;
787 bp
->eth_stats
.unrecoverable_error
++;
788 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
790 BNX2X_ERR("begin crash dump -----------------\n");
794 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
795 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
796 bp
->def_idx
, bp
->def_att_idx
, bp
->attn_state
,
797 bp
->spq_prod_idx
, bp
->stats_counter
);
798 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
799 bp
->def_status_blk
->atten_status_block
.attn_bits
,
800 bp
->def_status_blk
->atten_status_block
.attn_bits_ack
,
801 bp
->def_status_blk
->atten_status_block
.status_block_id
,
802 bp
->def_status_blk
->atten_status_block
.attn_bits_index
);
804 for (i
= 0; i
< HC_SP_SB_MAX_INDICES
; i
++)
806 bp
->def_status_blk
->sp_sb
.index_values
[i
],
807 (i
== HC_SP_SB_MAX_INDICES
- 1) ? ") " : " ");
809 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
810 *((u32
*)&sp_sb_data
+ i
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
811 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
814 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
815 sp_sb_data
.igu_sb_id
,
816 sp_sb_data
.igu_seg_id
,
817 sp_sb_data
.p_func
.pf_id
,
818 sp_sb_data
.p_func
.vnic_id
,
819 sp_sb_data
.p_func
.vf_id
,
820 sp_sb_data
.p_func
.vf_valid
,
824 for_each_eth_queue(bp
, i
) {
825 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
827 struct hc_status_block_data_e2 sb_data_e2
;
828 struct hc_status_block_data_e1x sb_data_e1x
;
829 struct hc_status_block_sm
*hc_sm_p
=
831 sb_data_e1x
.common
.state_machine
:
832 sb_data_e2
.common
.state_machine
;
833 struct hc_index_data
*hc_index_p
=
835 sb_data_e1x
.index_data
:
836 sb_data_e2
.index_data
;
839 struct bnx2x_fp_txdata txdata
;
842 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
843 " rx_comp_prod(0x%x)"
844 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
845 i
, fp
->rx_bd_prod
, fp
->rx_bd_cons
,
847 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
848 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
849 " fp_hc_idx(0x%x)\n",
850 fp
->rx_sge_prod
, fp
->last_max_sge
,
851 le16_to_cpu(fp
->fp_hc_idx
));
854 for_each_cos_in_tx_queue(fp
, cos
)
856 txdata
= fp
->txdata
[cos
];
857 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
858 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
859 " *tx_cons_sb(0x%x)\n",
860 i
, txdata
.tx_pkt_prod
,
861 txdata
.tx_pkt_cons
, txdata
.tx_bd_prod
,
863 le16_to_cpu(*txdata
.tx_cons_sb
));
866 loop
= CHIP_IS_E1x(bp
) ?
867 HC_SB_MAX_INDICES_E1X
: HC_SB_MAX_INDICES_E2
;
875 BNX2X_ERR(" run indexes (");
876 for (j
= 0; j
< HC_SB_MAX_SM
; j
++)
878 fp
->sb_running_index
[j
],
879 (j
== HC_SB_MAX_SM
- 1) ? ")" : " ");
881 BNX2X_ERR(" indexes (");
882 for (j
= 0; j
< loop
; j
++)
884 fp
->sb_index_values
[j
],
885 (j
== loop
- 1) ? ")" : " ");
887 data_size
= CHIP_IS_E1x(bp
) ?
888 sizeof(struct hc_status_block_data_e1x
) :
889 sizeof(struct hc_status_block_data_e2
);
890 data_size
/= sizeof(u32
);
891 sb_data_p
= CHIP_IS_E1x(bp
) ?
892 (u32
*)&sb_data_e1x
:
894 /* copy sb data in here */
895 for (j
= 0; j
< data_size
; j
++)
896 *(sb_data_p
+ j
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
897 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp
->fw_sb_id
) +
900 if (!CHIP_IS_E1x(bp
)) {
901 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
902 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
904 sb_data_e2
.common
.p_func
.pf_id
,
905 sb_data_e2
.common
.p_func
.vf_id
,
906 sb_data_e2
.common
.p_func
.vf_valid
,
907 sb_data_e2
.common
.p_func
.vnic_id
,
908 sb_data_e2
.common
.same_igu_sb_1b
,
909 sb_data_e2
.common
.state
);
911 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
912 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
914 sb_data_e1x
.common
.p_func
.pf_id
,
915 sb_data_e1x
.common
.p_func
.vf_id
,
916 sb_data_e1x
.common
.p_func
.vf_valid
,
917 sb_data_e1x
.common
.p_func
.vnic_id
,
918 sb_data_e1x
.common
.same_igu_sb_1b
,
919 sb_data_e1x
.common
.state
);
923 for (j
= 0; j
< HC_SB_MAX_SM
; j
++) {
924 pr_cont("SM[%d] __flags (0x%x) "
925 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
926 "time_to_expire (0x%x) "
927 "timer_value(0x%x)\n", j
,
929 hc_sm_p
[j
].igu_sb_id
,
930 hc_sm_p
[j
].igu_seg_id
,
931 hc_sm_p
[j
].time_to_expire
,
932 hc_sm_p
[j
].timer_value
);
936 for (j
= 0; j
< loop
; j
++) {
937 pr_cont("INDEX[%d] flags (0x%x) "
938 "timeout (0x%x)\n", j
,
940 hc_index_p
[j
].timeout
);
944 #ifdef BNX2X_STOP_ON_ERROR
947 for_each_rx_queue(bp
, i
) {
948 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
950 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
951 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
952 for (j
= start
; j
!= end
; j
= RX_BD(j
+ 1)) {
953 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
954 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
956 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
957 i
, j
, rx_bd
[1], rx_bd
[0], sw_bd
->data
);
960 start
= RX_SGE(fp
->rx_sge_prod
);
961 end
= RX_SGE(fp
->last_max_sge
);
962 for (j
= start
; j
!= end
; j
= RX_SGE(j
+ 1)) {
963 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
964 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
966 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
967 i
, j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
970 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
971 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
972 for (j
= start
; j
!= end
; j
= RCQ_BD(j
+ 1)) {
973 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
975 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
976 i
, j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
981 for_each_tx_queue(bp
, i
) {
982 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
983 for_each_cos_in_tx_queue(fp
, cos
) {
984 struct bnx2x_fp_txdata
*txdata
= &fp
->txdata
[cos
];
986 start
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) - 10);
987 end
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) + 245);
988 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
989 struct sw_tx_bd
*sw_bd
=
990 &txdata
->tx_buf_ring
[j
];
992 BNX2X_ERR("fp%d: txdata %d, "
993 "packet[%x]=[%p,%x]\n",
994 i
, cos
, j
, sw_bd
->skb
,
998 start
= TX_BD(txdata
->tx_bd_cons
- 10);
999 end
= TX_BD(txdata
->tx_bd_cons
+ 254);
1000 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1001 u32
*tx_bd
= (u32
*)&txdata
->tx_desc_ring
[j
];
1003 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
1005 i
, cos
, j
, tx_bd
[0], tx_bd
[1],
1006 tx_bd
[2], tx_bd
[3]);
1012 bnx2x_mc_assert(bp
);
1013 BNX2X_ERR("end crash dump -----------------\n");
1017 * FLR Support for E2
1019 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1022 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1023 #define FLR_WAIT_INTERVAL 50 /* usec */
1024 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1026 struct pbf_pN_buf_regs
{
1033 struct pbf_pN_cmd_regs
{
1039 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x
*bp
,
1040 struct pbf_pN_buf_regs
*regs
,
1043 u32 init_crd
, crd
, crd_start
, crd_freed
, crd_freed_start
;
1044 u32 cur_cnt
= poll_count
;
1046 crd_freed
= crd_freed_start
= REG_RD(bp
, regs
->crd_freed
);
1047 crd
= crd_start
= REG_RD(bp
, regs
->crd
);
1048 init_crd
= REG_RD(bp
, regs
->init_crd
);
1050 DP(BNX2X_MSG_SP
, "INIT CREDIT[%d] : %x\n", regs
->pN
, init_crd
);
1051 DP(BNX2X_MSG_SP
, "CREDIT[%d] : s:%x\n", regs
->pN
, crd
);
1052 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: s:%x\n", regs
->pN
, crd_freed
);
1054 while ((crd
!= init_crd
) && ((u32
)SUB_S32(crd_freed
, crd_freed_start
) <
1055 (init_crd
- crd_start
))) {
1057 udelay(FLR_WAIT_INTERVAL
);
1058 crd
= REG_RD(bp
, regs
->crd
);
1059 crd_freed
= REG_RD(bp
, regs
->crd_freed
);
1061 DP(BNX2X_MSG_SP
, "PBF tx buffer[%d] timed out\n",
1063 DP(BNX2X_MSG_SP
, "CREDIT[%d] : c:%x\n",
1065 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: c:%x\n",
1066 regs
->pN
, crd_freed
);
1070 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1071 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1074 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x
*bp
,
1075 struct pbf_pN_cmd_regs
*regs
,
1078 u32 occup
, to_free
, freed
, freed_start
;
1079 u32 cur_cnt
= poll_count
;
1081 occup
= to_free
= REG_RD(bp
, regs
->lines_occup
);
1082 freed
= freed_start
= REG_RD(bp
, regs
->lines_freed
);
1084 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n", regs
->pN
, occup
);
1085 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n", regs
->pN
, freed
);
1087 while (occup
&& ((u32
)SUB_S32(freed
, freed_start
) < to_free
)) {
1089 udelay(FLR_WAIT_INTERVAL
);
1090 occup
= REG_RD(bp
, regs
->lines_occup
);
1091 freed
= REG_RD(bp
, regs
->lines_freed
);
1093 DP(BNX2X_MSG_SP
, "PBF cmd queue[%d] timed out\n",
1095 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n",
1097 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n",
1102 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1103 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1106 static inline u32
bnx2x_flr_clnup_reg_poll(struct bnx2x
*bp
, u32 reg
,
1107 u32 expected
, u32 poll_count
)
1109 u32 cur_cnt
= poll_count
;
1112 while ((val
= REG_RD(bp
, reg
)) != expected
&& cur_cnt
--)
1113 udelay(FLR_WAIT_INTERVAL
);
1118 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x
*bp
, u32 reg
,
1119 char *msg
, u32 poll_cnt
)
1121 u32 val
= bnx2x_flr_clnup_reg_poll(bp
, reg
, 0, poll_cnt
);
1123 BNX2X_ERR("%s usage count=%d\n", msg
, val
);
1129 static u32
bnx2x_flr_clnup_poll_count(struct bnx2x
*bp
)
1131 /* adjust polling timeout */
1132 if (CHIP_REV_IS_EMUL(bp
))
1133 return FLR_POLL_CNT
* 2000;
1135 if (CHIP_REV_IS_FPGA(bp
))
1136 return FLR_POLL_CNT
* 120;
1138 return FLR_POLL_CNT
;
1141 static void bnx2x_tx_hw_flushed(struct bnx2x
*bp
, u32 poll_count
)
1143 struct pbf_pN_cmd_regs cmd_regs
[] = {
1144 {0, (CHIP_IS_E3B0(bp
)) ?
1145 PBF_REG_TQ_OCCUPANCY_Q0
:
1146 PBF_REG_P0_TQ_OCCUPANCY
,
1147 (CHIP_IS_E3B0(bp
)) ?
1148 PBF_REG_TQ_LINES_FREED_CNT_Q0
:
1149 PBF_REG_P0_TQ_LINES_FREED_CNT
},
1150 {1, (CHIP_IS_E3B0(bp
)) ?
1151 PBF_REG_TQ_OCCUPANCY_Q1
:
1152 PBF_REG_P1_TQ_OCCUPANCY
,
1153 (CHIP_IS_E3B0(bp
)) ?
1154 PBF_REG_TQ_LINES_FREED_CNT_Q1
:
1155 PBF_REG_P1_TQ_LINES_FREED_CNT
},
1156 {4, (CHIP_IS_E3B0(bp
)) ?
1157 PBF_REG_TQ_OCCUPANCY_LB_Q
:
1158 PBF_REG_P4_TQ_OCCUPANCY
,
1159 (CHIP_IS_E3B0(bp
)) ?
1160 PBF_REG_TQ_LINES_FREED_CNT_LB_Q
:
1161 PBF_REG_P4_TQ_LINES_FREED_CNT
}
1164 struct pbf_pN_buf_regs buf_regs
[] = {
1165 {0, (CHIP_IS_E3B0(bp
)) ?
1166 PBF_REG_INIT_CRD_Q0
:
1167 PBF_REG_P0_INIT_CRD
,
1168 (CHIP_IS_E3B0(bp
)) ?
1171 (CHIP_IS_E3B0(bp
)) ?
1172 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
:
1173 PBF_REG_P0_INTERNAL_CRD_FREED_CNT
},
1174 {1, (CHIP_IS_E3B0(bp
)) ?
1175 PBF_REG_INIT_CRD_Q1
:
1176 PBF_REG_P1_INIT_CRD
,
1177 (CHIP_IS_E3B0(bp
)) ?
1180 (CHIP_IS_E3B0(bp
)) ?
1181 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
:
1182 PBF_REG_P1_INTERNAL_CRD_FREED_CNT
},
1183 {4, (CHIP_IS_E3B0(bp
)) ?
1184 PBF_REG_INIT_CRD_LB_Q
:
1185 PBF_REG_P4_INIT_CRD
,
1186 (CHIP_IS_E3B0(bp
)) ?
1187 PBF_REG_CREDIT_LB_Q
:
1189 (CHIP_IS_E3B0(bp
)) ?
1190 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
:
1191 PBF_REG_P4_INTERNAL_CRD_FREED_CNT
},
1196 /* Verify the command queues are flushed P0, P1, P4 */
1197 for (i
= 0; i
< ARRAY_SIZE(cmd_regs
); i
++)
1198 bnx2x_pbf_pN_cmd_flushed(bp
, &cmd_regs
[i
], poll_count
);
1201 /* Verify the transmission buffers are flushed P0, P1, P4 */
1202 for (i
= 0; i
< ARRAY_SIZE(buf_regs
); i
++)
1203 bnx2x_pbf_pN_buf_flushed(bp
, &buf_regs
[i
], poll_count
);
1206 #define OP_GEN_PARAM(param) \
1207 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1209 #define OP_GEN_TYPE(type) \
1210 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1212 #define OP_GEN_AGG_VECT(index) \
1213 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1216 static inline int bnx2x_send_final_clnup(struct bnx2x
*bp
, u8 clnup_func
,
1219 struct sdm_op_gen op_gen
= {0};
1221 u32 comp_addr
= BAR_CSTRORM_INTMEM
+
1222 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func
);
1225 if (REG_RD(bp
, comp_addr
)) {
1226 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1230 op_gen
.command
|= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
);
1231 op_gen
.command
|= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
);
1232 op_gen
.command
|= OP_GEN_AGG_VECT(clnup_func
);
1233 op_gen
.command
|= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
;
1235 DP(BNX2X_MSG_SP
, "sending FW Final cleanup\n");
1236 REG_WR(bp
, XSDM_REG_OPERATION_GEN
, op_gen
.command
);
1238 if (bnx2x_flr_clnup_reg_poll(bp
, comp_addr
, 1, poll_cnt
) != 1) {
1239 BNX2X_ERR("FW final cleanup did not succeed\n");
1242 /* Zero completion for nxt FLR */
1243 REG_WR(bp
, comp_addr
, 0);
1248 static inline u8
bnx2x_is_pcie_pending(struct pci_dev
*dev
)
1253 pos
= pci_pcie_cap(dev
);
1257 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
1258 return status
& PCI_EXP_DEVSTA_TRPND
;
1261 /* PF FLR specific routines
1263 static int bnx2x_poll_hw_usage_counters(struct bnx2x
*bp
, u32 poll_cnt
)
1266 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1267 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1268 CFC_REG_NUM_LCIDS_INSIDE_PF
,
1269 "CFC PF usage counter timed out",
1274 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1275 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1276 DORQ_REG_PF_USAGE_CNT
,
1277 "DQ PF usage counter timed out",
1281 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1282 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1283 QM_REG_PF_USG_CNT_0
+ 4*BP_FUNC(bp
),
1284 "QM PF usage counter timed out",
1288 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1289 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1290 TM_REG_LIN0_VNIC_UC
+ 4*BP_PORT(bp
),
1291 "Timers VNIC usage counter timed out",
1294 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1295 TM_REG_LIN0_NUM_SCANS
+ 4*BP_PORT(bp
),
1296 "Timers NUM_SCANS usage counter timed out",
1300 /* Wait DMAE PF usage counter to zero */
1301 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1302 dmae_reg_go_c
[INIT_DMAE_C(bp
)],
1303 "DMAE dommand register timed out",
1310 static void bnx2x_hw_enable_status(struct bnx2x
*bp
)
1314 val
= REG_RD(bp
, CFC_REG_WEAK_ENABLE_PF
);
1315 DP(BNX2X_MSG_SP
, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val
);
1317 val
= REG_RD(bp
, PBF_REG_DISABLE_PF
);
1318 DP(BNX2X_MSG_SP
, "PBF_REG_DISABLE_PF is 0x%x\n", val
);
1320 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSI_EN
);
1321 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val
);
1323 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_EN
);
1324 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val
);
1326 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_FUNC_MASK
);
1327 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val
);
1329 val
= REG_RD(bp
, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
);
1330 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val
);
1332 val
= REG_RD(bp
, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
);
1333 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val
);
1335 val
= REG_RD(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
1336 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1340 static int bnx2x_pf_flr_clnup(struct bnx2x
*bp
)
1342 u32 poll_cnt
= bnx2x_flr_clnup_poll_count(bp
);
1344 DP(BNX2X_MSG_SP
, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp
));
1346 /* Re-enable PF target read access */
1347 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1349 /* Poll HW usage counters */
1350 DP(BNX2X_MSG_SP
, "Polling usage counters\n");
1351 if (bnx2x_poll_hw_usage_counters(bp
, poll_cnt
))
1354 /* Zero the igu 'trailing edge' and 'leading edge' */
1356 /* Send the FW cleanup command */
1357 if (bnx2x_send_final_clnup(bp
, (u8
)BP_FUNC(bp
), poll_cnt
))
1362 /* Verify TX hw is flushed */
1363 bnx2x_tx_hw_flushed(bp
, poll_cnt
);
1365 /* Wait 100ms (not adjusted according to platform) */
1368 /* Verify no pending pci transactions */
1369 if (bnx2x_is_pcie_pending(bp
->pdev
))
1370 BNX2X_ERR("PCIE Transactions still pending\n");
1373 bnx2x_hw_enable_status(bp
);
1376 * Master enable - Due to WB DMAE writes performed before this
1377 * register is re-initialized as part of the regular function init
1379 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
1384 static void bnx2x_hc_int_enable(struct bnx2x
*bp
)
1386 int port
= BP_PORT(bp
);
1387 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1388 u32 val
= REG_RD(bp
, addr
);
1389 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1390 int msi
= (bp
->flags
& USING_MSI_FLAG
) ? 1 : 0;
1393 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1394 HC_CONFIG_0_REG_INT_LINE_EN_0
);
1395 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1396 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1398 val
&= ~HC_CONFIG_0_REG_INT_LINE_EN_0
;
1399 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1400 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1401 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1403 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1404 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1405 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1406 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1408 if (!CHIP_IS_E1(bp
)) {
1409 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x)\n",
1412 REG_WR(bp
, addr
, val
);
1414 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
1419 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0x1FFFF);
1421 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x) mode %s\n",
1422 val
, port
, addr
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1424 REG_WR(bp
, addr
, val
);
1426 * Ensure that HC_CONFIG is written before leading/trailing edge config
1431 if (!CHIP_IS_E1(bp
)) {
1432 /* init leading/trailing edge */
1434 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1436 /* enable nig and gpio3 attention */
1441 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
1442 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
1445 /* Make sure that interrupts are indeed enabled from here on */
1449 static void bnx2x_igu_int_enable(struct bnx2x
*bp
)
1452 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1453 int msi
= (bp
->flags
& USING_MSI_FLAG
) ? 1 : 0;
1455 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1458 val
&= ~(IGU_PF_CONF_INT_LINE_EN
|
1459 IGU_PF_CONF_SINGLE_ISR_EN
);
1460 val
|= (IGU_PF_CONF_FUNC_EN
|
1461 IGU_PF_CONF_MSI_MSIX_EN
|
1462 IGU_PF_CONF_ATTN_BIT_EN
);
1464 val
&= ~IGU_PF_CONF_INT_LINE_EN
;
1465 val
|= (IGU_PF_CONF_FUNC_EN
|
1466 IGU_PF_CONF_MSI_MSIX_EN
|
1467 IGU_PF_CONF_ATTN_BIT_EN
|
1468 IGU_PF_CONF_SINGLE_ISR_EN
);
1470 val
&= ~IGU_PF_CONF_MSI_MSIX_EN
;
1471 val
|= (IGU_PF_CONF_FUNC_EN
|
1472 IGU_PF_CONF_INT_LINE_EN
|
1473 IGU_PF_CONF_ATTN_BIT_EN
|
1474 IGU_PF_CONF_SINGLE_ISR_EN
);
1477 DP(NETIF_MSG_INTR
, "write 0x%x to IGU mode %s\n",
1478 val
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1480 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1484 /* init leading/trailing edge */
1486 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1488 /* enable nig and gpio3 attention */
1493 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
1494 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
1496 /* Make sure that interrupts are indeed enabled from here on */
1500 void bnx2x_int_enable(struct bnx2x
*bp
)
1502 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1503 bnx2x_hc_int_enable(bp
);
1505 bnx2x_igu_int_enable(bp
);
1508 static void bnx2x_hc_int_disable(struct bnx2x
*bp
)
1510 int port
= BP_PORT(bp
);
1511 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1512 u32 val
= REG_RD(bp
, addr
);
1515 * in E1 we must use only PCI configuration space to disable
1516 * MSI/MSIX capablility
1517 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1519 if (CHIP_IS_E1(bp
)) {
1520 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1521 * Use mask register to prevent from HC sending interrupts
1522 * after we exit the function
1524 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0);
1526 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1527 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1528 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1530 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1531 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1532 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1533 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1535 DP(NETIF_MSG_INTR
, "write %x to HC %d (addr 0x%x)\n",
1538 /* flush all outstanding writes */
1541 REG_WR(bp
, addr
, val
);
1542 if (REG_RD(bp
, addr
) != val
)
1543 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1546 static void bnx2x_igu_int_disable(struct bnx2x
*bp
)
1548 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1550 val
&= ~(IGU_PF_CONF_MSI_MSIX_EN
|
1551 IGU_PF_CONF_INT_LINE_EN
|
1552 IGU_PF_CONF_ATTN_BIT_EN
);
1554 DP(NETIF_MSG_INTR
, "write %x to IGU\n", val
);
1556 /* flush all outstanding writes */
1559 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1560 if (REG_RD(bp
, IGU_REG_PF_CONFIGURATION
) != val
)
1561 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1564 void bnx2x_int_disable(struct bnx2x
*bp
)
1566 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1567 bnx2x_hc_int_disable(bp
);
1569 bnx2x_igu_int_disable(bp
);
1572 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
1574 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1578 /* prevent the HW from sending interrupts */
1579 bnx2x_int_disable(bp
);
1581 /* make sure all ISRs are done */
1583 synchronize_irq(bp
->msix_table
[0].vector
);
1588 for_each_eth_queue(bp
, i
)
1589 synchronize_irq(bp
->msix_table
[offset
++].vector
);
1591 synchronize_irq(bp
->pdev
->irq
);
1593 /* make sure sp_task is not running */
1594 cancel_delayed_work(&bp
->sp_task
);
1595 cancel_delayed_work(&bp
->period_task
);
1596 flush_workqueue(bnx2x_wq
);
1602 * General service functions
1605 /* Return true if succeeded to acquire the lock */
1606 static bool bnx2x_trylock_hw_lock(struct bnx2x
*bp
, u32 resource
)
1609 u32 resource_bit
= (1 << resource
);
1610 int func
= BP_FUNC(bp
);
1611 u32 hw_lock_control_reg
;
1613 DP(NETIF_MSG_HW
, "Trying to take a lock on resource %d\n", resource
);
1615 /* Validating that the resource is within range */
1616 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1618 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1619 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1624 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1626 hw_lock_control_reg
=
1627 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1629 /* Try to acquire the lock */
1630 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1631 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1632 if (lock_status
& resource_bit
)
1635 DP(NETIF_MSG_HW
, "Failed to get a lock on resource %d\n", resource
);
1640 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1642 * @bp: driver handle
1644 * Returns the recovery leader resource id according to the engine this function
1645 * belongs to. Currently only only 2 engines is supported.
1647 static inline int bnx2x_get_leader_lock_resource(struct bnx2x
*bp
)
1650 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1
;
1652 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0
;
1656 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1658 * @bp: driver handle
1660 * Tries to aquire a leader lock for cuurent engine.
1662 static inline bool bnx2x_trylock_leader_lock(struct bnx2x
*bp
)
1664 return bnx2x_trylock_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1668 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
);
1671 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
)
1673 struct bnx2x
*bp
= fp
->bp
;
1674 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1675 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1676 enum bnx2x_queue_cmd drv_cmd
= BNX2X_Q_CMD_MAX
;
1677 struct bnx2x_queue_sp_obj
*q_obj
= &fp
->q_obj
;
1680 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1681 fp
->index
, cid
, command
, bp
->state
,
1682 rr_cqe
->ramrod_cqe
.ramrod_type
);
1685 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE
):
1686 DP(BNX2X_MSG_SP
, "got UPDATE ramrod. CID %d\n", cid
);
1687 drv_cmd
= BNX2X_Q_CMD_UPDATE
;
1690 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
):
1691 DP(BNX2X_MSG_SP
, "got MULTI[%d] setup ramrod\n", cid
);
1692 drv_cmd
= BNX2X_Q_CMD_SETUP
;
1695 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
):
1696 DP(NETIF_MSG_IFUP
, "got MULTI[%d] tx-only setup ramrod\n", cid
);
1697 drv_cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
1700 case (RAMROD_CMD_ID_ETH_HALT
):
1701 DP(BNX2X_MSG_SP
, "got MULTI[%d] halt ramrod\n", cid
);
1702 drv_cmd
= BNX2X_Q_CMD_HALT
;
1705 case (RAMROD_CMD_ID_ETH_TERMINATE
):
1706 DP(BNX2X_MSG_SP
, "got MULTI[%d] teminate ramrod\n", cid
);
1707 drv_cmd
= BNX2X_Q_CMD_TERMINATE
;
1710 case (RAMROD_CMD_ID_ETH_EMPTY
):
1711 DP(BNX2X_MSG_SP
, "got MULTI[%d] empty ramrod\n", cid
);
1712 drv_cmd
= BNX2X_Q_CMD_EMPTY
;
1716 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1717 command
, fp
->index
);
1721 if ((drv_cmd
!= BNX2X_Q_CMD_MAX
) &&
1722 q_obj
->complete_cmd(bp
, q_obj
, drv_cmd
))
1723 /* q_obj->complete_cmd() failure means that this was
1724 * an unexpected completion.
1726 * In this case we don't want to increase the bp->spq_left
1727 * because apparently we haven't sent this command the first
1730 #ifdef BNX2X_STOP_ON_ERROR
1736 smp_mb__before_atomic_inc();
1737 atomic_inc(&bp
->cq_spq_left
);
1738 /* push the change in bp->spq_left and towards the memory */
1739 smp_mb__after_atomic_inc();
1741 DP(BNX2X_MSG_SP
, "bp->cq_spq_left %x\n", atomic_read(&bp
->cq_spq_left
));
1746 void bnx2x_update_rx_prod(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
1747 u16 bd_prod
, u16 rx_comp_prod
, u16 rx_sge_prod
)
1749 u32 start
= BAR_USTRORM_INTMEM
+ fp
->ustorm_rx_prods_offset
;
1751 bnx2x_update_rx_prod_gen(bp
, fp
, bd_prod
, rx_comp_prod
, rx_sge_prod
,
1755 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1757 struct bnx2x
*bp
= netdev_priv(dev_instance
);
1758 u16 status
= bnx2x_ack_int(bp
);
1763 /* Return here if interrupt is shared and it's not for us */
1764 if (unlikely(status
== 0)) {
1765 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1768 DP(NETIF_MSG_INTR
, "got an interrupt status 0x%x\n", status
);
1770 #ifdef BNX2X_STOP_ON_ERROR
1771 if (unlikely(bp
->panic
))
1775 for_each_eth_queue(bp
, i
) {
1776 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1778 mask
= 0x2 << (fp
->index
+ CNIC_PRESENT
);
1779 if (status
& mask
) {
1780 /* Handle Rx or Tx according to SB id */
1781 prefetch(fp
->rx_cons_sb
);
1782 for_each_cos_in_tx_queue(fp
, cos
)
1783 prefetch(fp
->txdata
[cos
].tx_cons_sb
);
1784 prefetch(&fp
->sb_running_index
[SM_RX_ID
]);
1785 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
1792 if (status
& (mask
| 0x1)) {
1793 struct cnic_ops
*c_ops
= NULL
;
1795 if (likely(bp
->state
== BNX2X_STATE_OPEN
)) {
1797 c_ops
= rcu_dereference(bp
->cnic_ops
);
1799 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
1807 if (unlikely(status
& 0x1)) {
1808 queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1815 if (unlikely(status
))
1816 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
1825 * General service functions
1828 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1831 u32 resource_bit
= (1 << resource
);
1832 int func
= BP_FUNC(bp
);
1833 u32 hw_lock_control_reg
;
1836 /* Validating that the resource is within range */
1837 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1839 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1840 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1845 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1847 hw_lock_control_reg
=
1848 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1851 /* Validating that the resource is not already taken */
1852 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1853 if (lock_status
& resource_bit
) {
1854 DP(NETIF_MSG_HW
, "lock_status 0x%x resource_bit 0x%x\n",
1855 lock_status
, resource_bit
);
1859 /* Try for 5 second every 5ms */
1860 for (cnt
= 0; cnt
< 1000; cnt
++) {
1861 /* Try to acquire the lock */
1862 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1863 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1864 if (lock_status
& resource_bit
)
1869 DP(NETIF_MSG_HW
, "Timeout\n");
1873 int bnx2x_release_leader_lock(struct bnx2x
*bp
)
1875 return bnx2x_release_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1878 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
1881 u32 resource_bit
= (1 << resource
);
1882 int func
= BP_FUNC(bp
);
1883 u32 hw_lock_control_reg
;
1885 DP(NETIF_MSG_HW
, "Releasing a lock on resource %d\n", resource
);
1887 /* Validating that the resource is within range */
1888 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1890 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1891 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1896 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1898 hw_lock_control_reg
=
1899 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1902 /* Validating that the resource is currently taken */
1903 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1904 if (!(lock_status
& resource_bit
)) {
1905 DP(NETIF_MSG_HW
, "lock_status 0x%x resource_bit 0x%x\n",
1906 lock_status
, resource_bit
);
1910 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
1915 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
)
1917 /* The GPIO should be swapped if swap register is set and active */
1918 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1919 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
1920 int gpio_shift
= gpio_num
+
1921 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
1922 u32 gpio_mask
= (1 << gpio_shift
);
1926 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
1927 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
1931 /* read GPIO value */
1932 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
1934 /* get the requested pin value */
1935 if ((gpio_reg
& gpio_mask
) == gpio_mask
)
1940 DP(NETIF_MSG_LINK
, "pin %d value 0x%x\n", gpio_num
, value
);
1945 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
1947 /* The GPIO should be swapped if swap register is set and active */
1948 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1949 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
1950 int gpio_shift
= gpio_num
+
1951 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
1952 u32 gpio_mask
= (1 << gpio_shift
);
1955 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
1956 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
1960 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1961 /* read GPIO and mask except the float bits */
1962 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
1965 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
1966 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> output low\n",
1967 gpio_num
, gpio_shift
);
1968 /* clear FLOAT and set CLR */
1969 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1970 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
1973 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
1974 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> output high\n",
1975 gpio_num
, gpio_shift
);
1976 /* clear FLOAT and set SET */
1977 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1978 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
1981 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
1982 DP(NETIF_MSG_LINK
, "Set GPIO %d (shift %d) -> input\n",
1983 gpio_num
, gpio_shift
);
1985 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1992 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
1993 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1998 int bnx2x_set_mult_gpio(struct bnx2x
*bp
, u8 pins
, u32 mode
)
2003 /* Any port swapping should be handled by caller. */
2005 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2006 /* read GPIO and mask except the float bits */
2007 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2008 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2009 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2010 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2013 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2014 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output low\n", pins
);
2016 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2019 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2020 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output high\n", pins
);
2022 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2025 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2026 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> input\n", pins
);
2028 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2032 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode
);
2038 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2040 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2045 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2047 /* The GPIO should be swapped if swap register is set and active */
2048 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2049 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2050 int gpio_shift
= gpio_num
+
2051 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2052 u32 gpio_mask
= (1 << gpio_shift
);
2055 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2056 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2060 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2062 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO_INT
);
2065 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
:
2066 DP(NETIF_MSG_LINK
, "Clear GPIO INT %d (shift %d) -> "
2067 "output low\n", gpio_num
, gpio_shift
);
2068 /* clear SET and set CLR */
2069 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2070 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2073 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET
:
2074 DP(NETIF_MSG_LINK
, "Set GPIO INT %d (shift %d) -> "
2075 "output high\n", gpio_num
, gpio_shift
);
2076 /* clear CLR and set SET */
2077 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2078 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2085 REG_WR(bp
, MISC_REG_GPIO_INT
, gpio_reg
);
2086 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2091 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio_num
, u32 mode
)
2093 u32 spio_mask
= (1 << spio_num
);
2096 if ((spio_num
< MISC_REGISTERS_SPIO_4
) ||
2097 (spio_num
> MISC_REGISTERS_SPIO_7
)) {
2098 BNX2X_ERR("Invalid SPIO %d\n", spio_num
);
2102 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2103 /* read SPIO and mask except the float bits */
2104 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_REGISTERS_SPIO_FLOAT
);
2107 case MISC_REGISTERS_SPIO_OUTPUT_LOW
:
2108 DP(NETIF_MSG_LINK
, "Set SPIO %d -> output low\n", spio_num
);
2109 /* clear FLOAT and set CLR */
2110 spio_reg
&= ~(spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2111 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_CLR_POS
);
2114 case MISC_REGISTERS_SPIO_OUTPUT_HIGH
:
2115 DP(NETIF_MSG_LINK
, "Set SPIO %d -> output high\n", spio_num
);
2116 /* clear FLOAT and set SET */
2117 spio_reg
&= ~(spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2118 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_SET_POS
);
2121 case MISC_REGISTERS_SPIO_INPUT_HI_Z
:
2122 DP(NETIF_MSG_LINK
, "Set SPIO %d -> input\n", spio_num
);
2124 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2131 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
2132 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2137 void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
2139 u8 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2140 switch (bp
->link_vars
.ieee_fc
&
2141 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) {
2142 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
:
2143 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2147 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
2148 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Asym_Pause
|
2152 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
2153 bp
->port
.advertising
[cfg_idx
] |= ADVERTISED_Asym_Pause
;
2157 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2163 u8
bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
)
2165 if (!BP_NOMCP(bp
)) {
2167 int cfx_idx
= bnx2x_get_link_cfg_idx(bp
);
2168 u16 req_line_speed
= bp
->link_params
.req_line_speed
[cfx_idx
];
2170 * Initialize link parameters structure variables
2171 * It is recommended to turn off RX FC for jumbo frames
2172 * for better performance
2174 if (CHIP_IS_E1x(bp
) && (bp
->dev
->mtu
> 5000))
2175 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
2177 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
2179 bnx2x_acquire_phy_lock(bp
);
2181 if (load_mode
== LOAD_DIAG
) {
2182 struct link_params
*lp
= &bp
->link_params
;
2183 lp
->loopback_mode
= LOOPBACK_XGXS
;
2184 /* do PHY loopback at 10G speed, if possible */
2185 if (lp
->req_line_speed
[cfx_idx
] < SPEED_10000
) {
2186 if (lp
->speed_cap_mask
[cfx_idx
] &
2187 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
2188 lp
->req_line_speed
[cfx_idx
] =
2191 lp
->req_line_speed
[cfx_idx
] =
2196 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2198 bnx2x_release_phy_lock(bp
);
2200 bnx2x_calc_fc_adv(bp
);
2202 if (CHIP_REV_IS_SLOW(bp
) && bp
->link_vars
.link_up
) {
2203 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2204 bnx2x_link_report(bp
);
2206 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2207 bp
->link_params
.req_line_speed
[cfx_idx
] = req_line_speed
;
2210 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2214 void bnx2x_link_set(struct bnx2x
*bp
)
2216 if (!BP_NOMCP(bp
)) {
2217 bnx2x_acquire_phy_lock(bp
);
2218 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2219 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2220 bnx2x_release_phy_lock(bp
);
2222 bnx2x_calc_fc_adv(bp
);
2224 BNX2X_ERR("Bootcode is missing - can not set link\n");
2227 static void bnx2x__link_reset(struct bnx2x
*bp
)
2229 if (!BP_NOMCP(bp
)) {
2230 bnx2x_acquire_phy_lock(bp
);
2231 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2232 bnx2x_release_phy_lock(bp
);
2234 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2237 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
)
2241 if (!BP_NOMCP(bp
)) {
2242 bnx2x_acquire_phy_lock(bp
);
2243 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
,
2245 bnx2x_release_phy_lock(bp
);
2247 BNX2X_ERR("Bootcode is missing - can not test link\n");
2252 static void bnx2x_init_port_minmax(struct bnx2x
*bp
)
2254 u32 r_param
= bp
->link_vars
.line_speed
/ 8;
2255 u32 fair_periodic_timeout_usec
;
2258 memset(&(bp
->cmng
.rs_vars
), 0,
2259 sizeof(struct rate_shaping_vars_per_port
));
2260 memset(&(bp
->cmng
.fair_vars
), 0, sizeof(struct fairness_vars_per_port
));
2262 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2263 bp
->cmng
.rs_vars
.rs_periodic_timeout
= RS_PERIODIC_TIMEOUT_USEC
/ 4;
2265 /* this is the threshold below which no timer arming will occur
2266 1.25 coefficient is for the threshold to be a little bigger
2267 than the real time, to compensate for timer in-accuracy */
2268 bp
->cmng
.rs_vars
.rs_threshold
=
2269 (RS_PERIODIC_TIMEOUT_USEC
* r_param
* 5) / 4;
2271 /* resolution of fairness timer */
2272 fair_periodic_timeout_usec
= QM_ARB_BYTES
/ r_param
;
2273 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2274 t_fair
= T_FAIR_COEF
/ bp
->link_vars
.line_speed
;
2276 /* this is the threshold below which we won't arm the timer anymore */
2277 bp
->cmng
.fair_vars
.fair_threshold
= QM_ARB_BYTES
;
2279 /* we multiply by 1e3/8 to get bytes/msec.
2280 We don't want the credits to pass a credit
2281 of the t_fair*FAIR_MEM (algorithm resolution) */
2282 bp
->cmng
.fair_vars
.upper_bound
= r_param
* t_fair
* FAIR_MEM
;
2283 /* since each tick is 4 usec */
2284 bp
->cmng
.fair_vars
.fairness_timeout
= fair_periodic_timeout_usec
/ 4;
2287 /* Calculates the sum of vn_min_rates.
2288 It's needed for further normalizing of the min_rates.
2290 sum of vn_min_rates.
2292 0 - if all the min_rates are 0.
2293 In the later case fainess algorithm should be deactivated.
2294 If not all min_rates are zero then those that are zeroes will be set to 1.
2296 static void bnx2x_calc_vn_weight_sum(struct bnx2x
*bp
)
2301 bp
->vn_weight_sum
= 0;
2302 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2303 u32 vn_cfg
= bp
->mf_config
[vn
];
2304 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2305 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2307 /* Skip hidden vns */
2308 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2311 /* If min rate is zero - set it to 1 */
2313 vn_min_rate
= DEF_MIN_RATE
;
2317 bp
->vn_weight_sum
+= vn_min_rate
;
2320 /* if ETS or all min rates are zeros - disable fairness */
2321 if (BNX2X_IS_ETS_ENABLED(bp
)) {
2322 bp
->cmng
.flags
.cmng_enables
&=
2323 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2324 DP(NETIF_MSG_IFUP
, "Fairness will be disabled due to ETS\n");
2325 } else if (all_zero
) {
2326 bp
->cmng
.flags
.cmng_enables
&=
2327 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2328 DP(NETIF_MSG_IFUP
, "All MIN values are zeroes"
2329 " fairness will be disabled\n");
2331 bp
->cmng
.flags
.cmng_enables
|=
2332 CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2335 static void bnx2x_init_vn_minmax(struct bnx2x
*bp
, int vn
)
2337 struct rate_shaping_vars_per_vn m_rs_vn
;
2338 struct fairness_vars_per_vn m_fair_vn
;
2339 u32 vn_cfg
= bp
->mf_config
[vn
];
2340 int func
= func_by_vn(bp
, vn
);
2341 u16 vn_min_rate
, vn_max_rate
;
2344 /* If function is hidden - set min and max to zeroes */
2345 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
) {
2350 u32 maxCfg
= bnx2x_extract_max_cfg(bp
, vn_cfg
);
2352 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2353 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2354 /* If fairness is enabled (not all min rates are zeroes) and
2355 if current min rate is zero - set it to 1.
2356 This is a requirement of the algorithm. */
2357 if (bp
->vn_weight_sum
&& (vn_min_rate
== 0))
2358 vn_min_rate
= DEF_MIN_RATE
;
2361 /* maxCfg in percents of linkspeed */
2362 vn_max_rate
= (bp
->link_vars
.line_speed
* maxCfg
) / 100;
2364 /* maxCfg is absolute in 100Mb units */
2365 vn_max_rate
= maxCfg
* 100;
2369 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2370 func
, vn_min_rate
, vn_max_rate
, bp
->vn_weight_sum
);
2372 memset(&m_rs_vn
, 0, sizeof(struct rate_shaping_vars_per_vn
));
2373 memset(&m_fair_vn
, 0, sizeof(struct fairness_vars_per_vn
));
2375 /* global vn counter - maximal Mbps for this vn */
2376 m_rs_vn
.vn_counter
.rate
= vn_max_rate
;
2378 /* quota - number of bytes transmitted in this period */
2379 m_rs_vn
.vn_counter
.quota
=
2380 (vn_max_rate
* RS_PERIODIC_TIMEOUT_USEC
) / 8;
2382 if (bp
->vn_weight_sum
) {
2383 /* credit for each period of the fairness algorithm:
2384 number of bytes in T_FAIR (the vn share the port rate).
2385 vn_weight_sum should not be larger than 10000, thus
2386 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2388 m_fair_vn
.vn_credit_delta
=
2389 max_t(u32
, (vn_min_rate
* (T_FAIR_COEF
/
2390 (8 * bp
->vn_weight_sum
))),
2391 (bp
->cmng
.fair_vars
.fair_threshold
+
2393 DP(NETIF_MSG_IFUP
, "m_fair_vn.vn_credit_delta %d\n",
2394 m_fair_vn
.vn_credit_delta
);
2397 /* Store it to internal memory */
2398 for (i
= 0; i
< sizeof(struct rate_shaping_vars_per_vn
)/4; i
++)
2399 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2400 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
) + i
* 4,
2401 ((u32
*)(&m_rs_vn
))[i
]);
2403 for (i
= 0; i
< sizeof(struct fairness_vars_per_vn
)/4; i
++)
2404 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2405 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
) + i
* 4,
2406 ((u32
*)(&m_fair_vn
))[i
]);
2409 static int bnx2x_get_cmng_fns_mode(struct bnx2x
*bp
)
2411 if (CHIP_REV_IS_SLOW(bp
))
2412 return CMNG_FNS_NONE
;
2414 return CMNG_FNS_MINMAX
;
2416 return CMNG_FNS_NONE
;
2419 void bnx2x_read_mf_cfg(struct bnx2x
*bp
)
2421 int vn
, n
= (CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1);
2424 return; /* what should be the default bvalue in this case */
2426 /* For 2 port configuration the absolute function number formula
2428 * abs_func = 2 * vn + BP_PORT + BP_PATH
2430 * and there are 4 functions per port
2432 * For 4 port configuration it is
2433 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2435 * and there are 2 functions per port
2437 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2438 int /*abs*/func
= n
* (2 * vn
+ BP_PORT(bp
)) + BP_PATH(bp
);
2440 if (func
>= E1H_FUNC_MAX
)
2444 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2448 static void bnx2x_cmng_fns_init(struct bnx2x
*bp
, u8 read_cfg
, u8 cmng_type
)
2451 if (cmng_type
== CMNG_FNS_MINMAX
) {
2454 /* clear cmng_enables */
2455 bp
->cmng
.flags
.cmng_enables
= 0;
2457 /* read mf conf from shmem */
2459 bnx2x_read_mf_cfg(bp
);
2461 /* Init rate shaping and fairness contexts */
2462 bnx2x_init_port_minmax(bp
);
2464 /* vn_weight_sum and enable fairness if not 0 */
2465 bnx2x_calc_vn_weight_sum(bp
);
2467 /* calculate and set min-max rate for each vn */
2469 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++)
2470 bnx2x_init_vn_minmax(bp
, vn
);
2472 /* always enable rate shaping and fairness */
2473 bp
->cmng
.flags
.cmng_enables
|=
2474 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
;
2475 if (!bp
->vn_weight_sum
)
2476 DP(NETIF_MSG_IFUP
, "All MIN values are zeroes"
2477 " fairness will be disabled\n");
2481 /* rate shaping and fairness are disabled */
2483 "rate shaping and fairness are disabled\n");
2486 /* This function is called upon link interrupt */
2487 static void bnx2x_link_attn(struct bnx2x
*bp
)
2489 /* Make sure that we are synced with the current statistics */
2490 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2492 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2494 if (bp
->link_vars
.link_up
) {
2496 /* dropless flow control */
2497 if (!CHIP_IS_E1(bp
) && bp
->dropless_fc
) {
2498 int port
= BP_PORT(bp
);
2499 u32 pause_enabled
= 0;
2501 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
2504 REG_WR(bp
, BAR_USTRORM_INTMEM
+
2505 USTORM_ETH_PAUSE_ENABLED_OFFSET(port
),
2509 if (bp
->link_vars
.mac_type
!= MAC_TYPE_EMAC
) {
2510 struct host_port_stats
*pstats
;
2512 pstats
= bnx2x_sp(bp
, port_stats
);
2513 /* reset old mac stats */
2514 memset(&(pstats
->mac_stx
[0]), 0,
2515 sizeof(struct mac_stx
));
2517 if (bp
->state
== BNX2X_STATE_OPEN
)
2518 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2521 if (bp
->link_vars
.link_up
&& bp
->link_vars
.line_speed
) {
2522 int cmng_fns
= bnx2x_get_cmng_fns_mode(bp
);
2524 if (cmng_fns
!= CMNG_FNS_NONE
) {
2525 bnx2x_cmng_fns_init(bp
, false, cmng_fns
);
2526 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2528 /* rate shaping and fairness are disabled */
2530 "single function mode without fairness\n");
2533 __bnx2x_link_report(bp
);
2536 bnx2x_link_sync_notify(bp
);
2539 void bnx2x__link_status_update(struct bnx2x
*bp
)
2541 if (bp
->state
!= BNX2X_STATE_OPEN
)
2544 /* read updated dcb configuration */
2545 bnx2x_dcbx_pmf_update(bp
);
2547 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2549 if (bp
->link_vars
.link_up
)
2550 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2552 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2554 /* indicate link status */
2555 bnx2x_link_report(bp
);
2558 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2560 int port
= BP_PORT(bp
);
2564 DP(NETIF_MSG_LINK
, "pmf %d\n", bp
->port
.pmf
);
2567 * We need the mb() to ensure the ordering between the writing to
2568 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2572 /* queue a periodic task */
2573 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2575 bnx2x_dcbx_pmf_update(bp
);
2577 /* enable nig attention */
2578 val
= (0xff0f | (1 << (BP_VN(bp
) + 4)));
2579 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
2580 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2581 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2582 } else if (!CHIP_IS_E1x(bp
)) {
2583 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
2584 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
2587 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
2595 * General service functions
2598 /* send the MCP a request, block until there is a reply */
2599 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
)
2601 int mb_idx
= BP_FW_MB_IDX(bp
);
2605 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
2607 mutex_lock(&bp
->fw_mb_mutex
);
2609 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_param
, param
);
2610 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_header
, (command
| seq
));
2612 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB param 0x%08x\n",
2613 (command
| seq
), param
);
2616 /* let the FW do it's magic ... */
2619 rc
= SHMEM_RD(bp
, func_mb
[mb_idx
].fw_mb_header
);
2621 /* Give the FW up to 5 second (500*10ms) */
2622 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 500));
2624 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2625 cnt
*delay
, rc
, seq
);
2627 /* is this a reply to our command? */
2628 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
))
2629 rc
&= FW_MSG_CODE_MASK
;
2632 BNX2X_ERR("FW failed to respond!\n");
2636 mutex_unlock(&bp
->fw_mb_mutex
);
2642 void bnx2x_func_init(struct bnx2x
*bp
, struct bnx2x_func_init_params
*p
)
2644 if (CHIP_IS_E1x(bp
)) {
2645 struct tstorm_eth_function_common_config tcfg
= {0};
2647 storm_memset_func_cfg(bp
, &tcfg
, p
->func_id
);
2650 /* Enable the function in the FW */
2651 storm_memset_vf_to_pf(bp
, p
->func_id
, p
->pf_id
);
2652 storm_memset_func_en(bp
, p
->func_id
, 1);
2655 if (p
->func_flgs
& FUNC_FLG_SPQ
) {
2656 storm_memset_spq_addr(bp
, p
->spq_map
, p
->func_id
);
2657 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+
2658 XSTORM_SPQ_PROD_OFFSET(p
->func_id
), p
->spq_prod
);
2663 * bnx2x_get_tx_only_flags - Return common flags
2667 * @zero_stats TRUE if statistics zeroing is needed
2669 * Return the flags that are common for the Tx-only and not normal connections.
2671 static inline unsigned long bnx2x_get_common_flags(struct bnx2x
*bp
,
2672 struct bnx2x_fastpath
*fp
,
2675 unsigned long flags
= 0;
2677 /* PF driver will always initialize the Queue to an ACTIVE state */
2678 __set_bit(BNX2X_Q_FLG_ACTIVE
, &flags
);
2680 /* tx only connections collect statistics (on the same index as the
2681 * parent connection). The statistics are zeroed when the parent
2682 * connection is initialized.
2685 __set_bit(BNX2X_Q_FLG_STATS
, &flags
);
2687 __set_bit(BNX2X_Q_FLG_ZERO_STATS
, &flags
);
2693 static inline unsigned long bnx2x_get_q_flags(struct bnx2x
*bp
,
2694 struct bnx2x_fastpath
*fp
,
2697 unsigned long flags
= 0;
2699 /* calculate other queue flags */
2701 __set_bit(BNX2X_Q_FLG_OV
, &flags
);
2704 __set_bit(BNX2X_Q_FLG_FCOE
, &flags
);
2706 if (!fp
->disable_tpa
) {
2707 __set_bit(BNX2X_Q_FLG_TPA
, &flags
);
2708 __set_bit(BNX2X_Q_FLG_TPA_IPV6
, &flags
);
2712 __set_bit(BNX2X_Q_FLG_LEADING_RSS
, &flags
);
2713 __set_bit(BNX2X_Q_FLG_MCAST
, &flags
);
2716 /* Always set HW VLAN stripping */
2717 __set_bit(BNX2X_Q_FLG_VLAN
, &flags
);
2720 return flags
| bnx2x_get_common_flags(bp
, fp
, true);
2723 static void bnx2x_pf_q_prep_general(struct bnx2x
*bp
,
2724 struct bnx2x_fastpath
*fp
, struct bnx2x_general_setup_params
*gen_init
,
2727 gen_init
->stat_id
= bnx2x_stats_id(fp
);
2728 gen_init
->spcl_id
= fp
->cl_id
;
2730 /* Always use mini-jumbo MTU for FCoE L2 ring */
2732 gen_init
->mtu
= BNX2X_FCOE_MINI_JUMBO_MTU
;
2734 gen_init
->mtu
= bp
->dev
->mtu
;
2736 gen_init
->cos
= cos
;
2739 static void bnx2x_pf_rx_q_prep(struct bnx2x
*bp
,
2740 struct bnx2x_fastpath
*fp
, struct rxq_pause_params
*pause
,
2741 struct bnx2x_rxq_setup_params
*rxq_init
)
2745 u16 tpa_agg_size
= 0;
2747 if (!fp
->disable_tpa
) {
2748 pause
->sge_th_lo
= SGE_TH_LO(bp
);
2749 pause
->sge_th_hi
= SGE_TH_HI(bp
);
2751 /* validate SGE ring has enough to cross high threshold */
2752 WARN_ON(bp
->dropless_fc
&&
2753 pause
->sge_th_hi
+ FW_PREFETCH_CNT
>
2754 MAX_RX_SGE_CNT
* NUM_RX_SGE_PAGES
);
2756 tpa_agg_size
= min_t(u32
,
2757 (min_t(u32
, 8, MAX_SKB_FRAGS
) *
2758 SGE_PAGE_SIZE
* PAGES_PER_SGE
), 0xffff);
2759 max_sge
= SGE_PAGE_ALIGN(bp
->dev
->mtu
) >>
2761 max_sge
= ((max_sge
+ PAGES_PER_SGE
- 1) &
2762 (~(PAGES_PER_SGE
-1))) >> PAGES_PER_SGE_SHIFT
;
2763 sge_sz
= (u16
)min_t(u32
, SGE_PAGE_SIZE
* PAGES_PER_SGE
,
2767 /* pause - not for e1 */
2768 if (!CHIP_IS_E1(bp
)) {
2769 pause
->bd_th_lo
= BD_TH_LO(bp
);
2770 pause
->bd_th_hi
= BD_TH_HI(bp
);
2772 pause
->rcq_th_lo
= RCQ_TH_LO(bp
);
2773 pause
->rcq_th_hi
= RCQ_TH_HI(bp
);
2775 * validate that rings have enough entries to cross
2778 WARN_ON(bp
->dropless_fc
&&
2779 pause
->bd_th_hi
+ FW_PREFETCH_CNT
>
2781 WARN_ON(bp
->dropless_fc
&&
2782 pause
->rcq_th_hi
+ FW_PREFETCH_CNT
>
2783 NUM_RCQ_RINGS
* MAX_RCQ_DESC_CNT
);
2789 rxq_init
->dscr_map
= fp
->rx_desc_mapping
;
2790 rxq_init
->sge_map
= fp
->rx_sge_mapping
;
2791 rxq_init
->rcq_map
= fp
->rx_comp_mapping
;
2792 rxq_init
->rcq_np_map
= fp
->rx_comp_mapping
+ BCM_PAGE_SIZE
;
2794 /* This should be a maximum number of data bytes that may be
2795 * placed on the BD (not including paddings).
2797 rxq_init
->buf_sz
= fp
->rx_buf_size
- BNX2X_FW_RX_ALIGN_START
-
2798 BNX2X_FW_RX_ALIGN_END
- IP_HEADER_ALIGNMENT_PADDING
;
2800 rxq_init
->cl_qzone_id
= fp
->cl_qzone_id
;
2801 rxq_init
->tpa_agg_sz
= tpa_agg_size
;
2802 rxq_init
->sge_buf_sz
= sge_sz
;
2803 rxq_init
->max_sges_pkt
= max_sge
;
2804 rxq_init
->rss_engine_id
= BP_FUNC(bp
);
2806 /* Maximum number or simultaneous TPA aggregation for this Queue.
2808 * For PF Clients it should be the maximum avaliable number.
2809 * VF driver(s) may want to define it to a smaller value.
2811 rxq_init
->max_tpa_queues
= MAX_AGG_QS(bp
);
2813 rxq_init
->cache_line_log
= BNX2X_RX_ALIGN_SHIFT
;
2814 rxq_init
->fw_sb_id
= fp
->fw_sb_id
;
2817 rxq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
;
2819 rxq_init
->sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
2822 static void bnx2x_pf_tx_q_prep(struct bnx2x
*bp
,
2823 struct bnx2x_fastpath
*fp
, struct bnx2x_txq_setup_params
*txq_init
,
2826 txq_init
->dscr_map
= fp
->txdata
[cos
].tx_desc_mapping
;
2827 txq_init
->sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
+ cos
;
2828 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_NW
;
2829 txq_init
->fw_sb_id
= fp
->fw_sb_id
;
2832 * set the tss leading client id for TX classfication ==
2833 * leading RSS client id
2835 txq_init
->tss_leading_cl_id
= bnx2x_fp(bp
, 0, cl_id
);
2837 if (IS_FCOE_FP(fp
)) {
2838 txq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
;
2839 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_FCOE
;
2843 static void bnx2x_pf_init(struct bnx2x
*bp
)
2845 struct bnx2x_func_init_params func_init
= {0};
2846 struct event_ring_data eq_data
= { {0} };
2849 if (!CHIP_IS_E1x(bp
)) {
2850 /* reset IGU PF statistics: MSIX + ATTN */
2852 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
2853 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
2854 (CHIP_MODE_IS_4_PORT(bp
) ?
2855 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
2857 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
2858 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
2859 BNX2X_IGU_STAS_MSG_PF_CNT
*4 +
2860 (CHIP_MODE_IS_4_PORT(bp
) ?
2861 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
2864 /* function setup flags */
2865 flags
= (FUNC_FLG_STATS
| FUNC_FLG_LEADING
| FUNC_FLG_SPQ
);
2867 /* This flag is relevant for E1x only.
2868 * E2 doesn't have a TPA configuration in a function level.
2870 flags
|= (bp
->flags
& TPA_ENABLE_FLAG
) ? FUNC_FLG_TPA
: 0;
2872 func_init
.func_flgs
= flags
;
2873 func_init
.pf_id
= BP_FUNC(bp
);
2874 func_init
.func_id
= BP_FUNC(bp
);
2875 func_init
.spq_map
= bp
->spq_mapping
;
2876 func_init
.spq_prod
= bp
->spq_prod_idx
;
2878 bnx2x_func_init(bp
, &func_init
);
2880 memset(&(bp
->cmng
), 0, sizeof(struct cmng_struct_per_port
));
2883 * Congestion management values depend on the link rate
2884 * There is no active link so initial link rate is set to 10 Gbps.
2885 * When the link comes up The congestion management values are
2886 * re-calculated according to the actual link rate.
2888 bp
->link_vars
.line_speed
= SPEED_10000
;
2889 bnx2x_cmng_fns_init(bp
, true, bnx2x_get_cmng_fns_mode(bp
));
2891 /* Only the PMF sets the HW */
2893 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2895 /* init Event Queue */
2896 eq_data
.base_addr
.hi
= U64_HI(bp
->eq_mapping
);
2897 eq_data
.base_addr
.lo
= U64_LO(bp
->eq_mapping
);
2898 eq_data
.producer
= bp
->eq_prod
;
2899 eq_data
.index_id
= HC_SP_INDEX_EQ_CONS
;
2900 eq_data
.sb_id
= DEF_SB_ID
;
2901 storm_memset_eq_data(bp
, &eq_data
, BP_FUNC(bp
));
2905 static void bnx2x_e1h_disable(struct bnx2x
*bp
)
2907 int port
= BP_PORT(bp
);
2909 bnx2x_tx_disable(bp
);
2911 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
2914 static void bnx2x_e1h_enable(struct bnx2x
*bp
)
2916 int port
= BP_PORT(bp
);
2918 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
2920 /* Tx queue should be only reenabled */
2921 netif_tx_wake_all_queues(bp
->dev
);
2924 * Should not call netif_carrier_on since it will be called if the link
2925 * is up when checking for link state
2929 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
2931 static void bnx2x_drv_info_ether_stat(struct bnx2x
*bp
)
2933 struct eth_stats_info
*ether_stat
=
2934 &bp
->slowpath
->drv_info_to_mcp
.ether_stat
;
2936 /* leave last char as NULL */
2937 memcpy(ether_stat
->version
, DRV_MODULE_VERSION
,
2938 ETH_STAT_INFO_VERSION_LEN
- 1);
2940 bp
->fp
[0].mac_obj
.get_n_elements(bp
, &bp
->fp
[0].mac_obj
,
2941 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
,
2942 ether_stat
->mac_local
);
2944 ether_stat
->mtu_size
= bp
->dev
->mtu
;
2946 if (bp
->dev
->features
& NETIF_F_RXCSUM
)
2947 ether_stat
->feature_flags
|= FEATURE_ETH_CHKSUM_OFFLOAD_MASK
;
2948 if (bp
->dev
->features
& NETIF_F_TSO
)
2949 ether_stat
->feature_flags
|= FEATURE_ETH_LSO_MASK
;
2950 ether_stat
->feature_flags
|= bp
->common
.boot_mode
;
2952 ether_stat
->promiscuous_mode
= (bp
->dev
->flags
& IFF_PROMISC
) ? 1 : 0;
2954 ether_stat
->txq_size
= bp
->tx_ring_size
;
2955 ether_stat
->rxq_size
= bp
->rx_ring_size
;
2958 static void bnx2x_drv_info_fcoe_stat(struct bnx2x
*bp
)
2961 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
2962 struct fcoe_stats_info
*fcoe_stat
=
2963 &bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
;
2965 memcpy(fcoe_stat
->mac_local
, bp
->fip_mac
, ETH_ALEN
);
2967 fcoe_stat
->qos_priority
=
2968 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_FCOE
];
2970 /* insert FCoE stats from ramrod response */
2972 struct tstorm_per_queue_stats
*fcoe_q_tstorm_stats
=
2973 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX
].
2974 tstorm_queue_statistics
;
2976 struct xstorm_per_queue_stats
*fcoe_q_xstorm_stats
=
2977 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX
].
2978 xstorm_queue_statistics
;
2980 struct fcoe_statistics_params
*fw_fcoe_stat
=
2981 &bp
->fw_stats_data
->fcoe
;
2983 ADD_64(fcoe_stat
->rx_bytes_hi
, 0, fcoe_stat
->rx_bytes_lo
,
2984 fw_fcoe_stat
->rx_stat0
.fcoe_rx_byte_cnt
);
2986 ADD_64(fcoe_stat
->rx_bytes_hi
,
2987 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.hi
,
2988 fcoe_stat
->rx_bytes_lo
,
2989 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.lo
);
2991 ADD_64(fcoe_stat
->rx_bytes_hi
,
2992 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.hi
,
2993 fcoe_stat
->rx_bytes_lo
,
2994 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.lo
);
2996 ADD_64(fcoe_stat
->rx_bytes_hi
,
2997 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.hi
,
2998 fcoe_stat
->rx_bytes_lo
,
2999 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.lo
);
3001 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
3002 fw_fcoe_stat
->rx_stat0
.fcoe_rx_pkt_cnt
);
3004 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
3005 fcoe_q_tstorm_stats
->rcv_ucast_pkts
);
3007 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
3008 fcoe_q_tstorm_stats
->rcv_bcast_pkts
);
3010 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
3011 fcoe_q_tstorm_stats
->rcv_mcast_pkts
);
3013 ADD_64(fcoe_stat
->tx_bytes_hi
, 0, fcoe_stat
->tx_bytes_lo
,
3014 fw_fcoe_stat
->tx_stat
.fcoe_tx_byte_cnt
);
3016 ADD_64(fcoe_stat
->tx_bytes_hi
,
3017 fcoe_q_xstorm_stats
->ucast_bytes_sent
.hi
,
3018 fcoe_stat
->tx_bytes_lo
,
3019 fcoe_q_xstorm_stats
->ucast_bytes_sent
.lo
);
3021 ADD_64(fcoe_stat
->tx_bytes_hi
,
3022 fcoe_q_xstorm_stats
->bcast_bytes_sent
.hi
,
3023 fcoe_stat
->tx_bytes_lo
,
3024 fcoe_q_xstorm_stats
->bcast_bytes_sent
.lo
);
3026 ADD_64(fcoe_stat
->tx_bytes_hi
,
3027 fcoe_q_xstorm_stats
->mcast_bytes_sent
.hi
,
3028 fcoe_stat
->tx_bytes_lo
,
3029 fcoe_q_xstorm_stats
->mcast_bytes_sent
.lo
);
3031 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3032 fw_fcoe_stat
->tx_stat
.fcoe_tx_pkt_cnt
);
3034 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3035 fcoe_q_xstorm_stats
->ucast_pkts_sent
);
3037 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3038 fcoe_q_xstorm_stats
->bcast_pkts_sent
);
3040 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3041 fcoe_q_xstorm_stats
->mcast_pkts_sent
);
3044 /* ask L5 driver to add data to the struct */
3045 bnx2x_cnic_notify(bp
, CNIC_CTL_FCOE_STATS_GET_CMD
);
3049 static void bnx2x_drv_info_iscsi_stat(struct bnx2x
*bp
)
3052 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3053 struct iscsi_stats_info
*iscsi_stat
=
3054 &bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
;
3056 memcpy(iscsi_stat
->mac_local
, bp
->cnic_eth_dev
.iscsi_mac
, ETH_ALEN
);
3058 iscsi_stat
->qos_priority
=
3059 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_ISCSI
];
3061 /* ask L5 driver to add data to the struct */
3062 bnx2x_cnic_notify(bp
, CNIC_CTL_ISCSI_STATS_GET_CMD
);
3066 /* called due to MCP event (on pmf):
3067 * reread new bandwidth configuration
3069 * notify others function about the change
3071 static inline void bnx2x_config_mf_bw(struct bnx2x
*bp
)
3073 if (bp
->link_vars
.link_up
) {
3074 bnx2x_cmng_fns_init(bp
, true, CMNG_FNS_MINMAX
);
3075 bnx2x_link_sync_notify(bp
);
3077 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3080 static inline void bnx2x_set_mf_bw(struct bnx2x
*bp
)
3082 bnx2x_config_mf_bw(bp
);
3083 bnx2x_fw_command(bp
, DRV_MSG_CODE_SET_MF_BW_ACK
, 0);
3086 static void bnx2x_handle_drv_info_req(struct bnx2x
*bp
)
3088 enum drv_info_opcode op_code
;
3089 u32 drv_info_ctl
= SHMEM2_RD(bp
, drv_info_control
);
3091 /* if drv_info version supported by MFW doesn't match - send NACK */
3092 if ((drv_info_ctl
& DRV_INFO_CONTROL_VER_MASK
) != DRV_INFO_CUR_VER
) {
3093 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3097 op_code
= (drv_info_ctl
& DRV_INFO_CONTROL_OP_CODE_MASK
) >>
3098 DRV_INFO_CONTROL_OP_CODE_SHIFT
;
3100 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3101 sizeof(union drv_info_to_mcp
));
3104 case ETH_STATS_OPCODE
:
3105 bnx2x_drv_info_ether_stat(bp
);
3107 case FCOE_STATS_OPCODE
:
3108 bnx2x_drv_info_fcoe_stat(bp
);
3110 case ISCSI_STATS_OPCODE
:
3111 bnx2x_drv_info_iscsi_stat(bp
);
3114 /* if op code isn't supported - send NACK */
3115 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3119 /* if we got drv_info attn from MFW then these fields are defined in
3122 SHMEM2_WR(bp
, drv_info_host_addr_lo
,
3123 U64_LO(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3124 SHMEM2_WR(bp
, drv_info_host_addr_hi
,
3125 U64_HI(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3127 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_ACK
, 0);
3130 static void bnx2x_dcc_event(struct bnx2x
*bp
, u32 dcc_event
)
3132 DP(BNX2X_MSG_MCP
, "dcc_event 0x%x\n", dcc_event
);
3134 if (dcc_event
& DRV_STATUS_DCC_DISABLE_ENABLE_PF
) {
3137 * This is the only place besides the function initialization
3138 * where the bp->flags can change so it is done without any
3141 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
3142 DP(NETIF_MSG_IFDOWN
, "mf_cfg function disabled\n");
3143 bp
->flags
|= MF_FUNC_DIS
;
3145 bnx2x_e1h_disable(bp
);
3147 DP(NETIF_MSG_IFUP
, "mf_cfg function enabled\n");
3148 bp
->flags
&= ~MF_FUNC_DIS
;
3150 bnx2x_e1h_enable(bp
);
3152 dcc_event
&= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF
;
3154 if (dcc_event
& DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
) {
3155 bnx2x_config_mf_bw(bp
);
3156 dcc_event
&= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
;
3159 /* Report results to MCP */
3161 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_FAILURE
, 0);
3163 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_OK
, 0);
3166 /* must be called under the spq lock */
3167 static inline struct eth_spe
*bnx2x_sp_get_next(struct bnx2x
*bp
)
3169 struct eth_spe
*next_spe
= bp
->spq_prod_bd
;
3171 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
3172 bp
->spq_prod_bd
= bp
->spq
;
3173 bp
->spq_prod_idx
= 0;
3174 DP(NETIF_MSG_TIMER
, "end of spq\n");
3182 /* must be called under the spq lock */
3183 static inline void bnx2x_sp_prod_update(struct bnx2x
*bp
)
3185 int func
= BP_FUNC(bp
);
3188 * Make sure that BD data is updated before writing the producer:
3189 * BD data is written to the memory, the producer is read from the
3190 * memory, thus we need a full memory barrier to ensure the ordering.
3194 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
3200 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3202 * @cmd: command to check
3203 * @cmd_type: command type
3205 static inline bool bnx2x_is_contextless_ramrod(int cmd
, int cmd_type
)
3207 if ((cmd_type
== NONE_CONNECTION_TYPE
) ||
3208 (cmd
== RAMROD_CMD_ID_ETH_FORWARD_SETUP
) ||
3209 (cmd
== RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
) ||
3210 (cmd
== RAMROD_CMD_ID_ETH_FILTER_RULES
) ||
3211 (cmd
== RAMROD_CMD_ID_ETH_MULTICAST_RULES
) ||
3212 (cmd
== RAMROD_CMD_ID_ETH_SET_MAC
) ||
3213 (cmd
== RAMROD_CMD_ID_ETH_RSS_UPDATE
))
3222 * bnx2x_sp_post - place a single command on an SP ring
3224 * @bp: driver handle
3225 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3226 * @cid: SW CID the command is related to
3227 * @data_hi: command private data address (high 32 bits)
3228 * @data_lo: command private data address (low 32 bits)
3229 * @cmd_type: command type (e.g. NONE, ETH)
3231 * SP data is handled as if it's always an address pair, thus data fields are
3232 * not swapped to little endian in upper functions. Instead this function swaps
3233 * data as if it's two u32 fields.
3235 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
3236 u32 data_hi
, u32 data_lo
, int cmd_type
)
3238 struct eth_spe
*spe
;
3240 bool common
= bnx2x_is_contextless_ramrod(command
, cmd_type
);
3242 #ifdef BNX2X_STOP_ON_ERROR
3243 if (unlikely(bp
->panic
))
3247 spin_lock_bh(&bp
->spq_lock
);
3250 if (!atomic_read(&bp
->eq_spq_left
)) {
3251 BNX2X_ERR("BUG! EQ ring full!\n");
3252 spin_unlock_bh(&bp
->spq_lock
);
3256 } else if (!atomic_read(&bp
->cq_spq_left
)) {
3257 BNX2X_ERR("BUG! SPQ ring full!\n");
3258 spin_unlock_bh(&bp
->spq_lock
);
3263 spe
= bnx2x_sp_get_next(bp
);
3265 /* CID needs port number to be encoded int it */
3266 spe
->hdr
.conn_and_cmd_data
=
3267 cpu_to_le32((command
<< SPE_HDR_CMD_ID_SHIFT
) |
3270 type
= (cmd_type
<< SPE_HDR_CONN_TYPE_SHIFT
) & SPE_HDR_CONN_TYPE
;
3272 type
|= ((BP_FUNC(bp
) << SPE_HDR_FUNCTION_ID_SHIFT
) &
3273 SPE_HDR_FUNCTION_ID
);
3275 spe
->hdr
.type
= cpu_to_le16(type
);
3277 spe
->data
.update_data_addr
.hi
= cpu_to_le32(data_hi
);
3278 spe
->data
.update_data_addr
.lo
= cpu_to_le32(data_lo
);
3281 * It's ok if the actual decrement is issued towards the memory
3282 * somewhere between the spin_lock and spin_unlock. Thus no
3283 * more explict memory barrier is needed.
3286 atomic_dec(&bp
->eq_spq_left
);
3288 atomic_dec(&bp
->cq_spq_left
);
3291 DP(BNX2X_MSG_SP
/*NETIF_MSG_TIMER*/,
3292 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3293 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3294 bp
->spq_prod_idx
, (u32
)U64_HI(bp
->spq_mapping
),
3295 (u32
)(U64_LO(bp
->spq_mapping
) +
3296 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
, common
,
3297 HW_CID(bp
, cid
), data_hi
, data_lo
, type
,
3298 atomic_read(&bp
->cq_spq_left
), atomic_read(&bp
->eq_spq_left
));
3300 bnx2x_sp_prod_update(bp
);
3301 spin_unlock_bh(&bp
->spq_lock
);
3305 /* acquire split MCP access lock register */
3306 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
3312 for (j
= 0; j
< 1000; j
++) {
3314 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, val
);
3315 val
= REG_RD(bp
, GRCBASE_MCP
+ 0x9c);
3316 if (val
& (1L << 31))
3321 if (!(val
& (1L << 31))) {
3322 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3329 /* release split MCP access lock register */
3330 static void bnx2x_release_alr(struct bnx2x
*bp
)
3332 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, 0);
3335 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3336 #define BNX2X_DEF_SB_IDX 0x0002
3338 static inline u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
3340 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
3343 barrier(); /* status block is written to by the chip */
3344 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
3345 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
3346 rc
|= BNX2X_DEF_SB_ATT_IDX
;
3349 if (bp
->def_idx
!= def_sb
->sp_sb
.running_index
) {
3350 bp
->def_idx
= def_sb
->sp_sb
.running_index
;
3351 rc
|= BNX2X_DEF_SB_IDX
;
3354 /* Do not reorder: indecies reading should complete before handling */
3360 * slow path service functions
3363 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
3365 int port
= BP_PORT(bp
);
3366 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
3367 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
3368 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
3369 NIG_REG_MASK_INTERRUPT_PORT0
;
3374 if (bp
->attn_state
& asserted
)
3375 BNX2X_ERR("IGU ERROR\n");
3377 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3378 aeu_mask
= REG_RD(bp
, aeu_addr
);
3380 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
3381 aeu_mask
, asserted
);
3382 aeu_mask
&= ~(asserted
& 0x3ff);
3383 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
3385 REG_WR(bp
, aeu_addr
, aeu_mask
);
3386 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3388 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
3389 bp
->attn_state
|= asserted
;
3390 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
3392 if (asserted
& ATTN_HARD_WIRED_MASK
) {
3393 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3395 bnx2x_acquire_phy_lock(bp
);
3397 /* save nig interrupt mask */
3398 nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
3400 /* If nig_mask is not set, no need to call the update
3404 REG_WR(bp
, nig_int_mask_addr
, 0);
3406 bnx2x_link_attn(bp
);
3409 /* handle unicore attn? */
3411 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
3412 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
3414 if (asserted
& GPIO_2_FUNC
)
3415 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
3417 if (asserted
& GPIO_3_FUNC
)
3418 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
3420 if (asserted
& GPIO_4_FUNC
)
3421 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
3424 if (asserted
& ATTN_GENERAL_ATTN_1
) {
3425 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
3426 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
3428 if (asserted
& ATTN_GENERAL_ATTN_2
) {
3429 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
3430 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
3432 if (asserted
& ATTN_GENERAL_ATTN_3
) {
3433 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
3434 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
3437 if (asserted
& ATTN_GENERAL_ATTN_4
) {
3438 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
3439 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
3441 if (asserted
& ATTN_GENERAL_ATTN_5
) {
3442 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
3443 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
3445 if (asserted
& ATTN_GENERAL_ATTN_6
) {
3446 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
3447 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
3451 } /* if hardwired */
3453 if (bp
->common
.int_block
== INT_BLOCK_HC
)
3454 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
3455 COMMAND_REG_ATTN_BITS_SET
);
3457 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_SET_UPPER
*8);
3459 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", asserted
,
3460 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
3461 REG_WR(bp
, reg_addr
, asserted
);
3463 /* now set back the mask */
3464 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3465 REG_WR(bp
, nig_int_mask_addr
, nig_mask
);
3466 bnx2x_release_phy_lock(bp
);
3470 static inline void bnx2x_fan_failure(struct bnx2x
*bp
)
3472 int port
= BP_PORT(bp
);
3474 /* mark the failure */
3477 dev_info
.port_hw_config
[port
].external_phy_config
);
3479 ext_phy_config
&= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
3480 ext_phy_config
|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
3481 SHMEM_WR(bp
, dev_info
.port_hw_config
[port
].external_phy_config
,
3484 /* log the failure */
3485 netdev_err(bp
->dev
, "Fan Failure on Network Controller has caused"
3486 " the driver to shutdown the card to prevent permanent"
3487 " damage. Please contact OEM Support for assistance\n");
3490 * Scheudle device reset (unload)
3491 * This is due to some boards consuming sufficient power when driver is
3492 * up to overheat if fan fails.
3494 smp_mb__before_clear_bit();
3495 set_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
);
3496 smp_mb__after_clear_bit();
3497 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
3501 static inline void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
3503 int port
= BP_PORT(bp
);
3507 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
3508 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
3510 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
3512 val
= REG_RD(bp
, reg_offset
);
3513 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
3514 REG_WR(bp
, reg_offset
, val
);
3516 BNX2X_ERR("SPIO5 hw attention\n");
3518 /* Fan failure attention */
3519 bnx2x_hw_reset_phy(&bp
->link_params
);
3520 bnx2x_fan_failure(bp
);
3523 if ((attn
& bp
->link_vars
.aeu_int_mask
) && bp
->port
.pmf
) {
3524 bnx2x_acquire_phy_lock(bp
);
3525 bnx2x_handle_module_detect_int(&bp
->link_params
);
3526 bnx2x_release_phy_lock(bp
);
3529 if (attn
& HW_INTERRUT_ASSERT_SET_0
) {
3531 val
= REG_RD(bp
, reg_offset
);
3532 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_0
);
3533 REG_WR(bp
, reg_offset
, val
);
3535 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3536 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_0
));
3541 static inline void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
3545 if (attn
& AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
) {
3547 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
3548 BNX2X_ERR("DB hw attention 0x%x\n", val
);
3549 /* DORQ discard attention */
3551 BNX2X_ERR("FATAL error from DORQ\n");
3554 if (attn
& HW_INTERRUT_ASSERT_SET_1
) {
3556 int port
= BP_PORT(bp
);
3559 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
3560 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
3562 val
= REG_RD(bp
, reg_offset
);
3563 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_1
);
3564 REG_WR(bp
, reg_offset
, val
);
3566 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3567 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_1
));
3572 static inline void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
3576 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
3578 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
3579 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
3580 /* CFC error attention */
3582 BNX2X_ERR("FATAL error from CFC\n");
3585 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
3586 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
3587 BNX2X_ERR("PXP hw attention-0 0x%x\n", val
);
3588 /* RQ_USDMDP_FIFO_OVERFLOW */
3590 BNX2X_ERR("FATAL error from PXP\n");
3592 if (!CHIP_IS_E1x(bp
)) {
3593 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_1
);
3594 BNX2X_ERR("PXP hw attention-1 0x%x\n", val
);
3598 if (attn
& HW_INTERRUT_ASSERT_SET_2
) {
3600 int port
= BP_PORT(bp
);
3603 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
3604 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
3606 val
= REG_RD(bp
, reg_offset
);
3607 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_2
);
3608 REG_WR(bp
, reg_offset
, val
);
3610 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3611 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_2
));
3616 static inline void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
3620 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
3622 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
3623 int func
= BP_FUNC(bp
);
3625 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
3626 bp
->mf_config
[BP_VN(bp
)] = MF_CFG_RD(bp
,
3627 func_mf_config
[BP_ABS_FUNC(bp
)].config
);
3629 func_mb
[BP_FW_MB_IDX(bp
)].drv_status
);
3630 if (val
& DRV_STATUS_DCC_EVENT_MASK
)
3632 (val
& DRV_STATUS_DCC_EVENT_MASK
));
3634 if (val
& DRV_STATUS_SET_MF_BW
)
3635 bnx2x_set_mf_bw(bp
);
3637 if (val
& DRV_STATUS_DRV_INFO_REQ
)
3638 bnx2x_handle_drv_info_req(bp
);
3639 if ((bp
->port
.pmf
== 0) && (val
& DRV_STATUS_PMF
))
3640 bnx2x_pmf_update(bp
);
3643 (val
& DRV_STATUS_DCBX_NEGOTIATION_RESULTS
) &&
3644 bp
->dcbx_enabled
> 0)
3645 /* start dcbx state machine */
3646 bnx2x_dcbx_set_params(bp
,
3647 BNX2X_DCBX_STATE_NEG_RECEIVED
);
3648 if (bp
->link_vars
.periodic_flags
&
3649 PERIODIC_FLAGS_LINK_EVENT
) {
3650 /* sync with link */
3651 bnx2x_acquire_phy_lock(bp
);
3652 bp
->link_vars
.periodic_flags
&=
3653 ~PERIODIC_FLAGS_LINK_EVENT
;
3654 bnx2x_release_phy_lock(bp
);
3656 bnx2x_link_sync_notify(bp
);
3657 bnx2x_link_report(bp
);
3659 /* Always call it here: bnx2x_link_report() will
3660 * prevent the link indication duplication.
3662 bnx2x__link_status_update(bp
);
3663 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
3665 BNX2X_ERR("MC assert!\n");
3666 bnx2x_mc_assert(bp
);
3667 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
3668 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
3669 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
3670 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
3673 } else if (attn
& BNX2X_MCP_ASSERT
) {
3675 BNX2X_ERR("MCP assert!\n");
3676 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
3680 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
3683 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
3684 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
3685 if (attn
& BNX2X_GRC_TIMEOUT
) {
3686 val
= CHIP_IS_E1(bp
) ? 0 :
3687 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
);
3688 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
3690 if (attn
& BNX2X_GRC_RSV
) {
3691 val
= CHIP_IS_E1(bp
) ? 0 :
3692 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
);
3693 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
3695 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
3701 * 0-7 - Engine0 load counter.
3702 * 8-15 - Engine1 load counter.
3703 * 16 - Engine0 RESET_IN_PROGRESS bit.
3704 * 17 - Engine1 RESET_IN_PROGRESS bit.
3705 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3707 * 19 - Engine1 ONE_IS_LOADED.
3708 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3709 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3710 * just the one belonging to its engine).
3713 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3715 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3716 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3717 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3718 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3719 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3720 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3721 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3724 * Set the GLOBAL_RESET bit.
3726 * Should be run under rtnl lock
3728 void bnx2x_set_reset_global(struct bnx2x
*bp
)
3731 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3732 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3733 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
| BNX2X_GLOBAL_RESET_BIT
);
3734 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3738 * Clear the GLOBAL_RESET bit.
3740 * Should be run under rtnl lock
3742 static inline void bnx2x_clear_reset_global(struct bnx2x
*bp
)
3745 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3746 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3747 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~BNX2X_GLOBAL_RESET_BIT
));
3748 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3752 * Checks the GLOBAL_RESET bit.
3754 * should be run under rtnl lock
3756 static inline bool bnx2x_reset_is_global(struct bnx2x
*bp
)
3758 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3760 DP(NETIF_MSG_HW
, "GEN_REG_VAL=0x%08x\n", val
);
3761 return (val
& BNX2X_GLOBAL_RESET_BIT
) ? true : false;
3765 * Clear RESET_IN_PROGRESS bit for the current engine.
3767 * Should be run under rtnl lock
3769 static inline void bnx2x_set_reset_done(struct bnx2x
*bp
)
3772 u32 bit
= BP_PATH(bp
) ?
3773 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3774 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3775 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3779 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3781 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3785 * Set RESET_IN_PROGRESS for the current engine.
3787 * should be run under rtnl lock
3789 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
)
3792 u32 bit
= BP_PATH(bp
) ?
3793 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3794 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3795 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3799 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3800 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3804 * Checks the RESET_IN_PROGRESS bit for the given engine.
3805 * should be run under rtnl lock
3807 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
)
3809 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3811 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3813 /* return false if bit is set */
3814 return (val
& bit
) ? false : true;
3818 * set pf load for the current pf.
3820 * should be run under rtnl lock
3822 void bnx2x_set_pf_load(struct bnx2x
*bp
)
3825 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3826 BNX2X_PATH0_LOAD_CNT_MASK
;
3827 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3828 BNX2X_PATH0_LOAD_CNT_SHIFT
;
3830 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3831 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3833 DP(NETIF_MSG_HW
, "Old GEN_REG_VAL=0x%08x\n", val
);
3835 /* get the current counter value */
3836 val1
= (val
& mask
) >> shift
;
3838 /* set bit of that PF */
3839 val1
|= (1 << bp
->pf_num
);
3841 /* clear the old value */
3844 /* set the new one */
3845 val
|= ((val1
<< shift
) & mask
);
3847 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3848 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3852 * bnx2x_clear_pf_load - clear pf load mark
3854 * @bp: driver handle
3856 * Should be run under rtnl lock.
3857 * Decrements the load counter for the current engine. Returns
3858 * whether other functions are still loaded
3860 bool bnx2x_clear_pf_load(struct bnx2x
*bp
)
3863 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3864 BNX2X_PATH0_LOAD_CNT_MASK
;
3865 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3866 BNX2X_PATH0_LOAD_CNT_SHIFT
;
3868 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3869 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3870 DP(NETIF_MSG_HW
, "Old GEN_REG_VAL=0x%08x\n", val
);
3872 /* get the current counter value */
3873 val1
= (val
& mask
) >> shift
;
3875 /* clear bit of that PF */
3876 val1
&= ~(1 << bp
->pf_num
);
3878 /* clear the old value */
3881 /* set the new one */
3882 val
|= ((val1
<< shift
) & mask
);
3884 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3885 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3890 * Read the load status for the current engine.
3892 * should be run under rtnl lock
3894 static inline bool bnx2x_get_load_status(struct bnx2x
*bp
, int engine
)
3896 u32 mask
= (engine
? BNX2X_PATH1_LOAD_CNT_MASK
:
3897 BNX2X_PATH0_LOAD_CNT_MASK
);
3898 u32 shift
= (engine
? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3899 BNX2X_PATH0_LOAD_CNT_SHIFT
);
3900 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3902 DP(NETIF_MSG_HW
, "GLOB_REG=0x%08x\n", val
);
3904 val
= (val
& mask
) >> shift
;
3906 DP(NETIF_MSG_HW
, "load mask for engine %d = 0x%x\n", engine
, val
);
3912 * Reset the load status for the current engine.
3914 static inline void bnx2x_clear_load_status(struct bnx2x
*bp
)
3917 u32 mask
= (BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3918 BNX2X_PATH0_LOAD_CNT_MASK
);
3919 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3920 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3921 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~mask
));
3922 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3925 static inline void _print_next_block(int idx
, const char *blk
)
3927 pr_cont("%s%s", idx
? ", " : "", blk
);
3930 static inline int bnx2x_check_blocks_with_parity0(u32 sig
, int par_num
,
3935 for (i
= 0; sig
; i
++) {
3936 cur_bit
= ((u32
)0x1 << i
);
3937 if (sig
& cur_bit
) {
3939 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
:
3941 _print_next_block(par_num
++, "BRB");
3943 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
:
3945 _print_next_block(par_num
++, "PARSER");
3947 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
:
3949 _print_next_block(par_num
++, "TSDM");
3951 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
:
3953 _print_next_block(par_num
++,
3956 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
:
3958 _print_next_block(par_num
++, "TCM");
3960 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
:
3962 _print_next_block(par_num
++, "TSEMI");
3964 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
:
3966 _print_next_block(par_num
++, "XPB");
3978 static inline int bnx2x_check_blocks_with_parity1(u32 sig
, int par_num
,
3979 bool *global
, bool print
)
3983 for (i
= 0; sig
; i
++) {
3984 cur_bit
= ((u32
)0x1 << i
);
3985 if (sig
& cur_bit
) {
3987 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
:
3989 _print_next_block(par_num
++, "PBF");
3991 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
:
3993 _print_next_block(par_num
++, "QM");
3995 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
:
3997 _print_next_block(par_num
++, "TM");
3999 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
:
4001 _print_next_block(par_num
++, "XSDM");
4003 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
:
4005 _print_next_block(par_num
++, "XCM");
4007 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
:
4009 _print_next_block(par_num
++, "XSEMI");
4011 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
:
4013 _print_next_block(par_num
++,
4016 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
:
4018 _print_next_block(par_num
++, "NIG");
4020 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
:
4022 _print_next_block(par_num
++,
4026 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
:
4028 _print_next_block(par_num
++, "DEBUG");
4030 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
:
4032 _print_next_block(par_num
++, "USDM");
4034 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
:
4036 _print_next_block(par_num
++, "UCM");
4038 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
:
4040 _print_next_block(par_num
++, "USEMI");
4042 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
:
4044 _print_next_block(par_num
++, "UPB");
4046 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
:
4048 _print_next_block(par_num
++, "CSDM");
4050 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
:
4052 _print_next_block(par_num
++, "CCM");
4064 static inline int bnx2x_check_blocks_with_parity2(u32 sig
, int par_num
,
4069 for (i
= 0; sig
; i
++) {
4070 cur_bit
= ((u32
)0x1 << i
);
4071 if (sig
& cur_bit
) {
4073 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
:
4075 _print_next_block(par_num
++, "CSEMI");
4077 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
:
4079 _print_next_block(par_num
++, "PXP");
4081 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
:
4083 _print_next_block(par_num
++,
4084 "PXPPCICLOCKCLIENT");
4086 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
:
4088 _print_next_block(par_num
++, "CFC");
4090 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
:
4092 _print_next_block(par_num
++, "CDU");
4094 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
:
4096 _print_next_block(par_num
++, "DMAE");
4098 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
:
4100 _print_next_block(par_num
++, "IGU");
4102 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
:
4104 _print_next_block(par_num
++, "MISC");
4116 static inline int bnx2x_check_blocks_with_parity3(u32 sig
, int par_num
,
4117 bool *global
, bool print
)
4121 for (i
= 0; sig
; i
++) {
4122 cur_bit
= ((u32
)0x1 << i
);
4123 if (sig
& cur_bit
) {
4125 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
:
4127 _print_next_block(par_num
++, "MCP ROM");
4130 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
:
4132 _print_next_block(par_num
++,
4136 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
:
4138 _print_next_block(par_num
++,
4142 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
:
4144 _print_next_block(par_num
++,
4158 static inline int bnx2x_check_blocks_with_parity4(u32 sig
, int par_num
,
4163 for (i
= 0; sig
; i
++) {
4164 cur_bit
= ((u32
)0x1 << i
);
4165 if (sig
& cur_bit
) {
4167 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
:
4169 _print_next_block(par_num
++, "PGLUE_B");
4171 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
:
4173 _print_next_block(par_num
++, "ATC");
4185 static inline bool bnx2x_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
,
4188 if ((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4189 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4190 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4191 (sig
[3] & HW_PRTY_ASSERT_SET_3
) ||
4192 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) {
4194 DP(NETIF_MSG_HW
, "Was parity error: HW block parity attention: "
4195 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4197 sig
[0] & HW_PRTY_ASSERT_SET_0
,
4198 sig
[1] & HW_PRTY_ASSERT_SET_1
,
4199 sig
[2] & HW_PRTY_ASSERT_SET_2
,
4200 sig
[3] & HW_PRTY_ASSERT_SET_3
,
4201 sig
[4] & HW_PRTY_ASSERT_SET_4
);
4204 "Parity errors detected in blocks: ");
4205 par_num
= bnx2x_check_blocks_with_parity0(
4206 sig
[0] & HW_PRTY_ASSERT_SET_0
, par_num
, print
);
4207 par_num
= bnx2x_check_blocks_with_parity1(
4208 sig
[1] & HW_PRTY_ASSERT_SET_1
, par_num
, global
, print
);
4209 par_num
= bnx2x_check_blocks_with_parity2(
4210 sig
[2] & HW_PRTY_ASSERT_SET_2
, par_num
, print
);
4211 par_num
= bnx2x_check_blocks_with_parity3(
4212 sig
[3] & HW_PRTY_ASSERT_SET_3
, par_num
, global
, print
);
4213 par_num
= bnx2x_check_blocks_with_parity4(
4214 sig
[4] & HW_PRTY_ASSERT_SET_4
, par_num
, print
);
4225 * bnx2x_chk_parity_attn - checks for parity attentions.
4227 * @bp: driver handle
4228 * @global: true if there was a global attention
4229 * @print: show parity attention in syslog
4231 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
)
4233 struct attn_route attn
= { {0} };
4234 int port
= BP_PORT(bp
);
4236 attn
.sig
[0] = REG_RD(bp
,
4237 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+
4239 attn
.sig
[1] = REG_RD(bp
,
4240 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+
4242 attn
.sig
[2] = REG_RD(bp
,
4243 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+
4245 attn
.sig
[3] = REG_RD(bp
,
4246 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+
4249 if (!CHIP_IS_E1x(bp
))
4250 attn
.sig
[4] = REG_RD(bp
,
4251 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+
4254 return bnx2x_parity_attn(bp
, global
, print
, attn
.sig
);
4258 static inline void bnx2x_attn_int_deasserted4(struct bnx2x
*bp
, u32 attn
)
4261 if (attn
& AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
) {
4263 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS_CLR
);
4264 BNX2X_ERR("PGLUE hw attention 0x%x\n", val
);
4265 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
)
4266 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4268 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
)
4269 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4270 "INCORRECT_RCV_BEHAVIOR\n");
4271 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
)
4272 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4273 "WAS_ERROR_ATTN\n");
4274 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
)
4275 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4276 "VF_LENGTH_VIOLATION_ATTN\n");
4278 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
)
4279 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4280 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4282 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
)
4283 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4284 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4285 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
)
4286 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4287 "TCPL_ERROR_ATTN\n");
4288 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
)
4289 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4290 "TCPL_IN_TWO_RCBS_ATTN\n");
4291 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
)
4292 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4293 "CSSNOOP_FIFO_OVERFLOW\n");
4295 if (attn
& AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
) {
4296 val
= REG_RD(bp
, ATC_REG_ATC_INT_STS_CLR
);
4297 BNX2X_ERR("ATC hw attention 0x%x\n", val
);
4298 if (val
& ATC_ATC_INT_STS_REG_ADDRESS_ERROR
)
4299 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4300 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
)
4301 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4302 "_ATC_TCPL_TO_NOT_PEND\n");
4303 if (val
& ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
)
4304 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4305 "ATC_GPA_MULTIPLE_HITS\n");
4306 if (val
& ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
)
4307 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4308 "ATC_RCPL_TO_EMPTY_CNT\n");
4309 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
)
4310 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4311 if (val
& ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
)
4312 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4313 "ATC_IREQ_LESS_THAN_STU\n");
4316 if (attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4317 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)) {
4318 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4319 (u32
)(attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4320 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)));
4325 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
4327 struct attn_route attn
, *group_mask
;
4328 int port
= BP_PORT(bp
);
4333 bool global
= false;
4335 /* need to take HW lock because MCP or other port might also
4336 try to handle this event */
4337 bnx2x_acquire_alr(bp
);
4339 if (bnx2x_chk_parity_attn(bp
, &global
, true)) {
4340 #ifndef BNX2X_STOP_ON_ERROR
4341 bp
->recovery_state
= BNX2X_RECOVERY_INIT
;
4342 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
4343 /* Disable HW interrupts */
4344 bnx2x_int_disable(bp
);
4345 /* In case of parity errors don't handle attentions so that
4346 * other function would "see" parity errors.
4351 bnx2x_release_alr(bp
);
4355 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
4356 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
4357 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
4358 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
4359 if (!CHIP_IS_E1x(bp
))
4361 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+ port
*4);
4365 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x %08x\n",
4366 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3], attn
.sig
[4]);
4368 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
4369 if (deasserted
& (1 << index
)) {
4370 group_mask
= &bp
->attn_group
[index
];
4372 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x "
4375 group_mask
->sig
[0], group_mask
->sig
[1],
4376 group_mask
->sig
[2], group_mask
->sig
[3],
4377 group_mask
->sig
[4]);
4379 bnx2x_attn_int_deasserted4(bp
,
4380 attn
.sig
[4] & group_mask
->sig
[4]);
4381 bnx2x_attn_int_deasserted3(bp
,
4382 attn
.sig
[3] & group_mask
->sig
[3]);
4383 bnx2x_attn_int_deasserted1(bp
,
4384 attn
.sig
[1] & group_mask
->sig
[1]);
4385 bnx2x_attn_int_deasserted2(bp
,
4386 attn
.sig
[2] & group_mask
->sig
[2]);
4387 bnx2x_attn_int_deasserted0(bp
,
4388 attn
.sig
[0] & group_mask
->sig
[0]);
4392 bnx2x_release_alr(bp
);
4394 if (bp
->common
.int_block
== INT_BLOCK_HC
)
4395 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
4396 COMMAND_REG_ATTN_BITS_CLR
);
4398 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_CLR_UPPER
*8);
4401 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", val
,
4402 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
4403 REG_WR(bp
, reg_addr
, val
);
4405 if (~bp
->attn_state
& deasserted
)
4406 BNX2X_ERR("IGU ERROR\n");
4408 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
4409 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
4411 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4412 aeu_mask
= REG_RD(bp
, reg_addr
);
4414 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
4415 aeu_mask
, deasserted
);
4416 aeu_mask
|= (deasserted
& 0x3ff);
4417 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
4419 REG_WR(bp
, reg_addr
, aeu_mask
);
4420 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4422 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
4423 bp
->attn_state
&= ~deasserted
;
4424 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
4427 static void bnx2x_attn_int(struct bnx2x
*bp
)
4429 /* read local copy of bits */
4430 u32 attn_bits
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4432 u32 attn_ack
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4434 u32 attn_state
= bp
->attn_state
;
4436 /* look for changed bits */
4437 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
4438 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
4441 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4442 attn_bits
, attn_ack
, asserted
, deasserted
);
4444 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
4445 BNX2X_ERR("BAD attention state\n");
4447 /* handle bits that were raised */
4449 bnx2x_attn_int_asserted(bp
, asserted
);
4452 bnx2x_attn_int_deasserted(bp
, deasserted
);
4455 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
4456 u16 index
, u8 op
, u8 update
)
4458 u32 igu_addr
= BAR_IGU_INTMEM
+ (IGU_CMD_INT_ACK_BASE
+ igu_sb_id
)*8;
4460 bnx2x_igu_ack_sb_gen(bp
, igu_sb_id
, segment
, index
, op
, update
,
4464 static inline void bnx2x_update_eq_prod(struct bnx2x
*bp
, u16 prod
)
4466 /* No memory barriers */
4467 storm_memset_eq_prod(bp
, prod
, BP_FUNC(bp
));
4468 mmiowb(); /* keep prod updates ordered */
4472 static int bnx2x_cnic_handle_cfc_del(struct bnx2x
*bp
, u32 cid
,
4473 union event_ring_elem
*elem
)
4475 u8 err
= elem
->message
.error
;
4477 if (!bp
->cnic_eth_dev
.starting_cid
||
4478 (cid
< bp
->cnic_eth_dev
.starting_cid
&&
4479 cid
!= bp
->cnic_eth_dev
.iscsi_l2_cid
))
4482 DP(BNX2X_MSG_SP
, "got delete ramrod for CNIC CID %d\n", cid
);
4484 if (unlikely(err
)) {
4486 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4488 bnx2x_panic_dump(bp
);
4490 bnx2x_cnic_cfc_comp(bp
, cid
, err
);
4495 static inline void bnx2x_handle_mcast_eqe(struct bnx2x
*bp
)
4497 struct bnx2x_mcast_ramrod_params rparam
;
4500 memset(&rparam
, 0, sizeof(rparam
));
4502 rparam
.mcast_obj
= &bp
->mcast_obj
;
4504 netif_addr_lock_bh(bp
->dev
);
4506 /* Clear pending state for the last command */
4507 bp
->mcast_obj
.raw
.clear_pending(&bp
->mcast_obj
.raw
);
4509 /* If there are pending mcast commands - send them */
4510 if (bp
->mcast_obj
.check_pending(&bp
->mcast_obj
)) {
4511 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_CONT
);
4513 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4517 netif_addr_unlock_bh(bp
->dev
);
4520 static inline void bnx2x_handle_classification_eqe(struct bnx2x
*bp
,
4521 union event_ring_elem
*elem
)
4523 unsigned long ramrod_flags
= 0;
4525 u32 cid
= elem
->message
.data
.eth_event
.echo
& BNX2X_SWCID_MASK
;
4526 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
;
4528 /* Always push next commands out, don't wait here */
4529 __set_bit(RAMROD_CONT
, &ramrod_flags
);
4531 switch (elem
->message
.data
.eth_event
.echo
>> BNX2X_SWCID_SHIFT
) {
4532 case BNX2X_FILTER_MAC_PENDING
:
4534 if (cid
== BNX2X_ISCSI_ETH_CID
)
4535 vlan_mac_obj
= &bp
->iscsi_l2_mac_obj
;
4538 vlan_mac_obj
= &bp
->fp
[cid
].mac_obj
;
4541 case BNX2X_FILTER_MCAST_PENDING
:
4542 /* This is only relevant for 57710 where multicast MACs are
4543 * configured as unicast MACs using the same ramrod.
4545 bnx2x_handle_mcast_eqe(bp
);
4548 BNX2X_ERR("Unsupported classification command: %d\n",
4549 elem
->message
.data
.eth_event
.echo
);
4553 rc
= vlan_mac_obj
->complete(bp
, vlan_mac_obj
, elem
, &ramrod_flags
);
4556 BNX2X_ERR("Failed to schedule new commands: %d\n", rc
);
4558 DP(BNX2X_MSG_SP
, "Scheduled next pending commands...\n");
4563 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
);
4566 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x
*bp
)
4568 netif_addr_lock_bh(bp
->dev
);
4570 clear_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
4572 /* Send rx_mode command again if was requested */
4573 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
))
4574 bnx2x_set_storm_rx_mode(bp
);
4576 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
,
4578 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
4579 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
,
4581 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
4584 netif_addr_unlock_bh(bp
->dev
);
4587 static inline struct bnx2x_queue_sp_obj
*bnx2x_cid_to_q_obj(
4588 struct bnx2x
*bp
, u32 cid
)
4590 DP(BNX2X_MSG_SP
, "retrieving fp from cid %d\n", cid
);
4592 if (cid
== BNX2X_FCOE_ETH_CID
)
4593 return &bnx2x_fcoe(bp
, q_obj
);
4596 return &bnx2x_fp(bp
, CID_TO_FP(cid
), q_obj
);
4599 static void bnx2x_eq_int(struct bnx2x
*bp
)
4601 u16 hw_cons
, sw_cons
, sw_prod
;
4602 union event_ring_elem
*elem
;
4606 struct bnx2x_queue_sp_obj
*q_obj
;
4607 struct bnx2x_func_sp_obj
*f_obj
= &bp
->func_obj
;
4608 struct bnx2x_raw_obj
*rss_raw
= &bp
->rss_conf_obj
.raw
;
4610 hw_cons
= le16_to_cpu(*bp
->eq_cons_sb
);
4612 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4613 * when we get the the next-page we nned to adjust so the loop
4614 * condition below will be met. The next element is the size of a
4615 * regular element and hence incrementing by 1
4617 if ((hw_cons
& EQ_DESC_MAX_PAGE
) == EQ_DESC_MAX_PAGE
)
4620 /* This function may never run in parallel with itself for a
4621 * specific bp, thus there is no need in "paired" read memory
4624 sw_cons
= bp
->eq_cons
;
4625 sw_prod
= bp
->eq_prod
;
4627 DP(BNX2X_MSG_SP
, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4628 hw_cons
, sw_cons
, atomic_read(&bp
->eq_spq_left
));
4630 for (; sw_cons
!= hw_cons
;
4631 sw_prod
= NEXT_EQ_IDX(sw_prod
), sw_cons
= NEXT_EQ_IDX(sw_cons
)) {
4634 elem
= &bp
->eq_ring
[EQ_DESC(sw_cons
)];
4636 cid
= SW_CID(elem
->message
.data
.cfc_del_event
.cid
);
4637 opcode
= elem
->message
.opcode
;
4640 /* handle eq element */
4642 case EVENT_RING_OPCODE_STAT_QUERY
:
4643 DP(NETIF_MSG_TIMER
, "got statistics comp event %d\n",
4645 /* nothing to do with stats comp */
4648 case EVENT_RING_OPCODE_CFC_DEL
:
4649 /* handle according to cid range */
4651 * we may want to verify here that the bp state is
4655 "got delete ramrod for MULTI[%d]\n", cid
);
4657 if (!bnx2x_cnic_handle_cfc_del(bp
, cid
, elem
))
4660 q_obj
= bnx2x_cid_to_q_obj(bp
, cid
);
4662 if (q_obj
->complete_cmd(bp
, q_obj
, BNX2X_Q_CMD_CFC_DEL
))
4669 case EVENT_RING_OPCODE_STOP_TRAFFIC
:
4670 DP(BNX2X_MSG_SP
, "got STOP TRAFFIC\n");
4671 if (f_obj
->complete_cmd(bp
, f_obj
,
4672 BNX2X_F_CMD_TX_STOP
))
4674 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_PAUSED
);
4677 case EVENT_RING_OPCODE_START_TRAFFIC
:
4678 DP(BNX2X_MSG_SP
, "got START TRAFFIC\n");
4679 if (f_obj
->complete_cmd(bp
, f_obj
,
4680 BNX2X_F_CMD_TX_START
))
4682 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_RELEASED
);
4684 case EVENT_RING_OPCODE_FUNCTION_START
:
4685 DP(BNX2X_MSG_SP
, "got FUNC_START ramrod\n");
4686 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_START
))
4691 case EVENT_RING_OPCODE_FUNCTION_STOP
:
4692 DP(BNX2X_MSG_SP
, "got FUNC_STOP ramrod\n");
4693 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_STOP
))
4699 switch (opcode
| bp
->state
) {
4700 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
4702 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
4703 BNX2X_STATE_OPENING_WAIT4_PORT
):
4704 cid
= elem
->message
.data
.eth_event
.echo
&
4706 DP(BNX2X_MSG_SP
, "got RSS_UPDATE ramrod. CID %d\n",
4708 rss_raw
->clear_pending(rss_raw
);
4711 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_OPEN
):
4712 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_DIAG
):
4713 case (EVENT_RING_OPCODE_SET_MAC
|
4714 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4715 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4717 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4719 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4720 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4721 DP(BNX2X_MSG_SP
, "got (un)set mac ramrod\n");
4722 bnx2x_handle_classification_eqe(bp
, elem
);
4725 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4727 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4729 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4730 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4731 DP(BNX2X_MSG_SP
, "got mcast ramrod\n");
4732 bnx2x_handle_mcast_eqe(bp
);
4735 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4737 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4739 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4740 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4741 DP(BNX2X_MSG_SP
, "got rx_mode ramrod\n");
4742 bnx2x_handle_rx_mode_eqe(bp
);
4745 /* unknown event log error and continue */
4746 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4747 elem
->message
.opcode
, bp
->state
);
4753 smp_mb__before_atomic_inc();
4754 atomic_add(spqe_cnt
, &bp
->eq_spq_left
);
4756 bp
->eq_cons
= sw_cons
;
4757 bp
->eq_prod
= sw_prod
;
4758 /* Make sure that above mem writes were issued towards the memory */
4761 /* update producer */
4762 bnx2x_update_eq_prod(bp
, bp
->eq_prod
);
4765 static void bnx2x_sp_task(struct work_struct
*work
)
4767 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
4770 status
= bnx2x_update_dsb_idx(bp
);
4771 /* if (status == 0) */
4772 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4774 DP(NETIF_MSG_INTR
, "got a slowpath interrupt (status 0x%x)\n", status
);
4777 if (status
& BNX2X_DEF_SB_ATT_IDX
) {
4779 status
&= ~BNX2X_DEF_SB_ATT_IDX
;
4782 /* SP events: STAT_QUERY and others */
4783 if (status
& BNX2X_DEF_SB_IDX
) {
4785 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
4787 if ((!NO_FCOE(bp
)) &&
4788 (bnx2x_has_rx_work(fp
) || bnx2x_has_tx_work(fp
))) {
4790 * Prevent local bottom-halves from running as
4791 * we are going to change the local NAPI list.
4794 napi_schedule(&bnx2x_fcoe(bp
, napi
));
4798 /* Handle EQ completions */
4801 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
,
4802 le16_to_cpu(bp
->def_idx
), IGU_INT_NOP
, 1);
4804 status
&= ~BNX2X_DEF_SB_IDX
;
4807 if (unlikely(status
))
4808 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
4811 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, ATTENTION_ID
,
4812 le16_to_cpu(bp
->def_att_idx
), IGU_INT_ENABLE
, 1);
4815 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
4817 struct net_device
*dev
= dev_instance
;
4818 struct bnx2x
*bp
= netdev_priv(dev
);
4820 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0,
4821 IGU_INT_DISABLE
, 0);
4823 #ifdef BNX2X_STOP_ON_ERROR
4824 if (unlikely(bp
->panic
))
4830 struct cnic_ops
*c_ops
;
4833 c_ops
= rcu_dereference(bp
->cnic_ops
);
4835 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
4839 queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
4844 /* end of slow path */
4847 void bnx2x_drv_pulse(struct bnx2x
*bp
)
4849 SHMEM_WR(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_pulse_mb
,
4850 bp
->fw_drv_pulse_wr_seq
);
4854 static void bnx2x_timer(unsigned long data
)
4857 struct bnx2x
*bp
= (struct bnx2x
*) data
;
4859 if (!netif_running(bp
->dev
))
4863 struct bnx2x_fastpath
*fp
= &bp
->fp
[0];
4865 for_each_cos_in_tx_queue(fp
, cos
)
4866 bnx2x_tx_int(bp
, &fp
->txdata
[cos
]);
4867 bnx2x_rx_int(fp
, 1000);
4870 if (!BP_NOMCP(bp
)) {
4871 int mb_idx
= BP_FW_MB_IDX(bp
);
4875 ++bp
->fw_drv_pulse_wr_seq
;
4876 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
4877 /* TBD - add SYSTEM_TIME */
4878 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
4879 bnx2x_drv_pulse(bp
);
4881 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[mb_idx
].mcp_pulse_mb
) &
4882 MCP_PULSE_SEQ_MASK
);
4883 /* The delta between driver pulse and mcp response
4884 * should be 1 (before mcp response) or 0 (after mcp response)
4886 if ((drv_pulse
!= mcp_pulse
) &&
4887 (drv_pulse
!= ((mcp_pulse
+ 1) & MCP_PULSE_SEQ_MASK
))) {
4888 /* someone lost a heartbeat... */
4889 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4890 drv_pulse
, mcp_pulse
);
4894 if (bp
->state
== BNX2X_STATE_OPEN
)
4895 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
4897 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4900 /* end of Statistics */
4905 * nic init service functions
4908 static inline void bnx2x_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
4911 if (!(len
%4) && !(addr
%4))
4912 for (i
= 0; i
< len
; i
+= 4)
4913 REG_WR(bp
, addr
+ i
, fill
);
4915 for (i
= 0; i
< len
; i
++)
4916 REG_WR8(bp
, addr
+ i
, fill
);
4920 /* helper: writes FP SP data to FW - data_size in dwords */
4921 static inline void bnx2x_wr_fp_sb_data(struct bnx2x
*bp
,
4927 for (index
= 0; index
< data_size
; index
++)
4928 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4929 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id
) +
4931 *(sb_data_p
+ index
));
4934 static inline void bnx2x_zero_fp_sb(struct bnx2x
*bp
, int fw_sb_id
)
4938 struct hc_status_block_data_e2 sb_data_e2
;
4939 struct hc_status_block_data_e1x sb_data_e1x
;
4941 /* disable the function first */
4942 if (!CHIP_IS_E1x(bp
)) {
4943 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
4944 sb_data_e2
.common
.state
= SB_DISABLED
;
4945 sb_data_e2
.common
.p_func
.vf_valid
= false;
4946 sb_data_p
= (u32
*)&sb_data_e2
;
4947 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
4949 memset(&sb_data_e1x
, 0,
4950 sizeof(struct hc_status_block_data_e1x
));
4951 sb_data_e1x
.common
.state
= SB_DISABLED
;
4952 sb_data_e1x
.common
.p_func
.vf_valid
= false;
4953 sb_data_p
= (u32
*)&sb_data_e1x
;
4954 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
4956 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
4958 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4959 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id
), 0,
4960 CSTORM_STATUS_BLOCK_SIZE
);
4961 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4962 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id
), 0,
4963 CSTORM_SYNC_BLOCK_SIZE
);
4966 /* helper: writes SP SB data to FW */
4967 static inline void bnx2x_wr_sp_sb_data(struct bnx2x
*bp
,
4968 struct hc_sp_status_block_data
*sp_sb_data
)
4970 int func
= BP_FUNC(bp
);
4972 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
4973 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4974 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
4976 *((u32
*)sp_sb_data
+ i
));
4979 static inline void bnx2x_zero_sp_sb(struct bnx2x
*bp
)
4981 int func
= BP_FUNC(bp
);
4982 struct hc_sp_status_block_data sp_sb_data
;
4983 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
4985 sp_sb_data
.state
= SB_DISABLED
;
4986 sp_sb_data
.p_func
.vf_valid
= false;
4988 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
4990 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4991 CSTORM_SP_STATUS_BLOCK_OFFSET(func
), 0,
4992 CSTORM_SP_STATUS_BLOCK_SIZE
);
4993 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4994 CSTORM_SP_SYNC_BLOCK_OFFSET(func
), 0,
4995 CSTORM_SP_SYNC_BLOCK_SIZE
);
5001 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm
*hc_sm
,
5002 int igu_sb_id
, int igu_seg_id
)
5004 hc_sm
->igu_sb_id
= igu_sb_id
;
5005 hc_sm
->igu_seg_id
= igu_seg_id
;
5006 hc_sm
->timer_value
= 0xFF;
5007 hc_sm
->time_to_expire
= 0xFFFFFFFF;
5011 /* allocates state machine ids. */
5013 void bnx2x_map_sb_state_machines(struct hc_index_data
*index_data
)
5015 /* zero out state machine indices */
5017 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5020 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5021 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5022 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5023 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5027 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
|=
5028 SM_RX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5031 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
|=
5032 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5033 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
|=
5034 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5035 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
|=
5036 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5037 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
|=
5038 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5041 static void bnx2x_init_sb(struct bnx2x
*bp
, dma_addr_t mapping
, int vfid
,
5042 u8 vf_valid
, int fw_sb_id
, int igu_sb_id
)
5046 struct hc_status_block_data_e2 sb_data_e2
;
5047 struct hc_status_block_data_e1x sb_data_e1x
;
5048 struct hc_status_block_sm
*hc_sm_p
;
5052 if (CHIP_INT_MODE_IS_BC(bp
))
5053 igu_seg_id
= HC_SEG_ACCESS_NORM
;
5055 igu_seg_id
= IGU_SEG_ACCESS_NORM
;
5057 bnx2x_zero_fp_sb(bp
, fw_sb_id
);
5059 if (!CHIP_IS_E1x(bp
)) {
5060 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5061 sb_data_e2
.common
.state
= SB_ENABLED
;
5062 sb_data_e2
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5063 sb_data_e2
.common
.p_func
.vf_id
= vfid
;
5064 sb_data_e2
.common
.p_func
.vf_valid
= vf_valid
;
5065 sb_data_e2
.common
.p_func
.vnic_id
= BP_VN(bp
);
5066 sb_data_e2
.common
.same_igu_sb_1b
= true;
5067 sb_data_e2
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5068 sb_data_e2
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5069 hc_sm_p
= sb_data_e2
.common
.state_machine
;
5070 sb_data_p
= (u32
*)&sb_data_e2
;
5071 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5072 bnx2x_map_sb_state_machines(sb_data_e2
.index_data
);
5074 memset(&sb_data_e1x
, 0,
5075 sizeof(struct hc_status_block_data_e1x
));
5076 sb_data_e1x
.common
.state
= SB_ENABLED
;
5077 sb_data_e1x
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5078 sb_data_e1x
.common
.p_func
.vf_id
= 0xff;
5079 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5080 sb_data_e1x
.common
.p_func
.vnic_id
= BP_VN(bp
);
5081 sb_data_e1x
.common
.same_igu_sb_1b
= true;
5082 sb_data_e1x
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5083 sb_data_e1x
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5084 hc_sm_p
= sb_data_e1x
.common
.state_machine
;
5085 sb_data_p
= (u32
*)&sb_data_e1x
;
5086 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5087 bnx2x_map_sb_state_machines(sb_data_e1x
.index_data
);
5090 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_RX_ID
],
5091 igu_sb_id
, igu_seg_id
);
5092 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_TX_ID
],
5093 igu_sb_id
, igu_seg_id
);
5095 DP(NETIF_MSG_HW
, "Init FW SB %d\n", fw_sb_id
);
5097 /* write indecies to HW */
5098 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5101 static void bnx2x_update_coalesce_sb(struct bnx2x
*bp
, u8 fw_sb_id
,
5102 u16 tx_usec
, u16 rx_usec
)
5104 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
, HC_INDEX_ETH_RX_CQ_CONS
,
5106 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5107 HC_INDEX_ETH_TX_CQ_CONS_COS0
, false,
5109 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5110 HC_INDEX_ETH_TX_CQ_CONS_COS1
, false,
5112 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5113 HC_INDEX_ETH_TX_CQ_CONS_COS2
, false,
5117 static void bnx2x_init_def_sb(struct bnx2x
*bp
)
5119 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
5120 dma_addr_t mapping
= bp
->def_status_blk_mapping
;
5121 int igu_sp_sb_index
;
5123 int port
= BP_PORT(bp
);
5124 int func
= BP_FUNC(bp
);
5125 int reg_offset
, reg_offset_en5
;
5128 struct hc_sp_status_block_data sp_sb_data
;
5129 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5131 if (CHIP_INT_MODE_IS_BC(bp
)) {
5132 igu_sp_sb_index
= DEF_SB_IGU_ID
;
5133 igu_seg_id
= HC_SEG_ACCESS_DEF
;
5135 igu_sp_sb_index
= bp
->igu_dsb_id
;
5136 igu_seg_id
= IGU_SEG_ACCESS_DEF
;
5140 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
5141 atten_status_block
);
5142 def_sb
->atten_status_block
.status_block_id
= igu_sp_sb_index
;
5146 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
5147 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
5148 reg_offset_en5
= (port
? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
:
5149 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
);
5150 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
5152 /* take care of sig[0]..sig[4] */
5153 for (sindex
= 0; sindex
< 4; sindex
++)
5154 bp
->attn_group
[index
].sig
[sindex
] =
5155 REG_RD(bp
, reg_offset
+ sindex
*0x4 + 0x10*index
);
5157 if (!CHIP_IS_E1x(bp
))
5159 * enable5 is separate from the rest of the registers,
5160 * and therefore the address skip is 4
5161 * and not 16 between the different groups
5163 bp
->attn_group
[index
].sig
[4] = REG_RD(bp
,
5164 reg_offset_en5
+ 0x4*index
);
5166 bp
->attn_group
[index
].sig
[4] = 0;
5169 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
5170 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
5171 HC_REG_ATTN_MSG0_ADDR_L
);
5173 REG_WR(bp
, reg_offset
, U64_LO(section
));
5174 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
5175 } else if (!CHIP_IS_E1x(bp
)) {
5176 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_L
, U64_LO(section
));
5177 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_H
, U64_HI(section
));
5180 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
5183 bnx2x_zero_sp_sb(bp
);
5185 sp_sb_data
.state
= SB_ENABLED
;
5186 sp_sb_data
.host_sb_addr
.lo
= U64_LO(section
);
5187 sp_sb_data
.host_sb_addr
.hi
= U64_HI(section
);
5188 sp_sb_data
.igu_sb_id
= igu_sp_sb_index
;
5189 sp_sb_data
.igu_seg_id
= igu_seg_id
;
5190 sp_sb_data
.p_func
.pf_id
= func
;
5191 sp_sb_data
.p_func
.vnic_id
= BP_VN(bp
);
5192 sp_sb_data
.p_func
.vf_id
= 0xff;
5194 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5196 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0, IGU_INT_ENABLE
, 0);
5199 void bnx2x_update_coalesce(struct bnx2x
*bp
)
5203 for_each_eth_queue(bp
, i
)
5204 bnx2x_update_coalesce_sb(bp
, bp
->fp
[i
].fw_sb_id
,
5205 bp
->tx_ticks
, bp
->rx_ticks
);
5208 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
5210 spin_lock_init(&bp
->spq_lock
);
5211 atomic_set(&bp
->cq_spq_left
, MAX_SPQ_PENDING
);
5213 bp
->spq_prod_idx
= 0;
5214 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
5215 bp
->spq_prod_bd
= bp
->spq
;
5216 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
5219 static void bnx2x_init_eq_ring(struct bnx2x
*bp
)
5222 for (i
= 1; i
<= NUM_EQ_PAGES
; i
++) {
5223 union event_ring_elem
*elem
=
5224 &bp
->eq_ring
[EQ_DESC_CNT_PAGE
* i
- 1];
5226 elem
->next_page
.addr
.hi
=
5227 cpu_to_le32(U64_HI(bp
->eq_mapping
+
5228 BCM_PAGE_SIZE
* (i
% NUM_EQ_PAGES
)));
5229 elem
->next_page
.addr
.lo
=
5230 cpu_to_le32(U64_LO(bp
->eq_mapping
+
5231 BCM_PAGE_SIZE
*(i
% NUM_EQ_PAGES
)));
5234 bp
->eq_prod
= NUM_EQ_DESC
;
5235 bp
->eq_cons_sb
= BNX2X_EQ_INDEX
;
5236 /* we want a warning message before it gets rought... */
5237 atomic_set(&bp
->eq_spq_left
,
5238 min_t(int, MAX_SP_DESC_CNT
- MAX_SPQ_PENDING
, NUM_EQ_DESC
) - 1);
5242 /* called with netif_addr_lock_bh() */
5243 void bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
5244 unsigned long rx_mode_flags
,
5245 unsigned long rx_accept_flags
,
5246 unsigned long tx_accept_flags
,
5247 unsigned long ramrod_flags
)
5249 struct bnx2x_rx_mode_ramrod_params ramrod_param
;
5252 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
5254 /* Prepare ramrod parameters */
5255 ramrod_param
.cid
= 0;
5256 ramrod_param
.cl_id
= cl_id
;
5257 ramrod_param
.rx_mode_obj
= &bp
->rx_mode_obj
;
5258 ramrod_param
.func_id
= BP_FUNC(bp
);
5260 ramrod_param
.pstate
= &bp
->sp_state
;
5261 ramrod_param
.state
= BNX2X_FILTER_RX_MODE_PENDING
;
5263 ramrod_param
.rdata
= bnx2x_sp(bp
, rx_mode_rdata
);
5264 ramrod_param
.rdata_mapping
= bnx2x_sp_mapping(bp
, rx_mode_rdata
);
5266 set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
5268 ramrod_param
.ramrod_flags
= ramrod_flags
;
5269 ramrod_param
.rx_mode_flags
= rx_mode_flags
;
5271 ramrod_param
.rx_accept_flags
= rx_accept_flags
;
5272 ramrod_param
.tx_accept_flags
= tx_accept_flags
;
5274 rc
= bnx2x_config_rx_mode(bp
, &ramrod_param
);
5276 BNX2X_ERR("Set rx_mode %d failed\n", bp
->rx_mode
);
5281 /* called with netif_addr_lock_bh() */
5282 void bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
5284 unsigned long rx_mode_flags
= 0, ramrod_flags
= 0;
5285 unsigned long rx_accept_flags
= 0, tx_accept_flags
= 0;
5290 /* Configure rx_mode of FCoE Queue */
5291 __set_bit(BNX2X_RX_MODE_FCOE_ETH
, &rx_mode_flags
);
5294 switch (bp
->rx_mode
) {
5295 case BNX2X_RX_MODE_NONE
:
5297 * 'drop all' supersedes any accept flags that may have been
5298 * passed to the function.
5301 case BNX2X_RX_MODE_NORMAL
:
5302 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5303 __set_bit(BNX2X_ACCEPT_MULTICAST
, &rx_accept_flags
);
5304 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5306 /* internal switching mode */
5307 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5308 __set_bit(BNX2X_ACCEPT_MULTICAST
, &tx_accept_flags
);
5309 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5312 case BNX2X_RX_MODE_ALLMULTI
:
5313 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5314 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &rx_accept_flags
);
5315 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5317 /* internal switching mode */
5318 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5319 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &tx_accept_flags
);
5320 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5323 case BNX2X_RX_MODE_PROMISC
:
5324 /* According to deffinition of SI mode, iface in promisc mode
5325 * should receive matched and unmatched (in resolution of port)
5328 __set_bit(BNX2X_ACCEPT_UNMATCHED
, &rx_accept_flags
);
5329 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5330 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &rx_accept_flags
);
5331 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5333 /* internal switching mode */
5334 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &tx_accept_flags
);
5335 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5338 __set_bit(BNX2X_ACCEPT_ALL_UNICAST
, &tx_accept_flags
);
5340 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5344 BNX2X_ERR("Unknown rx_mode: %d\n", bp
->rx_mode
);
5348 if (bp
->rx_mode
!= BNX2X_RX_MODE_NONE
) {
5349 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &rx_accept_flags
);
5350 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &tx_accept_flags
);
5353 __set_bit(RAMROD_RX
, &ramrod_flags
);
5354 __set_bit(RAMROD_TX
, &ramrod_flags
);
5356 bnx2x_set_q_rx_mode(bp
, bp
->fp
->cl_id
, rx_mode_flags
, rx_accept_flags
,
5357 tx_accept_flags
, ramrod_flags
);
5360 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
5366 * In switch independent mode, the TSTORM needs to accept
5367 * packets that failed classification, since approximate match
5368 * mac addresses aren't written to NIG LLH
5370 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5371 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 2);
5372 else if (!CHIP_IS_E1(bp
)) /* 57710 doesn't support MF */
5373 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5374 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 0);
5376 /* Zero this manually as its initialization is
5377 currently missing in the initTool */
5378 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
5379 REG_WR(bp
, BAR_USTRORM_INTMEM
+
5380 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
5381 if (!CHIP_IS_E1x(bp
)) {
5382 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_IGU_MODE_OFFSET
,
5383 CHIP_INT_MODE_IS_BC(bp
) ?
5384 HC_IGU_BC_MODE
: HC_IGU_NBC_MODE
);
5388 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
5390 switch (load_code
) {
5391 case FW_MSG_CODE_DRV_LOAD_COMMON
:
5392 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
5393 bnx2x_init_internal_common(bp
);
5396 case FW_MSG_CODE_DRV_LOAD_PORT
:
5400 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
5401 /* internal memory per function is
5402 initialized inside bnx2x_pf_init */
5406 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
5411 static inline u8
bnx2x_fp_igu_sb_id(struct bnx2x_fastpath
*fp
)
5413 return fp
->bp
->igu_base_sb
+ fp
->index
+ CNIC_PRESENT
;
5416 static inline u8
bnx2x_fp_fw_sb_id(struct bnx2x_fastpath
*fp
)
5418 return fp
->bp
->base_fw_ndsb
+ fp
->index
+ CNIC_PRESENT
;
5421 static inline u8
bnx2x_fp_cl_id(struct bnx2x_fastpath
*fp
)
5423 if (CHIP_IS_E1x(fp
->bp
))
5424 return BP_L_ID(fp
->bp
) + fp
->index
;
5425 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5426 return bnx2x_fp_igu_sb_id(fp
);
5429 static void bnx2x_init_eth_fp(struct bnx2x
*bp
, int fp_idx
)
5431 struct bnx2x_fastpath
*fp
= &bp
->fp
[fp_idx
];
5433 unsigned long q_type
= 0;
5434 u32 cids
[BNX2X_MULTI_TX_COS
] = { 0 };
5435 fp
->rx_queue
= fp_idx
;
5437 fp
->cl_id
= bnx2x_fp_cl_id(fp
);
5438 fp
->fw_sb_id
= bnx2x_fp_fw_sb_id(fp
);
5439 fp
->igu_sb_id
= bnx2x_fp_igu_sb_id(fp
);
5440 /* qZone id equals to FW (per path) client id */
5441 fp
->cl_qzone_id
= bnx2x_fp_qzone_id(fp
);
5444 fp
->ustorm_rx_prods_offset
= bnx2x_rx_ustorm_prods_offset(fp
);
5446 /* Setup SB indicies */
5447 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
5449 /* Configure Queue State object */
5450 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
5451 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
5453 BUG_ON(fp
->max_cos
> BNX2X_MULTI_TX_COS
);
5456 for_each_cos_in_tx_queue(fp
, cos
) {
5457 bnx2x_init_txdata(bp
, &fp
->txdata
[cos
],
5458 CID_COS_TO_TX_ONLY_CID(fp
->cid
, cos
),
5459 FP_COS_TO_TXQ(fp
, cos
),
5460 BNX2X_TX_SB_INDEX_BASE
+ cos
);
5461 cids
[cos
] = fp
->txdata
[cos
].cid
;
5464 bnx2x_init_queue_obj(bp
, &fp
->q_obj
, fp
->cl_id
, cids
, fp
->max_cos
,
5465 BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
5466 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
5469 * Configure classification DBs: Always enable Tx switching
5471 bnx2x_init_vlan_mac_fp_objs(fp
, BNX2X_OBJ_TYPE_RX_TX
);
5473 DP(NETIF_MSG_IFUP
, "queue[%d]: bnx2x_init_sb(%p,%p) "
5474 "cl_id %d fw_sb %d igu_sb %d\n",
5475 fp_idx
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
5477 bnx2x_init_sb(bp
, fp
->status_blk_mapping
, BNX2X_VF_ID_INVALID
, false,
5478 fp
->fw_sb_id
, fp
->igu_sb_id
);
5480 bnx2x_update_fpsb_idx(fp
);
5483 void bnx2x_nic_init(struct bnx2x
*bp
, u32 load_code
)
5487 for_each_eth_queue(bp
, i
)
5488 bnx2x_init_eth_fp(bp
, i
);
5491 bnx2x_init_fcoe_fp(bp
);
5493 bnx2x_init_sb(bp
, bp
->cnic_sb_mapping
,
5494 BNX2X_VF_ID_INVALID
, false,
5495 bnx2x_cnic_fw_sb_id(bp
), bnx2x_cnic_igu_sb_id(bp
));
5499 /* Initialize MOD_ABS interrupts */
5500 bnx2x_init_mod_abs_int(bp
, &bp
->link_vars
, bp
->common
.chip_id
,
5501 bp
->common
.shmem_base
, bp
->common
.shmem2_base
,
5503 /* ensure status block indices were read */
5506 bnx2x_init_def_sb(bp
);
5507 bnx2x_update_dsb_idx(bp
);
5508 bnx2x_init_rx_rings(bp
);
5509 bnx2x_init_tx_rings(bp
);
5510 bnx2x_init_sp_ring(bp
);
5511 bnx2x_init_eq_ring(bp
);
5512 bnx2x_init_internal(bp
, load_code
);
5514 bnx2x_stats_init(bp
);
5516 /* flush all before enabling interrupts */
5520 bnx2x_int_enable(bp
);
5522 /* Check for SPIO5 */
5523 bnx2x_attn_int_deasserted0(bp
,
5524 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ BP_PORT(bp
)*4) &
5525 AEU_INPUTS_ATTN_BITS_SPIO5
);
5528 /* end of nic init */
5531 * gzip service functions
5534 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
5536 bp
->gunzip_buf
= dma_alloc_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
,
5537 &bp
->gunzip_mapping
, GFP_KERNEL
);
5538 if (bp
->gunzip_buf
== NULL
)
5541 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
5542 if (bp
->strm
== NULL
)
5545 bp
->strm
->workspace
= vmalloc(zlib_inflate_workspacesize());
5546 if (bp
->strm
->workspace
== NULL
)
5556 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
5557 bp
->gunzip_mapping
);
5558 bp
->gunzip_buf
= NULL
;
5561 netdev_err(bp
->dev
, "Cannot allocate firmware buffer for"
5562 " un-compression\n");
5566 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
5569 vfree(bp
->strm
->workspace
);
5574 if (bp
->gunzip_buf
) {
5575 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
5576 bp
->gunzip_mapping
);
5577 bp
->gunzip_buf
= NULL
;
5581 static int bnx2x_gunzip(struct bnx2x
*bp
, const u8
*zbuf
, int len
)
5585 /* check gzip header */
5586 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
)) {
5587 BNX2X_ERR("Bad gzip header\n");
5595 if (zbuf
[3] & FNAME
)
5596 while ((zbuf
[n
++] != 0) && (n
< len
));
5598 bp
->strm
->next_in
= (typeof(bp
->strm
->next_in
))zbuf
+ n
;
5599 bp
->strm
->avail_in
= len
- n
;
5600 bp
->strm
->next_out
= bp
->gunzip_buf
;
5601 bp
->strm
->avail_out
= FW_BUF_SIZE
;
5603 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
5607 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
5608 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
5609 netdev_err(bp
->dev
, "Firmware decompression error: %s\n",
5612 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
5613 if (bp
->gunzip_outlen
& 0x3)
5614 netdev_err(bp
->dev
, "Firmware decompression error:"
5615 " gunzip_outlen (%d) not aligned\n",
5617 bp
->gunzip_outlen
>>= 2;
5619 zlib_inflateEnd(bp
->strm
);
5621 if (rc
== Z_STREAM_END
)
5627 /* nic load/unload */
5630 * General service functions
5633 /* send a NIG loopback debug packet */
5634 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
5638 /* Ethernet source and destination addresses */
5639 wb_write
[0] = 0x55555555;
5640 wb_write
[1] = 0x55555555;
5641 wb_write
[2] = 0x20; /* SOP */
5642 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
5644 /* NON-IP protocol */
5645 wb_write
[0] = 0x09000000;
5646 wb_write
[1] = 0x55555555;
5647 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
5648 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
5651 /* some of the internal memories
5652 * are not directly readable from the driver
5653 * to test them we send debug packets
5655 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
5661 if (CHIP_REV_IS_FPGA(bp
))
5663 else if (CHIP_REV_IS_EMUL(bp
))
5668 /* Disable inputs of parser neighbor blocks */
5669 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
5670 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
5671 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
5672 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
5674 /* Write 0 to parser credits for CFC search request */
5675 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
5677 /* send Ethernet packet */
5680 /* TODO do i reset NIG statistic? */
5681 /* Wait until NIG register shows 1 packet of size 0x10 */
5682 count
= 1000 * factor
;
5685 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
5686 val
= *bnx2x_sp(bp
, wb_data
[0]);
5694 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
5698 /* Wait until PRS register shows 1 packet */
5699 count
= 1000 * factor
;
5701 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5709 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5713 /* Reset and init BRB, PRS */
5714 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
5716 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
5718 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
5719 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
5721 DP(NETIF_MSG_HW
, "part2\n");
5723 /* Disable inputs of parser neighbor blocks */
5724 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
5725 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
5726 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
5727 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
5729 /* Write 0 to parser credits for CFC search request */
5730 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
5732 /* send 10 Ethernet packets */
5733 for (i
= 0; i
< 10; i
++)
5736 /* Wait until NIG register shows 10 + 1
5737 packets of size 11*0x10 = 0xb0 */
5738 count
= 1000 * factor
;
5741 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
5742 val
= *bnx2x_sp(bp
, wb_data
[0]);
5750 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
5754 /* Wait until PRS register shows 2 packets */
5755 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5757 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5759 /* Write 1 to parser credits for CFC search request */
5760 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
5762 /* Wait until PRS register shows 3 packets */
5763 msleep(10 * factor
);
5764 /* Wait until NIG register shows 1 packet of size 0x10 */
5765 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5767 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5769 /* clear NIG EOP FIFO */
5770 for (i
= 0; i
< 11; i
++)
5771 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
5772 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
5774 BNX2X_ERR("clear of NIG failed\n");
5778 /* Reset and init BRB, PRS, NIG */
5779 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
5781 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
5783 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
5784 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
5787 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
5790 /* Enable inputs of parser neighbor blocks */
5791 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
5792 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
5793 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
5794 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
5796 DP(NETIF_MSG_HW
, "done\n");
5801 static void bnx2x_enable_blocks_attention(struct bnx2x
*bp
)
5803 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
5804 if (!CHIP_IS_E1x(bp
))
5805 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0x40);
5807 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
5808 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
5809 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
5811 * mask read length error interrupts in brb for parser
5812 * (parsing unit and 'checksum and crc' unit)
5813 * these errors are legal (PU reads fixed length and CAC can cause
5814 * read length error on truncated packets)
5816 REG_WR(bp
, BRB1_REG_BRB1_INT_MASK
, 0xFC00);
5817 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
5818 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
5819 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
5820 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
5821 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
5822 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5823 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5824 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
5825 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
5826 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
5827 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5828 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5829 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
5830 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
5831 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
5832 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
5833 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5834 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5836 if (CHIP_REV_IS_FPGA(bp
))
5837 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, 0x580000);
5838 else if (!CHIP_IS_E1x(bp
))
5839 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
,
5840 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5841 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5842 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5843 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5844 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
));
5846 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, 0x480000);
5847 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
5848 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
5849 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
5850 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5852 if (!CHIP_IS_E1x(bp
))
5853 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5854 REG_WR(bp
, TSEM_REG_TSEM_INT_MASK_1
, 0x07ff);
5856 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
5857 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
5858 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5859 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0x18); /* bit 3,4 masked */
5862 static void bnx2x_reset_common(struct bnx2x
*bp
)
5867 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
5870 if (CHIP_IS_E3(bp
)) {
5871 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
5872 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
5875 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, val
);
5878 static void bnx2x_setup_dmae(struct bnx2x
*bp
)
5881 spin_lock_init(&bp
->dmae_lock
);
5884 static void bnx2x_init_pxp(struct bnx2x
*bp
)
5887 int r_order
, w_order
;
5889 pci_read_config_word(bp
->pdev
,
5890 pci_pcie_cap(bp
->pdev
) + PCI_EXP_DEVCTL
, &devctl
);
5891 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
5892 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
5894 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
5896 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
5900 bnx2x_init_pxp_arb(bp
, r_order
, w_order
);
5903 static void bnx2x_setup_fan_failure_detection(struct bnx2x
*bp
)
5913 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
5914 SHARED_HW_CFG_FAN_FAILURE_MASK
;
5916 if (val
== SHARED_HW_CFG_FAN_FAILURE_ENABLED
)
5920 * The fan failure mechanism is usually related to the PHY type since
5921 * the power consumption of the board is affected by the PHY. Currently,
5922 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5924 else if (val
== SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
)
5925 for (port
= PORT_0
; port
< PORT_MAX
; port
++) {
5927 bnx2x_fan_failure_det_req(
5929 bp
->common
.shmem_base
,
5930 bp
->common
.shmem2_base
,
5934 DP(NETIF_MSG_HW
, "fan detection setting: %d\n", is_required
);
5936 if (is_required
== 0)
5939 /* Fan failure is indicated by SPIO 5 */
5940 bnx2x_set_spio(bp
, MISC_REGISTERS_SPIO_5
,
5941 MISC_REGISTERS_SPIO_INPUT_HI_Z
);
5943 /* set to active low mode */
5944 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
5945 val
|= ((1 << MISC_REGISTERS_SPIO_5
) <<
5946 MISC_REGISTERS_SPIO_INT_OLD_SET_POS
);
5947 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
5949 /* enable interrupt to signal the IGU */
5950 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
5951 val
|= (1 << MISC_REGISTERS_SPIO_5
);
5952 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
5955 static void bnx2x_pretend_func(struct bnx2x
*bp
, u8 pretend_func_num
)
5961 if (CHIP_IS_E1H(bp
) && (pretend_func_num
>= E1H_FUNC_MAX
))
5964 switch (BP_ABS_FUNC(bp
)) {
5966 offset
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
5969 offset
= PXP2_REG_PGL_PRETEND_FUNC_F1
;
5972 offset
= PXP2_REG_PGL_PRETEND_FUNC_F2
;
5975 offset
= PXP2_REG_PGL_PRETEND_FUNC_F3
;
5978 offset
= PXP2_REG_PGL_PRETEND_FUNC_F4
;
5981 offset
= PXP2_REG_PGL_PRETEND_FUNC_F5
;
5984 offset
= PXP2_REG_PGL_PRETEND_FUNC_F6
;
5987 offset
= PXP2_REG_PGL_PRETEND_FUNC_F7
;
5993 REG_WR(bp
, offset
, pretend_func_num
);
5995 DP(NETIF_MSG_HW
, "Pretending to func %d\n", pretend_func_num
);
5998 void bnx2x_pf_disable(struct bnx2x
*bp
)
6000 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
6001 val
&= ~IGU_PF_CONF_FUNC_EN
;
6003 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
6004 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
6005 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 0);
6008 static inline void bnx2x__common_init_phy(struct bnx2x
*bp
)
6010 u32 shmem_base
[2], shmem2_base
[2];
6011 shmem_base
[0] = bp
->common
.shmem_base
;
6012 shmem2_base
[0] = bp
->common
.shmem2_base
;
6013 if (!CHIP_IS_E1x(bp
)) {
6015 SHMEM2_RD(bp
, other_shmem_base_addr
);
6017 SHMEM2_RD(bp
, other_shmem2_base_addr
);
6019 bnx2x_acquire_phy_lock(bp
);
6020 bnx2x_common_init_phy(bp
, shmem_base
, shmem2_base
,
6021 bp
->common
.chip_id
);
6022 bnx2x_release_phy_lock(bp
);
6026 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6028 * @bp: driver handle
6030 static int bnx2x_init_hw_common(struct bnx2x
*bp
)
6034 DP(BNX2X_MSG_MCP
, "starting common init func %d\n", BP_ABS_FUNC(bp
));
6037 * take the UNDI lock to protect undi_unload flow from accessing
6038 * registers while we're resetting the chip
6040 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
6042 bnx2x_reset_common(bp
);
6043 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
6046 if (CHIP_IS_E3(bp
)) {
6047 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6048 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6050 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, val
);
6052 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
6054 bnx2x_init_block(bp
, BLOCK_MISC
, PHASE_COMMON
);
6056 if (!CHIP_IS_E1x(bp
)) {
6060 * 4-port mode or 2-port mode we need to turn of master-enable
6061 * for everyone, after that, turn it back on for self.
6062 * so, we disregard multi-function or not, and always disable
6063 * for all functions on the given path, this means 0,2,4,6 for
6064 * path 0 and 1,3,5,7 for path 1
6066 for (abs_func_id
= BP_PATH(bp
);
6067 abs_func_id
< E2_FUNC_MAX
*2; abs_func_id
+= 2) {
6068 if (abs_func_id
== BP_ABS_FUNC(bp
)) {
6070 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
,
6075 bnx2x_pretend_func(bp
, abs_func_id
);
6076 /* clear pf enable */
6077 bnx2x_pf_disable(bp
);
6078 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6082 bnx2x_init_block(bp
, BLOCK_PXP
, PHASE_COMMON
);
6083 if (CHIP_IS_E1(bp
)) {
6084 /* enable HW interrupt from PXP on USDM overflow
6085 bit 16 on INT_MASK_0 */
6086 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6089 bnx2x_init_block(bp
, BLOCK_PXP2
, PHASE_COMMON
);
6093 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, 1);
6094 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, 1);
6095 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, 1);
6096 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, 1);
6097 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, 1);
6098 /* make sure this value is 0 */
6099 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 0);
6101 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6102 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, 1);
6103 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, 1);
6104 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, 1);
6105 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, 1);
6108 bnx2x_ilt_init_page_size(bp
, INITOP_SET
);
6110 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
6111 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
6113 /* let the HW do it's magic ... */
6115 /* finish PXP init */
6116 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
6118 BNX2X_ERR("PXP2 CFG failed\n");
6121 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
6123 BNX2X_ERR("PXP2 RD_INIT failed\n");
6127 /* Timers bug workaround E2 only. We need to set the entire ILT to
6128 * have entries with value "0" and valid bit on.
6129 * This needs to be done by the first PF that is loaded in a path
6130 * (i.e. common phase)
6132 if (!CHIP_IS_E1x(bp
)) {
6133 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6134 * (i.e. vnic3) to start even if it is marked as "scan-off".
6135 * This occurs when a different function (func2,3) is being marked
6136 * as "scan-off". Real-life scenario for example: if a driver is being
6137 * load-unloaded while func6,7 are down. This will cause the timer to access
6138 * the ilt, translate to a logical address and send a request to read/write.
6139 * Since the ilt for the function that is down is not valid, this will cause
6140 * a translation error which is unrecoverable.
6141 * The Workaround is intended to make sure that when this happens nothing fatal
6142 * will occur. The workaround:
6143 * 1. First PF driver which loads on a path will:
6144 * a. After taking the chip out of reset, by using pretend,
6145 * it will write "0" to the following registers of
6147 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6148 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6149 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6150 * And for itself it will write '1' to
6151 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6152 * dmae-operations (writing to pram for example.)
6153 * note: can be done for only function 6,7 but cleaner this
6155 * b. Write zero+valid to the entire ILT.
6156 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6157 * VNIC3 (of that port). The range allocated will be the
6158 * entire ILT. This is needed to prevent ILT range error.
6159 * 2. Any PF driver load flow:
6160 * a. ILT update with the physical addresses of the allocated
6162 * b. Wait 20msec. - note that this timeout is needed to make
6163 * sure there are no requests in one of the PXP internal
6164 * queues with "old" ILT addresses.
6165 * c. PF enable in the PGLC.
6166 * d. Clear the was_error of the PF in the PGLC. (could have
6167 * occured while driver was down)
6168 * e. PF enable in the CFC (WEAK + STRONG)
6169 * f. Timers scan enable
6170 * 3. PF driver unload flow:
6171 * a. Clear the Timers scan_en.
6172 * b. Polling for scan_on=0 for that PF.
6173 * c. Clear the PF enable bit in the PXP.
6174 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6175 * e. Write zero+valid to all ILT entries (The valid bit must
6177 * f. If this is VNIC 3 of a port then also init
6178 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6179 * to the last enrty in the ILT.
6182 * Currently the PF error in the PGLC is non recoverable.
6183 * In the future the there will be a recovery routine for this error.
6184 * Currently attention is masked.
6185 * Having an MCP lock on the load/unload process does not guarantee that
6186 * there is no Timer disable during Func6/7 enable. This is because the
6187 * Timers scan is currently being cleared by the MCP on FLR.
6188 * Step 2.d can be done only for PF6/7 and the driver can also check if
6189 * there is error before clearing it. But the flow above is simpler and
6191 * All ILT entries are written by zero+valid and not just PF6/7
6192 * ILT entries since in the future the ILT entries allocation for
6193 * PF-s might be dynamic.
6195 struct ilt_client_info ilt_cli
;
6196 struct bnx2x_ilt ilt
;
6197 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
6198 memset(&ilt
, 0, sizeof(struct bnx2x_ilt
));
6200 /* initialize dummy TM client */
6202 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
6203 ilt_cli
.client_num
= ILT_CLIENT_TM
;
6205 /* Step 1: set zeroes to all ilt page entries with valid bit on
6206 * Step 2: set the timers first/last ilt entry to point
6207 * to the entire range to prevent ILT range error for 3rd/4th
6208 * vnic (this code assumes existance of the vnic)
6210 * both steps performed by call to bnx2x_ilt_client_init_op()
6211 * with dummy TM client
6213 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6214 * and his brother are split registers
6216 bnx2x_pretend_func(bp
, (BP_PATH(bp
) + 6));
6217 bnx2x_ilt_client_init_op_ilt(bp
, &ilt
, &ilt_cli
, INITOP_CLEAR
);
6218 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6220 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN
, BNX2X_PXP_DRAM_ALIGN
);
6221 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_RD
, BNX2X_PXP_DRAM_ALIGN
);
6222 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_SEL
, 1);
6226 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
6227 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
6229 if (!CHIP_IS_E1x(bp
)) {
6230 int factor
= CHIP_REV_IS_EMUL(bp
) ? 1000 :
6231 (CHIP_REV_IS_FPGA(bp
) ? 400 : 0);
6232 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, PHASE_COMMON
);
6234 bnx2x_init_block(bp
, BLOCK_ATC
, PHASE_COMMON
);
6236 /* let the HW do it's magic ... */
6239 val
= REG_RD(bp
, ATC_REG_ATC_INIT_DONE
);
6240 } while (factor
-- && (val
!= 1));
6243 BNX2X_ERR("ATC_INIT failed\n");
6248 bnx2x_init_block(bp
, BLOCK_DMAE
, PHASE_COMMON
);
6250 /* clean the DMAE memory */
6252 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8, 1);
6254 bnx2x_init_block(bp
, BLOCK_TCM
, PHASE_COMMON
);
6256 bnx2x_init_block(bp
, BLOCK_UCM
, PHASE_COMMON
);
6258 bnx2x_init_block(bp
, BLOCK_CCM
, PHASE_COMMON
);
6260 bnx2x_init_block(bp
, BLOCK_XCM
, PHASE_COMMON
);
6262 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
6263 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
6264 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
6265 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
6267 bnx2x_init_block(bp
, BLOCK_QM
, PHASE_COMMON
);
6270 /* QM queues pointers table */
6271 bnx2x_qm_init_ptr_table(bp
, bp
->qm_cid_count
, INITOP_SET
);
6273 /* soft reset pulse */
6274 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
6275 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
6278 bnx2x_init_block(bp
, BLOCK_TM
, PHASE_COMMON
);
6281 bnx2x_init_block(bp
, BLOCK_DORQ
, PHASE_COMMON
);
6282 REG_WR(bp
, DORQ_REG_DPM_CID_OFST
, BNX2X_DB_SHIFT
);
6283 if (!CHIP_REV_IS_SLOW(bp
))
6284 /* enable hw interrupt from doorbell Q */
6285 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6287 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6289 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6290 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
6292 if (!CHIP_IS_E1(bp
))
6293 REG_WR(bp
, PRS_REG_E1HOV_MODE
, bp
->path_has_ovlan
);
6295 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_E3B0(bp
))
6296 /* Bit-map indicating which L2 hdrs may appear
6297 * after the basic Ethernet header
6299 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
,
6300 bp
->path_has_ovlan
? 7 : 6);
6302 bnx2x_init_block(bp
, BLOCK_TSDM
, PHASE_COMMON
);
6303 bnx2x_init_block(bp
, BLOCK_CSDM
, PHASE_COMMON
);
6304 bnx2x_init_block(bp
, BLOCK_USDM
, PHASE_COMMON
);
6305 bnx2x_init_block(bp
, BLOCK_XSDM
, PHASE_COMMON
);
6307 if (!CHIP_IS_E1x(bp
)) {
6308 /* reset VFC memories */
6309 REG_WR(bp
, TSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6310 VFC_MEMORIES_RST_REG_CAM_RST
|
6311 VFC_MEMORIES_RST_REG_RAM_RST
);
6312 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6313 VFC_MEMORIES_RST_REG_CAM_RST
|
6314 VFC_MEMORIES_RST_REG_RAM_RST
);
6319 bnx2x_init_block(bp
, BLOCK_TSEM
, PHASE_COMMON
);
6320 bnx2x_init_block(bp
, BLOCK_USEM
, PHASE_COMMON
);
6321 bnx2x_init_block(bp
, BLOCK_CSEM
, PHASE_COMMON
);
6322 bnx2x_init_block(bp
, BLOCK_XSEM
, PHASE_COMMON
);
6325 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6327 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
6330 bnx2x_init_block(bp
, BLOCK_UPB
, PHASE_COMMON
);
6331 bnx2x_init_block(bp
, BLOCK_XPB
, PHASE_COMMON
);
6332 bnx2x_init_block(bp
, BLOCK_PBF
, PHASE_COMMON
);
6334 if (!CHIP_IS_E1x(bp
))
6335 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
,
6336 bp
->path_has_ovlan
? 7 : 6);
6338 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
6340 bnx2x_init_block(bp
, BLOCK_SRC
, PHASE_COMMON
);
6343 REG_WR(bp
, SRC_REG_KEYSEARCH_0
, 0x63285672);
6344 REG_WR(bp
, SRC_REG_KEYSEARCH_1
, 0x24b8f2cc);
6345 REG_WR(bp
, SRC_REG_KEYSEARCH_2
, 0x223aef9b);
6346 REG_WR(bp
, SRC_REG_KEYSEARCH_3
, 0x26001e3a);
6347 REG_WR(bp
, SRC_REG_KEYSEARCH_4
, 0x7ae91116);
6348 REG_WR(bp
, SRC_REG_KEYSEARCH_5
, 0x5ce5230b);
6349 REG_WR(bp
, SRC_REG_KEYSEARCH_6
, 0x298d8adf);
6350 REG_WR(bp
, SRC_REG_KEYSEARCH_7
, 0x6eb0ff09);
6351 REG_WR(bp
, SRC_REG_KEYSEARCH_8
, 0x1830f82f);
6352 REG_WR(bp
, SRC_REG_KEYSEARCH_9
, 0x01e46be7);
6354 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
6356 if (sizeof(union cdu_context
) != 1024)
6357 /* we currently assume that a context is 1024 bytes */
6358 dev_alert(&bp
->pdev
->dev
, "please adjust the size "
6359 "of cdu_context(%ld)\n",
6360 (long)sizeof(union cdu_context
));
6362 bnx2x_init_block(bp
, BLOCK_CDU
, PHASE_COMMON
);
6363 val
= (4 << 24) + (0 << 12) + 1024;
6364 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
6366 bnx2x_init_block(bp
, BLOCK_CFC
, PHASE_COMMON
);
6367 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
6368 /* enable context validation interrupt from CFC */
6369 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6371 /* set the thresholds to prevent CFC/CDU race */
6372 REG_WR(bp
, CFC_REG_DEBUG0
, 0x20020000);
6374 bnx2x_init_block(bp
, BLOCK_HC
, PHASE_COMMON
);
6376 if (!CHIP_IS_E1x(bp
) && BP_NOMCP(bp
))
6377 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x36);
6379 bnx2x_init_block(bp
, BLOCK_IGU
, PHASE_COMMON
);
6380 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, PHASE_COMMON
);
6382 /* Reset PCIE errors for debug */
6383 REG_WR(bp
, 0x2814, 0xffffffff);
6384 REG_WR(bp
, 0x3820, 0xffffffff);
6386 if (!CHIP_IS_E1x(bp
)) {
6387 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_CONTROL_5
,
6388 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
|
6389 PXPCS_TL_CONTROL_5_ERR_UNSPPORT
));
6390 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC345_STAT
,
6391 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
|
6392 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
|
6393 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
));
6394 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC678_STAT
,
6395 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
|
6396 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
|
6397 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
));
6400 bnx2x_init_block(bp
, BLOCK_NIG
, PHASE_COMMON
);
6401 if (!CHIP_IS_E1(bp
)) {
6402 /* in E3 this done in per-port section */
6403 if (!CHIP_IS_E3(bp
))
6404 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
6406 if (CHIP_IS_E1H(bp
))
6407 /* not applicable for E2 (and above ...) */
6408 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_MF_SD(bp
));
6410 if (CHIP_REV_IS_SLOW(bp
))
6413 /* finish CFC init */
6414 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
6416 BNX2X_ERR("CFC LL_INIT failed\n");
6419 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
6421 BNX2X_ERR("CFC AC_INIT failed\n");
6424 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
6426 BNX2X_ERR("CFC CAM_INIT failed\n");
6429 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
6431 if (CHIP_IS_E1(bp
)) {
6432 /* read NIG statistic
6433 to see if this is our first up since powerup */
6434 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6435 val
= *bnx2x_sp(bp
, wb_data
[0]);
6437 /* do internal memory self test */
6438 if ((val
== 0) && bnx2x_int_mem_test(bp
)) {
6439 BNX2X_ERR("internal mem self test failed\n");
6444 bnx2x_setup_fan_failure_detection(bp
);
6446 /* clear PXP2 attentions */
6447 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
6449 bnx2x_enable_blocks_attention(bp
);
6450 bnx2x_enable_blocks_parity(bp
);
6452 if (!BP_NOMCP(bp
)) {
6453 if (CHIP_IS_E1x(bp
))
6454 bnx2x__common_init_phy(bp
);
6456 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6462 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6464 * @bp: driver handle
6466 static int bnx2x_init_hw_common_chip(struct bnx2x
*bp
)
6468 int rc
= bnx2x_init_hw_common(bp
);
6473 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6475 bnx2x__common_init_phy(bp
);
6480 static int bnx2x_init_hw_port(struct bnx2x
*bp
)
6482 int port
= BP_PORT(bp
);
6483 int init_phase
= port
? PHASE_PORT1
: PHASE_PORT0
;
6487 bnx2x__link_reset(bp
);
6489 DP(BNX2X_MSG_MCP
, "starting port init port %d\n", port
);
6491 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
6493 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
6494 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
6495 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
6497 /* Timers bug workaround: disables the pf_master bit in pglue at
6498 * common phase, we need to enable it here before any dmae access are
6499 * attempted. Therefore we manually added the enable-master to the
6500 * port phase (it also happens in the function phase)
6502 if (!CHIP_IS_E1x(bp
))
6503 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
6505 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
6506 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
6507 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
6508 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
6510 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
6511 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
6512 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
6513 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
6515 /* QM cid (connection) count */
6516 bnx2x_qm_init_cid_count(bp
, bp
->qm_cid_count
, INITOP_SET
);
6519 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
6520 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ port
*4, 20);
6521 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ port
*4, 31);
6524 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
6526 if (CHIP_IS_E1(bp
) || CHIP_IS_E1H(bp
)) {
6527 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
6530 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 160 : 246);
6531 else if (bp
->dev
->mtu
> 4096) {
6532 if (bp
->flags
& ONE_PORT_FLAG
)
6536 /* (24*1024 + val*4)/256 */
6537 low
= 96 + (val
/64) +
6538 ((val
% 64) ? 1 : 0);
6541 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 80 : 160);
6542 high
= low
+ 56; /* 14*1024/256 */
6543 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
+ port
*4, low
);
6544 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
+ port
*4, high
);
6547 if (CHIP_MODE_IS_4_PORT(bp
))
6548 REG_WR(bp
, (BP_PORT(bp
) ?
6549 BRB1_REG_MAC_GUARANTIED_1
:
6550 BRB1_REG_MAC_GUARANTIED_0
), 40);
6553 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
6554 if (CHIP_IS_E3B0(bp
))
6555 /* Ovlan exists only if we are in multi-function +
6556 * switch-dependent mode, in switch-independent there
6557 * is no ovlan headers
6559 REG_WR(bp
, BP_PORT(bp
) ?
6560 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
6561 PRS_REG_HDRS_AFTER_BASIC_PORT_0
,
6562 (bp
->path_has_ovlan
? 7 : 6));
6564 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
6565 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
6566 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
6567 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
6569 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
6570 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
6571 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
6572 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
6574 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
6575 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
6577 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
6579 if (CHIP_IS_E1x(bp
)) {
6580 /* configure PBF to work without PAUSE mtu 9000 */
6581 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
6583 /* update threshold */
6584 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
6585 /* update init credit */
6586 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
6589 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
6591 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
6595 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
6597 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
6598 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
6600 if (CHIP_IS_E1(bp
)) {
6601 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
6602 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
6604 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
6606 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
6608 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
6609 /* init aeu_mask_attn_func_0/1:
6610 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6611 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6612 * bits 4-7 are used for "per vn group attention" */
6613 val
= IS_MF(bp
) ? 0xF7 : 0x7;
6614 /* Enable DCBX attention for all but E1 */
6615 val
|= CHIP_IS_E1(bp
) ? 0 : 0x10;
6616 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, val
);
6618 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
6620 if (!CHIP_IS_E1x(bp
)) {
6621 /* Bit-map indicating which L2 hdrs may appear after the
6622 * basic Ethernet header
6624 REG_WR(bp
, BP_PORT(bp
) ?
6625 NIG_REG_P1_HDRS_AFTER_BASIC
:
6626 NIG_REG_P0_HDRS_AFTER_BASIC
,
6627 IS_MF_SD(bp
) ? 7 : 6);
6630 REG_WR(bp
, BP_PORT(bp
) ?
6631 NIG_REG_LLH1_MF_MODE
:
6632 NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
6634 if (!CHIP_IS_E3(bp
))
6635 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
6637 if (!CHIP_IS_E1(bp
)) {
6638 /* 0x2 disable mf_ov, 0x1 enable */
6639 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
6640 (IS_MF_SD(bp
) ? 0x1 : 0x2));
6642 if (!CHIP_IS_E1x(bp
)) {
6644 switch (bp
->mf_mode
) {
6645 case MULTI_FUNCTION_SD
:
6648 case MULTI_FUNCTION_SI
:
6653 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_CLS_TYPE
:
6654 NIG_REG_LLH0_CLS_TYPE
), val
);
6657 REG_WR(bp
, NIG_REG_LLFC_ENABLE_0
+ port
*4, 0);
6658 REG_WR(bp
, NIG_REG_LLFC_OUT_EN_0
+ port
*4, 0);
6659 REG_WR(bp
, NIG_REG_PAUSE_ENABLE_0
+ port
*4, 1);
6664 /* If SPIO5 is set to generate interrupts, enable it for this port */
6665 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
6666 if (val
& (1 << MISC_REGISTERS_SPIO_5
)) {
6667 u32 reg_addr
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
6668 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
6669 val
= REG_RD(bp
, reg_addr
);
6670 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
6671 REG_WR(bp
, reg_addr
, val
);
6677 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
6682 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
6684 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
6686 bnx2x_wb_wr(bp
, reg
, ONCHIP_ADDR1(addr
), ONCHIP_ADDR2(addr
));
6689 static inline void bnx2x_igu_clear_sb(struct bnx2x
*bp
, u8 idu_sb_id
)
6691 bnx2x_igu_clear_sb_gen(bp
, BP_FUNC(bp
), idu_sb_id
, true /*PF*/);
6694 static inline void bnx2x_clear_func_ilt(struct bnx2x
*bp
, u32 func
)
6696 u32 i
, base
= FUNC_ILT_BASE(func
);
6697 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
6698 bnx2x_ilt_wr(bp
, i
, 0);
6701 static int bnx2x_init_hw_func(struct bnx2x
*bp
)
6703 int port
= BP_PORT(bp
);
6704 int func
= BP_FUNC(bp
);
6705 int init_phase
= PHASE_PF0
+ func
;
6706 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
6709 u32 main_mem_base
, main_mem_size
, main_mem_prty_clr
;
6710 int i
, main_mem_width
, rc
;
6712 DP(BNX2X_MSG_MCP
, "starting func init func %d\n", func
);
6714 /* FLR cleanup - hmmm */
6715 if (!CHIP_IS_E1x(bp
)) {
6716 rc
= bnx2x_pf_flr_clnup(bp
);
6721 /* set MSI reconfigure capability */
6722 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6723 addr
= (port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
);
6724 val
= REG_RD(bp
, addr
);
6725 val
|= HC_CONFIG_0_REG_MSI_ATTN_EN_0
;
6726 REG_WR(bp
, addr
, val
);
6729 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
6730 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
6733 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
6735 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++) {
6736 ilt
->lines
[cdu_ilt_start
+ i
].page
=
6737 bp
->context
.vcxt
+ (ILT_PAGE_CIDS
* i
);
6738 ilt
->lines
[cdu_ilt_start
+ i
].page_mapping
=
6739 bp
->context
.cxt_mapping
+ (CDU_ILT_PAGE_SZ
* i
);
6740 /* cdu ilt pages are allocated manually so there's no need to
6743 bnx2x_ilt_init_op(bp
, INITOP_SET
);
6746 bnx2x_src_init_t2(bp
, bp
->t2
, bp
->t2_mapping
, SRC_CONN_NUM
);
6748 /* T1 hash bits value determines the T1 number of entries */
6749 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ port
*4, SRC_HASH_BITS
);
6754 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
6755 #endif /* BCM_CNIC */
6757 if (!CHIP_IS_E1x(bp
)) {
6758 u32 pf_conf
= IGU_PF_CONF_FUNC_EN
;
6760 /* Turn on a single ISR mode in IGU if driver is going to use
6763 if (!(bp
->flags
& USING_MSIX_FLAG
))
6764 pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
6766 * Timers workaround bug: function init part.
6767 * Need to wait 20msec after initializing ILT,
6768 * needed to make sure there are no requests in
6769 * one of the PXP internal queues with "old" ILT addresses
6773 * Master enable - Due to WB DMAE writes performed before this
6774 * register is re-initialized as part of the regular function
6777 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
6778 /* Enable the function in IGU */
6779 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, pf_conf
);
6784 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
6786 if (!CHIP_IS_E1x(bp
))
6787 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
, func
);
6789 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
6790 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
6791 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
6792 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
6793 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
6794 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
6795 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
6796 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
6797 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
6798 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
6799 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
6800 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
6801 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
6803 if (!CHIP_IS_E1x(bp
))
6804 REG_WR(bp
, QM_REG_PF_EN
, 1);
6806 if (!CHIP_IS_E1x(bp
)) {
6807 REG_WR(bp
, TSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6808 REG_WR(bp
, USEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6809 REG_WR(bp
, CSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6810 REG_WR(bp
, XSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6812 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
6814 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
6815 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
6816 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
6817 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
6818 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
6819 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
6820 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
6821 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
6822 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
6823 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
6824 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
6825 if (!CHIP_IS_E1x(bp
))
6826 REG_WR(bp
, PBF_REG_DISABLE_PF
, 0);
6828 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
6830 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
6832 if (!CHIP_IS_E1x(bp
))
6833 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 1);
6836 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
6837 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
*8, bp
->mf_ov
);
6840 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
6842 /* HC init per function */
6843 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6844 if (CHIP_IS_E1H(bp
)) {
6845 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
6847 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
6848 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
6850 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
6853 int num_segs
, sb_idx
, prod_offset
;
6855 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
6857 if (!CHIP_IS_E1x(bp
)) {
6858 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
6859 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
6862 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
6864 if (!CHIP_IS_E1x(bp
)) {
6868 * E2 mode: address 0-135 match to the mapping memory;
6869 * 136 - PF0 default prod; 137 - PF1 default prod;
6870 * 138 - PF2 default prod; 139 - PF3 default prod;
6871 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6872 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6875 * E1.5 mode - In backward compatible mode;
6876 * for non default SB; each even line in the memory
6877 * holds the U producer and each odd line hold
6878 * the C producer. The first 128 producers are for
6879 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6880 * producers are for the DSB for each PF.
6881 * Each PF has five segments: (the order inside each
6882 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6883 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6884 * 144-147 attn prods;
6886 /* non-default-status-blocks */
6887 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
6888 IGU_BC_NDSB_NUM_SEGS
: IGU_NORM_NDSB_NUM_SEGS
;
6889 for (sb_idx
= 0; sb_idx
< bp
->igu_sb_cnt
; sb_idx
++) {
6890 prod_offset
= (bp
->igu_base_sb
+ sb_idx
) *
6893 for (i
= 0; i
< num_segs
; i
++) {
6894 addr
= IGU_REG_PROD_CONS_MEMORY
+
6895 (prod_offset
+ i
) * 4;
6896 REG_WR(bp
, addr
, 0);
6898 /* send consumer update with value 0 */
6899 bnx2x_ack_sb(bp
, bp
->igu_base_sb
+ sb_idx
,
6900 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6901 bnx2x_igu_clear_sb(bp
,
6902 bp
->igu_base_sb
+ sb_idx
);
6905 /* default-status-blocks */
6906 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
6907 IGU_BC_DSB_NUM_SEGS
: IGU_NORM_DSB_NUM_SEGS
;
6909 if (CHIP_MODE_IS_4_PORT(bp
))
6910 dsb_idx
= BP_FUNC(bp
);
6912 dsb_idx
= BP_VN(bp
);
6914 prod_offset
= (CHIP_INT_MODE_IS_BC(bp
) ?
6915 IGU_BC_BASE_DSB_PROD
+ dsb_idx
:
6916 IGU_NORM_BASE_DSB_PROD
+ dsb_idx
);
6919 * igu prods come in chunks of E1HVN_MAX (4) -
6920 * does not matters what is the current chip mode
6922 for (i
= 0; i
< (num_segs
* E1HVN_MAX
);
6924 addr
= IGU_REG_PROD_CONS_MEMORY
+
6925 (prod_offset
+ i
)*4;
6926 REG_WR(bp
, addr
, 0);
6928 /* send consumer update with 0 */
6929 if (CHIP_INT_MODE_IS_BC(bp
)) {
6930 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6931 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6932 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6933 CSTORM_ID
, 0, IGU_INT_NOP
, 1);
6934 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6935 XSTORM_ID
, 0, IGU_INT_NOP
, 1);
6936 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6937 TSTORM_ID
, 0, IGU_INT_NOP
, 1);
6938 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6939 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
6941 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6942 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6943 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6944 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
6946 bnx2x_igu_clear_sb(bp
, bp
->igu_dsb_id
);
6948 /* !!! these should become driver const once
6949 rf-tool supports split-68 const */
6950 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_LSB
, 0);
6951 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_MSB
, 0);
6952 REG_WR(bp
, IGU_REG_SB_MASK_LSB
, 0);
6953 REG_WR(bp
, IGU_REG_SB_MASK_MSB
, 0);
6954 REG_WR(bp
, IGU_REG_PBA_STATUS_LSB
, 0);
6955 REG_WR(bp
, IGU_REG_PBA_STATUS_MSB
, 0);
6959 /* Reset PCIE errors for debug */
6960 REG_WR(bp
, 0x2114, 0xffffffff);
6961 REG_WR(bp
, 0x2120, 0xffffffff);
6963 if (CHIP_IS_E1x(bp
)) {
6964 main_mem_size
= HC_REG_MAIN_MEMORY_SIZE
/ 2; /*dwords*/
6965 main_mem_base
= HC_REG_MAIN_MEMORY
+
6966 BP_PORT(bp
) * (main_mem_size
* 4);
6967 main_mem_prty_clr
= HC_REG_HC_PRTY_STS_CLR
;
6970 val
= REG_RD(bp
, main_mem_prty_clr
);
6972 DP(BNX2X_MSG_MCP
, "Hmmm... Parity errors in HC "
6974 "function init (0x%x)!\n", val
);
6976 /* Clear "false" parity errors in MSI-X table */
6977 for (i
= main_mem_base
;
6978 i
< main_mem_base
+ main_mem_size
* 4;
6979 i
+= main_mem_width
) {
6980 bnx2x_read_dmae(bp
, i
, main_mem_width
/ 4);
6981 bnx2x_write_dmae(bp
, bnx2x_sp_mapping(bp
, wb_data
),
6982 i
, main_mem_width
/ 4);
6984 /* Clear HC parity attention */
6985 REG_RD(bp
, main_mem_prty_clr
);
6988 #ifdef BNX2X_STOP_ON_ERROR
6989 /* Enable STORMs SP logging */
6990 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
6991 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6992 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
6993 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6994 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
6995 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6996 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+
6997 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7000 bnx2x_phy_probe(&bp
->link_params
);
7006 void bnx2x_free_mem(struct bnx2x
*bp
)
7009 bnx2x_free_fp_mem(bp
);
7010 /* end of fastpath */
7012 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
7013 sizeof(struct host_sp_status_block
));
7015 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
7016 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
7018 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
7019 sizeof(struct bnx2x_slowpath
));
7021 BNX2X_PCI_FREE(bp
->context
.vcxt
, bp
->context
.cxt_mapping
,
7024 bnx2x_ilt_mem_op(bp
, ILT_MEMOP_FREE
);
7026 BNX2X_FREE(bp
->ilt
->lines
);
7029 if (!CHIP_IS_E1x(bp
))
7030 BNX2X_PCI_FREE(bp
->cnic_sb
.e2_sb
, bp
->cnic_sb_mapping
,
7031 sizeof(struct host_hc_status_block_e2
));
7033 BNX2X_PCI_FREE(bp
->cnic_sb
.e1x_sb
, bp
->cnic_sb_mapping
,
7034 sizeof(struct host_hc_status_block_e1x
));
7036 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
7039 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
7041 BNX2X_PCI_FREE(bp
->eq_ring
, bp
->eq_mapping
,
7042 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
7045 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x
*bp
)
7048 int is_fcoe_stats
= NO_FCOE(bp
) ? 0 : 1;
7050 /* number of queues for statistics is number of eth queues + FCoE */
7051 u8 num_queue_stats
= BNX2X_NUM_ETH_QUEUES(bp
) + is_fcoe_stats
;
7053 /* Total number of FW statistics requests =
7054 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7057 bp
->fw_stats_num
= 2 + is_fcoe_stats
+ num_queue_stats
;
7060 /* Request is built from stats_query_header and an array of
7061 * stats_query_cmd_group each of which contains
7062 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7063 * configured in the stats_query_header.
7065 num_groups
= ((bp
->fw_stats_num
) / STATS_QUERY_CMD_COUNT
) +
7066 (((bp
->fw_stats_num
) % STATS_QUERY_CMD_COUNT
) ? 1 : 0);
7068 bp
->fw_stats_req_sz
= sizeof(struct stats_query_header
) +
7069 num_groups
* sizeof(struct stats_query_cmd_group
);
7071 /* Data for statistics requests + stats_conter
7073 * stats_counter holds per-STORM counters that are incremented
7074 * when STORM has finished with the current request.
7076 * memory for FCoE offloaded statistics are counted anyway,
7077 * even if they will not be sent.
7079 bp
->fw_stats_data_sz
= sizeof(struct per_port_stats
) +
7080 sizeof(struct per_pf_stats
) +
7081 sizeof(struct fcoe_statistics_params
) +
7082 sizeof(struct per_queue_stats
) * num_queue_stats
+
7083 sizeof(struct stats_counter
);
7085 BNX2X_PCI_ALLOC(bp
->fw_stats
, &bp
->fw_stats_mapping
,
7086 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
7089 bp
->fw_stats_req
= (struct bnx2x_fw_stats_req
*)bp
->fw_stats
;
7090 bp
->fw_stats_req_mapping
= bp
->fw_stats_mapping
;
7092 bp
->fw_stats_data
= (struct bnx2x_fw_stats_data
*)
7093 ((u8
*)bp
->fw_stats
+ bp
->fw_stats_req_sz
);
7095 bp
->fw_stats_data_mapping
= bp
->fw_stats_mapping
+
7096 bp
->fw_stats_req_sz
;
7100 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
7101 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
7106 int bnx2x_alloc_mem(struct bnx2x
*bp
)
7109 if (!CHIP_IS_E1x(bp
))
7110 /* size = the status block + ramrod buffers */
7111 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e2_sb
, &bp
->cnic_sb_mapping
,
7112 sizeof(struct host_hc_status_block_e2
));
7114 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e1x_sb
, &bp
->cnic_sb_mapping
,
7115 sizeof(struct host_hc_status_block_e1x
));
7117 /* allocate searcher T2 table */
7118 BNX2X_PCI_ALLOC(bp
->t2
, &bp
->t2_mapping
, SRC_T2_SZ
);
7122 BNX2X_PCI_ALLOC(bp
->def_status_blk
, &bp
->def_status_blk_mapping
,
7123 sizeof(struct host_sp_status_block
));
7125 BNX2X_PCI_ALLOC(bp
->slowpath
, &bp
->slowpath_mapping
,
7126 sizeof(struct bnx2x_slowpath
));
7129 /* write address to which L5 should insert its values */
7130 bp
->cnic_eth_dev
.addr_drv_info_to_mcp
= &bp
->slowpath
->drv_info_to_mcp
;
7133 /* Allocated memory for FW statistics */
7134 if (bnx2x_alloc_fw_stats_mem(bp
))
7137 bp
->context
.size
= sizeof(union cdu_context
) * BNX2X_L2_CID_COUNT(bp
);
7139 BNX2X_PCI_ALLOC(bp
->context
.vcxt
, &bp
->context
.cxt_mapping
,
7142 BNX2X_ALLOC(bp
->ilt
->lines
, sizeof(struct ilt_line
) * ILT_MAX_LINES
);
7144 if (bnx2x_ilt_mem_op(bp
, ILT_MEMOP_ALLOC
))
7147 /* Slow path ring */
7148 BNX2X_PCI_ALLOC(bp
->spq
, &bp
->spq_mapping
, BCM_PAGE_SIZE
);
7151 BNX2X_PCI_ALLOC(bp
->eq_ring
, &bp
->eq_mapping
,
7152 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
7156 /* need to be done at the end, since it's self adjusting to amount
7157 * of memory available for RSS queues
7159 if (bnx2x_alloc_fp_mem(bp
))
7169 * Init service functions
7172 int bnx2x_set_mac_one(struct bnx2x
*bp
, u8
*mac
,
7173 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
7174 int mac_type
, unsigned long *ramrod_flags
)
7177 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
7179 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
7181 /* Fill general parameters */
7182 ramrod_param
.vlan_mac_obj
= obj
;
7183 ramrod_param
.ramrod_flags
= *ramrod_flags
;
7185 /* Fill a user request section if needed */
7186 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
7187 memcpy(ramrod_param
.user_req
.u
.mac
.mac
, mac
, ETH_ALEN
);
7189 __set_bit(mac_type
, &ramrod_param
.user_req
.vlan_mac_flags
);
7191 /* Set the command: ADD or DEL */
7193 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
7195 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
7198 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
7200 BNX2X_ERR("%s MAC failed\n", (set
? "Set" : "Del"));
7204 int bnx2x_del_all_macs(struct bnx2x
*bp
,
7205 struct bnx2x_vlan_mac_obj
*mac_obj
,
7206 int mac_type
, bool wait_for_comp
)
7209 unsigned long ramrod_flags
= 0, vlan_mac_flags
= 0;
7211 /* Wait for completion of requested */
7213 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7215 /* Set the mac type of addresses we want to clear */
7216 __set_bit(mac_type
, &vlan_mac_flags
);
7218 rc
= mac_obj
->delete_all(bp
, mac_obj
, &vlan_mac_flags
, &ramrod_flags
);
7220 BNX2X_ERR("Failed to delete MACs: %d\n", rc
);
7225 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
)
7227 unsigned long ramrod_flags
= 0;
7230 if (is_zero_ether_addr(bp
->dev
->dev_addr
) && IS_MF_ISCSI_SD(bp
)) {
7231 DP(NETIF_MSG_IFUP
, "Ignoring Zero MAC for iSCSI SD mode\n");
7236 DP(NETIF_MSG_IFUP
, "Adding Eth MAC\n");
7238 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7239 /* Eth MAC is set on RSS leading client (fp[0]) */
7240 return bnx2x_set_mac_one(bp
, bp
->dev
->dev_addr
, &bp
->fp
->mac_obj
, set
,
7241 BNX2X_ETH_MAC
, &ramrod_flags
);
7244 int bnx2x_setup_leading(struct bnx2x
*bp
)
7246 return bnx2x_setup_queue(bp
, &bp
->fp
[0], 1);
7250 * bnx2x_set_int_mode - configure interrupt mode
7252 * @bp: driver handle
7254 * In case of MSI-X it will also try to enable MSI-X.
7256 static void __devinit
bnx2x_set_int_mode(struct bnx2x
*bp
)
7260 bnx2x_enable_msi(bp
);
7261 /* falling through... */
7263 bp
->num_queues
= 1 + NON_ETH_CONTEXT_USE
;
7264 DP(NETIF_MSG_IFUP
, "set number of queues to 1\n");
7267 /* Set number of queues according to bp->multi_mode value */
7268 bnx2x_set_num_queues(bp
);
7270 DP(NETIF_MSG_IFUP
, "set number of queues to %d\n",
7273 /* if we can't use MSI-X we only need one fp,
7274 * so try to enable MSI-X with the requested number of fp's
7275 * and fallback to MSI or legacy INTx with one fp
7277 if (bnx2x_enable_msix(bp
)) {
7278 /* failed to enable MSI-X */
7281 "Multi requested but failed to "
7282 "enable MSI-X (%d), "
7283 "set number of queues to %d\n",
7285 1 + NON_ETH_CONTEXT_USE
);
7286 bp
->num_queues
= 1 + NON_ETH_CONTEXT_USE
;
7288 /* Try to enable MSI */
7289 if (!(bp
->flags
& DISABLE_MSI_FLAG
))
7290 bnx2x_enable_msi(bp
);
7296 /* must be called prioir to any HW initializations */
7297 static inline u16
bnx2x_cid_ilt_lines(struct bnx2x
*bp
)
7299 return L2_ILT_LINES(bp
);
7302 void bnx2x_ilt_set_info(struct bnx2x
*bp
)
7304 struct ilt_client_info
*ilt_client
;
7305 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7308 ilt
->start_line
= FUNC_ILT_BASE(BP_FUNC(bp
));
7309 DP(BNX2X_MSG_SP
, "ilt starts at line %d\n", ilt
->start_line
);
7312 ilt_client
= &ilt
->clients
[ILT_CLIENT_CDU
];
7313 ilt_client
->client_num
= ILT_CLIENT_CDU
;
7314 ilt_client
->page_size
= CDU_ILT_PAGE_SZ
;
7315 ilt_client
->flags
= ILT_CLIENT_SKIP_MEM
;
7316 ilt_client
->start
= line
;
7317 line
+= bnx2x_cid_ilt_lines(bp
);
7319 line
+= CNIC_ILT_LINES
;
7321 ilt_client
->end
= line
- 1;
7323 DP(BNX2X_MSG_SP
, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7324 "flags 0x%x, hw psz %d\n",
7327 ilt_client
->page_size
,
7329 ilog2(ilt_client
->page_size
>> 12));
7332 if (QM_INIT(bp
->qm_cid_count
)) {
7333 ilt_client
= &ilt
->clients
[ILT_CLIENT_QM
];
7334 ilt_client
->client_num
= ILT_CLIENT_QM
;
7335 ilt_client
->page_size
= QM_ILT_PAGE_SZ
;
7336 ilt_client
->flags
= 0;
7337 ilt_client
->start
= line
;
7339 /* 4 bytes for each cid */
7340 line
+= DIV_ROUND_UP(bp
->qm_cid_count
* QM_QUEUES_PER_FUNC
* 4,
7343 ilt_client
->end
= line
- 1;
7345 DP(BNX2X_MSG_SP
, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7346 "flags 0x%x, hw psz %d\n",
7349 ilt_client
->page_size
,
7351 ilog2(ilt_client
->page_size
>> 12));
7355 ilt_client
= &ilt
->clients
[ILT_CLIENT_SRC
];
7357 ilt_client
->client_num
= ILT_CLIENT_SRC
;
7358 ilt_client
->page_size
= SRC_ILT_PAGE_SZ
;
7359 ilt_client
->flags
= 0;
7360 ilt_client
->start
= line
;
7361 line
+= SRC_ILT_LINES
;
7362 ilt_client
->end
= line
- 1;
7364 DP(BNX2X_MSG_SP
, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7365 "flags 0x%x, hw psz %d\n",
7368 ilt_client
->page_size
,
7370 ilog2(ilt_client
->page_size
>> 12));
7373 ilt_client
->flags
= (ILT_CLIENT_SKIP_INIT
| ILT_CLIENT_SKIP_MEM
);
7377 ilt_client
= &ilt
->clients
[ILT_CLIENT_TM
];
7379 ilt_client
->client_num
= ILT_CLIENT_TM
;
7380 ilt_client
->page_size
= TM_ILT_PAGE_SZ
;
7381 ilt_client
->flags
= 0;
7382 ilt_client
->start
= line
;
7383 line
+= TM_ILT_LINES
;
7384 ilt_client
->end
= line
- 1;
7386 DP(BNX2X_MSG_SP
, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7387 "flags 0x%x, hw psz %d\n",
7390 ilt_client
->page_size
,
7392 ilog2(ilt_client
->page_size
>> 12));
7395 ilt_client
->flags
= (ILT_CLIENT_SKIP_INIT
| ILT_CLIENT_SKIP_MEM
);
7397 BUG_ON(line
> ILT_MAX_LINES
);
7401 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7403 * @bp: driver handle
7404 * @fp: pointer to fastpath
7405 * @init_params: pointer to parameters structure
7407 * parameters configured:
7408 * - HC configuration
7409 * - Queue's CDU context
7411 static inline void bnx2x_pf_q_prep_init(struct bnx2x
*bp
,
7412 struct bnx2x_fastpath
*fp
, struct bnx2x_queue_init_params
*init_params
)
7416 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7417 if (!IS_FCOE_FP(fp
)) {
7418 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->rx
.flags
);
7419 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->tx
.flags
);
7421 /* If HC is supporterd, enable host coalescing in the transition
7424 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->rx
.flags
);
7425 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->tx
.flags
);
7428 init_params
->rx
.hc_rate
= bp
->rx_ticks
?
7429 (1000000 / bp
->rx_ticks
) : 0;
7430 init_params
->tx
.hc_rate
= bp
->tx_ticks
?
7431 (1000000 / bp
->tx_ticks
) : 0;
7434 init_params
->rx
.fw_sb_id
= init_params
->tx
.fw_sb_id
=
7438 * CQ index among the SB indices: FCoE clients uses the default
7439 * SB, therefore it's different.
7441 init_params
->rx
.sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
7442 init_params
->tx
.sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
;
7445 /* set maximum number of COSs supported by this queue */
7446 init_params
->max_cos
= fp
->max_cos
;
7448 DP(BNX2X_MSG_SP
, "fp: %d setting queue params max cos to: %d\n",
7449 fp
->index
, init_params
->max_cos
);
7451 /* set the context pointers queue object */
7452 for (cos
= FIRST_TX_COS_INDEX
; cos
< init_params
->max_cos
; cos
++)
7453 init_params
->cxts
[cos
] =
7454 &bp
->context
.vcxt
[fp
->txdata
[cos
].cid
].eth
;
7457 int bnx2x_setup_tx_only(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
7458 struct bnx2x_queue_state_params
*q_params
,
7459 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
,
7460 int tx_index
, bool leading
)
7462 memset(tx_only_params
, 0, sizeof(*tx_only_params
));
7464 /* Set the command */
7465 q_params
->cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
7467 /* Set tx-only QUEUE flags: don't zero statistics */
7468 tx_only_params
->flags
= bnx2x_get_common_flags(bp
, fp
, false);
7470 /* choose the index of the cid to send the slow path on */
7471 tx_only_params
->cid_index
= tx_index
;
7473 /* Set general TX_ONLY_SETUP parameters */
7474 bnx2x_pf_q_prep_general(bp
, fp
, &tx_only_params
->gen_params
, tx_index
);
7476 /* Set Tx TX_ONLY_SETUP parameters */
7477 bnx2x_pf_tx_q_prep(bp
, fp
, &tx_only_params
->txq_params
, tx_index
);
7479 DP(BNX2X_MSG_SP
, "preparing to send tx-only ramrod for connection:"
7480 "cos %d, primary cid %d, cid %d, "
7481 "client id %d, sp-client id %d, flags %lx\n",
7482 tx_index
, q_params
->q_obj
->cids
[FIRST_TX_COS_INDEX
],
7483 q_params
->q_obj
->cids
[tx_index
], q_params
->q_obj
->cl_id
,
7484 tx_only_params
->gen_params
.spcl_id
, tx_only_params
->flags
);
7486 /* send the ramrod */
7487 return bnx2x_queue_state_change(bp
, q_params
);
7492 * bnx2x_setup_queue - setup queue
7494 * @bp: driver handle
7495 * @fp: pointer to fastpath
7496 * @leading: is leading
7498 * This function performs 2 steps in a Queue state machine
7499 * actually: 1) RESET->INIT 2) INIT->SETUP
7502 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
7505 struct bnx2x_queue_state_params q_params
= {0};
7506 struct bnx2x_queue_setup_params
*setup_params
=
7507 &q_params
.params
.setup
;
7508 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
7509 &q_params
.params
.tx_only
;
7513 DP(BNX2X_MSG_SP
, "setting up queue %d\n", fp
->index
);
7515 /* reset IGU state skip FCoE L2 queue */
7516 if (!IS_FCOE_FP(fp
))
7517 bnx2x_ack_sb(bp
, fp
->igu_sb_id
, USTORM_ID
, 0,
7520 q_params
.q_obj
= &fp
->q_obj
;
7521 /* We want to wait for completion in this context */
7522 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
7524 /* Prepare the INIT parameters */
7525 bnx2x_pf_q_prep_init(bp
, fp
, &q_params
.params
.init
);
7527 /* Set the command */
7528 q_params
.cmd
= BNX2X_Q_CMD_INIT
;
7530 /* Change the state to INIT */
7531 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7533 BNX2X_ERR("Queue(%d) INIT failed\n", fp
->index
);
7537 DP(BNX2X_MSG_SP
, "init complete\n");
7540 /* Now move the Queue to the SETUP state... */
7541 memset(setup_params
, 0, sizeof(*setup_params
));
7543 /* Set QUEUE flags */
7544 setup_params
->flags
= bnx2x_get_q_flags(bp
, fp
, leading
);
7546 /* Set general SETUP parameters */
7547 bnx2x_pf_q_prep_general(bp
, fp
, &setup_params
->gen_params
,
7548 FIRST_TX_COS_INDEX
);
7550 bnx2x_pf_rx_q_prep(bp
, fp
, &setup_params
->pause_params
,
7551 &setup_params
->rxq_params
);
7553 bnx2x_pf_tx_q_prep(bp
, fp
, &setup_params
->txq_params
,
7554 FIRST_TX_COS_INDEX
);
7556 /* Set the command */
7557 q_params
.cmd
= BNX2X_Q_CMD_SETUP
;
7559 /* Change the state to SETUP */
7560 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7562 BNX2X_ERR("Queue(%d) SETUP failed\n", fp
->index
);
7566 /* loop through the relevant tx-only indices */
7567 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
7568 tx_index
< fp
->max_cos
;
7571 /* prepare and send tx-only ramrod*/
7572 rc
= bnx2x_setup_tx_only(bp
, fp
, &q_params
,
7573 tx_only_params
, tx_index
, leading
);
7575 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7576 fp
->index
, tx_index
);
7584 static int bnx2x_stop_queue(struct bnx2x
*bp
, int index
)
7586 struct bnx2x_fastpath
*fp
= &bp
->fp
[index
];
7587 struct bnx2x_fp_txdata
*txdata
;
7588 struct bnx2x_queue_state_params q_params
= {0};
7591 DP(BNX2X_MSG_SP
, "stopping queue %d cid %d\n", index
, fp
->cid
);
7593 q_params
.q_obj
= &fp
->q_obj
;
7594 /* We want to wait for completion in this context */
7595 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
7598 /* close tx-only connections */
7599 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
7600 tx_index
< fp
->max_cos
;
7603 /* ascertain this is a normal queue*/
7604 txdata
= &fp
->txdata
[tx_index
];
7606 DP(BNX2X_MSG_SP
, "stopping tx-only queue %d\n",
7609 /* send halt terminate on tx-only connection */
7610 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
7611 memset(&q_params
.params
.terminate
, 0,
7612 sizeof(q_params
.params
.terminate
));
7613 q_params
.params
.terminate
.cid_index
= tx_index
;
7615 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7619 /* send halt terminate on tx-only connection */
7620 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
7621 memset(&q_params
.params
.cfc_del
, 0,
7622 sizeof(q_params
.params
.cfc_del
));
7623 q_params
.params
.cfc_del
.cid_index
= tx_index
;
7624 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7628 /* Stop the primary connection: */
7629 /* ...halt the connection */
7630 q_params
.cmd
= BNX2X_Q_CMD_HALT
;
7631 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7635 /* ...terminate the connection */
7636 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
7637 memset(&q_params
.params
.terminate
, 0,
7638 sizeof(q_params
.params
.terminate
));
7639 q_params
.params
.terminate
.cid_index
= FIRST_TX_COS_INDEX
;
7640 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7643 /* ...delete cfc entry */
7644 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
7645 memset(&q_params
.params
.cfc_del
, 0,
7646 sizeof(q_params
.params
.cfc_del
));
7647 q_params
.params
.cfc_del
.cid_index
= FIRST_TX_COS_INDEX
;
7648 return bnx2x_queue_state_change(bp
, &q_params
);
7652 static void bnx2x_reset_func(struct bnx2x
*bp
)
7654 int port
= BP_PORT(bp
);
7655 int func
= BP_FUNC(bp
);
7658 /* Disable the function in the FW */
7659 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(func
), 0);
7660 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(func
), 0);
7661 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(func
), 0);
7662 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(func
), 0);
7665 for_each_eth_queue(bp
, i
) {
7666 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
7667 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7668 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp
->fw_sb_id
),
7674 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7675 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp
)),
7679 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7680 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func
),
7683 for (i
= 0; i
< XSTORM_SPQ_DATA_SIZE
/ 4; i
++)
7684 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_DATA_OFFSET(func
),
7688 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7689 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7690 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7692 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
7693 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
7697 /* Disable Timer scan */
7698 REG_WR(bp
, TM_REG_EN_LINEAR0_TIMER
+ port
*4, 0);
7700 * Wait for at least 10ms and up to 2 second for the timers scan to
7703 for (i
= 0; i
< 200; i
++) {
7705 if (!REG_RD(bp
, TM_REG_LIN0_SCAN_ON
+ port
*4))
7710 bnx2x_clear_func_ilt(bp
, func
);
7712 /* Timers workaround bug for E2: if this is vnic-3,
7713 * we need to set the entire ilt range for this timers.
7715 if (!CHIP_IS_E1x(bp
) && BP_VN(bp
) == 3) {
7716 struct ilt_client_info ilt_cli
;
7717 /* use dummy TM client */
7718 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
7720 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
7721 ilt_cli
.client_num
= ILT_CLIENT_TM
;
7723 bnx2x_ilt_boundry_init_op(bp
, &ilt_cli
, 0, INITOP_CLEAR
);
7726 /* this assumes that reset_port() called before reset_func()*/
7727 if (!CHIP_IS_E1x(bp
))
7728 bnx2x_pf_disable(bp
);
7733 static void bnx2x_reset_port(struct bnx2x
*bp
)
7735 int port
= BP_PORT(bp
);
7738 /* Reset physical Link */
7739 bnx2x__link_reset(bp
);
7741 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
7743 /* Do not rcv packets to BRB */
7744 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
7745 /* Do not direct rcv packets that are not for MCP to the BRB */
7746 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
7747 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
7750 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
7753 /* Check for BRB port occupancy */
7754 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
7756 DP(NETIF_MSG_IFDOWN
,
7757 "BRB1 is not empty %d blocks are occupied\n", val
);
7759 /* TODO: Close Doorbell port? */
7762 static inline int bnx2x_reset_hw(struct bnx2x
*bp
, u32 load_code
)
7764 struct bnx2x_func_state_params func_params
= {0};
7766 /* Prepare parameters for function state transitions */
7767 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7769 func_params
.f_obj
= &bp
->func_obj
;
7770 func_params
.cmd
= BNX2X_F_CMD_HW_RESET
;
7772 func_params
.params
.hw_init
.load_phase
= load_code
;
7774 return bnx2x_func_state_change(bp
, &func_params
);
7777 static inline int bnx2x_func_stop(struct bnx2x
*bp
)
7779 struct bnx2x_func_state_params func_params
= {0};
7782 /* Prepare parameters for function state transitions */
7783 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7784 func_params
.f_obj
= &bp
->func_obj
;
7785 func_params
.cmd
= BNX2X_F_CMD_STOP
;
7788 * Try to stop the function the 'good way'. If fails (in case
7789 * of a parity error during bnx2x_chip_cleanup()) and we are
7790 * not in a debug mode, perform a state transaction in order to
7791 * enable further HW_RESET transaction.
7793 rc
= bnx2x_func_state_change(bp
, &func_params
);
7795 #ifdef BNX2X_STOP_ON_ERROR
7798 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7800 __set_bit(RAMROD_DRV_CLR_ONLY
, &func_params
.ramrod_flags
);
7801 return bnx2x_func_state_change(bp
, &func_params
);
7809 * bnx2x_send_unload_req - request unload mode from the MCP.
7811 * @bp: driver handle
7812 * @unload_mode: requested function's unload mode
7814 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7816 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
)
7819 int port
= BP_PORT(bp
);
7821 /* Select the UNLOAD request mode */
7822 if (unload_mode
== UNLOAD_NORMAL
)
7823 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
7825 else if (bp
->flags
& NO_WOL_FLAG
)
7826 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
7829 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
7830 u8
*mac_addr
= bp
->dev
->dev_addr
;
7834 /* The mac address is written to entries 1-4 to
7835 * preserve entry 0 which is used by the PMF
7837 u8 entry
= (BP_VN(bp
) + 1)*8;
7839 val
= (mac_addr
[0] << 8) | mac_addr
[1];
7840 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
7842 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
7843 (mac_addr
[4] << 8) | mac_addr
[5];
7844 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
7846 /* Enable the PME and clear the status */
7847 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, &pmc
);
7848 pmc
|= PCI_PM_CTRL_PME_ENABLE
| PCI_PM_CTRL_PME_STATUS
;
7849 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, pmc
);
7851 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
7854 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
7856 /* Send the request to the MCP */
7858 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
7860 int path
= BP_PATH(bp
);
7862 DP(NETIF_MSG_IFDOWN
, "NO MCP - load counts[%d] "
7864 path
, load_count
[path
][0], load_count
[path
][1],
7865 load_count
[path
][2]);
7866 load_count
[path
][0]--;
7867 load_count
[path
][1 + port
]--;
7868 DP(NETIF_MSG_IFDOWN
, "NO MCP - new load counts[%d] "
7870 path
, load_count
[path
][0], load_count
[path
][1],
7871 load_count
[path
][2]);
7872 if (load_count
[path
][0] == 0)
7873 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
7874 else if (load_count
[path
][1 + port
] == 0)
7875 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
7877 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
7884 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7886 * @bp: driver handle
7888 void bnx2x_send_unload_done(struct bnx2x
*bp
)
7890 /* Report UNLOAD_DONE to MCP */
7892 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
7895 static inline int bnx2x_func_wait_started(struct bnx2x
*bp
)
7898 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
7904 * (assumption: No Attention from MCP at this stage)
7905 * PMF probably in the middle of TXdisable/enable transaction
7906 * 1. Sync IRS for default SB
7907 * 2. Sync SP queue - this guarantes us that attention handling started
7908 * 3. Wait, that TXdisable/enable transaction completes
7910 * 1+2 guranty that if DCBx attention was scheduled it already changed
7911 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7912 * received complettion for the transaction the state is TX_STOPPED.
7913 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7917 /* make sure default SB ISR is done */
7919 synchronize_irq(bp
->msix_table
[0].vector
);
7921 synchronize_irq(bp
->pdev
->irq
);
7923 flush_workqueue(bnx2x_wq
);
7925 while (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
7926 BNX2X_F_STATE_STARTED
&& tout
--)
7929 if (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
7930 BNX2X_F_STATE_STARTED
) {
7931 #ifdef BNX2X_STOP_ON_ERROR
7935 * Failed to complete the transaction in a "good way"
7936 * Force both transactions with CLR bit
7938 struct bnx2x_func_state_params func_params
= {0};
7940 DP(BNX2X_MSG_SP
, "Hmmm... unexpected function state! "
7941 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7943 func_params
.f_obj
= &bp
->func_obj
;
7944 __set_bit(RAMROD_DRV_CLR_ONLY
,
7945 &func_params
.ramrod_flags
);
7947 /* STARTED-->TX_ST0PPED */
7948 func_params
.cmd
= BNX2X_F_CMD_TX_STOP
;
7949 bnx2x_func_state_change(bp
, &func_params
);
7951 /* TX_ST0PPED-->STARTED */
7952 func_params
.cmd
= BNX2X_F_CMD_TX_START
;
7953 return bnx2x_func_state_change(bp
, &func_params
);
7960 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
)
7962 int port
= BP_PORT(bp
);
7965 struct bnx2x_mcast_ramrod_params rparam
= {0};
7968 /* Wait until tx fastpath tasks complete */
7969 for_each_tx_queue(bp
, i
) {
7970 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
7972 for_each_cos_in_tx_queue(fp
, cos
)
7973 rc
= bnx2x_clean_tx_queue(bp
, &fp
->txdata
[cos
]);
7974 #ifdef BNX2X_STOP_ON_ERROR
7980 /* Give HW time to discard old tx messages */
7981 usleep_range(1000, 1000);
7983 /* Clean all ETH MACs */
7984 rc
= bnx2x_del_all_macs(bp
, &bp
->fp
[0].mac_obj
, BNX2X_ETH_MAC
, false);
7986 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc
);
7988 /* Clean up UC list */
7989 rc
= bnx2x_del_all_macs(bp
, &bp
->fp
[0].mac_obj
, BNX2X_UC_LIST_MAC
,
7992 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7996 if (!CHIP_IS_E1(bp
))
7997 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
7999 /* Set "drop all" (stop Rx).
8000 * We need to take a netif_addr_lock() here in order to prevent
8001 * a race between the completion code and this code.
8003 netif_addr_lock_bh(bp
->dev
);
8004 /* Schedule the rx_mode command */
8005 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
8006 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
8008 bnx2x_set_storm_rx_mode(bp
);
8010 /* Cleanup multicast configuration */
8011 rparam
.mcast_obj
= &bp
->mcast_obj
;
8012 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
8014 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc
);
8016 netif_addr_unlock_bh(bp
->dev
);
8021 * Send the UNLOAD_REQUEST to the MCP. This will return if
8022 * this function should perform FUNC, PORT or COMMON HW
8025 reset_code
= bnx2x_send_unload_req(bp
, unload_mode
);
8028 * (assumption: No Attention from MCP at this stage)
8029 * PMF probably in the middle of TXdisable/enable transaction
8031 rc
= bnx2x_func_wait_started(bp
);
8033 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8034 #ifdef BNX2X_STOP_ON_ERROR
8039 /* Close multi and leading connections
8040 * Completions for ramrods are collected in a synchronous way
8042 for_each_queue(bp
, i
)
8043 if (bnx2x_stop_queue(bp
, i
))
8044 #ifdef BNX2X_STOP_ON_ERROR
8049 /* If SP settings didn't get completed so far - something
8050 * very wrong has happen.
8052 if (!bnx2x_wait_sp_comp(bp
, ~0x0UL
))
8053 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8055 #ifndef BNX2X_STOP_ON_ERROR
8058 rc
= bnx2x_func_stop(bp
);
8060 BNX2X_ERR("Function stop failed!\n");
8061 #ifdef BNX2X_STOP_ON_ERROR
8066 /* Disable HW interrupts, NAPI */
8067 bnx2x_netif_stop(bp
, 1);
8072 /* Reset the chip */
8073 rc
= bnx2x_reset_hw(bp
, reset_code
);
8075 BNX2X_ERR("HW_RESET failed\n");
8078 /* Report UNLOAD_DONE to MCP */
8079 bnx2x_send_unload_done(bp
);
8082 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
)
8086 DP(NETIF_MSG_HW
, "Disabling \"close the gates\"\n");
8088 if (CHIP_IS_E1(bp
)) {
8089 int port
= BP_PORT(bp
);
8090 u32 addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
8091 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
8093 val
= REG_RD(bp
, addr
);
8095 REG_WR(bp
, addr
, val
);
8097 val
= REG_RD(bp
, MISC_REG_AEU_GENERAL_MASK
);
8098 val
&= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
|
8099 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
);
8100 REG_WR(bp
, MISC_REG_AEU_GENERAL_MASK
, val
);
8104 /* Close gates #2, #3 and #4: */
8105 static void bnx2x_set_234_gates(struct bnx2x
*bp
, bool close
)
8109 /* Gates #2 and #4a are closed/opened for "not E1" only */
8110 if (!CHIP_IS_E1(bp
)) {
8112 REG_WR(bp
, PXP_REG_HST_DISCARD_DOORBELLS
, !!close
);
8114 REG_WR(bp
, PXP_REG_HST_DISCARD_INTERNAL_WRITES
, !!close
);
8118 if (CHIP_IS_E1x(bp
)) {
8119 /* Prevent interrupts from HC on both ports */
8120 val
= REG_RD(bp
, HC_REG_CONFIG_1
);
8121 REG_WR(bp
, HC_REG_CONFIG_1
,
8122 (!close
) ? (val
| HC_CONFIG_1_REG_BLOCK_DISABLE_1
) :
8123 (val
& ~(u32
)HC_CONFIG_1_REG_BLOCK_DISABLE_1
));
8125 val
= REG_RD(bp
, HC_REG_CONFIG_0
);
8126 REG_WR(bp
, HC_REG_CONFIG_0
,
8127 (!close
) ? (val
| HC_CONFIG_0_REG_BLOCK_DISABLE_0
) :
8128 (val
& ~(u32
)HC_CONFIG_0_REG_BLOCK_DISABLE_0
));
8130 /* Prevent incomming interrupts in IGU */
8131 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
8133 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
,
8135 (val
| IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
) :
8136 (val
& ~(u32
)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
));
8139 DP(NETIF_MSG_HW
, "%s gates #2, #3 and #4\n",
8140 close
? "closing" : "opening");
8144 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8146 static void bnx2x_clp_reset_prep(struct bnx2x
*bp
, u32
*magic_val
)
8148 /* Do some magic... */
8149 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
8150 *magic_val
= val
& SHARED_MF_CLP_MAGIC
;
8151 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
, val
| SHARED_MF_CLP_MAGIC
);
8155 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8157 * @bp: driver handle
8158 * @magic_val: old value of the `magic' bit.
8160 static void bnx2x_clp_reset_done(struct bnx2x
*bp
, u32 magic_val
)
8162 /* Restore the `magic' bit value... */
8163 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
8164 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
,
8165 (val
& (~SHARED_MF_CLP_MAGIC
)) | magic_val
);
8169 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8171 * @bp: driver handle
8172 * @magic_val: old value of 'magic' bit.
8174 * Takes care of CLP configurations.
8176 static void bnx2x_reset_mcp_prep(struct bnx2x
*bp
, u32
*magic_val
)
8179 u32 validity_offset
;
8181 DP(NETIF_MSG_HW
, "Starting\n");
8183 /* Set `magic' bit in order to save MF config */
8184 if (!CHIP_IS_E1(bp
))
8185 bnx2x_clp_reset_prep(bp
, magic_val
);
8187 /* Get shmem offset */
8188 shmem
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8189 validity_offset
= offsetof(struct shmem_region
, validity_map
[0]);
8191 /* Clear validity map flags */
8193 REG_WR(bp
, shmem
+ validity_offset
, 0);
8196 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8197 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8200 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8202 * @bp: driver handle
8204 static inline void bnx2x_mcp_wait_one(struct bnx2x
*bp
)
8206 /* special handling for emulation and FPGA,
8207 wait 10 times longer */
8208 if (CHIP_REV_IS_SLOW(bp
))
8209 msleep(MCP_ONE_TIMEOUT
*10);
8211 msleep(MCP_ONE_TIMEOUT
);
8215 * initializes bp->common.shmem_base and waits for validity signature to appear
8217 static int bnx2x_init_shmem(struct bnx2x
*bp
)
8223 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8224 if (bp
->common
.shmem_base
) {
8225 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
8226 if (val
& SHR_MEM_VALIDITY_MB
)
8230 bnx2x_mcp_wait_one(bp
);
8232 } while (cnt
++ < (MCP_TIMEOUT
/ MCP_ONE_TIMEOUT
));
8234 BNX2X_ERR("BAD MCP validity signature\n");
8239 static int bnx2x_reset_mcp_comp(struct bnx2x
*bp
, u32 magic_val
)
8241 int rc
= bnx2x_init_shmem(bp
);
8243 /* Restore the `magic' bit value */
8244 if (!CHIP_IS_E1(bp
))
8245 bnx2x_clp_reset_done(bp
, magic_val
);
8250 static void bnx2x_pxp_prep(struct bnx2x
*bp
)
8252 if (!CHIP_IS_E1(bp
)) {
8253 REG_WR(bp
, PXP2_REG_RD_START_INIT
, 0);
8254 REG_WR(bp
, PXP2_REG_RQ_RBC_DONE
, 0);
8260 * Reset the whole chip except for:
8262 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8265 * - MISC (including AEU)
8269 static void bnx2x_process_kill_chip_reset(struct bnx2x
*bp
, bool global
)
8271 u32 not_reset_mask1
, reset_mask1
, not_reset_mask2
, reset_mask2
;
8272 u32 global_bits2
, stay_reset2
;
8275 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8276 * (per chip) blocks.
8279 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
|
8280 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
;
8282 /* Don't reset the following blocks */
8284 MISC_REGISTERS_RESET_REG_1_RST_HC
|
8285 MISC_REGISTERS_RESET_REG_1_RST_PXPV
|
8286 MISC_REGISTERS_RESET_REG_1_RST_PXP
;
8289 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
|
8290 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
|
8291 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
|
8292 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
|
8293 MISC_REGISTERS_RESET_REG_2_RST_RBCN
|
8294 MISC_REGISTERS_RESET_REG_2_RST_GRC
|
8295 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
|
8296 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
|
8297 MISC_REGISTERS_RESET_REG_2_RST_ATC
|
8298 MISC_REGISTERS_RESET_REG_2_PGLC
;
8301 * Keep the following blocks in reset:
8302 * - all xxMACs are handled by the bnx2x_link code.
8305 MISC_REGISTERS_RESET_REG_2_RST_BMAC0
|
8306 MISC_REGISTERS_RESET_REG_2_RST_BMAC1
|
8307 MISC_REGISTERS_RESET_REG_2_RST_EMAC0
|
8308 MISC_REGISTERS_RESET_REG_2_RST_EMAC1
|
8309 MISC_REGISTERS_RESET_REG_2_UMAC0
|
8310 MISC_REGISTERS_RESET_REG_2_UMAC1
|
8311 MISC_REGISTERS_RESET_REG_2_XMAC
|
8312 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
;
8314 /* Full reset masks according to the chip */
8315 reset_mask1
= 0xffffffff;
8318 reset_mask2
= 0xffff;
8319 else if (CHIP_IS_E1H(bp
))
8320 reset_mask2
= 0x1ffff;
8321 else if (CHIP_IS_E2(bp
))
8322 reset_mask2
= 0xfffff;
8323 else /* CHIP_IS_E3 */
8324 reset_mask2
= 0x3ffffff;
8326 /* Don't reset global blocks unless we need to */
8328 reset_mask2
&= ~global_bits2
;
8331 * In case of attention in the QM, we need to reset PXP
8332 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8333 * because otherwise QM reset would release 'close the gates' shortly
8334 * before resetting the PXP, then the PSWRQ would send a write
8335 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8336 * read the payload data from PSWWR, but PSWWR would not
8337 * respond. The write queue in PGLUE would stuck, dmae commands
8338 * would not return. Therefore it's important to reset the second
8339 * reset register (containing the
8340 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8341 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8344 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
8345 reset_mask2
& (~not_reset_mask2
));
8347 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
8348 reset_mask1
& (~not_reset_mask1
));
8353 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
8354 reset_mask2
& (~stay_reset2
));
8359 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, reset_mask1
);
8364 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8365 * It should get cleared in no more than 1s.
8367 * @bp: driver handle
8369 * It should get cleared in no more than 1s. Returns 0 if
8370 * pending writes bit gets cleared.
8372 static int bnx2x_er_poll_igu_vq(struct bnx2x
*bp
)
8378 pend_bits
= REG_RD(bp
, IGU_REG_PENDING_BITS_STATUS
);
8383 usleep_range(1000, 1000);
8384 } while (cnt
-- > 0);
8387 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8395 static int bnx2x_process_kill(struct bnx2x
*bp
, bool global
)
8399 u32 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
, pgl_exp_rom2
;
8402 /* Empty the Tetris buffer, wait for 1s */
8404 sr_cnt
= REG_RD(bp
, PXP2_REG_RD_SR_CNT
);
8405 blk_cnt
= REG_RD(bp
, PXP2_REG_RD_BLK_CNT
);
8406 port_is_idle_0
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_0
);
8407 port_is_idle_1
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_1
);
8408 pgl_exp_rom2
= REG_RD(bp
, PXP2_REG_PGL_EXP_ROM2
);
8409 if ((sr_cnt
== 0x7e) && (blk_cnt
== 0xa0) &&
8410 ((port_is_idle_0
& 0x1) == 0x1) &&
8411 ((port_is_idle_1
& 0x1) == 0x1) &&
8412 (pgl_exp_rom2
== 0xffffffff))
8414 usleep_range(1000, 1000);
8415 } while (cnt
-- > 0);
8418 DP(NETIF_MSG_HW
, "Tetris buffer didn't get empty or there"
8420 " outstanding read requests after 1s!\n");
8421 DP(NETIF_MSG_HW
, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8422 " port_is_idle_0=0x%08x,"
8423 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8424 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
,
8431 /* Close gates #2, #3 and #4 */
8432 bnx2x_set_234_gates(bp
, true);
8434 /* Poll for IGU VQs for 57712 and newer chips */
8435 if (!CHIP_IS_E1x(bp
) && bnx2x_er_poll_igu_vq(bp
))
8439 /* TBD: Indicate that "process kill" is in progress to MCP */
8441 /* Clear "unprepared" bit */
8442 REG_WR(bp
, MISC_REG_UNPREPARED
, 0);
8445 /* Make sure all is written to the chip before the reset */
8448 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8449 * PSWHST, GRC and PSWRD Tetris buffer.
8451 usleep_range(1000, 1000);
8453 /* Prepare to chip reset: */
8456 bnx2x_reset_mcp_prep(bp
, &val
);
8462 /* reset the chip */
8463 bnx2x_process_kill_chip_reset(bp
, global
);
8466 /* Recover after reset: */
8468 if (global
&& bnx2x_reset_mcp_comp(bp
, val
))
8471 /* TBD: Add resetting the NO_MCP mode DB here */
8476 /* Open the gates #2, #3 and #4 */
8477 bnx2x_set_234_gates(bp
, false);
8479 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8480 * reset state, re-enable attentions. */
8485 int bnx2x_leader_reset(struct bnx2x
*bp
)
8488 bool global
= bnx2x_reset_is_global(bp
);
8491 /* if not going to reset MCP - load "fake" driver to reset HW while
8492 * driver is owner of the HW
8494 if (!global
&& !BP_NOMCP(bp
)) {
8495 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_REQ
, 0);
8497 BNX2X_ERR("MCP response failure, aborting\n");
8499 goto exit_leader_reset
;
8501 if ((load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
) &&
8502 (load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON
)) {
8503 BNX2X_ERR("MCP unexpected resp, aborting\n");
8505 goto exit_leader_reset2
;
8507 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_DONE
, 0);
8509 BNX2X_ERR("MCP response failure, aborting\n");
8511 goto exit_leader_reset2
;
8515 /* Try to recover after the failure */
8516 if (bnx2x_process_kill(bp
, global
)) {
8517 netdev_err(bp
->dev
, "Something bad had happen on engine %d! "
8518 "Aii!\n", BP_PATH(bp
));
8520 goto exit_leader_reset2
;
8524 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8527 bnx2x_set_reset_done(bp
);
8529 bnx2x_clear_reset_global(bp
);
8532 /* unload "fake driver" if it was loaded */
8533 if (!global
&& !BP_NOMCP(bp
)) {
8534 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
, 0);
8535 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
8539 bnx2x_release_leader_lock(bp
);
8544 static inline void bnx2x_recovery_failed(struct bnx2x
*bp
)
8546 netdev_err(bp
->dev
, "Recovery has failed. Power cycle is needed.\n");
8548 /* Disconnect this device */
8549 netif_device_detach(bp
->dev
);
8552 * Block ifup for all function on this engine until "process kill"
8555 bnx2x_set_reset_in_progress(bp
);
8557 /* Shut down the power */
8558 bnx2x_set_power_state(bp
, PCI_D3hot
);
8560 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
8566 * Assumption: runs under rtnl lock. This together with the fact
8567 * that it's called only from bnx2x_sp_rtnl() ensure that it
8568 * will never be called when netif_running(bp->dev) is false.
8570 static void bnx2x_parity_recover(struct bnx2x
*bp
)
8572 bool global
= false;
8573 u32 error_recovered
, error_unrecovered
;
8576 DP(NETIF_MSG_HW
, "Handling parity\n");
8578 switch (bp
->recovery_state
) {
8579 case BNX2X_RECOVERY_INIT
:
8580 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_INIT\n");
8581 is_parity
= bnx2x_chk_parity_attn(bp
, &global
, false);
8582 WARN_ON(!is_parity
);
8584 /* Try to get a LEADER_LOCK HW lock */
8585 if (bnx2x_trylock_leader_lock(bp
)) {
8586 bnx2x_set_reset_in_progress(bp
);
8588 * Check if there is a global attention and if
8589 * there was a global attention, set the global
8594 bnx2x_set_reset_global(bp
);
8599 /* Stop the driver */
8600 /* If interface has been removed - break */
8601 if (bnx2x_nic_unload(bp
, UNLOAD_RECOVERY
))
8604 bp
->recovery_state
= BNX2X_RECOVERY_WAIT
;
8606 /* Ensure "is_leader", MCP command sequence and
8607 * "recovery_state" update values are seen on other
8613 case BNX2X_RECOVERY_WAIT
:
8614 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_WAIT\n");
8615 if (bp
->is_leader
) {
8616 int other_engine
= BP_PATH(bp
) ? 0 : 1;
8617 bool other_load_status
=
8618 bnx2x_get_load_status(bp
, other_engine
);
8620 bnx2x_get_load_status(bp
, BP_PATH(bp
));
8621 global
= bnx2x_reset_is_global(bp
);
8624 * In case of a parity in a global block, let
8625 * the first leader that performs a
8626 * leader_reset() reset the global blocks in
8627 * order to clear global attentions. Otherwise
8628 * the the gates will remain closed for that
8632 (global
&& other_load_status
)) {
8633 /* Wait until all other functions get
8636 schedule_delayed_work(&bp
->sp_rtnl_task
,
8640 /* If all other functions got down -
8641 * try to bring the chip back to
8642 * normal. In any case it's an exit
8643 * point for a leader.
8645 if (bnx2x_leader_reset(bp
)) {
8646 bnx2x_recovery_failed(bp
);
8650 /* If we are here, means that the
8651 * leader has succeeded and doesn't
8652 * want to be a leader any more. Try
8653 * to continue as a none-leader.
8657 } else { /* non-leader */
8658 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
))) {
8659 /* Try to get a LEADER_LOCK HW lock as
8660 * long as a former leader may have
8661 * been unloaded by the user or
8662 * released a leadership by another
8665 if (bnx2x_trylock_leader_lock(bp
)) {
8666 /* I'm a leader now! Restart a
8673 schedule_delayed_work(&bp
->sp_rtnl_task
,
8679 * If there was a global attention, wait
8680 * for it to be cleared.
8682 if (bnx2x_reset_is_global(bp
)) {
8683 schedule_delayed_work(
8690 bp
->eth_stats
.recoverable_error
;
8692 bp
->eth_stats
.unrecoverable_error
;
8693 bp
->recovery_state
=
8694 BNX2X_RECOVERY_NIC_LOADING
;
8695 if (bnx2x_nic_load(bp
, LOAD_NORMAL
)) {
8696 error_unrecovered
++;
8701 /* Disconnect this device */
8702 netif_device_detach(bp
->dev
);
8703 /* Shut down the power */
8704 bnx2x_set_power_state(
8708 bp
->recovery_state
=
8709 BNX2X_RECOVERY_DONE
;
8713 bp
->eth_stats
.recoverable_error
=
8715 bp
->eth_stats
.unrecoverable_error
=
8727 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8728 * scheduled on a general queue in order to prevent a dead lock.
8730 static void bnx2x_sp_rtnl_task(struct work_struct
*work
)
8732 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_rtnl_task
.work
);
8736 if (!netif_running(bp
->dev
))
8739 /* if stop on error is defined no recovery flows should be executed */
8740 #ifdef BNX2X_STOP_ON_ERROR
8741 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8742 "so reset not done to allow debug dump,\n"
8743 "you will need to reboot when done\n");
8744 goto sp_rtnl_not_reset
;
8747 if (unlikely(bp
->recovery_state
!= BNX2X_RECOVERY_DONE
)) {
8749 * Clear all pending SP commands as we are going to reset the
8752 bp
->sp_rtnl_state
= 0;
8755 bnx2x_parity_recover(bp
);
8760 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT
, &bp
->sp_rtnl_state
)) {
8762 * Clear all pending SP commands as we are going to reset the
8765 bp
->sp_rtnl_state
= 0;
8768 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
8769 bnx2x_nic_load(bp
, LOAD_NORMAL
);
8773 #ifdef BNX2X_STOP_ON_ERROR
8776 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC
, &bp
->sp_rtnl_state
))
8777 bnx2x_setup_tc(bp
->dev
, bp
->dcbx_port_params
.ets
.num_of_cos
);
8780 * in case of fan failure we need to reset id if the "stop on error"
8781 * debug flag is set, since we trying to prevent permanent overheating
8784 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
)) {
8785 DP(BNX2X_MSG_SP
, "fan failure detected. Unloading driver\n");
8786 netif_device_detach(bp
->dev
);
8787 bnx2x_close(bp
->dev
);
8794 /* end of nic load/unload */
8796 static void bnx2x_period_task(struct work_struct
*work
)
8798 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, period_task
.work
);
8800 if (!netif_running(bp
->dev
))
8801 goto period_task_exit
;
8803 if (CHIP_REV_IS_SLOW(bp
)) {
8804 BNX2X_ERR("period task called on emulation, ignoring\n");
8805 goto period_task_exit
;
8808 bnx2x_acquire_phy_lock(bp
);
8810 * The barrier is needed to ensure the ordering between the writing to
8811 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8816 bnx2x_period_func(&bp
->link_params
, &bp
->link_vars
);
8818 /* Re-queue task in 1 sec */
8819 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 1*HZ
);
8822 bnx2x_release_phy_lock(bp
);
8828 * Init service functions
8831 static u32
bnx2x_get_pretend_reg(struct bnx2x
*bp
)
8833 u32 base
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
8834 u32 stride
= PXP2_REG_PGL_PRETEND_FUNC_F1
- base
;
8835 return base
+ (BP_ABS_FUNC(bp
)) * stride
;
8838 static void bnx2x_undi_int_disable_e1h(struct bnx2x
*bp
)
8840 u32 reg
= bnx2x_get_pretend_reg(bp
);
8842 /* Flush all outstanding writes */
8845 /* Pretend to be function 0 */
8847 REG_RD(bp
, reg
); /* Flush the GRC transaction (in the chip) */
8849 /* From now we are in the "like-E1" mode */
8850 bnx2x_int_disable(bp
);
8852 /* Flush all outstanding writes */
8855 /* Restore the original function */
8856 REG_WR(bp
, reg
, BP_ABS_FUNC(bp
));
8860 static inline void bnx2x_undi_int_disable(struct bnx2x
*bp
)
8863 bnx2x_int_disable(bp
);
8865 bnx2x_undi_int_disable_e1h(bp
);
8868 static void __devinit
bnx2x_undi_unload(struct bnx2x
*bp
)
8872 /* possibly another driver is trying to reset the chip */
8873 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
8875 /* check if doorbell queue is reset */
8876 if (REG_RD(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
)
8877 & MISC_REGISTERS_RESET_REG_1_RST_DORQ
) {
8880 * Check if it is the UNDI driver
8881 * UNDI driver initializes CID offset for normal bell to 0x7
8883 val
= REG_RD(bp
, DORQ_REG_NORM_CID_OFST
);
8885 u32 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8886 /* save our pf_num */
8887 int orig_pf_num
= bp
->pf_num
;
8889 u32 swap_en
, swap_val
, value
;
8891 /* clear the UNDI indication */
8892 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
8894 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8896 /* try unload UNDI on port 0 */
8899 (SHMEM_RD(bp
, func_mb
[bp
->pf_num
].drv_mb_header
) &
8900 DRV_MSG_SEQ_NUMBER_MASK
);
8901 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
8903 /* if UNDI is loaded on the other port */
8904 if (reset_code
!= FW_MSG_CODE_DRV_UNLOAD_COMMON
) {
8906 /* send "DONE" for previous unload */
8907 bnx2x_fw_command(bp
,
8908 DRV_MSG_CODE_UNLOAD_DONE
, 0);
8910 /* unload UNDI on port 1 */
8913 (SHMEM_RD(bp
, func_mb
[bp
->pf_num
].drv_mb_header
) &
8914 DRV_MSG_SEQ_NUMBER_MASK
);
8915 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8917 bnx2x_fw_command(bp
, reset_code
, 0);
8920 bnx2x_undi_int_disable(bp
);
8923 /* close input traffic and wait for it */
8924 /* Do not rcv packets to BRB */
8925 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_DRV_MASK
:
8926 NIG_REG_LLH0_BRB1_DRV_MASK
), 0x0);
8927 /* Do not direct rcv packets that are not for MCP to
8929 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
8930 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
8932 REG_WR(bp
, (port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
8933 MISC_REG_AEU_MASK_ATTN_FUNC_0
), 0);
8936 /* save NIG port swap info */
8937 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
8938 swap_en
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
8941 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
8945 if (CHIP_IS_E3(bp
)) {
8946 value
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
8947 value
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
8951 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
8954 /* take the NIG out of reset and restore swap values */
8956 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
8957 MISC_REGISTERS_RESET_REG_1_RST_NIG
);
8958 REG_WR(bp
, NIG_REG_PORT_SWAP
, swap_val
);
8959 REG_WR(bp
, NIG_REG_STRAP_OVERRIDE
, swap_en
);
8961 /* send unload done to the MCP */
8962 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
8964 /* restore our func and fw_seq */
8965 bp
->pf_num
= orig_pf_num
;
8969 /* now it's safe to release the lock */
8970 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
8973 static void __devinit
bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
8975 u32 val
, val2
, val3
, val4
, id
, boot_mode
;
8978 /* Get the chip revision id and number. */
8979 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8980 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
8981 id
= ((val
& 0xffff) << 16);
8982 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
8983 id
|= ((val
& 0xf) << 12);
8984 val
= REG_RD(bp
, MISC_REG_CHIP_METAL
);
8985 id
|= ((val
& 0xff) << 4);
8986 val
= REG_RD(bp
, MISC_REG_BOND_ID
);
8988 bp
->common
.chip_id
= id
;
8990 /* Set doorbell size */
8991 bp
->db_size
= (1 << BNX2X_DB_SHIFT
);
8993 if (!CHIP_IS_E1x(bp
)) {
8994 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
8996 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
8998 val
= (val
>> 1) & 1;
8999 BNX2X_DEV_INFO("chip is in %s\n", val
? "4_PORT_MODE" :
9001 bp
->common
.chip_port_mode
= val
? CHIP_4_PORT_MODE
:
9004 if (CHIP_MODE_IS_4_PORT(bp
))
9005 bp
->pfid
= (bp
->pf_num
>> 1); /* 0..3 */
9007 bp
->pfid
= (bp
->pf_num
& 0x6); /* 0, 2, 4, 6 */
9009 bp
->common
.chip_port_mode
= CHIP_PORT_MODE_NONE
; /* N/A */
9010 bp
->pfid
= bp
->pf_num
; /* 0..7 */
9013 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
9014 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
9016 val
= (REG_RD(bp
, 0x2874) & 0x55);
9017 if ((bp
->common
.chip_id
& 0x1) ||
9018 (CHIP_IS_E1(bp
) && val
) || (CHIP_IS_E1H(bp
) && (val
== 0x55))) {
9019 bp
->flags
|= ONE_PORT_FLAG
;
9020 BNX2X_DEV_INFO("single port device\n");
9023 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
9024 bp
->common
.flash_size
= (BNX2X_NVRAM_1MB_SIZE
<<
9025 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
9026 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9027 bp
->common
.flash_size
, bp
->common
.flash_size
);
9029 bnx2x_init_shmem(bp
);
9033 bp
->common
.shmem2_base
= REG_RD(bp
, (BP_PATH(bp
) ?
9034 MISC_REG_GENERIC_CR_1
:
9035 MISC_REG_GENERIC_CR_0
));
9037 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
9038 bp
->link_params
.shmem2_base
= bp
->common
.shmem2_base
;
9039 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9040 bp
->common
.shmem_base
, bp
->common
.shmem2_base
);
9042 if (!bp
->common
.shmem_base
) {
9043 BNX2X_DEV_INFO("MCP not active\n");
9044 bp
->flags
|= NO_MCP_FLAG
;
9048 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
9049 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp
->common
.hw_config
);
9051 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
9052 SHARED_HW_CFG_LED_MODE_MASK
) >>
9053 SHARED_HW_CFG_LED_MODE_SHIFT
);
9055 bp
->link_params
.feature_config_flags
= 0;
9056 val
= SHMEM_RD(bp
, dev_info
.shared_feature_config
.config
);
9057 if (val
& SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
)
9058 bp
->link_params
.feature_config_flags
|=
9059 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
9061 bp
->link_params
.feature_config_flags
&=
9062 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
9064 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
9065 bp
->common
.bc_ver
= val
;
9066 BNX2X_DEV_INFO("bc_ver %X\n", val
);
9067 if (val
< BNX2X_BC_VER
) {
9068 /* for now only warn
9069 * later we might need to enforce this */
9070 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
9071 "please upgrade BC\n", BNX2X_BC_VER
, val
);
9073 bp
->link_params
.feature_config_flags
|=
9074 (val
>= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
) ?
9075 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
: 0;
9077 bp
->link_params
.feature_config_flags
|=
9078 (val
>= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
) ?
9079 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
: 0;
9081 bp
->link_params
.feature_config_flags
|=
9082 (val
>= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
) ?
9083 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
: 0;
9084 bp
->flags
|= (val
>= REQ_BC_VER_4_PFC_STATS_SUPPORTED
) ?
9085 BC_SUPPORTS_PFC_STATS
: 0;
9087 boot_mode
= SHMEM_RD(bp
,
9088 dev_info
.port_feature_config
[BP_PORT(bp
)].mba_config
) &
9089 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
;
9090 switch (boot_mode
) {
9091 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
:
9092 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_PXE
;
9094 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB
:
9095 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_ISCSI
;
9097 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT
:
9098 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_FCOE
;
9100 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE
:
9101 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_NONE
;
9105 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_PMC
, &pmc
);
9106 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
9108 BNX2X_DEV_INFO("%sWoL capable\n",
9109 (bp
->flags
& NO_WOL_FLAG
) ? "not " : "");
9111 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
9112 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
9113 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
9114 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
9116 dev_info(&bp
->pdev
->dev
, "part number %X-%X-%X-%X\n",
9117 val
, val2
, val3
, val4
);
9120 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9121 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9123 static void __devinit
bnx2x_get_igu_cam_info(struct bnx2x
*bp
)
9125 int pfid
= BP_FUNC(bp
);
9128 u8 fid
, igu_sb_cnt
= 0;
9130 bp
->igu_base_sb
= 0xff;
9131 if (CHIP_INT_MODE_IS_BC(bp
)) {
9133 igu_sb_cnt
= bp
->igu_sb_cnt
;
9134 bp
->igu_base_sb
= (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
) *
9137 bp
->igu_dsb_id
= E1HVN_MAX
* FP_SB_MAX_E1x
+
9138 (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
);
9143 /* IGU in normal mode - read CAM */
9144 for (igu_sb_id
= 0; igu_sb_id
< IGU_REG_MAPPING_MEMORY_SIZE
;
9146 val
= REG_RD(bp
, IGU_REG_MAPPING_MEMORY
+ igu_sb_id
* 4);
9147 if (!(val
& IGU_REG_MAPPING_MEMORY_VALID
))
9150 if ((fid
& IGU_FID_ENCODE_IS_PF
)) {
9151 if ((fid
& IGU_FID_PF_NUM_MASK
) != pfid
)
9153 if (IGU_VEC(val
) == 0)
9154 /* default status block */
9155 bp
->igu_dsb_id
= igu_sb_id
;
9157 if (bp
->igu_base_sb
== 0xff)
9158 bp
->igu_base_sb
= igu_sb_id
;
9164 #ifdef CONFIG_PCI_MSI
9166 * It's expected that number of CAM entries for this functions is equal
9167 * to the number evaluated based on the MSI-X table size. We want a
9168 * harsh warning if these values are different!
9170 WARN_ON(bp
->igu_sb_cnt
!= igu_sb_cnt
);
9173 if (igu_sb_cnt
== 0)
9174 BNX2X_ERR("CAM configuration error\n");
9177 static void __devinit
bnx2x_link_settings_supported(struct bnx2x
*bp
,
9180 int cfg_size
= 0, idx
, port
= BP_PORT(bp
);
9182 /* Aggregation of supported attributes of all external phys */
9183 bp
->port
.supported
[0] = 0;
9184 bp
->port
.supported
[1] = 0;
9185 switch (bp
->link_params
.num_phys
) {
9187 bp
->port
.supported
[0] = bp
->link_params
.phy
[INT_PHY
].supported
;
9191 bp
->port
.supported
[0] = bp
->link_params
.phy
[EXT_PHY1
].supported
;
9195 if (bp
->link_params
.multi_phy_config
&
9196 PORT_HW_CFG_PHY_SWAPPED_ENABLED
) {
9197 bp
->port
.supported
[1] =
9198 bp
->link_params
.phy
[EXT_PHY1
].supported
;
9199 bp
->port
.supported
[0] =
9200 bp
->link_params
.phy
[EXT_PHY2
].supported
;
9202 bp
->port
.supported
[0] =
9203 bp
->link_params
.phy
[EXT_PHY1
].supported
;
9204 bp
->port
.supported
[1] =
9205 bp
->link_params
.phy
[EXT_PHY2
].supported
;
9211 if (!(bp
->port
.supported
[0] || bp
->port
.supported
[1])) {
9212 BNX2X_ERR("NVRAM config error. BAD phy config."
9213 "PHY1 config 0x%x, PHY2 config 0x%x\n",
9215 dev_info
.port_hw_config
[port
].external_phy_config
),
9217 dev_info
.port_hw_config
[port
].external_phy_config2
));
9222 bp
->port
.phy_addr
= REG_RD(bp
, MISC_REG_WC0_CTRL_PHY_ADDR
);
9224 switch (switch_cfg
) {
9226 bp
->port
.phy_addr
= REG_RD(
9227 bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+ port
*0x10);
9229 case SWITCH_CFG_10G
:
9230 bp
->port
.phy_addr
= REG_RD(
9231 bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+ port
*0x18);
9234 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9235 bp
->port
.link_config
[0]);
9239 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
9240 /* mask what we support according to speed_cap_mask per configuration */
9241 for (idx
= 0; idx
< cfg_size
; idx
++) {
9242 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9243 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
9244 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Half
;
9246 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9247 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
9248 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Full
;
9250 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9251 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
9252 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Half
;
9254 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9255 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
9256 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Full
;
9258 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9259 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
9260 bp
->port
.supported
[idx
] &= ~(SUPPORTED_1000baseT_Half
|
9261 SUPPORTED_1000baseT_Full
);
9263 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9264 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
9265 bp
->port
.supported
[idx
] &= ~SUPPORTED_2500baseX_Full
;
9267 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9268 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
9269 bp
->port
.supported
[idx
] &= ~SUPPORTED_10000baseT_Full
;
9273 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp
->port
.supported
[0],
9274 bp
->port
.supported
[1]);
9277 static void __devinit
bnx2x_link_settings_requested(struct bnx2x
*bp
)
9279 u32 link_config
, idx
, cfg_size
= 0;
9280 bp
->port
.advertising
[0] = 0;
9281 bp
->port
.advertising
[1] = 0;
9282 switch (bp
->link_params
.num_phys
) {
9291 for (idx
= 0; idx
< cfg_size
; idx
++) {
9292 bp
->link_params
.req_duplex
[idx
] = DUPLEX_FULL
;
9293 link_config
= bp
->port
.link_config
[idx
];
9294 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
9295 case PORT_FEATURE_LINK_SPEED_AUTO
:
9296 if (bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
) {
9297 bp
->link_params
.req_line_speed
[idx
] =
9299 bp
->port
.advertising
[idx
] |=
9300 bp
->port
.supported
[idx
];
9302 /* force 10G, no AN */
9303 bp
->link_params
.req_line_speed
[idx
] =
9305 bp
->port
.advertising
[idx
] |=
9306 (ADVERTISED_10000baseT_Full
|
9312 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
9313 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Full
) {
9314 bp
->link_params
.req_line_speed
[idx
] =
9316 bp
->port
.advertising
[idx
] |=
9317 (ADVERTISED_10baseT_Full
|
9320 BNX2X_ERR("NVRAM config error. "
9321 "Invalid link_config 0x%x"
9322 " speed_cap_mask 0x%x\n",
9324 bp
->link_params
.speed_cap_mask
[idx
]);
9329 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
9330 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Half
) {
9331 bp
->link_params
.req_line_speed
[idx
] =
9333 bp
->link_params
.req_duplex
[idx
] =
9335 bp
->port
.advertising
[idx
] |=
9336 (ADVERTISED_10baseT_Half
|
9339 BNX2X_ERR("NVRAM config error. "
9340 "Invalid link_config 0x%x"
9341 " speed_cap_mask 0x%x\n",
9343 bp
->link_params
.speed_cap_mask
[idx
]);
9348 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
9349 if (bp
->port
.supported
[idx
] &
9350 SUPPORTED_100baseT_Full
) {
9351 bp
->link_params
.req_line_speed
[idx
] =
9353 bp
->port
.advertising
[idx
] |=
9354 (ADVERTISED_100baseT_Full
|
9357 BNX2X_ERR("NVRAM config error. "
9358 "Invalid link_config 0x%x"
9359 " speed_cap_mask 0x%x\n",
9361 bp
->link_params
.speed_cap_mask
[idx
]);
9366 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
9367 if (bp
->port
.supported
[idx
] &
9368 SUPPORTED_100baseT_Half
) {
9369 bp
->link_params
.req_line_speed
[idx
] =
9371 bp
->link_params
.req_duplex
[idx
] =
9373 bp
->port
.advertising
[idx
] |=
9374 (ADVERTISED_100baseT_Half
|
9377 BNX2X_ERR("NVRAM config error. "
9378 "Invalid link_config 0x%x"
9379 " speed_cap_mask 0x%x\n",
9381 bp
->link_params
.speed_cap_mask
[idx
]);
9386 case PORT_FEATURE_LINK_SPEED_1G
:
9387 if (bp
->port
.supported
[idx
] &
9388 SUPPORTED_1000baseT_Full
) {
9389 bp
->link_params
.req_line_speed
[idx
] =
9391 bp
->port
.advertising
[idx
] |=
9392 (ADVERTISED_1000baseT_Full
|
9395 BNX2X_ERR("NVRAM config error. "
9396 "Invalid link_config 0x%x"
9397 " speed_cap_mask 0x%x\n",
9399 bp
->link_params
.speed_cap_mask
[idx
]);
9404 case PORT_FEATURE_LINK_SPEED_2_5G
:
9405 if (bp
->port
.supported
[idx
] &
9406 SUPPORTED_2500baseX_Full
) {
9407 bp
->link_params
.req_line_speed
[idx
] =
9409 bp
->port
.advertising
[idx
] |=
9410 (ADVERTISED_2500baseX_Full
|
9413 BNX2X_ERR("NVRAM config error. "
9414 "Invalid link_config 0x%x"
9415 " speed_cap_mask 0x%x\n",
9417 bp
->link_params
.speed_cap_mask
[idx
]);
9422 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
9423 if (bp
->port
.supported
[idx
] &
9424 SUPPORTED_10000baseT_Full
) {
9425 bp
->link_params
.req_line_speed
[idx
] =
9427 bp
->port
.advertising
[idx
] |=
9428 (ADVERTISED_10000baseT_Full
|
9431 BNX2X_ERR("NVRAM config error. "
9432 "Invalid link_config 0x%x"
9433 " speed_cap_mask 0x%x\n",
9435 bp
->link_params
.speed_cap_mask
[idx
]);
9439 case PORT_FEATURE_LINK_SPEED_20G
:
9440 bp
->link_params
.req_line_speed
[idx
] = SPEED_20000
;
9444 BNX2X_ERR("NVRAM config error. "
9445 "BAD link speed link_config 0x%x\n",
9447 bp
->link_params
.req_line_speed
[idx
] =
9449 bp
->port
.advertising
[idx
] =
9450 bp
->port
.supported
[idx
];
9454 bp
->link_params
.req_flow_ctrl
[idx
] = (link_config
&
9455 PORT_FEATURE_FLOW_CONTROL_MASK
);
9456 if ((bp
->link_params
.req_flow_ctrl
[idx
] ==
9457 BNX2X_FLOW_CTRL_AUTO
) &&
9458 !(bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
)) {
9459 bp
->link_params
.req_flow_ctrl
[idx
] =
9460 BNX2X_FLOW_CTRL_NONE
;
9463 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9464 " 0x%x advertising 0x%x\n",
9465 bp
->link_params
.req_line_speed
[idx
],
9466 bp
->link_params
.req_duplex
[idx
],
9467 bp
->link_params
.req_flow_ctrl
[idx
],
9468 bp
->port
.advertising
[idx
]);
9472 static void __devinit
bnx2x_set_mac_buf(u8
*mac_buf
, u32 mac_lo
, u16 mac_hi
)
9474 mac_hi
= cpu_to_be16(mac_hi
);
9475 mac_lo
= cpu_to_be32(mac_lo
);
9476 memcpy(mac_buf
, &mac_hi
, sizeof(mac_hi
));
9477 memcpy(mac_buf
+ sizeof(mac_hi
), &mac_lo
, sizeof(mac_lo
));
9480 static void __devinit
bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
9482 int port
= BP_PORT(bp
);
9484 u32 ext_phy_type
, ext_phy_config
;
9486 bp
->link_params
.bp
= bp
;
9487 bp
->link_params
.port
= port
;
9489 bp
->link_params
.lane_config
=
9490 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
9492 bp
->link_params
.speed_cap_mask
[0] =
9494 dev_info
.port_hw_config
[port
].speed_capability_mask
);
9495 bp
->link_params
.speed_cap_mask
[1] =
9497 dev_info
.port_hw_config
[port
].speed_capability_mask2
);
9498 bp
->port
.link_config
[0] =
9499 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
9501 bp
->port
.link_config
[1] =
9502 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config2
);
9504 bp
->link_params
.multi_phy_config
=
9505 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].multi_phy_config
);
9506 /* If the device is capable of WoL, set the default state according
9509 config
= SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].config
);
9510 bp
->wol
= (!(bp
->flags
& NO_WOL_FLAG
) &&
9511 (config
& PORT_FEATURE_WOL_ENABLED
));
9513 BNX2X_DEV_INFO("lane_config 0x%08x "
9514 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9515 bp
->link_params
.lane_config
,
9516 bp
->link_params
.speed_cap_mask
[0],
9517 bp
->port
.link_config
[0]);
9519 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
[0] &
9520 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
9521 bnx2x_phy_probe(&bp
->link_params
);
9522 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
9524 bnx2x_link_settings_requested(bp
);
9527 * If connected directly, work with the internal PHY, otherwise, work
9528 * with the external PHY
9532 dev_info
.port_hw_config
[port
].external_phy_config
);
9533 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
9534 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
9535 bp
->mdio
.prtad
= bp
->port
.phy_addr
;
9537 else if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
9538 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
9540 XGXS_EXT_PHY_ADDR(ext_phy_config
);
9543 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9544 * In MF mode, it is set to cover self test cases
9547 bp
->port
.need_hw_lock
= 1;
9549 bp
->port
.need_hw_lock
= bnx2x_hw_lock_required(bp
,
9550 bp
->common
.shmem_base
,
9551 bp
->common
.shmem2_base
);
9554 void bnx2x_get_iscsi_info(struct bnx2x
*bp
)
9557 int port
= BP_PORT(bp
);
9559 u32 max_iscsi_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
9560 drv_lic_key
[port
].max_iscsi_conn
);
9562 /* Get the number of maximum allowed iSCSI connections */
9563 bp
->cnic_eth_dev
.max_iscsi_conn
=
9564 (max_iscsi_conn
& BNX2X_MAX_ISCSI_INIT_CONN_MASK
) >>
9565 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
;
9567 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9568 bp
->cnic_eth_dev
.max_iscsi_conn
);
9571 * If maximum allowed number of connections is zero -
9572 * disable the feature.
9574 if (!bp
->cnic_eth_dev
.max_iscsi_conn
)
9575 bp
->flags
|= NO_ISCSI_FLAG
;
9577 bp
->flags
|= NO_ISCSI_FLAG
;
9581 static void __devinit
bnx2x_get_fcoe_info(struct bnx2x
*bp
)
9584 int port
= BP_PORT(bp
);
9585 int func
= BP_ABS_FUNC(bp
);
9587 u32 max_fcoe_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
9588 drv_lic_key
[port
].max_fcoe_conn
);
9590 /* Get the number of maximum allowed FCoE connections */
9591 bp
->cnic_eth_dev
.max_fcoe_conn
=
9592 (max_fcoe_conn
& BNX2X_MAX_FCOE_INIT_CONN_MASK
) >>
9593 BNX2X_MAX_FCOE_INIT_CONN_SHIFT
;
9598 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
9600 dev_info
.port_hw_config
[port
].
9601 fcoe_wwn_port_name_upper
);
9602 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
9604 dev_info
.port_hw_config
[port
].
9605 fcoe_wwn_port_name_lower
);
9608 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
9610 dev_info
.port_hw_config
[port
].
9611 fcoe_wwn_node_name_upper
);
9612 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
9614 dev_info
.port_hw_config
[port
].
9615 fcoe_wwn_node_name_lower
);
9616 } else if (!IS_MF_SD(bp
)) {
9617 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
9620 * Read the WWN info only if the FCoE feature is enabled for
9623 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
9625 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
9626 MF_CFG_RD(bp
, func_ext_config
[func
].
9627 fcoe_wwn_port_name_upper
);
9628 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
9629 MF_CFG_RD(bp
, func_ext_config
[func
].
9630 fcoe_wwn_port_name_lower
);
9633 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
9634 MF_CFG_RD(bp
, func_ext_config
[func
].
9635 fcoe_wwn_node_name_upper
);
9636 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
9637 MF_CFG_RD(bp
, func_ext_config
[func
].
9638 fcoe_wwn_node_name_lower
);
9642 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp
->cnic_eth_dev
.max_fcoe_conn
);
9645 * If maximum allowed number of connections is zero -
9646 * disable the feature.
9648 if (!bp
->cnic_eth_dev
.max_fcoe_conn
)
9649 bp
->flags
|= NO_FCOE_FLAG
;
9651 bp
->flags
|= NO_FCOE_FLAG
;
9655 static void __devinit
bnx2x_get_cnic_info(struct bnx2x
*bp
)
9658 * iSCSI may be dynamically disabled but reading
9659 * info here we will decrease memory usage by driver
9660 * if the feature is disabled for good
9662 bnx2x_get_iscsi_info(bp
);
9663 bnx2x_get_fcoe_info(bp
);
9666 static void __devinit
bnx2x_get_mac_hwinfo(struct bnx2x
*bp
)
9669 int func
= BP_ABS_FUNC(bp
);
9670 int port
= BP_PORT(bp
);
9672 u8
*iscsi_mac
= bp
->cnic_eth_dev
.iscsi_mac
;
9673 u8
*fip_mac
= bp
->fip_mac
;
9676 /* Zero primary MAC configuration */
9677 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
9680 BNX2X_ERROR("warning: random MAC workaround active\n");
9681 random_ether_addr(bp
->dev
->dev_addr
);
9682 } else if (IS_MF(bp
)) {
9683 val2
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
9684 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_lower
);
9685 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
9686 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
))
9687 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
9691 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9692 * FCoE MAC then the appropriate feature should be disabled.
9695 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
9696 if (cfg
& MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
) {
9697 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
9698 iscsi_mac_addr_upper
);
9699 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
9700 iscsi_mac_addr_lower
);
9701 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
9702 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9705 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
9707 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
9708 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
9709 fcoe_mac_addr_upper
);
9710 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
9711 fcoe_mac_addr_lower
);
9712 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
9713 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
9717 bp
->flags
|= NO_FCOE_FLAG
;
9718 } else { /* SD mode */
9719 if (BNX2X_IS_MF_PROTOCOL_ISCSI(bp
)) {
9720 /* use primary mac as iscsi mac */
9721 memcpy(iscsi_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
9722 /* Zero primary MAC configuration */
9723 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
9725 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9726 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9732 /* in SF read MACs from port configuration */
9733 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
9734 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
9735 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
9738 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9740 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9742 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
9744 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9745 fcoe_fip_mac_upper
);
9746 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9747 fcoe_fip_mac_lower
);
9748 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
9752 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
9753 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
9756 /* Set the FCoE MAC in MF_SD mode */
9757 if (!CHIP_IS_E1x(bp
) && IS_MF_SD(bp
))
9758 memcpy(fip_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
9760 /* Disable iSCSI if MAC configuration is
9763 if (!is_valid_ether_addr(iscsi_mac
)) {
9764 bp
->flags
|= NO_ISCSI_FLAG
;
9765 memset(iscsi_mac
, 0, ETH_ALEN
);
9768 /* Disable FCoE if MAC configuration is
9771 if (!is_valid_ether_addr(fip_mac
)) {
9772 bp
->flags
|= NO_FCOE_FLAG
;
9773 memset(bp
->fip_mac
, 0, ETH_ALEN
);
9777 if (!bnx2x_is_valid_ether_addr(bp
, bp
->dev
->dev_addr
))
9778 dev_err(&bp
->pdev
->dev
,
9779 "bad Ethernet MAC address configuration: "
9780 "%pM, change it manually before bringing up "
9781 "the appropriate network interface\n",
9785 static int __devinit
bnx2x_get_hwinfo(struct bnx2x
*bp
)
9787 int /*abs*/func
= BP_ABS_FUNC(bp
);
9792 bnx2x_get_common_hwinfo(bp
);
9795 * initialize IGU parameters
9797 if (CHIP_IS_E1x(bp
)) {
9798 bp
->common
.int_block
= INT_BLOCK_HC
;
9800 bp
->igu_dsb_id
= DEF_SB_IGU_ID
;
9801 bp
->igu_base_sb
= 0;
9803 bp
->common
.int_block
= INT_BLOCK_IGU
;
9805 /* do not allow device reset during IGU info preocessing */
9806 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
9808 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
9810 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
9813 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9815 val
&= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
);
9816 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
, val
);
9817 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x7f);
9819 while (tout
&& REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
9821 usleep_range(1000, 1000);
9824 if (REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
9825 dev_err(&bp
->pdev
->dev
,
9826 "FORCING Normal Mode failed!!!\n");
9831 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
9832 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9833 bp
->common
.int_block
|= INT_BLOCK_MODE_BW_COMP
;
9835 BNX2X_DEV_INFO("IGU Normal Mode\n");
9837 bnx2x_get_igu_cam_info(bp
);
9839 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
9843 * set base FW non-default (fast path) status block id, this value is
9844 * used to initialize the fw_sb_id saved on the fp/queue structure to
9845 * determine the id used by the FW.
9847 if (CHIP_IS_E1x(bp
))
9848 bp
->base_fw_ndsb
= BP_PORT(bp
) * FP_SB_MAX_E1x
+ BP_L_ID(bp
);
9850 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9851 * the same queue are indicated on the same IGU SB). So we prefer
9852 * FW and IGU SBs to be the same value.
9854 bp
->base_fw_ndsb
= bp
->igu_base_sb
;
9856 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9857 "base_fw_ndsb %d\n", bp
->igu_dsb_id
, bp
->igu_base_sb
,
9858 bp
->igu_sb_cnt
, bp
->base_fw_ndsb
);
9861 * Initialize MF configuration
9868 if (!CHIP_IS_E1(bp
) && !BP_NOMCP(bp
)) {
9869 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9870 bp
->common
.shmem2_base
, SHMEM2_RD(bp
, size
),
9871 (u32
)offsetof(struct shmem2_region
, mf_cfg_addr
));
9873 if (SHMEM2_HAS(bp
, mf_cfg_addr
))
9874 bp
->common
.mf_cfg_base
= SHMEM2_RD(bp
, mf_cfg_addr
);
9876 bp
->common
.mf_cfg_base
= bp
->common
.shmem_base
+
9877 offsetof(struct shmem_region
, func_mb
) +
9878 E1H_FUNC_MAX
* sizeof(struct drv_func_mb
);
9880 * get mf configuration:
9881 * 1. existence of MF configuration
9882 * 2. MAC address must be legal (check only upper bytes)
9883 * for Switch-Independent mode;
9884 * OVLAN must be legal for Switch-Dependent mode
9885 * 3. SF_MODE configures specific MF mode
9887 if (bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
9888 /* get mf configuration */
9890 dev_info
.shared_feature_config
.config
);
9891 val
&= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
;
9894 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
:
9895 val
= MF_CFG_RD(bp
, func_mf_config
[func
].
9897 /* check for legal mac (upper bytes)*/
9898 if (val
!= 0xffff) {
9899 bp
->mf_mode
= MULTI_FUNCTION_SI
;
9900 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
9901 func_mf_config
[func
].config
);
9903 BNX2X_DEV_INFO("illegal MAC address "
9906 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
:
9907 /* get OV configuration */
9909 func_mf_config
[FUNC_0
].e1hov_tag
);
9910 val
&= FUNC_MF_CFG_E1HOV_TAG_MASK
;
9912 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
9913 bp
->mf_mode
= MULTI_FUNCTION_SD
;
9914 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
9915 func_mf_config
[func
].config
);
9917 BNX2X_DEV_INFO("illegal OV for SD\n");
9920 /* Unknown configuration: reset mf_config */
9921 bp
->mf_config
[vn
] = 0;
9922 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val
);
9926 BNX2X_DEV_INFO("%s function mode\n",
9927 IS_MF(bp
) ? "multi" : "single");
9929 switch (bp
->mf_mode
) {
9930 case MULTI_FUNCTION_SD
:
9931 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
9932 FUNC_MF_CFG_E1HOV_TAG_MASK
;
9933 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
9935 bp
->path_has_ovlan
= true;
9937 BNX2X_DEV_INFO("MF OV for func %d is %d "
9938 "(0x%04x)\n", func
, bp
->mf_ov
,
9941 dev_err(&bp
->pdev
->dev
,
9942 "No valid MF OV for func %d, "
9943 "aborting\n", func
);
9947 case MULTI_FUNCTION_SI
:
9948 BNX2X_DEV_INFO("func %d is in MF "
9949 "switch-independent mode\n", func
);
9953 dev_err(&bp
->pdev
->dev
,
9954 "VN %d is in a single function mode, "
9961 /* check if other port on the path needs ovlan:
9962 * Since MF configuration is shared between ports
9963 * Possible mixed modes are only
9964 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9966 if (CHIP_MODE_IS_4_PORT(bp
) &&
9967 !bp
->path_has_ovlan
&&
9969 bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
9970 u8 other_port
= !BP_PORT(bp
);
9971 u8 other_func
= BP_PATH(bp
) + 2*other_port
;
9973 func_mf_config
[other_func
].e1hov_tag
);
9974 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
)
9975 bp
->path_has_ovlan
= true;
9979 /* adjust igu_sb_cnt to MF for E1x */
9980 if (CHIP_IS_E1x(bp
) && IS_MF(bp
))
9981 bp
->igu_sb_cnt
/= E1HVN_MAX
;
9984 bnx2x_get_port_hwinfo(bp
);
9986 /* Get MAC addresses */
9987 bnx2x_get_mac_hwinfo(bp
);
9989 bnx2x_get_cnic_info(bp
);
9994 static void __devinit
bnx2x_read_fwinfo(struct bnx2x
*bp
)
9996 int cnt
, i
, block_end
, rodi
;
9997 char vpd_start
[BNX2X_VPD_LEN
+1];
9998 char str_id_reg
[VENDOR_ID_LEN
+1];
9999 char str_id_cap
[VENDOR_ID_LEN
+1];
10001 char *vpd_extended_data
= NULL
;
10004 cnt
= pci_read_vpd(bp
->pdev
, 0, BNX2X_VPD_LEN
, vpd_start
);
10005 memset(bp
->fw_ver
, 0, sizeof(bp
->fw_ver
));
10007 if (cnt
< BNX2X_VPD_LEN
)
10008 goto out_not_found
;
10010 /* VPD RO tag should be first tag after identifier string, hence
10011 * we should be able to find it in first BNX2X_VPD_LEN chars
10013 i
= pci_vpd_find_tag(vpd_start
, 0, BNX2X_VPD_LEN
,
10014 PCI_VPD_LRDT_RO_DATA
);
10016 goto out_not_found
;
10018 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+
10019 pci_vpd_lrdt_size(&vpd_start
[i
]);
10021 i
+= PCI_VPD_LRDT_TAG_SIZE
;
10023 if (block_end
> BNX2X_VPD_LEN
) {
10024 vpd_extended_data
= kmalloc(block_end
, GFP_KERNEL
);
10025 if (vpd_extended_data
== NULL
)
10026 goto out_not_found
;
10028 /* read rest of vpd image into vpd_extended_data */
10029 memcpy(vpd_extended_data
, vpd_start
, BNX2X_VPD_LEN
);
10030 cnt
= pci_read_vpd(bp
->pdev
, BNX2X_VPD_LEN
,
10031 block_end
- BNX2X_VPD_LEN
,
10032 vpd_extended_data
+ BNX2X_VPD_LEN
);
10033 if (cnt
< (block_end
- BNX2X_VPD_LEN
))
10034 goto out_not_found
;
10035 vpd_data
= vpd_extended_data
;
10037 vpd_data
= vpd_start
;
10039 /* now vpd_data holds full vpd content in both cases */
10041 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
10042 PCI_VPD_RO_KEYWORD_MFR_ID
);
10044 goto out_not_found
;
10046 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
10048 if (len
!= VENDOR_ID_LEN
)
10049 goto out_not_found
;
10051 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
10053 /* vendor specific info */
10054 snprintf(str_id_reg
, VENDOR_ID_LEN
+ 1, "%04x", PCI_VENDOR_ID_DELL
);
10055 snprintf(str_id_cap
, VENDOR_ID_LEN
+ 1, "%04X", PCI_VENDOR_ID_DELL
);
10056 if (!strncmp(str_id_reg
, &vpd_data
[rodi
], VENDOR_ID_LEN
) ||
10057 !strncmp(str_id_cap
, &vpd_data
[rodi
], VENDOR_ID_LEN
)) {
10059 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
10060 PCI_VPD_RO_KEYWORD_VENDOR0
);
10062 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
10064 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
10066 if (len
< 32 && (len
+ rodi
) <= BNX2X_VPD_LEN
) {
10067 memcpy(bp
->fw_ver
, &vpd_data
[rodi
], len
);
10068 bp
->fw_ver
[len
] = ' ';
10071 kfree(vpd_extended_data
);
10075 kfree(vpd_extended_data
);
10079 static void __devinit
bnx2x_set_modes_bitmap(struct bnx2x
*bp
)
10083 if (CHIP_REV_IS_FPGA(bp
))
10084 SET_FLAGS(flags
, MODE_FPGA
);
10085 else if (CHIP_REV_IS_EMUL(bp
))
10086 SET_FLAGS(flags
, MODE_EMUL
);
10088 SET_FLAGS(flags
, MODE_ASIC
);
10090 if (CHIP_MODE_IS_4_PORT(bp
))
10091 SET_FLAGS(flags
, MODE_PORT4
);
10093 SET_FLAGS(flags
, MODE_PORT2
);
10095 if (CHIP_IS_E2(bp
))
10096 SET_FLAGS(flags
, MODE_E2
);
10097 else if (CHIP_IS_E3(bp
)) {
10098 SET_FLAGS(flags
, MODE_E3
);
10099 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
10100 SET_FLAGS(flags
, MODE_E3_A0
);
10101 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10102 SET_FLAGS(flags
, MODE_E3_B0
| MODE_COS3
);
10106 SET_FLAGS(flags
, MODE_MF
);
10107 switch (bp
->mf_mode
) {
10108 case MULTI_FUNCTION_SD
:
10109 SET_FLAGS(flags
, MODE_MF_SD
);
10111 case MULTI_FUNCTION_SI
:
10112 SET_FLAGS(flags
, MODE_MF_SI
);
10116 SET_FLAGS(flags
, MODE_SF
);
10118 #if defined(__LITTLE_ENDIAN)
10119 SET_FLAGS(flags
, MODE_LITTLE_ENDIAN
);
10120 #else /*(__BIG_ENDIAN)*/
10121 SET_FLAGS(flags
, MODE_BIG_ENDIAN
);
10123 INIT_MODE_FLAGS(bp
) = flags
;
10126 static int __devinit
bnx2x_init_bp(struct bnx2x
*bp
)
10129 int timer_interval
;
10132 mutex_init(&bp
->port
.phy_mutex
);
10133 mutex_init(&bp
->fw_mb_mutex
);
10134 spin_lock_init(&bp
->stats_lock
);
10136 mutex_init(&bp
->cnic_mutex
);
10139 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
10140 INIT_DELAYED_WORK(&bp
->sp_rtnl_task
, bnx2x_sp_rtnl_task
);
10141 INIT_DELAYED_WORK(&bp
->period_task
, bnx2x_period_task
);
10142 rc
= bnx2x_get_hwinfo(bp
);
10146 bnx2x_set_modes_bitmap(bp
);
10148 rc
= bnx2x_alloc_mem_bp(bp
);
10152 bnx2x_read_fwinfo(bp
);
10154 func
= BP_FUNC(bp
);
10156 /* need to reset chip if undi was active */
10158 bnx2x_undi_unload(bp
);
10160 if (CHIP_REV_IS_FPGA(bp
))
10161 dev_err(&bp
->pdev
->dev
, "FPGA detected\n");
10163 if (BP_NOMCP(bp
) && (func
== 0))
10164 dev_err(&bp
->pdev
->dev
, "MCP disabled, "
10165 "must load devices in order!\n");
10167 bp
->multi_mode
= multi_mode
;
10169 bp
->disable_tpa
= disable_tpa
;
10172 bp
->disable_tpa
|= IS_MF_ISCSI_SD(bp
);
10175 /* Set TPA flags */
10176 if (bp
->disable_tpa
) {
10177 bp
->flags
&= ~TPA_ENABLE_FLAG
;
10178 bp
->dev
->features
&= ~NETIF_F_LRO
;
10180 bp
->flags
|= TPA_ENABLE_FLAG
;
10181 bp
->dev
->features
|= NETIF_F_LRO
;
10184 if (CHIP_IS_E1(bp
))
10185 bp
->dropless_fc
= 0;
10187 bp
->dropless_fc
= dropless_fc
;
10191 bp
->tx_ring_size
= MAX_TX_AVAIL
;
10193 /* make sure that the numbers are in the right granularity */
10194 bp
->tx_ticks
= (50 / BNX2X_BTR
) * BNX2X_BTR
;
10195 bp
->rx_ticks
= (25 / BNX2X_BTR
) * BNX2X_BTR
;
10197 timer_interval
= (CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
);
10198 bp
->current_interval
= (poll
? poll
: timer_interval
);
10200 init_timer(&bp
->timer
);
10201 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
10202 bp
->timer
.data
= (unsigned long) bp
;
10203 bp
->timer
.function
= bnx2x_timer
;
10205 bnx2x_dcbx_set_state(bp
, true, BNX2X_DCBX_ENABLED_ON_NEG_ON
);
10206 bnx2x_dcbx_init_params(bp
);
10209 if (CHIP_IS_E1x(bp
))
10210 bp
->cnic_base_cl_id
= FP_SB_MAX_E1x
;
10212 bp
->cnic_base_cl_id
= FP_SB_MAX_E2
;
10215 /* multiple tx priority */
10216 if (CHIP_IS_E1x(bp
))
10217 bp
->max_cos
= BNX2X_MULTI_TX_COS_E1X
;
10218 if (CHIP_IS_E2(bp
) || CHIP_IS_E3A0(bp
))
10219 bp
->max_cos
= BNX2X_MULTI_TX_COS_E2_E3A0
;
10220 if (CHIP_IS_E3B0(bp
))
10221 bp
->max_cos
= BNX2X_MULTI_TX_COS_E3B0
;
10227 /****************************************************************************
10228 * General service functions
10229 ****************************************************************************/
10232 * net_device service functions
10235 /* called with rtnl_lock */
10236 static int bnx2x_open(struct net_device
*dev
)
10238 struct bnx2x
*bp
= netdev_priv(dev
);
10239 bool global
= false;
10240 int other_engine
= BP_PATH(bp
) ? 0 : 1;
10241 bool other_load_status
, load_status
;
10243 bp
->stats_init
= true;
10245 netif_carrier_off(dev
);
10247 bnx2x_set_power_state(bp
, PCI_D0
);
10249 other_load_status
= bnx2x_get_load_status(bp
, other_engine
);
10250 load_status
= bnx2x_get_load_status(bp
, BP_PATH(bp
));
10253 * If parity had happen during the unload, then attentions
10254 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10255 * want the first function loaded on the current engine to
10256 * complete the recovery.
10258 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
)) ||
10259 bnx2x_chk_parity_attn(bp
, &global
, true))
10262 * If there are attentions and they are in a global
10263 * blocks, set the GLOBAL_RESET bit regardless whether
10264 * it will be this function that will complete the
10268 bnx2x_set_reset_global(bp
);
10271 * Only the first function on the current engine should
10272 * try to recover in open. In case of attentions in
10273 * global blocks only the first in the chip should try
10276 if ((!load_status
&&
10277 (!global
|| !other_load_status
)) &&
10278 bnx2x_trylock_leader_lock(bp
) &&
10279 !bnx2x_leader_reset(bp
)) {
10280 netdev_info(bp
->dev
, "Recovered in open\n");
10284 /* recovery has failed... */
10285 bnx2x_set_power_state(bp
, PCI_D3hot
);
10286 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
10288 netdev_err(bp
->dev
, "Recovery flow hasn't been properly"
10289 " completed yet. Try again later. If u still see this"
10290 " message after a few retries then power cycle is"
10296 bp
->recovery_state
= BNX2X_RECOVERY_DONE
;
10297 return bnx2x_nic_load(bp
, LOAD_OPEN
);
10300 /* called with rtnl_lock */
10301 int bnx2x_close(struct net_device
*dev
)
10303 struct bnx2x
*bp
= netdev_priv(dev
);
10305 /* Unload the driver, release IRQs */
10306 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
);
10309 bnx2x_set_power_state(bp
, PCI_D3hot
);
10314 static inline int bnx2x_init_mcast_macs_list(struct bnx2x
*bp
,
10315 struct bnx2x_mcast_ramrod_params
*p
)
10317 int mc_count
= netdev_mc_count(bp
->dev
);
10318 struct bnx2x_mcast_list_elem
*mc_mac
=
10319 kzalloc(sizeof(*mc_mac
) * mc_count
, GFP_ATOMIC
);
10320 struct netdev_hw_addr
*ha
;
10325 INIT_LIST_HEAD(&p
->mcast_list
);
10327 netdev_for_each_mc_addr(ha
, bp
->dev
) {
10328 mc_mac
->mac
= bnx2x_mc_addr(ha
);
10329 list_add_tail(&mc_mac
->link
, &p
->mcast_list
);
10333 p
->mcast_list_len
= mc_count
;
10338 static inline void bnx2x_free_mcast_macs_list(
10339 struct bnx2x_mcast_ramrod_params
*p
)
10341 struct bnx2x_mcast_list_elem
*mc_mac
=
10342 list_first_entry(&p
->mcast_list
, struct bnx2x_mcast_list_elem
,
10350 * bnx2x_set_uc_list - configure a new unicast MACs list.
10352 * @bp: driver handle
10354 * We will use zero (0) as a MAC type for these MACs.
10356 static inline int bnx2x_set_uc_list(struct bnx2x
*bp
)
10359 struct net_device
*dev
= bp
->dev
;
10360 struct netdev_hw_addr
*ha
;
10361 struct bnx2x_vlan_mac_obj
*mac_obj
= &bp
->fp
->mac_obj
;
10362 unsigned long ramrod_flags
= 0;
10364 /* First schedule a cleanup up of old configuration */
10365 rc
= bnx2x_del_all_macs(bp
, mac_obj
, BNX2X_UC_LIST_MAC
, false);
10367 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc
);
10371 netdev_for_each_uc_addr(ha
, dev
) {
10372 rc
= bnx2x_set_mac_one(bp
, bnx2x_uc_addr(ha
), mac_obj
, true,
10373 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
10375 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10381 /* Execute the pending commands */
10382 __set_bit(RAMROD_CONT
, &ramrod_flags
);
10383 return bnx2x_set_mac_one(bp
, NULL
, mac_obj
, false /* don't care */,
10384 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
10387 static inline int bnx2x_set_mc_list(struct bnx2x
*bp
)
10389 struct net_device
*dev
= bp
->dev
;
10390 struct bnx2x_mcast_ramrod_params rparam
= {0};
10393 rparam
.mcast_obj
= &bp
->mcast_obj
;
10395 /* first, clear all configured multicast MACs */
10396 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
10398 BNX2X_ERR("Failed to clear multicast "
10399 "configuration: %d\n", rc
);
10403 /* then, configure a new MACs list */
10404 if (netdev_mc_count(dev
)) {
10405 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
);
10407 BNX2X_ERR("Failed to create multicast MACs "
10412 /* Now add the new MACs */
10413 rc
= bnx2x_config_mcast(bp
, &rparam
,
10414 BNX2X_MCAST_CMD_ADD
);
10416 BNX2X_ERR("Failed to set a new multicast "
10417 "configuration: %d\n", rc
);
10419 bnx2x_free_mcast_macs_list(&rparam
);
10426 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10427 void bnx2x_set_rx_mode(struct net_device
*dev
)
10429 struct bnx2x
*bp
= netdev_priv(dev
);
10430 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
10432 if (bp
->state
!= BNX2X_STATE_OPEN
) {
10433 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
10437 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", bp
->dev
->flags
);
10439 if (dev
->flags
& IFF_PROMISC
)
10440 rx_mode
= BNX2X_RX_MODE_PROMISC
;
10441 else if ((dev
->flags
& IFF_ALLMULTI
) ||
10442 ((netdev_mc_count(dev
) > BNX2X_MAX_MULTICAST
) &&
10444 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
10446 /* some multicasts */
10447 if (bnx2x_set_mc_list(bp
) < 0)
10448 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
10450 if (bnx2x_set_uc_list(bp
) < 0)
10451 rx_mode
= BNX2X_RX_MODE_PROMISC
;
10454 bp
->rx_mode
= rx_mode
;
10456 /* handle ISCSI SD mode */
10457 if (IS_MF_ISCSI_SD(bp
))
10458 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
10461 /* Schedule the rx_mode command */
10462 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
)) {
10463 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
10467 bnx2x_set_storm_rx_mode(bp
);
10470 /* called with rtnl_lock */
10471 static int bnx2x_mdio_read(struct net_device
*netdev
, int prtad
,
10472 int devad
, u16 addr
)
10474 struct bnx2x
*bp
= netdev_priv(netdev
);
10478 DP(NETIF_MSG_LINK
, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10479 prtad
, devad
, addr
);
10481 /* The HW expects different devad if CL22 is used */
10482 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
10484 bnx2x_acquire_phy_lock(bp
);
10485 rc
= bnx2x_phy_read(&bp
->link_params
, prtad
, devad
, addr
, &value
);
10486 bnx2x_release_phy_lock(bp
);
10487 DP(NETIF_MSG_LINK
, "mdio_read_val 0x%x rc = 0x%x\n", value
, rc
);
10494 /* called with rtnl_lock */
10495 static int bnx2x_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
10496 u16 addr
, u16 value
)
10498 struct bnx2x
*bp
= netdev_priv(netdev
);
10501 DP(NETIF_MSG_LINK
, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10502 " value 0x%x\n", prtad
, devad
, addr
, value
);
10504 /* The HW expects different devad if CL22 is used */
10505 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
10507 bnx2x_acquire_phy_lock(bp
);
10508 rc
= bnx2x_phy_write(&bp
->link_params
, prtad
, devad
, addr
, value
);
10509 bnx2x_release_phy_lock(bp
);
10513 /* called with rtnl_lock */
10514 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10516 struct bnx2x
*bp
= netdev_priv(dev
);
10517 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
10519 DP(NETIF_MSG_LINK
, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10520 mdio
->phy_id
, mdio
->reg_num
, mdio
->val_in
);
10522 if (!netif_running(dev
))
10525 return mdio_mii_ioctl(&bp
->mdio
, mdio
, cmd
);
10528 #ifdef CONFIG_NET_POLL_CONTROLLER
10529 static void poll_bnx2x(struct net_device
*dev
)
10531 struct bnx2x
*bp
= netdev_priv(dev
);
10533 disable_irq(bp
->pdev
->irq
);
10534 bnx2x_interrupt(bp
->pdev
->irq
, dev
);
10535 enable_irq(bp
->pdev
->irq
);
10539 static int bnx2x_validate_addr(struct net_device
*dev
)
10541 struct bnx2x
*bp
= netdev_priv(dev
);
10543 if (!bnx2x_is_valid_ether_addr(bp
, dev
->dev_addr
))
10544 return -EADDRNOTAVAIL
;
10548 static const struct net_device_ops bnx2x_netdev_ops
= {
10549 .ndo_open
= bnx2x_open
,
10550 .ndo_stop
= bnx2x_close
,
10551 .ndo_start_xmit
= bnx2x_start_xmit
,
10552 .ndo_select_queue
= bnx2x_select_queue
,
10553 .ndo_set_rx_mode
= bnx2x_set_rx_mode
,
10554 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
10555 .ndo_validate_addr
= bnx2x_validate_addr
,
10556 .ndo_do_ioctl
= bnx2x_ioctl
,
10557 .ndo_change_mtu
= bnx2x_change_mtu
,
10558 .ndo_fix_features
= bnx2x_fix_features
,
10559 .ndo_set_features
= bnx2x_set_features
,
10560 .ndo_tx_timeout
= bnx2x_tx_timeout
,
10561 #ifdef CONFIG_NET_POLL_CONTROLLER
10562 .ndo_poll_controller
= poll_bnx2x
,
10564 .ndo_setup_tc
= bnx2x_setup_tc
,
10566 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10567 .ndo_fcoe_get_wwn
= bnx2x_fcoe_get_wwn
,
10571 static inline int bnx2x_set_coherency_mask(struct bnx2x
*bp
)
10573 struct device
*dev
= &bp
->pdev
->dev
;
10575 if (dma_set_mask(dev
, DMA_BIT_MASK(64)) == 0) {
10576 bp
->flags
|= USING_DAC_FLAG
;
10577 if (dma_set_coherent_mask(dev
, DMA_BIT_MASK(64)) != 0) {
10578 dev_err(dev
, "dma_set_coherent_mask failed, "
10582 } else if (dma_set_mask(dev
, DMA_BIT_MASK(32)) != 0) {
10583 dev_err(dev
, "System does not support DMA, aborting\n");
10590 static int __devinit
bnx2x_init_dev(struct pci_dev
*pdev
,
10591 struct net_device
*dev
,
10592 unsigned long board_type
)
10597 bool chip_is_e1x
= (board_type
== BCM57710
||
10598 board_type
== BCM57711
||
10599 board_type
== BCM57711E
);
10601 SET_NETDEV_DEV(dev
, &pdev
->dev
);
10602 bp
= netdev_priv(dev
);
10608 rc
= pci_enable_device(pdev
);
10610 dev_err(&bp
->pdev
->dev
,
10611 "Cannot enable PCI device, aborting\n");
10615 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
10616 dev_err(&bp
->pdev
->dev
,
10617 "Cannot find PCI device base address, aborting\n");
10619 goto err_out_disable
;
10622 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
10623 dev_err(&bp
->pdev
->dev
, "Cannot find second PCI device"
10624 " base address, aborting\n");
10626 goto err_out_disable
;
10629 if (atomic_read(&pdev
->enable_cnt
) == 1) {
10630 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
10632 dev_err(&bp
->pdev
->dev
,
10633 "Cannot obtain PCI resources, aborting\n");
10634 goto err_out_disable
;
10637 pci_set_master(pdev
);
10638 pci_save_state(pdev
);
10641 bp
->pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
10642 if (bp
->pm_cap
== 0) {
10643 dev_err(&bp
->pdev
->dev
,
10644 "Cannot find power management capability, aborting\n");
10646 goto err_out_release
;
10649 if (!pci_is_pcie(pdev
)) {
10650 dev_err(&bp
->pdev
->dev
, "Not PCI Express, aborting\n");
10652 goto err_out_release
;
10655 rc
= bnx2x_set_coherency_mask(bp
);
10657 goto err_out_release
;
10659 dev
->mem_start
= pci_resource_start(pdev
, 0);
10660 dev
->base_addr
= dev
->mem_start
;
10661 dev
->mem_end
= pci_resource_end(pdev
, 0);
10663 dev
->irq
= pdev
->irq
;
10665 bp
->regview
= pci_ioremap_bar(pdev
, 0);
10666 if (!bp
->regview
) {
10667 dev_err(&bp
->pdev
->dev
,
10668 "Cannot map register space, aborting\n");
10670 goto err_out_release
;
10673 /* In E1/E1H use pci device function given by kernel.
10674 * In E2/E3 read physical function from ME register since these chips
10675 * support Physical Device Assignment where kernel BDF maybe arbitrary
10676 * (depending on hypervisor).
10679 bp
->pf_num
= PCI_FUNC(pdev
->devfn
);
10680 else {/* chip is E2/3*/
10681 pci_read_config_dword(bp
->pdev
,
10682 PCICFG_ME_REGISTER
, &pci_cfg_dword
);
10683 bp
->pf_num
= (u8
)((pci_cfg_dword
& ME_REG_ABS_PF_NUM
) >>
10684 ME_REG_ABS_PF_NUM_SHIFT
);
10686 DP(BNX2X_MSG_SP
, "me reg PF num: %d\n", bp
->pf_num
);
10688 bnx2x_set_power_state(bp
, PCI_D0
);
10690 /* clean indirect addresses */
10691 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
10692 PCICFG_VENDOR_ID_OFFSET
);
10694 * Clean the following indirect addresses for all functions since it
10695 * is not used by the driver.
10697 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
, 0);
10698 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
, 0);
10699 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
, 0);
10700 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
, 0);
10703 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F1
, 0);
10704 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F1
, 0);
10705 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F1
, 0);
10706 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F1
, 0);
10710 * Enable internal target-read (in case we are probed after PF FLR).
10711 * Must be done prior to any BAR read access. Only for 57712 and up
10714 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
10716 /* Reset the load counter */
10717 bnx2x_clear_load_status(bp
);
10719 dev
->watchdog_timeo
= TX_TIMEOUT
;
10721 dev
->netdev_ops
= &bnx2x_netdev_ops
;
10722 bnx2x_set_ethtool_ops(dev
);
10724 dev
->priv_flags
|= IFF_UNICAST_FLT
;
10726 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
10727 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_LRO
|
10728 NETIF_F_RXCSUM
| NETIF_F_RXHASH
| NETIF_F_HW_VLAN_TX
;
10730 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
10731 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_HIGHDMA
;
10733 dev
->features
|= dev
->hw_features
| NETIF_F_HW_VLAN_RX
;
10734 if (bp
->flags
& USING_DAC_FLAG
)
10735 dev
->features
|= NETIF_F_HIGHDMA
;
10737 /* Add Loopback capability to the device */
10738 dev
->hw_features
|= NETIF_F_LOOPBACK
;
10741 dev
->dcbnl_ops
= &bnx2x_dcbnl_ops
;
10744 /* get_port_hwinfo() will set prtad and mmds properly */
10745 bp
->mdio
.prtad
= MDIO_PRTAD_NONE
;
10747 bp
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
10748 bp
->mdio
.dev
= dev
;
10749 bp
->mdio
.mdio_read
= bnx2x_mdio_read
;
10750 bp
->mdio
.mdio_write
= bnx2x_mdio_write
;
10755 if (atomic_read(&pdev
->enable_cnt
) == 1)
10756 pci_release_regions(pdev
);
10759 pci_disable_device(pdev
);
10760 pci_set_drvdata(pdev
, NULL
);
10766 static void __devinit
bnx2x_get_pcie_width_speed(struct bnx2x
*bp
,
10767 int *width
, int *speed
)
10769 u32 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCICFG_LINK_CONTROL
);
10771 *width
= (val
& PCICFG_LINK_WIDTH
) >> PCICFG_LINK_WIDTH_SHIFT
;
10773 /* return value of 1=2.5GHz 2=5GHz */
10774 *speed
= (val
& PCICFG_LINK_SPEED
) >> PCICFG_LINK_SPEED_SHIFT
;
10777 static int bnx2x_check_firmware(struct bnx2x
*bp
)
10779 const struct firmware
*firmware
= bp
->firmware
;
10780 struct bnx2x_fw_file_hdr
*fw_hdr
;
10781 struct bnx2x_fw_file_section
*sections
;
10782 u32 offset
, len
, num_ops
;
10787 if (firmware
->size
< sizeof(struct bnx2x_fw_file_hdr
))
10790 fw_hdr
= (struct bnx2x_fw_file_hdr
*)firmware
->data
;
10791 sections
= (struct bnx2x_fw_file_section
*)fw_hdr
;
10793 /* Make sure none of the offsets and sizes make us read beyond
10794 * the end of the firmware data */
10795 for (i
= 0; i
< sizeof(*fw_hdr
) / sizeof(*sections
); i
++) {
10796 offset
= be32_to_cpu(sections
[i
].offset
);
10797 len
= be32_to_cpu(sections
[i
].len
);
10798 if (offset
+ len
> firmware
->size
) {
10799 dev_err(&bp
->pdev
->dev
,
10800 "Section %d length is out of bounds\n", i
);
10805 /* Likewise for the init_ops offsets */
10806 offset
= be32_to_cpu(fw_hdr
->init_ops_offsets
.offset
);
10807 ops_offsets
= (u16
*)(firmware
->data
+ offset
);
10808 num_ops
= be32_to_cpu(fw_hdr
->init_ops
.len
) / sizeof(struct raw_op
);
10810 for (i
= 0; i
< be32_to_cpu(fw_hdr
->init_ops_offsets
.len
) / 2; i
++) {
10811 if (be16_to_cpu(ops_offsets
[i
]) > num_ops
) {
10812 dev_err(&bp
->pdev
->dev
,
10813 "Section offset %d is out of bounds\n", i
);
10818 /* Check FW version */
10819 offset
= be32_to_cpu(fw_hdr
->fw_version
.offset
);
10820 fw_ver
= firmware
->data
+ offset
;
10821 if ((fw_ver
[0] != BCM_5710_FW_MAJOR_VERSION
) ||
10822 (fw_ver
[1] != BCM_5710_FW_MINOR_VERSION
) ||
10823 (fw_ver
[2] != BCM_5710_FW_REVISION_VERSION
) ||
10824 (fw_ver
[3] != BCM_5710_FW_ENGINEERING_VERSION
)) {
10825 dev_err(&bp
->pdev
->dev
,
10826 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10827 fw_ver
[0], fw_ver
[1], fw_ver
[2],
10828 fw_ver
[3], BCM_5710_FW_MAJOR_VERSION
,
10829 BCM_5710_FW_MINOR_VERSION
,
10830 BCM_5710_FW_REVISION_VERSION
,
10831 BCM_5710_FW_ENGINEERING_VERSION
);
10838 static inline void be32_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
10840 const __be32
*source
= (const __be32
*)_source
;
10841 u32
*target
= (u32
*)_target
;
10844 for (i
= 0; i
< n
/4; i
++)
10845 target
[i
] = be32_to_cpu(source
[i
]);
10849 Ops array is stored in the following format:
10850 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10852 static inline void bnx2x_prep_ops(const u8
*_source
, u8
*_target
, u32 n
)
10854 const __be32
*source
= (const __be32
*)_source
;
10855 struct raw_op
*target
= (struct raw_op
*)_target
;
10858 for (i
= 0, j
= 0; i
< n
/8; i
++, j
+= 2) {
10859 tmp
= be32_to_cpu(source
[j
]);
10860 target
[i
].op
= (tmp
>> 24) & 0xff;
10861 target
[i
].offset
= tmp
& 0xffffff;
10862 target
[i
].raw_data
= be32_to_cpu(source
[j
+ 1]);
10867 * IRO array is stored in the following format:
10868 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10870 static inline void bnx2x_prep_iro(const u8
*_source
, u8
*_target
, u32 n
)
10872 const __be32
*source
= (const __be32
*)_source
;
10873 struct iro
*target
= (struct iro
*)_target
;
10876 for (i
= 0, j
= 0; i
< n
/sizeof(struct iro
); i
++) {
10877 target
[i
].base
= be32_to_cpu(source
[j
]);
10879 tmp
= be32_to_cpu(source
[j
]);
10880 target
[i
].m1
= (tmp
>> 16) & 0xffff;
10881 target
[i
].m2
= tmp
& 0xffff;
10883 tmp
= be32_to_cpu(source
[j
]);
10884 target
[i
].m3
= (tmp
>> 16) & 0xffff;
10885 target
[i
].size
= tmp
& 0xffff;
10890 static inline void be16_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
10892 const __be16
*source
= (const __be16
*)_source
;
10893 u16
*target
= (u16
*)_target
;
10896 for (i
= 0; i
< n
/2; i
++)
10897 target
[i
] = be16_to_cpu(source
[i
]);
10900 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10902 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10903 bp->arr = kmalloc(len, GFP_KERNEL); \
10906 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10907 (u8 *)bp->arr, len); \
10910 int bnx2x_init_firmware(struct bnx2x
*bp
)
10912 struct bnx2x_fw_file_hdr
*fw_hdr
;
10916 if (!bp
->firmware
) {
10917 const char *fw_file_name
;
10919 if (CHIP_IS_E1(bp
))
10920 fw_file_name
= FW_FILE_NAME_E1
;
10921 else if (CHIP_IS_E1H(bp
))
10922 fw_file_name
= FW_FILE_NAME_E1H
;
10923 else if (!CHIP_IS_E1x(bp
))
10924 fw_file_name
= FW_FILE_NAME_E2
;
10926 BNX2X_ERR("Unsupported chip revision\n");
10929 BNX2X_DEV_INFO("Loading %s\n", fw_file_name
);
10931 rc
= request_firmware(&bp
->firmware
, fw_file_name
,
10934 BNX2X_ERR("Can't load firmware file %s\n",
10936 goto request_firmware_exit
;
10939 rc
= bnx2x_check_firmware(bp
);
10941 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name
);
10942 goto request_firmware_exit
;
10946 fw_hdr
= (struct bnx2x_fw_file_hdr
*)bp
->firmware
->data
;
10948 /* Initialize the pointers to the init arrays */
10950 BNX2X_ALLOC_AND_SET(init_data
, request_firmware_exit
, be32_to_cpu_n
);
10953 BNX2X_ALLOC_AND_SET(init_ops
, init_ops_alloc_err
, bnx2x_prep_ops
);
10956 BNX2X_ALLOC_AND_SET(init_ops_offsets
, init_offsets_alloc_err
,
10959 /* STORMs firmware */
10960 INIT_TSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10961 be32_to_cpu(fw_hdr
->tsem_int_table_data
.offset
);
10962 INIT_TSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10963 be32_to_cpu(fw_hdr
->tsem_pram_data
.offset
);
10964 INIT_USEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10965 be32_to_cpu(fw_hdr
->usem_int_table_data
.offset
);
10966 INIT_USEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10967 be32_to_cpu(fw_hdr
->usem_pram_data
.offset
);
10968 INIT_XSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10969 be32_to_cpu(fw_hdr
->xsem_int_table_data
.offset
);
10970 INIT_XSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10971 be32_to_cpu(fw_hdr
->xsem_pram_data
.offset
);
10972 INIT_CSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10973 be32_to_cpu(fw_hdr
->csem_int_table_data
.offset
);
10974 INIT_CSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10975 be32_to_cpu(fw_hdr
->csem_pram_data
.offset
);
10977 BNX2X_ALLOC_AND_SET(iro_arr
, iro_alloc_err
, bnx2x_prep_iro
);
10982 kfree(bp
->init_ops_offsets
);
10983 init_offsets_alloc_err
:
10984 kfree(bp
->init_ops
);
10985 init_ops_alloc_err
:
10986 kfree(bp
->init_data
);
10987 request_firmware_exit
:
10988 release_firmware(bp
->firmware
);
10993 static void bnx2x_release_firmware(struct bnx2x
*bp
)
10995 kfree(bp
->init_ops_offsets
);
10996 kfree(bp
->init_ops
);
10997 kfree(bp
->init_data
);
10998 release_firmware(bp
->firmware
);
10999 bp
->firmware
= NULL
;
11003 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv
= {
11004 .init_hw_cmn_chip
= bnx2x_init_hw_common_chip
,
11005 .init_hw_cmn
= bnx2x_init_hw_common
,
11006 .init_hw_port
= bnx2x_init_hw_port
,
11007 .init_hw_func
= bnx2x_init_hw_func
,
11009 .reset_hw_cmn
= bnx2x_reset_common
,
11010 .reset_hw_port
= bnx2x_reset_port
,
11011 .reset_hw_func
= bnx2x_reset_func
,
11013 .gunzip_init
= bnx2x_gunzip_init
,
11014 .gunzip_end
= bnx2x_gunzip_end
,
11016 .init_fw
= bnx2x_init_firmware
,
11017 .release_fw
= bnx2x_release_firmware
,
11020 void bnx2x__init_func_obj(struct bnx2x
*bp
)
11022 /* Prepare DMAE related driver resources */
11023 bnx2x_setup_dmae(bp
);
11025 bnx2x_init_func_obj(bp
, &bp
->func_obj
,
11026 bnx2x_sp(bp
, func_rdata
),
11027 bnx2x_sp_mapping(bp
, func_rdata
),
11028 &bnx2x_func_sp_drv
);
11031 /* must be called after sriov-enable */
11032 static inline int bnx2x_set_qm_cid_count(struct bnx2x
*bp
)
11034 int cid_count
= BNX2X_L2_CID_COUNT(bp
);
11037 cid_count
+= CNIC_CID_MAX
;
11039 return roundup(cid_count
, QM_CID_ROUND
);
11043 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
11048 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev
*pdev
)
11053 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSIX
);
11056 * If MSI-X is not supported - return number of SBs needed to support
11057 * one fast path queue: one FP queue + SB for CNIC
11060 return 1 + CNIC_PRESENT
;
11063 * The value in the PCI configuration space is the index of the last
11064 * entry, namely one less than the actual size of the table, which is
11065 * exactly what we want to return from this function: number of all SBs
11066 * without the default SB.
11068 pci_read_config_word(pdev
, pos
+ PCI_MSI_FLAGS
, &control
);
11069 return control
& PCI_MSIX_FLAGS_QSIZE
;
11072 static int __devinit
bnx2x_init_one(struct pci_dev
*pdev
,
11073 const struct pci_device_id
*ent
)
11075 struct net_device
*dev
= NULL
;
11077 int pcie_width
, pcie_speed
;
11078 int rc
, max_non_def_sbs
;
11079 int rx_count
, tx_count
, rss_count
;
11081 * An estimated maximum supported CoS number according to the chip
11083 * We will try to roughly estimate the maximum number of CoSes this chip
11084 * may support in order to minimize the memory allocated for Tx
11085 * netdev_queue's. This number will be accurately calculated during the
11086 * initialization of bp->max_cos based on the chip versions AND chip
11087 * revision in the bnx2x_init_bp().
11089 u8 max_cos_est
= 0;
11091 switch (ent
->driver_data
) {
11095 max_cos_est
= BNX2X_MULTI_TX_COS_E1X
;
11100 max_cos_est
= BNX2X_MULTI_TX_COS_E2_E3A0
;
11109 max_cos_est
= BNX2X_MULTI_TX_COS_E3B0
;
11113 pr_err("Unknown board_type (%ld), aborting\n",
11118 max_non_def_sbs
= bnx2x_get_num_non_def_sbs(pdev
);
11121 * Do not allow the maximum SB count to grow above 16
11122 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
11123 * We will use the FP_SB_MAX_E1x macro for this matter.
11125 max_non_def_sbs
= min_t(int, FP_SB_MAX_E1x
, max_non_def_sbs
);
11127 WARN_ON(!max_non_def_sbs
);
11129 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11130 rss_count
= max_non_def_sbs
- CNIC_PRESENT
;
11132 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11133 rx_count
= rss_count
+ FCOE_PRESENT
;
11136 * Maximum number of netdev Tx queues:
11137 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11139 tx_count
= MAX_TXQS_PER_COS
* max_cos_est
+ FCOE_PRESENT
;
11141 /* dev zeroed in init_etherdev */
11142 dev
= alloc_etherdev_mqs(sizeof(*bp
), tx_count
, rx_count
);
11146 bp
= netdev_priv(dev
);
11148 DP(NETIF_MSG_DRV
, "Allocated netdev with %d tx and %d rx queues\n",
11149 tx_count
, rx_count
);
11151 bp
->igu_sb_cnt
= max_non_def_sbs
;
11152 bp
->msg_enable
= debug
;
11153 pci_set_drvdata(pdev
, dev
);
11155 rc
= bnx2x_init_dev(pdev
, dev
, ent
->driver_data
);
11161 DP(NETIF_MSG_DRV
, "max_non_def_sbs %d\n", max_non_def_sbs
);
11163 rc
= bnx2x_init_bp(bp
);
11165 goto init_one_exit
;
11168 * Map doorbels here as we need the real value of bp->max_cos which
11169 * is initialized in bnx2x_init_bp().
11171 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
11172 min_t(u64
, BNX2X_DB_SIZE(bp
),
11173 pci_resource_len(pdev
, 2)));
11174 if (!bp
->doorbells
) {
11175 dev_err(&bp
->pdev
->dev
,
11176 "Cannot map doorbell space, aborting\n");
11178 goto init_one_exit
;
11181 /* calc qm_cid_count */
11182 bp
->qm_cid_count
= bnx2x_set_qm_cid_count(bp
);
11185 /* disable FCOE L2 queue for E1x */
11186 if (CHIP_IS_E1x(bp
))
11187 bp
->flags
|= NO_FCOE_FLAG
;
11191 /* Configure interrupt mode: try to enable MSI-X/MSI if
11192 * needed, set bp->num_queues appropriately.
11194 bnx2x_set_int_mode(bp
);
11196 /* Add all NAPI objects */
11197 bnx2x_add_all_napi(bp
);
11199 rc
= register_netdev(dev
);
11201 dev_err(&pdev
->dev
, "Cannot register net device\n");
11202 goto init_one_exit
;
11206 if (!NO_FCOE(bp
)) {
11207 /* Add storage MAC address */
11209 dev_addr_add(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
11214 bnx2x_get_pcie_width_speed(bp
, &pcie_width
, &pcie_speed
);
11216 netdev_info(dev
, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11217 board_info
[ent
->driver_data
].name
,
11218 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
11220 ((!CHIP_IS_E2(bp
) && pcie_speed
== 2) ||
11221 (CHIP_IS_E2(bp
) && pcie_speed
== 1)) ?
11222 "5GHz (Gen2)" : "2.5GHz",
11223 dev
->base_addr
, bp
->pdev
->irq
, dev
->dev_addr
);
11229 iounmap(bp
->regview
);
11232 iounmap(bp
->doorbells
);
11236 if (atomic_read(&pdev
->enable_cnt
) == 1)
11237 pci_release_regions(pdev
);
11239 pci_disable_device(pdev
);
11240 pci_set_drvdata(pdev
, NULL
);
11245 static void __devexit
bnx2x_remove_one(struct pci_dev
*pdev
)
11247 struct net_device
*dev
= pci_get_drvdata(pdev
);
11251 dev_err(&pdev
->dev
, "BAD net device from bnx2x_init_one\n");
11254 bp
= netdev_priv(dev
);
11257 /* Delete storage MAC address */
11258 if (!NO_FCOE(bp
)) {
11260 dev_addr_del(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
11266 /* Delete app tlvs from dcbnl */
11267 bnx2x_dcbnl_update_applist(bp
, true);
11270 unregister_netdev(dev
);
11272 /* Delete all NAPI objects */
11273 bnx2x_del_all_napi(bp
);
11275 /* Power on: we can't let PCI layer write to us while we are in D3 */
11276 bnx2x_set_power_state(bp
, PCI_D0
);
11278 /* Disable MSI/MSI-X */
11279 bnx2x_disable_msi(bp
);
11282 bnx2x_set_power_state(bp
, PCI_D3hot
);
11284 /* Make sure RESET task is not scheduled before continuing */
11285 cancel_delayed_work_sync(&bp
->sp_rtnl_task
);
11288 iounmap(bp
->regview
);
11291 iounmap(bp
->doorbells
);
11293 bnx2x_release_firmware(bp
);
11295 bnx2x_free_mem_bp(bp
);
11299 if (atomic_read(&pdev
->enable_cnt
) == 1)
11300 pci_release_regions(pdev
);
11302 pci_disable_device(pdev
);
11303 pci_set_drvdata(pdev
, NULL
);
11306 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
11310 bp
->state
= BNX2X_STATE_ERROR
;
11312 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
11315 bnx2x_cnic_notify(bp
, CNIC_CTL_STOP_CMD
);
11318 bnx2x_tx_disable(bp
);
11320 bnx2x_netif_stop(bp
, 0);
11322 del_timer_sync(&bp
->timer
);
11324 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
11327 bnx2x_free_irq(bp
);
11329 /* Free SKBs, SGEs, TPA pool and driver internals */
11330 bnx2x_free_skbs(bp
);
11332 for_each_rx_queue(bp
, i
)
11333 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
11335 bnx2x_free_mem(bp
);
11337 bp
->state
= BNX2X_STATE_CLOSED
;
11339 netif_carrier_off(bp
->dev
);
11344 static void bnx2x_eeh_recover(struct bnx2x
*bp
)
11348 mutex_init(&bp
->port
.phy_mutex
);
11350 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
11351 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
11352 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp
->common
.shmem_base
);
11354 if (!bp
->common
.shmem_base
||
11355 (bp
->common
.shmem_base
< 0xA0000) ||
11356 (bp
->common
.shmem_base
>= 0xC0000)) {
11357 BNX2X_DEV_INFO("MCP not active\n");
11358 bp
->flags
|= NO_MCP_FLAG
;
11362 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
11363 if ((val
& (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
11364 != (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
11365 BNX2X_ERR("BAD MCP validity signature\n");
11369 * bnx2x_io_error_detected - called when PCI error is detected
11370 * @pdev: Pointer to PCI device
11371 * @state: The current pci connection state
11373 * This function is called after a PCI bus error affecting
11374 * this device has been detected.
11376 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
11377 pci_channel_state_t state
)
11379 struct net_device
*dev
= pci_get_drvdata(pdev
);
11380 struct bnx2x
*bp
= netdev_priv(dev
);
11384 netif_device_detach(dev
);
11386 if (state
== pci_channel_io_perm_failure
) {
11388 return PCI_ERS_RESULT_DISCONNECT
;
11391 if (netif_running(dev
))
11392 bnx2x_eeh_nic_unload(bp
);
11394 pci_disable_device(pdev
);
11398 /* Request a slot reset */
11399 return PCI_ERS_RESULT_NEED_RESET
;
11403 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11404 * @pdev: Pointer to PCI device
11406 * Restart the card from scratch, as if from a cold-boot.
11408 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
11410 struct net_device
*dev
= pci_get_drvdata(pdev
);
11411 struct bnx2x
*bp
= netdev_priv(dev
);
11415 if (pci_enable_device(pdev
)) {
11416 dev_err(&pdev
->dev
,
11417 "Cannot re-enable PCI device after reset\n");
11419 return PCI_ERS_RESULT_DISCONNECT
;
11422 pci_set_master(pdev
);
11423 pci_restore_state(pdev
);
11425 if (netif_running(dev
))
11426 bnx2x_set_power_state(bp
, PCI_D0
);
11430 return PCI_ERS_RESULT_RECOVERED
;
11434 * bnx2x_io_resume - called when traffic can start flowing again
11435 * @pdev: Pointer to PCI device
11437 * This callback is called when the error recovery driver tells us that
11438 * its OK to resume normal operation.
11440 static void bnx2x_io_resume(struct pci_dev
*pdev
)
11442 struct net_device
*dev
= pci_get_drvdata(pdev
);
11443 struct bnx2x
*bp
= netdev_priv(dev
);
11445 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
11446 netdev_err(bp
->dev
, "Handling parity error recovery. "
11447 "Try again later\n");
11453 bnx2x_eeh_recover(bp
);
11455 if (netif_running(dev
))
11456 bnx2x_nic_load(bp
, LOAD_NORMAL
);
11458 netif_device_attach(dev
);
11463 static struct pci_error_handlers bnx2x_err_handler
= {
11464 .error_detected
= bnx2x_io_error_detected
,
11465 .slot_reset
= bnx2x_io_slot_reset
,
11466 .resume
= bnx2x_io_resume
,
11469 static struct pci_driver bnx2x_pci_driver
= {
11470 .name
= DRV_MODULE_NAME
,
11471 .id_table
= bnx2x_pci_tbl
,
11472 .probe
= bnx2x_init_one
,
11473 .remove
= __devexit_p(bnx2x_remove_one
),
11474 .suspend
= bnx2x_suspend
,
11475 .resume
= bnx2x_resume
,
11476 .err_handler
= &bnx2x_err_handler
,
11479 static int __init
bnx2x_init(void)
11483 pr_info("%s", version
);
11485 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
11486 if (bnx2x_wq
== NULL
) {
11487 pr_err("Cannot create workqueue\n");
11491 ret
= pci_register_driver(&bnx2x_pci_driver
);
11493 pr_err("Cannot register driver\n");
11494 destroy_workqueue(bnx2x_wq
);
11499 static void __exit
bnx2x_cleanup(void)
11501 pci_unregister_driver(&bnx2x_pci_driver
);
11503 destroy_workqueue(bnx2x_wq
);
11506 void bnx2x_notify_link_changed(struct bnx2x
*bp
)
11508 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ BP_FUNC(bp
)*sizeof(u32
), 1);
11511 module_init(bnx2x_init
);
11512 module_exit(bnx2x_cleanup
);
11516 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11518 * @bp: driver handle
11519 * @set: set or clear the CAM entry
11521 * This function will wait until the ramdord completion returns.
11522 * Return 0 if success, -ENODEV if ramrod doesn't return.
11524 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x
*bp
)
11526 unsigned long ramrod_flags
= 0;
11528 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
11529 return bnx2x_set_mac_one(bp
, bp
->cnic_eth_dev
.iscsi_mac
,
11530 &bp
->iscsi_l2_mac_obj
, true,
11531 BNX2X_ISCSI_ETH_MAC
, &ramrod_flags
);
11534 /* count denotes the number of new completions we have seen */
11535 static void bnx2x_cnic_sp_post(struct bnx2x
*bp
, int count
)
11537 struct eth_spe
*spe
;
11539 #ifdef BNX2X_STOP_ON_ERROR
11540 if (unlikely(bp
->panic
))
11544 spin_lock_bh(&bp
->spq_lock
);
11545 BUG_ON(bp
->cnic_spq_pending
< count
);
11546 bp
->cnic_spq_pending
-= count
;
11549 for (; bp
->cnic_kwq_pending
; bp
->cnic_kwq_pending
--) {
11550 u16 type
= (le16_to_cpu(bp
->cnic_kwq_cons
->hdr
.type
)
11551 & SPE_HDR_CONN_TYPE
) >>
11552 SPE_HDR_CONN_TYPE_SHIFT
;
11553 u8 cmd
= (le32_to_cpu(bp
->cnic_kwq_cons
->hdr
.conn_and_cmd_data
)
11554 >> SPE_HDR_CMD_ID_SHIFT
) & 0xff;
11556 /* Set validation for iSCSI L2 client before sending SETUP
11559 if (type
== ETH_CONNECTION_TYPE
) {
11560 if (cmd
== RAMROD_CMD_ID_ETH_CLIENT_SETUP
)
11561 bnx2x_set_ctx_validation(bp
, &bp
->context
.
11562 vcxt
[BNX2X_ISCSI_ETH_CID
].eth
,
11563 BNX2X_ISCSI_ETH_CID
);
11567 * There may be not more than 8 L2, not more than 8 L5 SPEs
11568 * and in the air. We also check that number of outstanding
11569 * COMMON ramrods is not more than the EQ and SPQ can
11572 if (type
== ETH_CONNECTION_TYPE
) {
11573 if (!atomic_read(&bp
->cq_spq_left
))
11576 atomic_dec(&bp
->cq_spq_left
);
11577 } else if (type
== NONE_CONNECTION_TYPE
) {
11578 if (!atomic_read(&bp
->eq_spq_left
))
11581 atomic_dec(&bp
->eq_spq_left
);
11582 } else if ((type
== ISCSI_CONNECTION_TYPE
) ||
11583 (type
== FCOE_CONNECTION_TYPE
)) {
11584 if (bp
->cnic_spq_pending
>=
11585 bp
->cnic_eth_dev
.max_kwqe_pending
)
11588 bp
->cnic_spq_pending
++;
11590 BNX2X_ERR("Unknown SPE type: %d\n", type
);
11595 spe
= bnx2x_sp_get_next(bp
);
11596 *spe
= *bp
->cnic_kwq_cons
;
11598 DP(NETIF_MSG_TIMER
, "pending on SPQ %d, on KWQ %d count %d\n",
11599 bp
->cnic_spq_pending
, bp
->cnic_kwq_pending
, count
);
11601 if (bp
->cnic_kwq_cons
== bp
->cnic_kwq_last
)
11602 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
11604 bp
->cnic_kwq_cons
++;
11606 bnx2x_sp_prod_update(bp
);
11607 spin_unlock_bh(&bp
->spq_lock
);
11610 static int bnx2x_cnic_sp_queue(struct net_device
*dev
,
11611 struct kwqe_16
*kwqes
[], u32 count
)
11613 struct bnx2x
*bp
= netdev_priv(dev
);
11616 #ifdef BNX2X_STOP_ON_ERROR
11617 if (unlikely(bp
->panic
))
11621 if ((bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) &&
11622 (bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
11623 netdev_err(dev
, "Handling parity error recovery. Try again "
11628 spin_lock_bh(&bp
->spq_lock
);
11630 for (i
= 0; i
< count
; i
++) {
11631 struct eth_spe
*spe
= (struct eth_spe
*)kwqes
[i
];
11633 if (bp
->cnic_kwq_pending
== MAX_SP_DESC_CNT
)
11636 *bp
->cnic_kwq_prod
= *spe
;
11638 bp
->cnic_kwq_pending
++;
11640 DP(NETIF_MSG_TIMER
, "L5 SPQE %x %x %x:%x pos %d\n",
11641 spe
->hdr
.conn_and_cmd_data
, spe
->hdr
.type
,
11642 spe
->data
.update_data_addr
.hi
,
11643 spe
->data
.update_data_addr
.lo
,
11644 bp
->cnic_kwq_pending
);
11646 if (bp
->cnic_kwq_prod
== bp
->cnic_kwq_last
)
11647 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
11649 bp
->cnic_kwq_prod
++;
11652 spin_unlock_bh(&bp
->spq_lock
);
11654 if (bp
->cnic_spq_pending
< bp
->cnic_eth_dev
.max_kwqe_pending
)
11655 bnx2x_cnic_sp_post(bp
, 0);
11660 static int bnx2x_cnic_ctl_send(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
11662 struct cnic_ops
*c_ops
;
11665 mutex_lock(&bp
->cnic_mutex
);
11666 c_ops
= rcu_dereference_protected(bp
->cnic_ops
,
11667 lockdep_is_held(&bp
->cnic_mutex
));
11669 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
11670 mutex_unlock(&bp
->cnic_mutex
);
11675 static int bnx2x_cnic_ctl_send_bh(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
11677 struct cnic_ops
*c_ops
;
11681 c_ops
= rcu_dereference(bp
->cnic_ops
);
11683 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
11690 * for commands that have no data
11692 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
)
11694 struct cnic_ctl_info ctl
= {0};
11698 return bnx2x_cnic_ctl_send(bp
, &ctl
);
11701 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
)
11703 struct cnic_ctl_info ctl
= {0};
11705 /* first we tell CNIC and only then we count this as a completion */
11706 ctl
.cmd
= CNIC_CTL_COMPLETION_CMD
;
11707 ctl
.data
.comp
.cid
= cid
;
11708 ctl
.data
.comp
.error
= err
;
11710 bnx2x_cnic_ctl_send_bh(bp
, &ctl
);
11711 bnx2x_cnic_sp_post(bp
, 0);
11715 /* Called with netif_addr_lock_bh() taken.
11716 * Sets an rx_mode config for an iSCSI ETH client.
11718 * Completion should be checked outside.
11720 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
)
11722 unsigned long accept_flags
= 0, ramrod_flags
= 0;
11723 u8 cl_id
= bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
11724 int sched_state
= BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
;
11727 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11728 * because it's the only way for UIO Queue to accept
11729 * multicasts (in non-promiscuous mode only one Queue per
11730 * function will receive multicast packets (leading in our
11733 __set_bit(BNX2X_ACCEPT_UNICAST
, &accept_flags
);
11734 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &accept_flags
);
11735 __set_bit(BNX2X_ACCEPT_BROADCAST
, &accept_flags
);
11736 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &accept_flags
);
11738 /* Clear STOP_PENDING bit if START is requested */
11739 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &bp
->sp_state
);
11741 sched_state
= BNX2X_FILTER_ISCSI_ETH_START_SCHED
;
11743 /* Clear START_PENDING bit if STOP is requested */
11744 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &bp
->sp_state
);
11746 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
11747 set_bit(sched_state
, &bp
->sp_state
);
11749 __set_bit(RAMROD_RX
, &ramrod_flags
);
11750 bnx2x_set_q_rx_mode(bp
, cl_id
, 0, accept_flags
, 0,
11756 static int bnx2x_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*ctl
)
11758 struct bnx2x
*bp
= netdev_priv(dev
);
11761 switch (ctl
->cmd
) {
11762 case DRV_CTL_CTXTBL_WR_CMD
: {
11763 u32 index
= ctl
->data
.io
.offset
;
11764 dma_addr_t addr
= ctl
->data
.io
.dma_addr
;
11766 bnx2x_ilt_wr(bp
, index
, addr
);
11770 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD
: {
11771 int count
= ctl
->data
.credit
.credit_count
;
11773 bnx2x_cnic_sp_post(bp
, count
);
11777 /* rtnl_lock is held. */
11778 case DRV_CTL_START_L2_CMD
: {
11779 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11780 unsigned long sp_bits
= 0;
11782 /* Configure the iSCSI classification object */
11783 bnx2x_init_mac_obj(bp
, &bp
->iscsi_l2_mac_obj
,
11784 cp
->iscsi_l2_client_id
,
11785 cp
->iscsi_l2_cid
, BP_FUNC(bp
),
11786 bnx2x_sp(bp
, mac_rdata
),
11787 bnx2x_sp_mapping(bp
, mac_rdata
),
11788 BNX2X_FILTER_MAC_PENDING
,
11789 &bp
->sp_state
, BNX2X_OBJ_TYPE_RX
,
11792 /* Set iSCSI MAC address */
11793 rc
= bnx2x_set_iscsi_eth_mac_addr(bp
);
11800 /* Start accepting on iSCSI L2 ring */
11802 netif_addr_lock_bh(dev
);
11803 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
11804 netif_addr_unlock_bh(dev
);
11806 /* bits to wait on */
11807 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
11808 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &sp_bits
);
11810 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
11811 BNX2X_ERR("rx_mode completion timed out!\n");
11816 /* rtnl_lock is held. */
11817 case DRV_CTL_STOP_L2_CMD
: {
11818 unsigned long sp_bits
= 0;
11820 /* Stop accepting on iSCSI L2 ring */
11821 netif_addr_lock_bh(dev
);
11822 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
11823 netif_addr_unlock_bh(dev
);
11825 /* bits to wait on */
11826 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
11827 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &sp_bits
);
11829 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
11830 BNX2X_ERR("rx_mode completion timed out!\n");
11835 /* Unset iSCSI L2 MAC */
11836 rc
= bnx2x_del_all_macs(bp
, &bp
->iscsi_l2_mac_obj
,
11837 BNX2X_ISCSI_ETH_MAC
, true);
11840 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD
: {
11841 int count
= ctl
->data
.credit
.credit_count
;
11843 smp_mb__before_atomic_inc();
11844 atomic_add(count
, &bp
->cq_spq_left
);
11845 smp_mb__after_atomic_inc();
11848 case DRV_CTL_ULP_REGISTER_CMD
: {
11849 int ulp_type
= ctl
->data
.ulp_type
;
11851 if (CHIP_IS_E3(bp
)) {
11852 int idx
= BP_FW_MB_IDX(bp
);
11855 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
11856 if (ulp_type
== CNIC_ULP_ISCSI
)
11857 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
11858 else if (ulp_type
== CNIC_ULP_FCOE
)
11859 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
11860 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
11864 case DRV_CTL_ULP_UNREGISTER_CMD
: {
11865 int ulp_type
= ctl
->data
.ulp_type
;
11867 if (CHIP_IS_E3(bp
)) {
11868 int idx
= BP_FW_MB_IDX(bp
);
11871 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
11872 if (ulp_type
== CNIC_ULP_ISCSI
)
11873 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
11874 else if (ulp_type
== CNIC_ULP_FCOE
)
11875 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
11876 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
11882 BNX2X_ERR("unknown command %x\n", ctl
->cmd
);
11889 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
)
11891 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11893 if (bp
->flags
& USING_MSIX_FLAG
) {
11894 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
11895 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
11896 cp
->irq_arr
[0].vector
= bp
->msix_table
[1].vector
;
11898 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
11899 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
11901 if (!CHIP_IS_E1x(bp
))
11902 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e2_sb
;
11904 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e1x_sb
;
11906 cp
->irq_arr
[0].status_blk_num
= bnx2x_cnic_fw_sb_id(bp
);
11907 cp
->irq_arr
[0].status_blk_num2
= bnx2x_cnic_igu_sb_id(bp
);
11908 cp
->irq_arr
[1].status_blk
= bp
->def_status_blk
;
11909 cp
->irq_arr
[1].status_blk_num
= DEF_SB_ID
;
11910 cp
->irq_arr
[1].status_blk_num2
= DEF_SB_IGU_ID
;
11915 static int bnx2x_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
11918 struct bnx2x
*bp
= netdev_priv(dev
);
11919 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11924 bp
->cnic_kwq
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
11928 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
11929 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
11930 bp
->cnic_kwq_last
= bp
->cnic_kwq
+ MAX_SP_DESC_CNT
;
11932 bp
->cnic_spq_pending
= 0;
11933 bp
->cnic_kwq_pending
= 0;
11935 bp
->cnic_data
= data
;
11938 cp
->drv_state
|= CNIC_DRV_STATE_REGD
;
11939 cp
->iro_arr
= bp
->iro_arr
;
11941 bnx2x_setup_cnic_irq_info(bp
);
11943 rcu_assign_pointer(bp
->cnic_ops
, ops
);
11948 static int bnx2x_unregister_cnic(struct net_device
*dev
)
11950 struct bnx2x
*bp
= netdev_priv(dev
);
11951 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11953 mutex_lock(&bp
->cnic_mutex
);
11955 RCU_INIT_POINTER(bp
->cnic_ops
, NULL
);
11956 mutex_unlock(&bp
->cnic_mutex
);
11958 kfree(bp
->cnic_kwq
);
11959 bp
->cnic_kwq
= NULL
;
11964 struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
)
11966 struct bnx2x
*bp
= netdev_priv(dev
);
11967 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11969 /* If both iSCSI and FCoE are disabled - return NULL in
11970 * order to indicate CNIC that it should not try to work
11971 * with this device.
11973 if (NO_ISCSI(bp
) && NO_FCOE(bp
))
11976 cp
->drv_owner
= THIS_MODULE
;
11977 cp
->chip_id
= CHIP_ID(bp
);
11978 cp
->pdev
= bp
->pdev
;
11979 cp
->io_base
= bp
->regview
;
11980 cp
->io_base2
= bp
->doorbells
;
11981 cp
->max_kwqe_pending
= 8;
11982 cp
->ctx_blk_size
= CDU_ILT_PAGE_SZ
;
11983 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
11984 bnx2x_cid_ilt_lines(bp
);
11985 cp
->ctx_tbl_len
= CNIC_ILT_LINES
;
11986 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
11987 cp
->drv_submit_kwqes_16
= bnx2x_cnic_sp_queue
;
11988 cp
->drv_ctl
= bnx2x_drv_ctl
;
11989 cp
->drv_register_cnic
= bnx2x_register_cnic
;
11990 cp
->drv_unregister_cnic
= bnx2x_unregister_cnic
;
11991 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID
;
11992 cp
->iscsi_l2_client_id
=
11993 bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
11994 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID
;
11996 if (NO_ISCSI_OOO(bp
))
11997 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
12000 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI
;
12003 cp
->drv_state
|= CNIC_DRV_STATE_NO_FCOE
;
12005 DP(BNX2X_MSG_SP
, "page_size %d, tbl_offset %d, tbl_lines %d, "
12006 "starting cid %d\n",
12008 cp
->ctx_tbl_offset
,
12013 EXPORT_SYMBOL(bnx2x_cnic_probe
);
12015 #endif /* BCM_CNIC */