projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'pci-v4.5-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10 #include <linux/module.h>
11
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
30 #include <asm/page.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
33 #include <linux/if.h>
34 #include <linux/if_vlan.h>
35 #include <net/ip.h>
36 #include <net/tcp.h>
37 #include <net/udp.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
42 #endif
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
45 #endif
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53
54 #include "bnxt_hsi.h"
55 #include "bnxt.h"
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
58
59 #define BNXT_TX_TIMEOUT (5 * HZ)
60
61 static const char version[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
63
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION);
67
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
71
72 #define BNXT_TX_PUSH_THRESH 92
73
74 enum board_idx {
75 BCM57301,
76 BCM57302,
77 BCM57304,
78 BCM57402,
79 BCM57404,
80 BCM57406,
81 BCM57304_VF,
82 BCM57404_VF,
83 };
84
85 /* indexed by enum above */
86 static const struct {
87 char *name;
88 } board_info[] = {
89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
97 };
98
99 static const struct pci_device_id bnxt_pci_tbl[] = {
100 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
101 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
102 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
103 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
104 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
105 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
106 #ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
108 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
109 #endif
110 { 0 }
111 };
112
113 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
114
115 static const u16 bnxt_vf_req_snif[] = {
116 HWRM_FUNC_CFG,
117 HWRM_PORT_PHY_QCFG,
118 HWRM_CFA_L2_FILTER_ALLOC,
119 };
120
121 static bool bnxt_vf_pciid(enum board_idx idx)
122 {
123 return (idx == BCM57304_VF || idx == BCM57404_VF);
124 }
125
126 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
129
130 #define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
132
133 #define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
135
136 #define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
138
139 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
140 {
141 /* Tell compiler to fetch tx indices from memory. */
142 barrier();
143
144 return bp->tx_ring_size -
145 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
146 }
147
148 static const u16 bnxt_lhint_arr[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
150 TX_BD_FLAGS_LHINT_512_TO_1023,
151 TX_BD_FLAGS_LHINT_1024_TO_2047,
152 TX_BD_FLAGS_LHINT_1024_TO_2047,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
168 };
169
170 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
171 {
172 struct bnxt *bp = netdev_priv(dev);
173 struct tx_bd *txbd;
174 struct tx_bd_ext *txbd1;
175 struct netdev_queue *txq;
176 int i;
177 dma_addr_t mapping;
178 unsigned int length, pad = 0;
179 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
180 u16 prod, last_frag;
181 struct pci_dev *pdev = bp->pdev;
182 struct bnxt_tx_ring_info *txr;
183 struct bnxt_sw_tx_bd *tx_buf;
184
185 i = skb_get_queue_mapping(skb);
186 if (unlikely(i >= bp->tx_nr_rings)) {
187 dev_kfree_skb_any(skb);
188 return NETDEV_TX_OK;
189 }
190
191 txr = &bp->tx_ring[i];
192 txq = netdev_get_tx_queue(dev, i);
193 prod = txr->tx_prod;
194
195 free_size = bnxt_tx_avail(bp, txr);
196 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
197 netif_tx_stop_queue(txq);
198 return NETDEV_TX_BUSY;
199 }
200
201 length = skb->len;
202 len = skb_headlen(skb);
203 last_frag = skb_shinfo(skb)->nr_frags;
204
205 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
206
207 txbd->tx_bd_opaque = prod;
208
209 tx_buf = &txr->tx_buf_ring[prod];
210 tx_buf->skb = skb;
211 tx_buf->nr_frags = last_frag;
212
213 vlan_tag_flags = 0;
214 cfa_action = 0;
215 if (skb_vlan_tag_present(skb)) {
216 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
217 skb_vlan_tag_get(skb);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
220 */
221 if (skb->vlan_proto == htons(ETH_P_8021Q))
222 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
223 }
224
225 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
226 struct tx_push_bd *push = txr->tx_push;
227 struct tx_bd *tx_push = &push->txbd1;
228 struct tx_bd_ext *tx_push1 = &push->txbd2;
229 void *pdata = tx_push1 + 1;
230 int j;
231
232 /* Set COAL_NOW to be ready quickly for the next push */
233 tx_push->tx_bd_len_flags_type =
234 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
235 TX_BD_TYPE_LONG_TX_BD |
236 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
237 TX_BD_FLAGS_COAL_NOW |
238 TX_BD_FLAGS_PACKET_END |
239 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
240
241 if (skb->ip_summed == CHECKSUM_PARTIAL)
242 tx_push1->tx_bd_hsize_lflags =
243 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
244 else
245 tx_push1->tx_bd_hsize_lflags = 0;
246
247 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
248 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
249
250 skb_copy_from_linear_data(skb, pdata, len);
251 pdata += len;
252 for (j = 0; j < last_frag; j++) {
253 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
254 void *fptr;
255
256 fptr = skb_frag_address_safe(frag);
257 if (!fptr)
258 goto normal_tx;
259
260 memcpy(pdata, fptr, skb_frag_size(frag));
261 pdata += skb_frag_size(frag);
262 }
263
264 memcpy(txbd, tx_push, sizeof(*txbd));
265 prod = NEXT_TX(prod);
266 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
267 memcpy(txbd, tx_push1, sizeof(*txbd));
268 prod = NEXT_TX(prod);
269 push->doorbell =
270 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
271 txr->tx_prod = prod;
272
273 netdev_tx_sent_queue(txq, skb->len);
274
275 __iowrite64_copy(txr->tx_doorbell, push,
276 (length + sizeof(*push) + 8) / 8);
277
278 tx_buf->is_push = 1;
279
280 goto tx_done;
281 }
282
283 normal_tx:
284 if (length < BNXT_MIN_PKT_SIZE) {
285 pad = BNXT_MIN_PKT_SIZE - length;
286 if (skb_pad(skb, pad)) {
287 /* SKB already freed. */
288 tx_buf->skb = NULL;
289 return NETDEV_TX_OK;
290 }
291 length = BNXT_MIN_PKT_SIZE;
292 }
293
294 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
295
296 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
297 dev_kfree_skb_any(skb);
298 tx_buf->skb = NULL;
299 return NETDEV_TX_OK;
300 }
301
302 dma_unmap_addr_set(tx_buf, mapping, mapping);
303 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
304 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
305
306 txbd->tx_bd_haddr = cpu_to_le64(mapping);
307
308 prod = NEXT_TX(prod);
309 txbd1 = (struct tx_bd_ext *)
310 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
311
312 txbd1->tx_bd_hsize_lflags = 0;
313 if (skb_is_gso(skb)) {
314 u32 hdr_len;
315
316 if (skb->encapsulation)
317 hdr_len = skb_inner_network_offset(skb) +
318 skb_inner_network_header_len(skb) +
319 inner_tcp_hdrlen(skb);
320 else
321 hdr_len = skb_transport_offset(skb) +
322 tcp_hdrlen(skb);
323
324 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
325 TX_BD_FLAGS_T_IPID |
326 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
327 length = skb_shinfo(skb)->gso_size;
328 txbd1->tx_bd_mss = cpu_to_le32(length);
329 length += hdr_len;
330 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
331 txbd1->tx_bd_hsize_lflags =
332 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
333 txbd1->tx_bd_mss = 0;
334 }
335
336 length >>= 9;
337 flags |= bnxt_lhint_arr[length];
338 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
339
340 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
341 txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
342 for (i = 0; i < last_frag; i++) {
343 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
344
345 prod = NEXT_TX(prod);
346 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
347
348 len = skb_frag_size(frag);
349 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
350 DMA_TO_DEVICE);
351
352 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
353 goto tx_dma_error;
354
355 tx_buf = &txr->tx_buf_ring[prod];
356 dma_unmap_addr_set(tx_buf, mapping, mapping);
357
358 txbd->tx_bd_haddr = cpu_to_le64(mapping);
359
360 flags = len << TX_BD_LEN_SHIFT;
361 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
362 }
363
364 flags &= ~TX_BD_LEN;
365 txbd->tx_bd_len_flags_type =
366 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
367 TX_BD_FLAGS_PACKET_END);
368
369 netdev_tx_sent_queue(txq, skb->len);
370
371 /* Sync BD data before updating doorbell */
372 wmb();
373
374 prod = NEXT_TX(prod);
375 txr->tx_prod = prod;
376
377 writel(DB_KEY_TX | prod, txr->tx_doorbell);
378 writel(DB_KEY_TX | prod, txr->tx_doorbell);
379
380 tx_done:
381
382 mmiowb();
383
384 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
385 netif_tx_stop_queue(txq);
386
387 /* netif_tx_stop_queue() must be done before checking
388 * tx index in bnxt_tx_avail() below, because in
389 * bnxt_tx_int(), we update tx index before checking for
390 * netif_tx_queue_stopped().
391 */
392 smp_mb();
393 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
394 netif_tx_wake_queue(txq);
395 }
396 return NETDEV_TX_OK;
397
398 tx_dma_error:
399 last_frag = i;
400
401 /* start back at beginning and unmap skb */
402 prod = txr->tx_prod;
403 tx_buf = &txr->tx_buf_ring[prod];
404 tx_buf->skb = NULL;
405 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
406 skb_headlen(skb), PCI_DMA_TODEVICE);
407 prod = NEXT_TX(prod);
408
409 /* unmap remaining mapped pages */
410 for (i = 0; i < last_frag; i++) {
411 prod = NEXT_TX(prod);
412 tx_buf = &txr->tx_buf_ring[prod];
413 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
414 skb_frag_size(&skb_shinfo(skb)->frags[i]),
415 PCI_DMA_TODEVICE);
416 }
417
418 dev_kfree_skb_any(skb);
419 return NETDEV_TX_OK;
420 }
421
422 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
423 {
424 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
425 int index = txr - &bp->tx_ring[0];
426 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
427 u16 cons = txr->tx_cons;
428 struct pci_dev *pdev = bp->pdev;
429 int i;
430 unsigned int tx_bytes = 0;
431
432 for (i = 0; i < nr_pkts; i++) {
433 struct bnxt_sw_tx_bd *tx_buf;
434 struct sk_buff *skb;
435 int j, last;
436
437 tx_buf = &txr->tx_buf_ring[cons];
438 cons = NEXT_TX(cons);
439 skb = tx_buf->skb;
440 tx_buf->skb = NULL;
441
442 if (tx_buf->is_push) {
443 tx_buf->is_push = 0;
444 goto next_tx_int;
445 }
446
447 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
448 skb_headlen(skb), PCI_DMA_TODEVICE);
449 last = tx_buf->nr_frags;
450
451 for (j = 0; j < last; j++) {
452 cons = NEXT_TX(cons);
453 tx_buf = &txr->tx_buf_ring[cons];
454 dma_unmap_page(
455 &pdev->dev,
456 dma_unmap_addr(tx_buf, mapping),
457 skb_frag_size(&skb_shinfo(skb)->frags[j]),
458 PCI_DMA_TODEVICE);
459 }
460
461 next_tx_int:
462 cons = NEXT_TX(cons);
463
464 tx_bytes += skb->len;
465 dev_kfree_skb_any(skb);
466 }
467
468 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
469 txr->tx_cons = cons;
470
471 /* Need to make the tx_cons update visible to bnxt_start_xmit()
472 * before checking for netif_tx_queue_stopped(). Without the
473 * memory barrier, there is a small possibility that bnxt_start_xmit()
474 * will miss it and cause the queue to be stopped forever.
475 */
476 smp_mb();
477
478 if (unlikely(netif_tx_queue_stopped(txq)) &&
479 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
480 __netif_tx_lock(txq, smp_processor_id());
481 if (netif_tx_queue_stopped(txq) &&
482 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
483 txr->dev_state != BNXT_DEV_STATE_CLOSING)
484 netif_tx_wake_queue(txq);
485 __netif_tx_unlock(txq);
486 }
487 }
488
489 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
490 gfp_t gfp)
491 {
492 u8 *data;
493 struct pci_dev *pdev = bp->pdev;
494
495 data = kmalloc(bp->rx_buf_size, gfp);
496 if (!data)
497 return NULL;
498
499 *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
500 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
501
502 if (dma_mapping_error(&pdev->dev, *mapping)) {
503 kfree(data);
504 data = NULL;
505 }
506 return data;
507 }
508
509 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
510 struct bnxt_rx_ring_info *rxr,
511 u16 prod, gfp_t gfp)
512 {
513 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
514 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
515 u8 *data;
516 dma_addr_t mapping;
517
518 data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
519 if (!data)
520 return -ENOMEM;
521
522 rx_buf->data = data;
523 dma_unmap_addr_set(rx_buf, mapping, mapping);
524
525 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
526
527 return 0;
528 }
529
530 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
531 u8 *data)
532 {
533 u16 prod = rxr->rx_prod;
534 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
535 struct rx_bd *cons_bd, *prod_bd;
536
537 prod_rx_buf = &rxr->rx_buf_ring[prod];
538 cons_rx_buf = &rxr->rx_buf_ring[cons];
539
540 prod_rx_buf->data = data;
541
542 dma_unmap_addr_set(prod_rx_buf, mapping,
543 dma_unmap_addr(cons_rx_buf, mapping));
544
545 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
546 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
547
548 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
549 }
550
551 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
552 {
553 u16 next, max = rxr->rx_agg_bmap_size;
554
555 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
556 if (next >= max)
557 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
558 return next;
559 }
560
561 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
562 struct bnxt_rx_ring_info *rxr,
563 u16 prod, gfp_t gfp)
564 {
565 struct rx_bd *rxbd =
566 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
567 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
568 struct pci_dev *pdev = bp->pdev;
569 struct page *page;
570 dma_addr_t mapping;
571 u16 sw_prod = rxr->rx_sw_agg_prod;
572
573 page = alloc_page(gfp);
574 if (!page)
575 return -ENOMEM;
576
577 mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
578 PCI_DMA_FROMDEVICE);
579 if (dma_mapping_error(&pdev->dev, mapping)) {
580 __free_page(page);
581 return -EIO;
582 }
583
584 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
585 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
586
587 __set_bit(sw_prod, rxr->rx_agg_bmap);
588 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
589 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
590
591 rx_agg_buf->page = page;
592 rx_agg_buf->mapping = mapping;
593 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
594 rxbd->rx_bd_opaque = sw_prod;
595 return 0;
596 }
597
598 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
599 u32 agg_bufs)
600 {
601 struct bnxt *bp = bnapi->bp;
602 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
603 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
604 u16 prod = rxr->rx_agg_prod;
605 u16 sw_prod = rxr->rx_sw_agg_prod;
606 u32 i;
607
608 for (i = 0; i < agg_bufs; i++) {
609 u16 cons;
610 struct rx_agg_cmp *agg;
611 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
612 struct rx_bd *prod_bd;
613 struct page *page;
614
615 agg = (struct rx_agg_cmp *)
616 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
617 cons = agg->rx_agg_cmp_opaque;
618 __clear_bit(cons, rxr->rx_agg_bmap);
619
620 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
621 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
622
623 __set_bit(sw_prod, rxr->rx_agg_bmap);
624 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
625 cons_rx_buf = &rxr->rx_agg_ring[cons];
626
627 /* It is possible for sw_prod to be equal to cons, so
628 * set cons_rx_buf->page to NULL first.
629 */
630 page = cons_rx_buf->page;
631 cons_rx_buf->page = NULL;
632 prod_rx_buf->page = page;
633
634 prod_rx_buf->mapping = cons_rx_buf->mapping;
635
636 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
637
638 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
639 prod_bd->rx_bd_opaque = sw_prod;
640
641 prod = NEXT_RX_AGG(prod);
642 sw_prod = NEXT_RX_AGG(sw_prod);
643 cp_cons = NEXT_CMP(cp_cons);
644 }
645 rxr->rx_agg_prod = prod;
646 rxr->rx_sw_agg_prod = sw_prod;
647 }
648
649 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
650 struct bnxt_rx_ring_info *rxr, u16 cons,
651 u16 prod, u8 *data, dma_addr_t dma_addr,
652 unsigned int len)
653 {
654 int err;
655 struct sk_buff *skb;
656
657 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
658 if (unlikely(err)) {
659 bnxt_reuse_rx_data(rxr, cons, data);
660 return NULL;
661 }
662
663 skb = build_skb(data, 0);
664 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
665 PCI_DMA_FROMDEVICE);
666 if (!skb) {
667 kfree(data);
668 return NULL;
669 }
670
671 skb_reserve(skb, BNXT_RX_OFFSET);
672 skb_put(skb, len);
673 return skb;
674 }
675
676 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
677 struct sk_buff *skb, u16 cp_cons,
678 u32 agg_bufs)
679 {
680 struct pci_dev *pdev = bp->pdev;
681 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
682 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
683 u16 prod = rxr->rx_agg_prod;
684 u32 i;
685
686 for (i = 0; i < agg_bufs; i++) {
687 u16 cons, frag_len;
688 struct rx_agg_cmp *agg;
689 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
690 struct page *page;
691 dma_addr_t mapping;
692
693 agg = (struct rx_agg_cmp *)
694 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
695 cons = agg->rx_agg_cmp_opaque;
696 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
697 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
698
699 cons_rx_buf = &rxr->rx_agg_ring[cons];
700 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
701 __clear_bit(cons, rxr->rx_agg_bmap);
702
703 /* It is possible for bnxt_alloc_rx_page() to allocate
704 * a sw_prod index that equals the cons index, so we
705 * need to clear the cons entry now.
706 */
707 mapping = dma_unmap_addr(cons_rx_buf, mapping);
708 page = cons_rx_buf->page;
709 cons_rx_buf->page = NULL;
710
711 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
712 struct skb_shared_info *shinfo;
713 unsigned int nr_frags;
714
715 shinfo = skb_shinfo(skb);
716 nr_frags = --shinfo->nr_frags;
717 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
718
719 dev_kfree_skb(skb);
720
721 cons_rx_buf->page = page;
722
723 /* Update prod since possibly some pages have been
724 * allocated already.
725 */
726 rxr->rx_agg_prod = prod;
727 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
728 return NULL;
729 }
730
731 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
732 PCI_DMA_FROMDEVICE);
733
734 skb->data_len += frag_len;
735 skb->len += frag_len;
736 skb->truesize += PAGE_SIZE;
737
738 prod = NEXT_RX_AGG(prod);
739 cp_cons = NEXT_CMP(cp_cons);
740 }
741 rxr->rx_agg_prod = prod;
742 return skb;
743 }
744
745 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
746 u8 agg_bufs, u32 *raw_cons)
747 {
748 u16 last;
749 struct rx_agg_cmp *agg;
750
751 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
752 last = RING_CMP(*raw_cons);
753 agg = (struct rx_agg_cmp *)
754 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
755 return RX_AGG_CMP_VALID(agg, *raw_cons);
756 }
757
758 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
759 unsigned int len,
760 dma_addr_t mapping)
761 {
762 struct bnxt *bp = bnapi->bp;
763 struct pci_dev *pdev = bp->pdev;
764 struct sk_buff *skb;
765
766 skb = napi_alloc_skb(&bnapi->napi, len);
767 if (!skb)
768 return NULL;
769
770 dma_sync_single_for_cpu(&pdev->dev, mapping,
771 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
772
773 memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
774
775 dma_sync_single_for_device(&pdev->dev, mapping,
776 bp->rx_copy_thresh,
777 PCI_DMA_FROMDEVICE);
778
779 skb_put(skb, len);
780 return skb;
781 }
782
783 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
784 struct rx_tpa_start_cmp *tpa_start,
785 struct rx_tpa_start_cmp_ext *tpa_start1)
786 {
787 u8 agg_id = TPA_START_AGG_ID(tpa_start);
788 u16 cons, prod;
789 struct bnxt_tpa_info *tpa_info;
790 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
791 struct rx_bd *prod_bd;
792 dma_addr_t mapping;
793
794 cons = tpa_start->rx_tpa_start_cmp_opaque;
795 prod = rxr->rx_prod;
796 cons_rx_buf = &rxr->rx_buf_ring[cons];
797 prod_rx_buf = &rxr->rx_buf_ring[prod];
798 tpa_info = &rxr->rx_tpa[agg_id];
799
800 prod_rx_buf->data = tpa_info->data;
801
802 mapping = tpa_info->mapping;
803 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
804
805 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
806
807 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
808
809 tpa_info->data = cons_rx_buf->data;
810 cons_rx_buf->data = NULL;
811 tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
812
813 tpa_info->len =
814 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
815 RX_TPA_START_CMP_LEN_SHIFT;
816 if (likely(TPA_START_HASH_VALID(tpa_start))) {
817 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
818
819 tpa_info->hash_type = PKT_HASH_TYPE_L4;
820 tpa_info->gso_type = SKB_GSO_TCPV4;
821 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
822 if (hash_type == 3)
823 tpa_info->gso_type = SKB_GSO_TCPV6;
824 tpa_info->rss_hash =
825 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
826 } else {
827 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
828 tpa_info->gso_type = 0;
829 if (netif_msg_rx_err(bp))
830 netdev_warn(bp->dev, "TPA packet without valid hash\n");
831 }
832 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
833 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
834
835 rxr->rx_prod = NEXT_RX(prod);
836 cons = NEXT_RX(cons);
837 cons_rx_buf = &rxr->rx_buf_ring[cons];
838
839 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
840 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
841 cons_rx_buf->data = NULL;
842 }
843
844 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
845 u16 cp_cons, u32 agg_bufs)
846 {
847 if (agg_bufs)
848 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
849 }
850
851 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
852 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
853
854 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
855 struct rx_tpa_end_cmp *tpa_end,
856 struct rx_tpa_end_cmp_ext *tpa_end1,
857 struct sk_buff *skb)
858 {
859 #ifdef CONFIG_INET
860 struct tcphdr *th;
861 int payload_off, tcp_opt_len = 0;
862 int len, nw_off;
863 u16 segs;
864
865 segs = TPA_END_TPA_SEGS(tpa_end);
866 if (segs == 1)
867 return skb;
868
869 NAPI_GRO_CB(skb)->count = segs;
870 skb_shinfo(skb)->gso_size =
871 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
872 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
873 payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
874 RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
875 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
876 if (TPA_END_GRO_TS(tpa_end))
877 tcp_opt_len = 12;
878
879 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
880 struct iphdr *iph;
881
882 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
883 ETH_HLEN;
884 skb_set_network_header(skb, nw_off);
885 iph = ip_hdr(skb);
886 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
887 len = skb->len - skb_transport_offset(skb);
888 th = tcp_hdr(skb);
889 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
890 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
891 struct ipv6hdr *iph;
892
893 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
894 ETH_HLEN;
895 skb_set_network_header(skb, nw_off);
896 iph = ipv6_hdr(skb);
897 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
898 len = skb->len - skb_transport_offset(skb);
899 th = tcp_hdr(skb);
900 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
901 } else {
902 dev_kfree_skb_any(skb);
903 return NULL;
904 }
905 tcp_gro_complete(skb);
906
907 if (nw_off) { /* tunnel */
908 struct udphdr *uh = NULL;
909
910 if (skb->protocol == htons(ETH_P_IP)) {
911 struct iphdr *iph = (struct iphdr *)skb->data;
912
913 if (iph->protocol == IPPROTO_UDP)
914 uh = (struct udphdr *)(iph + 1);
915 } else {
916 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
917
918 if (iph->nexthdr == IPPROTO_UDP)
919 uh = (struct udphdr *)(iph + 1);
920 }
921 if (uh) {
922 if (uh->check)
923 skb_shinfo(skb)->gso_type |=
924 SKB_GSO_UDP_TUNNEL_CSUM;
925 else
926 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
927 }
928 }
929 #endif
930 return skb;
931 }
932
933 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
934 struct bnxt_napi *bnapi,
935 u32 *raw_cons,
936 struct rx_tpa_end_cmp *tpa_end,
937 struct rx_tpa_end_cmp_ext *tpa_end1,
938 bool *agg_event)
939 {
940 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
941 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
942 u8 agg_id = TPA_END_AGG_ID(tpa_end);
943 u8 *data, agg_bufs;
944 u16 cp_cons = RING_CMP(*raw_cons);
945 unsigned int len;
946 struct bnxt_tpa_info *tpa_info;
947 dma_addr_t mapping;
948 struct sk_buff *skb;
949
950 tpa_info = &rxr->rx_tpa[agg_id];
951 data = tpa_info->data;
952 prefetch(data);
953 len = tpa_info->len;
954 mapping = tpa_info->mapping;
955
956 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
957 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
958
959 if (agg_bufs) {
960 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
961 return ERR_PTR(-EBUSY);
962
963 *agg_event = true;
964 cp_cons = NEXT_CMP(cp_cons);
965 }
966
967 if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
968 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
969 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
970 agg_bufs, (int)MAX_SKB_FRAGS);
971 return NULL;
972 }
973
974 if (len <= bp->rx_copy_thresh) {
975 skb = bnxt_copy_skb(bnapi, data, len, mapping);
976 if (!skb) {
977 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
978 return NULL;
979 }
980 } else {
981 u8 *new_data;
982 dma_addr_t new_mapping;
983
984 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
985 if (!new_data) {
986 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
987 return NULL;
988 }
989
990 tpa_info->data = new_data;
991 tpa_info->mapping = new_mapping;
992
993 skb = build_skb(data, 0);
994 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
995 PCI_DMA_FROMDEVICE);
996
997 if (!skb) {
998 kfree(data);
999 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1000 return NULL;
1001 }
1002 skb_reserve(skb, BNXT_RX_OFFSET);
1003 skb_put(skb, len);
1004 }
1005
1006 if (agg_bufs) {
1007 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1008 if (!skb) {
1009 /* Page reuse already handled by bnxt_rx_pages(). */
1010 return NULL;
1011 }
1012 }
1013 skb->protocol = eth_type_trans(skb, bp->dev);
1014
1015 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1016 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1017
1018 if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1019 netdev_features_t features = skb->dev->features;
1020 u16 vlan_proto = tpa_info->metadata >>
1021 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1022
1023 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1024 vlan_proto == ETH_P_8021Q) ||
1025 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1026 vlan_proto == ETH_P_8021AD)) {
1027 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1028 tpa_info->metadata &
1029 RX_CMP_FLAGS2_METADATA_VID_MASK);
1030 }
1031 }
1032
1033 skb_checksum_none_assert(skb);
1034 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1035 skb->ip_summed = CHECKSUM_UNNECESSARY;
1036 skb->csum_level =
1037 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1038 }
1039
1040 if (TPA_END_GRO(tpa_end))
1041 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1042
1043 return skb;
1044 }
1045
1046 /* returns the following:
1047 * 1 - 1 packet successfully received
1048 * 0 - successful TPA_START, packet not completed yet
1049 * -EBUSY - completion ring does not have all the agg buffers yet
1050 * -ENOMEM - packet aborted due to out of memory
1051 * -EIO - packet aborted due to hw error indicated in BD
1052 */
1053 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1054 bool *agg_event)
1055 {
1056 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1057 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1058 struct net_device *dev = bp->dev;
1059 struct rx_cmp *rxcmp;
1060 struct rx_cmp_ext *rxcmp1;
1061 u32 tmp_raw_cons = *raw_cons;
1062 u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1063 struct bnxt_sw_rx_bd *rx_buf;
1064 unsigned int len;
1065 u8 *data, agg_bufs, cmp_type;
1066 dma_addr_t dma_addr;
1067 struct sk_buff *skb;
1068 int rc = 0;
1069
1070 rxcmp = (struct rx_cmp *)
1071 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1072
1073 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1074 cp_cons = RING_CMP(tmp_raw_cons);
1075 rxcmp1 = (struct rx_cmp_ext *)
1076 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1077
1078 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1079 return -EBUSY;
1080
1081 cmp_type = RX_CMP_TYPE(rxcmp);
1082
1083 prod = rxr->rx_prod;
1084
1085 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1086 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1087 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1088
1089 goto next_rx_no_prod;
1090
1091 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1092 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1093 (struct rx_tpa_end_cmp *)rxcmp,
1094 (struct rx_tpa_end_cmp_ext *)rxcmp1,
1095 agg_event);
1096
1097 if (unlikely(IS_ERR(skb)))
1098 return -EBUSY;
1099
1100 rc = -ENOMEM;
1101 if (likely(skb)) {
1102 skb_record_rx_queue(skb, bnapi->index);
1103 skb_mark_napi_id(skb, &bnapi->napi);
1104 if (bnxt_busy_polling(bnapi))
1105 netif_receive_skb(skb);
1106 else
1107 napi_gro_receive(&bnapi->napi, skb);
1108 rc = 1;
1109 }
1110 goto next_rx_no_prod;
1111 }
1112
1113 cons = rxcmp->rx_cmp_opaque;
1114 rx_buf = &rxr->rx_buf_ring[cons];
1115 data = rx_buf->data;
1116 prefetch(data);
1117
1118 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1119 RX_CMP_AGG_BUFS_SHIFT;
1120
1121 if (agg_bufs) {
1122 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1123 return -EBUSY;
1124
1125 cp_cons = NEXT_CMP(cp_cons);
1126 *agg_event = true;
1127 }
1128
1129 rx_buf->data = NULL;
1130 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1131 bnxt_reuse_rx_data(rxr, cons, data);
1132 if (agg_bufs)
1133 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1134
1135 rc = -EIO;
1136 goto next_rx;
1137 }
1138
1139 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1140 dma_addr = dma_unmap_addr(rx_buf, mapping);
1141
1142 if (len <= bp->rx_copy_thresh) {
1143 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1144 bnxt_reuse_rx_data(rxr, cons, data);
1145 if (!skb) {
1146 rc = -ENOMEM;
1147 goto next_rx;
1148 }
1149 } else {
1150 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1151 if (!skb) {
1152 rc = -ENOMEM;
1153 goto next_rx;
1154 }
1155 }
1156
1157 if (agg_bufs) {
1158 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1159 if (!skb) {
1160 rc = -ENOMEM;
1161 goto next_rx;
1162 }
1163 }
1164
1165 if (RX_CMP_HASH_VALID(rxcmp)) {
1166 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1167 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1168
1169 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1170 if (hash_type != 1 && hash_type != 3)
1171 type = PKT_HASH_TYPE_L3;
1172 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1173 }
1174
1175 skb->protocol = eth_type_trans(skb, dev);
1176
1177 if (rxcmp1->rx_cmp_flags2 &
1178 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1179 netdev_features_t features = skb->dev->features;
1180 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1181 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1182
1183 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1184 vlan_proto == ETH_P_8021Q) ||
1185 ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1186 vlan_proto == ETH_P_8021AD))
1187 __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1188 meta_data &
1189 RX_CMP_FLAGS2_METADATA_VID_MASK);
1190 }
1191
1192 skb_checksum_none_assert(skb);
1193 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1194 if (dev->features & NETIF_F_RXCSUM) {
1195 skb->ip_summed = CHECKSUM_UNNECESSARY;
1196 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1197 }
1198 } else {
1199 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1200 if (dev->features & NETIF_F_RXCSUM)
1201 cpr->rx_l4_csum_errors++;
1202 }
1203 }
1204
1205 skb_record_rx_queue(skb, bnapi->index);
1206 skb_mark_napi_id(skb, &bnapi->napi);
1207 if (bnxt_busy_polling(bnapi))
1208 netif_receive_skb(skb);
1209 else
1210 napi_gro_receive(&bnapi->napi, skb);
1211 rc = 1;
1212
1213 next_rx:
1214 rxr->rx_prod = NEXT_RX(prod);
1215
1216 next_rx_no_prod:
1217 *raw_cons = tmp_raw_cons;
1218
1219 return rc;
1220 }
1221
1222 static int bnxt_async_event_process(struct bnxt *bp,
1223 struct hwrm_async_event_cmpl *cmpl)
1224 {
1225 u16 event_id = le16_to_cpu(cmpl->event_id);
1226
1227 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1228 switch (event_id) {
1229 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1230 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1231 schedule_work(&bp->sp_task);
1232 break;
1233 default:
1234 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1235 event_id);
1236 break;
1237 }
1238 return 0;
1239 }
1240
1241 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1242 {
1243 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1244 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1245 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1246 (struct hwrm_fwd_req_cmpl *)txcmp;
1247
1248 switch (cmpl_type) {
1249 case CMPL_BASE_TYPE_HWRM_DONE:
1250 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1251 if (seq_id == bp->hwrm_intr_seq_id)
1252 bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1253 else
1254 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1255 break;
1256
1257 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1258 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1259
1260 if ((vf_id < bp->pf.first_vf_id) ||
1261 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1262 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1263 vf_id);
1264 return -EINVAL;
1265 }
1266
1267 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1268 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1269 schedule_work(&bp->sp_task);
1270 break;
1271
1272 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1273 bnxt_async_event_process(bp,
1274 (struct hwrm_async_event_cmpl *)txcmp);
1275
1276 default:
1277 break;
1278 }
1279
1280 return 0;
1281 }
1282
1283 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1284 {
1285 struct bnxt_napi *bnapi = dev_instance;
1286 struct bnxt *bp = bnapi->bp;
1287 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1288 u32 cons = RING_CMP(cpr->cp_raw_cons);
1289
1290 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1291 napi_schedule(&bnapi->napi);
1292 return IRQ_HANDLED;
1293 }
1294
1295 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1296 {
1297 u32 raw_cons = cpr->cp_raw_cons;
1298 u16 cons = RING_CMP(raw_cons);
1299 struct tx_cmp *txcmp;
1300
1301 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1302
1303 return TX_CMP_VALID(txcmp, raw_cons);
1304 }
1305
1306 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1307 {
1308 struct bnxt_napi *bnapi = dev_instance;
1309 struct bnxt *bp = bnapi->bp;
1310 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1311 u32 cons = RING_CMP(cpr->cp_raw_cons);
1312 u32 int_status;
1313
1314 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1315
1316 if (!bnxt_has_work(bp, cpr)) {
1317 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1318 /* return if erroneous interrupt */
1319 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1320 return IRQ_NONE;
1321 }
1322
1323 /* disable ring IRQ */
1324 BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1325
1326 /* Return here if interrupt is shared and is disabled. */
1327 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1328 return IRQ_HANDLED;
1329
1330 napi_schedule(&bnapi->napi);
1331 return IRQ_HANDLED;
1332 }
1333
1334 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1335 {
1336 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1337 u32 raw_cons = cpr->cp_raw_cons;
1338 u32 cons;
1339 int tx_pkts = 0;
1340 int rx_pkts = 0;
1341 bool rx_event = false;
1342 bool agg_event = false;
1343 struct tx_cmp *txcmp;
1344
1345 while (1) {
1346 int rc;
1347
1348 cons = RING_CMP(raw_cons);
1349 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1350
1351 if (!TX_CMP_VALID(txcmp, raw_cons))
1352 break;
1353
1354 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1355 tx_pkts++;
1356 /* return full budget so NAPI will complete. */
1357 if (unlikely(tx_pkts > bp->tx_wake_thresh))
1358 rx_pkts = budget;
1359 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1360 rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1361 if (likely(rc >= 0))
1362 rx_pkts += rc;
1363 else if (rc == -EBUSY) /* partial completion */
1364 break;
1365 rx_event = true;
1366 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1367 CMPL_BASE_TYPE_HWRM_DONE) ||
1368 (TX_CMP_TYPE(txcmp) ==
1369 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1370 (TX_CMP_TYPE(txcmp) ==
1371 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1372 bnxt_hwrm_handler(bp, txcmp);
1373 }
1374 raw_cons = NEXT_RAW_CMP(raw_cons);
1375
1376 if (rx_pkts == budget)
1377 break;
1378 }
1379
1380 cpr->cp_raw_cons = raw_cons;
1381 /* ACK completion ring before freeing tx ring and producing new
1382 * buffers in rx/agg rings to prevent overflowing the completion
1383 * ring.
1384 */
1385 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1386
1387 if (tx_pkts)
1388 bnxt_tx_int(bp, bnapi, tx_pkts);
1389
1390 if (rx_event) {
1391 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1392
1393 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1394 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1395 if (agg_event) {
1396 writel(DB_KEY_RX | rxr->rx_agg_prod,
1397 rxr->rx_agg_doorbell);
1398 writel(DB_KEY_RX | rxr->rx_agg_prod,
1399 rxr->rx_agg_doorbell);
1400 }
1401 }
1402 return rx_pkts;
1403 }
1404
1405 static int bnxt_poll(struct napi_struct *napi, int budget)
1406 {
1407 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1408 struct bnxt *bp = bnapi->bp;
1409 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1410 int work_done = 0;
1411
1412 if (!bnxt_lock_napi(bnapi))
1413 return budget;
1414
1415 while (1) {
1416 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1417
1418 if (work_done >= budget)
1419 break;
1420
1421 if (!bnxt_has_work(bp, cpr)) {
1422 napi_complete(napi);
1423 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1424 break;
1425 }
1426 }
1427 mmiowb();
1428 bnxt_unlock_napi(bnapi);
1429 return work_done;
1430 }
1431
1432 #ifdef CONFIG_NET_RX_BUSY_POLL
1433 static int bnxt_busy_poll(struct napi_struct *napi)
1434 {
1435 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1436 struct bnxt *bp = bnapi->bp;
1437 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1438 int rx_work, budget = 4;
1439
1440 if (atomic_read(&bp->intr_sem) != 0)
1441 return LL_FLUSH_FAILED;
1442
1443 if (!bnxt_lock_poll(bnapi))
1444 return LL_FLUSH_BUSY;
1445
1446 rx_work = bnxt_poll_work(bp, bnapi, budget);
1447
1448 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1449
1450 bnxt_unlock_poll(bnapi);
1451 return rx_work;
1452 }
1453 #endif
1454
1455 static void bnxt_free_tx_skbs(struct bnxt *bp)
1456 {
1457 int i, max_idx;
1458 struct pci_dev *pdev = bp->pdev;
1459
1460 if (!bp->tx_ring)
1461 return;
1462
1463 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1464 for (i = 0; i < bp->tx_nr_rings; i++) {
1465 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1466 int j;
1467
1468 for (j = 0; j < max_idx;) {
1469 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1470 struct sk_buff *skb = tx_buf->skb;
1471 int k, last;
1472
1473 if (!skb) {
1474 j++;
1475 continue;
1476 }
1477
1478 tx_buf->skb = NULL;
1479
1480 if (tx_buf->is_push) {
1481 dev_kfree_skb(skb);
1482 j += 2;
1483 continue;
1484 }
1485
1486 dma_unmap_single(&pdev->dev,
1487 dma_unmap_addr(tx_buf, mapping),
1488 skb_headlen(skb),
1489 PCI_DMA_TODEVICE);
1490
1491 last = tx_buf->nr_frags;
1492 j += 2;
1493 for (k = 0; k < last; k++, j++) {
1494 int ring_idx = j & bp->tx_ring_mask;
1495 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1496
1497 tx_buf = &txr->tx_buf_ring[ring_idx];
1498 dma_unmap_page(
1499 &pdev->dev,
1500 dma_unmap_addr(tx_buf, mapping),
1501 skb_frag_size(frag), PCI_DMA_TODEVICE);
1502 }
1503 dev_kfree_skb(skb);
1504 }
1505 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1506 }
1507 }
1508
1509 static void bnxt_free_rx_skbs(struct bnxt *bp)
1510 {
1511 int i, max_idx, max_agg_idx;
1512 struct pci_dev *pdev = bp->pdev;
1513
1514 if (!bp->rx_ring)
1515 return;
1516
1517 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1518 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1519 for (i = 0; i < bp->rx_nr_rings; i++) {
1520 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1521 int j;
1522
1523 if (rxr->rx_tpa) {
1524 for (j = 0; j < MAX_TPA; j++) {
1525 struct bnxt_tpa_info *tpa_info =
1526 &rxr->rx_tpa[j];
1527 u8 *data = tpa_info->data;
1528
1529 if (!data)
1530 continue;
1531
1532 dma_unmap_single(
1533 &pdev->dev,
1534 dma_unmap_addr(tpa_info, mapping),
1535 bp->rx_buf_use_size,
1536 PCI_DMA_FROMDEVICE);
1537
1538 tpa_info->data = NULL;
1539
1540 kfree(data);
1541 }
1542 }
1543
1544 for (j = 0; j < max_idx; j++) {
1545 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1546 u8 *data = rx_buf->data;
1547
1548 if (!data)
1549 continue;
1550
1551 dma_unmap_single(&pdev->dev,
1552 dma_unmap_addr(rx_buf, mapping),
1553 bp->rx_buf_use_size,
1554 PCI_DMA_FROMDEVICE);
1555
1556 rx_buf->data = NULL;
1557
1558 kfree(data);
1559 }
1560
1561 for (j = 0; j < max_agg_idx; j++) {
1562 struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1563 &rxr->rx_agg_ring[j];
1564 struct page *page = rx_agg_buf->page;
1565
1566 if (!page)
1567 continue;
1568
1569 dma_unmap_page(&pdev->dev,
1570 dma_unmap_addr(rx_agg_buf, mapping),
1571 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1572
1573 rx_agg_buf->page = NULL;
1574 __clear_bit(j, rxr->rx_agg_bmap);
1575
1576 __free_page(page);
1577 }
1578 }
1579 }
1580
1581 static void bnxt_free_skbs(struct bnxt *bp)
1582 {
1583 bnxt_free_tx_skbs(bp);
1584 bnxt_free_rx_skbs(bp);
1585 }
1586
1587 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1588 {
1589 struct pci_dev *pdev = bp->pdev;
1590 int i;
1591
1592 for (i = 0; i < ring->nr_pages; i++) {
1593 if (!ring->pg_arr[i])
1594 continue;
1595
1596 dma_free_coherent(&pdev->dev, ring->page_size,
1597 ring->pg_arr[i], ring->dma_arr[i]);
1598
1599 ring->pg_arr[i] = NULL;
1600 }
1601 if (ring->pg_tbl) {
1602 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1603 ring->pg_tbl, ring->pg_tbl_map);
1604 ring->pg_tbl = NULL;
1605 }
1606 if (ring->vmem_size && *ring->vmem) {
1607 vfree(*ring->vmem);
1608 *ring->vmem = NULL;
1609 }
1610 }
1611
1612 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1613 {
1614 int i;
1615 struct pci_dev *pdev = bp->pdev;
1616
1617 if (ring->nr_pages > 1) {
1618 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1619 ring->nr_pages * 8,
1620 &ring->pg_tbl_map,
1621 GFP_KERNEL);
1622 if (!ring->pg_tbl)
1623 return -ENOMEM;
1624 }
1625
1626 for (i = 0; i < ring->nr_pages; i++) {
1627 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1628 ring->page_size,
1629 &ring->dma_arr[i],
1630 GFP_KERNEL);
1631 if (!ring->pg_arr[i])
1632 return -ENOMEM;
1633
1634 if (ring->nr_pages > 1)
1635 ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1636 }
1637
1638 if (ring->vmem_size) {
1639 *ring->vmem = vzalloc(ring->vmem_size);
1640 if (!(*ring->vmem))
1641 return -ENOMEM;
1642 }
1643 return 0;
1644 }
1645
1646 static void bnxt_free_rx_rings(struct bnxt *bp)
1647 {
1648 int i;
1649
1650 if (!bp->rx_ring)
1651 return;
1652
1653 for (i = 0; i < bp->rx_nr_rings; i++) {
1654 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1655 struct bnxt_ring_struct *ring;
1656
1657 kfree(rxr->rx_tpa);
1658 rxr->rx_tpa = NULL;
1659
1660 kfree(rxr->rx_agg_bmap);
1661 rxr->rx_agg_bmap = NULL;
1662
1663 ring = &rxr->rx_ring_struct;
1664 bnxt_free_ring(bp, ring);
1665
1666 ring = &rxr->rx_agg_ring_struct;
1667 bnxt_free_ring(bp, ring);
1668 }
1669 }
1670
1671 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1672 {
1673 int i, rc, agg_rings = 0, tpa_rings = 0;
1674
1675 if (!bp->rx_ring)
1676 return -ENOMEM;
1677
1678 if (bp->flags & BNXT_FLAG_AGG_RINGS)
1679 agg_rings = 1;
1680
1681 if (bp->flags & BNXT_FLAG_TPA)
1682 tpa_rings = 1;
1683
1684 for (i = 0; i < bp->rx_nr_rings; i++) {
1685 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1686 struct bnxt_ring_struct *ring;
1687
1688 ring = &rxr->rx_ring_struct;
1689
1690 rc = bnxt_alloc_ring(bp, ring);
1691 if (rc)
1692 return rc;
1693
1694 if (agg_rings) {
1695 u16 mem_size;
1696
1697 ring = &rxr->rx_agg_ring_struct;
1698 rc = bnxt_alloc_ring(bp, ring);
1699 if (rc)
1700 return rc;
1701
1702 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1703 mem_size = rxr->rx_agg_bmap_size / 8;
1704 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1705 if (!rxr->rx_agg_bmap)
1706 return -ENOMEM;
1707
1708 if (tpa_rings) {
1709 rxr->rx_tpa = kcalloc(MAX_TPA,
1710 sizeof(struct bnxt_tpa_info),
1711 GFP_KERNEL);
1712 if (!rxr->rx_tpa)
1713 return -ENOMEM;
1714 }
1715 }
1716 }
1717 return 0;
1718 }
1719
1720 static void bnxt_free_tx_rings(struct bnxt *bp)
1721 {
1722 int i;
1723 struct pci_dev *pdev = bp->pdev;
1724
1725 if (!bp->tx_ring)
1726 return;
1727
1728 for (i = 0; i < bp->tx_nr_rings; i++) {
1729 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1730 struct bnxt_ring_struct *ring;
1731
1732 if (txr->tx_push) {
1733 dma_free_coherent(&pdev->dev, bp->tx_push_size,
1734 txr->tx_push, txr->tx_push_mapping);
1735 txr->tx_push = NULL;
1736 }
1737
1738 ring = &txr->tx_ring_struct;
1739
1740 bnxt_free_ring(bp, ring);
1741 }
1742 }
1743
1744 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1745 {
1746 int i, j, rc;
1747 struct pci_dev *pdev = bp->pdev;
1748
1749 bp->tx_push_size = 0;
1750 if (bp->tx_push_thresh) {
1751 int push_size;
1752
1753 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1754 bp->tx_push_thresh);
1755
1756 if (push_size > 128) {
1757 push_size = 0;
1758 bp->tx_push_thresh = 0;
1759 }
1760
1761 bp->tx_push_size = push_size;
1762 }
1763
1764 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1765 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1766 struct bnxt_ring_struct *ring;
1767
1768 ring = &txr->tx_ring_struct;
1769
1770 rc = bnxt_alloc_ring(bp, ring);
1771 if (rc)
1772 return rc;
1773
1774 if (bp->tx_push_size) {
1775 struct tx_bd *txbd;
1776 dma_addr_t mapping;
1777
1778 /* One pre-allocated DMA buffer to backup
1779 * TX push operation
1780 */
1781 txr->tx_push = dma_alloc_coherent(&pdev->dev,
1782 bp->tx_push_size,
1783 &txr->tx_push_mapping,
1784 GFP_KERNEL);
1785
1786 if (!txr->tx_push)
1787 return -ENOMEM;
1788
1789 txbd = &txr->tx_push->txbd1;
1790
1791 mapping = txr->tx_push_mapping +
1792 sizeof(struct tx_push_bd);
1793 txbd->tx_bd_haddr = cpu_to_le64(mapping);
1794
1795 memset(txbd + 1, 0, sizeof(struct tx_bd_ext));
1796 }
1797 ring->queue_id = bp->q_info[j].queue_id;
1798 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1799 j++;
1800 }
1801 return 0;
1802 }
1803
1804 static void bnxt_free_cp_rings(struct bnxt *bp)
1805 {
1806 int i;
1807
1808 if (!bp->bnapi)
1809 return;
1810
1811 for (i = 0; i < bp->cp_nr_rings; i++) {
1812 struct bnxt_napi *bnapi = bp->bnapi[i];
1813 struct bnxt_cp_ring_info *cpr;
1814 struct bnxt_ring_struct *ring;
1815
1816 if (!bnapi)
1817 continue;
1818
1819 cpr = &bnapi->cp_ring;
1820 ring = &cpr->cp_ring_struct;
1821
1822 bnxt_free_ring(bp, ring);
1823 }
1824 }
1825
1826 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1827 {
1828 int i, rc;
1829
1830 for (i = 0; i < bp->cp_nr_rings; i++) {
1831 struct bnxt_napi *bnapi = bp->bnapi[i];
1832 struct bnxt_cp_ring_info *cpr;
1833 struct bnxt_ring_struct *ring;
1834
1835 if (!bnapi)
1836 continue;
1837
1838 cpr = &bnapi->cp_ring;
1839 ring = &cpr->cp_ring_struct;
1840
1841 rc = bnxt_alloc_ring(bp, ring);
1842 if (rc)
1843 return rc;
1844 }
1845 return 0;
1846 }
1847
1848 static void bnxt_init_ring_struct(struct bnxt *bp)
1849 {
1850 int i;
1851
1852 for (i = 0; i < bp->cp_nr_rings; i++) {
1853 struct bnxt_napi *bnapi = bp->bnapi[i];
1854 struct bnxt_cp_ring_info *cpr;
1855 struct bnxt_rx_ring_info *rxr;
1856 struct bnxt_tx_ring_info *txr;
1857 struct bnxt_ring_struct *ring;
1858
1859 if (!bnapi)
1860 continue;
1861
1862 cpr = &bnapi->cp_ring;
1863 ring = &cpr->cp_ring_struct;
1864 ring->nr_pages = bp->cp_nr_pages;
1865 ring->page_size = HW_CMPD_RING_SIZE;
1866 ring->pg_arr = (void **)cpr->cp_desc_ring;
1867 ring->dma_arr = cpr->cp_desc_mapping;
1868 ring->vmem_size = 0;
1869
1870 rxr = bnapi->rx_ring;
1871 if (!rxr)
1872 goto skip_rx;
1873
1874 ring = &rxr->rx_ring_struct;
1875 ring->nr_pages = bp->rx_nr_pages;
1876 ring->page_size = HW_RXBD_RING_SIZE;
1877 ring->pg_arr = (void **)rxr->rx_desc_ring;
1878 ring->dma_arr = rxr->rx_desc_mapping;
1879 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1880 ring->vmem = (void **)&rxr->rx_buf_ring;
1881
1882 ring = &rxr->rx_agg_ring_struct;
1883 ring->nr_pages = bp->rx_agg_nr_pages;
1884 ring->page_size = HW_RXBD_RING_SIZE;
1885 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1886 ring->dma_arr = rxr->rx_agg_desc_mapping;
1887 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1888 ring->vmem = (void **)&rxr->rx_agg_ring;
1889
1890 skip_rx:
1891 txr = bnapi->tx_ring;
1892 if (!txr)
1893 continue;
1894
1895 ring = &txr->tx_ring_struct;
1896 ring->nr_pages = bp->tx_nr_pages;
1897 ring->page_size = HW_RXBD_RING_SIZE;
1898 ring->pg_arr = (void **)txr->tx_desc_ring;
1899 ring->dma_arr = txr->tx_desc_mapping;
1900 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1901 ring->vmem = (void **)&txr->tx_buf_ring;
1902 }
1903 }
1904
1905 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1906 {
1907 int i;
1908 u32 prod;
1909 struct rx_bd **rx_buf_ring;
1910
1911 rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1912 for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1913 int j;
1914 struct rx_bd *rxbd;
1915
1916 rxbd = rx_buf_ring[i];
1917 if (!rxbd)
1918 continue;
1919
1920 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1921 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1922 rxbd->rx_bd_opaque = prod;
1923 }
1924 }
1925 }
1926
1927 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1928 {
1929 struct net_device *dev = bp->dev;
1930 struct bnxt_rx_ring_info *rxr;
1931 struct bnxt_ring_struct *ring;
1932 u32 prod, type;
1933 int i;
1934
1935 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1936 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1937
1938 if (NET_IP_ALIGN == 2)
1939 type |= RX_BD_FLAGS_SOP;
1940
1941 rxr = &bp->rx_ring[ring_nr];
1942 ring = &rxr->rx_ring_struct;
1943 bnxt_init_rxbd_pages(ring, type);
1944
1945 prod = rxr->rx_prod;
1946 for (i = 0; i < bp->rx_ring_size; i++) {
1947 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1948 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1949 ring_nr, i, bp->rx_ring_size);
1950 break;
1951 }
1952 prod = NEXT_RX(prod);
1953 }
1954 rxr->rx_prod = prod;
1955 ring->fw_ring_id = INVALID_HW_RING_ID;
1956
1957 ring = &rxr->rx_agg_ring_struct;
1958 ring->fw_ring_id = INVALID_HW_RING_ID;
1959
1960 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1961 return 0;
1962
1963 type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1964 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1965
1966 bnxt_init_rxbd_pages(ring, type);
1967
1968 prod = rxr->rx_agg_prod;
1969 for (i = 0; i < bp->rx_agg_ring_size; i++) {
1970 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1971 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1972 ring_nr, i, bp->rx_ring_size);
1973 break;
1974 }
1975 prod = NEXT_RX_AGG(prod);
1976 }
1977 rxr->rx_agg_prod = prod;
1978
1979 if (bp->flags & BNXT_FLAG_TPA) {
1980 if (rxr->rx_tpa) {
1981 u8 *data;
1982 dma_addr_t mapping;
1983
1984 for (i = 0; i < MAX_TPA; i++) {
1985 data = __bnxt_alloc_rx_data(bp, &mapping,
1986 GFP_KERNEL);
1987 if (!data)
1988 return -ENOMEM;
1989
1990 rxr->rx_tpa[i].data = data;
1991 rxr->rx_tpa[i].mapping = mapping;
1992 }
1993 } else {
1994 netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
1995 return -ENOMEM;
1996 }
1997 }
1998
1999 return 0;
2000 }
2001
2002 static int bnxt_init_rx_rings(struct bnxt *bp)
2003 {
2004 int i, rc = 0;
2005
2006 for (i = 0; i < bp->rx_nr_rings; i++) {
2007 rc = bnxt_init_one_rx_ring(bp, i);
2008 if (rc)
2009 break;
2010 }
2011
2012 return rc;
2013 }
2014
2015 static int bnxt_init_tx_rings(struct bnxt *bp)
2016 {
2017 u16 i;
2018
2019 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2020 MAX_SKB_FRAGS + 1);
2021
2022 for (i = 0; i < bp->tx_nr_rings; i++) {
2023 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2024 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2025
2026 ring->fw_ring_id = INVALID_HW_RING_ID;
2027 }
2028
2029 return 0;
2030 }
2031
2032 static void bnxt_free_ring_grps(struct bnxt *bp)
2033 {
2034 kfree(bp->grp_info);
2035 bp->grp_info = NULL;
2036 }
2037
2038 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2039 {
2040 int i;
2041
2042 if (irq_re_init) {
2043 bp->grp_info = kcalloc(bp->cp_nr_rings,
2044 sizeof(struct bnxt_ring_grp_info),
2045 GFP_KERNEL);
2046 if (!bp->grp_info)
2047 return -ENOMEM;
2048 }
2049 for (i = 0; i < bp->cp_nr_rings; i++) {
2050 if (irq_re_init)
2051 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2052 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2053 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2054 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2055 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2056 }
2057 return 0;
2058 }
2059
2060 static void bnxt_free_vnics(struct bnxt *bp)
2061 {
2062 kfree(bp->vnic_info);
2063 bp->vnic_info = NULL;
2064 bp->nr_vnics = 0;
2065 }
2066
2067 static int bnxt_alloc_vnics(struct bnxt *bp)
2068 {
2069 int num_vnics = 1;
2070
2071 #ifdef CONFIG_RFS_ACCEL
2072 if (bp->flags & BNXT_FLAG_RFS)
2073 num_vnics += bp->rx_nr_rings;
2074 #endif
2075
2076 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2077 GFP_KERNEL);
2078 if (!bp->vnic_info)
2079 return -ENOMEM;
2080
2081 bp->nr_vnics = num_vnics;
2082 return 0;
2083 }
2084
2085 static void bnxt_init_vnics(struct bnxt *bp)
2086 {
2087 int i;
2088
2089 for (i = 0; i < bp->nr_vnics; i++) {
2090 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2091
2092 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2093 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2094 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2095
2096 if (bp->vnic_info[i].rss_hash_key) {
2097 if (i == 0)
2098 prandom_bytes(vnic->rss_hash_key,
2099 HW_HASH_KEY_SIZE);
2100 else
2101 memcpy(vnic->rss_hash_key,
2102 bp->vnic_info[0].rss_hash_key,
2103 HW_HASH_KEY_SIZE);
2104 }
2105 }
2106 }
2107
2108 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2109 {
2110 int pages;
2111
2112 pages = ring_size / desc_per_pg;
2113
2114 if (!pages)
2115 return 1;
2116
2117 pages++;
2118
2119 while (pages & (pages - 1))
2120 pages++;
2121
2122 return pages;
2123 }
2124
2125 static void bnxt_set_tpa_flags(struct bnxt *bp)
2126 {
2127 bp->flags &= ~BNXT_FLAG_TPA;
2128 if (bp->dev->features & NETIF_F_LRO)
2129 bp->flags |= BNXT_FLAG_LRO;
2130 if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2131 bp->flags |= BNXT_FLAG_GRO;
2132 }
2133
2134 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2135 * be set on entry.
2136 */
2137 void bnxt_set_ring_params(struct bnxt *bp)
2138 {
2139 u32 ring_size, rx_size, rx_space;
2140 u32 agg_factor = 0, agg_ring_size = 0;
2141
2142 /* 8 for CRC and VLAN */
2143 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2144
2145 rx_space = rx_size + NET_SKB_PAD +
2146 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2147
2148 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2149 ring_size = bp->rx_ring_size;
2150 bp->rx_agg_ring_size = 0;
2151 bp->rx_agg_nr_pages = 0;
2152
2153 if (bp->flags & BNXT_FLAG_TPA)
2154 agg_factor = 4;
2155
2156 bp->flags &= ~BNXT_FLAG_JUMBO;
2157 if (rx_space > PAGE_SIZE) {
2158 u32 jumbo_factor;
2159
2160 bp->flags |= BNXT_FLAG_JUMBO;
2161 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2162 if (jumbo_factor > agg_factor)
2163 agg_factor = jumbo_factor;
2164 }
2165 agg_ring_size = ring_size * agg_factor;
2166
2167 if (agg_ring_size) {
2168 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2169 RX_DESC_CNT);
2170 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2171 u32 tmp = agg_ring_size;
2172
2173 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2174 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2175 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2176 tmp, agg_ring_size);
2177 }
2178 bp->rx_agg_ring_size = agg_ring_size;
2179 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2180 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2181 rx_space = rx_size + NET_SKB_PAD +
2182 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2183 }
2184
2185 bp->rx_buf_use_size = rx_size;
2186 bp->rx_buf_size = rx_space;
2187
2188 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2189 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2190
2191 ring_size = bp->tx_ring_size;
2192 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2193 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2194
2195 ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2196 bp->cp_ring_size = ring_size;
2197
2198 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2199 if (bp->cp_nr_pages > MAX_CP_PAGES) {
2200 bp->cp_nr_pages = MAX_CP_PAGES;
2201 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2202 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2203 ring_size, bp->cp_ring_size);
2204 }
2205 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2206 bp->cp_ring_mask = bp->cp_bit - 1;
2207 }
2208
2209 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2210 {
2211 int i;
2212 struct bnxt_vnic_info *vnic;
2213 struct pci_dev *pdev = bp->pdev;
2214
2215 if (!bp->vnic_info)
2216 return;
2217
2218 for (i = 0; i < bp->nr_vnics; i++) {
2219 vnic = &bp->vnic_info[i];
2220
2221 kfree(vnic->fw_grp_ids);
2222 vnic->fw_grp_ids = NULL;
2223
2224 kfree(vnic->uc_list);
2225 vnic->uc_list = NULL;
2226
2227 if (vnic->mc_list) {
2228 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2229 vnic->mc_list, vnic->mc_list_mapping);
2230 vnic->mc_list = NULL;
2231 }
2232
2233 if (vnic->rss_table) {
2234 dma_free_coherent(&pdev->dev, PAGE_SIZE,
2235 vnic->rss_table,
2236 vnic->rss_table_dma_addr);
2237 vnic->rss_table = NULL;
2238 }
2239
2240 vnic->rss_hash_key = NULL;
2241 vnic->flags = 0;
2242 }
2243 }
2244
2245 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2246 {
2247 int i, rc = 0, size;
2248 struct bnxt_vnic_info *vnic;
2249 struct pci_dev *pdev = bp->pdev;
2250 int max_rings;
2251
2252 for (i = 0; i < bp->nr_vnics; i++) {
2253 vnic = &bp->vnic_info[i];
2254
2255 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2256 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2257
2258 if (mem_size > 0) {
2259 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2260 if (!vnic->uc_list) {
2261 rc = -ENOMEM;
2262 goto out;
2263 }
2264 }
2265 }
2266
2267 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2268 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2269 vnic->mc_list =
2270 dma_alloc_coherent(&pdev->dev,
2271 vnic->mc_list_size,
2272 &vnic->mc_list_mapping,
2273 GFP_KERNEL);
2274 if (!vnic->mc_list) {
2275 rc = -ENOMEM;
2276 goto out;
2277 }
2278 }
2279
2280 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2281 max_rings = bp->rx_nr_rings;
2282 else
2283 max_rings = 1;
2284
2285 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2286 if (!vnic->fw_grp_ids) {
2287 rc = -ENOMEM;
2288 goto out;
2289 }
2290
2291 /* Allocate rss table and hash key */
2292 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2293 &vnic->rss_table_dma_addr,
2294 GFP_KERNEL);
2295 if (!vnic->rss_table) {
2296 rc = -ENOMEM;
2297 goto out;
2298 }
2299
2300 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2301
2302 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2303 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2304 }
2305 return 0;
2306
2307 out:
2308 return rc;
2309 }
2310
2311 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2312 {
2313 struct pci_dev *pdev = bp->pdev;
2314
2315 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2316 bp->hwrm_cmd_resp_dma_addr);
2317
2318 bp->hwrm_cmd_resp_addr = NULL;
2319 if (bp->hwrm_dbg_resp_addr) {
2320 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2321 bp->hwrm_dbg_resp_addr,
2322 bp->hwrm_dbg_resp_dma_addr);
2323
2324 bp->hwrm_dbg_resp_addr = NULL;
2325 }
2326 }
2327
2328 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2329 {
2330 struct pci_dev *pdev = bp->pdev;
2331
2332 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2333 &bp->hwrm_cmd_resp_dma_addr,
2334 GFP_KERNEL);
2335 if (!bp->hwrm_cmd_resp_addr)
2336 return -ENOMEM;
2337 bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2338 HWRM_DBG_REG_BUF_SIZE,
2339 &bp->hwrm_dbg_resp_dma_addr,
2340 GFP_KERNEL);
2341 if (!bp->hwrm_dbg_resp_addr)
2342 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2343
2344 return 0;
2345 }
2346
2347 static void bnxt_free_stats(struct bnxt *bp)
2348 {
2349 u32 size, i;
2350 struct pci_dev *pdev = bp->pdev;
2351
2352 if (!bp->bnapi)
2353 return;
2354
2355 size = sizeof(struct ctx_hw_stats);
2356
2357 for (i = 0; i < bp->cp_nr_rings; i++) {
2358 struct bnxt_napi *bnapi = bp->bnapi[i];
2359 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2360
2361 if (cpr->hw_stats) {
2362 dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2363 cpr->hw_stats_map);
2364 cpr->hw_stats = NULL;
2365 }
2366 }
2367 }
2368
2369 static int bnxt_alloc_stats(struct bnxt *bp)
2370 {
2371 u32 size, i;
2372 struct pci_dev *pdev = bp->pdev;
2373
2374 size = sizeof(struct ctx_hw_stats);
2375
2376 for (i = 0; i < bp->cp_nr_rings; i++) {
2377 struct bnxt_napi *bnapi = bp->bnapi[i];
2378 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2379
2380 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2381 &cpr->hw_stats_map,
2382 GFP_KERNEL);
2383 if (!cpr->hw_stats)
2384 return -ENOMEM;
2385
2386 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2387 }
2388 return 0;
2389 }
2390
2391 static void bnxt_clear_ring_indices(struct bnxt *bp)
2392 {
2393 int i;
2394
2395 if (!bp->bnapi)
2396 return;
2397
2398 for (i = 0; i < bp->cp_nr_rings; i++) {
2399 struct bnxt_napi *bnapi = bp->bnapi[i];
2400 struct bnxt_cp_ring_info *cpr;
2401 struct bnxt_rx_ring_info *rxr;
2402 struct bnxt_tx_ring_info *txr;
2403
2404 if (!bnapi)
2405 continue;
2406
2407 cpr = &bnapi->cp_ring;
2408 cpr->cp_raw_cons = 0;
2409
2410 txr = bnapi->tx_ring;
2411 if (txr) {
2412 txr->tx_prod = 0;
2413 txr->tx_cons = 0;
2414 }
2415
2416 rxr = bnapi->rx_ring;
2417 if (rxr) {
2418 rxr->rx_prod = 0;
2419 rxr->rx_agg_prod = 0;
2420 rxr->rx_sw_agg_prod = 0;
2421 }
2422 }
2423 }
2424
2425 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2426 {
2427 #ifdef CONFIG_RFS_ACCEL
2428 int i;
2429
2430 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2431 * safe to delete the hash table.
2432 */
2433 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2434 struct hlist_head *head;
2435 struct hlist_node *tmp;
2436 struct bnxt_ntuple_filter *fltr;
2437
2438 head = &bp->ntp_fltr_hash_tbl[i];
2439 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2440 hlist_del(&fltr->hash);
2441 kfree(fltr);
2442 }
2443 }
2444 if (irq_reinit) {
2445 kfree(bp->ntp_fltr_bmap);
2446 bp->ntp_fltr_bmap = NULL;
2447 }
2448 bp->ntp_fltr_count = 0;
2449 #endif
2450 }
2451
2452 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2453 {
2454 #ifdef CONFIG_RFS_ACCEL
2455 int i, rc = 0;
2456
2457 if (!(bp->flags & BNXT_FLAG_RFS))
2458 return 0;
2459
2460 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2461 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2462
2463 bp->ntp_fltr_count = 0;
2464 bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2465 GFP_KERNEL);
2466
2467 if (!bp->ntp_fltr_bmap)
2468 rc = -ENOMEM;
2469
2470 return rc;
2471 #else
2472 return 0;
2473 #endif
2474 }
2475
2476 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2477 {
2478 bnxt_free_vnic_attributes(bp);
2479 bnxt_free_tx_rings(bp);
2480 bnxt_free_rx_rings(bp);
2481 bnxt_free_cp_rings(bp);
2482 bnxt_free_ntp_fltrs(bp, irq_re_init);
2483 if (irq_re_init) {
2484 bnxt_free_stats(bp);
2485 bnxt_free_ring_grps(bp);
2486 bnxt_free_vnics(bp);
2487 kfree(bp->tx_ring);
2488 bp->tx_ring = NULL;
2489 kfree(bp->rx_ring);
2490 bp->rx_ring = NULL;
2491 kfree(bp->bnapi);
2492 bp->bnapi = NULL;
2493 } else {
2494 bnxt_clear_ring_indices(bp);
2495 }
2496 }
2497
2498 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2499 {
2500 int i, j, rc, size, arr_size;
2501 void *bnapi;
2502
2503 if (irq_re_init) {
2504 /* Allocate bnapi mem pointer array and mem block for
2505 * all queues
2506 */
2507 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2508 bp->cp_nr_rings);
2509 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2510 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2511 if (!bnapi)
2512 return -ENOMEM;
2513
2514 bp->bnapi = bnapi;
2515 bnapi += arr_size;
2516 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2517 bp->bnapi[i] = bnapi;
2518 bp->bnapi[i]->index = i;
2519 bp->bnapi[i]->bp = bp;
2520 }
2521
2522 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2523 sizeof(struct bnxt_rx_ring_info),
2524 GFP_KERNEL);
2525 if (!bp->rx_ring)
2526 return -ENOMEM;
2527
2528 for (i = 0; i < bp->rx_nr_rings; i++) {
2529 bp->rx_ring[i].bnapi = bp->bnapi[i];
2530 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2531 }
2532
2533 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2534 sizeof(struct bnxt_tx_ring_info),
2535 GFP_KERNEL);
2536 if (!bp->tx_ring)
2537 return -ENOMEM;
2538
2539 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2540 j = 0;
2541 else
2542 j = bp->rx_nr_rings;
2543
2544 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2545 bp->tx_ring[i].bnapi = bp->bnapi[j];
2546 bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2547 }
2548
2549 rc = bnxt_alloc_stats(bp);
2550 if (rc)
2551 goto alloc_mem_err;
2552
2553 rc = bnxt_alloc_ntp_fltrs(bp);
2554 if (rc)
2555 goto alloc_mem_err;
2556
2557 rc = bnxt_alloc_vnics(bp);
2558 if (rc)
2559 goto alloc_mem_err;
2560 }
2561
2562 bnxt_init_ring_struct(bp);
2563
2564 rc = bnxt_alloc_rx_rings(bp);
2565 if (rc)
2566 goto alloc_mem_err;
2567
2568 rc = bnxt_alloc_tx_rings(bp);
2569 if (rc)
2570 goto alloc_mem_err;
2571
2572 rc = bnxt_alloc_cp_rings(bp);
2573 if (rc)
2574 goto alloc_mem_err;
2575
2576 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2577 BNXT_VNIC_UCAST_FLAG;
2578 rc = bnxt_alloc_vnic_attributes(bp);
2579 if (rc)
2580 goto alloc_mem_err;
2581 return 0;
2582
2583 alloc_mem_err:
2584 bnxt_free_mem(bp, true);
2585 return rc;
2586 }
2587
2588 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2589 u16 cmpl_ring, u16 target_id)
2590 {
2591 struct hwrm_cmd_req_hdr *req = request;
2592
2593 req->cmpl_ring_req_type =
2594 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2595 req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2596 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2597 }
2598
2599 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2600 {
2601 int i, intr_process, rc;
2602 struct hwrm_cmd_req_hdr *req = msg;
2603 u32 *data = msg;
2604 __le32 *resp_len, *valid;
2605 u16 cp_ring_id, len = 0;
2606 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2607
2608 req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2609 memset(resp, 0, PAGE_SIZE);
2610 cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2611 HWRM_CMPL_RING_MASK) >>
2612 HWRM_CMPL_RING_SFT;
2613 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2614
2615 /* Write request msg to hwrm channel */
2616 __iowrite32_copy(bp->bar0, data, msg_len / 4);
2617
2618 for (i = msg_len; i < HWRM_MAX_REQ_LEN; i += 4)
2619 writel(0, bp->bar0 + i);
2620
2621 /* currently supports only one outstanding message */
2622 if (intr_process)
2623 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2624 HWRM_SEQ_ID_MASK;
2625
2626 /* Ring channel doorbell */
2627 writel(1, bp->bar0 + 0x100);
2628
2629 i = 0;
2630 if (intr_process) {
2631 /* Wait until hwrm response cmpl interrupt is processed */
2632 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2633 i++ < timeout) {
2634 usleep_range(600, 800);
2635 }
2636
2637 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2638 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2639 req->cmpl_ring_req_type);
2640 return -1;
2641 }
2642 } else {
2643 /* Check if response len is updated */
2644 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2645 for (i = 0; i < timeout; i++) {
2646 len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2647 HWRM_RESP_LEN_SFT;
2648 if (len)
2649 break;
2650 usleep_range(600, 800);
2651 }
2652
2653 if (i >= timeout) {
2654 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2655 timeout, req->cmpl_ring_req_type,
2656 req->target_id_seq_id, *resp_len);
2657 return -1;
2658 }
2659
2660 /* Last word of resp contains valid bit */
2661 valid = bp->hwrm_cmd_resp_addr + len - 4;
2662 for (i = 0; i < timeout; i++) {
2663 if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2664 break;
2665 usleep_range(600, 800);
2666 }
2667
2668 if (i >= timeout) {
2669 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2670 timeout, req->cmpl_ring_req_type,
2671 req->target_id_seq_id, len, *valid);
2672 return -1;
2673 }
2674 }
2675
2676 rc = le16_to_cpu(resp->error_code);
2677 if (rc) {
2678 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2679 le16_to_cpu(resp->req_type),
2680 le16_to_cpu(resp->seq_id), rc);
2681 return rc;
2682 }
2683 return 0;
2684 }
2685
2686 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2687 {
2688 int rc;
2689
2690 mutex_lock(&bp->hwrm_cmd_lock);
2691 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2692 mutex_unlock(&bp->hwrm_cmd_lock);
2693 return rc;
2694 }
2695
2696 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2697 {
2698 struct hwrm_func_drv_rgtr_input req = {0};
2699 int i;
2700
2701 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2702
2703 req.enables =
2704 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2705 FUNC_DRV_RGTR_REQ_ENABLES_VER |
2706 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2707
2708 /* TODO: current async event fwd bits are not defined and the firmware
2709 * only checks if it is non-zero to enable async event forwarding
2710 */
2711 req.async_event_fwd[0] |= cpu_to_le32(1);
2712 req.os_type = cpu_to_le16(1);
2713 req.ver_maj = DRV_VER_MAJ;
2714 req.ver_min = DRV_VER_MIN;
2715 req.ver_upd = DRV_VER_UPD;
2716
2717 if (BNXT_PF(bp)) {
2718 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2719 u32 *data = (u32 *)vf_req_snif_bmap;
2720
2721 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2722 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2723 __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2724
2725 for (i = 0; i < 8; i++)
2726 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2727
2728 req.enables |=
2729 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2730 }
2731
2732 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2733 }
2734
2735 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2736 {
2737 struct hwrm_func_drv_unrgtr_input req = {0};
2738
2739 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2740 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2741 }
2742
2743 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2744 {
2745 u32 rc = 0;
2746 struct hwrm_tunnel_dst_port_free_input req = {0};
2747
2748 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2749 req.tunnel_type = tunnel_type;
2750
2751 switch (tunnel_type) {
2752 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2753 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2754 break;
2755 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2756 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2757 break;
2758 default:
2759 break;
2760 }
2761
2762 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2763 if (rc)
2764 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2765 rc);
2766 return rc;
2767 }
2768
2769 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2770 u8 tunnel_type)
2771 {
2772 u32 rc = 0;
2773 struct hwrm_tunnel_dst_port_alloc_input req = {0};
2774 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2775
2776 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2777
2778 req.tunnel_type = tunnel_type;
2779 req.tunnel_dst_port_val = port;
2780
2781 mutex_lock(&bp->hwrm_cmd_lock);
2782 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2783 if (rc) {
2784 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2785 rc);
2786 goto err_out;
2787 }
2788
2789 if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2790 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2791
2792 else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2793 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2794 err_out:
2795 mutex_unlock(&bp->hwrm_cmd_lock);
2796 return rc;
2797 }
2798
2799 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2800 {
2801 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2802 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2803
2804 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2805 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2806
2807 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2808 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2809 req.mask = cpu_to_le32(vnic->rx_mask);
2810 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2811 }
2812
2813 #ifdef CONFIG_RFS_ACCEL
2814 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2815 struct bnxt_ntuple_filter *fltr)
2816 {
2817 struct hwrm_cfa_ntuple_filter_free_input req = {0};
2818
2819 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2820 req.ntuple_filter_id = fltr->filter_id;
2821 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2822 }
2823
2824 #define BNXT_NTP_FLTR_FLAGS \
2825 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2826 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2827 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2828 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2829 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2830 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2831 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2832 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2833 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2834 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2835 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2836 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2837 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2838 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2839
2840 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2841 struct bnxt_ntuple_filter *fltr)
2842 {
2843 int rc = 0;
2844 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2845 struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2846 bp->hwrm_cmd_resp_addr;
2847 struct flow_keys *keys = &fltr->fkeys;
2848 struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2849
2850 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2851 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2852
2853 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2854
2855 req.ethertype = htons(ETH_P_IP);
2856 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2857 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
2858 req.ip_protocol = keys->basic.ip_proto;
2859
2860 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2861 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2862 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2863 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2864
2865 req.src_port = keys->ports.src;
2866 req.src_port_mask = cpu_to_be16(0xffff);
2867 req.dst_port = keys->ports.dst;
2868 req.dst_port_mask = cpu_to_be16(0xffff);
2869
2870 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
2871 mutex_lock(&bp->hwrm_cmd_lock);
2872 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2873 if (!rc)
2874 fltr->filter_id = resp->ntuple_filter_id;
2875 mutex_unlock(&bp->hwrm_cmd_lock);
2876 return rc;
2877 }
2878 #endif
2879
2880 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2881 u8 *mac_addr)
2882 {
2883 u32 rc = 0;
2884 struct hwrm_cfa_l2_filter_alloc_input req = {0};
2885 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2886
2887 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2888 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2889 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2890 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2891 req.enables =
2892 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2893 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
2894 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2895 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2896 req.l2_addr_mask[0] = 0xff;
2897 req.l2_addr_mask[1] = 0xff;
2898 req.l2_addr_mask[2] = 0xff;
2899 req.l2_addr_mask[3] = 0xff;
2900 req.l2_addr_mask[4] = 0xff;
2901 req.l2_addr_mask[5] = 0xff;
2902
2903 mutex_lock(&bp->hwrm_cmd_lock);
2904 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2905 if (!rc)
2906 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2907 resp->l2_filter_id;
2908 mutex_unlock(&bp->hwrm_cmd_lock);
2909 return rc;
2910 }
2911
2912 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2913 {
2914 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2915 int rc = 0;
2916
2917 /* Any associated ntuple filters will also be cleared by firmware. */
2918 mutex_lock(&bp->hwrm_cmd_lock);
2919 for (i = 0; i < num_of_vnics; i++) {
2920 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2921
2922 for (j = 0; j < vnic->uc_filter_count; j++) {
2923 struct hwrm_cfa_l2_filter_free_input req = {0};
2924
2925 bnxt_hwrm_cmd_hdr_init(bp, &req,
2926 HWRM_CFA_L2_FILTER_FREE, -1, -1);
2927
2928 req.l2_filter_id = vnic->fw_l2_filter_id[j];
2929
2930 rc = _hwrm_send_message(bp, &req, sizeof(req),
2931 HWRM_CMD_TIMEOUT);
2932 }
2933 vnic->uc_filter_count = 0;
2934 }
2935 mutex_unlock(&bp->hwrm_cmd_lock);
2936
2937 return rc;
2938 }
2939
2940 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2941 {
2942 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2943 struct hwrm_vnic_tpa_cfg_input req = {0};
2944
2945 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2946
2947 if (tpa_flags) {
2948 u16 mss = bp->dev->mtu - 40;
2949 u32 nsegs, n, segs = 0, flags;
2950
2951 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2952 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2953 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2954 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2955 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2956 if (tpa_flags & BNXT_FLAG_GRO)
2957 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2958
2959 req.flags = cpu_to_le32(flags);
2960
2961 req.enables =
2962 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
2963 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
2964 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
2965
2966 /* Number of segs are log2 units, and first packet is not
2967 * included as part of this units.
2968 */
2969 if (mss <= PAGE_SIZE) {
2970 n = PAGE_SIZE / mss;
2971 nsegs = (MAX_SKB_FRAGS - 1) * n;
2972 } else {
2973 n = mss / PAGE_SIZE;
2974 if (mss & (PAGE_SIZE - 1))
2975 n++;
2976 nsegs = (MAX_SKB_FRAGS - n) / n;
2977 }
2978
2979 segs = ilog2(nsegs);
2980 req.max_agg_segs = cpu_to_le16(segs);
2981 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
2982
2983 req.min_agg_len = cpu_to_le32(512);
2984 }
2985 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2986
2987 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2988 }
2989
2990 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
2991 {
2992 u32 i, j, max_rings;
2993 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2994 struct hwrm_vnic_rss_cfg_input req = {0};
2995
2996 if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
2997 return 0;
2998
2999 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3000 if (set_rss) {
3001 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3002 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3003 BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3004 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3005
3006 req.hash_type = cpu_to_le32(vnic->hash_type);
3007
3008 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3009 max_rings = bp->rx_nr_rings;
3010 else
3011 max_rings = 1;
3012
3013 /* Fill the RSS indirection table with ring group ids */
3014 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3015 if (j == max_rings)
3016 j = 0;
3017 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3018 }
3019
3020 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3021 req.hash_key_tbl_addr =
3022 cpu_to_le64(vnic->rss_hash_key_dma_addr);
3023 }
3024 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3025 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3026 }
3027
3028 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3029 {
3030 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3031 struct hwrm_vnic_plcmodes_cfg_input req = {0};
3032
3033 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3034 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3035 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3036 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3037 req.enables =
3038 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3039 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3040 /* thresholds not implemented in firmware yet */
3041 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3042 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3043 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3044 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3045 }
3046
3047 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3048 {
3049 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3050
3051 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3052 req.rss_cos_lb_ctx_id =
3053 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3054
3055 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3056 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3057 }
3058
3059 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3060 {
3061 int i;
3062
3063 for (i = 0; i < bp->nr_vnics; i++) {
3064 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3065
3066 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3067 bnxt_hwrm_vnic_ctx_free_one(bp, i);
3068 }
3069 bp->rsscos_nr_ctxs = 0;
3070 }
3071
3072 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3073 {
3074 int rc;
3075 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3076 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3077 bp->hwrm_cmd_resp_addr;
3078
3079 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3080 -1);
3081
3082 mutex_lock(&bp->hwrm_cmd_lock);
3083 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3084 if (!rc)
3085 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3086 le16_to_cpu(resp->rss_cos_lb_ctx_id);
3087 mutex_unlock(&bp->hwrm_cmd_lock);
3088
3089 return rc;
3090 }
3091
3092 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3093 {
3094 unsigned int ring = 0, grp_idx;
3095 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3096 struct hwrm_vnic_cfg_input req = {0};
3097
3098 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3099 /* Only RSS support for now TBD: COS & LB */
3100 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3101 VNIC_CFG_REQ_ENABLES_RSS_RULE);
3102 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3103 req.cos_rule = cpu_to_le16(0xffff);
3104 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3105 ring = 0;
3106 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3107 ring = vnic_id - 1;
3108
3109 grp_idx = bp->rx_ring[ring].bnapi->index;
3110 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3111 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3112
3113 req.lb_rule = cpu_to_le16(0xffff);
3114 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3115 VLAN_HLEN);
3116
3117 if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3118 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3119
3120 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3121 }
3122
3123 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3124 {
3125 u32 rc = 0;
3126
3127 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3128 struct hwrm_vnic_free_input req = {0};
3129
3130 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3131 req.vnic_id =
3132 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3133
3134 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3135 if (rc)
3136 return rc;
3137 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3138 }
3139 return rc;
3140 }
3141
3142 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3143 {
3144 u16 i;
3145
3146 for (i = 0; i < bp->nr_vnics; i++)
3147 bnxt_hwrm_vnic_free_one(bp, i);
3148 }
3149
3150 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3151 unsigned int start_rx_ring_idx,
3152 unsigned int nr_rings)
3153 {
3154 int rc = 0;
3155 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3156 struct hwrm_vnic_alloc_input req = {0};
3157 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3158
3159 /* map ring groups to this vnic */
3160 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3161 grp_idx = bp->rx_ring[i].bnapi->index;
3162 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3163 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3164 j, nr_rings);
3165 break;
3166 }
3167 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3168 bp->grp_info[grp_idx].fw_grp_id;
3169 }
3170
3171 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3172 if (vnic_id == 0)
3173 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3174
3175 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3176
3177 mutex_lock(&bp->hwrm_cmd_lock);
3178 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3179 if (!rc)
3180 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3181 mutex_unlock(&bp->hwrm_cmd_lock);
3182 return rc;
3183 }
3184
3185 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3186 {
3187 u16 i;
3188 u32 rc = 0;
3189
3190 mutex_lock(&bp->hwrm_cmd_lock);
3191 for (i = 0; i < bp->rx_nr_rings; i++) {
3192 struct hwrm_ring_grp_alloc_input req = {0};
3193 struct hwrm_ring_grp_alloc_output *resp =
3194 bp->hwrm_cmd_resp_addr;
3195 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3196
3197 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3198
3199 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3200 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3201 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3202 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3203
3204 rc = _hwrm_send_message(bp, &req, sizeof(req),
3205 HWRM_CMD_TIMEOUT);
3206 if (rc)
3207 break;
3208
3209 bp->grp_info[grp_idx].fw_grp_id =
3210 le32_to_cpu(resp->ring_group_id);
3211 }
3212 mutex_unlock(&bp->hwrm_cmd_lock);
3213 return rc;
3214 }
3215
3216 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3217 {
3218 u16 i;
3219 u32 rc = 0;
3220 struct hwrm_ring_grp_free_input req = {0};
3221
3222 if (!bp->grp_info)
3223 return 0;
3224
3225 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3226
3227 mutex_lock(&bp->hwrm_cmd_lock);
3228 for (i = 0; i < bp->cp_nr_rings; i++) {
3229 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3230 continue;
3231 req.ring_group_id =
3232 cpu_to_le32(bp->grp_info[i].fw_grp_id);
3233
3234 rc = _hwrm_send_message(bp, &req, sizeof(req),
3235 HWRM_CMD_TIMEOUT);
3236 if (rc)
3237 break;
3238 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3239 }
3240 mutex_unlock(&bp->hwrm_cmd_lock);
3241 return rc;
3242 }
3243
3244 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3245 struct bnxt_ring_struct *ring,
3246 u32 ring_type, u32 map_index,
3247 u32 stats_ctx_id)
3248 {
3249 int rc = 0, err = 0;
3250 struct hwrm_ring_alloc_input req = {0};
3251 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3252 u16 ring_id;
3253
3254 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3255
3256 req.enables = 0;
3257 if (ring->nr_pages > 1) {
3258 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3259 /* Page size is in log2 units */
3260 req.page_size = BNXT_PAGE_SHIFT;
3261 req.page_tbl_depth = 1;
3262 } else {
3263 req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]);
3264 }
3265 req.fbo = 0;
3266 /* Association of ring index with doorbell index and MSIX number */
3267 req.logical_id = cpu_to_le16(map_index);
3268
3269 switch (ring_type) {
3270 case HWRM_RING_ALLOC_TX:
3271 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3272 /* Association of transmit ring with completion ring */
3273 req.cmpl_ring_id =
3274 cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3275 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3276 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3277 req.queue_id = cpu_to_le16(ring->queue_id);
3278 break;
3279 case HWRM_RING_ALLOC_RX:
3280 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3281 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3282 break;
3283 case HWRM_RING_ALLOC_AGG:
3284 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3285 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3286 break;
3287 case HWRM_RING_ALLOC_CMPL:
3288 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3289 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3290 if (bp->flags & BNXT_FLAG_USING_MSIX)
3291 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3292 break;
3293 default:
3294 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3295 ring_type);
3296 return -1;
3297 }
3298
3299 mutex_lock(&bp->hwrm_cmd_lock);
3300 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3301 err = le16_to_cpu(resp->error_code);
3302 ring_id = le16_to_cpu(resp->ring_id);
3303 mutex_unlock(&bp->hwrm_cmd_lock);
3304
3305 if (rc || err) {
3306 switch (ring_type) {
3307 case RING_FREE_REQ_RING_TYPE_CMPL:
3308 netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3309 rc, err);
3310 return -1;
3311
3312 case RING_FREE_REQ_RING_TYPE_RX:
3313 netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3314 rc, err);
3315 return -1;
3316
3317 case RING_FREE_REQ_RING_TYPE_TX:
3318 netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3319 rc, err);
3320 return -1;
3321
3322 default:
3323 netdev_err(bp->dev, "Invalid ring\n");
3324 return -1;
3325 }
3326 }
3327 ring->fw_ring_id = ring_id;
3328 return rc;
3329 }
3330
3331 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3332 {
3333 int i, rc = 0;
3334
3335 for (i = 0; i < bp->cp_nr_rings; i++) {
3336 struct bnxt_napi *bnapi = bp->bnapi[i];
3337 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3338 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3339
3340 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3341 INVALID_STATS_CTX_ID);
3342 if (rc)
3343 goto err_out;
3344 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3345 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3346 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3347 }
3348
3349 for (i = 0; i < bp->tx_nr_rings; i++) {
3350 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3351 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3352 u32 map_idx = txr->bnapi->index;
3353 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3354
3355 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3356 map_idx, fw_stats_ctx);
3357 if (rc)
3358 goto err_out;
3359 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3360 }
3361
3362 for (i = 0; i < bp->rx_nr_rings; i++) {
3363 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3364 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3365 u32 map_idx = rxr->bnapi->index;
3366
3367 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3368 map_idx, INVALID_STATS_CTX_ID);
3369 if (rc)
3370 goto err_out;
3371 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3372 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3373 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3374 }
3375
3376 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3377 for (i = 0; i < bp->rx_nr_rings; i++) {
3378 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3379 struct bnxt_ring_struct *ring =
3380 &rxr->rx_agg_ring_struct;
3381 u32 grp_idx = rxr->bnapi->index;
3382 u32 map_idx = grp_idx + bp->rx_nr_rings;
3383
3384 rc = hwrm_ring_alloc_send_msg(bp, ring,
3385 HWRM_RING_ALLOC_AGG,
3386 map_idx,
3387 INVALID_STATS_CTX_ID);
3388 if (rc)
3389 goto err_out;
3390
3391 rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3392 writel(DB_KEY_RX | rxr->rx_agg_prod,
3393 rxr->rx_agg_doorbell);
3394 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3395 }
3396 }
3397 err_out:
3398 return rc;
3399 }
3400
3401 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3402 struct bnxt_ring_struct *ring,
3403 u32 ring_type, int cmpl_ring_id)
3404 {
3405 int rc;
3406 struct hwrm_ring_free_input req = {0};
3407 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3408 u16 error_code;
3409
3410 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3411 req.ring_type = ring_type;
3412 req.ring_id = cpu_to_le16(ring->fw_ring_id);
3413
3414 mutex_lock(&bp->hwrm_cmd_lock);
3415 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3416 error_code = le16_to_cpu(resp->error_code);
3417 mutex_unlock(&bp->hwrm_cmd_lock);
3418
3419 if (rc || error_code) {
3420 switch (ring_type) {
3421 case RING_FREE_REQ_RING_TYPE_CMPL:
3422 netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3423 rc);
3424 return rc;
3425 case RING_FREE_REQ_RING_TYPE_RX:
3426 netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3427 rc);
3428 return rc;
3429 case RING_FREE_REQ_RING_TYPE_TX:
3430 netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3431 rc);
3432 return rc;
3433 default:
3434 netdev_err(bp->dev, "Invalid ring\n");
3435 return -1;
3436 }
3437 }
3438 return 0;
3439 }
3440
3441 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3442 {
3443 int i;
3444
3445 if (!bp->bnapi)
3446 return;
3447
3448 for (i = 0; i < bp->tx_nr_rings; i++) {
3449 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3450 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3451 u32 grp_idx = txr->bnapi->index;
3452 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3453
3454 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3455 hwrm_ring_free_send_msg(bp, ring,
3456 RING_FREE_REQ_RING_TYPE_TX,
3457 close_path ? cmpl_ring_id :
3458 INVALID_HW_RING_ID);
3459 ring->fw_ring_id = INVALID_HW_RING_ID;
3460 }
3461 }
3462
3463 for (i = 0; i < bp->rx_nr_rings; i++) {
3464 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3465 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3466 u32 grp_idx = rxr->bnapi->index;
3467 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3468
3469 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3470 hwrm_ring_free_send_msg(bp, ring,
3471 RING_FREE_REQ_RING_TYPE_RX,
3472 close_path ? cmpl_ring_id :
3473 INVALID_HW_RING_ID);
3474 ring->fw_ring_id = INVALID_HW_RING_ID;
3475 bp->grp_info[grp_idx].rx_fw_ring_id =
3476 INVALID_HW_RING_ID;
3477 }
3478 }
3479
3480 for (i = 0; i < bp->rx_nr_rings; i++) {
3481 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3482 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3483 u32 grp_idx = rxr->bnapi->index;
3484 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3485
3486 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3487 hwrm_ring_free_send_msg(bp, ring,
3488 RING_FREE_REQ_RING_TYPE_RX,
3489 close_path ? cmpl_ring_id :
3490 INVALID_HW_RING_ID);
3491 ring->fw_ring_id = INVALID_HW_RING_ID;
3492 bp->grp_info[grp_idx].agg_fw_ring_id =
3493 INVALID_HW_RING_ID;
3494 }
3495 }
3496
3497 for (i = 0; i < bp->cp_nr_rings; i++) {
3498 struct bnxt_napi *bnapi = bp->bnapi[i];
3499 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3500 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3501
3502 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3503 hwrm_ring_free_send_msg(bp, ring,
3504 RING_FREE_REQ_RING_TYPE_CMPL,
3505 INVALID_HW_RING_ID);
3506 ring->fw_ring_id = INVALID_HW_RING_ID;
3507 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3508 }
3509 }
3510 }
3511
3512 int bnxt_hwrm_set_coal(struct bnxt *bp)
3513 {
3514 int i, rc = 0;
3515 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3516 u16 max_buf, max_buf_irq;
3517 u16 buf_tmr, buf_tmr_irq;
3518 u32 flags;
3519
3520 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3521 -1, -1);
3522
3523 /* Each rx completion (2 records) should be DMAed immediately */
3524 max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3525 /* max_buf must not be zero */
3526 max_buf = clamp_t(u16, max_buf, 1, 63);
3527 max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3528 buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3529 buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3530
3531 flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3532
3533 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3534 * if coal_ticks is less than 25 us.
3535 */
3536 if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3537 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3538
3539 req.flags = cpu_to_le16(flags);
3540 req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3541 req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3542 req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3543 req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3544 req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3545 req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3546 req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3547
3548 mutex_lock(&bp->hwrm_cmd_lock);
3549 for (i = 0; i < bp->cp_nr_rings; i++) {
3550 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3551
3552 rc = _hwrm_send_message(bp, &req, sizeof(req),
3553 HWRM_CMD_TIMEOUT);
3554 if (rc)
3555 break;
3556 }
3557 mutex_unlock(&bp->hwrm_cmd_lock);
3558 return rc;
3559 }
3560
3561 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3562 {
3563 int rc = 0, i;
3564 struct hwrm_stat_ctx_free_input req = {0};
3565
3566 if (!bp->bnapi)
3567 return 0;
3568
3569 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3570
3571 mutex_lock(&bp->hwrm_cmd_lock);
3572 for (i = 0; i < bp->cp_nr_rings; i++) {
3573 struct bnxt_napi *bnapi = bp->bnapi[i];
3574 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3575
3576 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3577 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3578
3579 rc = _hwrm_send_message(bp, &req, sizeof(req),
3580 HWRM_CMD_TIMEOUT);
3581 if (rc)
3582 break;
3583
3584 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3585 }
3586 }
3587 mutex_unlock(&bp->hwrm_cmd_lock);
3588 return rc;
3589 }
3590
3591 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3592 {
3593 int rc = 0, i;
3594 struct hwrm_stat_ctx_alloc_input req = {0};
3595 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3596
3597 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3598
3599 req.update_period_ms = cpu_to_le32(1000);
3600
3601 mutex_lock(&bp->hwrm_cmd_lock);
3602 for (i = 0; i < bp->cp_nr_rings; i++) {
3603 struct bnxt_napi *bnapi = bp->bnapi[i];
3604 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3605
3606 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3607
3608 rc = _hwrm_send_message(bp, &req, sizeof(req),
3609 HWRM_CMD_TIMEOUT);
3610 if (rc)
3611 break;
3612
3613 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3614
3615 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3616 }
3617 mutex_unlock(&bp->hwrm_cmd_lock);
3618 return 0;
3619 }
3620
3621 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3622 {
3623 int rc = 0;
3624 struct hwrm_func_qcaps_input req = {0};
3625 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3626
3627 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3628 req.fid = cpu_to_le16(0xffff);
3629
3630 mutex_lock(&bp->hwrm_cmd_lock);
3631 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3632 if (rc)
3633 goto hwrm_func_qcaps_exit;
3634
3635 if (BNXT_PF(bp)) {
3636 struct bnxt_pf_info *pf = &bp->pf;
3637
3638 pf->fw_fid = le16_to_cpu(resp->fid);
3639 pf->port_id = le16_to_cpu(resp->port_id);
3640 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3641 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3642 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3643 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3644 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3645 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3646 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3647 if (!pf->max_hw_ring_grps)
3648 pf->max_hw_ring_grps = pf->max_tx_rings;
3649 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3650 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3651 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3652 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3653 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3654 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3655 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3656 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3657 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3658 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3659 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3660 } else {
3661 #ifdef CONFIG_BNXT_SRIOV
3662 struct bnxt_vf_info *vf = &bp->vf;
3663
3664 vf->fw_fid = le16_to_cpu(resp->fid);
3665 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3666 if (is_valid_ether_addr(vf->mac_addr))
3667 /* overwrite netdev dev_adr with admin VF MAC */
3668 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3669 else
3670 random_ether_addr(bp->dev->dev_addr);
3671
3672 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3673 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3674 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3675 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3676 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3677 if (!vf->max_hw_ring_grps)
3678 vf->max_hw_ring_grps = vf->max_tx_rings;
3679 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3680 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3681 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3682 #endif
3683 }
3684
3685 bp->tx_push_thresh = 0;
3686 if (resp->flags &
3687 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3688 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3689
3690 hwrm_func_qcaps_exit:
3691 mutex_unlock(&bp->hwrm_cmd_lock);
3692 return rc;
3693 }
3694
3695 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3696 {
3697 struct hwrm_func_reset_input req = {0};
3698
3699 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3700 req.enables = 0;
3701
3702 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3703 }
3704
3705 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3706 {
3707 int rc = 0;
3708 struct hwrm_queue_qportcfg_input req = {0};
3709 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3710 u8 i, *qptr;
3711
3712 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3713
3714 mutex_lock(&bp->hwrm_cmd_lock);
3715 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3716 if (rc)
3717 goto qportcfg_exit;
3718
3719 if (!resp->max_configurable_queues) {
3720 rc = -EINVAL;
3721 goto qportcfg_exit;
3722 }
3723 bp->max_tc = resp->max_configurable_queues;
3724 if (bp->max_tc > BNXT_MAX_QUEUE)
3725 bp->max_tc = BNXT_MAX_QUEUE;
3726
3727 qptr = &resp->queue_id0;
3728 for (i = 0; i < bp->max_tc; i++) {
3729 bp->q_info[i].queue_id = *qptr++;
3730 bp->q_info[i].queue_profile = *qptr++;
3731 }
3732
3733 qportcfg_exit:
3734 mutex_unlock(&bp->hwrm_cmd_lock);
3735 return rc;
3736 }
3737
3738 static int bnxt_hwrm_ver_get(struct bnxt *bp)
3739 {
3740 int rc;
3741 struct hwrm_ver_get_input req = {0};
3742 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3743
3744 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3745 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3746 req.hwrm_intf_min = HWRM_VERSION_MINOR;
3747 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3748 mutex_lock(&bp->hwrm_cmd_lock);
3749 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3750 if (rc)
3751 goto hwrm_ver_get_exit;
3752
3753 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3754
3755 if (resp->hwrm_intf_maj < 1) {
3756 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3757 resp->hwrm_intf_maj, resp->hwrm_intf_min,
3758 resp->hwrm_intf_upd);
3759 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3760 }
3761 snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3762 resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3763 resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3764
3765 hwrm_ver_get_exit:
3766 mutex_unlock(&bp->hwrm_cmd_lock);
3767 return rc;
3768 }
3769
3770 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3771 {
3772 if (bp->vxlan_port_cnt) {
3773 bnxt_hwrm_tunnel_dst_port_free(
3774 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3775 }
3776 bp->vxlan_port_cnt = 0;
3777 if (bp->nge_port_cnt) {
3778 bnxt_hwrm_tunnel_dst_port_free(
3779 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3780 }
3781 bp->nge_port_cnt = 0;
3782 }
3783
3784 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3785 {
3786 int rc, i;
3787 u32 tpa_flags = 0;
3788
3789 if (set_tpa)
3790 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3791 for (i = 0; i < bp->nr_vnics; i++) {
3792 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3793 if (rc) {
3794 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3795 rc, i);
3796 return rc;
3797 }
3798 }
3799 return 0;
3800 }
3801
3802 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3803 {
3804 int i;
3805
3806 for (i = 0; i < bp->nr_vnics; i++)
3807 bnxt_hwrm_vnic_set_rss(bp, i, false);
3808 }
3809
3810 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3811 bool irq_re_init)
3812 {
3813 if (bp->vnic_info) {
3814 bnxt_hwrm_clear_vnic_filter(bp);
3815 /* clear all RSS setting before free vnic ctx */
3816 bnxt_hwrm_clear_vnic_rss(bp);
3817 bnxt_hwrm_vnic_ctx_free(bp);
3818 /* before free the vnic, undo the vnic tpa settings */
3819 if (bp->flags & BNXT_FLAG_TPA)
3820 bnxt_set_tpa(bp, false);
3821 bnxt_hwrm_vnic_free(bp);
3822 }
3823 bnxt_hwrm_ring_free(bp, close_path);
3824 bnxt_hwrm_ring_grp_free(bp);
3825 if (irq_re_init) {
3826 bnxt_hwrm_stat_ctx_free(bp);
3827 bnxt_hwrm_free_tunnel_ports(bp);
3828 }
3829 }
3830
3831 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3832 {
3833 int rc;
3834
3835 /* allocate context for vnic */
3836 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3837 if (rc) {
3838 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3839 vnic_id, rc);
3840 goto vnic_setup_err;
3841 }
3842 bp->rsscos_nr_ctxs++;
3843
3844 /* configure default vnic, ring grp */
3845 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3846 if (rc) {
3847 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3848 vnic_id, rc);
3849 goto vnic_setup_err;
3850 }
3851
3852 /* Enable RSS hashing on vnic */
3853 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3854 if (rc) {
3855 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3856 vnic_id, rc);
3857 goto vnic_setup_err;
3858 }
3859
3860 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3861 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3862 if (rc) {
3863 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3864 vnic_id, rc);
3865 }
3866 }
3867
3868 vnic_setup_err:
3869 return rc;
3870 }
3871
3872 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3873 {
3874 #ifdef CONFIG_RFS_ACCEL
3875 int i, rc = 0;
3876
3877 for (i = 0; i < bp->rx_nr_rings; i++) {
3878 u16 vnic_id = i + 1;
3879 u16 ring_id = i;
3880
3881 if (vnic_id >= bp->nr_vnics)
3882 break;
3883
3884 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
3885 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
3886 if (rc) {
3887 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3888 vnic_id, rc);
3889 break;
3890 }
3891 rc = bnxt_setup_vnic(bp, vnic_id);
3892 if (rc)
3893 break;
3894 }
3895 return rc;
3896 #else
3897 return 0;
3898 #endif
3899 }
3900
3901 static int bnxt_cfg_rx_mode(struct bnxt *);
3902
3903 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3904 {
3905 int rc = 0;
3906
3907 if (irq_re_init) {
3908 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3909 if (rc) {
3910 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3911 rc);
3912 goto err_out;
3913 }
3914 }
3915
3916 rc = bnxt_hwrm_ring_alloc(bp);
3917 if (rc) {
3918 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3919 goto err_out;
3920 }
3921
3922 rc = bnxt_hwrm_ring_grp_alloc(bp);
3923 if (rc) {
3924 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3925 goto err_out;
3926 }
3927
3928 /* default vnic 0 */
3929 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3930 if (rc) {
3931 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3932 goto err_out;
3933 }
3934
3935 rc = bnxt_setup_vnic(bp, 0);
3936 if (rc)
3937 goto err_out;
3938
3939 if (bp->flags & BNXT_FLAG_RFS) {
3940 rc = bnxt_alloc_rfs_vnics(bp);
3941 if (rc)
3942 goto err_out;
3943 }
3944
3945 if (bp->flags & BNXT_FLAG_TPA) {
3946 rc = bnxt_set_tpa(bp, true);
3947 if (rc)
3948 goto err_out;
3949 }
3950
3951 if (BNXT_VF(bp))
3952 bnxt_update_vf_mac(bp);
3953
3954 /* Filter for default vnic 0 */
3955 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3956 if (rc) {
3957 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3958 goto err_out;
3959 }
3960 bp->vnic_info[0].uc_filter_count = 1;
3961
3962 bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
3963
3964 if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3965 bp->vnic_info[0].rx_mask |=
3966 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3967
3968 rc = bnxt_cfg_rx_mode(bp);
3969 if (rc)
3970 goto err_out;
3971
3972 rc = bnxt_hwrm_set_coal(bp);
3973 if (rc)
3974 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3975 rc);
3976
3977 return 0;
3978
3979 err_out:
3980 bnxt_hwrm_resource_free(bp, 0, true);
3981
3982 return rc;
3983 }
3984
3985 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
3986 {
3987 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
3988 return 0;
3989 }
3990
3991 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
3992 {
3993 bnxt_init_rx_rings(bp);
3994 bnxt_init_tx_rings(bp);
3995 bnxt_init_ring_grps(bp, irq_re_init);
3996 bnxt_init_vnics(bp);
3997
3998 return bnxt_init_chip(bp, irq_re_init);
3999 }
4000
4001 static void bnxt_disable_int(struct bnxt *bp)
4002 {
4003 int i;
4004
4005 if (!bp->bnapi)
4006 return;
4007
4008 for (i = 0; i < bp->cp_nr_rings; i++) {
4009 struct bnxt_napi *bnapi = bp->bnapi[i];
4010 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4011
4012 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4013 }
4014 }
4015
4016 static void bnxt_enable_int(struct bnxt *bp)
4017 {
4018 int i;
4019
4020 atomic_set(&bp->intr_sem, 0);
4021 for (i = 0; i < bp->cp_nr_rings; i++) {
4022 struct bnxt_napi *bnapi = bp->bnapi[i];
4023 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4024
4025 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4026 }
4027 }
4028
4029 static int bnxt_set_real_num_queues(struct bnxt *bp)
4030 {
4031 int rc;
4032 struct net_device *dev = bp->dev;
4033
4034 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4035 if (rc)
4036 return rc;
4037
4038 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4039 if (rc)
4040 return rc;
4041
4042 #ifdef CONFIG_RFS_ACCEL
4043 if (bp->flags & BNXT_FLAG_RFS)
4044 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4045 #endif
4046
4047 return rc;
4048 }
4049
4050 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4051 bool shared)
4052 {
4053 int _rx = *rx, _tx = *tx;
4054
4055 if (shared) {
4056 *rx = min_t(int, _rx, max);
4057 *tx = min_t(int, _tx, max);
4058 } else {
4059 if (max < 2)
4060 return -ENOMEM;
4061
4062 while (_rx + _tx > max) {
4063 if (_rx > _tx && _rx > 1)
4064 _rx--;
4065 else if (_tx > 1)
4066 _tx--;
4067 }
4068 *rx = _rx;
4069 *tx = _tx;
4070 }
4071 return 0;
4072 }
4073
4074 static int bnxt_setup_msix(struct bnxt *bp)
4075 {
4076 struct msix_entry *msix_ent;
4077 struct net_device *dev = bp->dev;
4078 int i, total_vecs, rc = 0, min = 1;
4079 const int len = sizeof(bp->irq_tbl[0].name);
4080
4081 bp->flags &= ~BNXT_FLAG_USING_MSIX;
4082 total_vecs = bp->cp_nr_rings;
4083
4084 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4085 if (!msix_ent)
4086 return -ENOMEM;
4087
4088 for (i = 0; i < total_vecs; i++) {
4089 msix_ent[i].entry = i;
4090 msix_ent[i].vector = 0;
4091 }
4092
4093 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4094 min = 2;
4095
4096 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4097 if (total_vecs < 0) {
4098 rc = -ENODEV;
4099 goto msix_setup_exit;
4100 }
4101
4102 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4103 if (bp->irq_tbl) {
4104 int tcs;
4105
4106 /* Trim rings based upon num of vectors allocated */
4107 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4108 total_vecs, min == 1);
4109 if (rc)
4110 goto msix_setup_exit;
4111
4112 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4113 tcs = netdev_get_num_tc(dev);
4114 if (tcs > 1) {
4115 bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4116 if (bp->tx_nr_rings_per_tc == 0) {
4117 netdev_reset_tc(dev);
4118 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4119 } else {
4120 int i, off, count;
4121
4122 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4123 for (i = 0; i < tcs; i++) {
4124 count = bp->tx_nr_rings_per_tc;
4125 off = i * count;
4126 netdev_set_tc_queue(dev, i, count, off);
4127 }
4128 }
4129 }
4130 bp->cp_nr_rings = total_vecs;
4131
4132 for (i = 0; i < bp->cp_nr_rings; i++) {
4133 char *attr;
4134
4135 bp->irq_tbl[i].vector = msix_ent[i].vector;
4136 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4137 attr = "TxRx";
4138 else if (i < bp->rx_nr_rings)
4139 attr = "rx";
4140 else
4141 attr = "tx";
4142
4143 snprintf(bp->irq_tbl[i].name, len,
4144 "%s-%s-%d", dev->name, attr, i);
4145 bp->irq_tbl[i].handler = bnxt_msix;
4146 }
4147 rc = bnxt_set_real_num_queues(bp);
4148 if (rc)
4149 goto msix_setup_exit;
4150 } else {
4151 rc = -ENOMEM;
4152 goto msix_setup_exit;
4153 }
4154 bp->flags |= BNXT_FLAG_USING_MSIX;
4155 kfree(msix_ent);
4156 return 0;
4157
4158 msix_setup_exit:
4159 netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4160 pci_disable_msix(bp->pdev);
4161 kfree(msix_ent);
4162 return rc;
4163 }
4164
4165 static int bnxt_setup_inta(struct bnxt *bp)
4166 {
4167 int rc;
4168 const int len = sizeof(bp->irq_tbl[0].name);
4169
4170 if (netdev_get_num_tc(bp->dev))
4171 netdev_reset_tc(bp->dev);
4172
4173 bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4174 if (!bp->irq_tbl) {
4175 rc = -ENOMEM;
4176 return rc;
4177 }
4178 bp->rx_nr_rings = 1;
4179 bp->tx_nr_rings = 1;
4180 bp->cp_nr_rings = 1;
4181 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4182 bp->flags |= BNXT_FLAG_SHARED_RINGS;
4183 bp->irq_tbl[0].vector = bp->pdev->irq;
4184 snprintf(bp->irq_tbl[0].name, len,
4185 "%s-%s-%d", bp->dev->name, "TxRx", 0);
4186 bp->irq_tbl[0].handler = bnxt_inta;
4187 rc = bnxt_set_real_num_queues(bp);
4188 return rc;
4189 }
4190
4191 static int bnxt_setup_int_mode(struct bnxt *bp)
4192 {
4193 int rc = 0;
4194
4195 if (bp->flags & BNXT_FLAG_MSIX_CAP)
4196 rc = bnxt_setup_msix(bp);
4197
4198 if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4199 /* fallback to INTA */
4200 rc = bnxt_setup_inta(bp);
4201 }
4202 return rc;
4203 }
4204
4205 static void bnxt_free_irq(struct bnxt *bp)
4206 {
4207 struct bnxt_irq *irq;
4208 int i;
4209
4210 #ifdef CONFIG_RFS_ACCEL
4211 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4212 bp->dev->rx_cpu_rmap = NULL;
4213 #endif
4214 if (!bp->irq_tbl)
4215 return;
4216
4217 for (i = 0; i < bp->cp_nr_rings; i++) {
4218 irq = &bp->irq_tbl[i];
4219 if (irq->requested)
4220 free_irq(irq->vector, bp->bnapi[i]);
4221 irq->requested = 0;
4222 }
4223 if (bp->flags & BNXT_FLAG_USING_MSIX)
4224 pci_disable_msix(bp->pdev);
4225 kfree(bp->irq_tbl);
4226 bp->irq_tbl = NULL;
4227 }
4228
4229 static int bnxt_request_irq(struct bnxt *bp)
4230 {
4231 int i, j, rc = 0;
4232 unsigned long flags = 0;
4233 #ifdef CONFIG_RFS_ACCEL
4234 struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4235 #endif
4236
4237 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4238 flags = IRQF_SHARED;
4239
4240 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4241 struct bnxt_irq *irq = &bp->irq_tbl[i];
4242 #ifdef CONFIG_RFS_ACCEL
4243 if (rmap && bp->bnapi[i]->rx_ring) {
4244 rc = irq_cpu_rmap_add(rmap, irq->vector);
4245 if (rc)
4246 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4247 j);
4248 j++;
4249 }
4250 #endif
4251 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4252 bp->bnapi[i]);
4253 if (rc)
4254 break;
4255
4256 irq->requested = 1;
4257 }
4258 return rc;
4259 }
4260
4261 static void bnxt_del_napi(struct bnxt *bp)
4262 {
4263 int i;
4264
4265 if (!bp->bnapi)
4266 return;
4267
4268 for (i = 0; i < bp->cp_nr_rings; i++) {
4269 struct bnxt_napi *bnapi = bp->bnapi[i];
4270
4271 napi_hash_del(&bnapi->napi);
4272 netif_napi_del(&bnapi->napi);
4273 }
4274 }
4275
4276 static void bnxt_init_napi(struct bnxt *bp)
4277 {
4278 int i;
4279 struct bnxt_napi *bnapi;
4280
4281 if (bp->flags & BNXT_FLAG_USING_MSIX) {
4282 for (i = 0; i < bp->cp_nr_rings; i++) {
4283 bnapi = bp->bnapi[i];
4284 netif_napi_add(bp->dev, &bnapi->napi,
4285 bnxt_poll, 64);
4286 }
4287 } else {
4288 bnapi = bp->bnapi[0];
4289 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4290 }
4291 }
4292
4293 static void bnxt_disable_napi(struct bnxt *bp)
4294 {
4295 int i;
4296
4297 if (!bp->bnapi)
4298 return;
4299
4300 for (i = 0; i < bp->cp_nr_rings; i++) {
4301 napi_disable(&bp->bnapi[i]->napi);
4302 bnxt_disable_poll(bp->bnapi[i]);
4303 }
4304 }
4305
4306 static void bnxt_enable_napi(struct bnxt *bp)
4307 {
4308 int i;
4309
4310 for (i = 0; i < bp->cp_nr_rings; i++) {
4311 bnxt_enable_poll(bp->bnapi[i]);
4312 napi_enable(&bp->bnapi[i]->napi);
4313 }
4314 }
4315
4316 static void bnxt_tx_disable(struct bnxt *bp)
4317 {
4318 int i;
4319 struct bnxt_tx_ring_info *txr;
4320 struct netdev_queue *txq;
4321
4322 if (bp->tx_ring) {
4323 for (i = 0; i < bp->tx_nr_rings; i++) {
4324 txr = &bp->tx_ring[i];
4325 txq = netdev_get_tx_queue(bp->dev, i);
4326 __netif_tx_lock(txq, smp_processor_id());
4327 txr->dev_state = BNXT_DEV_STATE_CLOSING;
4328 __netif_tx_unlock(txq);
4329 }
4330 }
4331 /* Stop all TX queues */
4332 netif_tx_disable(bp->dev);
4333 netif_carrier_off(bp->dev);
4334 }
4335
4336 static void bnxt_tx_enable(struct bnxt *bp)
4337 {
4338 int i;
4339 struct bnxt_tx_ring_info *txr;
4340 struct netdev_queue *txq;
4341
4342 for (i = 0; i < bp->tx_nr_rings; i++) {
4343 txr = &bp->tx_ring[i];
4344 txq = netdev_get_tx_queue(bp->dev, i);
4345 txr->dev_state = 0;
4346 }
4347 netif_tx_wake_all_queues(bp->dev);
4348 if (bp->link_info.link_up)
4349 netif_carrier_on(bp->dev);
4350 }
4351
4352 static void bnxt_report_link(struct bnxt *bp)
4353 {
4354 if (bp->link_info.link_up) {
4355 const char *duplex;
4356 const char *flow_ctrl;
4357 u16 speed;
4358
4359 netif_carrier_on(bp->dev);
4360 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4361 duplex = "full";
4362 else
4363 duplex = "half";
4364 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4365 flow_ctrl = "ON - receive & transmit";
4366 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4367 flow_ctrl = "ON - transmit";
4368 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4369 flow_ctrl = "ON - receive";
4370 else
4371 flow_ctrl = "none";
4372 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4373 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4374 speed, duplex, flow_ctrl);
4375 } else {
4376 netif_carrier_off(bp->dev);
4377 netdev_err(bp->dev, "NIC Link is Down\n");
4378 }
4379 }
4380
4381 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4382 {
4383 int rc = 0;
4384 struct bnxt_link_info *link_info = &bp->link_info;
4385 struct hwrm_port_phy_qcfg_input req = {0};
4386 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4387 u8 link_up = link_info->link_up;
4388
4389 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4390
4391 mutex_lock(&bp->hwrm_cmd_lock);
4392 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4393 if (rc) {
4394 mutex_unlock(&bp->hwrm_cmd_lock);
4395 return rc;
4396 }
4397
4398 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4399 link_info->phy_link_status = resp->link;
4400 link_info->duplex = resp->duplex;
4401 link_info->pause = resp->pause;
4402 link_info->auto_mode = resp->auto_mode;
4403 link_info->auto_pause_setting = resp->auto_pause;
4404 link_info->force_pause_setting = resp->force_pause;
4405 link_info->duplex_setting = resp->duplex;
4406 if (link_info->phy_link_status == BNXT_LINK_LINK)
4407 link_info->link_speed = le16_to_cpu(resp->link_speed);
4408 else
4409 link_info->link_speed = 0;
4410 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4411 link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4412 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4413 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4414 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4415 link_info->phy_ver[0] = resp->phy_maj;
4416 link_info->phy_ver[1] = resp->phy_min;
4417 link_info->phy_ver[2] = resp->phy_bld;
4418 link_info->media_type = resp->media_type;
4419 link_info->transceiver = resp->transceiver_type;
4420 link_info->phy_addr = resp->phy_addr;
4421
4422 /* TODO: need to add more logic to report VF link */
4423 if (chng_link_state) {
4424 if (link_info->phy_link_status == BNXT_LINK_LINK)
4425 link_info->link_up = 1;
4426 else
4427 link_info->link_up = 0;
4428 if (link_up != link_info->link_up)
4429 bnxt_report_link(bp);
4430 } else {
4431 /* alwasy link down if not require to update link state */
4432 link_info->link_up = 0;
4433 }
4434 mutex_unlock(&bp->hwrm_cmd_lock);
4435 return 0;
4436 }
4437
4438 static void
4439 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4440 {
4441 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4442 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4443 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4444 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4445 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4446 req->enables |=
4447 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4448 } else {
4449 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4450 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4451 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4452 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4453 req->enables |=
4454 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4455 }
4456 }
4457
4458 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4459 struct hwrm_port_phy_cfg_input *req)
4460 {
4461 u8 autoneg = bp->link_info.autoneg;
4462 u16 fw_link_speed = bp->link_info.req_link_speed;
4463 u32 advertising = bp->link_info.advertising;
4464
4465 if (autoneg & BNXT_AUTONEG_SPEED) {
4466 req->auto_mode |=
4467 PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4468
4469 req->enables |= cpu_to_le32(
4470 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4471 req->auto_link_speed_mask = cpu_to_le16(advertising);
4472
4473 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4474 req->flags |=
4475 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4476 } else {
4477 req->force_link_speed = cpu_to_le16(fw_link_speed);
4478 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4479 }
4480
4481 /* currently don't support half duplex */
4482 req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4483 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4484 /* tell chimp that the setting takes effect immediately */
4485 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4486 }
4487
4488 int bnxt_hwrm_set_pause(struct bnxt *bp)
4489 {
4490 struct hwrm_port_phy_cfg_input req = {0};
4491 int rc;
4492
4493 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4494 bnxt_hwrm_set_pause_common(bp, &req);
4495
4496 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4497 bp->link_info.force_link_chng)
4498 bnxt_hwrm_set_link_common(bp, &req);
4499
4500 mutex_lock(&bp->hwrm_cmd_lock);
4501 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4502 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4503 /* since changing of pause setting doesn't trigger any link
4504 * change event, the driver needs to update the current pause
4505 * result upon successfully return of the phy_cfg command
4506 */
4507 bp->link_info.pause =
4508 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4509 bp->link_info.auto_pause_setting = 0;
4510 if (!bp->link_info.force_link_chng)
4511 bnxt_report_link(bp);
4512 }
4513 bp->link_info.force_link_chng = false;
4514 mutex_unlock(&bp->hwrm_cmd_lock);
4515 return rc;
4516 }
4517
4518 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4519 {
4520 struct hwrm_port_phy_cfg_input req = {0};
4521
4522 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4523 if (set_pause)
4524 bnxt_hwrm_set_pause_common(bp, &req);
4525
4526 bnxt_hwrm_set_link_common(bp, &req);
4527 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4528 }
4529
4530 static int bnxt_update_phy_setting(struct bnxt *bp)
4531 {
4532 int rc;
4533 bool update_link = false;
4534 bool update_pause = false;
4535 struct bnxt_link_info *link_info = &bp->link_info;
4536
4537 rc = bnxt_update_link(bp, true);
4538 if (rc) {
4539 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4540 rc);
4541 return rc;
4542 }
4543 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4544 link_info->auto_pause_setting != link_info->req_flow_ctrl)
4545 update_pause = true;
4546 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4547 link_info->force_pause_setting != link_info->req_flow_ctrl)
4548 update_pause = true;
4549 if (link_info->req_duplex != link_info->duplex_setting)
4550 update_link = true;
4551 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4552 if (BNXT_AUTO_MODE(link_info->auto_mode))
4553 update_link = true;
4554 if (link_info->req_link_speed != link_info->force_link_speed)
4555 update_link = true;
4556 } else {
4557 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4558 update_link = true;
4559 if (link_info->advertising != link_info->auto_link_speeds)
4560 update_link = true;
4561 if (link_info->req_link_speed != link_info->auto_link_speed)
4562 update_link = true;
4563 }
4564
4565 if (update_link)
4566 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4567 else if (update_pause)
4568 rc = bnxt_hwrm_set_pause(bp);
4569 if (rc) {
4570 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4571 rc);
4572 return rc;
4573 }
4574
4575 return rc;
4576 }
4577
4578 /* Common routine to pre-map certain register block to different GRC window.
4579 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4580 * in PF and 3 windows in VF that can be customized to map in different
4581 * register blocks.
4582 */
4583 static void bnxt_preset_reg_win(struct bnxt *bp)
4584 {
4585 if (BNXT_PF(bp)) {
4586 /* CAG registers map to GRC window #4 */
4587 writel(BNXT_CAG_REG_BASE,
4588 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4589 }
4590 }
4591
4592 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4593 {
4594 int rc = 0;
4595
4596 bnxt_preset_reg_win(bp);
4597 netif_carrier_off(bp->dev);
4598 if (irq_re_init) {
4599 rc = bnxt_setup_int_mode(bp);
4600 if (rc) {
4601 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4602 rc);
4603 return rc;
4604 }
4605 }
4606 if ((bp->flags & BNXT_FLAG_RFS) &&
4607 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4608 /* disable RFS if falling back to INTA */
4609 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4610 bp->flags &= ~BNXT_FLAG_RFS;
4611 }
4612
4613 rc = bnxt_alloc_mem(bp, irq_re_init);
4614 if (rc) {
4615 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4616 goto open_err_free_mem;
4617 }
4618
4619 if (irq_re_init) {
4620 bnxt_init_napi(bp);
4621 rc = bnxt_request_irq(bp);
4622 if (rc) {
4623 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4624 goto open_err;
4625 }
4626 }
4627
4628 bnxt_enable_napi(bp);
4629
4630 rc = bnxt_init_nic(bp, irq_re_init);
4631 if (rc) {
4632 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4633 goto open_err;
4634 }
4635
4636 if (link_re_init) {
4637 rc = bnxt_update_phy_setting(bp);
4638 if (rc)
4639 goto open_err;
4640 }
4641
4642 if (irq_re_init) {
4643 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4644 vxlan_get_rx_port(bp->dev);
4645 #endif
4646 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4647 bp, htons(0x17c1),
4648 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4649 bp->nge_port_cnt = 1;
4650 }
4651
4652 set_bit(BNXT_STATE_OPEN, &bp->state);
4653 bnxt_enable_int(bp);
4654 /* Enable TX queues */
4655 bnxt_tx_enable(bp);
4656 mod_timer(&bp->timer, jiffies + bp->current_interval);
4657
4658 return 0;
4659
4660 open_err:
4661 bnxt_disable_napi(bp);
4662 bnxt_del_napi(bp);
4663
4664 open_err_free_mem:
4665 bnxt_free_skbs(bp);
4666 bnxt_free_irq(bp);
4667 bnxt_free_mem(bp, true);
4668 return rc;
4669 }
4670
4671 /* rtnl_lock held */
4672 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4673 {
4674 int rc = 0;
4675
4676 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4677 if (rc) {
4678 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4679 dev_close(bp->dev);
4680 }
4681 return rc;
4682 }
4683
4684 static int bnxt_open(struct net_device *dev)
4685 {
4686 struct bnxt *bp = netdev_priv(dev);
4687 int rc = 0;
4688
4689 rc = bnxt_hwrm_func_reset(bp);
4690 if (rc) {
4691 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4692 rc);
4693 rc = -1;
4694 return rc;
4695 }
4696 return __bnxt_open_nic(bp, true, true);
4697 }
4698
4699 static void bnxt_disable_int_sync(struct bnxt *bp)
4700 {
4701 int i;
4702
4703 atomic_inc(&bp->intr_sem);
4704 if (!netif_running(bp->dev))
4705 return;
4706
4707 bnxt_disable_int(bp);
4708 for (i = 0; i < bp->cp_nr_rings; i++)
4709 synchronize_irq(bp->irq_tbl[i].vector);
4710 }
4711
4712 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4713 {
4714 int rc = 0;
4715
4716 #ifdef CONFIG_BNXT_SRIOV
4717 if (bp->sriov_cfg) {
4718 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4719 !bp->sriov_cfg,
4720 BNXT_SRIOV_CFG_WAIT_TMO);
4721 if (rc)
4722 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4723 }
4724 #endif
4725 /* Change device state to avoid TX queue wake up's */
4726 bnxt_tx_disable(bp);
4727
4728 clear_bit(BNXT_STATE_OPEN, &bp->state);
4729 smp_mb__after_atomic();
4730 while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4731 msleep(20);
4732
4733 /* Flush rings before disabling interrupts */
4734 bnxt_shutdown_nic(bp, irq_re_init);
4735
4736 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4737
4738 bnxt_disable_napi(bp);
4739 bnxt_disable_int_sync(bp);
4740 del_timer_sync(&bp->timer);
4741 bnxt_free_skbs(bp);
4742
4743 if (irq_re_init) {
4744 bnxt_free_irq(bp);
4745 bnxt_del_napi(bp);
4746 }
4747 bnxt_free_mem(bp, irq_re_init);
4748 return rc;
4749 }
4750
4751 static int bnxt_close(struct net_device *dev)
4752 {
4753 struct bnxt *bp = netdev_priv(dev);
4754
4755 bnxt_close_nic(bp, true, true);
4756 return 0;
4757 }
4758
4759 /* rtnl_lock held */
4760 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4761 {
4762 switch (cmd) {
4763 case SIOCGMIIPHY:
4764 /* fallthru */
4765 case SIOCGMIIREG: {
4766 if (!netif_running(dev))
4767 return -EAGAIN;
4768
4769 return 0;
4770 }
4771
4772 case SIOCSMIIREG:
4773 if (!netif_running(dev))
4774 return -EAGAIN;
4775
4776 return 0;
4777
4778 default:
4779 /* do nothing */
4780 break;
4781 }
4782 return -EOPNOTSUPP;
4783 }
4784
4785 static struct rtnl_link_stats64 *
4786 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4787 {
4788 u32 i;
4789 struct bnxt *bp = netdev_priv(dev);
4790
4791 memset(stats, 0, sizeof(struct rtnl_link_stats64));
4792
4793 if (!bp->bnapi)
4794 return stats;
4795
4796 /* TODO check if we need to synchronize with bnxt_close path */
4797 for (i = 0; i < bp->cp_nr_rings; i++) {
4798 struct bnxt_napi *bnapi = bp->bnapi[i];
4799 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4800 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4801
4802 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4803 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4804 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4805
4806 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4807 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4808 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4809
4810 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4811 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4812 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4813
4814 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4815 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4816 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4817
4818 stats->rx_missed_errors +=
4819 le64_to_cpu(hw_stats->rx_discard_pkts);
4820
4821 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4822
4823 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4824 }
4825
4826 return stats;
4827 }
4828
4829 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4830 {
4831 struct net_device *dev = bp->dev;
4832 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4833 struct netdev_hw_addr *ha;
4834 u8 *haddr;
4835 int mc_count = 0;
4836 bool update = false;
4837 int off = 0;
4838
4839 netdev_for_each_mc_addr(ha, dev) {
4840 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4841 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4842 vnic->mc_list_count = 0;
4843 return false;
4844 }
4845 haddr = ha->addr;
4846 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4847 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4848 update = true;
4849 }
4850 off += ETH_ALEN;
4851 mc_count++;
4852 }
4853 if (mc_count)
4854 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4855
4856 if (mc_count != vnic->mc_list_count) {
4857 vnic->mc_list_count = mc_count;
4858 update = true;
4859 }
4860 return update;
4861 }
4862
4863 static bool bnxt_uc_list_updated(struct bnxt *bp)
4864 {
4865 struct net_device *dev = bp->dev;
4866 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4867 struct netdev_hw_addr *ha;
4868 int off = 0;
4869
4870 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4871 return true;
4872
4873 netdev_for_each_uc_addr(ha, dev) {
4874 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4875 return true;
4876
4877 off += ETH_ALEN;
4878 }
4879 return false;
4880 }
4881
4882 static void bnxt_set_rx_mode(struct net_device *dev)
4883 {
4884 struct bnxt *bp = netdev_priv(dev);
4885 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4886 u32 mask = vnic->rx_mask;
4887 bool mc_update = false;
4888 bool uc_update;
4889
4890 if (!netif_running(dev))
4891 return;
4892
4893 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4894 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4895 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4896
4897 /* Only allow PF to be in promiscuous mode */
4898 if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4899 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4900
4901 uc_update = bnxt_uc_list_updated(bp);
4902
4903 if (dev->flags & IFF_ALLMULTI) {
4904 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4905 vnic->mc_list_count = 0;
4906 } else {
4907 mc_update = bnxt_mc_list_updated(bp, &mask);
4908 }
4909
4910 if (mask != vnic->rx_mask || uc_update || mc_update) {
4911 vnic->rx_mask = mask;
4912
4913 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4914 schedule_work(&bp->sp_task);
4915 }
4916 }
4917
4918 static int bnxt_cfg_rx_mode(struct bnxt *bp)
4919 {
4920 struct net_device *dev = bp->dev;
4921 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4922 struct netdev_hw_addr *ha;
4923 int i, off = 0, rc;
4924 bool uc_update;
4925
4926 netif_addr_lock_bh(dev);
4927 uc_update = bnxt_uc_list_updated(bp);
4928 netif_addr_unlock_bh(dev);
4929
4930 if (!uc_update)
4931 goto skip_uc;
4932
4933 mutex_lock(&bp->hwrm_cmd_lock);
4934 for (i = 1; i < vnic->uc_filter_count; i++) {
4935 struct hwrm_cfa_l2_filter_free_input req = {0};
4936
4937 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4938 -1);
4939
4940 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4941
4942 rc = _hwrm_send_message(bp, &req, sizeof(req),
4943 HWRM_CMD_TIMEOUT);
4944 }
4945 mutex_unlock(&bp->hwrm_cmd_lock);
4946
4947 vnic->uc_filter_count = 1;
4948
4949 netif_addr_lock_bh(dev);
4950 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4951 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4952 } else {
4953 netdev_for_each_uc_addr(ha, dev) {
4954 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4955 off += ETH_ALEN;
4956 vnic->uc_filter_count++;
4957 }
4958 }
4959 netif_addr_unlock_bh(dev);
4960
4961 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4962 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4963 if (rc) {
4964 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4965 rc);
4966 vnic->uc_filter_count = i;
4967 return rc;
4968 }
4969 }
4970
4971 skip_uc:
4972 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4973 if (rc)
4974 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
4975 rc);
4976
4977 return rc;
4978 }
4979
4980 static bool bnxt_rfs_capable(struct bnxt *bp)
4981 {
4982 #ifdef CONFIG_RFS_ACCEL
4983 struct bnxt_pf_info *pf = &bp->pf;
4984 int vnics;
4985
4986 if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
4987 return false;
4988
4989 vnics = 1 + bp->rx_nr_rings;
4990 if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
4991 return false;
4992
4993 return true;
4994 #else
4995 return false;
4996 #endif
4997 }
4998
4999 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5000 netdev_features_t features)
5001 {
5002 struct bnxt *bp = netdev_priv(dev);
5003
5004 if (!bnxt_rfs_capable(bp))
5005 features &= ~NETIF_F_NTUPLE;
5006 return features;
5007 }
5008
5009 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5010 {
5011 struct bnxt *bp = netdev_priv(dev);
5012 u32 flags = bp->flags;
5013 u32 changes;
5014 int rc = 0;
5015 bool re_init = false;
5016 bool update_tpa = false;
5017
5018 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5019 if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5020 flags |= BNXT_FLAG_GRO;
5021 if (features & NETIF_F_LRO)
5022 flags |= BNXT_FLAG_LRO;
5023
5024 if (features & NETIF_F_HW_VLAN_CTAG_RX)
5025 flags |= BNXT_FLAG_STRIP_VLAN;
5026
5027 if (features & NETIF_F_NTUPLE)
5028 flags |= BNXT_FLAG_RFS;
5029
5030 changes = flags ^ bp->flags;
5031 if (changes & BNXT_FLAG_TPA) {
5032 update_tpa = true;
5033 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5034 (flags & BNXT_FLAG_TPA) == 0)
5035 re_init = true;
5036 }
5037
5038 if (changes & ~BNXT_FLAG_TPA)
5039 re_init = true;
5040
5041 if (flags != bp->flags) {
5042 u32 old_flags = bp->flags;
5043
5044 bp->flags = flags;
5045
5046 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5047 if (update_tpa)
5048 bnxt_set_ring_params(bp);
5049 return rc;
5050 }
5051
5052 if (re_init) {
5053 bnxt_close_nic(bp, false, false);
5054 if (update_tpa)
5055 bnxt_set_ring_params(bp);
5056
5057 return bnxt_open_nic(bp, false, false);
5058 }
5059 if (update_tpa) {
5060 rc = bnxt_set_tpa(bp,
5061 (flags & BNXT_FLAG_TPA) ?
5062 true : false);
5063 if (rc)
5064 bp->flags = old_flags;
5065 }
5066 }
5067 return rc;
5068 }
5069
5070 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5071 {
5072 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5073 int i = bnapi->index;
5074
5075 if (!txr)
5076 return;
5077
5078 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5079 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5080 txr->tx_cons);
5081 }
5082
5083 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5084 {
5085 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5086 int i = bnapi->index;
5087
5088 if (!rxr)
5089 return;
5090
5091 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5092 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5093 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5094 rxr->rx_sw_agg_prod);
5095 }
5096
5097 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5098 {
5099 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5100 int i = bnapi->index;
5101
5102 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5103 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5104 }
5105
5106 static void bnxt_dbg_dump_states(struct bnxt *bp)
5107 {
5108 int i;
5109 struct bnxt_napi *bnapi;
5110
5111 for (i = 0; i < bp->cp_nr_rings; i++) {
5112 bnapi = bp->bnapi[i];
5113 if (netif_msg_drv(bp)) {
5114 bnxt_dump_tx_sw_state(bnapi);
5115 bnxt_dump_rx_sw_state(bnapi);
5116 bnxt_dump_cp_sw_state(bnapi);
5117 }
5118 }
5119 }
5120
5121 static void bnxt_reset_task(struct bnxt *bp)
5122 {
5123 bnxt_dbg_dump_states(bp);
5124 if (netif_running(bp->dev)) {
5125 bnxt_close_nic(bp, false, false);
5126 bnxt_open_nic(bp, false, false);
5127 }
5128 }
5129
5130 static void bnxt_tx_timeout(struct net_device *dev)
5131 {
5132 struct bnxt *bp = netdev_priv(dev);
5133
5134 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
5135 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5136 schedule_work(&bp->sp_task);
5137 }
5138
5139 #ifdef CONFIG_NET_POLL_CONTROLLER
5140 static void bnxt_poll_controller(struct net_device *dev)
5141 {
5142 struct bnxt *bp = netdev_priv(dev);
5143 int i;
5144
5145 for (i = 0; i < bp->cp_nr_rings; i++) {
5146 struct bnxt_irq *irq = &bp->irq_tbl[i];
5147
5148 disable_irq(irq->vector);
5149 irq->handler(irq->vector, bp->bnapi[i]);
5150 enable_irq(irq->vector);
5151 }
5152 }
5153 #endif
5154
5155 static void bnxt_timer(unsigned long data)
5156 {
5157 struct bnxt *bp = (struct bnxt *)data;
5158 struct net_device *dev = bp->dev;
5159
5160 if (!netif_running(dev))
5161 return;
5162
5163 if (atomic_read(&bp->intr_sem) != 0)
5164 goto bnxt_restart_timer;
5165
5166 bnxt_restart_timer:
5167 mod_timer(&bp->timer, jiffies + bp->current_interval);
5168 }
5169
5170 static void bnxt_cfg_ntp_filters(struct bnxt *);
5171
5172 static void bnxt_sp_task(struct work_struct *work)
5173 {
5174 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5175 int rc;
5176
5177 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5178 smp_mb__after_atomic();
5179 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5180 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5181 return;
5182 }
5183
5184 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5185 bnxt_cfg_rx_mode(bp);
5186
5187 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5188 bnxt_cfg_ntp_filters(bp);
5189 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5190 rc = bnxt_update_link(bp, true);
5191 if (rc)
5192 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5193 rc);
5194 }
5195 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5196 bnxt_hwrm_exec_fwd_req(bp);
5197 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5198 bnxt_hwrm_tunnel_dst_port_alloc(
5199 bp, bp->vxlan_port,
5200 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5201 }
5202 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5203 bnxt_hwrm_tunnel_dst_port_free(
5204 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5205 }
5206 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5207 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5208 * for BNXT_STATE_IN_SP_TASK to clear.
5209 */
5210 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5211 rtnl_lock();
5212 bnxt_reset_task(bp);
5213 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5214 rtnl_unlock();
5215 }
5216
5217 smp_mb__before_atomic();
5218 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5219 }
5220
5221 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5222 {
5223 int rc;
5224 struct bnxt *bp = netdev_priv(dev);
5225
5226 SET_NETDEV_DEV(dev, &pdev->dev);
5227
5228 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5229 rc = pci_enable_device(pdev);
5230 if (rc) {
5231 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5232 goto init_err;
5233 }
5234
5235 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5236 dev_err(&pdev->dev,
5237 "Cannot find PCI device base address, aborting\n");
5238 rc = -ENODEV;
5239 goto init_err_disable;
5240 }
5241
5242 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5243 if (rc) {
5244 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5245 goto init_err_disable;
5246 }
5247
5248 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5249 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5250 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5251 goto init_err_disable;
5252 }
5253
5254 pci_set_master(pdev);
5255
5256 bp->dev = dev;
5257 bp->pdev = pdev;
5258
5259 bp->bar0 = pci_ioremap_bar(pdev, 0);
5260 if (!bp->bar0) {
5261 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5262 rc = -ENOMEM;
5263 goto init_err_release;
5264 }
5265
5266 bp->bar1 = pci_ioremap_bar(pdev, 2);
5267 if (!bp->bar1) {
5268 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5269 rc = -ENOMEM;
5270 goto init_err_release;
5271 }
5272
5273 bp->bar2 = pci_ioremap_bar(pdev, 4);
5274 if (!bp->bar2) {
5275 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5276 rc = -ENOMEM;
5277 goto init_err_release;
5278 }
5279
5280 INIT_WORK(&bp->sp_task, bnxt_sp_task);
5281
5282 spin_lock_init(&bp->ntp_fltr_lock);
5283
5284 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5285 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5286
5287 bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5288 bp->coal_bufs = 20;
5289 bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5290 bp->coal_bufs_irq = 2;
5291
5292 init_timer(&bp->timer);
5293 bp->timer.data = (unsigned long)bp;
5294 bp->timer.function = bnxt_timer;
5295 bp->current_interval = BNXT_TIMER_INTERVAL;
5296
5297 clear_bit(BNXT_STATE_OPEN, &bp->state);
5298
5299 return 0;
5300
5301 init_err_release:
5302 if (bp->bar2) {
5303 pci_iounmap(pdev, bp->bar2);
5304 bp->bar2 = NULL;
5305 }
5306
5307 if (bp->bar1) {
5308 pci_iounmap(pdev, bp->bar1);
5309 bp->bar1 = NULL;
5310 }
5311
5312 if (bp->bar0) {
5313 pci_iounmap(pdev, bp->bar0);
5314 bp->bar0 = NULL;
5315 }
5316
5317 pci_release_regions(pdev);
5318
5319 init_err_disable:
5320 pci_disable_device(pdev);
5321
5322 init_err:
5323 return rc;
5324 }
5325
5326 /* rtnl_lock held */
5327 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5328 {
5329 struct sockaddr *addr = p;
5330 struct bnxt *bp = netdev_priv(dev);
5331 int rc = 0;
5332
5333 if (!is_valid_ether_addr(addr->sa_data))
5334 return -EADDRNOTAVAIL;
5335
5336 #ifdef CONFIG_BNXT_SRIOV
5337 if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5338 return -EADDRNOTAVAIL;
5339 #endif
5340
5341 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5342 return 0;
5343
5344 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5345 if (netif_running(dev)) {
5346 bnxt_close_nic(bp, false, false);
5347 rc = bnxt_open_nic(bp, false, false);
5348 }
5349
5350 return rc;
5351 }
5352
5353 /* rtnl_lock held */
5354 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5355 {
5356 struct bnxt *bp = netdev_priv(dev);
5357
5358 if (new_mtu < 60 || new_mtu > 9000)
5359 return -EINVAL;
5360
5361 if (netif_running(dev))
5362 bnxt_close_nic(bp, false, false);
5363
5364 dev->mtu = new_mtu;
5365 bnxt_set_ring_params(bp);
5366
5367 if (netif_running(dev))
5368 return bnxt_open_nic(bp, false, false);
5369
5370 return 0;
5371 }
5372
5373 static int bnxt_setup_tc(struct net_device *dev, u8 tc)
5374 {
5375 struct bnxt *bp = netdev_priv(dev);
5376
5377 if (tc > bp->max_tc) {
5378 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5379 tc, bp->max_tc);
5380 return -EINVAL;
5381 }
5382
5383 if (netdev_get_num_tc(dev) == tc)
5384 return 0;
5385
5386 if (tc) {
5387 int max_rx_rings, max_tx_rings, rc;
5388 bool sh = false;
5389
5390 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5391 sh = true;
5392
5393 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5394 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5395 return -ENOMEM;
5396 }
5397
5398 /* Needs to close the device and do hw resource re-allocations */
5399 if (netif_running(bp->dev))
5400 bnxt_close_nic(bp, true, false);
5401
5402 if (tc) {
5403 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5404 netdev_set_num_tc(dev, tc);
5405 } else {
5406 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5407 netdev_reset_tc(dev);
5408 }
5409 bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5410 bp->num_stat_ctxs = bp->cp_nr_rings;
5411
5412 if (netif_running(bp->dev))
5413 return bnxt_open_nic(bp, true, false);
5414
5415 return 0;
5416 }
5417
5418 #ifdef CONFIG_RFS_ACCEL
5419 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5420 struct bnxt_ntuple_filter *f2)
5421 {
5422 struct flow_keys *keys1 = &f1->fkeys;
5423 struct flow_keys *keys2 = &f2->fkeys;
5424
5425 if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5426 keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5427 keys1->ports.ports == keys2->ports.ports &&
5428 keys1->basic.ip_proto == keys2->basic.ip_proto &&
5429 keys1->basic.n_proto == keys2->basic.n_proto &&
5430 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5431 return true;
5432
5433 return false;
5434 }
5435
5436 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5437 u16 rxq_index, u32 flow_id)
5438 {
5439 struct bnxt *bp = netdev_priv(dev);
5440 struct bnxt_ntuple_filter *fltr, *new_fltr;
5441 struct flow_keys *fkeys;
5442 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5443 int rc = 0, idx, bit_id;
5444 struct hlist_head *head;
5445
5446 if (skb->encapsulation)
5447 return -EPROTONOSUPPORT;
5448
5449 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5450 if (!new_fltr)
5451 return -ENOMEM;
5452
5453 fkeys = &new_fltr->fkeys;
5454 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5455 rc = -EPROTONOSUPPORT;
5456 goto err_free;
5457 }
5458
5459 if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5460 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5461 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5462 rc = -EPROTONOSUPPORT;
5463 goto err_free;
5464 }
5465
5466 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5467
5468 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5469 head = &bp->ntp_fltr_hash_tbl[idx];
5470 rcu_read_lock();
5471 hlist_for_each_entry_rcu(fltr, head, hash) {
5472 if (bnxt_fltr_match(fltr, new_fltr)) {
5473 rcu_read_unlock();
5474 rc = 0;
5475 goto err_free;
5476 }
5477 }
5478 rcu_read_unlock();
5479
5480 spin_lock_bh(&bp->ntp_fltr_lock);
5481 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5482 BNXT_NTP_FLTR_MAX_FLTR, 0);
5483 if (bit_id < 0) {
5484 spin_unlock_bh(&bp->ntp_fltr_lock);
5485 rc = -ENOMEM;
5486 goto err_free;
5487 }
5488
5489 new_fltr->sw_id = (u16)bit_id;
5490 new_fltr->flow_id = flow_id;
5491 new_fltr->rxq = rxq_index;
5492 hlist_add_head_rcu(&new_fltr->hash, head);
5493 bp->ntp_fltr_count++;
5494 spin_unlock_bh(&bp->ntp_fltr_lock);
5495
5496 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5497 schedule_work(&bp->sp_task);
5498
5499 return new_fltr->sw_id;
5500
5501 err_free:
5502 kfree(new_fltr);
5503 return rc;
5504 }
5505
5506 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5507 {
5508 int i;
5509
5510 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5511 struct hlist_head *head;
5512 struct hlist_node *tmp;
5513 struct bnxt_ntuple_filter *fltr;
5514 int rc;
5515
5516 head = &bp->ntp_fltr_hash_tbl[i];
5517 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5518 bool del = false;
5519
5520 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5521 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5522 fltr->flow_id,
5523 fltr->sw_id)) {
5524 bnxt_hwrm_cfa_ntuple_filter_free(bp,
5525 fltr);
5526 del = true;
5527 }
5528 } else {
5529 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5530 fltr);
5531 if (rc)
5532 del = true;
5533 else
5534 set_bit(BNXT_FLTR_VALID, &fltr->state);
5535 }
5536
5537 if (del) {
5538 spin_lock_bh(&bp->ntp_fltr_lock);
5539 hlist_del_rcu(&fltr->hash);
5540 bp->ntp_fltr_count--;
5541 spin_unlock_bh(&bp->ntp_fltr_lock);
5542 synchronize_rcu();
5543 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5544 kfree(fltr);
5545 }
5546 }
5547 }
5548 }
5549
5550 #else
5551
5552 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5553 {
5554 }
5555
5556 #endif /* CONFIG_RFS_ACCEL */
5557
5558 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5559 __be16 port)
5560 {
5561 struct bnxt *bp = netdev_priv(dev);
5562
5563 if (!netif_running(dev))
5564 return;
5565
5566 if (sa_family != AF_INET6 && sa_family != AF_INET)
5567 return;
5568
5569 if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5570 return;
5571
5572 bp->vxlan_port_cnt++;
5573 if (bp->vxlan_port_cnt == 1) {
5574 bp->vxlan_port = port;
5575 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5576 schedule_work(&bp->sp_task);
5577 }
5578 }
5579
5580 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5581 __be16 port)
5582 {
5583 struct bnxt *bp = netdev_priv(dev);
5584
5585 if (!netif_running(dev))
5586 return;
5587
5588 if (sa_family != AF_INET6 && sa_family != AF_INET)
5589 return;
5590
5591 if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5592 bp->vxlan_port_cnt--;
5593
5594 if (bp->vxlan_port_cnt == 0) {
5595 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5596 schedule_work(&bp->sp_task);
5597 }
5598 }
5599 }
5600
5601 static const struct net_device_ops bnxt_netdev_ops = {
5602 .ndo_open = bnxt_open,
5603 .ndo_start_xmit = bnxt_start_xmit,
5604 .ndo_stop = bnxt_close,
5605 .ndo_get_stats64 = bnxt_get_stats64,
5606 .ndo_set_rx_mode = bnxt_set_rx_mode,
5607 .ndo_do_ioctl = bnxt_ioctl,
5608 .ndo_validate_addr = eth_validate_addr,
5609 .ndo_set_mac_address = bnxt_change_mac_addr,
5610 .ndo_change_mtu = bnxt_change_mtu,
5611 .ndo_fix_features = bnxt_fix_features,
5612 .ndo_set_features = bnxt_set_features,
5613 .ndo_tx_timeout = bnxt_tx_timeout,
5614 #ifdef CONFIG_BNXT_SRIOV
5615 .ndo_get_vf_config = bnxt_get_vf_config,
5616 .ndo_set_vf_mac = bnxt_set_vf_mac,
5617 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
5618 .ndo_set_vf_rate = bnxt_set_vf_bw,
5619 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
5620 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
5621 #endif
5622 #ifdef CONFIG_NET_POLL_CONTROLLER
5623 .ndo_poll_controller = bnxt_poll_controller,
5624 #endif
5625 .ndo_setup_tc = bnxt_setup_tc,
5626 #ifdef CONFIG_RFS_ACCEL
5627 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
5628 #endif
5629 .ndo_add_vxlan_port = bnxt_add_vxlan_port,
5630 .ndo_del_vxlan_port = bnxt_del_vxlan_port,
5631 #ifdef CONFIG_NET_RX_BUSY_POLL
5632 .ndo_busy_poll = bnxt_busy_poll,
5633 #endif
5634 };
5635
5636 static void bnxt_remove_one(struct pci_dev *pdev)
5637 {
5638 struct net_device *dev = pci_get_drvdata(pdev);
5639 struct bnxt *bp = netdev_priv(dev);
5640
5641 if (BNXT_PF(bp))
5642 bnxt_sriov_disable(bp);
5643
5644 unregister_netdev(dev);
5645 cancel_work_sync(&bp->sp_task);
5646 bp->sp_event = 0;
5647
5648 bnxt_hwrm_func_drv_unrgtr(bp);
5649 bnxt_free_hwrm_resources(bp);
5650 pci_iounmap(pdev, bp->bar2);
5651 pci_iounmap(pdev, bp->bar1);
5652 pci_iounmap(pdev, bp->bar0);
5653 free_netdev(dev);
5654
5655 pci_release_regions(pdev);
5656 pci_disable_device(pdev);
5657 }
5658
5659 static int bnxt_probe_phy(struct bnxt *bp)
5660 {
5661 int rc = 0;
5662 struct bnxt_link_info *link_info = &bp->link_info;
5663 char phy_ver[PHY_VER_STR_LEN];
5664
5665 rc = bnxt_update_link(bp, false);
5666 if (rc) {
5667 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5668 rc);
5669 return rc;
5670 }
5671
5672 /*initialize the ethool setting copy with NVM settings */
5673 if (BNXT_AUTO_MODE(link_info->auto_mode))
5674 link_info->autoneg |= BNXT_AUTONEG_SPEED;
5675
5676 if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5677 if (link_info->auto_pause_setting == BNXT_LINK_PAUSE_BOTH)
5678 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
5679 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5680 } else if (link_info->force_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5681 link_info->req_flow_ctrl = link_info->force_pause_setting;
5682 }
5683 link_info->req_duplex = link_info->duplex_setting;
5684 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5685 link_info->req_link_speed = link_info->auto_link_speed;
5686 else
5687 link_info->req_link_speed = link_info->force_link_speed;
5688 link_info->advertising = link_info->auto_link_speeds;
5689 snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5690 link_info->phy_ver[0],
5691 link_info->phy_ver[1],
5692 link_info->phy_ver[2]);
5693 strcat(bp->fw_ver_str, phy_ver);
5694 return rc;
5695 }
5696
5697 static int bnxt_get_max_irq(struct pci_dev *pdev)
5698 {
5699 u16 ctrl;
5700
5701 if (!pdev->msix_cap)
5702 return 1;
5703
5704 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5705 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5706 }
5707
5708 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
5709 int *max_cp)
5710 {
5711 int max_ring_grps = 0;
5712
5713 #ifdef CONFIG_BNXT_SRIOV
5714 if (!BNXT_PF(bp)) {
5715 *max_tx = bp->vf.max_tx_rings;
5716 *max_rx = bp->vf.max_rx_rings;
5717 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5718 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
5719 max_ring_grps = bp->vf.max_hw_ring_grps;
5720 } else
5721 #endif
5722 {
5723 *max_tx = bp->pf.max_tx_rings;
5724 *max_rx = bp->pf.max_rx_rings;
5725 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5726 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
5727 max_ring_grps = bp->pf.max_hw_ring_grps;
5728 }
5729
5730 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5731 *max_rx >>= 1;
5732 *max_rx = min_t(int, *max_rx, max_ring_grps);
5733 }
5734
5735 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
5736 {
5737 int rx, tx, cp;
5738
5739 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
5740 if (!rx || !tx || !cp)
5741 return -ENOMEM;
5742
5743 *max_rx = rx;
5744 *max_tx = tx;
5745 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
5746 }
5747
5748 static int bnxt_set_dflt_rings(struct bnxt *bp)
5749 {
5750 int dflt_rings, max_rx_rings, max_tx_rings, rc;
5751 bool sh = true;
5752
5753 if (sh)
5754 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5755 dflt_rings = netif_get_num_default_rss_queues();
5756 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5757 if (rc)
5758 return rc;
5759 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5760 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5761 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5762 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5763 bp->tx_nr_rings + bp->rx_nr_rings;
5764 bp->num_stat_ctxs = bp->cp_nr_rings;
5765 return rc;
5766 }
5767
5768 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5769 {
5770 static int version_printed;
5771 struct net_device *dev;
5772 struct bnxt *bp;
5773 int rc, max_irqs;
5774
5775 if (version_printed++ == 0)
5776 pr_info("%s", version);
5777
5778 max_irqs = bnxt_get_max_irq(pdev);
5779 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5780 if (!dev)
5781 return -ENOMEM;
5782
5783 bp = netdev_priv(dev);
5784
5785 if (bnxt_vf_pciid(ent->driver_data))
5786 bp->flags |= BNXT_FLAG_VF;
5787
5788 if (pdev->msix_cap)
5789 bp->flags |= BNXT_FLAG_MSIX_CAP;
5790
5791 rc = bnxt_init_board(pdev, dev);
5792 if (rc < 0)
5793 goto init_err_free;
5794
5795 dev->netdev_ops = &bnxt_netdev_ops;
5796 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5797 dev->ethtool_ops = &bnxt_ethtool_ops;
5798
5799 pci_set_drvdata(pdev, dev);
5800
5801 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5802 NETIF_F_TSO | NETIF_F_TSO6 |
5803 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5804 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5805 NETIF_F_RXHASH |
5806 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5807
5808 dev->hw_enc_features =
5809 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5810 NETIF_F_TSO | NETIF_F_TSO6 |
5811 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5812 NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5813 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5814 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5815 NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5816 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5817 dev->priv_flags |= IFF_UNICAST_FLT;
5818
5819 #ifdef CONFIG_BNXT_SRIOV
5820 init_waitqueue_head(&bp->sriov_cfg_wait);
5821 #endif
5822 rc = bnxt_alloc_hwrm_resources(bp);
5823 if (rc)
5824 goto init_err;
5825
5826 mutex_init(&bp->hwrm_cmd_lock);
5827 bnxt_hwrm_ver_get(bp);
5828
5829 rc = bnxt_hwrm_func_drv_rgtr(bp);
5830 if (rc)
5831 goto init_err;
5832
5833 /* Get the MAX capabilities for this function */
5834 rc = bnxt_hwrm_func_qcaps(bp);
5835 if (rc) {
5836 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5837 rc);
5838 rc = -1;
5839 goto init_err;
5840 }
5841
5842 rc = bnxt_hwrm_queue_qportcfg(bp);
5843 if (rc) {
5844 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5845 rc);
5846 rc = -1;
5847 goto init_err;
5848 }
5849
5850 bnxt_set_tpa_flags(bp);
5851 bnxt_set_ring_params(bp);
5852 if (BNXT_PF(bp))
5853 bp->pf.max_irqs = max_irqs;
5854 #if defined(CONFIG_BNXT_SRIOV)
5855 else
5856 bp->vf.max_irqs = max_irqs;
5857 #endif
5858 bnxt_set_dflt_rings(bp);
5859
5860 if (BNXT_PF(bp)) {
5861 dev->hw_features |= NETIF_F_NTUPLE;
5862 if (bnxt_rfs_capable(bp)) {
5863 bp->flags |= BNXT_FLAG_RFS;
5864 dev->features |= NETIF_F_NTUPLE;
5865 }
5866 }
5867
5868 if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5869 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5870
5871 rc = bnxt_probe_phy(bp);
5872 if (rc)
5873 goto init_err;
5874
5875 rc = register_netdev(dev);
5876 if (rc)
5877 goto init_err;
5878
5879 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5880 board_info[ent->driver_data].name,
5881 (long)pci_resource_start(pdev, 0), dev->dev_addr);
5882
5883 return 0;
5884
5885 init_err:
5886 pci_iounmap(pdev, bp->bar0);
5887 pci_release_regions(pdev);
5888 pci_disable_device(pdev);
5889
5890 init_err_free:
5891 free_netdev(dev);
5892 return rc;
5893 }
5894
5895 static struct pci_driver bnxt_pci_driver = {
5896 .name = DRV_MODULE_NAME,
5897 .id_table = bnxt_pci_tbl,
5898 .probe = bnxt_init_one,
5899 .remove = bnxt_remove_one,
5900 #if defined(CONFIG_BNXT_SRIOV)
5901 .sriov_configure = bnxt_sriov_configure,
5902 #endif
5903 };
5904
5905 module_pci_driver(bnxt_pci_driver);
Linux kernel - Deliverables
This page took 0.147826 seconds and 6 git commands to generate.