1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
59 #define BNXT_TX_TIMEOUT (5 * HZ)
61 static const char version
[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION
);
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
72 #define BNXT_TX_PUSH_THRESH 92
85 /* indexed by enum above */
89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
99 static const struct pci_device_id bnxt_pci_tbl
[] = {
100 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
101 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
102 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
103 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
104 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
105 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
106 #ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
108 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
113 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
115 static const u16 bnxt_vf_req_snif
[] = {
118 HWRM_CFA_L2_FILTER_ALLOC
,
121 static bool bnxt_vf_pciid(enum board_idx idx
)
123 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
);
126 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
130 #define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
133 #define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
136 #define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
139 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
141 /* Tell compiler to fetch tx indices from memory. */
144 return bp
->tx_ring_size
-
145 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
148 static const u16 bnxt_lhint_arr
[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
150 TX_BD_FLAGS_LHINT_512_TO_1023
,
151 TX_BD_FLAGS_LHINT_1024_TO_2047
,
152 TX_BD_FLAGS_LHINT_1024_TO_2047
,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
170 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
172 struct bnxt
*bp
= netdev_priv(dev
);
174 struct tx_bd_ext
*txbd1
;
175 struct netdev_queue
*txq
;
178 unsigned int length
, pad
= 0;
179 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
181 struct pci_dev
*pdev
= bp
->pdev
;
182 struct bnxt_tx_ring_info
*txr
;
183 struct bnxt_sw_tx_bd
*tx_buf
;
185 i
= skb_get_queue_mapping(skb
);
186 if (unlikely(i
>= bp
->tx_nr_rings
)) {
187 dev_kfree_skb_any(skb
);
191 txr
= &bp
->tx_ring
[i
];
192 txq
= netdev_get_tx_queue(dev
, i
);
195 free_size
= bnxt_tx_avail(bp
, txr
);
196 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
197 netif_tx_stop_queue(txq
);
198 return NETDEV_TX_BUSY
;
202 len
= skb_headlen(skb
);
203 last_frag
= skb_shinfo(skb
)->nr_frags
;
205 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
207 txbd
->tx_bd_opaque
= prod
;
209 tx_buf
= &txr
->tx_buf_ring
[prod
];
211 tx_buf
->nr_frags
= last_frag
;
215 if (skb_vlan_tag_present(skb
)) {
216 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
217 skb_vlan_tag_get(skb
);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
221 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
222 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
225 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
226 struct tx_push_bd
*push
= txr
->tx_push
;
227 struct tx_bd
*tx_push
= &push
->txbd1
;
228 struct tx_bd_ext
*tx_push1
= &push
->txbd2
;
229 void *pdata
= tx_push1
+ 1;
232 /* Set COAL_NOW to be ready quickly for the next push */
233 tx_push
->tx_bd_len_flags_type
=
234 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
235 TX_BD_TYPE_LONG_TX_BD
|
236 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
237 TX_BD_FLAGS_COAL_NOW
|
238 TX_BD_FLAGS_PACKET_END
|
239 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
241 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
242 tx_push1
->tx_bd_hsize_lflags
=
243 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
245 tx_push1
->tx_bd_hsize_lflags
= 0;
247 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
248 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
250 skb_copy_from_linear_data(skb
, pdata
, len
);
252 for (j
= 0; j
< last_frag
; j
++) {
253 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
256 fptr
= skb_frag_address_safe(frag
);
260 memcpy(pdata
, fptr
, skb_frag_size(frag
));
261 pdata
+= skb_frag_size(frag
);
264 memcpy(txbd
, tx_push
, sizeof(*txbd
));
265 prod
= NEXT_TX(prod
);
266 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
267 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
268 prod
= NEXT_TX(prod
);
270 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
273 netdev_tx_sent_queue(txq
, skb
->len
);
275 __iowrite64_copy(txr
->tx_doorbell
, push
,
276 (length
+ sizeof(*push
) + 8) / 8);
284 if (length
< BNXT_MIN_PKT_SIZE
) {
285 pad
= BNXT_MIN_PKT_SIZE
- length
;
286 if (skb_pad(skb
, pad
)) {
287 /* SKB already freed. */
291 length
= BNXT_MIN_PKT_SIZE
;
294 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
296 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
297 dev_kfree_skb_any(skb
);
302 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
303 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
304 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
306 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
308 prod
= NEXT_TX(prod
);
309 txbd1
= (struct tx_bd_ext
*)
310 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
312 txbd1
->tx_bd_hsize_lflags
= 0;
313 if (skb_is_gso(skb
)) {
316 if (skb
->encapsulation
)
317 hdr_len
= skb_inner_network_offset(skb
) +
318 skb_inner_network_header_len(skb
) +
319 inner_tcp_hdrlen(skb
);
321 hdr_len
= skb_transport_offset(skb
) +
324 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
326 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
327 length
= skb_shinfo(skb
)->gso_size
;
328 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
330 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
331 txbd1
->tx_bd_hsize_lflags
=
332 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
333 txbd1
->tx_bd_mss
= 0;
337 flags
|= bnxt_lhint_arr
[length
];
338 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
340 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
341 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
342 for (i
= 0; i
< last_frag
; i
++) {
343 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
345 prod
= NEXT_TX(prod
);
346 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
348 len
= skb_frag_size(frag
);
349 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
352 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
355 tx_buf
= &txr
->tx_buf_ring
[prod
];
356 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
358 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
360 flags
= len
<< TX_BD_LEN_SHIFT
;
361 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
365 txbd
->tx_bd_len_flags_type
=
366 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
367 TX_BD_FLAGS_PACKET_END
);
369 netdev_tx_sent_queue(txq
, skb
->len
);
371 /* Sync BD data before updating doorbell */
374 prod
= NEXT_TX(prod
);
377 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
378 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
384 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
385 netif_tx_stop_queue(txq
);
387 /* netif_tx_stop_queue() must be done before checking
388 * tx index in bnxt_tx_avail() below, because in
389 * bnxt_tx_int(), we update tx index before checking for
390 * netif_tx_queue_stopped().
393 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
394 netif_tx_wake_queue(txq
);
401 /* start back at beginning and unmap skb */
403 tx_buf
= &txr
->tx_buf_ring
[prod
];
405 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
406 skb_headlen(skb
), PCI_DMA_TODEVICE
);
407 prod
= NEXT_TX(prod
);
409 /* unmap remaining mapped pages */
410 for (i
= 0; i
< last_frag
; i
++) {
411 prod
= NEXT_TX(prod
);
412 tx_buf
= &txr
->tx_buf_ring
[prod
];
413 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
414 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
418 dev_kfree_skb_any(skb
);
422 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
424 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
425 int index
= txr
- &bp
->tx_ring
[0];
426 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
427 u16 cons
= txr
->tx_cons
;
428 struct pci_dev
*pdev
= bp
->pdev
;
430 unsigned int tx_bytes
= 0;
432 for (i
= 0; i
< nr_pkts
; i
++) {
433 struct bnxt_sw_tx_bd
*tx_buf
;
437 tx_buf
= &txr
->tx_buf_ring
[cons
];
438 cons
= NEXT_TX(cons
);
442 if (tx_buf
->is_push
) {
447 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
448 skb_headlen(skb
), PCI_DMA_TODEVICE
);
449 last
= tx_buf
->nr_frags
;
451 for (j
= 0; j
< last
; j
++) {
452 cons
= NEXT_TX(cons
);
453 tx_buf
= &txr
->tx_buf_ring
[cons
];
456 dma_unmap_addr(tx_buf
, mapping
),
457 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
462 cons
= NEXT_TX(cons
);
464 tx_bytes
+= skb
->len
;
465 dev_kfree_skb_any(skb
);
468 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
471 /* Need to make the tx_cons update visible to bnxt_start_xmit()
472 * before checking for netif_tx_queue_stopped(). Without the
473 * memory barrier, there is a small possibility that bnxt_start_xmit()
474 * will miss it and cause the queue to be stopped forever.
478 if (unlikely(netif_tx_queue_stopped(txq
)) &&
479 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
480 __netif_tx_lock(txq
, smp_processor_id());
481 if (netif_tx_queue_stopped(txq
) &&
482 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
483 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
484 netif_tx_wake_queue(txq
);
485 __netif_tx_unlock(txq
);
489 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
493 struct pci_dev
*pdev
= bp
->pdev
;
495 data
= kmalloc(bp
->rx_buf_size
, gfp
);
499 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
500 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
502 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
509 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
510 struct bnxt_rx_ring_info
*rxr
,
513 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
514 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
518 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
523 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
525 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
530 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
533 u16 prod
= rxr
->rx_prod
;
534 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
535 struct rx_bd
*cons_bd
, *prod_bd
;
537 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
538 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
540 prod_rx_buf
->data
= data
;
542 dma_unmap_addr_set(prod_rx_buf
, mapping
,
543 dma_unmap_addr(cons_rx_buf
, mapping
));
545 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
546 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
548 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
551 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
553 u16 next
, max
= rxr
->rx_agg_bmap_size
;
555 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
557 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
561 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
562 struct bnxt_rx_ring_info
*rxr
,
566 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
567 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
568 struct pci_dev
*pdev
= bp
->pdev
;
571 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
573 page
= alloc_page(gfp
);
577 mapping
= dma_map_page(&pdev
->dev
, page
, 0, PAGE_SIZE
,
579 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
584 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
585 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
587 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
588 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
589 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
591 rx_agg_buf
->page
= page
;
592 rx_agg_buf
->mapping
= mapping
;
593 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
594 rxbd
->rx_bd_opaque
= sw_prod
;
598 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
601 struct bnxt
*bp
= bnapi
->bp
;
602 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
603 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
604 u16 prod
= rxr
->rx_agg_prod
;
605 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
608 for (i
= 0; i
< agg_bufs
; i
++) {
610 struct rx_agg_cmp
*agg
;
611 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
612 struct rx_bd
*prod_bd
;
615 agg
= (struct rx_agg_cmp
*)
616 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
617 cons
= agg
->rx_agg_cmp_opaque
;
618 __clear_bit(cons
, rxr
->rx_agg_bmap
);
620 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
621 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
623 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
624 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
625 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
627 /* It is possible for sw_prod to be equal to cons, so
628 * set cons_rx_buf->page to NULL first.
630 page
= cons_rx_buf
->page
;
631 cons_rx_buf
->page
= NULL
;
632 prod_rx_buf
->page
= page
;
634 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
636 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
638 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
639 prod_bd
->rx_bd_opaque
= sw_prod
;
641 prod
= NEXT_RX_AGG(prod
);
642 sw_prod
= NEXT_RX_AGG(sw_prod
);
643 cp_cons
= NEXT_CMP(cp_cons
);
645 rxr
->rx_agg_prod
= prod
;
646 rxr
->rx_sw_agg_prod
= sw_prod
;
649 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
650 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
651 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
657 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
659 bnxt_reuse_rx_data(rxr
, cons
, data
);
663 skb
= build_skb(data
, 0);
664 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
671 skb_reserve(skb
, BNXT_RX_OFFSET
);
676 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
677 struct sk_buff
*skb
, u16 cp_cons
,
680 struct pci_dev
*pdev
= bp
->pdev
;
681 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
682 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
683 u16 prod
= rxr
->rx_agg_prod
;
686 for (i
= 0; i
< agg_bufs
; i
++) {
688 struct rx_agg_cmp
*agg
;
689 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
693 agg
= (struct rx_agg_cmp
*)
694 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
695 cons
= agg
->rx_agg_cmp_opaque
;
696 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
697 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
699 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
700 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
, 0, frag_len
);
701 __clear_bit(cons
, rxr
->rx_agg_bmap
);
703 /* It is possible for bnxt_alloc_rx_page() to allocate
704 * a sw_prod index that equals the cons index, so we
705 * need to clear the cons entry now.
707 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
708 page
= cons_rx_buf
->page
;
709 cons_rx_buf
->page
= NULL
;
711 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
712 struct skb_shared_info
*shinfo
;
713 unsigned int nr_frags
;
715 shinfo
= skb_shinfo(skb
);
716 nr_frags
= --shinfo
->nr_frags
;
717 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
721 cons_rx_buf
->page
= page
;
723 /* Update prod since possibly some pages have been
726 rxr
->rx_agg_prod
= prod
;
727 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
731 dma_unmap_page(&pdev
->dev
, mapping
, PAGE_SIZE
,
734 skb
->data_len
+= frag_len
;
735 skb
->len
+= frag_len
;
736 skb
->truesize
+= PAGE_SIZE
;
738 prod
= NEXT_RX_AGG(prod
);
739 cp_cons
= NEXT_CMP(cp_cons
);
741 rxr
->rx_agg_prod
= prod
;
745 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
746 u8 agg_bufs
, u32
*raw_cons
)
749 struct rx_agg_cmp
*agg
;
751 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
752 last
= RING_CMP(*raw_cons
);
753 agg
= (struct rx_agg_cmp
*)
754 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
755 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
758 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
762 struct bnxt
*bp
= bnapi
->bp
;
763 struct pci_dev
*pdev
= bp
->pdev
;
766 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
770 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
771 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
773 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
775 dma_sync_single_for_device(&pdev
->dev
, mapping
,
783 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
784 struct rx_tpa_start_cmp
*tpa_start
,
785 struct rx_tpa_start_cmp_ext
*tpa_start1
)
787 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
789 struct bnxt_tpa_info
*tpa_info
;
790 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
791 struct rx_bd
*prod_bd
;
794 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
796 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
797 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
798 tpa_info
= &rxr
->rx_tpa
[agg_id
];
800 prod_rx_buf
->data
= tpa_info
->data
;
802 mapping
= tpa_info
->mapping
;
803 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
805 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
807 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
809 tpa_info
->data
= cons_rx_buf
->data
;
810 cons_rx_buf
->data
= NULL
;
811 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
814 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
815 RX_TPA_START_CMP_LEN_SHIFT
;
816 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
817 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
819 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
820 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
821 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
823 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
825 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
827 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
828 tpa_info
->gso_type
= 0;
829 if (netif_msg_rx_err(bp
))
830 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
832 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
833 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
835 rxr
->rx_prod
= NEXT_RX(prod
);
836 cons
= NEXT_RX(cons
);
837 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
839 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
840 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
841 cons_rx_buf
->data
= NULL
;
844 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
845 u16 cp_cons
, u32 agg_bufs
)
848 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
851 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
852 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
854 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt_tpa_info
*tpa_info
,
855 struct rx_tpa_end_cmp
*tpa_end
,
856 struct rx_tpa_end_cmp_ext
*tpa_end1
,
861 int payload_off
, tcp_opt_len
= 0;
865 segs
= TPA_END_TPA_SEGS(tpa_end
);
869 NAPI_GRO_CB(skb
)->count
= segs
;
870 skb_shinfo(skb
)->gso_size
=
871 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
872 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
873 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
874 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
875 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
876 if (TPA_END_GRO_TS(tpa_end
))
879 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
882 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
884 skb_set_network_header(skb
, nw_off
);
886 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
887 len
= skb
->len
- skb_transport_offset(skb
);
889 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
890 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
893 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
895 skb_set_network_header(skb
, nw_off
);
897 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
898 len
= skb
->len
- skb_transport_offset(skb
);
900 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
902 dev_kfree_skb_any(skb
);
905 tcp_gro_complete(skb
);
907 if (nw_off
) { /* tunnel */
908 struct udphdr
*uh
= NULL
;
910 if (skb
->protocol
== htons(ETH_P_IP
)) {
911 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
913 if (iph
->protocol
== IPPROTO_UDP
)
914 uh
= (struct udphdr
*)(iph
+ 1);
916 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
918 if (iph
->nexthdr
== IPPROTO_UDP
)
919 uh
= (struct udphdr
*)(iph
+ 1);
923 skb_shinfo(skb
)->gso_type
|=
924 SKB_GSO_UDP_TUNNEL_CSUM
;
926 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
933 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
934 struct bnxt_napi
*bnapi
,
936 struct rx_tpa_end_cmp
*tpa_end
,
937 struct rx_tpa_end_cmp_ext
*tpa_end1
,
940 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
941 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
942 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
944 u16 cp_cons
= RING_CMP(*raw_cons
);
946 struct bnxt_tpa_info
*tpa_info
;
950 tpa_info
= &rxr
->rx_tpa
[agg_id
];
951 data
= tpa_info
->data
;
954 mapping
= tpa_info
->mapping
;
956 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
957 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
960 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
961 return ERR_PTR(-EBUSY
);
964 cp_cons
= NEXT_CMP(cp_cons
);
967 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
968 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
969 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
970 agg_bufs
, (int)MAX_SKB_FRAGS
);
974 if (len
<= bp
->rx_copy_thresh
) {
975 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
977 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
982 dma_addr_t new_mapping
;
984 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
986 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
990 tpa_info
->data
= new_data
;
991 tpa_info
->mapping
= new_mapping
;
993 skb
= build_skb(data
, 0);
994 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
999 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1002 skb_reserve(skb
, BNXT_RX_OFFSET
);
1007 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1009 /* Page reuse already handled by bnxt_rx_pages(). */
1013 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1015 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1016 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1018 if (tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) {
1019 netdev_features_t features
= skb
->dev
->features
;
1020 u16 vlan_proto
= tpa_info
->metadata
>>
1021 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1023 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1024 vlan_proto
== ETH_P_8021Q
) ||
1025 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1026 vlan_proto
== ETH_P_8021AD
)) {
1027 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1028 tpa_info
->metadata
&
1029 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1033 skb_checksum_none_assert(skb
);
1034 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1035 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1037 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1040 if (TPA_END_GRO(tpa_end
))
1041 skb
= bnxt_gro_skb(tpa_info
, tpa_end
, tpa_end1
, skb
);
1046 /* returns the following:
1047 * 1 - 1 packet successfully received
1048 * 0 - successful TPA_START, packet not completed yet
1049 * -EBUSY - completion ring does not have all the agg buffers yet
1050 * -ENOMEM - packet aborted due to out of memory
1051 * -EIO - packet aborted due to hw error indicated in BD
1053 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1056 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1057 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1058 struct net_device
*dev
= bp
->dev
;
1059 struct rx_cmp
*rxcmp
;
1060 struct rx_cmp_ext
*rxcmp1
;
1061 u32 tmp_raw_cons
= *raw_cons
;
1062 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1063 struct bnxt_sw_rx_bd
*rx_buf
;
1065 u8
*data
, agg_bufs
, cmp_type
;
1066 dma_addr_t dma_addr
;
1067 struct sk_buff
*skb
;
1070 rxcmp
= (struct rx_cmp
*)
1071 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1073 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1074 cp_cons
= RING_CMP(tmp_raw_cons
);
1075 rxcmp1
= (struct rx_cmp_ext
*)
1076 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1078 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1081 cmp_type
= RX_CMP_TYPE(rxcmp
);
1083 prod
= rxr
->rx_prod
;
1085 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1086 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1087 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1089 goto next_rx_no_prod
;
1091 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1092 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1093 (struct rx_tpa_end_cmp
*)rxcmp
,
1094 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1097 if (unlikely(IS_ERR(skb
)))
1102 skb_record_rx_queue(skb
, bnapi
->index
);
1103 skb_mark_napi_id(skb
, &bnapi
->napi
);
1104 if (bnxt_busy_polling(bnapi
))
1105 netif_receive_skb(skb
);
1107 napi_gro_receive(&bnapi
->napi
, skb
);
1110 goto next_rx_no_prod
;
1113 cons
= rxcmp
->rx_cmp_opaque
;
1114 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1115 data
= rx_buf
->data
;
1118 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1119 RX_CMP_AGG_BUFS_SHIFT
;
1122 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1125 cp_cons
= NEXT_CMP(cp_cons
);
1129 rx_buf
->data
= NULL
;
1130 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1131 bnxt_reuse_rx_data(rxr
, cons
, data
);
1133 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1139 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1140 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1142 if (len
<= bp
->rx_copy_thresh
) {
1143 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1144 bnxt_reuse_rx_data(rxr
, cons
, data
);
1150 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1158 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1165 if (RX_CMP_HASH_VALID(rxcmp
)) {
1166 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1167 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1169 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1170 if (hash_type
!= 1 && hash_type
!= 3)
1171 type
= PKT_HASH_TYPE_L3
;
1172 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1175 skb
->protocol
= eth_type_trans(skb
, dev
);
1177 if (rxcmp1
->rx_cmp_flags2
&
1178 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) {
1179 netdev_features_t features
= skb
->dev
->features
;
1180 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1181 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1183 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1184 vlan_proto
== ETH_P_8021Q
) ||
1185 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1186 vlan_proto
== ETH_P_8021AD
))
1187 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1189 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1192 skb_checksum_none_assert(skb
);
1193 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1194 if (dev
->features
& NETIF_F_RXCSUM
) {
1195 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1196 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1199 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1200 if (dev
->features
& NETIF_F_RXCSUM
)
1201 cpr
->rx_l4_csum_errors
++;
1205 skb_record_rx_queue(skb
, bnapi
->index
);
1206 skb_mark_napi_id(skb
, &bnapi
->napi
);
1207 if (bnxt_busy_polling(bnapi
))
1208 netif_receive_skb(skb
);
1210 napi_gro_receive(&bnapi
->napi
, skb
);
1214 rxr
->rx_prod
= NEXT_RX(prod
);
1217 *raw_cons
= tmp_raw_cons
;
1222 static int bnxt_async_event_process(struct bnxt
*bp
,
1223 struct hwrm_async_event_cmpl
*cmpl
)
1225 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1227 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1229 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1230 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1231 schedule_work(&bp
->sp_task
);
1234 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1241 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1243 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1244 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1245 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1246 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1248 switch (cmpl_type
) {
1249 case CMPL_BASE_TYPE_HWRM_DONE
:
1250 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1251 if (seq_id
== bp
->hwrm_intr_seq_id
)
1252 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1254 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1257 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1258 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1260 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1261 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1262 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1267 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1268 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1269 schedule_work(&bp
->sp_task
);
1272 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1273 bnxt_async_event_process(bp
,
1274 (struct hwrm_async_event_cmpl
*)txcmp
);
1283 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1285 struct bnxt_napi
*bnapi
= dev_instance
;
1286 struct bnxt
*bp
= bnapi
->bp
;
1287 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1288 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1290 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1291 napi_schedule(&bnapi
->napi
);
1295 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1297 u32 raw_cons
= cpr
->cp_raw_cons
;
1298 u16 cons
= RING_CMP(raw_cons
);
1299 struct tx_cmp
*txcmp
;
1301 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1303 return TX_CMP_VALID(txcmp
, raw_cons
);
1306 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1308 struct bnxt_napi
*bnapi
= dev_instance
;
1309 struct bnxt
*bp
= bnapi
->bp
;
1310 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1311 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1314 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1316 if (!bnxt_has_work(bp
, cpr
)) {
1317 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1318 /* return if erroneous interrupt */
1319 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1323 /* disable ring IRQ */
1324 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1326 /* Return here if interrupt is shared and is disabled. */
1327 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1330 napi_schedule(&bnapi
->napi
);
1334 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1336 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1337 u32 raw_cons
= cpr
->cp_raw_cons
;
1341 bool rx_event
= false;
1342 bool agg_event
= false;
1343 struct tx_cmp
*txcmp
;
1348 cons
= RING_CMP(raw_cons
);
1349 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1351 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1354 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1356 /* return full budget so NAPI will complete. */
1357 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1359 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1360 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1361 if (likely(rc
>= 0))
1363 else if (rc
== -EBUSY
) /* partial completion */
1366 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1367 CMPL_BASE_TYPE_HWRM_DONE
) ||
1368 (TX_CMP_TYPE(txcmp
) ==
1369 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1370 (TX_CMP_TYPE(txcmp
) ==
1371 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1372 bnxt_hwrm_handler(bp
, txcmp
);
1374 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1376 if (rx_pkts
== budget
)
1380 cpr
->cp_raw_cons
= raw_cons
;
1381 /* ACK completion ring before freeing tx ring and producing new
1382 * buffers in rx/agg rings to prevent overflowing the completion
1385 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1388 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1391 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1393 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1394 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1396 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1397 rxr
->rx_agg_doorbell
);
1398 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1399 rxr
->rx_agg_doorbell
);
1405 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1407 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1408 struct bnxt
*bp
= bnapi
->bp
;
1409 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1412 if (!bnxt_lock_napi(bnapi
))
1416 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1418 if (work_done
>= budget
)
1421 if (!bnxt_has_work(bp
, cpr
)) {
1422 napi_complete(napi
);
1423 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1428 bnxt_unlock_napi(bnapi
);
1432 #ifdef CONFIG_NET_RX_BUSY_POLL
1433 static int bnxt_busy_poll(struct napi_struct
*napi
)
1435 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1436 struct bnxt
*bp
= bnapi
->bp
;
1437 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1438 int rx_work
, budget
= 4;
1440 if (atomic_read(&bp
->intr_sem
) != 0)
1441 return LL_FLUSH_FAILED
;
1443 if (!bnxt_lock_poll(bnapi
))
1444 return LL_FLUSH_BUSY
;
1446 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1448 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1450 bnxt_unlock_poll(bnapi
);
1455 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1458 struct pci_dev
*pdev
= bp
->pdev
;
1463 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1464 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1465 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1468 for (j
= 0; j
< max_idx
;) {
1469 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1470 struct sk_buff
*skb
= tx_buf
->skb
;
1480 if (tx_buf
->is_push
) {
1486 dma_unmap_single(&pdev
->dev
,
1487 dma_unmap_addr(tx_buf
, mapping
),
1491 last
= tx_buf
->nr_frags
;
1493 for (k
= 0; k
< last
; k
++, j
= NEXT_TX(j
)) {
1494 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1496 tx_buf
= &txr
->tx_buf_ring
[j
];
1499 dma_unmap_addr(tx_buf
, mapping
),
1500 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1504 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1508 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1510 int i
, max_idx
, max_agg_idx
;
1511 struct pci_dev
*pdev
= bp
->pdev
;
1516 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1517 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1518 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1519 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1523 for (j
= 0; j
< MAX_TPA
; j
++) {
1524 struct bnxt_tpa_info
*tpa_info
=
1526 u8
*data
= tpa_info
->data
;
1533 dma_unmap_addr(tpa_info
, mapping
),
1534 bp
->rx_buf_use_size
,
1535 PCI_DMA_FROMDEVICE
);
1537 tpa_info
->data
= NULL
;
1543 for (j
= 0; j
< max_idx
; j
++) {
1544 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1545 u8
*data
= rx_buf
->data
;
1550 dma_unmap_single(&pdev
->dev
,
1551 dma_unmap_addr(rx_buf
, mapping
),
1552 bp
->rx_buf_use_size
,
1553 PCI_DMA_FROMDEVICE
);
1555 rx_buf
->data
= NULL
;
1560 for (j
= 0; j
< max_agg_idx
; j
++) {
1561 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1562 &rxr
->rx_agg_ring
[j
];
1563 struct page
*page
= rx_agg_buf
->page
;
1568 dma_unmap_page(&pdev
->dev
,
1569 dma_unmap_addr(rx_agg_buf
, mapping
),
1570 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1572 rx_agg_buf
->page
= NULL
;
1573 __clear_bit(j
, rxr
->rx_agg_bmap
);
1580 static void bnxt_free_skbs(struct bnxt
*bp
)
1582 bnxt_free_tx_skbs(bp
);
1583 bnxt_free_rx_skbs(bp
);
1586 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1588 struct pci_dev
*pdev
= bp
->pdev
;
1591 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1592 if (!ring
->pg_arr
[i
])
1595 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1596 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1598 ring
->pg_arr
[i
] = NULL
;
1601 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1602 ring
->pg_tbl
, ring
->pg_tbl_map
);
1603 ring
->pg_tbl
= NULL
;
1605 if (ring
->vmem_size
&& *ring
->vmem
) {
1611 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1614 struct pci_dev
*pdev
= bp
->pdev
;
1616 if (ring
->nr_pages
> 1) {
1617 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1625 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1626 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1630 if (!ring
->pg_arr
[i
])
1633 if (ring
->nr_pages
> 1)
1634 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1637 if (ring
->vmem_size
) {
1638 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1645 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1652 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1653 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1654 struct bnxt_ring_struct
*ring
;
1659 kfree(rxr
->rx_agg_bmap
);
1660 rxr
->rx_agg_bmap
= NULL
;
1662 ring
= &rxr
->rx_ring_struct
;
1663 bnxt_free_ring(bp
, ring
);
1665 ring
= &rxr
->rx_agg_ring_struct
;
1666 bnxt_free_ring(bp
, ring
);
1670 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1672 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1677 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1680 if (bp
->flags
& BNXT_FLAG_TPA
)
1683 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1684 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1685 struct bnxt_ring_struct
*ring
;
1687 ring
= &rxr
->rx_ring_struct
;
1689 rc
= bnxt_alloc_ring(bp
, ring
);
1696 ring
= &rxr
->rx_agg_ring_struct
;
1697 rc
= bnxt_alloc_ring(bp
, ring
);
1701 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1702 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1703 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1704 if (!rxr
->rx_agg_bmap
)
1708 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1709 sizeof(struct bnxt_tpa_info
),
1719 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1722 struct pci_dev
*pdev
= bp
->pdev
;
1727 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1728 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1729 struct bnxt_ring_struct
*ring
;
1732 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
1733 txr
->tx_push
, txr
->tx_push_mapping
);
1734 txr
->tx_push
= NULL
;
1737 ring
= &txr
->tx_ring_struct
;
1739 bnxt_free_ring(bp
, ring
);
1743 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
1746 struct pci_dev
*pdev
= bp
->pdev
;
1748 bp
->tx_push_size
= 0;
1749 if (bp
->tx_push_thresh
) {
1752 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
1753 bp
->tx_push_thresh
);
1755 if (push_size
> 128) {
1757 bp
->tx_push_thresh
= 0;
1760 bp
->tx_push_size
= push_size
;
1763 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
1764 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1765 struct bnxt_ring_struct
*ring
;
1767 ring
= &txr
->tx_ring_struct
;
1769 rc
= bnxt_alloc_ring(bp
, ring
);
1773 if (bp
->tx_push_size
) {
1777 /* One pre-allocated DMA buffer to backup
1780 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
1782 &txr
->tx_push_mapping
,
1788 txbd
= &txr
->tx_push
->txbd1
;
1790 mapping
= txr
->tx_push_mapping
+
1791 sizeof(struct tx_push_bd
);
1792 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
1794 memset(txbd
+ 1, 0, sizeof(struct tx_bd_ext
));
1796 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
1797 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
1803 static void bnxt_free_cp_rings(struct bnxt
*bp
)
1810 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1811 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1812 struct bnxt_cp_ring_info
*cpr
;
1813 struct bnxt_ring_struct
*ring
;
1818 cpr
= &bnapi
->cp_ring
;
1819 ring
= &cpr
->cp_ring_struct
;
1821 bnxt_free_ring(bp
, ring
);
1825 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
1829 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1830 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1831 struct bnxt_cp_ring_info
*cpr
;
1832 struct bnxt_ring_struct
*ring
;
1837 cpr
= &bnapi
->cp_ring
;
1838 ring
= &cpr
->cp_ring_struct
;
1840 rc
= bnxt_alloc_ring(bp
, ring
);
1847 static void bnxt_init_ring_struct(struct bnxt
*bp
)
1851 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1852 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1853 struct bnxt_cp_ring_info
*cpr
;
1854 struct bnxt_rx_ring_info
*rxr
;
1855 struct bnxt_tx_ring_info
*txr
;
1856 struct bnxt_ring_struct
*ring
;
1861 cpr
= &bnapi
->cp_ring
;
1862 ring
= &cpr
->cp_ring_struct
;
1863 ring
->nr_pages
= bp
->cp_nr_pages
;
1864 ring
->page_size
= HW_CMPD_RING_SIZE
;
1865 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
1866 ring
->dma_arr
= cpr
->cp_desc_mapping
;
1867 ring
->vmem_size
= 0;
1869 rxr
= bnapi
->rx_ring
;
1873 ring
= &rxr
->rx_ring_struct
;
1874 ring
->nr_pages
= bp
->rx_nr_pages
;
1875 ring
->page_size
= HW_RXBD_RING_SIZE
;
1876 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
1877 ring
->dma_arr
= rxr
->rx_desc_mapping
;
1878 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
1879 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
1881 ring
= &rxr
->rx_agg_ring_struct
;
1882 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
1883 ring
->page_size
= HW_RXBD_RING_SIZE
;
1884 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
1885 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
1886 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
1887 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
1890 txr
= bnapi
->tx_ring
;
1894 ring
= &txr
->tx_ring_struct
;
1895 ring
->nr_pages
= bp
->tx_nr_pages
;
1896 ring
->page_size
= HW_RXBD_RING_SIZE
;
1897 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
1898 ring
->dma_arr
= txr
->tx_desc_mapping
;
1899 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
1900 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
1904 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
1908 struct rx_bd
**rx_buf_ring
;
1910 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
1911 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
1915 rxbd
= rx_buf_ring
[i
];
1919 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
1920 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
1921 rxbd
->rx_bd_opaque
= prod
;
1926 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
1928 struct net_device
*dev
= bp
->dev
;
1929 struct bnxt_rx_ring_info
*rxr
;
1930 struct bnxt_ring_struct
*ring
;
1934 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
1935 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
1937 if (NET_IP_ALIGN
== 2)
1938 type
|= RX_BD_FLAGS_SOP
;
1940 rxr
= &bp
->rx_ring
[ring_nr
];
1941 ring
= &rxr
->rx_ring_struct
;
1942 bnxt_init_rxbd_pages(ring
, type
);
1944 prod
= rxr
->rx_prod
;
1945 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
1946 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1947 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
1948 ring_nr
, i
, bp
->rx_ring_size
);
1951 prod
= NEXT_RX(prod
);
1953 rxr
->rx_prod
= prod
;
1954 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1956 ring
= &rxr
->rx_agg_ring_struct
;
1957 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1959 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
1962 type
= ((u32
)PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
1963 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
1965 bnxt_init_rxbd_pages(ring
, type
);
1967 prod
= rxr
->rx_agg_prod
;
1968 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
1969 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1970 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
1971 ring_nr
, i
, bp
->rx_ring_size
);
1974 prod
= NEXT_RX_AGG(prod
);
1976 rxr
->rx_agg_prod
= prod
;
1978 if (bp
->flags
& BNXT_FLAG_TPA
) {
1983 for (i
= 0; i
< MAX_TPA
; i
++) {
1984 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
1989 rxr
->rx_tpa
[i
].data
= data
;
1990 rxr
->rx_tpa
[i
].mapping
= mapping
;
1993 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2001 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2005 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2006 rc
= bnxt_init_one_rx_ring(bp
, i
);
2014 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2018 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2021 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2022 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2023 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2025 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2031 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2033 kfree(bp
->grp_info
);
2034 bp
->grp_info
= NULL
;
2037 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2042 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2043 sizeof(struct bnxt_ring_grp_info
),
2048 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2050 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2051 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2052 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2053 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2054 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2059 static void bnxt_free_vnics(struct bnxt
*bp
)
2061 kfree(bp
->vnic_info
);
2062 bp
->vnic_info
= NULL
;
2066 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2070 #ifdef CONFIG_RFS_ACCEL
2071 if (bp
->flags
& BNXT_FLAG_RFS
)
2072 num_vnics
+= bp
->rx_nr_rings
;
2075 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2080 bp
->nr_vnics
= num_vnics
;
2084 static void bnxt_init_vnics(struct bnxt
*bp
)
2088 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2089 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2091 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2092 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2093 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2095 if (bp
->vnic_info
[i
].rss_hash_key
) {
2097 prandom_bytes(vnic
->rss_hash_key
,
2100 memcpy(vnic
->rss_hash_key
,
2101 bp
->vnic_info
[0].rss_hash_key
,
2107 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2111 pages
= ring_size
/ desc_per_pg
;
2118 while (pages
& (pages
- 1))
2124 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2126 bp
->flags
&= ~BNXT_FLAG_TPA
;
2127 if (bp
->dev
->features
& NETIF_F_LRO
)
2128 bp
->flags
|= BNXT_FLAG_LRO
;
2129 if ((bp
->dev
->features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
2130 bp
->flags
|= BNXT_FLAG_GRO
;
2133 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2136 void bnxt_set_ring_params(struct bnxt
*bp
)
2138 u32 ring_size
, rx_size
, rx_space
;
2139 u32 agg_factor
= 0, agg_ring_size
= 0;
2141 /* 8 for CRC and VLAN */
2142 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2144 rx_space
= rx_size
+ NET_SKB_PAD
+
2145 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2147 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2148 ring_size
= bp
->rx_ring_size
;
2149 bp
->rx_agg_ring_size
= 0;
2150 bp
->rx_agg_nr_pages
= 0;
2152 if (bp
->flags
& BNXT_FLAG_TPA
)
2155 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2156 if (rx_space
> PAGE_SIZE
) {
2159 bp
->flags
|= BNXT_FLAG_JUMBO
;
2160 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2161 if (jumbo_factor
> agg_factor
)
2162 agg_factor
= jumbo_factor
;
2164 agg_ring_size
= ring_size
* agg_factor
;
2166 if (agg_ring_size
) {
2167 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2169 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2170 u32 tmp
= agg_ring_size
;
2172 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2173 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2174 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2175 tmp
, agg_ring_size
);
2177 bp
->rx_agg_ring_size
= agg_ring_size
;
2178 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2179 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2180 rx_space
= rx_size
+ NET_SKB_PAD
+
2181 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2184 bp
->rx_buf_use_size
= rx_size
;
2185 bp
->rx_buf_size
= rx_space
;
2187 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2188 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2190 ring_size
= bp
->tx_ring_size
;
2191 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2192 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2194 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2195 bp
->cp_ring_size
= ring_size
;
2197 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2198 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2199 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2200 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2201 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2202 ring_size
, bp
->cp_ring_size
);
2204 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2205 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2208 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2211 struct bnxt_vnic_info
*vnic
;
2212 struct pci_dev
*pdev
= bp
->pdev
;
2217 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2218 vnic
= &bp
->vnic_info
[i
];
2220 kfree(vnic
->fw_grp_ids
);
2221 vnic
->fw_grp_ids
= NULL
;
2223 kfree(vnic
->uc_list
);
2224 vnic
->uc_list
= NULL
;
2226 if (vnic
->mc_list
) {
2227 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2228 vnic
->mc_list
, vnic
->mc_list_mapping
);
2229 vnic
->mc_list
= NULL
;
2232 if (vnic
->rss_table
) {
2233 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2235 vnic
->rss_table_dma_addr
);
2236 vnic
->rss_table
= NULL
;
2239 vnic
->rss_hash_key
= NULL
;
2244 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2246 int i
, rc
= 0, size
;
2247 struct bnxt_vnic_info
*vnic
;
2248 struct pci_dev
*pdev
= bp
->pdev
;
2251 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2252 vnic
= &bp
->vnic_info
[i
];
2254 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2255 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2258 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2259 if (!vnic
->uc_list
) {
2266 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2267 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2269 dma_alloc_coherent(&pdev
->dev
,
2271 &vnic
->mc_list_mapping
,
2273 if (!vnic
->mc_list
) {
2279 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2280 max_rings
= bp
->rx_nr_rings
;
2284 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2285 if (!vnic
->fw_grp_ids
) {
2290 /* Allocate rss table and hash key */
2291 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2292 &vnic
->rss_table_dma_addr
,
2294 if (!vnic
->rss_table
) {
2299 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2301 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2302 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2310 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2312 struct pci_dev
*pdev
= bp
->pdev
;
2314 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2315 bp
->hwrm_cmd_resp_dma_addr
);
2317 bp
->hwrm_cmd_resp_addr
= NULL
;
2318 if (bp
->hwrm_dbg_resp_addr
) {
2319 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2320 bp
->hwrm_dbg_resp_addr
,
2321 bp
->hwrm_dbg_resp_dma_addr
);
2323 bp
->hwrm_dbg_resp_addr
= NULL
;
2327 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2329 struct pci_dev
*pdev
= bp
->pdev
;
2331 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2332 &bp
->hwrm_cmd_resp_dma_addr
,
2334 if (!bp
->hwrm_cmd_resp_addr
)
2336 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2337 HWRM_DBG_REG_BUF_SIZE
,
2338 &bp
->hwrm_dbg_resp_dma_addr
,
2340 if (!bp
->hwrm_dbg_resp_addr
)
2341 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2346 static void bnxt_free_stats(struct bnxt
*bp
)
2349 struct pci_dev
*pdev
= bp
->pdev
;
2354 size
= sizeof(struct ctx_hw_stats
);
2356 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2357 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2358 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2360 if (cpr
->hw_stats
) {
2361 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2363 cpr
->hw_stats
= NULL
;
2368 static int bnxt_alloc_stats(struct bnxt
*bp
)
2371 struct pci_dev
*pdev
= bp
->pdev
;
2373 size
= sizeof(struct ctx_hw_stats
);
2375 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2376 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2377 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2379 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2385 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2390 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2397 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2398 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2399 struct bnxt_cp_ring_info
*cpr
;
2400 struct bnxt_rx_ring_info
*rxr
;
2401 struct bnxt_tx_ring_info
*txr
;
2406 cpr
= &bnapi
->cp_ring
;
2407 cpr
->cp_raw_cons
= 0;
2409 txr
= bnapi
->tx_ring
;
2415 rxr
= bnapi
->rx_ring
;
2418 rxr
->rx_agg_prod
= 0;
2419 rxr
->rx_sw_agg_prod
= 0;
2424 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2426 #ifdef CONFIG_RFS_ACCEL
2429 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2430 * safe to delete the hash table.
2432 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2433 struct hlist_head
*head
;
2434 struct hlist_node
*tmp
;
2435 struct bnxt_ntuple_filter
*fltr
;
2437 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2438 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2439 hlist_del(&fltr
->hash
);
2444 kfree(bp
->ntp_fltr_bmap
);
2445 bp
->ntp_fltr_bmap
= NULL
;
2447 bp
->ntp_fltr_count
= 0;
2451 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2453 #ifdef CONFIG_RFS_ACCEL
2456 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2459 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2460 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2462 bp
->ntp_fltr_count
= 0;
2463 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2466 if (!bp
->ntp_fltr_bmap
)
2475 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2477 bnxt_free_vnic_attributes(bp
);
2478 bnxt_free_tx_rings(bp
);
2479 bnxt_free_rx_rings(bp
);
2480 bnxt_free_cp_rings(bp
);
2481 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2483 bnxt_free_stats(bp
);
2484 bnxt_free_ring_grps(bp
);
2485 bnxt_free_vnics(bp
);
2493 bnxt_clear_ring_indices(bp
);
2497 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2499 int i
, j
, rc
, size
, arr_size
;
2503 /* Allocate bnapi mem pointer array and mem block for
2506 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2508 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2509 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2515 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2516 bp
->bnapi
[i
] = bnapi
;
2517 bp
->bnapi
[i
]->index
= i
;
2518 bp
->bnapi
[i
]->bp
= bp
;
2521 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2522 sizeof(struct bnxt_rx_ring_info
),
2527 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2528 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2529 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2532 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2533 sizeof(struct bnxt_tx_ring_info
),
2538 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2541 j
= bp
->rx_nr_rings
;
2543 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2544 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2545 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2548 rc
= bnxt_alloc_stats(bp
);
2552 rc
= bnxt_alloc_ntp_fltrs(bp
);
2556 rc
= bnxt_alloc_vnics(bp
);
2561 bnxt_init_ring_struct(bp
);
2563 rc
= bnxt_alloc_rx_rings(bp
);
2567 rc
= bnxt_alloc_tx_rings(bp
);
2571 rc
= bnxt_alloc_cp_rings(bp
);
2575 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2576 BNXT_VNIC_UCAST_FLAG
;
2577 rc
= bnxt_alloc_vnic_attributes(bp
);
2583 bnxt_free_mem(bp
, true);
2587 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2588 u16 cmpl_ring
, u16 target_id
)
2590 struct hwrm_cmd_req_hdr
*req
= request
;
2592 req
->cmpl_ring_req_type
=
2593 cpu_to_le32(req_type
| (cmpl_ring
<< HWRM_CMPL_RING_SFT
));
2594 req
->target_id_seq_id
= cpu_to_le32(target_id
<< HWRM_TARGET_FID_SFT
);
2595 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2598 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2600 int i
, intr_process
, rc
;
2601 struct hwrm_cmd_req_hdr
*req
= msg
;
2603 __le32
*resp_len
, *valid
;
2604 u16 cp_ring_id
, len
= 0;
2605 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2607 req
->target_id_seq_id
|= cpu_to_le32(bp
->hwrm_cmd_seq
++);
2608 memset(resp
, 0, PAGE_SIZE
);
2609 cp_ring_id
= (le32_to_cpu(req
->cmpl_ring_req_type
) &
2610 HWRM_CMPL_RING_MASK
) >>
2612 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2614 /* Write request msg to hwrm channel */
2615 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2617 for (i
= msg_len
; i
< HWRM_MAX_REQ_LEN
; i
+= 4)
2618 writel(0, bp
->bar0
+ i
);
2620 /* currently supports only one outstanding message */
2622 bp
->hwrm_intr_seq_id
= le32_to_cpu(req
->target_id_seq_id
) &
2625 /* Ring channel doorbell */
2626 writel(1, bp
->bar0
+ 0x100);
2630 /* Wait until hwrm response cmpl interrupt is processed */
2631 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2633 usleep_range(600, 800);
2636 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2637 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2638 req
->cmpl_ring_req_type
);
2642 /* Check if response len is updated */
2643 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2644 for (i
= 0; i
< timeout
; i
++) {
2645 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2649 usleep_range(600, 800);
2653 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2654 timeout
, req
->cmpl_ring_req_type
,
2655 req
->target_id_seq_id
, *resp_len
);
2659 /* Last word of resp contains valid bit */
2660 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2661 for (i
= 0; i
< timeout
; i
++) {
2662 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2664 usleep_range(600, 800);
2668 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2669 timeout
, req
->cmpl_ring_req_type
,
2670 req
->target_id_seq_id
, len
, *valid
);
2675 rc
= le16_to_cpu(resp
->error_code
);
2677 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2678 le16_to_cpu(resp
->req_type
),
2679 le16_to_cpu(resp
->seq_id
), rc
);
2685 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2689 mutex_lock(&bp
->hwrm_cmd_lock
);
2690 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2691 mutex_unlock(&bp
->hwrm_cmd_lock
);
2695 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
2697 struct hwrm_func_drv_rgtr_input req
= {0};
2700 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
2703 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
2704 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
2705 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
2707 /* TODO: current async event fwd bits are not defined and the firmware
2708 * only checks if it is non-zero to enable async event forwarding
2710 req
.async_event_fwd
[0] |= cpu_to_le32(1);
2711 req
.os_type
= cpu_to_le16(1);
2712 req
.ver_maj
= DRV_VER_MAJ
;
2713 req
.ver_min
= DRV_VER_MIN
;
2714 req
.ver_upd
= DRV_VER_UPD
;
2717 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
2718 u32
*data
= (u32
*)vf_req_snif_bmap
;
2720 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
2721 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
2722 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
2724 for (i
= 0; i
< 8; i
++)
2725 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
2728 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
2731 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2734 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
2736 struct hwrm_func_drv_unrgtr_input req
= {0};
2738 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
2739 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2742 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
2745 struct hwrm_tunnel_dst_port_free_input req
= {0};
2747 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
2748 req
.tunnel_type
= tunnel_type
;
2750 switch (tunnel_type
) {
2751 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
2752 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
2754 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
2755 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
2761 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2763 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2768 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
2772 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
2773 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2775 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
2777 req
.tunnel_type
= tunnel_type
;
2778 req
.tunnel_dst_port_val
= port
;
2780 mutex_lock(&bp
->hwrm_cmd_lock
);
2781 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2783 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2788 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
2789 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2791 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
2792 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2794 mutex_unlock(&bp
->hwrm_cmd_lock
);
2798 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
2800 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
2801 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2803 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
2804 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
2806 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
2807 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
2808 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
2809 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2812 #ifdef CONFIG_RFS_ACCEL
2813 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
2814 struct bnxt_ntuple_filter
*fltr
)
2816 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
2818 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
2819 req
.ntuple_filter_id
= fltr
->filter_id
;
2820 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2823 #define BNXT_NTP_FLTR_FLAGS \
2824 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2825 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2826 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2827 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2828 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2829 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2830 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2831 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2832 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2833 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2834 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2835 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2836 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2837 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2839 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
2840 struct bnxt_ntuple_filter
*fltr
)
2843 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
2844 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
2845 bp
->hwrm_cmd_resp_addr
;
2846 struct flow_keys
*keys
= &fltr
->fkeys
;
2847 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
2849 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
2850 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
2852 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
2854 req
.ethertype
= htons(ETH_P_IP
);
2855 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
2856 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
2857 req
.ip_protocol
= keys
->basic
.ip_proto
;
2859 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
2860 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2861 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
2862 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2864 req
.src_port
= keys
->ports
.src
;
2865 req
.src_port_mask
= cpu_to_be16(0xffff);
2866 req
.dst_port
= keys
->ports
.dst
;
2867 req
.dst_port_mask
= cpu_to_be16(0xffff);
2869 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2870 mutex_lock(&bp
->hwrm_cmd_lock
);
2871 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2873 fltr
->filter_id
= resp
->ntuple_filter_id
;
2874 mutex_unlock(&bp
->hwrm_cmd_lock
);
2879 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
2883 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
2884 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2886 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
2887 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
2888 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
2889 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
2891 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
2892 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
2893 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
2894 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
2895 req
.l2_addr_mask
[0] = 0xff;
2896 req
.l2_addr_mask
[1] = 0xff;
2897 req
.l2_addr_mask
[2] = 0xff;
2898 req
.l2_addr_mask
[3] = 0xff;
2899 req
.l2_addr_mask
[4] = 0xff;
2900 req
.l2_addr_mask
[5] = 0xff;
2902 mutex_lock(&bp
->hwrm_cmd_lock
);
2903 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2905 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
2907 mutex_unlock(&bp
->hwrm_cmd_lock
);
2911 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
2913 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
2916 /* Any associated ntuple filters will also be cleared by firmware. */
2917 mutex_lock(&bp
->hwrm_cmd_lock
);
2918 for (i
= 0; i
< num_of_vnics
; i
++) {
2919 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2921 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
2922 struct hwrm_cfa_l2_filter_free_input req
= {0};
2924 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
2925 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
2927 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
2929 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
2932 vnic
->uc_filter_count
= 0;
2934 mutex_unlock(&bp
->hwrm_cmd_lock
);
2939 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
2941 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2942 struct hwrm_vnic_tpa_cfg_input req
= {0};
2944 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
2947 u16 mss
= bp
->dev
->mtu
- 40;
2948 u32 nsegs
, n
, segs
= 0, flags
;
2950 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
2951 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
2952 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
2953 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
2954 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
2955 if (tpa_flags
& BNXT_FLAG_GRO
)
2956 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
2958 req
.flags
= cpu_to_le32(flags
);
2961 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
2962 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
2963 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
2965 /* Number of segs are log2 units, and first packet is not
2966 * included as part of this units.
2968 if (mss
<= PAGE_SIZE
) {
2969 n
= PAGE_SIZE
/ mss
;
2970 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
2972 n
= mss
/ PAGE_SIZE
;
2973 if (mss
& (PAGE_SIZE
- 1))
2975 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
2978 segs
= ilog2(nsegs
);
2979 req
.max_agg_segs
= cpu_to_le16(segs
);
2980 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
2982 req
.min_agg_len
= cpu_to_le32(512);
2984 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2986 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2989 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
2991 u32 i
, j
, max_rings
;
2992 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2993 struct hwrm_vnic_rss_cfg_input req
= {0};
2995 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
2998 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3000 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
3001 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
3002 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
3003 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
3005 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
3007 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3008 max_rings
= bp
->rx_nr_rings
;
3012 /* Fill the RSS indirection table with ring group ids */
3013 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3016 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3019 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3020 req
.hash_key_tbl_addr
=
3021 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3023 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3024 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3027 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3029 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3030 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3032 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3033 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3034 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3035 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3037 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3038 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3039 /* thresholds not implemented in firmware yet */
3040 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3041 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3042 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3043 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3046 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3048 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3050 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3051 req
.rss_cos_lb_ctx_id
=
3052 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3054 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3055 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3058 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3062 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3063 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3065 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3066 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3068 bp
->rsscos_nr_ctxs
= 0;
3071 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3074 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3075 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3076 bp
->hwrm_cmd_resp_addr
;
3078 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3081 mutex_lock(&bp
->hwrm_cmd_lock
);
3082 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3084 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3085 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3086 mutex_unlock(&bp
->hwrm_cmd_lock
);
3091 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3093 unsigned int ring
= 0, grp_idx
;
3094 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3095 struct hwrm_vnic_cfg_input req
= {0};
3097 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3098 /* Only RSS support for now TBD: COS & LB */
3099 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3100 VNIC_CFG_REQ_ENABLES_RSS_RULE
);
3101 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3102 req
.cos_rule
= cpu_to_le16(0xffff);
3103 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3105 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3108 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3109 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3110 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3112 req
.lb_rule
= cpu_to_le16(0xffff);
3113 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3116 if (bp
->flags
& BNXT_FLAG_STRIP_VLAN
)
3117 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3119 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3122 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3126 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3127 struct hwrm_vnic_free_input req
= {0};
3129 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3131 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3133 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3136 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3141 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3145 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3146 bnxt_hwrm_vnic_free_one(bp
, i
);
3149 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3150 unsigned int start_rx_ring_idx
,
3151 unsigned int nr_rings
)
3154 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3155 struct hwrm_vnic_alloc_input req
= {0};
3156 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3158 /* map ring groups to this vnic */
3159 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3160 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3161 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3162 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3166 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3167 bp
->grp_info
[grp_idx
].fw_grp_id
;
3170 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3172 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3174 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3176 mutex_lock(&bp
->hwrm_cmd_lock
);
3177 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3179 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3180 mutex_unlock(&bp
->hwrm_cmd_lock
);
3184 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3189 mutex_lock(&bp
->hwrm_cmd_lock
);
3190 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3191 struct hwrm_ring_grp_alloc_input req
= {0};
3192 struct hwrm_ring_grp_alloc_output
*resp
=
3193 bp
->hwrm_cmd_resp_addr
;
3194 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3196 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3198 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3199 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3200 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3201 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3203 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3208 bp
->grp_info
[grp_idx
].fw_grp_id
=
3209 le32_to_cpu(resp
->ring_group_id
);
3211 mutex_unlock(&bp
->hwrm_cmd_lock
);
3215 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3219 struct hwrm_ring_grp_free_input req
= {0};
3224 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3226 mutex_lock(&bp
->hwrm_cmd_lock
);
3227 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3228 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3231 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3233 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3237 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3239 mutex_unlock(&bp
->hwrm_cmd_lock
);
3243 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3244 struct bnxt_ring_struct
*ring
,
3245 u32 ring_type
, u32 map_index
,
3248 int rc
= 0, err
= 0;
3249 struct hwrm_ring_alloc_input req
= {0};
3250 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3253 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3256 if (ring
->nr_pages
> 1) {
3257 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3258 /* Page size is in log2 units */
3259 req
.page_size
= BNXT_PAGE_SHIFT
;
3260 req
.page_tbl_depth
= 1;
3262 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3265 /* Association of ring index with doorbell index and MSIX number */
3266 req
.logical_id
= cpu_to_le16(map_index
);
3268 switch (ring_type
) {
3269 case HWRM_RING_ALLOC_TX
:
3270 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3271 /* Association of transmit ring with completion ring */
3273 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3274 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3275 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3276 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3278 case HWRM_RING_ALLOC_RX
:
3279 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3280 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3282 case HWRM_RING_ALLOC_AGG
:
3283 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3284 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3286 case HWRM_RING_ALLOC_CMPL
:
3287 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3288 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3289 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3290 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3293 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3298 mutex_lock(&bp
->hwrm_cmd_lock
);
3299 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3300 err
= le16_to_cpu(resp
->error_code
);
3301 ring_id
= le16_to_cpu(resp
->ring_id
);
3302 mutex_unlock(&bp
->hwrm_cmd_lock
);
3305 switch (ring_type
) {
3306 case RING_FREE_REQ_RING_TYPE_CMPL
:
3307 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3311 case RING_FREE_REQ_RING_TYPE_RX
:
3312 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3316 case RING_FREE_REQ_RING_TYPE_TX
:
3317 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3322 netdev_err(bp
->dev
, "Invalid ring\n");
3326 ring
->fw_ring_id
= ring_id
;
3330 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3334 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3335 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3336 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3337 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3339 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3340 INVALID_STATS_CTX_ID
);
3343 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3344 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3345 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3348 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3349 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3350 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3351 u32 map_idx
= txr
->bnapi
->index
;
3352 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3354 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3355 map_idx
, fw_stats_ctx
);
3358 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3361 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3362 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3363 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3364 u32 map_idx
= rxr
->bnapi
->index
;
3366 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3367 map_idx
, INVALID_STATS_CTX_ID
);
3370 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3371 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3372 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3375 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3376 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3377 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3378 struct bnxt_ring_struct
*ring
=
3379 &rxr
->rx_agg_ring_struct
;
3380 u32 grp_idx
= rxr
->bnapi
->index
;
3381 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3383 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3384 HWRM_RING_ALLOC_AGG
,
3386 INVALID_STATS_CTX_ID
);
3390 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3391 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3392 rxr
->rx_agg_doorbell
);
3393 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3400 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3401 struct bnxt_ring_struct
*ring
,
3402 u32 ring_type
, int cmpl_ring_id
)
3405 struct hwrm_ring_free_input req
= {0};
3406 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3409 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, -1, -1);
3410 req
.ring_type
= ring_type
;
3411 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3413 mutex_lock(&bp
->hwrm_cmd_lock
);
3414 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3415 error_code
= le16_to_cpu(resp
->error_code
);
3416 mutex_unlock(&bp
->hwrm_cmd_lock
);
3418 if (rc
|| error_code
) {
3419 switch (ring_type
) {
3420 case RING_FREE_REQ_RING_TYPE_CMPL
:
3421 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3424 case RING_FREE_REQ_RING_TYPE_RX
:
3425 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3428 case RING_FREE_REQ_RING_TYPE_TX
:
3429 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3433 netdev_err(bp
->dev
, "Invalid ring\n");
3440 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3447 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3448 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3449 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3450 u32 grp_idx
= txr
->bnapi
->index
;
3451 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3453 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3454 hwrm_ring_free_send_msg(bp
, ring
,
3455 RING_FREE_REQ_RING_TYPE_TX
,
3456 close_path
? cmpl_ring_id
:
3457 INVALID_HW_RING_ID
);
3458 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3462 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3463 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3464 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3465 u32 grp_idx
= rxr
->bnapi
->index
;
3466 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3468 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3469 hwrm_ring_free_send_msg(bp
, ring
,
3470 RING_FREE_REQ_RING_TYPE_RX
,
3471 close_path
? cmpl_ring_id
:
3472 INVALID_HW_RING_ID
);
3473 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3474 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
3479 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3480 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3481 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
3482 u32 grp_idx
= rxr
->bnapi
->index
;
3483 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3485 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3486 hwrm_ring_free_send_msg(bp
, ring
,
3487 RING_FREE_REQ_RING_TYPE_RX
,
3488 close_path
? cmpl_ring_id
:
3489 INVALID_HW_RING_ID
);
3490 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3491 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
3496 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3497 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3498 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3499 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3501 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3502 hwrm_ring_free_send_msg(bp
, ring
,
3503 RING_FREE_REQ_RING_TYPE_CMPL
,
3504 INVALID_HW_RING_ID
);
3505 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3506 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
3511 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3514 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req
= {0};
3515 u16 max_buf
, max_buf_irq
;
3516 u16 buf_tmr
, buf_tmr_irq
;
3519 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
,
3522 /* Each rx completion (2 records) should be DMAed immediately */
3523 max_buf
= min_t(u16
, bp
->coal_bufs
/ 4, 2);
3524 /* max_buf must not be zero */
3525 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3526 max_buf_irq
= clamp_t(u16
, bp
->coal_bufs_irq
, 1, 63);
3527 buf_tmr
= max_t(u16
, bp
->coal_ticks
/ 4, 1);
3528 buf_tmr_irq
= max_t(u16
, bp
->coal_ticks_irq
, 1);
3530 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3532 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3533 * if coal_ticks is less than 25 us.
3535 if (BNXT_COAL_TIMER_TO_USEC(bp
->coal_ticks
) < 25)
3536 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3538 req
.flags
= cpu_to_le16(flags
);
3539 req
.num_cmpl_dma_aggr
= cpu_to_le16(max_buf
);
3540 req
.num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_buf_irq
);
3541 req
.cmpl_aggr_dma_tmr
= cpu_to_le16(buf_tmr
);
3542 req
.cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmr_irq
);
3543 req
.int_lat_tmr_min
= cpu_to_le16(buf_tmr
);
3544 req
.int_lat_tmr_max
= cpu_to_le16(bp
->coal_ticks
);
3545 req
.num_cmpl_aggr_int
= cpu_to_le16(bp
->coal_bufs
);
3547 mutex_lock(&bp
->hwrm_cmd_lock
);
3548 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3549 req
.ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3551 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3556 mutex_unlock(&bp
->hwrm_cmd_lock
);
3560 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3563 struct hwrm_stat_ctx_free_input req
= {0};
3568 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3570 mutex_lock(&bp
->hwrm_cmd_lock
);
3571 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3572 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3573 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3575 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3576 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3578 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3583 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3586 mutex_unlock(&bp
->hwrm_cmd_lock
);
3590 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3593 struct hwrm_stat_ctx_alloc_input req
= {0};
3594 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3596 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3598 req
.update_period_ms
= cpu_to_le32(1000);
3600 mutex_lock(&bp
->hwrm_cmd_lock
);
3601 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3602 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3603 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3605 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3607 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3612 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3614 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3616 mutex_unlock(&bp
->hwrm_cmd_lock
);
3620 int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
3623 struct hwrm_func_qcaps_input req
= {0};
3624 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3626 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
3627 req
.fid
= cpu_to_le16(0xffff);
3629 mutex_lock(&bp
->hwrm_cmd_lock
);
3630 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3632 goto hwrm_func_qcaps_exit
;
3635 struct bnxt_pf_info
*pf
= &bp
->pf
;
3637 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
3638 pf
->port_id
= le16_to_cpu(resp
->port_id
);
3639 memcpy(pf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3640 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
3641 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3642 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3643 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3644 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3645 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3646 if (!pf
->max_hw_ring_grps
)
3647 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
3648 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3649 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3650 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3651 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
3652 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
3653 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
3654 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
3655 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
3656 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
3657 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
3658 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
3660 #ifdef CONFIG_BNXT_SRIOV
3661 struct bnxt_vf_info
*vf
= &bp
->vf
;
3663 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
3664 memcpy(vf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3665 if (is_valid_ether_addr(vf
->mac_addr
))
3666 /* overwrite netdev dev_adr with admin VF MAC */
3667 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
3669 random_ether_addr(bp
->dev
->dev_addr
);
3671 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3672 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3673 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3674 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3675 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3676 if (!vf
->max_hw_ring_grps
)
3677 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
3678 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3679 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3680 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3684 bp
->tx_push_thresh
= 0;
3686 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
3687 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
3689 hwrm_func_qcaps_exit
:
3690 mutex_unlock(&bp
->hwrm_cmd_lock
);
3694 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
3696 struct hwrm_func_reset_input req
= {0};
3698 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
3701 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
3704 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
3707 struct hwrm_queue_qportcfg_input req
= {0};
3708 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3711 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
3713 mutex_lock(&bp
->hwrm_cmd_lock
);
3714 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3718 if (!resp
->max_configurable_queues
) {
3722 bp
->max_tc
= resp
->max_configurable_queues
;
3723 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
3724 bp
->max_tc
= BNXT_MAX_QUEUE
;
3726 qptr
= &resp
->queue_id0
;
3727 for (i
= 0; i
< bp
->max_tc
; i
++) {
3728 bp
->q_info
[i
].queue_id
= *qptr
++;
3729 bp
->q_info
[i
].queue_profile
= *qptr
++;
3733 mutex_unlock(&bp
->hwrm_cmd_lock
);
3737 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
3740 struct hwrm_ver_get_input req
= {0};
3741 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3743 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
3744 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
3745 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
3746 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
3747 mutex_lock(&bp
->hwrm_cmd_lock
);
3748 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3750 goto hwrm_ver_get_exit
;
3752 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
3754 if (resp
->hwrm_intf_maj
< 1) {
3755 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3756 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
3757 resp
->hwrm_intf_upd
);
3758 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3760 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "bc %d.%d.%d rm %d.%d.%d",
3761 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
3762 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
3765 mutex_unlock(&bp
->hwrm_cmd_lock
);
3769 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
3771 if (bp
->vxlan_port_cnt
) {
3772 bnxt_hwrm_tunnel_dst_port_free(
3773 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
3775 bp
->vxlan_port_cnt
= 0;
3776 if (bp
->nge_port_cnt
) {
3777 bnxt_hwrm_tunnel_dst_port_free(
3778 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
3780 bp
->nge_port_cnt
= 0;
3783 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
3789 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
3790 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3791 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
3793 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3801 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
3805 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3806 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
3809 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
3812 if (bp
->vnic_info
) {
3813 bnxt_hwrm_clear_vnic_filter(bp
);
3814 /* clear all RSS setting before free vnic ctx */
3815 bnxt_hwrm_clear_vnic_rss(bp
);
3816 bnxt_hwrm_vnic_ctx_free(bp
);
3817 /* before free the vnic, undo the vnic tpa settings */
3818 if (bp
->flags
& BNXT_FLAG_TPA
)
3819 bnxt_set_tpa(bp
, false);
3820 bnxt_hwrm_vnic_free(bp
);
3822 bnxt_hwrm_ring_free(bp
, close_path
);
3823 bnxt_hwrm_ring_grp_free(bp
);
3825 bnxt_hwrm_stat_ctx_free(bp
);
3826 bnxt_hwrm_free_tunnel_ports(bp
);
3830 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
3834 /* allocate context for vnic */
3835 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
3837 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3839 goto vnic_setup_err
;
3841 bp
->rsscos_nr_ctxs
++;
3843 /* configure default vnic, ring grp */
3844 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
3846 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
3848 goto vnic_setup_err
;
3851 /* Enable RSS hashing on vnic */
3852 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
3854 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
3856 goto vnic_setup_err
;
3859 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3860 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
3862 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
3871 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
3873 #ifdef CONFIG_RFS_ACCEL
3876 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3877 u16 vnic_id
= i
+ 1;
3880 if (vnic_id
>= bp
->nr_vnics
)
3883 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
3884 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
3886 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3890 rc
= bnxt_setup_vnic(bp
, vnic_id
);
3900 static int bnxt_cfg_rx_mode(struct bnxt
*);
3902 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
3907 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
3909 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
3915 rc
= bnxt_hwrm_ring_alloc(bp
);
3917 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
3921 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
3923 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
3927 /* default vnic 0 */
3928 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
3930 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
3934 rc
= bnxt_setup_vnic(bp
, 0);
3938 if (bp
->flags
& BNXT_FLAG_RFS
) {
3939 rc
= bnxt_alloc_rfs_vnics(bp
);
3944 if (bp
->flags
& BNXT_FLAG_TPA
) {
3945 rc
= bnxt_set_tpa(bp
, true);
3951 bnxt_update_vf_mac(bp
);
3953 /* Filter for default vnic 0 */
3954 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
3956 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
3959 bp
->vnic_info
[0].uc_filter_count
= 1;
3961 bp
->vnic_info
[0].rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
3963 if ((bp
->dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
3964 bp
->vnic_info
[0].rx_mask
|=
3965 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
3967 rc
= bnxt_cfg_rx_mode(bp
);
3971 rc
= bnxt_hwrm_set_coal(bp
);
3973 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
3979 bnxt_hwrm_resource_free(bp
, 0, true);
3984 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
3986 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
3990 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
3992 bnxt_init_rx_rings(bp
);
3993 bnxt_init_tx_rings(bp
);
3994 bnxt_init_ring_grps(bp
, irq_re_init
);
3995 bnxt_init_vnics(bp
);
3997 return bnxt_init_chip(bp
, irq_re_init
);
4000 static void bnxt_disable_int(struct bnxt
*bp
)
4007 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4008 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4009 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4011 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4015 static void bnxt_enable_int(struct bnxt
*bp
)
4019 atomic_set(&bp
->intr_sem
, 0);
4020 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4021 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4022 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4024 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4028 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4031 struct net_device
*dev
= bp
->dev
;
4033 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4037 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4041 #ifdef CONFIG_RFS_ACCEL
4042 if (bp
->flags
& BNXT_FLAG_RFS
)
4043 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4049 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4052 int _rx
= *rx
, _tx
= *tx
;
4055 *rx
= min_t(int, _rx
, max
);
4056 *tx
= min_t(int, _tx
, max
);
4061 while (_rx
+ _tx
> max
) {
4062 if (_rx
> _tx
&& _rx
> 1)
4073 static int bnxt_setup_msix(struct bnxt
*bp
)
4075 struct msix_entry
*msix_ent
;
4076 struct net_device
*dev
= bp
->dev
;
4077 int i
, total_vecs
, rc
= 0, min
= 1;
4078 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4080 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4081 total_vecs
= bp
->cp_nr_rings
;
4083 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4087 for (i
= 0; i
< total_vecs
; i
++) {
4088 msix_ent
[i
].entry
= i
;
4089 msix_ent
[i
].vector
= 0;
4092 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
4095 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
4096 if (total_vecs
< 0) {
4098 goto msix_setup_exit
;
4101 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4105 /* Trim rings based upon num of vectors allocated */
4106 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
4107 total_vecs
, min
== 1);
4109 goto msix_setup_exit
;
4111 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4112 tcs
= netdev_get_num_tc(dev
);
4114 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4115 if (bp
->tx_nr_rings_per_tc
== 0) {
4116 netdev_reset_tc(dev
);
4117 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4121 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4122 for (i
= 0; i
< tcs
; i
++) {
4123 count
= bp
->tx_nr_rings_per_tc
;
4125 netdev_set_tc_queue(dev
, i
, count
, off
);
4129 bp
->cp_nr_rings
= total_vecs
;
4131 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4134 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4135 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4137 else if (i
< bp
->rx_nr_rings
)
4142 snprintf(bp
->irq_tbl
[i
].name
, len
,
4143 "%s-%s-%d", dev
->name
, attr
, i
);
4144 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4146 rc
= bnxt_set_real_num_queues(bp
);
4148 goto msix_setup_exit
;
4151 goto msix_setup_exit
;
4153 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4158 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4159 pci_disable_msix(bp
->pdev
);
4164 static int bnxt_setup_inta(struct bnxt
*bp
)
4167 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4169 if (netdev_get_num_tc(bp
->dev
))
4170 netdev_reset_tc(bp
->dev
);
4172 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4177 bp
->rx_nr_rings
= 1;
4178 bp
->tx_nr_rings
= 1;
4179 bp
->cp_nr_rings
= 1;
4180 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4181 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
4182 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4183 snprintf(bp
->irq_tbl
[0].name
, len
,
4184 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4185 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4186 rc
= bnxt_set_real_num_queues(bp
);
4190 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4194 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4195 rc
= bnxt_setup_msix(bp
);
4197 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4198 /* fallback to INTA */
4199 rc
= bnxt_setup_inta(bp
);
4204 static void bnxt_free_irq(struct bnxt
*bp
)
4206 struct bnxt_irq
*irq
;
4209 #ifdef CONFIG_RFS_ACCEL
4210 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4211 bp
->dev
->rx_cpu_rmap
= NULL
;
4216 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4217 irq
= &bp
->irq_tbl
[i
];
4219 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4222 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4223 pci_disable_msix(bp
->pdev
);
4228 static int bnxt_request_irq(struct bnxt
*bp
)
4231 unsigned long flags
= 0;
4232 #ifdef CONFIG_RFS_ACCEL
4233 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4236 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4237 flags
= IRQF_SHARED
;
4239 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
4240 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4241 #ifdef CONFIG_RFS_ACCEL
4242 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
4243 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4245 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4250 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4260 static void bnxt_del_napi(struct bnxt
*bp
)
4267 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4268 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4270 napi_hash_del(&bnapi
->napi
);
4271 netif_napi_del(&bnapi
->napi
);
4275 static void bnxt_init_napi(struct bnxt
*bp
)
4278 struct bnxt_napi
*bnapi
;
4280 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4281 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4282 bnapi
= bp
->bnapi
[i
];
4283 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4287 bnapi
= bp
->bnapi
[0];
4288 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4292 static void bnxt_disable_napi(struct bnxt
*bp
)
4299 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4300 napi_disable(&bp
->bnapi
[i
]->napi
);
4301 bnxt_disable_poll(bp
->bnapi
[i
]);
4305 static void bnxt_enable_napi(struct bnxt
*bp
)
4309 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4310 bnxt_enable_poll(bp
->bnapi
[i
]);
4311 napi_enable(&bp
->bnapi
[i
]->napi
);
4315 static void bnxt_tx_disable(struct bnxt
*bp
)
4318 struct bnxt_tx_ring_info
*txr
;
4319 struct netdev_queue
*txq
;
4322 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4323 txr
= &bp
->tx_ring
[i
];
4324 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4325 __netif_tx_lock(txq
, smp_processor_id());
4326 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4327 __netif_tx_unlock(txq
);
4330 /* Stop all TX queues */
4331 netif_tx_disable(bp
->dev
);
4332 netif_carrier_off(bp
->dev
);
4335 static void bnxt_tx_enable(struct bnxt
*bp
)
4338 struct bnxt_tx_ring_info
*txr
;
4339 struct netdev_queue
*txq
;
4341 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4342 txr
= &bp
->tx_ring
[i
];
4343 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4346 netif_tx_wake_all_queues(bp
->dev
);
4347 if (bp
->link_info
.link_up
)
4348 netif_carrier_on(bp
->dev
);
4351 static void bnxt_report_link(struct bnxt
*bp
)
4353 if (bp
->link_info
.link_up
) {
4355 const char *flow_ctrl
;
4358 netif_carrier_on(bp
->dev
);
4359 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4363 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4364 flow_ctrl
= "ON - receive & transmit";
4365 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4366 flow_ctrl
= "ON - transmit";
4367 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4368 flow_ctrl
= "ON - receive";
4371 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4372 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4373 speed
, duplex
, flow_ctrl
);
4375 netif_carrier_off(bp
->dev
);
4376 netdev_err(bp
->dev
, "NIC Link is Down\n");
4380 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4383 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4384 struct hwrm_port_phy_qcfg_input req
= {0};
4385 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4386 u8 link_up
= link_info
->link_up
;
4388 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4390 mutex_lock(&bp
->hwrm_cmd_lock
);
4391 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4393 mutex_unlock(&bp
->hwrm_cmd_lock
);
4397 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4398 link_info
->phy_link_status
= resp
->link
;
4399 link_info
->duplex
= resp
->duplex
;
4400 link_info
->pause
= resp
->pause
;
4401 link_info
->auto_mode
= resp
->auto_mode
;
4402 link_info
->auto_pause_setting
= resp
->auto_pause
;
4403 link_info
->force_pause_setting
= resp
->force_pause
;
4404 link_info
->duplex_setting
= resp
->duplex
;
4405 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4406 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4408 link_info
->link_speed
= 0;
4409 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4410 link_info
->auto_link_speed
= le16_to_cpu(resp
->auto_link_speed
);
4411 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4412 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4413 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4414 link_info
->phy_ver
[0] = resp
->phy_maj
;
4415 link_info
->phy_ver
[1] = resp
->phy_min
;
4416 link_info
->phy_ver
[2] = resp
->phy_bld
;
4417 link_info
->media_type
= resp
->media_type
;
4418 link_info
->transceiver
= resp
->transceiver_type
;
4419 link_info
->phy_addr
= resp
->phy_addr
;
4421 /* TODO: need to add more logic to report VF link */
4422 if (chng_link_state
) {
4423 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4424 link_info
->link_up
= 1;
4426 link_info
->link_up
= 0;
4427 if (link_up
!= link_info
->link_up
)
4428 bnxt_report_link(bp
);
4430 /* alwasy link down if not require to update link state */
4431 link_info
->link_up
= 0;
4433 mutex_unlock(&bp
->hwrm_cmd_lock
);
4438 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4440 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4441 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4442 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4443 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4444 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4446 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4448 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4449 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
4450 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4451 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
4453 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
4457 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
4458 struct hwrm_port_phy_cfg_input
*req
)
4460 u8 autoneg
= bp
->link_info
.autoneg
;
4461 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
4462 u32 advertising
= bp
->link_info
.advertising
;
4464 if (autoneg
& BNXT_AUTONEG_SPEED
) {
4466 PORT_PHY_CFG_REQ_AUTO_MODE_MASK
;
4468 req
->enables
|= cpu_to_le32(
4469 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
4470 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
4472 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
4474 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
4476 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
4477 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
4480 /* currently don't support half duplex */
4481 req
->auto_duplex
= PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL
;
4482 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
);
4483 /* tell chimp that the setting takes effect immediately */
4484 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
4487 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
4489 struct hwrm_port_phy_cfg_input req
= {0};
4492 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4493 bnxt_hwrm_set_pause_common(bp
, &req
);
4495 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
4496 bp
->link_info
.force_link_chng
)
4497 bnxt_hwrm_set_link_common(bp
, &req
);
4499 mutex_lock(&bp
->hwrm_cmd_lock
);
4500 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4501 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
4502 /* since changing of pause setting doesn't trigger any link
4503 * change event, the driver needs to update the current pause
4504 * result upon successfully return of the phy_cfg command
4506 bp
->link_info
.pause
=
4507 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
4508 bp
->link_info
.auto_pause_setting
= 0;
4509 if (!bp
->link_info
.force_link_chng
)
4510 bnxt_report_link(bp
);
4512 bp
->link_info
.force_link_chng
= false;
4513 mutex_unlock(&bp
->hwrm_cmd_lock
);
4517 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
)
4519 struct hwrm_port_phy_cfg_input req
= {0};
4521 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4523 bnxt_hwrm_set_pause_common(bp
, &req
);
4525 bnxt_hwrm_set_link_common(bp
, &req
);
4526 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4529 static int bnxt_update_phy_setting(struct bnxt
*bp
)
4532 bool update_link
= false;
4533 bool update_pause
= false;
4534 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4536 rc
= bnxt_update_link(bp
, true);
4538 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
4542 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4543 link_info
->auto_pause_setting
!= link_info
->req_flow_ctrl
)
4544 update_pause
= true;
4545 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4546 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
4547 update_pause
= true;
4548 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
4550 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4551 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
4553 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
4556 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
4558 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
4560 if (link_info
->req_link_speed
!= link_info
->auto_link_speed
)
4565 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
);
4566 else if (update_pause
)
4567 rc
= bnxt_hwrm_set_pause(bp
);
4569 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
4577 /* Common routine to pre-map certain register block to different GRC window.
4578 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4579 * in PF and 3 windows in VF that can be customized to map in different
4582 static void bnxt_preset_reg_win(struct bnxt
*bp
)
4585 /* CAG registers map to GRC window #4 */
4586 writel(BNXT_CAG_REG_BASE
,
4587 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
4591 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4595 bnxt_preset_reg_win(bp
);
4596 netif_carrier_off(bp
->dev
);
4598 rc
= bnxt_setup_int_mode(bp
);
4600 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
4605 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
4606 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4607 /* disable RFS if falling back to INTA */
4608 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
4609 bp
->flags
&= ~BNXT_FLAG_RFS
;
4612 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
4614 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
4615 goto open_err_free_mem
;
4620 rc
= bnxt_request_irq(bp
);
4622 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
4627 bnxt_enable_napi(bp
);
4629 rc
= bnxt_init_nic(bp
, irq_re_init
);
4631 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
4636 rc
= bnxt_update_phy_setting(bp
);
4642 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4643 vxlan_get_rx_port(bp
->dev
);
4645 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4647 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
))
4648 bp
->nge_port_cnt
= 1;
4651 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
4652 bnxt_enable_int(bp
);
4653 /* Enable TX queues */
4655 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4660 bnxt_disable_napi(bp
);
4666 bnxt_free_mem(bp
, true);
4670 /* rtnl_lock held */
4671 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4675 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
4677 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
4683 static int bnxt_open(struct net_device
*dev
)
4685 struct bnxt
*bp
= netdev_priv(dev
);
4688 rc
= bnxt_hwrm_func_reset(bp
);
4690 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
4695 return __bnxt_open_nic(bp
, true, true);
4698 static void bnxt_disable_int_sync(struct bnxt
*bp
)
4702 atomic_inc(&bp
->intr_sem
);
4703 if (!netif_running(bp
->dev
))
4706 bnxt_disable_int(bp
);
4707 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
4708 synchronize_irq(bp
->irq_tbl
[i
].vector
);
4711 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4715 #ifdef CONFIG_BNXT_SRIOV
4716 if (bp
->sriov_cfg
) {
4717 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
4719 BNXT_SRIOV_CFG_WAIT_TMO
);
4721 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
4724 /* Change device state to avoid TX queue wake up's */
4725 bnxt_tx_disable(bp
);
4727 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
4728 smp_mb__after_atomic();
4729 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
4732 /* Flush rings before disabling interrupts */
4733 bnxt_shutdown_nic(bp
, irq_re_init
);
4735 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4737 bnxt_disable_napi(bp
);
4738 bnxt_disable_int_sync(bp
);
4739 del_timer_sync(&bp
->timer
);
4746 bnxt_free_mem(bp
, irq_re_init
);
4750 static int bnxt_close(struct net_device
*dev
)
4752 struct bnxt
*bp
= netdev_priv(dev
);
4754 bnxt_close_nic(bp
, true, true);
4758 /* rtnl_lock held */
4759 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4765 if (!netif_running(dev
))
4772 if (!netif_running(dev
))
4784 static struct rtnl_link_stats64
*
4785 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
4788 struct bnxt
*bp
= netdev_priv(dev
);
4790 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
4795 /* TODO check if we need to synchronize with bnxt_close path */
4796 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4797 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4798 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4799 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
4801 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
4802 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4803 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
4805 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
4806 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
4807 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
4809 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
4810 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
4811 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
4813 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
4814 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
4815 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
4817 stats
->rx_missed_errors
+=
4818 le64_to_cpu(hw_stats
->rx_discard_pkts
);
4820 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4822 stats
->rx_dropped
+= le64_to_cpu(hw_stats
->rx_drop_pkts
);
4824 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
4830 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
4832 struct net_device
*dev
= bp
->dev
;
4833 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4834 struct netdev_hw_addr
*ha
;
4837 bool update
= false;
4840 netdev_for_each_mc_addr(ha
, dev
) {
4841 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
4842 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4843 vnic
->mc_list_count
= 0;
4847 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
4848 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
4855 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
4857 if (mc_count
!= vnic
->mc_list_count
) {
4858 vnic
->mc_list_count
= mc_count
;
4864 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
4866 struct net_device
*dev
= bp
->dev
;
4867 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4868 struct netdev_hw_addr
*ha
;
4871 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
4874 netdev_for_each_uc_addr(ha
, dev
) {
4875 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
4883 static void bnxt_set_rx_mode(struct net_device
*dev
)
4885 struct bnxt
*bp
= netdev_priv(dev
);
4886 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4887 u32 mask
= vnic
->rx_mask
;
4888 bool mc_update
= false;
4891 if (!netif_running(dev
))
4894 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
4895 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
4896 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
4898 /* Only allow PF to be in promiscuous mode */
4899 if ((dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
4900 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4902 uc_update
= bnxt_uc_list_updated(bp
);
4904 if (dev
->flags
& IFF_ALLMULTI
) {
4905 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4906 vnic
->mc_list_count
= 0;
4908 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
4911 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
4912 vnic
->rx_mask
= mask
;
4914 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
4915 schedule_work(&bp
->sp_task
);
4919 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
4921 struct net_device
*dev
= bp
->dev
;
4922 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4923 struct netdev_hw_addr
*ha
;
4927 netif_addr_lock_bh(dev
);
4928 uc_update
= bnxt_uc_list_updated(bp
);
4929 netif_addr_unlock_bh(dev
);
4934 mutex_lock(&bp
->hwrm_cmd_lock
);
4935 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
4936 struct hwrm_cfa_l2_filter_free_input req
= {0};
4938 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
4941 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
4943 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4946 mutex_unlock(&bp
->hwrm_cmd_lock
);
4948 vnic
->uc_filter_count
= 1;
4950 netif_addr_lock_bh(dev
);
4951 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
4952 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4954 netdev_for_each_uc_addr(ha
, dev
) {
4955 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
4957 vnic
->uc_filter_count
++;
4960 netif_addr_unlock_bh(dev
);
4962 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
4963 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
4965 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
4967 vnic
->uc_filter_count
= i
;
4973 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
4975 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
4981 static bool bnxt_rfs_capable(struct bnxt
*bp
)
4983 #ifdef CONFIG_RFS_ACCEL
4984 struct bnxt_pf_info
*pf
= &bp
->pf
;
4987 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
4990 vnics
= 1 + bp
->rx_nr_rings
;
4991 if (vnics
> pf
->max_rsscos_ctxs
|| vnics
> pf
->max_vnics
)
5000 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
5001 netdev_features_t features
)
5003 struct bnxt
*bp
= netdev_priv(dev
);
5005 if (!bnxt_rfs_capable(bp
))
5006 features
&= ~NETIF_F_NTUPLE
;
5010 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
5012 struct bnxt
*bp
= netdev_priv(dev
);
5013 u32 flags
= bp
->flags
;
5016 bool re_init
= false;
5017 bool update_tpa
= false;
5019 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
5020 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
5021 flags
|= BNXT_FLAG_GRO
;
5022 if (features
& NETIF_F_LRO
)
5023 flags
|= BNXT_FLAG_LRO
;
5025 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
5026 flags
|= BNXT_FLAG_STRIP_VLAN
;
5028 if (features
& NETIF_F_NTUPLE
)
5029 flags
|= BNXT_FLAG_RFS
;
5031 changes
= flags
^ bp
->flags
;
5032 if (changes
& BNXT_FLAG_TPA
) {
5034 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
5035 (flags
& BNXT_FLAG_TPA
) == 0)
5039 if (changes
& ~BNXT_FLAG_TPA
)
5042 if (flags
!= bp
->flags
) {
5043 u32 old_flags
= bp
->flags
;
5047 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5049 bnxt_set_ring_params(bp
);
5054 bnxt_close_nic(bp
, false, false);
5056 bnxt_set_ring_params(bp
);
5058 return bnxt_open_nic(bp
, false, false);
5061 rc
= bnxt_set_tpa(bp
,
5062 (flags
& BNXT_FLAG_TPA
) ?
5065 bp
->flags
= old_flags
;
5071 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
5073 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
5074 int i
= bnapi
->index
;
5079 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5080 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
5084 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
5086 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
5087 int i
= bnapi
->index
;
5092 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5093 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
5094 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
5095 rxr
->rx_sw_agg_prod
);
5098 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
5100 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5101 int i
= bnapi
->index
;
5103 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5104 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
5107 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
5110 struct bnxt_napi
*bnapi
;
5112 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5113 bnapi
= bp
->bnapi
[i
];
5114 if (netif_msg_drv(bp
)) {
5115 bnxt_dump_tx_sw_state(bnapi
);
5116 bnxt_dump_rx_sw_state(bnapi
);
5117 bnxt_dump_cp_sw_state(bnapi
);
5122 static void bnxt_reset_task(struct bnxt
*bp
)
5124 bnxt_dbg_dump_states(bp
);
5125 if (netif_running(bp
->dev
)) {
5126 bnxt_close_nic(bp
, false, false);
5127 bnxt_open_nic(bp
, false, false);
5131 static void bnxt_tx_timeout(struct net_device
*dev
)
5133 struct bnxt
*bp
= netdev_priv(dev
);
5135 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5136 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5137 schedule_work(&bp
->sp_task
);
5140 #ifdef CONFIG_NET_POLL_CONTROLLER
5141 static void bnxt_poll_controller(struct net_device
*dev
)
5143 struct bnxt
*bp
= netdev_priv(dev
);
5146 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5147 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5149 disable_irq(irq
->vector
);
5150 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5151 enable_irq(irq
->vector
);
5156 static void bnxt_timer(unsigned long data
)
5158 struct bnxt
*bp
= (struct bnxt
*)data
;
5159 struct net_device
*dev
= bp
->dev
;
5161 if (!netif_running(dev
))
5164 if (atomic_read(&bp
->intr_sem
) != 0)
5165 goto bnxt_restart_timer
;
5168 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5171 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5173 static void bnxt_sp_task(struct work_struct
*work
)
5175 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5178 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5179 smp_mb__after_atomic();
5180 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5181 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5185 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5186 bnxt_cfg_rx_mode(bp
);
5188 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5189 bnxt_cfg_ntp_filters(bp
);
5190 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5191 rc
= bnxt_update_link(bp
, true);
5193 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5196 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5197 bnxt_hwrm_exec_fwd_req(bp
);
5198 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5199 bnxt_hwrm_tunnel_dst_port_alloc(
5201 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5203 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5204 bnxt_hwrm_tunnel_dst_port_free(
5205 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5207 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
)) {
5208 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5209 * for BNXT_STATE_IN_SP_TASK to clear.
5211 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5213 bnxt_reset_task(bp
);
5214 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5218 smp_mb__before_atomic();
5219 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5222 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5225 struct bnxt
*bp
= netdev_priv(dev
);
5227 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5229 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5230 rc
= pci_enable_device(pdev
);
5232 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5236 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5238 "Cannot find PCI device base address, aborting\n");
5240 goto init_err_disable
;
5243 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5245 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5246 goto init_err_disable
;
5249 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5250 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5251 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5252 goto init_err_disable
;
5255 pci_set_master(pdev
);
5260 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5262 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5264 goto init_err_release
;
5267 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5269 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5271 goto init_err_release
;
5274 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5276 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5278 goto init_err_release
;
5281 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5283 spin_lock_init(&bp
->ntp_fltr_lock
);
5285 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5286 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5288 bp
->coal_ticks
= BNXT_USEC_TO_COAL_TIMER(4);
5290 bp
->coal_ticks_irq
= BNXT_USEC_TO_COAL_TIMER(1);
5291 bp
->coal_bufs_irq
= 2;
5293 init_timer(&bp
->timer
);
5294 bp
->timer
.data
= (unsigned long)bp
;
5295 bp
->timer
.function
= bnxt_timer
;
5296 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
5298 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5304 pci_iounmap(pdev
, bp
->bar2
);
5309 pci_iounmap(pdev
, bp
->bar1
);
5314 pci_iounmap(pdev
, bp
->bar0
);
5318 pci_release_regions(pdev
);
5321 pci_disable_device(pdev
);
5327 /* rtnl_lock held */
5328 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
5330 struct sockaddr
*addr
= p
;
5331 struct bnxt
*bp
= netdev_priv(dev
);
5334 if (!is_valid_ether_addr(addr
->sa_data
))
5335 return -EADDRNOTAVAIL
;
5337 #ifdef CONFIG_BNXT_SRIOV
5338 if (BNXT_VF(bp
) && is_valid_ether_addr(bp
->vf
.mac_addr
))
5339 return -EADDRNOTAVAIL
;
5342 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
5345 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5346 if (netif_running(dev
)) {
5347 bnxt_close_nic(bp
, false, false);
5348 rc
= bnxt_open_nic(bp
, false, false);
5354 /* rtnl_lock held */
5355 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
5357 struct bnxt
*bp
= netdev_priv(dev
);
5359 if (new_mtu
< 60 || new_mtu
> 9000)
5362 if (netif_running(dev
))
5363 bnxt_close_nic(bp
, false, false);
5366 bnxt_set_ring_params(bp
);
5368 if (netif_running(dev
))
5369 return bnxt_open_nic(bp
, false, false);
5374 static int bnxt_setup_tc(struct net_device
*dev
, u8 tc
)
5376 struct bnxt
*bp
= netdev_priv(dev
);
5378 if (tc
> bp
->max_tc
) {
5379 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
5384 if (netdev_get_num_tc(dev
) == tc
)
5388 int max_rx_rings
, max_tx_rings
, rc
;
5391 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5394 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5395 if (rc
|| bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
5399 /* Needs to close the device and do hw resource re-allocations */
5400 if (netif_running(bp
->dev
))
5401 bnxt_close_nic(bp
, true, false);
5404 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
5405 netdev_set_num_tc(dev
, tc
);
5407 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5408 netdev_reset_tc(dev
);
5410 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
5411 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5413 if (netif_running(bp
->dev
))
5414 return bnxt_open_nic(bp
, true, false);
5419 #ifdef CONFIG_RFS_ACCEL
5420 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
5421 struct bnxt_ntuple_filter
*f2
)
5423 struct flow_keys
*keys1
= &f1
->fkeys
;
5424 struct flow_keys
*keys2
= &f2
->fkeys
;
5426 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
5427 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
5428 keys1
->ports
.ports
== keys2
->ports
.ports
&&
5429 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
5430 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
5431 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
5437 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
5438 u16 rxq_index
, u32 flow_id
)
5440 struct bnxt
*bp
= netdev_priv(dev
);
5441 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
5442 struct flow_keys
*fkeys
;
5443 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
5444 int rc
= 0, idx
, bit_id
;
5445 struct hlist_head
*head
;
5447 if (skb
->encapsulation
)
5448 return -EPROTONOSUPPORT
;
5450 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
5454 fkeys
= &new_fltr
->fkeys
;
5455 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
5456 rc
= -EPROTONOSUPPORT
;
5460 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
5461 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
5462 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
5463 rc
= -EPROTONOSUPPORT
;
5467 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
5469 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
5470 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
5472 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
5473 if (bnxt_fltr_match(fltr
, new_fltr
)) {
5481 spin_lock_bh(&bp
->ntp_fltr_lock
);
5482 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
5483 BNXT_NTP_FLTR_MAX_FLTR
, 0);
5485 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5490 new_fltr
->sw_id
= (u16
)bit_id
;
5491 new_fltr
->flow_id
= flow_id
;
5492 new_fltr
->rxq
= rxq_index
;
5493 hlist_add_head_rcu(&new_fltr
->hash
, head
);
5494 bp
->ntp_fltr_count
++;
5495 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5497 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
5498 schedule_work(&bp
->sp_task
);
5500 return new_fltr
->sw_id
;
5507 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5511 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
5512 struct hlist_head
*head
;
5513 struct hlist_node
*tmp
;
5514 struct bnxt_ntuple_filter
*fltr
;
5517 head
= &bp
->ntp_fltr_hash_tbl
[i
];
5518 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
5521 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
5522 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
5525 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
5530 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
5535 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
5539 spin_lock_bh(&bp
->ntp_fltr_lock
);
5540 hlist_del_rcu(&fltr
->hash
);
5541 bp
->ntp_fltr_count
--;
5542 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5544 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
5553 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5557 #endif /* CONFIG_RFS_ACCEL */
5559 static void bnxt_add_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5562 struct bnxt
*bp
= netdev_priv(dev
);
5564 if (!netif_running(dev
))
5567 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5570 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= port
)
5573 bp
->vxlan_port_cnt
++;
5574 if (bp
->vxlan_port_cnt
== 1) {
5575 bp
->vxlan_port
= port
;
5576 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
5577 schedule_work(&bp
->sp_task
);
5581 static void bnxt_del_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5584 struct bnxt
*bp
= netdev_priv(dev
);
5586 if (!netif_running(dev
))
5589 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5592 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
== port
) {
5593 bp
->vxlan_port_cnt
--;
5595 if (bp
->vxlan_port_cnt
== 0) {
5596 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
5597 schedule_work(&bp
->sp_task
);
5602 static const struct net_device_ops bnxt_netdev_ops
= {
5603 .ndo_open
= bnxt_open
,
5604 .ndo_start_xmit
= bnxt_start_xmit
,
5605 .ndo_stop
= bnxt_close
,
5606 .ndo_get_stats64
= bnxt_get_stats64
,
5607 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
5608 .ndo_do_ioctl
= bnxt_ioctl
,
5609 .ndo_validate_addr
= eth_validate_addr
,
5610 .ndo_set_mac_address
= bnxt_change_mac_addr
,
5611 .ndo_change_mtu
= bnxt_change_mtu
,
5612 .ndo_fix_features
= bnxt_fix_features
,
5613 .ndo_set_features
= bnxt_set_features
,
5614 .ndo_tx_timeout
= bnxt_tx_timeout
,
5615 #ifdef CONFIG_BNXT_SRIOV
5616 .ndo_get_vf_config
= bnxt_get_vf_config
,
5617 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
5618 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
5619 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
5620 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
5621 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
5623 #ifdef CONFIG_NET_POLL_CONTROLLER
5624 .ndo_poll_controller
= bnxt_poll_controller
,
5626 .ndo_setup_tc
= bnxt_setup_tc
,
5627 #ifdef CONFIG_RFS_ACCEL
5628 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
5630 .ndo_add_vxlan_port
= bnxt_add_vxlan_port
,
5631 .ndo_del_vxlan_port
= bnxt_del_vxlan_port
,
5632 #ifdef CONFIG_NET_RX_BUSY_POLL
5633 .ndo_busy_poll
= bnxt_busy_poll
,
5637 static void bnxt_remove_one(struct pci_dev
*pdev
)
5639 struct net_device
*dev
= pci_get_drvdata(pdev
);
5640 struct bnxt
*bp
= netdev_priv(dev
);
5643 bnxt_sriov_disable(bp
);
5645 unregister_netdev(dev
);
5646 cancel_work_sync(&bp
->sp_task
);
5649 bnxt_hwrm_func_drv_unrgtr(bp
);
5650 bnxt_free_hwrm_resources(bp
);
5651 pci_iounmap(pdev
, bp
->bar2
);
5652 pci_iounmap(pdev
, bp
->bar1
);
5653 pci_iounmap(pdev
, bp
->bar0
);
5656 pci_release_regions(pdev
);
5657 pci_disable_device(pdev
);
5660 static int bnxt_probe_phy(struct bnxt
*bp
)
5663 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5664 char phy_ver
[PHY_VER_STR_LEN
];
5666 rc
= bnxt_update_link(bp
, false);
5668 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
5673 /*initialize the ethool setting copy with NVM settings */
5674 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
5675 link_info
->autoneg
|= BNXT_AUTONEG_SPEED
;
5677 if (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) {
5678 if (link_info
->auto_pause_setting
== BNXT_LINK_PAUSE_BOTH
)
5679 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
5680 link_info
->req_flow_ctrl
= link_info
->auto_pause_setting
;
5681 } else if (link_info
->force_pause_setting
& BNXT_LINK_PAUSE_BOTH
) {
5682 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
5684 link_info
->req_duplex
= link_info
->duplex_setting
;
5685 if (link_info
->autoneg
& BNXT_AUTONEG_SPEED
)
5686 link_info
->req_link_speed
= link_info
->auto_link_speed
;
5688 link_info
->req_link_speed
= link_info
->force_link_speed
;
5689 link_info
->advertising
= link_info
->auto_link_speeds
;
5690 snprintf(phy_ver
, PHY_VER_STR_LEN
, " ph %d.%d.%d",
5691 link_info
->phy_ver
[0],
5692 link_info
->phy_ver
[1],
5693 link_info
->phy_ver
[2]);
5694 strcat(bp
->fw_ver_str
, phy_ver
);
5698 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
5702 if (!pdev
->msix_cap
)
5705 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
5706 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
5709 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
5712 int max_ring_grps
= 0;
5714 #ifdef CONFIG_BNXT_SRIOV
5716 *max_tx
= bp
->vf
.max_tx_rings
;
5717 *max_rx
= bp
->vf
.max_rx_rings
;
5718 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
5719 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
5720 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
5724 *max_tx
= bp
->pf
.max_tx_rings
;
5725 *max_rx
= bp
->pf
.max_rx_rings
;
5726 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
5727 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
5728 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
5731 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5733 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
5736 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
5740 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
5741 if (!rx
|| !tx
|| !cp
)
5746 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
5749 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
5751 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
5755 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5756 dflt_rings
= netif_get_num_default_rss_queues();
5757 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5760 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
5761 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
5762 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5763 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5764 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5765 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5769 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
5771 static int version_printed
;
5772 struct net_device
*dev
;
5776 if (version_printed
++ == 0)
5777 pr_info("%s", version
);
5779 max_irqs
= bnxt_get_max_irq(pdev
);
5780 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
5784 bp
= netdev_priv(dev
);
5786 if (bnxt_vf_pciid(ent
->driver_data
))
5787 bp
->flags
|= BNXT_FLAG_VF
;
5790 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
5792 rc
= bnxt_init_board(pdev
, dev
);
5796 dev
->netdev_ops
= &bnxt_netdev_ops
;
5797 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
5798 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
5800 pci_set_drvdata(pdev
, dev
);
5802 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5803 NETIF_F_TSO
| NETIF_F_TSO6
|
5804 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5805 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
|
5807 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
5809 dev
->hw_enc_features
=
5810 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5811 NETIF_F_TSO
| NETIF_F_TSO6
|
5812 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5813 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
;
5814 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
5815 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
5816 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
5817 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
5818 dev
->priv_flags
|= IFF_UNICAST_FLT
;
5820 #ifdef CONFIG_BNXT_SRIOV
5821 init_waitqueue_head(&bp
->sriov_cfg_wait
);
5823 rc
= bnxt_alloc_hwrm_resources(bp
);
5827 mutex_init(&bp
->hwrm_cmd_lock
);
5828 bnxt_hwrm_ver_get(bp
);
5830 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
5834 /* Get the MAX capabilities for this function */
5835 rc
= bnxt_hwrm_func_qcaps(bp
);
5837 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
5843 rc
= bnxt_hwrm_queue_qportcfg(bp
);
5845 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
5851 bnxt_set_tpa_flags(bp
);
5852 bnxt_set_ring_params(bp
);
5854 bp
->pf
.max_irqs
= max_irqs
;
5855 #if defined(CONFIG_BNXT_SRIOV)
5857 bp
->vf
.max_irqs
= max_irqs
;
5859 bnxt_set_dflt_rings(bp
);
5862 dev
->hw_features
|= NETIF_F_NTUPLE
;
5863 if (bnxt_rfs_capable(bp
)) {
5864 bp
->flags
|= BNXT_FLAG_RFS
;
5865 dev
->features
|= NETIF_F_NTUPLE
;
5869 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
5870 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
5872 rc
= bnxt_probe_phy(bp
);
5876 rc
= register_netdev(dev
);
5880 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
5881 board_info
[ent
->driver_data
].name
,
5882 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
5887 pci_iounmap(pdev
, bp
->bar0
);
5888 pci_release_regions(pdev
);
5889 pci_disable_device(pdev
);
5896 static struct pci_driver bnxt_pci_driver
= {
5897 .name
= DRV_MODULE_NAME
,
5898 .id_table
= bnxt_pci_tbl
,
5899 .probe
= bnxt_init_one
,
5900 .remove
= bnxt_remove_one
,
5901 #if defined(CONFIG_BNXT_SRIOV)
5902 .sriov_configure
= bnxt_sriov_configure
,
5906 module_pci_driver(bnxt_pci_driver
);