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bnxt_en: Fix dmesg log firmware error messages.
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt_hsi.h
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2015 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9
10 #ifndef BNXT_HSI_H
11 #define BNXT_HSI_H
12
13 /* per-context HW statistics -- chip view */
14 struct ctx_hw_stats {
15 __le64 rx_ucast_pkts;
16 __le64 rx_mcast_pkts;
17 __le64 rx_bcast_pkts;
18 __le64 rx_discard_pkts;
19 __le64 rx_drop_pkts;
20 __le64 rx_ucast_bytes;
21 __le64 rx_mcast_bytes;
22 __le64 rx_bcast_bytes;
23 __le64 tx_ucast_pkts;
24 __le64 tx_mcast_pkts;
25 __le64 tx_bcast_pkts;
26 __le64 tx_discard_pkts;
27 __le64 tx_drop_pkts;
28 __le64 tx_ucast_bytes;
29 __le64 tx_mcast_bytes;
30 __le64 tx_bcast_bytes;
31 __le64 tpa_pkts;
32 __le64 tpa_bytes;
33 __le64 tpa_events;
34 __le64 tpa_aborts;
35 };
36
37 /* Statistics Ejection Buffer Completion Record (16 bytes) */
38 struct eject_cmpl {
39 __le16 type;
40 #define EJECT_CMPL_TYPE_MASK 0x3fUL
41 #define EJECT_CMPL_TYPE_SFT 0
42 #define EJECT_CMPL_TYPE_STAT_EJECT (0x1aUL << 0)
43 __le16 len;
44 __le32 opaque;
45 __le32 v;
46 #define EJECT_CMPL_V 0x1UL
47 __le32 unused_2;
48 };
49
50 /* HWRM Completion Record (16 bytes) */
51 struct hwrm_cmpl {
52 __le16 type;
53 #define HWRM_CMPL_TYPE_MASK 0x3fUL
54 #define HWRM_CMPL_TYPE_SFT 0
55 #define HWRM_CMPL_TYPE_HWRM_DONE (0x20UL << 0)
56 __le16 sequence_id;
57 __le32 unused_1;
58 __le32 v;
59 #define HWRM_CMPL_V 0x1UL
60 __le32 unused_3;
61 };
62
63 /* HWRM Forwarded Request (16 bytes) */
64 struct hwrm_fwd_req_cmpl {
65 __le16 req_len_type;
66 #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL
67 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0
68 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (0x22UL << 0)
69 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL
70 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6
71 __le16 source_id;
72 __le32 unused_0;
73 __le32 req_buf_addr_v[2];
74 #define HWRM_FWD_REQ_CMPL_V 0x1UL
75 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
76 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
77 };
78
79 /* HWRM Forwarded Response (16 bytes) */
80 struct hwrm_fwd_resp_cmpl {
81 __le16 type;
82 #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL
83 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0
84 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP (0x24UL << 0)
85 __le16 source_id;
86 __le16 resp_len;
87 __le16 unused_1;
88 __le32 resp_buf_addr_v[2];
89 #define HWRM_FWD_RESP_CMPL_V 0x1UL
90 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
91 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
92 };
93
94 /* HWRM Asynchronous Event Completion Record (16 bytes) */
95 struct hwrm_async_event_cmpl {
96 __le16 type;
97 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL
98 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0
99 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
100 __le16 event_id;
101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
102 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
103 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
104 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
106 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0)
107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
109 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0)
111 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (0x30UL << 0)
112 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
113 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0)
114 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR (0xffUL << 0)
115 __le32 event_data2;
116 u8 opaque_v;
117 #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL
118 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
119 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1
120 u8 timestamp_lo;
121 __le16 timestamp_hi;
122 __le32 event_data1;
123 };
124
125 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */
126 struct hwrm_async_event_cmpl_link_status_change {
127 __le16 type;
128 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL
129 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0
130 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
131 __le16 event_id;
132 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0)
133 __le32 event_data2;
134 u8 opaque_v;
135 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL
136 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
137 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
138 u8 timestamp_lo;
139 __le16 timestamp_hi;
140 __le32 event_data1;
141 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL
142 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0)
143 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0)
144 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL
145 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1
146 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL
147 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4
148 };
149
150 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */
151 struct hwrm_async_event_cmpl_link_mtu_change {
152 __le16 type;
153 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL
154 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0
155 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
156 __le16 event_id;
157 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0)
158 __le32 event_data2;
159 u8 opaque_v;
160 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL
161 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL
162 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1
163 u8 timestamp_lo;
164 __le16 timestamp_hi;
165 __le32 event_data1;
166 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL
167 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0
168 };
169
170 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */
171 struct hwrm_async_event_cmpl_link_speed_change {
172 __le16 type;
173 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL
174 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0
175 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
176 __le16 event_id;
177 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0)
178 __le32 event_data2;
179 u8 opaque_v;
180 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL
181 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL
182 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1
183 u8 timestamp_lo;
184 __le16 timestamp_hi;
185 __le32 event_data1;
186 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL
187 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL
188 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1
189 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1)
190 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1)
191 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1)
192 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1)
193 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1)
194 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1)
195 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1)
196 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1)
197 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1)
198 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL
199 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16
200 };
201
202 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */
203 struct hwrm_async_event_cmpl_dcb_config_change {
204 __le16 type;
205 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL
206 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0
207 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
208 __le16 event_id;
209 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0)
210 __le32 event_data2;
211 u8 opaque_v;
212 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL
213 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL
214 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1
215 u8 timestamp_lo;
216 __le16 timestamp_hi;
217 __le32 event_data1;
218 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL
219 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0
220 };
221
222 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */
223 struct hwrm_async_event_cmpl_port_conn_not_allowed {
224 __le16 type;
225 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL
226 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0
227 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
228 __le16 event_id;
229 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0)
230 __le32 event_data2;
231 u8 opaque_v;
232 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL
233 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
234 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
235 u8 timestamp_lo;
236 __le16 timestamp_hi;
237 __le32 event_data1;
238 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL
239 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0
240 };
241
242 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */
243 struct hwrm_async_event_cmpl_func_drvr_unload {
244 __le16 type;
245 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL
246 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0
247 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
248 __le16 event_id;
249 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0)
250 __le32 event_data2;
251 u8 opaque_v;
252 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL
253 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
254 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1
255 u8 timestamp_lo;
256 __le16 timestamp_hi;
257 __le32 event_data1;
258 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
259 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
260 };
261
262 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */
263 struct hwrm_async_event_cmpl_func_drvr_load {
264 __le16 type;
265 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL
266 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0
267 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
268 __le16 event_id;
269 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0)
270 __le32 event_data2;
271 u8 opaque_v;
272 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL
273 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL
274 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1
275 u8 timestamp_lo;
276 __le16 timestamp_hi;
277 __le32 event_data1;
278 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
279 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
280 };
281
282 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */
283 struct hwrm_async_event_cmpl_pf_drvr_unload {
284 __le16 type;
285 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL
286 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0
287 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
288 __le16 event_id;
289 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0)
290 __le32 event_data2;
291 u8 opaque_v;
292 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL
293 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL
294 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1
295 u8 timestamp_lo;
296 __le16 timestamp_hi;
297 __le32 event_data1;
298 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
299 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0
300 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL
301 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16
302 };
303
304 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */
305 struct hwrm_async_event_cmpl_pf_drvr_load {
306 __le16 type;
307 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL
308 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0
309 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
310 __le16 event_id;
311 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0)
312 __le32 event_data2;
313 u8 opaque_v;
314 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL
315 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL
316 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1
317 u8 timestamp_lo;
318 __le16 timestamp_hi;
319 __le32 event_data1;
320 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL
321 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0
322 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL
323 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16
324 };
325
326 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */
327 struct hwrm_async_event_cmpl_vf_flr {
328 __le16 type;
329 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL
330 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0
331 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
332 __le16 event_id;
333 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR (0x30UL << 0)
334 __le32 event_data2;
335 u8 opaque_v;
336 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL
337 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL
338 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1
339 u8 timestamp_lo;
340 __le16 timestamp_hi;
341 __le32 event_data1;
342 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL
343 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0
344 };
345
346 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */
347 struct hwrm_async_event_cmpl_vf_mac_addr_change {
348 __le16 type;
349 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL
350 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0
351 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
352 __le16 event_id;
353 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0)
354 __le32 event_data2;
355 u8 opaque_v;
356 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL
357 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL
358 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1
359 u8 timestamp_lo;
360 __le16 timestamp_hi;
361 __le32 event_data1;
362 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL
363 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0
364 };
365
366 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */
367 struct hwrm_async_event_cmpl_hwrm_error {
368 __le16 type;
369 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL
370 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
371 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
372 __le16 event_id;
373 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR (0xffUL << 0)
374 __le32 event_data2;
375 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL
376 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
377 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING (0x0UL << 0)
378 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL (0x1UL << 0)
379 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL (0x2UL << 0)
380 u8 opaque_v;
381 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL
382 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
383 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
384 u8 timestamp_lo;
385 __le16 timestamp_hi;
386 __le32 event_data1;
387 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL
388 };
389
390 /* HW Resource Manager Specification 1.0.0 */
391 #define HWRM_VERSION_MAJOR 1
392 #define HWRM_VERSION_MINOR 0
393 #define HWRM_VERSION_UPDATE 0
394
395 #define HWRM_VERSION_STR "1.0.0"
396 /*
397 * Following is the signature for HWRM message field that indicates not
398 * applicable (All F's). Need to cast it the size of the field if needed.
399 */
400 #define HWRM_NA_SIGNATURE ((__le32)(-1))
401 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */
402 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */
403 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */
404 #define HW_HASH_KEY_SIZE 40
405 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */
406 /* Input (16 bytes) */
407 struct input {
408 __le16 req_type;
409 __le16 cmpl_ring;
410 __le16 seq_id;
411 __le16 target_id;
412 __le64 resp_addr;
413 };
414
415 /* Output (8 bytes) */
416 struct output {
417 __le16 error_code;
418 __le16 req_type;
419 __le16 seq_id;
420 __le16 resp_len;
421 };
422
423 /* Command numbering (8 bytes) */
424 struct cmd_nums {
425 __le16 req_type;
426 #define HWRM_VER_GET (0x0UL)
427 #define HWRM_FUNC_BUF_UNRGTR (0xeUL)
428 #define HWRM_FUNC_VF_CFG (0xfUL)
429 #define RESERVED1 (0x10UL)
430 #define HWRM_FUNC_RESET (0x11UL)
431 #define HWRM_FUNC_GETFID (0x12UL)
432 #define HWRM_FUNC_VF_ALLOC (0x13UL)
433 #define HWRM_FUNC_VF_FREE (0x14UL)
434 #define HWRM_FUNC_QCAPS (0x15UL)
435 #define HWRM_FUNC_QCFG (0x16UL)
436 #define HWRM_FUNC_CFG (0x17UL)
437 #define HWRM_FUNC_QSTATS (0x18UL)
438 #define HWRM_FUNC_CLR_STATS (0x19UL)
439 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL)
440 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL)
441 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL)
442 #define HWRM_FUNC_DRV_RGTR (0x1dUL)
443 #define HWRM_FUNC_DRV_QVER (0x1eUL)
444 #define HWRM_FUNC_BUF_RGTR (0x1fUL)
445 #define HWRM_PORT_PHY_CFG (0x20UL)
446 #define HWRM_PORT_MAC_CFG (0x21UL)
447 #define RESERVED2 (0x22UL)
448 #define HWRM_PORT_QSTATS (0x23UL)
449 #define HWRM_PORT_LPBK_QSTATS (0x24UL)
450 #define HWRM_PORT_CLR_STATS (0x25UL)
451 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL)
452 #define HWRM_PORT_PHY_QCFG (0x27UL)
453 #define HWRM_PORT_MAC_QCFG (0x28UL)
454 #define HWRM_PORT_BLINK_LED (0x29UL)
455 #define HWRM_QUEUE_QPORTCFG (0x30UL)
456 #define HWRM_QUEUE_QCFG (0x31UL)
457 #define HWRM_QUEUE_CFG (0x32UL)
458 #define HWRM_QUEUE_BUFFERS_QCFG (0x33UL)
459 #define HWRM_QUEUE_BUFFERS_CFG (0x34UL)
460 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL)
461 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL)
462 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL)
463 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL)
464 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL)
465 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL)
466 #define HWRM_VNIC_ALLOC (0x40UL)
467 #define HWRM_VNIC_FREE (0x41UL)
468 #define HWRM_VNIC_CFG (0x42UL)
469 #define HWRM_VNIC_QCFG (0x43UL)
470 #define HWRM_VNIC_TPA_CFG (0x44UL)
471 #define HWRM_VNIC_TPA_QCFG (0x45UL)
472 #define HWRM_VNIC_RSS_CFG (0x46UL)
473 #define HWRM_VNIC_RSS_QCFG (0x47UL)
474 #define HWRM_VNIC_PLCMODES_CFG (0x48UL)
475 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL)
476 #define HWRM_RING_ALLOC (0x50UL)
477 #define HWRM_RING_FREE (0x51UL)
478 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL)
479 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL)
480 #define HWRM_RING_RESET (0x5eUL)
481 #define HWRM_RING_GRP_ALLOC (0x60UL)
482 #define HWRM_RING_GRP_FREE (0x61UL)
483 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL)
484 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL)
485 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL)
486 #define HWRM_CFA_L2_FILTER_FREE (0x91UL)
487 #define HWRM_CFA_L2_FILTER_CFG (0x92UL)
488 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL)
489 #define RESERVED3 (0x94UL)
490 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL)
491 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL)
492 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL)
493 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL)
494 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL)
495 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL)
496 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL)
497 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL)
498 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL)
499 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL)
500 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL)
501 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL)
502 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL)
503 #define HWRM_STAT_CTX_ALLOC (0xb0UL)
504 #define HWRM_STAT_CTX_FREE (0xb1UL)
505 #define HWRM_STAT_CTX_QUERY (0xb2UL)
506 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL)
507 #define HWRM_FW_RESET (0xc0UL)
508 #define HWRM_FW_QSTATUS (0xc1UL)
509 #define HWRM_EXEC_FWD_RESP (0xd0UL)
510 #define HWRM_REJECT_FWD_RESP (0xd1UL)
511 #define HWRM_FWD_RESP (0xd2UL)
512 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL)
513 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL)
514 #define HWRM_DBG_READ_DIRECT (0xff10UL)
515 #define HWRM_DBG_READ_INDIRECT (0xff11UL)
516 #define HWRM_DBG_WRITE_DIRECT (0xff12UL)
517 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL)
518 #define HWRM_DBG_DUMP (0xff14UL)
519 #define HWRM_NVM_MODIFY (0xfff4UL)
520 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL)
521 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL)
522 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL)
523 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL)
524 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL)
525 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL)
526 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL)
527 #define HWRM_NVM_RAW_DUMP (0xfffcUL)
528 #define HWRM_NVM_READ (0xfffdUL)
529 #define HWRM_NVM_WRITE (0xfffeUL)
530 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL)
531 __le16 unused_0[3];
532 };
533
534 struct ret_codes {
535 __le16 error_code;
536 #define HWRM_ERR_CODE_SUCCESS (0x0UL)
537 #define HWRM_ERR_CODE_FAIL (0x1UL)
538 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL)
539 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL)
540 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL)
541 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL)
542 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL)
543 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL)
544 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL)
545 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL)
546 __le16 unused_0[3];
547 };
548
549 /* Output (16 bytes) */
550 struct hwrm_err_output {
551 __le16 error_code;
552 __le16 req_type;
553 __le16 seq_id;
554 __le16 resp_len;
555 __le32 opaque_0;
556 __le16 opaque_1;
557 u8 cmd_err;
558 u8 valid;
559 };
560
561 /* Port Tx Statistics Formats (408 bytes) */
562 struct tx_port_stats {
563 __le64 tx_64b_frames;
564 __le64 tx_65b_127b_frames;
565 __le64 tx_128b_255b_frames;
566 __le64 tx_256b_511b_frames;
567 __le64 tx_512b_1023b_frames;
568 __le64 tx_1024b_1518_frames;
569 __le64 tx_good_vlan_frames;
570 __le64 tx_1519b_2047_frames;
571 __le64 tx_2048b_4095b_frames;
572 __le64 tx_4096b_9216b_frames;
573 __le64 tx_9217b_16383b_frames;
574 __le64 tx_good_frames;
575 __le64 tx_total_frames;
576 __le64 tx_ucast_frames;
577 __le64 tx_mcast_frames;
578 __le64 tx_bcast_frames;
579 __le64 tx_pause_frames;
580 __le64 tx_pfc_frames;
581 __le64 tx_jabber_frames;
582 __le64 tx_fcs_err_frames;
583 __le64 tx_control_frames;
584 __le64 tx_oversz_frames;
585 __le64 tx_single_dfrl_frames;
586 __le64 tx_multi_dfrl_frames;
587 __le64 tx_single_coll_frames;
588 __le64 tx_multi_coll_frames;
589 __le64 tx_late_coll_frames;
590 __le64 tx_excessive_coll_frames;
591 __le64 tx_frag_frames;
592 __le64 tx_err;
593 __le64 tx_tagged_frames;
594 __le64 tx_dbl_tagged_frames;
595 __le64 tx_runt_frames;
596 __le64 tx_fifo_underruns;
597 __le64 tx_pfc_ena_frames_pri0;
598 __le64 tx_pfc_ena_frames_pri1;
599 __le64 tx_pfc_ena_frames_pri2;
600 __le64 tx_pfc_ena_frames_pri3;
601 __le64 tx_pfc_ena_frames_pri4;
602 __le64 tx_pfc_ena_frames_pri5;
603 __le64 tx_pfc_ena_frames_pri6;
604 __le64 tx_pfc_ena_frames_pri7;
605 __le64 tx_eee_lpi_events;
606 __le64 tx_eee_lpi_duration;
607 __le64 tx_llfc_logical_msgs;
608 __le64 tx_hcfc_msgs;
609 __le64 tx_total_collisions;
610 __le64 tx_bytes;
611 __le64 tx_xthol_frames;
612 __le64 tx_stat_discard;
613 __le64 tx_stat_error;
614 };
615
616 /* Port Rx Statistics Formats (528 bytes) */
617 struct rx_port_stats {
618 __le64 rx_64b_frames;
619 __le64 rx_65b_127b_frames;
620 __le64 rx_128b_255b_frames;
621 __le64 rx_256b_511b_frames;
622 __le64 rx_512b_1023b_frames;
623 __le64 rx_1024b_1518_frames;
624 __le64 rx_good_vlan_frames;
625 __le64 rx_1519b_2047b_frames;
626 __le64 rx_2048b_4095b_frames;
627 __le64 rx_4096b_9216b_frames;
628 __le64 rx_9217b_16383b_frames;
629 __le64 rx_total_frames;
630 __le64 rx_ucast_frames;
631 __le64 rx_mcast_frames;
632 __le64 rx_bcast_frames;
633 __le64 rx_fcs_err_frames;
634 __le64 rx_ctrl_frames;
635 __le64 rx_pause_frames;
636 __le64 rx_pfc_frames;
637 __le64 rx_unsupported_opcode_frames;
638 __le64 rx_unsupported_da_pausepfc_frames;
639 __le64 rx_wrong_sa_frames;
640 __le64 rx_align_err_frames;
641 __le64 rx_oor_len_frames;
642 __le64 rx_code_err_frames;
643 __le64 rx_false_carrier_frames;
644 __le64 rx_ovrsz_frames;
645 __le64 rx_jbr_frames;
646 __le64 rx_mtu_err_frames;
647 __le64 rx_match_crc_frames;
648 __le64 rx_promiscuous_frames;
649 __le64 rx_tagged_frames;
650 __le64 rx_double_tagged_frames;
651 __le64 rx_trunc_frames;
652 __le64 rx_good_frames;
653 __le64 rx_pfc_xon2xoff_frames_pri0;
654 __le64 rx_pfc_xon2xoff_frames_pri1;
655 __le64 rx_pfc_xon2xoff_frames_pri2;
656 __le64 rx_pfc_xon2xoff_frames_pri3;
657 __le64 rx_pfc_xon2xoff_frames_pri4;
658 __le64 rx_pfc_xon2xoff_frames_pri5;
659 __le64 rx_pfc_xon2xoff_frames_pri6;
660 __le64 rx_pfc_xon2xoff_frames_pri7;
661 __le64 rx_pfc_ena_frames_pri0;
662 __le64 rx_pfc_ena_frames_pri1;
663 __le64 rx_pfc_ena_frames_pri2;
664 __le64 rx_pfc_ena_frames_pri3;
665 __le64 rx_pfc_ena_frames_pri4;
666 __le64 rx_pfc_ena_frames_pri5;
667 __le64 rx_pfc_ena_frames_pri6;
668 __le64 rx_pfc_ena_frames_pri7;
669 __le64 rx_sch_crc_err_frames;
670 __le64 rx_undrsz_frames;
671 __le64 rx_frag_frames;
672 __le64 rx_eee_lpi_events;
673 __le64 rx_eee_lpi_duration;
674 __le64 rx_llfc_physical_msgs;
675 __le64 rx_llfc_logical_msgs;
676 __le64 rx_llfc_msgs_with_crc_err;
677 __le64 rx_hcfc_msgs;
678 __le64 rx_hcfc_msgs_with_crc_err;
679 __le64 rx_bytes;
680 __le64 rx_runt_bytes;
681 __le64 rx_runt_frames;
682 __le64 rx_stat_discard;
683 __le64 rx_stat_err;
684 };
685
686 /* hwrm_ver_get */
687 /* Input (24 bytes) */
688 struct hwrm_ver_get_input {
689 __le16 req_type;
690 __le16 cmpl_ring;
691 __le16 seq_id;
692 __le16 target_id;
693 __le64 resp_addr;
694 u8 hwrm_intf_maj;
695 u8 hwrm_intf_min;
696 u8 hwrm_intf_upd;
697 u8 unused_0[5];
698 };
699
700 /* Output (128 bytes) */
701 struct hwrm_ver_get_output {
702 __le16 error_code;
703 __le16 req_type;
704 __le16 seq_id;
705 __le16 resp_len;
706 u8 hwrm_intf_maj;
707 u8 hwrm_intf_min;
708 u8 hwrm_intf_upd;
709 u8 hwrm_intf_rsvd;
710 u8 hwrm_fw_maj;
711 u8 hwrm_fw_min;
712 u8 hwrm_fw_bld;
713 u8 hwrm_fw_rsvd;
714 u8 mgmt_fw_maj;
715 u8 mgmt_fw_min;
716 u8 mgmt_fw_bld;
717 u8 mgmt_fw_rsvd;
718 u8 netctrl_fw_maj;
719 u8 netctrl_fw_min;
720 u8 netctrl_fw_bld;
721 u8 netctrl_fw_rsvd;
722 __le32 reserved1;
723 u8 roce_fw_maj;
724 u8 roce_fw_min;
725 u8 roce_fw_bld;
726 u8 roce_fw_rsvd;
727 char hwrm_fw_name[16];
728 char mgmt_fw_name[16];
729 char netctrl_fw_name[16];
730 __le32 reserved2[4];
731 char roce_fw_name[16];
732 __le16 chip_num;
733 u8 chip_rev;
734 u8 chip_metal;
735 u8 chip_bond_id;
736 u8 chip_platform_type;
737 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC (0x0UL << 0)
738 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA (0x1UL << 0)
739 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM (0x2UL << 0)
740 __le16 max_req_win_len;
741 __le16 max_resp_len;
742 __le16 def_req_timeout;
743 u8 unused_0;
744 u8 unused_1;
745 u8 unused_2;
746 u8 valid;
747 };
748
749 /* hwrm_func_reset */
750 /* Input (24 bytes) */
751 struct hwrm_func_reset_input {
752 __le16 req_type;
753 __le16 cmpl_ring;
754 __le16 seq_id;
755 __le16 target_id;
756 __le64 resp_addr;
757 __le32 enables;
758 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL
759 __le16 vf_id;
760 u8 func_reset_level;
761 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL (0x0UL << 0)
762 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME (0x1UL << 0)
763 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN (0x2UL << 0)
764 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF (0x3UL << 0)
765 u8 unused_0;
766 };
767
768 /* Output (16 bytes) */
769 struct hwrm_func_reset_output {
770 __le16 error_code;
771 __le16 req_type;
772 __le16 seq_id;
773 __le16 resp_len;
774 __le32 unused_0;
775 u8 unused_1;
776 u8 unused_2;
777 u8 unused_3;
778 u8 valid;
779 };
780
781 /* hwrm_func_getfid */
782 /* Input (24 bytes) */
783 struct hwrm_func_getfid_input {
784 __le16 req_type;
785 __le16 cmpl_ring;
786 __le16 seq_id;
787 __le16 target_id;
788 __le64 resp_addr;
789 __le32 enables;
790 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL
791 __le16 pci_id;
792 __le16 unused_0;
793 };
794
795 /* Output (16 bytes) */
796 struct hwrm_func_getfid_output {
797 __le16 error_code;
798 __le16 req_type;
799 __le16 seq_id;
800 __le16 resp_len;
801 __le16 fid;
802 u8 unused_0;
803 u8 unused_1;
804 u8 unused_2;
805 u8 unused_3;
806 u8 unused_4;
807 u8 valid;
808 };
809
810 /* hwrm_func_vf_alloc */
811 /* Input (24 bytes) */
812 struct hwrm_func_vf_alloc_input {
813 __le16 req_type;
814 __le16 cmpl_ring;
815 __le16 seq_id;
816 __le16 target_id;
817 __le64 resp_addr;
818 __le32 enables;
819 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL
820 __le16 first_vf_id;
821 __le16 num_vfs;
822 };
823
824 /* Output (16 bytes) */
825 struct hwrm_func_vf_alloc_output {
826 __le16 error_code;
827 __le16 req_type;
828 __le16 seq_id;
829 __le16 resp_len;
830 __le16 first_vf_id;
831 u8 unused_0;
832 u8 unused_1;
833 u8 unused_2;
834 u8 unused_3;
835 u8 unused_4;
836 u8 valid;
837 };
838
839 /* hwrm_func_vf_free */
840 /* Input (24 bytes) */
841 struct hwrm_func_vf_free_input {
842 __le16 req_type;
843 __le16 cmpl_ring;
844 __le16 seq_id;
845 __le16 target_id;
846 __le64 resp_addr;
847 __le32 enables;
848 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL
849 __le16 first_vf_id;
850 __le16 num_vfs;
851 };
852
853 /* Output (16 bytes) */
854 struct hwrm_func_vf_free_output {
855 __le16 error_code;
856 __le16 req_type;
857 __le16 seq_id;
858 __le16 resp_len;
859 __le32 unused_0;
860 u8 unused_1;
861 u8 unused_2;
862 u8 unused_3;
863 u8 valid;
864 };
865
866 /* hwrm_func_vf_cfg */
867 /* Input (32 bytes) */
868 struct hwrm_func_vf_cfg_input {
869 __le16 req_type;
870 __le16 cmpl_ring;
871 __le16 seq_id;
872 __le16 target_id;
873 __le64 resp_addr;
874 __le32 enables;
875 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL
876 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL
877 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL
878 __le16 mtu;
879 __le16 guest_vlan;
880 __le16 async_event_cr;
881 __le16 unused_0[3];
882 };
883
884 /* Output (16 bytes) */
885 struct hwrm_func_vf_cfg_output {
886 __le16 error_code;
887 __le16 req_type;
888 __le16 seq_id;
889 __le16 resp_len;
890 __le32 unused_0;
891 u8 unused_1;
892 u8 unused_2;
893 u8 unused_3;
894 u8 valid;
895 };
896
897 /* hwrm_func_qcaps */
898 /* Input (24 bytes) */
899 struct hwrm_func_qcaps_input {
900 __le16 req_type;
901 __le16 cmpl_ring;
902 __le16 seq_id;
903 __le16 target_id;
904 __le64 resp_addr;
905 __le16 fid;
906 __le16 unused_0[3];
907 };
908
909 /* Output (80 bytes) */
910 struct hwrm_func_qcaps_output {
911 __le16 error_code;
912 __le16 req_type;
913 __le16 seq_id;
914 __le16 resp_len;
915 __le16 fid;
916 __le16 port_id;
917 __le32 flags;
918 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL
919 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL
920 u8 perm_mac_address[6];
921 __le16 max_rsscos_ctx;
922 __le16 max_cmpl_rings;
923 __le16 max_tx_rings;
924 __le16 max_rx_rings;
925 __le16 max_l2_ctxs;
926 __le16 max_vnics;
927 __le16 first_vf_id;
928 __le16 max_vfs;
929 __le16 max_stat_ctx;
930 __le32 max_encap_records;
931 __le32 max_decap_records;
932 __le32 max_tx_em_flows;
933 __le32 max_tx_wm_flows;
934 __le32 max_rx_em_flows;
935 __le32 max_rx_wm_flows;
936 __le32 max_mcast_filters;
937 __le32 max_flow_id;
938 __le32 max_hw_ring_grps;
939 u8 unused_0;
940 u8 unused_1;
941 u8 unused_2;
942 u8 valid;
943 };
944
945 /* hwrm_func_cfg */
946 /* Input (88 bytes) */
947 struct hwrm_func_cfg_input {
948 __le16 req_type;
949 __le16 cmpl_ring;
950 __le16 seq_id;
951 __le16 target_id;
952 __le64 resp_addr;
953 __le16 fid;
954 u8 unused_0;
955 u8 unused_1;
956 __le32 flags;
957 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL
958 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL
959 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL
960 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL
961 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL
962 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL
963 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL
964 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL
965 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL
966 __le32 enables;
967 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL
968 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL
969 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL
970 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL
971 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL
972 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL
973 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL
974 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL
975 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL
976 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL
977 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL
978 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL
979 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL
980 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL
981 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL
982 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL
983 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL
984 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL
985 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL
986 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL
987 __le16 mtu;
988 __le16 mru;
989 __le16 num_rsscos_ctxs;
990 __le16 num_cmpl_rings;
991 __le16 num_tx_rings;
992 __le16 num_rx_rings;
993 __le16 num_l2_ctxs;
994 __le16 num_vnics;
995 __le16 num_stat_ctxs;
996 __le16 num_hw_ring_grps;
997 u8 dflt_mac_addr[6];
998 __le16 dflt_vlan;
999 __be32 dflt_ip_addr[4];
1000 __le32 min_bw;
1001 __le32 max_bw;
1002 __le16 async_event_cr;
1003 u8 vlan_antispoof_mode;
1004 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK (0x0UL << 0)
1005 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN (0x1UL << 0)
1006 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0)
1007 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0)
1008 u8 allowed_vlan_pris;
1009 u8 evb_mode;
1010 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB (0x0UL << 0)
1011 #define FUNC_CFG_REQ_EVB_MODE_VEB (0x1UL << 0)
1012 #define FUNC_CFG_REQ_EVB_MODE_VEPA (0x2UL << 0)
1013 u8 unused_2;
1014 __le16 num_mcast_filters;
1015 };
1016
1017 /* Output (16 bytes) */
1018 struct hwrm_func_cfg_output {
1019 __le16 error_code;
1020 __le16 req_type;
1021 __le16 seq_id;
1022 __le16 resp_len;
1023 __le32 unused_0;
1024 u8 unused_1;
1025 u8 unused_2;
1026 u8 unused_3;
1027 u8 valid;
1028 };
1029
1030 /* hwrm_func_qstats */
1031 /* Input (24 bytes) */
1032 struct hwrm_func_qstats_input {
1033 __le16 req_type;
1034 __le16 cmpl_ring;
1035 __le16 seq_id;
1036 __le16 target_id;
1037 __le64 resp_addr;
1038 __le16 fid;
1039 __le16 unused_0[3];
1040 };
1041
1042 /* Output (176 bytes) */
1043 struct hwrm_func_qstats_output {
1044 __le16 error_code;
1045 __le16 req_type;
1046 __le16 seq_id;
1047 __le16 resp_len;
1048 __le64 tx_ucast_pkts;
1049 __le64 tx_mcast_pkts;
1050 __le64 tx_bcast_pkts;
1051 __le64 tx_err_pkts;
1052 __le64 tx_drop_pkts;
1053 __le64 tx_ucast_bytes;
1054 __le64 tx_mcast_bytes;
1055 __le64 tx_bcast_bytes;
1056 __le64 rx_ucast_pkts;
1057 __le64 rx_mcast_pkts;
1058 __le64 rx_bcast_pkts;
1059 __le64 rx_err_pkts;
1060 __le64 rx_drop_pkts;
1061 __le64 rx_ucast_bytes;
1062 __le64 rx_mcast_bytes;
1063 __le64 rx_bcast_bytes;
1064 __le64 rx_agg_pkts;
1065 __le64 rx_agg_bytes;
1066 __le64 rx_agg_events;
1067 __le64 rx_agg_aborts;
1068 __le32 unused_0;
1069 u8 unused_1;
1070 u8 unused_2;
1071 u8 unused_3;
1072 u8 valid;
1073 };
1074
1075 /* hwrm_func_clr_stats */
1076 /* Input (24 bytes) */
1077 struct hwrm_func_clr_stats_input {
1078 __le16 req_type;
1079 __le16 cmpl_ring;
1080 __le16 seq_id;
1081 __le16 target_id;
1082 __le64 resp_addr;
1083 __le16 fid;
1084 __le16 unused_0[3];
1085 };
1086
1087 /* Output (16 bytes) */
1088 struct hwrm_func_clr_stats_output {
1089 __le16 error_code;
1090 __le16 req_type;
1091 __le16 seq_id;
1092 __le16 resp_len;
1093 __le32 unused_0;
1094 u8 unused_1;
1095 u8 unused_2;
1096 u8 unused_3;
1097 u8 valid;
1098 };
1099
1100 /* hwrm_func_vf_resc_free */
1101 /* Input (24 bytes) */
1102 struct hwrm_func_vf_resc_free_input {
1103 __le16 req_type;
1104 __le16 cmpl_ring;
1105 __le16 seq_id;
1106 __le16 target_id;
1107 __le64 resp_addr;
1108 __le16 vf_id;
1109 __le16 unused_0[3];
1110 };
1111
1112 /* Output (16 bytes) */
1113 struct hwrm_func_vf_resc_free_output {
1114 __le16 error_code;
1115 __le16 req_type;
1116 __le16 seq_id;
1117 __le16 resp_len;
1118 __le32 unused_0;
1119 u8 unused_1;
1120 u8 unused_2;
1121 u8 unused_3;
1122 u8 valid;
1123 };
1124
1125 /* hwrm_func_vf_vnic_ids_query */
1126 /* Input (32 bytes) */
1127 struct hwrm_func_vf_vnic_ids_query_input {
1128 __le16 req_type;
1129 __le16 cmpl_ring;
1130 __le16 seq_id;
1131 __le16 target_id;
1132 __le64 resp_addr;
1133 __le16 vf_id;
1134 u8 unused_0;
1135 u8 unused_1;
1136 __le32 max_vnic_id_cnt;
1137 __le64 vnic_id_tbl_addr;
1138 };
1139
1140 /* Output (16 bytes) */
1141 struct hwrm_func_vf_vnic_ids_query_output {
1142 __le16 error_code;
1143 __le16 req_type;
1144 __le16 seq_id;
1145 __le16 resp_len;
1146 __le32 vnic_id_cnt;
1147 u8 unused_0;
1148 u8 unused_1;
1149 u8 unused_2;
1150 u8 valid;
1151 };
1152
1153 /* hwrm_func_drv_rgtr */
1154 /* Input (80 bytes) */
1155 struct hwrm_func_drv_rgtr_input {
1156 __le16 req_type;
1157 __le16 cmpl_ring;
1158 __le16 seq_id;
1159 __le16 target_id;
1160 __le64 resp_addr;
1161 __le32 flags;
1162 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL
1163 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL
1164 __le32 enables;
1165 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL
1166 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL
1167 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL
1168 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL
1169 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL
1170 __le16 os_type;
1171 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN (0x0UL << 0)
1172 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER (0x1UL << 0)
1173 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS (0xeUL << 0)
1174 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS (0x1dUL << 0)
1175 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX (0x24UL << 0)
1176 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD (0x2aUL << 0)
1177 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI (0x68UL << 0)
1178 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 (0x73UL << 0)
1179 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 (0x74UL << 0)
1180 u8 ver_maj;
1181 u8 ver_min;
1182 u8 ver_upd;
1183 u8 unused_0;
1184 __le16 unused_1;
1185 __le32 timestamp;
1186 __le32 unused_2;
1187 __le32 vf_req_fwd[8];
1188 __le32 async_event_fwd[8];
1189 };
1190
1191 /* Output (16 bytes) */
1192 struct hwrm_func_drv_rgtr_output {
1193 __le16 error_code;
1194 __le16 req_type;
1195 __le16 seq_id;
1196 __le16 resp_len;
1197 __le32 unused_0;
1198 u8 unused_1;
1199 u8 unused_2;
1200 u8 unused_3;
1201 u8 valid;
1202 };
1203
1204 /* hwrm_func_drv_unrgtr */
1205 /* Input (24 bytes) */
1206 struct hwrm_func_drv_unrgtr_input {
1207 __le16 req_type;
1208 __le16 cmpl_ring;
1209 __le16 seq_id;
1210 __le16 target_id;
1211 __le64 resp_addr;
1212 __le32 flags;
1213 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL
1214 __le32 unused_0;
1215 };
1216
1217 /* Output (16 bytes) */
1218 struct hwrm_func_drv_unrgtr_output {
1219 __le16 error_code;
1220 __le16 req_type;
1221 __le16 seq_id;
1222 __le16 resp_len;
1223 __le32 unused_0;
1224 u8 unused_1;
1225 u8 unused_2;
1226 u8 unused_3;
1227 u8 valid;
1228 };
1229
1230 /* hwrm_func_buf_rgtr */
1231 /* Input (128 bytes) */
1232 struct hwrm_func_buf_rgtr_input {
1233 __le16 req_type;
1234 __le16 cmpl_ring;
1235 __le16 seq_id;
1236 __le16 target_id;
1237 __le64 resp_addr;
1238 __le32 enables;
1239 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL
1240 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL
1241 __le16 vf_id;
1242 __le16 req_buf_num_pages;
1243 __le16 req_buf_page_size;
1244 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B (0x4UL << 0)
1245 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K (0xcUL << 0)
1246 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K (0xdUL << 0)
1247 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K (0x10UL << 0)
1248 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M (0x16UL << 0)
1249 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M (0x17UL << 0)
1250 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G (0x1eUL << 0)
1251 __le16 req_buf_len;
1252 __le16 resp_buf_len;
1253 u8 unused_0;
1254 u8 unused_1;
1255 __le64 req_buf_page_addr0;
1256 __le64 req_buf_page_addr1;
1257 __le64 req_buf_page_addr2;
1258 __le64 req_buf_page_addr3;
1259 __le64 req_buf_page_addr4;
1260 __le64 req_buf_page_addr5;
1261 __le64 req_buf_page_addr6;
1262 __le64 req_buf_page_addr7;
1263 __le64 req_buf_page_addr8;
1264 __le64 req_buf_page_addr9;
1265 __le64 error_buf_addr;
1266 __le64 resp_buf_addr;
1267 };
1268
1269 /* Output (16 bytes) */
1270 struct hwrm_func_buf_rgtr_output {
1271 __le16 error_code;
1272 __le16 req_type;
1273 __le16 seq_id;
1274 __le16 resp_len;
1275 __le32 unused_0;
1276 u8 unused_1;
1277 u8 unused_2;
1278 u8 unused_3;
1279 u8 valid;
1280 };
1281
1282 /* hwrm_func_drv_qver */
1283 /* Input (24 bytes) */
1284 struct hwrm_func_drv_qver_input {
1285 __le16 req_type;
1286 __le16 cmpl_ring;
1287 __le16 seq_id;
1288 __le16 target_id;
1289 __le64 resp_addr;
1290 __le32 reserved;
1291 __le16 fid;
1292 __le16 unused_0;
1293 };
1294
1295 /* Output (16 bytes) */
1296 struct hwrm_func_drv_qver_output {
1297 __le16 error_code;
1298 __le16 req_type;
1299 __le16 seq_id;
1300 __le16 resp_len;
1301 __le16 os_type;
1302 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN (0x0UL << 0)
1303 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER (0x1UL << 0)
1304 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS (0xeUL << 0)
1305 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS (0x1dUL << 0)
1306 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX (0x24UL << 0)
1307 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD (0x2aUL << 0)
1308 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI (0x68UL << 0)
1309 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 (0x73UL << 0)
1310 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 (0x74UL << 0)
1311 u8 ver_maj;
1312 u8 ver_min;
1313 u8 ver_upd;
1314 u8 unused_0;
1315 u8 unused_1;
1316 u8 valid;
1317 };
1318
1319 /* hwrm_port_phy_cfg */
1320 /* Input (48 bytes) */
1321 struct hwrm_port_phy_cfg_input {
1322 __le16 req_type;
1323 __le16 cmpl_ring;
1324 __le16 seq_id;
1325 __le16 target_id;
1326 __le64 resp_addr;
1327 __le32 flags;
1328 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL
1329 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN 0x2UL
1330 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL
1331 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL
1332 __le32 enables;
1333 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL
1334 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL
1335 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL
1336 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL
1337 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL
1338 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL
1339 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL
1340 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL
1341 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL
1342 __le16 port_id;
1343 __le16 force_link_speed;
1344 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB (0x1UL << 0)
1345 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB (0xaUL << 0)
1346 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB (0x14UL << 0)
1347 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB (0x19UL << 0)
1348 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB (0x64UL << 0)
1349 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB (0xc8UL << 0)
1350 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB (0xfaUL << 0)
1351 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB (0x190UL << 0)
1352 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB (0x1f4UL << 0)
1353 u8 auto_mode;
1354 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE (0x0UL << 0)
1355 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1356 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1357 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1358 #define PORT_PHY_CFG_REQ_AUTO_MODE_MASK (0x4UL << 0)
1359 u8 auto_duplex;
1360 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF (0x0UL << 0)
1361 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL (0x1UL << 0)
1362 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH (0x2UL << 0)
1363 u8 auto_pause;
1364 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL
1365 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL
1366 u8 unused_0;
1367 __le16 auto_link_speed;
1368 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB (0x1UL << 0)
1369 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB (0xaUL << 0)
1370 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB (0x14UL << 0)
1371 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB (0x19UL << 0)
1372 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB (0x64UL << 0)
1373 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB (0xc8UL << 0)
1374 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB (0xfaUL << 0)
1375 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB (0x190UL << 0)
1376 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB (0x1f4UL << 0)
1377 __le16 auto_link_speed_mask;
1378 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1379 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1380 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1381 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1382 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1383 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1384 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1385 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1386 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1387 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1388 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1389 u8 wirespeed;
1390 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF (0x0UL << 0)
1391 #define PORT_PHY_CFG_REQ_WIRESPEED_ON (0x1UL << 0)
1392 u8 lpbk;
1393 #define PORT_PHY_CFG_REQ_LPBK_NONE (0x0UL << 0)
1394 #define PORT_PHY_CFG_REQ_LPBK_LOCAL (0x1UL << 0)
1395 #define PORT_PHY_CFG_REQ_LPBK_REMOTE (0x2UL << 0)
1396 u8 force_pause;
1397 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL
1398 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL
1399 u8 unused_1;
1400 __le32 preemphasis;
1401 __le32 unused_2;
1402 };
1403
1404 /* Output (16 bytes) */
1405 struct hwrm_port_phy_cfg_output {
1406 __le16 error_code;
1407 __le16 req_type;
1408 __le16 seq_id;
1409 __le16 resp_len;
1410 __le32 unused_0;
1411 u8 unused_1;
1412 u8 unused_2;
1413 u8 unused_3;
1414 u8 valid;
1415 };
1416
1417 /* hwrm_port_phy_qcfg */
1418 /* Input (24 bytes) */
1419 struct hwrm_port_phy_qcfg_input {
1420 __le16 req_type;
1421 __le16 cmpl_ring;
1422 __le16 seq_id;
1423 __le16 target_id;
1424 __le64 resp_addr;
1425 __le16 port_id;
1426 __le16 unused_0[3];
1427 };
1428
1429 /* Output (48 bytes) */
1430 struct hwrm_port_phy_qcfg_output {
1431 __le16 error_code;
1432 __le16 req_type;
1433 __le16 seq_id;
1434 __le16 resp_len;
1435 u8 link;
1436 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK (0x0UL << 0)
1437 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL (0x1UL << 0)
1438 #define PORT_PHY_QCFG_RESP_LINK_LINK (0x2UL << 0)
1439 u8 unused_0;
1440 __le16 link_speed;
1441 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB (0x1UL << 0)
1442 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB (0xaUL << 0)
1443 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB (0x14UL << 0)
1444 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB (0x19UL << 0)
1445 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB (0x64UL << 0)
1446 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB (0xc8UL << 0)
1447 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB (0xfaUL << 0)
1448 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB (0x190UL << 0)
1449 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB (0x1f4UL << 0)
1450 u8 duplex;
1451 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF (0x0UL << 0)
1452 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL (0x1UL << 0)
1453 u8 pause;
1454 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL
1455 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL
1456 __le16 support_speeds;
1457 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL
1458 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL
1459 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL
1460 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL
1461 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL
1462 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL
1463 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL
1464 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL
1465 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL
1466 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL
1467 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL
1468 __le16 force_link_speed;
1469 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB (0x1UL << 0)
1470 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB (0xaUL << 0)
1471 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB (0x14UL << 0)
1472 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB (0x19UL << 0)
1473 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB (0x64UL << 0)
1474 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB (0xc8UL << 0)
1475 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB (0xfaUL << 0)
1476 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB (0x190UL << 0)
1477 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB (0x1f4UL << 0)
1478 u8 auto_mode;
1479 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE (0x0UL << 0)
1480 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1481 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1482 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1483 #define PORT_PHY_QCFG_RESP_AUTO_MODE_MASK (0x4UL << 0)
1484 u8 auto_pause;
1485 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL
1486 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL
1487 __le16 auto_link_speed;
1488 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB (0x1UL << 0)
1489 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB (0xaUL << 0)
1490 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB (0x14UL << 0)
1491 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB (0x19UL << 0)
1492 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB (0x64UL << 0)
1493 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB (0xc8UL << 0)
1494 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB (0xfaUL << 0)
1495 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB (0x190UL << 0)
1496 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB (0x1f4UL << 0)
1497 __le16 auto_link_speed_mask;
1498 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL
1499 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL
1500 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL
1501 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL
1502 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL
1503 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL
1504 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL
1505 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL
1506 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL
1507 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL
1508 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL
1509 u8 wirespeed;
1510 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF (0x0UL << 0)
1511 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON (0x1UL << 0)
1512 u8 lpbk;
1513 #define PORT_PHY_QCFG_RESP_LPBK_NONE (0x0UL << 0)
1514 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL (0x1UL << 0)
1515 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE (0x2UL << 0)
1516 u8 force_pause;
1517 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL
1518 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL
1519 u8 reserved1;
1520 __le32 preemphasis;
1521 u8 phy_maj;
1522 u8 phy_min;
1523 u8 phy_bld;
1524 u8 phy_type;
1525 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR4 (0x1UL << 0)
1526 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 (0x2UL << 0)
1527 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR4 (0x3UL << 0)
1528 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR4 (0x4UL << 0)
1529 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 (0x5UL << 0)
1530 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX4 (0x6UL << 0)
1531 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR (0x7UL << 0)
1532 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET (0x8UL << 0)
1533 u8 media_type;
1534 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP (0x1UL << 0)
1535 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC (0x2UL << 0)
1536 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE (0x3UL << 0)
1537 u8 transceiver_type;
1538 #define PORT_PHY_QCFG_RESP_TRANSCEIVER_TYPE_XCVR_INTERNAL (0x1UL << 0)
1539 #define PORT_PHY_QCFG_RESP_TRANSCEIVER_TYPE_XCVR_EXTERNAL (0x2UL << 0)
1540 u8 phy_addr;
1541 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL
1542 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0
1543 u8 unused_2;
1544 __le16 link_partner_adv_speeds;
1545 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL
1546 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL
1547 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL
1548 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL
1549 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL
1550 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL
1551 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL
1552 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL
1553 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL
1554 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL
1555 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL
1556 u8 link_partner_adv_auto_mode;
1557 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE (0x0UL << 0)
1558 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS (0x1UL << 0)
1559 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED (0x2UL << 0)
1560 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0)
1561 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_MASK (0x4UL << 0)
1562 u8 link_partner_adv_pause;
1563 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL
1564 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL
1565 u8 unused_3;
1566 u8 unused_4;
1567 u8 unused_5;
1568 u8 valid;
1569 };
1570
1571 /* hwrm_port_mac_cfg */
1572 /* Input (32 bytes) */
1573 struct hwrm_port_mac_cfg_input {
1574 __le16 req_type;
1575 __le16 cmpl_ring;
1576 __le16 seq_id;
1577 __le16 target_id;
1578 __le64 resp_addr;
1579 __le32 flags;
1580 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL
1581 #define PORT_MAC_CFG_REQ_FLAGS_COS_ASSIGNMENT_ENABLE 0x2UL
1582 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL
1583 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL
1584 __le32 enables;
1585 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL
1586 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL
1587 #define PORT_MAC_CFG_REQ_ENABLES_IVLAN_PRI2COS_MAP_PRI 0x4UL
1588 #define PORT_MAC_CFG_REQ_ENABLES_LCOS_MAP_PRI 0x8UL
1589 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL
1590 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL
1591 __le16 port_id;
1592 u8 ipg;
1593 u8 lpbk;
1594 #define PORT_MAC_CFG_REQ_LPBK_NONE (0x0UL << 0)
1595 #define PORT_MAC_CFG_REQ_LPBK_LOCAL (0x1UL << 0)
1596 #define PORT_MAC_CFG_REQ_LPBK_REMOTE (0x2UL << 0)
1597 u8 ivlan_pri2cos_map_pri;
1598 u8 lcos_map_pri;
1599 u8 tunnel_pri2cos_map_pri;
1600 u8 dscp2pri_map_pri;
1601 };
1602
1603 /* Output (16 bytes) */
1604 struct hwrm_port_mac_cfg_output {
1605 __le16 error_code;
1606 __le16 req_type;
1607 __le16 seq_id;
1608 __le16 resp_len;
1609 __le16 mru;
1610 __le16 mtu;
1611 u8 ipg;
1612 u8 lpbk;
1613 #define PORT_MAC_CFG_RESP_LPBK_NONE (0x0UL << 0)
1614 #define PORT_MAC_CFG_RESP_LPBK_LOCAL (0x1UL << 0)
1615 #define PORT_MAC_CFG_RESP_LPBK_REMOTE (0x2UL << 0)
1616 u8 unused_0;
1617 u8 valid;
1618 };
1619
1620 /* hwrm_port_qstats */
1621 /* Input (40 bytes) */
1622 struct hwrm_port_qstats_input {
1623 __le16 req_type;
1624 __le16 cmpl_ring;
1625 __le16 seq_id;
1626 __le16 target_id;
1627 __le64 resp_addr;
1628 __le16 port_id;
1629 u8 unused_0;
1630 u8 unused_1;
1631 u8 unused_2[3];
1632 u8 unused_3;
1633 __le64 tx_stat_host_addr;
1634 __le64 rx_stat_host_addr;
1635 };
1636
1637 /* Output (16 bytes) */
1638 struct hwrm_port_qstats_output {
1639 __le16 error_code;
1640 __le16 req_type;
1641 __le16 seq_id;
1642 __le16 resp_len;
1643 __le16 tx_stat_size;
1644 __le16 rx_stat_size;
1645 u8 unused_0;
1646 u8 unused_1;
1647 u8 unused_2;
1648 u8 valid;
1649 };
1650
1651 /* hwrm_port_lpbk_qstats */
1652 /* Input (16 bytes) */
1653 struct hwrm_port_lpbk_qstats_input {
1654 __le16 req_type;
1655 __le16 cmpl_ring;
1656 __le16 seq_id;
1657 __le16 target_id;
1658 __le64 resp_addr;
1659 };
1660
1661 /* Output (96 bytes) */
1662 struct hwrm_port_lpbk_qstats_output {
1663 __le16 error_code;
1664 __le16 req_type;
1665 __le16 seq_id;
1666 __le16 resp_len;
1667 __le64 lpbk_ucast_frames;
1668 __le64 lpbk_mcast_frames;
1669 __le64 lpbk_bcast_frames;
1670 __le64 lpbk_ucast_bytes;
1671 __le64 lpbk_mcast_bytes;
1672 __le64 lpbk_bcast_bytes;
1673 __le64 tx_stat_discard;
1674 __le64 tx_stat_error;
1675 __le64 rx_stat_discard;
1676 __le64 rx_stat_error;
1677 __le32 unused_0;
1678 u8 unused_1;
1679 u8 unused_2;
1680 u8 unused_3;
1681 u8 valid;
1682 };
1683
1684 /* hwrm_port_clr_stats */
1685 /* Input (24 bytes) */
1686 struct hwrm_port_clr_stats_input {
1687 __le16 req_type;
1688 __le16 cmpl_ring;
1689 __le16 seq_id;
1690 __le16 target_id;
1691 __le64 resp_addr;
1692 __le16 port_id;
1693 __le16 unused_0[3];
1694 };
1695
1696 /* Output (16 bytes) */
1697 struct hwrm_port_clr_stats_output {
1698 __le16 error_code;
1699 __le16 req_type;
1700 __le16 seq_id;
1701 __le16 resp_len;
1702 __le32 unused_0;
1703 u8 unused_1;
1704 u8 unused_2;
1705 u8 unused_3;
1706 u8 valid;
1707 };
1708
1709 /* hwrm_port_lpbk_clr_stats */
1710 /* Input (16 bytes) */
1711 struct hwrm_port_lpbk_clr_stats_input {
1712 __le16 req_type;
1713 __le16 cmpl_ring;
1714 __le16 seq_id;
1715 __le16 target_id;
1716 __le64 resp_addr;
1717 };
1718
1719 /* Output (16 bytes) */
1720 struct hwrm_port_lpbk_clr_stats_output {
1721 __le16 error_code;
1722 __le16 req_type;
1723 __le16 seq_id;
1724 __le16 resp_len;
1725 __le32 unused_0;
1726 u8 unused_1;
1727 u8 unused_2;
1728 u8 unused_3;
1729 u8 valid;
1730 };
1731
1732 /* hwrm_port_blink_led */
1733 /* Input (24 bytes) */
1734 struct hwrm_port_blink_led_input {
1735 __le16 req_type;
1736 __le16 cmpl_ring;
1737 __le16 seq_id;
1738 __le16 target_id;
1739 __le64 resp_addr;
1740 __le32 num_blinks;
1741 __le32 unused_0;
1742 };
1743
1744 /* Output (16 bytes) */
1745 struct hwrm_port_blink_led_output {
1746 __le16 error_code;
1747 __le16 req_type;
1748 __le16 seq_id;
1749 __le16 resp_len;
1750 __le32 unused_0;
1751 u8 unused_1;
1752 u8 unused_2;
1753 u8 unused_3;
1754 u8 valid;
1755 };
1756
1757 /* hwrm_queue_qportcfg */
1758 /* Input (24 bytes) */
1759 struct hwrm_queue_qportcfg_input {
1760 __le16 req_type;
1761 __le16 cmpl_ring;
1762 __le16 seq_id;
1763 __le16 target_id;
1764 __le64 resp_addr;
1765 __le32 flags;
1766 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL
1767 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
1768 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
1769 __le16 port_id;
1770 __le16 unused_0;
1771 };
1772
1773 /* Output (32 bytes) */
1774 struct hwrm_queue_qportcfg_output {
1775 __le16 error_code;
1776 __le16 req_type;
1777 __le16 seq_id;
1778 __le16 resp_len;
1779 u8 max_configurable_queues;
1780 u8 max_configurable_lossless_queues;
1781 u8 queue_cfg_allowed;
1782 u8 queue_buffers_cfg_allowed;
1783 u8 queue_pfcenable_cfg_allowed;
1784 u8 queue_pri2cos_cfg_allowed;
1785 u8 queue_cos2bw_cfg_allowed;
1786 u8 queue_id0;
1787 u8 queue_id0_service_profile;
1788 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1789 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1790 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1791 u8 queue_id1;
1792 u8 queue_id1_service_profile;
1793 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1794 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1795 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1796 u8 queue_id2;
1797 u8 queue_id2_service_profile;
1798 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1799 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1800 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1801 u8 queue_id3;
1802 u8 queue_id3_service_profile;
1803 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1804 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1805 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1806 u8 queue_id4;
1807 u8 queue_id4_service_profile;
1808 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1809 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1810 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1811 u8 queue_id5;
1812 u8 queue_id5_service_profile;
1813 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1814 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1815 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1816 u8 queue_id6;
1817 u8 queue_id6_service_profile;
1818 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1819 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1820 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1821 u8 queue_id7;
1822 u8 queue_id7_service_profile;
1823 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1824 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1825 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1826 u8 valid;
1827 };
1828
1829 /* hwrm_queue_cfg */
1830 /* Input (40 bytes) */
1831 struct hwrm_queue_cfg_input {
1832 __le16 req_type;
1833 __le16 cmpl_ring;
1834 __le16 seq_id;
1835 __le16 target_id;
1836 __le64 resp_addr;
1837 __le32 flags;
1838 #define QUEUE_CFG_REQ_FLAGS_PATH 0x1UL
1839 #define QUEUE_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
1840 #define QUEUE_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
1841 __le32 enables;
1842 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL
1843 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL
1844 __le32 queue_id;
1845 __le32 dflt_len;
1846 u8 service_profile;
1847 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY (0x0UL << 0)
1848 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS (0x1UL << 0)
1849 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN (0xffUL << 0)
1850 u8 unused_0[7];
1851 };
1852
1853 /* Output (16 bytes) */
1854 struct hwrm_queue_cfg_output {
1855 __le16 error_code;
1856 __le16 req_type;
1857 __le16 seq_id;
1858 __le16 resp_len;
1859 __le32 unused_0;
1860 u8 unused_1;
1861 u8 unused_2;
1862 u8 unused_3;
1863 u8 valid;
1864 };
1865
1866 /* hwrm_queue_buffers_cfg */
1867 /* Input (56 bytes) */
1868 struct hwrm_queue_buffers_cfg_input {
1869 __le16 req_type;
1870 __le16 cmpl_ring;
1871 __le16 seq_id;
1872 __le16 target_id;
1873 __le64 resp_addr;
1874 __le32 flags;
1875 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH 0x1UL
1876 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
1877 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
1878 __le32 enables;
1879 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED 0x1UL
1880 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED 0x2UL
1881 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x4UL
1882 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x8UL
1883 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x10UL
1884 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x20UL
1885 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x40UL
1886 __le32 queue_id;
1887 __le32 reserved;
1888 __le32 shared;
1889 __le32 xoff;
1890 __le32 xon;
1891 __le32 full;
1892 __le32 notfull;
1893 __le32 max;
1894 };
1895
1896 /* Output (16 bytes) */
1897 struct hwrm_queue_buffers_cfg_output {
1898 __le16 error_code;
1899 __le16 req_type;
1900 __le16 seq_id;
1901 __le16 resp_len;
1902 __le32 unused_0;
1903 u8 unused_1;
1904 u8 unused_2;
1905 u8 unused_3;
1906 u8 valid;
1907 };
1908
1909 /* hwrm_queue_pfcenable_cfg */
1910 /* Input (24 bytes) */
1911 struct hwrm_queue_pfcenable_cfg_input {
1912 __le16 req_type;
1913 __le16 cmpl_ring;
1914 __le16 seq_id;
1915 __le16 target_id;
1916 __le64 resp_addr;
1917 __le32 flags;
1918 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL
1919 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL
1920 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL
1921 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL
1922 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL
1923 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL
1924 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL
1925 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL
1926 __le16 port_id;
1927 __le16 unused_0;
1928 };
1929
1930 /* Output (16 bytes) */
1931 struct hwrm_queue_pfcenable_cfg_output {
1932 __le16 error_code;
1933 __le16 req_type;
1934 __le16 seq_id;
1935 __le16 resp_len;
1936 __le32 unused_0;
1937 u8 unused_1;
1938 u8 unused_2;
1939 u8 unused_3;
1940 u8 valid;
1941 };
1942
1943 /* hwrm_queue_pri2cos_cfg */
1944 /* Input (40 bytes) */
1945 struct hwrm_queue_pri2cos_cfg_input {
1946 __le16 req_type;
1947 __le16 cmpl_ring;
1948 __le16 seq_id;
1949 __le16 target_id;
1950 __le64 resp_addr;
1951 __le32 flags;
1952 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH 0x1UL
1953 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
1954 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
1955 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x2UL
1956 __le32 enables;
1957 u8 port_id;
1958 u8 pri0_cos_queue_id;
1959 u8 pri1_cos_queue_id;
1960 u8 pri2_cos_queue_id;
1961 u8 pri3_cos_queue_id;
1962 u8 pri4_cos_queue_id;
1963 u8 pri5_cos_queue_id;
1964 u8 pri6_cos_queue_id;
1965 u8 pri7_cos_queue_id;
1966 u8 unused_0[7];
1967 };
1968
1969 /* Output (16 bytes) */
1970 struct hwrm_queue_pri2cos_cfg_output {
1971 __le16 error_code;
1972 __le16 req_type;
1973 __le16 seq_id;
1974 __le16 resp_len;
1975 __le32 unused_0;
1976 u8 unused_1;
1977 u8 unused_2;
1978 u8 unused_3;
1979 u8 valid;
1980 };
1981
1982 /* hwrm_queue_cos2bw_cfg */
1983 /* Input (128 bytes) */
1984 struct hwrm_queue_cos2bw_cfg_input {
1985 __le16 req_type;
1986 __le16 cmpl_ring;
1987 __le16 seq_id;
1988 __le16 target_id;
1989 __le64 resp_addr;
1990 __le32 flags;
1991 __le32 enables;
1992 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL
1993 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL
1994 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL
1995 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL
1996 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL
1997 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL
1998 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL
1999 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL
2000 __le16 port_id;
2001 u8 queue_id0;
2002 u8 unused_0;
2003 __le32 queue_id0_min_bw;
2004 __le32 queue_id0_max_bw;
2005 u8 queue_id0_tsa_assign;
2006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP (0x0UL << 0)
2007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS (0x1UL << 0)
2008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2010 u8 queue_id0_pri_lvl;
2011 u8 queue_id0_bw_weight;
2012 u8 queue_id1;
2013 __le32 queue_id1_min_bw;
2014 __le32 queue_id1_max_bw;
2015 u8 queue_id1_tsa_assign;
2016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP (0x0UL << 0)
2017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS (0x1UL << 0)
2018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2020 u8 queue_id1_pri_lvl;
2021 u8 queue_id1_bw_weight;
2022 u8 queue_id2;
2023 __le32 queue_id2_min_bw;
2024 __le32 queue_id2_max_bw;
2025 u8 queue_id2_tsa_assign;
2026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP (0x0UL << 0)
2027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS (0x1UL << 0)
2028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2030 u8 queue_id2_pri_lvl;
2031 u8 queue_id2_bw_weight;
2032 u8 queue_id3;
2033 __le32 queue_id3_min_bw;
2034 __le32 queue_id3_max_bw;
2035 u8 queue_id3_tsa_assign;
2036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP (0x0UL << 0)
2037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS (0x1UL << 0)
2038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2040 u8 queue_id3_pri_lvl;
2041 u8 queue_id3_bw_weight;
2042 u8 queue_id4;
2043 __le32 queue_id4_min_bw;
2044 __le32 queue_id4_max_bw;
2045 u8 queue_id4_tsa_assign;
2046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP (0x0UL << 0)
2047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS (0x1UL << 0)
2048 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2050 u8 queue_id4_pri_lvl;
2051 u8 queue_id4_bw_weight;
2052 u8 queue_id5;
2053 __le32 queue_id5_min_bw;
2054 __le32 queue_id5_max_bw;
2055 u8 queue_id5_tsa_assign;
2056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP (0x0UL << 0)
2057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS (0x1UL << 0)
2058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2060 u8 queue_id5_pri_lvl;
2061 u8 queue_id5_bw_weight;
2062 u8 queue_id6;
2063 __le32 queue_id6_min_bw;
2064 __le32 queue_id6_max_bw;
2065 u8 queue_id6_tsa_assign;
2066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP (0x0UL << 0)
2067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS (0x1UL << 0)
2068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2070 u8 queue_id6_pri_lvl;
2071 u8 queue_id6_bw_weight;
2072 u8 queue_id7;
2073 __le32 queue_id7_min_bw;
2074 __le32 queue_id7_max_bw;
2075 u8 queue_id7_tsa_assign;
2076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP (0x0UL << 0)
2077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS (0x1UL << 0)
2078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0)
2079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0)
2080 u8 queue_id7_pri_lvl;
2081 u8 queue_id7_bw_weight;
2082 u8 unused_1[5];
2083 };
2084
2085 /* Output (16 bytes) */
2086 struct hwrm_queue_cos2bw_cfg_output {
2087 __le16 error_code;
2088 __le16 req_type;
2089 __le16 seq_id;
2090 __le16 resp_len;
2091 __le32 unused_0;
2092 u8 unused_1;
2093 u8 unused_2;
2094 u8 unused_3;
2095 u8 valid;
2096 };
2097
2098 /* hwrm_vnic_alloc */
2099 /* Input (24 bytes) */
2100 struct hwrm_vnic_alloc_input {
2101 __le16 req_type;
2102 __le16 cmpl_ring;
2103 __le16 seq_id;
2104 __le16 target_id;
2105 __le64 resp_addr;
2106 __le32 flags;
2107 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL
2108 __le32 unused_0;
2109 };
2110
2111 /* Output (16 bytes) */
2112 struct hwrm_vnic_alloc_output {
2113 __le16 error_code;
2114 __le16 req_type;
2115 __le16 seq_id;
2116 __le16 resp_len;
2117 __le32 vnic_id;
2118 u8 unused_0;
2119 u8 unused_1;
2120 u8 unused_2;
2121 u8 valid;
2122 };
2123
2124 /* hwrm_vnic_free */
2125 /* Input (24 bytes) */
2126 struct hwrm_vnic_free_input {
2127 __le16 req_type;
2128 __le16 cmpl_ring;
2129 __le16 seq_id;
2130 __le16 target_id;
2131 __le64 resp_addr;
2132 __le32 vnic_id;
2133 __le32 unused_0;
2134 };
2135
2136 /* Output (16 bytes) */
2137 struct hwrm_vnic_free_output {
2138 __le16 error_code;
2139 __le16 req_type;
2140 __le16 seq_id;
2141 __le16 resp_len;
2142 __le32 unused_0;
2143 u8 unused_1;
2144 u8 unused_2;
2145 u8 unused_3;
2146 u8 valid;
2147 };
2148
2149 /* hwrm_vnic_cfg */
2150 /* Input (40 bytes) */
2151 struct hwrm_vnic_cfg_input {
2152 __le16 req_type;
2153 __le16 cmpl_ring;
2154 __le16 seq_id;
2155 __le16 target_id;
2156 __le64 resp_addr;
2157 __le32 flags;
2158 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL
2159 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL
2160 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL
2161 __le32 enables;
2162 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL
2163 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL
2164 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL
2165 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL
2166 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL
2167 __le16 vnic_id;
2168 __le16 dflt_ring_grp;
2169 __le16 rss_rule;
2170 __le16 cos_rule;
2171 __le16 lb_rule;
2172 __le16 mru;
2173 __le32 unused_0;
2174 };
2175
2176 /* Output (16 bytes) */
2177 struct hwrm_vnic_cfg_output {
2178 __le16 error_code;
2179 __le16 req_type;
2180 __le16 seq_id;
2181 __le16 resp_len;
2182 __le32 unused_0;
2183 u8 unused_1;
2184 u8 unused_2;
2185 u8 unused_3;
2186 u8 valid;
2187 };
2188
2189 /* hwrm_vnic_tpa_cfg */
2190 /* Input (40 bytes) */
2191 struct hwrm_vnic_tpa_cfg_input {
2192 __le16 req_type;
2193 __le16 cmpl_ring;
2194 __le16 seq_id;
2195 __le16 target_id;
2196 __le64 resp_addr;
2197 __le32 flags;
2198 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL
2199 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL
2200 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL
2201 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL
2202 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL
2203 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL
2204 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL
2205 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL
2206 __le32 enables;
2207 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL
2208 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL
2209 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL
2210 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL
2211 __le16 vnic_id;
2212 __le16 max_agg_segs;
2213 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 (0x0UL << 0)
2214 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 (0x1UL << 0)
2215 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 (0x2UL << 0)
2216 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 (0x3UL << 0)
2217 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX (0x1fUL << 0)
2218 __le16 max_aggs;
2219 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 (0x0UL << 0)
2220 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 (0x1UL << 0)
2221 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 (0x2UL << 0)
2222 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 (0x3UL << 0)
2223 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 (0x4UL << 0)
2224 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX (0x7UL << 0)
2225 u8 unused_0;
2226 u8 unused_1;
2227 __le32 max_agg_timer;
2228 __le32 min_agg_len;
2229 };
2230
2231 /* Output (16 bytes) */
2232 struct hwrm_vnic_tpa_cfg_output {
2233 __le16 error_code;
2234 __le16 req_type;
2235 __le16 seq_id;
2236 __le16 resp_len;
2237 __le32 unused_0;
2238 u8 unused_1;
2239 u8 unused_2;
2240 u8 unused_3;
2241 u8 valid;
2242 };
2243
2244 /* hwrm_vnic_rss_cfg */
2245 /* Input (48 bytes) */
2246 struct hwrm_vnic_rss_cfg_input {
2247 __le16 req_type;
2248 __le16 cmpl_ring;
2249 __le16 seq_id;
2250 __le16 target_id;
2251 __le64 resp_addr;
2252 __le32 hash_type;
2253 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL
2254 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL
2255 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL
2256 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL
2257 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL
2258 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL
2259 __le32 unused_0;
2260 __le64 ring_grp_tbl_addr;
2261 __le64 hash_key_tbl_addr;
2262 __le16 rss_ctx_idx;
2263 __le16 unused_1[3];
2264 };
2265
2266 /* Output (16 bytes) */
2267 struct hwrm_vnic_rss_cfg_output {
2268 __le16 error_code;
2269 __le16 req_type;
2270 __le16 seq_id;
2271 __le16 resp_len;
2272 __le32 unused_0;
2273 u8 unused_1;
2274 u8 unused_2;
2275 u8 unused_3;
2276 u8 valid;
2277 };
2278
2279 /* hwrm_vnic_plcmodes_cfg */
2280 /* Input (40 bytes) */
2281 struct hwrm_vnic_plcmodes_cfg_input {
2282 __le16 req_type;
2283 __le16 cmpl_ring;
2284 __le16 seq_id;
2285 __le16 target_id;
2286 __le64 resp_addr;
2287 __le32 flags;
2288 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL
2289 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL
2290 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL
2291 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL
2292 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL
2293 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL
2294 __le32 enables;
2295 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL
2296 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL
2297 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL
2298 __le32 vnic_id;
2299 __le16 jumbo_thresh;
2300 __le16 hds_offset;
2301 __le16 hds_threshold;
2302 __le16 unused_0[3];
2303 };
2304
2305 /* Output (16 bytes) */
2306 struct hwrm_vnic_plcmodes_cfg_output {
2307 __le16 error_code;
2308 __le16 req_type;
2309 __le16 seq_id;
2310 __le16 resp_len;
2311 __le32 unused_0;
2312 u8 unused_1;
2313 u8 unused_2;
2314 u8 unused_3;
2315 u8 valid;
2316 };
2317
2318 /* hwrm_vnic_rss_cos_lb_ctx_alloc */
2319 /* Input (16 bytes) */
2320 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
2321 __le16 req_type;
2322 __le16 cmpl_ring;
2323 __le16 seq_id;
2324 __le16 target_id;
2325 __le64 resp_addr;
2326 };
2327
2328 /* Output (16 bytes) */
2329 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output {
2330 __le16 error_code;
2331 __le16 req_type;
2332 __le16 seq_id;
2333 __le16 resp_len;
2334 __le16 rss_cos_lb_ctx_id;
2335 u8 unused_0;
2336 u8 unused_1;
2337 u8 unused_2;
2338 u8 unused_3;
2339 u8 unused_4;
2340 u8 valid;
2341 };
2342
2343 /* hwrm_vnic_rss_cos_lb_ctx_free */
2344 /* Input (24 bytes) */
2345 struct hwrm_vnic_rss_cos_lb_ctx_free_input {
2346 __le16 req_type;
2347 __le16 cmpl_ring;
2348 __le16 seq_id;
2349 __le16 target_id;
2350 __le64 resp_addr;
2351 __le16 rss_cos_lb_ctx_id;
2352 __le16 unused_0[3];
2353 };
2354
2355 /* Output (16 bytes) */
2356 struct hwrm_vnic_rss_cos_lb_ctx_free_output {
2357 __le16 error_code;
2358 __le16 req_type;
2359 __le16 seq_id;
2360 __le16 resp_len;
2361 __le32 unused_0;
2362 u8 unused_1;
2363 u8 unused_2;
2364 u8 unused_3;
2365 u8 valid;
2366 };
2367
2368 /* hwrm_ring_alloc */
2369 /* Input (80 bytes) */
2370 struct hwrm_ring_alloc_input {
2371 __le16 req_type;
2372 __le16 cmpl_ring;
2373 __le16 seq_id;
2374 __le16 target_id;
2375 __le64 resp_addr;
2376 __le32 enables;
2377 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL
2378 #define RING_ALLOC_REQ_ENABLES_RESERVED2 0x2UL
2379 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL
2380 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL
2381 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL
2382 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL
2383 u8 ring_type;
2384 #define RING_ALLOC_REQ_RING_TYPE_CMPL (0x0UL << 0)
2385 #define RING_ALLOC_REQ_RING_TYPE_TX (0x1UL << 0)
2386 #define RING_ALLOC_REQ_RING_TYPE_RX (0x2UL << 0)
2387 u8 unused_0;
2388 __le16 unused_1;
2389 __le64 page_tbl_addr;
2390 __le32 fbo;
2391 u8 page_size;
2392 u8 page_tbl_depth;
2393 u8 unused_2;
2394 u8 unused_3;
2395 __le32 length;
2396 __le16 logical_id;
2397 __le16 cmpl_ring_id;
2398 __le16 queue_id;
2399 u8 unused_4;
2400 u8 unused_5;
2401 __le32 reserved1;
2402 __le16 reserved2;
2403 u8 unused_6;
2404 u8 unused_7;
2405 __le32 reserved3;
2406 __le32 stat_ctx_id;
2407 __le32 reserved4;
2408 __le32 max_bw;
2409 u8 int_mode;
2410 #define RING_ALLOC_REQ_INT_MODE_LEGACY (0x0UL << 0)
2411 #define RING_ALLOC_REQ_INT_MODE_RSVD (0x1UL << 0)
2412 #define RING_ALLOC_REQ_INT_MODE_MSIX (0x2UL << 0)
2413 #define RING_ALLOC_REQ_INT_MODE_POLL (0x3UL << 0)
2414 u8 unused_8[3];
2415 };
2416
2417 /* Output (16 bytes) */
2418 struct hwrm_ring_alloc_output {
2419 __le16 error_code;
2420 __le16 req_type;
2421 __le16 seq_id;
2422 __le16 resp_len;
2423 __le16 ring_id;
2424 __le16 logical_ring_id;
2425 u8 unused_0;
2426 u8 unused_1;
2427 u8 unused_2;
2428 u8 valid;
2429 };
2430
2431 /* hwrm_ring_free */
2432 /* Input (24 bytes) */
2433 struct hwrm_ring_free_input {
2434 __le16 req_type;
2435 __le16 cmpl_ring;
2436 __le16 seq_id;
2437 __le16 target_id;
2438 __le64 resp_addr;
2439 u8 ring_type;
2440 #define RING_FREE_REQ_RING_TYPE_CMPL (0x0UL << 0)
2441 #define RING_FREE_REQ_RING_TYPE_TX (0x1UL << 0)
2442 #define RING_FREE_REQ_RING_TYPE_RX (0x2UL << 0)
2443 u8 unused_0;
2444 __le16 ring_id;
2445 __le32 unused_1;
2446 };
2447
2448 /* Output (16 bytes) */
2449 struct hwrm_ring_free_output {
2450 __le16 error_code;
2451 __le16 req_type;
2452 __le16 seq_id;
2453 __le16 resp_len;
2454 __le32 unused_0;
2455 u8 unused_1;
2456 u8 unused_2;
2457 u8 unused_3;
2458 u8 valid;
2459 };
2460
2461 /* hwrm_ring_cmpl_ring_qaggint_params */
2462 /* Input (24 bytes) */
2463 struct hwrm_ring_cmpl_ring_qaggint_params_input {
2464 __le16 req_type;
2465 __le16 cmpl_ring;
2466 __le16 seq_id;
2467 __le16 target_id;
2468 __le64 resp_addr;
2469 __le16 ring_id;
2470 __le16 unused_0[3];
2471 };
2472
2473 /* Output (32 bytes) */
2474 struct hwrm_ring_cmpl_ring_qaggint_params_output {
2475 __le16 error_code;
2476 __le16 req_type;
2477 __le16 seq_id;
2478 __le16 resp_len;
2479 __le16 flags;
2480 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL
2481 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL
2482 __le16 num_cmpl_dma_aggr;
2483 __le16 num_cmpl_dma_aggr_during_int;
2484 __le16 cmpl_aggr_dma_tmr;
2485 __le16 cmpl_aggr_dma_tmr_during_int;
2486 __le16 int_lat_tmr_min;
2487 __le16 int_lat_tmr_max;
2488 __le16 num_cmpl_aggr_int;
2489 __le32 unused_0;
2490 u8 unused_1;
2491 u8 unused_2;
2492 u8 unused_3;
2493 u8 valid;
2494 };
2495
2496 /* hwrm_ring_cmpl_ring_cfg_aggint_params */
2497 /* Input (40 bytes) */
2498 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
2499 __le16 req_type;
2500 __le16 cmpl_ring;
2501 __le16 seq_id;
2502 __le16 target_id;
2503 __le64 resp_addr;
2504 __le16 ring_id;
2505 __le16 flags;
2506 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL
2507 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL
2508 __le16 num_cmpl_dma_aggr;
2509 __le16 num_cmpl_dma_aggr_during_int;
2510 __le16 cmpl_aggr_dma_tmr;
2511 __le16 cmpl_aggr_dma_tmr_during_int;
2512 __le16 int_lat_tmr_min;
2513 __le16 int_lat_tmr_max;
2514 __le16 num_cmpl_aggr_int;
2515 __le16 unused_0[3];
2516 };
2517
2518 /* Output (16 bytes) */
2519 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output {
2520 __le16 error_code;
2521 __le16 req_type;
2522 __le16 seq_id;
2523 __le16 resp_len;
2524 __le32 unused_0;
2525 u8 unused_1;
2526 u8 unused_2;
2527 u8 unused_3;
2528 u8 valid;
2529 };
2530
2531 /* hwrm_ring_reset */
2532 /* Input (24 bytes) */
2533 struct hwrm_ring_reset_input {
2534 __le16 req_type;
2535 __le16 cmpl_ring;
2536 __le16 seq_id;
2537 __le16 target_id;
2538 __le64 resp_addr;
2539 u8 ring_type;
2540 #define RING_RESET_REQ_RING_TYPE_CMPL (0x0UL << 0)
2541 #define RING_RESET_REQ_RING_TYPE_TX (0x1UL << 0)
2542 #define RING_RESET_REQ_RING_TYPE_RX (0x2UL << 0)
2543 u8 unused_0;
2544 __le16 ring_id;
2545 __le32 unused_1;
2546 };
2547
2548 /* Output (16 bytes) */
2549 struct hwrm_ring_reset_output {
2550 __le16 error_code;
2551 __le16 req_type;
2552 __le16 seq_id;
2553 __le16 resp_len;
2554 __le32 unused_0;
2555 u8 unused_1;
2556 u8 unused_2;
2557 u8 unused_3;
2558 u8 valid;
2559 };
2560
2561 /* hwrm_ring_grp_alloc */
2562 /* Input (24 bytes) */
2563 struct hwrm_ring_grp_alloc_input {
2564 __le16 req_type;
2565 __le16 cmpl_ring;
2566 __le16 seq_id;
2567 __le16 target_id;
2568 __le64 resp_addr;
2569 __le16 cr;
2570 __le16 rr;
2571 __le16 ar;
2572 __le16 sc;
2573 };
2574
2575 /* Output (16 bytes) */
2576 struct hwrm_ring_grp_alloc_output {
2577 __le16 error_code;
2578 __le16 req_type;
2579 __le16 seq_id;
2580 __le16 resp_len;
2581 __le32 ring_group_id;
2582 u8 unused_0;
2583 u8 unused_1;
2584 u8 unused_2;
2585 u8 valid;
2586 };
2587
2588 /* hwrm_ring_grp_free */
2589 /* Input (24 bytes) */
2590 struct hwrm_ring_grp_free_input {
2591 __le16 req_type;
2592 __le16 cmpl_ring;
2593 __le16 seq_id;
2594 __le16 target_id;
2595 __le64 resp_addr;
2596 __le32 ring_group_id;
2597 __le32 unused_0;
2598 };
2599
2600 /* Output (16 bytes) */
2601 struct hwrm_ring_grp_free_output {
2602 __le16 error_code;
2603 __le16 req_type;
2604 __le16 seq_id;
2605 __le16 resp_len;
2606 __le32 unused_0;
2607 u8 unused_1;
2608 u8 unused_2;
2609 u8 unused_3;
2610 u8 valid;
2611 };
2612
2613 /* hwrm_cfa_l2_filter_alloc */
2614 /* Input (96 bytes) */
2615 struct hwrm_cfa_l2_filter_alloc_input {
2616 __le16 req_type;
2617 __le16 cmpl_ring;
2618 __le16 seq_id;
2619 __le16 target_id;
2620 __le64 resp_addr;
2621 __le32 flags;
2622 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL
2623 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0)
2624 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0)
2625 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL
2626 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL
2627 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL
2628 __le32 enables;
2629 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL
2630 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL
2631 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL
2632 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL
2633 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL
2634 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL
2635 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL
2636 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL
2637 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL
2638 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL
2639 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL
2640 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL
2641 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL
2642 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL
2643 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL
2644 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL
2645 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL
2646 u8 l2_addr[6];
2647 u8 unused_0;
2648 u8 unused_1;
2649 u8 l2_addr_mask[6];
2650 __le16 l2_ovlan;
2651 __le16 l2_ovlan_mask;
2652 __le16 l2_ivlan;
2653 __le16 l2_ivlan_mask;
2654 u8 unused_2;
2655 u8 unused_3;
2656 u8 t_l2_addr[6];
2657 u8 unused_4;
2658 u8 unused_5;
2659 u8 t_l2_addr_mask[6];
2660 __le16 t_l2_ovlan;
2661 __le16 t_l2_ovlan_mask;
2662 __le16 t_l2_ivlan;
2663 __le16 t_l2_ivlan_mask;
2664 u8 src_type;
2665 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT (0x0UL << 0)
2666 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF (0x1UL << 0)
2667 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF (0x2UL << 0)
2668 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC (0x3UL << 0)
2669 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG (0x4UL << 0)
2670 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE (0x5UL << 0)
2671 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO (0x6UL << 0)
2672 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG (0x7UL << 0)
2673 u8 unused_6;
2674 __le32 src_id;
2675 u8 tunnel_type;
2676 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
2677 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
2678 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
2679 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
2680 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
2681 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
2682 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
2683 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
2684 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
2685 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
2686 u8 unused_7;
2687 __le16 dst_id;
2688 __le16 mirror_vnic_id;
2689 u8 pri_hint;
2690 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0)
2691 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER (0x1UL << 0)
2692 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER (0x2UL << 0)
2693 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX (0x3UL << 0)
2694 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN (0x4UL << 0)
2695 u8 unused_8;
2696 __le32 unused_9;
2697 __le64 l2_filter_id_hint;
2698 };
2699
2700 /* Output (24 bytes) */
2701 struct hwrm_cfa_l2_filter_alloc_output {
2702 __le16 error_code;
2703 __le16 req_type;
2704 __le16 seq_id;
2705 __le16 resp_len;
2706 __le64 l2_filter_id;
2707 __le32 flow_id;
2708 u8 unused_0;
2709 u8 unused_1;
2710 u8 unused_2;
2711 u8 valid;
2712 };
2713
2714 /* hwrm_cfa_l2_filter_free */
2715 /* Input (24 bytes) */
2716 struct hwrm_cfa_l2_filter_free_input {
2717 __le16 req_type;
2718 __le16 cmpl_ring;
2719 __le16 seq_id;
2720 __le16 target_id;
2721 __le64 resp_addr;
2722 __le64 l2_filter_id;
2723 };
2724
2725 /* Output (16 bytes) */
2726 struct hwrm_cfa_l2_filter_free_output {
2727 __le16 error_code;
2728 __le16 req_type;
2729 __le16 seq_id;
2730 __le16 resp_len;
2731 __le32 unused_0;
2732 u8 unused_1;
2733 u8 unused_2;
2734 u8 unused_3;
2735 u8 valid;
2736 };
2737
2738 /* hwrm_cfa_l2_filter_cfg */
2739 /* Input (40 bytes) */
2740 struct hwrm_cfa_l2_filter_cfg_input {
2741 __le16 req_type;
2742 __le16 cmpl_ring;
2743 __le16 seq_id;
2744 __le16 target_id;
2745 __le64 resp_addr;
2746 __le32 flags;
2747 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL
2748 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0)
2749 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0)
2750 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL
2751 __le32 enables;
2752 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL
2753 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
2754 __le64 l2_filter_id;
2755 __le32 dst_id;
2756 __le32 new_mirror_vnic_id;
2757 };
2758
2759 /* Output (16 bytes) */
2760 struct hwrm_cfa_l2_filter_cfg_output {
2761 __le16 error_code;
2762 __le16 req_type;
2763 __le16 seq_id;
2764 __le16 resp_len;
2765 __le32 unused_0;
2766 u8 unused_1;
2767 u8 unused_2;
2768 u8 unused_3;
2769 u8 valid;
2770 };
2771
2772 /* hwrm_cfa_l2_set_rx_mask */
2773 /* Input (40 bytes) */
2774 struct hwrm_cfa_l2_set_rx_mask_input {
2775 __le16 req_type;
2776 __le16 cmpl_ring;
2777 __le16 seq_id;
2778 __le16 target_id;
2779 __le64 resp_addr;
2780 __le32 vnic_id;
2781 __le32 mask;
2782 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL
2783 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL
2784 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL
2785 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL
2786 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL
2787 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL
2788 __le64 mc_tbl_addr;
2789 __le32 num_mc_entries;
2790 __le32 unused_0;
2791 };
2792
2793 /* Output (16 bytes) */
2794 struct hwrm_cfa_l2_set_rx_mask_output {
2795 __le16 error_code;
2796 __le16 req_type;
2797 __le16 seq_id;
2798 __le16 resp_len;
2799 __le32 unused_0;
2800 u8 unused_1;
2801 u8 unused_2;
2802 u8 unused_3;
2803 u8 valid;
2804 };
2805
2806 /* hwrm_cfa_tunnel_filter_alloc */
2807 /* Input (88 bytes) */
2808 struct hwrm_cfa_tunnel_filter_alloc_input {
2809 __le16 req_type;
2810 __le16 cmpl_ring;
2811 __le16 seq_id;
2812 __le16 target_id;
2813 __le64 resp_addr;
2814 __le32 flags;
2815 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
2816 __le32 enables;
2817 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
2818 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL
2819 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL
2820 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL
2821 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL
2822 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL
2823 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL
2824 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL
2825 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL
2826 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL
2827 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL
2828 __le64 l2_filter_id;
2829 u8 l2_addr[6];
2830 __le16 l2_ivlan;
2831 __le32 l3_addr[4];
2832 __le32 t_l3_addr[4];
2833 u8 l3_addr_type;
2834 u8 t_l3_addr_type;
2835 u8 tunnel_type;
2836 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
2837 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
2838 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
2839 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
2840 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
2841 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
2842 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
2843 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
2844 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
2845 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
2846 u8 unused_0;
2847 __le32 vni;
2848 __le32 dst_vnic_id;
2849 __le32 mirror_vnic_id;
2850 };
2851
2852 /* Output (24 bytes) */
2853 struct hwrm_cfa_tunnel_filter_alloc_output {
2854 __le16 error_code;
2855 __le16 req_type;
2856 __le16 seq_id;
2857 __le16 resp_len;
2858 __le64 tunnel_filter_id;
2859 __le32 flow_id;
2860 u8 unused_0;
2861 u8 unused_1;
2862 u8 unused_2;
2863 u8 valid;
2864 };
2865
2866 /* hwrm_cfa_tunnel_filter_free */
2867 /* Input (24 bytes) */
2868 struct hwrm_cfa_tunnel_filter_free_input {
2869 __le16 req_type;
2870 __le16 cmpl_ring;
2871 __le16 seq_id;
2872 __le16 target_id;
2873 __le64 resp_addr;
2874 __le64 tunnel_filter_id;
2875 };
2876
2877 /* Output (16 bytes) */
2878 struct hwrm_cfa_tunnel_filter_free_output {
2879 __le16 error_code;
2880 __le16 req_type;
2881 __le16 seq_id;
2882 __le16 resp_len;
2883 __le32 unused_0;
2884 u8 unused_1;
2885 u8 unused_2;
2886 u8 unused_3;
2887 u8 valid;
2888 };
2889
2890 /* hwrm_cfa_encap_record_alloc */
2891 /* Input (32 bytes) */
2892 struct hwrm_cfa_encap_record_alloc_input {
2893 __le16 req_type;
2894 __le16 cmpl_ring;
2895 __le16 seq_id;
2896 __le16 target_id;
2897 __le64 resp_addr;
2898 __le32 flags;
2899 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
2900 u8 encap_type;
2901 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN (0x1UL << 0)
2902 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE (0x2UL << 0)
2903 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE (0x3UL << 0)
2904 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP (0x4UL << 0)
2905 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE (0x5UL << 0)
2906 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS (0x6UL << 0)
2907 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN (0x7UL << 0)
2908 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE (0x8UL << 0)
2909 u8 unused_0;
2910 __le16 unused_1;
2911 __le32 encap_data[16];
2912 };
2913
2914 /* Output (16 bytes) */
2915 struct hwrm_cfa_encap_record_alloc_output {
2916 __le16 error_code;
2917 __le16 req_type;
2918 __le16 seq_id;
2919 __le16 resp_len;
2920 __le32 encap_record_id;
2921 u8 unused_0;
2922 u8 unused_1;
2923 u8 unused_2;
2924 u8 valid;
2925 };
2926
2927 /* hwrm_cfa_encap_record_free */
2928 /* Input (24 bytes) */
2929 struct hwrm_cfa_encap_record_free_input {
2930 __le16 req_type;
2931 __le16 cmpl_ring;
2932 __le16 seq_id;
2933 __le16 target_id;
2934 __le64 resp_addr;
2935 __le32 encap_record_id;
2936 __le32 unused_0;
2937 };
2938
2939 /* Output (16 bytes) */
2940 struct hwrm_cfa_encap_record_free_output {
2941 __le16 error_code;
2942 __le16 req_type;
2943 __le16 seq_id;
2944 __le16 resp_len;
2945 __le32 unused_0;
2946 u8 unused_1;
2947 u8 unused_2;
2948 u8 unused_3;
2949 u8 valid;
2950 };
2951
2952 /* hwrm_cfa_ntuple_filter_alloc */
2953 /* Input (128 bytes) */
2954 struct hwrm_cfa_ntuple_filter_alloc_input {
2955 __le16 req_type;
2956 __le16 cmpl_ring;
2957 __le16 seq_id;
2958 __le16 target_id;
2959 __le64 resp_addr;
2960 __le32 flags;
2961 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL
2962 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL
2963 __le32 enables;
2964 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL
2965 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL
2966 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL
2967 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL
2968 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL
2969 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL
2970 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL
2971 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL
2972 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL
2973 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL
2974 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL
2975 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL
2976 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL
2977 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL
2978 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL
2979 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL
2980 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL
2981 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL
2982 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL
2983 __le64 l2_filter_id;
2984 u8 src_macaddr[6];
2985 __be16 ethertype;
2986 u8 ip_addr_type;
2987 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN (0x0UL << 0)
2988 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 (0x4UL << 0)
2989 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 (0x6UL << 0)
2990 u8 ip_protocol;
2991 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN (0x0UL << 0)
2992 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP (0x6UL << 0)
2993 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP (0x11UL << 0)
2994 __le16 dst_id;
2995 __le16 mirror_vnic_id;
2996 u8 tunnel_type;
2997 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0)
2998 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
2999 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0)
3000 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0)
3001 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0)
3002 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3003 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0)
3004 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0)
3005 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0)
3006 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0)
3007 u8 pri_hint;
3008 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0)
3009 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE (0x1UL << 0)
3010 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW (0x2UL << 0)
3011 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST (0x3UL << 0)
3012 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST (0x4UL << 0)
3013 __be32 src_ipaddr[4];
3014 __be32 src_ipaddr_mask[4];
3015 __be32 dst_ipaddr[4];
3016 __be32 dst_ipaddr_mask[4];
3017 __be16 src_port;
3018 __be16 src_port_mask;
3019 __be16 dst_port;
3020 __be16 dst_port_mask;
3021 __le64 ntuple_filter_id_hint;
3022 };
3023
3024 /* Output (24 bytes) */
3025 struct hwrm_cfa_ntuple_filter_alloc_output {
3026 __le16 error_code;
3027 __le16 req_type;
3028 __le16 seq_id;
3029 __le16 resp_len;
3030 __le64 ntuple_filter_id;
3031 __le32 flow_id;
3032 u8 unused_0;
3033 u8 unused_1;
3034 u8 unused_2;
3035 u8 valid;
3036 };
3037
3038 /* hwrm_cfa_ntuple_filter_free */
3039 /* Input (24 bytes) */
3040 struct hwrm_cfa_ntuple_filter_free_input {
3041 __le16 req_type;
3042 __le16 cmpl_ring;
3043 __le16 seq_id;
3044 __le16 target_id;
3045 __le64 resp_addr;
3046 __le64 ntuple_filter_id;
3047 };
3048
3049 /* Output (16 bytes) */
3050 struct hwrm_cfa_ntuple_filter_free_output {
3051 __le16 error_code;
3052 __le16 req_type;
3053 __le16 seq_id;
3054 __le16 resp_len;
3055 __le32 unused_0;
3056 u8 unused_1;
3057 u8 unused_2;
3058 u8 unused_3;
3059 u8 valid;
3060 };
3061
3062 /* hwrm_cfa_ntuple_filter_cfg */
3063 /* Input (40 bytes) */
3064 struct hwrm_cfa_ntuple_filter_cfg_input {
3065 __le16 req_type;
3066 __le16 cmpl_ring;
3067 __le16 seq_id;
3068 __le16 target_id;
3069 __le64 resp_addr;
3070 __le32 enables;
3071 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL
3072 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL
3073 __le32 unused_0;
3074 __le64 ntuple_filter_id;
3075 __le32 new_dst_id;
3076 __le32 new_mirror_vnic_id;
3077 };
3078
3079 /* Output (16 bytes) */
3080 struct hwrm_cfa_ntuple_filter_cfg_output {
3081 __le16 error_code;
3082 __le16 req_type;
3083 __le16 seq_id;
3084 __le16 resp_len;
3085 __le32 unused_0;
3086 u8 unused_1;
3087 u8 unused_2;
3088 u8 unused_3;
3089 u8 valid;
3090 };
3091
3092 /* hwrm_tunnel_dst_port_query */
3093 /* Input (24 bytes) */
3094 struct hwrm_tunnel_dst_port_query_input {
3095 __le16 req_type;
3096 __le16 cmpl_ring;
3097 __le16 seq_id;
3098 __le16 target_id;
3099 __le64 resp_addr;
3100 u8 tunnel_type;
3101 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3102 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3103 u8 unused_0[7];
3104 };
3105
3106 /* Output (16 bytes) */
3107 struct hwrm_tunnel_dst_port_query_output {
3108 __le16 error_code;
3109 __le16 req_type;
3110 __le16 seq_id;
3111 __le16 resp_len;
3112 __le16 tunnel_dst_port_id;
3113 __be16 tunnel_dst_port_val;
3114 u8 unused_0;
3115 u8 unused_1;
3116 u8 unused_2;
3117 u8 valid;
3118 };
3119
3120 /* hwrm_tunnel_dst_port_alloc */
3121 /* Input (24 bytes) */
3122 struct hwrm_tunnel_dst_port_alloc_input {
3123 __le16 req_type;
3124 __le16 cmpl_ring;
3125 __le16 seq_id;
3126 __le16 target_id;
3127 __le64 resp_addr;
3128 u8 tunnel_type;
3129 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3130 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3131 u8 unused_0;
3132 __be16 tunnel_dst_port_val;
3133 __le32 unused_1;
3134 };
3135
3136 /* Output (16 bytes) */
3137 struct hwrm_tunnel_dst_port_alloc_output {
3138 __le16 error_code;
3139 __le16 req_type;
3140 __le16 seq_id;
3141 __le16 resp_len;
3142 __le16 tunnel_dst_port_id;
3143 u8 unused_0;
3144 u8 unused_1;
3145 u8 unused_2;
3146 u8 unused_3;
3147 u8 unused_4;
3148 u8 valid;
3149 };
3150
3151 /* hwrm_tunnel_dst_port_free */
3152 /* Input (24 bytes) */
3153 struct hwrm_tunnel_dst_port_free_input {
3154 __le16 req_type;
3155 __le16 cmpl_ring;
3156 __le16 seq_id;
3157 __le16 target_id;
3158 __le64 resp_addr;
3159 u8 tunnel_type;
3160 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0)
3161 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0)
3162 u8 unused_0;
3163 __le16 tunnel_dst_port_id;
3164 __le32 unused_1;
3165 };
3166
3167 /* Output (16 bytes) */
3168 struct hwrm_tunnel_dst_port_free_output {
3169 __le16 error_code;
3170 __le16 req_type;
3171 __le16 seq_id;
3172 __le16 resp_len;
3173 __le32 unused_0;
3174 u8 unused_1;
3175 u8 unused_2;
3176 u8 unused_3;
3177 u8 valid;
3178 };
3179
3180 /* hwrm_stat_ctx_alloc */
3181 /* Input (32 bytes) */
3182 struct hwrm_stat_ctx_alloc_input {
3183 __le16 req_type;
3184 __le16 cmpl_ring;
3185 __le16 seq_id;
3186 __le16 target_id;
3187 __le64 resp_addr;
3188 __le64 stats_dma_addr;
3189 __le32 update_period_ms;
3190 __le32 unused_0;
3191 };
3192
3193 /* Output (16 bytes) */
3194 struct hwrm_stat_ctx_alloc_output {
3195 __le16 error_code;
3196 __le16 req_type;
3197 __le16 seq_id;
3198 __le16 resp_len;
3199 __le32 stat_ctx_id;
3200 u8 unused_0;
3201 u8 unused_1;
3202 u8 unused_2;
3203 u8 valid;
3204 };
3205
3206 /* hwrm_stat_ctx_free */
3207 /* Input (24 bytes) */
3208 struct hwrm_stat_ctx_free_input {
3209 __le16 req_type;
3210 __le16 cmpl_ring;
3211 __le16 seq_id;
3212 __le16 target_id;
3213 __le64 resp_addr;
3214 __le32 stat_ctx_id;
3215 __le32 unused_0;
3216 };
3217
3218 /* Output (16 bytes) */
3219 struct hwrm_stat_ctx_free_output {
3220 __le16 error_code;
3221 __le16 req_type;
3222 __le16 seq_id;
3223 __le16 resp_len;
3224 __le32 stat_ctx_id;
3225 u8 unused_0;
3226 u8 unused_1;
3227 u8 unused_2;
3228 u8 valid;
3229 };
3230
3231 /* hwrm_stat_ctx_query */
3232 /* Input (24 bytes) */
3233 struct hwrm_stat_ctx_query_input {
3234 __le16 req_type;
3235 __le16 cmpl_ring;
3236 __le16 seq_id;
3237 __le16 target_id;
3238 __le64 resp_addr;
3239 __le32 stat_ctx_id;
3240 __le32 unused_0;
3241 };
3242
3243 /* Output (176 bytes) */
3244 struct hwrm_stat_ctx_query_output {
3245 __le16 error_code;
3246 __le16 req_type;
3247 __le16 seq_id;
3248 __le16 resp_len;
3249 __le64 tx_ucast_pkts;
3250 __le64 tx_mcast_pkts;
3251 __le64 tx_bcast_pkts;
3252 __le64 tx_err_pkts;
3253 __le64 tx_drop_pkts;
3254 __le64 tx_ucast_bytes;
3255 __le64 tx_mcast_bytes;
3256 __le64 tx_bcast_bytes;
3257 __le64 rx_ucast_pkts;
3258 __le64 rx_mcast_pkts;
3259 __le64 rx_bcast_pkts;
3260 __le64 rx_err_pkts;
3261 __le64 rx_drop_pkts;
3262 __le64 rx_ucast_bytes;
3263 __le64 rx_mcast_bytes;
3264 __le64 rx_bcast_bytes;
3265 __le64 rx_agg_pkts;
3266 __le64 rx_agg_bytes;
3267 __le64 rx_agg_events;
3268 __le64 rx_agg_aborts;
3269 __le32 unused_0;
3270 u8 unused_1;
3271 u8 unused_2;
3272 u8 unused_3;
3273 u8 valid;
3274 };
3275
3276 /* hwrm_stat_ctx_clr_stats */
3277 /* Input (24 bytes) */
3278 struct hwrm_stat_ctx_clr_stats_input {
3279 __le16 req_type;
3280 __le16 cmpl_ring;
3281 __le16 seq_id;
3282 __le16 target_id;
3283 __le64 resp_addr;
3284 __le32 stat_ctx_id;
3285 __le32 unused_0;
3286 };
3287
3288 /* Output (16 bytes) */
3289 struct hwrm_stat_ctx_clr_stats_output {
3290 __le16 error_code;
3291 __le16 req_type;
3292 __le16 seq_id;
3293 __le16 resp_len;
3294 __le32 unused_0;
3295 u8 unused_1;
3296 u8 unused_2;
3297 u8 unused_3;
3298 u8 valid;
3299 };
3300
3301 /* hwrm_fw_reset */
3302 /* Input (24 bytes) */
3303 struct hwrm_fw_reset_input {
3304 __le16 req_type;
3305 __le16 cmpl_ring;
3306 __le16 seq_id;
3307 __le16 target_id;
3308 __le64 resp_addr;
3309 u8 embedded_proc_type;
3310 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0)
3311 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0)
3312 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0)
3313 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0)
3314 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0)
3315 u8 selfrst_status;
3316 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3317 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3318 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3319 __le16 unused_0[3];
3320 };
3321
3322 /* Output (16 bytes) */
3323 struct hwrm_fw_reset_output {
3324 __le16 error_code;
3325 __le16 req_type;
3326 __le16 seq_id;
3327 __le16 resp_len;
3328 u8 selfrst_status;
3329 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0)
3330 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0)
3331 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0)
3332 u8 unused_0;
3333 __le16 unused_1;
3334 u8 unused_2;
3335 u8 unused_3;
3336 u8 unused_4;
3337 u8 valid;
3338 };
3339
3340 /* hwrm_exec_fwd_resp */
3341 /* Input (128 bytes) */
3342 struct hwrm_exec_fwd_resp_input {
3343 __le16 req_type;
3344 __le16 cmpl_ring;
3345 __le16 seq_id;
3346 __le16 target_id;
3347 __le64 resp_addr;
3348 __le32 encap_request[26];
3349 __le16 encap_resp_target_id;
3350 __le16 unused_0[3];
3351 };
3352
3353 /* Output (16 bytes) */
3354 struct hwrm_exec_fwd_resp_output {
3355 __le16 error_code;
3356 __le16 req_type;
3357 __le16 seq_id;
3358 __le16 resp_len;
3359 __le32 unused_0;
3360 u8 unused_1;
3361 u8 unused_2;
3362 u8 unused_3;
3363 u8 valid;
3364 };
3365
3366 /* hwrm_reject_fwd_resp */
3367 /* Input (128 bytes) */
3368 struct hwrm_reject_fwd_resp_input {
3369 __le16 req_type;
3370 __le16 cmpl_ring;
3371 __le16 seq_id;
3372 __le16 target_id;
3373 __le64 resp_addr;
3374 __le32 encap_request[26];
3375 __le16 encap_resp_target_id;
3376 __le16 unused_0[3];
3377 };
3378
3379 /* Output (16 bytes) */
3380 struct hwrm_reject_fwd_resp_output {
3381 __le16 error_code;
3382 __le16 req_type;
3383 __le16 seq_id;
3384 __le16 resp_len;
3385 __le32 unused_0;
3386 u8 unused_1;
3387 u8 unused_2;
3388 u8 unused_3;
3389 u8 valid;
3390 };
3391
3392 /* hwrm_fwd_resp */
3393 /* Input (40 bytes) */
3394 struct hwrm_fwd_resp_input {
3395 __le16 req_type;
3396 __le16 cmpl_ring;
3397 __le16 seq_id;
3398 __le16 target_id;
3399 __le64 resp_addr;
3400 __le16 encap_resp_target_id;
3401 __le16 encap_resp_cmpl_ring;
3402 __le16 encap_resp_len;
3403 u8 unused_0;
3404 u8 unused_1;
3405 __le64 encap_resp_addr;
3406 __le32 encap_resp[24];
3407 };
3408
3409 /* Output (16 bytes) */
3410 struct hwrm_fwd_resp_output {
3411 __le16 error_code;
3412 __le16 req_type;
3413 __le16 seq_id;
3414 __le16 resp_len;
3415 __le32 unused_0;
3416 u8 unused_1;
3417 u8 unused_2;
3418 u8 unused_3;
3419 u8 valid;
3420 };
3421
3422 /* hwrm_fwd_async_event_cmpl */
3423 /* Input (32 bytes) */
3424 struct hwrm_fwd_async_event_cmpl_input {
3425 __le16 req_type;
3426 __le16 cmpl_ring;
3427 __le16 seq_id;
3428 __le16 target_id;
3429 __le64 resp_addr;
3430 __le16 encap_async_event_target_id;
3431 u8 unused_0;
3432 u8 unused_1;
3433 u8 unused_2[3];
3434 u8 unused_3;
3435 __le32 encap_async_event_cmpl[4];
3436 };
3437
3438 /* Output (16 bytes) */
3439 struct hwrm_fwd_async_event_cmpl_output {
3440 __le16 error_code;
3441 __le16 req_type;
3442 __le16 seq_id;
3443 __le16 resp_len;
3444 __le32 unused_0;
3445 u8 unused_1;
3446 u8 unused_2;
3447 u8 unused_3;
3448 u8 valid;
3449 };
3450
3451 /* hwrm_temp_monitor_query */
3452 /* Input (16 bytes) */
3453 struct hwrm_temp_monitor_query_input {
3454 __le16 req_type;
3455 __le16 cmpl_ring;
3456 __le16 seq_id;
3457 __le16 target_id;
3458 __le64 resp_addr;
3459 };
3460
3461 /* Output (16 bytes) */
3462 struct hwrm_temp_monitor_query_output {
3463 __le16 error_code;
3464 __le16 req_type;
3465 __le16 seq_id;
3466 __le16 resp_len;
3467 u8 temp;
3468 u8 unused_0;
3469 __le16 unused_1;
3470 u8 unused_2;
3471 u8 unused_3;
3472 u8 unused_4;
3473 u8 valid;
3474 };
3475
3476 /* hwrm_nvm_raw_write_blk */
3477 /* Input (32 bytes) */
3478 struct hwrm_nvm_raw_write_blk_input {
3479 __le16 req_type;
3480 __le16 cmpl_ring;
3481 __le16 seq_id;
3482 __le16 target_id;
3483 __le64 resp_addr;
3484 __le64 host_src_addr;
3485 __le32 dest_addr;
3486 __le32 len;
3487 };
3488
3489 /* Output (16 bytes) */
3490 struct hwrm_nvm_raw_write_blk_output {
3491 __le16 error_code;
3492 __le16 req_type;
3493 __le16 seq_id;
3494 __le16 resp_len;
3495 __le32 unused_0;
3496 u8 unused_1;
3497 u8 unused_2;
3498 u8 unused_3;
3499 u8 valid;
3500 };
3501
3502 /* hwrm_nvm_read */
3503 /* Input (40 bytes) */
3504 struct hwrm_nvm_read_input {
3505 __le16 req_type;
3506 __le16 cmpl_ring;
3507 __le16 seq_id;
3508 __le16 target_id;
3509 __le64 resp_addr;
3510 __le64 host_dest_addr;
3511 __le16 dir_idx;
3512 u8 unused_0;
3513 u8 unused_1;
3514 __le32 offset;
3515 __le32 len;
3516 __le32 unused_2;
3517 };
3518
3519 /* Output (16 bytes) */
3520 struct hwrm_nvm_read_output {
3521 __le16 error_code;
3522 __le16 req_type;
3523 __le16 seq_id;
3524 __le16 resp_len;
3525 __le32 unused_0;
3526 u8 unused_1;
3527 u8 unused_2;
3528 u8 unused_3;
3529 u8 valid;
3530 };
3531
3532 /* hwrm_nvm_raw_dump */
3533 /* Input (32 bytes) */
3534 struct hwrm_nvm_raw_dump_input {
3535 __le16 req_type;
3536 __le16 cmpl_ring;
3537 __le16 seq_id;
3538 __le16 target_id;
3539 __le64 resp_addr;
3540 __le64 host_dest_addr;
3541 __le32 offset;
3542 __le32 len;
3543 };
3544
3545 /* Output (16 bytes) */
3546 struct hwrm_nvm_raw_dump_output {
3547 __le16 error_code;
3548 __le16 req_type;
3549 __le16 seq_id;
3550 __le16 resp_len;
3551 __le32 unused_0;
3552 u8 unused_1;
3553 u8 unused_2;
3554 u8 unused_3;
3555 u8 valid;
3556 };
3557
3558 /* hwrm_nvm_get_dir_entries */
3559 /* Input (24 bytes) */
3560 struct hwrm_nvm_get_dir_entries_input {
3561 __le16 req_type;
3562 __le16 cmpl_ring;
3563 __le16 seq_id;
3564 __le16 target_id;
3565 __le64 resp_addr;
3566 __le64 host_dest_addr;
3567 };
3568
3569 /* Output (16 bytes) */
3570 struct hwrm_nvm_get_dir_entries_output {
3571 __le16 error_code;
3572 __le16 req_type;
3573 __le16 seq_id;
3574 __le16 resp_len;
3575 __le32 unused_0;
3576 u8 unused_1;
3577 u8 unused_2;
3578 u8 unused_3;
3579 u8 valid;
3580 };
3581
3582 /* hwrm_nvm_get_dir_info */
3583 /* Input (16 bytes) */
3584 struct hwrm_nvm_get_dir_info_input {
3585 __le16 req_type;
3586 __le16 cmpl_ring;
3587 __le16 seq_id;
3588 __le16 target_id;
3589 __le64 resp_addr;
3590 };
3591
3592 /* Output (24 bytes) */
3593 struct hwrm_nvm_get_dir_info_output {
3594 __le16 error_code;
3595 __le16 req_type;
3596 __le16 seq_id;
3597 __le16 resp_len;
3598 __le32 entries;
3599 __le32 entry_length;
3600 __le32 unused_0;
3601 u8 unused_1;
3602 u8 unused_2;
3603 u8 unused_3;
3604 u8 valid;
3605 };
3606
3607 /* hwrm_nvm_write */
3608 /* Input (48 bytes) */
3609 struct hwrm_nvm_write_input {
3610 __le16 req_type;
3611 __le16 cmpl_ring;
3612 __le16 seq_id;
3613 __le16 target_id;
3614 __le64 resp_addr;
3615 __le64 host_src_addr;
3616 __le16 dir_type;
3617 __le16 dir_ordinal;
3618 __le16 dir_ext;
3619 __le16 dir_attr;
3620 __le32 dir_data_length;
3621 __le16 option;
3622 __le16 flags;
3623 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL
3624 __le32 dir_item_length;
3625 __le32 unused_0;
3626 };
3627
3628 /* Output (16 bytes) */
3629 struct hwrm_nvm_write_output {
3630 __le16 error_code;
3631 __le16 req_type;
3632 __le16 seq_id;
3633 __le16 resp_len;
3634 __le32 dir_item_length;
3635 __le16 dir_idx;
3636 u8 unused_0;
3637 u8 valid;
3638 };
3639
3640 /* hwrm_nvm_modify */
3641 /* Input (40 bytes) */
3642 struct hwrm_nvm_modify_input {
3643 __le16 req_type;
3644 __le16 cmpl_ring;
3645 __le16 seq_id;
3646 __le16 target_id;
3647 __le64 resp_addr;
3648 __le64 host_src_addr;
3649 __le16 dir_idx;
3650 u8 unused_0;
3651 u8 unused_1;
3652 __le32 offset;
3653 __le32 len;
3654 __le32 unused_2;
3655 };
3656
3657 /* Output (16 bytes) */
3658 struct hwrm_nvm_modify_output {
3659 __le16 error_code;
3660 __le16 req_type;
3661 __le16 seq_id;
3662 __le16 resp_len;
3663 __le32 unused_0;
3664 u8 unused_1;
3665 u8 unused_2;
3666 u8 unused_3;
3667 u8 valid;
3668 };
3669
3670 /* hwrm_nvm_find_dir_entry */
3671 /* Input (32 bytes) */
3672 struct hwrm_nvm_find_dir_entry_input {
3673 __le16 req_type;
3674 __le16 cmpl_ring;
3675 __le16 seq_id;
3676 __le16 target_id;
3677 __le64 resp_addr;
3678 __le32 enables;
3679 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL
3680 __le16 dir_idx;
3681 __le16 dir_type;
3682 __le16 dir_ordinal;
3683 __le16 dir_ext;
3684 u8 opt_ordinal;
3685 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL
3686 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0
3687 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ (0x0UL << 0)
3688 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE (0x1UL << 0)
3689 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT (0x2UL << 0)
3690 u8 unused_1[3];
3691 };
3692
3693 /* Output (32 bytes) */
3694 struct hwrm_nvm_find_dir_entry_output {
3695 __le16 error_code;
3696 __le16 req_type;
3697 __le16 seq_id;
3698 __le16 resp_len;
3699 __le32 dir_item_length;
3700 __le32 dir_data_length;
3701 __le32 fw_ver;
3702 __le16 dir_ordinal;
3703 __le16 dir_idx;
3704 __le32 unused_0;
3705 u8 unused_1;
3706 u8 unused_2;
3707 u8 unused_3;
3708 u8 valid;
3709 };
3710
3711 /* hwrm_nvm_erase_dir_entry */
3712 /* Input (24 bytes) */
3713 struct hwrm_nvm_erase_dir_entry_input {
3714 __le16 req_type;
3715 __le16 cmpl_ring;
3716 __le16 seq_id;
3717 __le16 target_id;
3718 __le64 resp_addr;
3719 __le16 dir_idx;
3720 __le16 unused_0[3];
3721 };
3722
3723 /* Output (16 bytes) */
3724 struct hwrm_nvm_erase_dir_entry_output {
3725 __le16 error_code;
3726 __le16 req_type;
3727 __le16 seq_id;
3728 __le16 resp_len;
3729 __le32 unused_0;
3730 u8 unused_1;
3731 u8 unused_2;
3732 u8 unused_3;
3733 u8 valid;
3734 };
3735
3736 /* hwrm_nvm_get_dev_info */
3737 /* Input (16 bytes) */
3738 struct hwrm_nvm_get_dev_info_input {
3739 __le16 req_type;
3740 __le16 cmpl_ring;
3741 __le16 seq_id;
3742 __le16 target_id;
3743 __le64 resp_addr;
3744 };
3745
3746 /* Output (32 bytes) */
3747 struct hwrm_nvm_get_dev_info_output {
3748 __le16 error_code;
3749 __le16 req_type;
3750 __le16 seq_id;
3751 __le16 resp_len;
3752 __le16 manufacturer_id;
3753 __le16 device_id;
3754 __le32 sector_size;
3755 __le32 nvram_size;
3756 __le32 reserved_size;
3757 __le32 available_size;
3758 u8 unused_0;
3759 u8 unused_1;
3760 u8 unused_2;
3761 u8 valid;
3762 };
3763
3764 /* hwrm_nvm_mod_dir_entry */
3765 /* Input (32 bytes) */
3766 struct hwrm_nvm_mod_dir_entry_input {
3767 __le16 req_type;
3768 __le16 cmpl_ring;
3769 __le16 seq_id;
3770 __le16 target_id;
3771 __le64 resp_addr;
3772 __le32 enables;
3773 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL
3774 __le16 dir_idx;
3775 __le16 dir_ordinal;
3776 __le16 dir_ext;
3777 __le16 dir_attr;
3778 __le32 checksum;
3779 };
3780
3781 /* Output (16 bytes) */
3782 struct hwrm_nvm_mod_dir_entry_output {
3783 __le16 error_code;
3784 __le16 req_type;
3785 __le16 seq_id;
3786 __le16 resp_len;
3787 __le32 unused_0;
3788 u8 unused_1;
3789 u8 unused_2;
3790 u8 unused_3;
3791 u8 valid;
3792 };
3793
3794 /* hwrm_nvm_verify_update */
3795 /* Input (24 bytes) */
3796 struct hwrm_nvm_verify_update_input {
3797 __le16 req_type;
3798 __le16 cmpl_ring;
3799 __le16 seq_id;
3800 __le16 target_id;
3801 __le64 resp_addr;
3802 __le16 dir_type;
3803 __le16 dir_ordinal;
3804 __le16 dir_ext;
3805 __le16 unused_0;
3806 };
3807
3808 /* Output (16 bytes) */
3809 struct hwrm_nvm_verify_update_output {
3810 __le16 error_code;
3811 __le16 req_type;
3812 __le16 seq_id;
3813 __le16 resp_len;
3814 __le32 unused_0;
3815 u8 unused_1;
3816 u8 unused_2;
3817 u8 unused_3;
3818 u8 valid;
3819 };
3820
3821 #endif
Linux kernel - Deliverables
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