2 * Linux network driver for QLogic BR-series Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
15 * Copyright (c) 2014-2015 QLogic Corporation
19 #include <linux/bitops.h>
20 #include <linux/netdevice.h>
21 #include <linux/skbuff.h>
22 #include <linux/etherdevice.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_vlan.h>
26 #include <linux/if_ether.h>
28 #include <linux/prefetch.h>
29 #include <linux/module.h>
35 static DEFINE_MUTEX(bnad_fwimg_mutex
);
40 static uint bnad_msix_disable
;
41 module_param(bnad_msix_disable
, uint
, 0444);
42 MODULE_PARM_DESC(bnad_msix_disable
, "Disable MSIX mode");
44 static uint bnad_ioc_auto_recover
= 1;
45 module_param(bnad_ioc_auto_recover
, uint
, 0444);
46 MODULE_PARM_DESC(bnad_ioc_auto_recover
, "Enable / Disable auto recovery");
48 static uint bna_debugfs_enable
= 1;
49 module_param(bna_debugfs_enable
, uint
, S_IRUGO
| S_IWUSR
);
50 MODULE_PARM_DESC(bna_debugfs_enable
, "Enables debugfs feature, default=1,"
51 " Range[false:0|true:1]");
56 static u32 bnad_rxqs_per_cq
= 2;
58 static struct mutex bnad_list_mutex
;
59 static LIST_HEAD(bnad_list
);
60 static const u8 bnad_bcast_addr
[] __aligned(2) =
61 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
66 #define BNAD_GET_MBOX_IRQ(_bnad) \
67 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
68 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
69 ((_bnad)->pcidev->irq))
71 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \
73 (_res_info)->res_type = BNA_RES_T_MEM; \
74 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
75 (_res_info)->res_u.mem_info.num = (_num); \
76 (_res_info)->res_u.mem_info.len = (_size); \
80 bnad_add_to_list(struct bnad
*bnad
)
82 mutex_lock(&bnad_list_mutex
);
83 list_add_tail(&bnad
->list_entry
, &bnad_list
);
85 mutex_unlock(&bnad_list_mutex
);
89 bnad_remove_from_list(struct bnad
*bnad
)
91 mutex_lock(&bnad_list_mutex
);
92 list_del(&bnad
->list_entry
);
93 mutex_unlock(&bnad_list_mutex
);
97 * Reinitialize completions in CQ, once Rx is taken down
100 bnad_cq_cleanup(struct bnad
*bnad
, struct bna_ccb
*ccb
)
102 struct bna_cq_entry
*cmpl
;
105 for (i
= 0; i
< ccb
->q_depth
; i
++) {
106 cmpl
= &((struct bna_cq_entry
*)ccb
->sw_q
)[i
];
111 /* Tx Datapath functions */
114 /* Caller should ensure that the entry at unmap_q[index] is valid */
116 bnad_tx_buff_unmap(struct bnad
*bnad
,
117 struct bnad_tx_unmap
*unmap_q
,
118 u32 q_depth
, u32 index
)
120 struct bnad_tx_unmap
*unmap
;
124 unmap
= &unmap_q
[index
];
125 nvecs
= unmap
->nvecs
;
130 dma_unmap_single(&bnad
->pcidev
->dev
,
131 dma_unmap_addr(&unmap
->vectors
[0], dma_addr
),
132 skb_headlen(skb
), DMA_TO_DEVICE
);
133 dma_unmap_addr_set(&unmap
->vectors
[0], dma_addr
, 0);
139 if (vector
== BFI_TX_MAX_VECTORS_PER_WI
) {
141 BNA_QE_INDX_INC(index
, q_depth
);
142 unmap
= &unmap_q
[index
];
145 dma_unmap_page(&bnad
->pcidev
->dev
,
146 dma_unmap_addr(&unmap
->vectors
[vector
], dma_addr
),
147 dma_unmap_len(&unmap
->vectors
[vector
], dma_len
),
149 dma_unmap_addr_set(&unmap
->vectors
[vector
], dma_addr
, 0);
153 BNA_QE_INDX_INC(index
, q_depth
);
159 * Frees all pending Tx Bufs
160 * At this point no activity is expected on the Q,
161 * so DMA unmap & freeing is fine.
164 bnad_txq_cleanup(struct bnad
*bnad
, struct bna_tcb
*tcb
)
166 struct bnad_tx_unmap
*unmap_q
= tcb
->unmap_q
;
170 for (i
= 0; i
< tcb
->q_depth
; i
++) {
171 skb
= unmap_q
[i
].skb
;
174 bnad_tx_buff_unmap(bnad
, unmap_q
, tcb
->q_depth
, i
);
176 dev_kfree_skb_any(skb
);
181 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
182 * Can be called in a) Interrupt context
186 bnad_txcmpl_process(struct bnad
*bnad
, struct bna_tcb
*tcb
)
188 u32 sent_packets
= 0, sent_bytes
= 0;
189 u32 wis
, unmap_wis
, hw_cons
, cons
, q_depth
;
190 struct bnad_tx_unmap
*unmap_q
= tcb
->unmap_q
;
191 struct bnad_tx_unmap
*unmap
;
194 /* Just return if TX is stopped */
195 if (!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
198 hw_cons
= *(tcb
->hw_consumer_index
);
199 cons
= tcb
->consumer_index
;
200 q_depth
= tcb
->q_depth
;
202 wis
= BNA_Q_INDEX_CHANGE(cons
, hw_cons
, q_depth
);
203 BUG_ON(!(wis
<= BNA_QE_IN_USE_CNT(tcb
, tcb
->q_depth
)));
206 unmap
= &unmap_q
[cons
];
211 sent_bytes
+= skb
->len
;
213 unmap_wis
= BNA_TXQ_WI_NEEDED(unmap
->nvecs
);
216 cons
= bnad_tx_buff_unmap(bnad
, unmap_q
, q_depth
, cons
);
217 dev_kfree_skb_any(skb
);
220 /* Update consumer pointers. */
221 tcb
->consumer_index
= hw_cons
;
223 tcb
->txq
->tx_packets
+= sent_packets
;
224 tcb
->txq
->tx_bytes
+= sent_bytes
;
230 bnad_tx_complete(struct bnad
*bnad
, struct bna_tcb
*tcb
)
232 struct net_device
*netdev
= bnad
->netdev
;
235 if (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
))
238 sent
= bnad_txcmpl_process(bnad
, tcb
);
240 if (netif_queue_stopped(netdev
) &&
241 netif_carrier_ok(netdev
) &&
242 BNA_QE_FREE_CNT(tcb
, tcb
->q_depth
) >=
243 BNAD_NETIF_WAKE_THRESHOLD
) {
244 if (test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)) {
245 netif_wake_queue(netdev
);
246 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
251 if (likely(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
252 bna_ib_ack(tcb
->i_dbell
, sent
);
254 smp_mb__before_atomic();
255 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
260 /* MSIX Tx Completion Handler */
262 bnad_msix_tx(int irq
, void *data
)
264 struct bna_tcb
*tcb
= (struct bna_tcb
*)data
;
265 struct bnad
*bnad
= tcb
->bnad
;
267 bnad_tx_complete(bnad
, tcb
);
273 bnad_rxq_alloc_uninit(struct bnad
*bnad
, struct bna_rcb
*rcb
)
275 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
277 unmap_q
->reuse_pi
= -1;
278 unmap_q
->alloc_order
= -1;
279 unmap_q
->map_size
= 0;
280 unmap_q
->type
= BNAD_RXBUF_NONE
;
283 /* Default is page-based allocation. Multi-buffer support - TBD */
285 bnad_rxq_alloc_init(struct bnad
*bnad
, struct bna_rcb
*rcb
)
287 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
290 bnad_rxq_alloc_uninit(bnad
, rcb
);
292 order
= get_order(rcb
->rxq
->buffer_size
);
294 unmap_q
->type
= BNAD_RXBUF_PAGE
;
296 if (bna_is_small_rxq(rcb
->id
)) {
297 unmap_q
->alloc_order
= 0;
298 unmap_q
->map_size
= rcb
->rxq
->buffer_size
;
300 if (rcb
->rxq
->multi_buffer
) {
301 unmap_q
->alloc_order
= 0;
302 unmap_q
->map_size
= rcb
->rxq
->buffer_size
;
303 unmap_q
->type
= BNAD_RXBUF_MULTI_BUFF
;
305 unmap_q
->alloc_order
= order
;
307 (rcb
->rxq
->buffer_size
> 2048) ?
308 PAGE_SIZE
<< order
: 2048;
312 BUG_ON((PAGE_SIZE
<< order
) % unmap_q
->map_size
);
318 bnad_rxq_cleanup_page(struct bnad
*bnad
, struct bnad_rx_unmap
*unmap
)
323 dma_unmap_page(&bnad
->pcidev
->dev
,
324 dma_unmap_addr(&unmap
->vector
, dma_addr
),
325 unmap
->vector
.len
, DMA_FROM_DEVICE
);
326 put_page(unmap
->page
);
328 dma_unmap_addr_set(&unmap
->vector
, dma_addr
, 0);
329 unmap
->vector
.len
= 0;
333 bnad_rxq_cleanup_skb(struct bnad
*bnad
, struct bnad_rx_unmap
*unmap
)
338 dma_unmap_single(&bnad
->pcidev
->dev
,
339 dma_unmap_addr(&unmap
->vector
, dma_addr
),
340 unmap
->vector
.len
, DMA_FROM_DEVICE
);
341 dev_kfree_skb_any(unmap
->skb
);
343 dma_unmap_addr_set(&unmap
->vector
, dma_addr
, 0);
344 unmap
->vector
.len
= 0;
348 bnad_rxq_cleanup(struct bnad
*bnad
, struct bna_rcb
*rcb
)
350 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
353 for (i
= 0; i
< rcb
->q_depth
; i
++) {
354 struct bnad_rx_unmap
*unmap
= &unmap_q
->unmap
[i
];
356 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
357 bnad_rxq_cleanup_skb(bnad
, unmap
);
359 bnad_rxq_cleanup_page(bnad
, unmap
);
361 bnad_rxq_alloc_uninit(bnad
, rcb
);
365 bnad_rxq_refill_page(struct bnad
*bnad
, struct bna_rcb
*rcb
, u32 nalloc
)
367 u32 alloced
, prod
, q_depth
;
368 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
369 struct bnad_rx_unmap
*unmap
, *prev
;
370 struct bna_rxq_entry
*rxent
;
372 u32 page_offset
, alloc_size
;
375 prod
= rcb
->producer_index
;
376 q_depth
= rcb
->q_depth
;
378 alloc_size
= PAGE_SIZE
<< unmap_q
->alloc_order
;
382 unmap
= &unmap_q
->unmap
[prod
];
384 if (unmap_q
->reuse_pi
< 0) {
385 page
= alloc_pages(GFP_ATOMIC
| __GFP_COMP
,
386 unmap_q
->alloc_order
);
389 prev
= &unmap_q
->unmap
[unmap_q
->reuse_pi
];
391 page_offset
= prev
->page_offset
+ unmap_q
->map_size
;
395 if (unlikely(!page
)) {
396 BNAD_UPDATE_CTR(bnad
, rxbuf_alloc_failed
);
397 rcb
->rxq
->rxbuf_alloc_failed
++;
401 dma_addr
= dma_map_page(&bnad
->pcidev
->dev
, page
, page_offset
,
402 unmap_q
->map_size
, DMA_FROM_DEVICE
);
405 unmap
->page_offset
= page_offset
;
406 dma_unmap_addr_set(&unmap
->vector
, dma_addr
, dma_addr
);
407 unmap
->vector
.len
= unmap_q
->map_size
;
408 page_offset
+= unmap_q
->map_size
;
410 if (page_offset
< alloc_size
)
411 unmap_q
->reuse_pi
= prod
;
413 unmap_q
->reuse_pi
= -1;
415 rxent
= &((struct bna_rxq_entry
*)rcb
->sw_q
)[prod
];
416 BNA_SET_DMA_ADDR(dma_addr
, &rxent
->host_addr
);
417 BNA_QE_INDX_INC(prod
, q_depth
);
422 if (likely(alloced
)) {
423 rcb
->producer_index
= prod
;
425 if (likely(test_bit(BNAD_RXQ_POST_OK
, &rcb
->flags
)))
426 bna_rxq_prod_indx_doorbell(rcb
);
433 bnad_rxq_refill_skb(struct bnad
*bnad
, struct bna_rcb
*rcb
, u32 nalloc
)
435 u32 alloced
, prod
, q_depth
, buff_sz
;
436 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
437 struct bnad_rx_unmap
*unmap
;
438 struct bna_rxq_entry
*rxent
;
442 buff_sz
= rcb
->rxq
->buffer_size
;
443 prod
= rcb
->producer_index
;
444 q_depth
= rcb
->q_depth
;
448 unmap
= &unmap_q
->unmap
[prod
];
450 skb
= netdev_alloc_skb_ip_align(bnad
->netdev
, buff_sz
);
452 if (unlikely(!skb
)) {
453 BNAD_UPDATE_CTR(bnad
, rxbuf_alloc_failed
);
454 rcb
->rxq
->rxbuf_alloc_failed
++;
457 dma_addr
= dma_map_single(&bnad
->pcidev
->dev
, skb
->data
,
458 buff_sz
, DMA_FROM_DEVICE
);
461 dma_unmap_addr_set(&unmap
->vector
, dma_addr
, dma_addr
);
462 unmap
->vector
.len
= buff_sz
;
464 rxent
= &((struct bna_rxq_entry
*)rcb
->sw_q
)[prod
];
465 BNA_SET_DMA_ADDR(dma_addr
, &rxent
->host_addr
);
466 BNA_QE_INDX_INC(prod
, q_depth
);
471 if (likely(alloced
)) {
472 rcb
->producer_index
= prod
;
474 if (likely(test_bit(BNAD_RXQ_POST_OK
, &rcb
->flags
)))
475 bna_rxq_prod_indx_doorbell(rcb
);
482 bnad_rxq_post(struct bnad
*bnad
, struct bna_rcb
*rcb
)
484 struct bnad_rx_unmap_q
*unmap_q
= rcb
->unmap_q
;
487 to_alloc
= BNA_QE_FREE_CNT(rcb
, rcb
->q_depth
);
488 if (!(to_alloc
>> BNAD_RXQ_REFILL_THRESHOLD_SHIFT
))
491 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
492 bnad_rxq_refill_skb(bnad
, rcb
, to_alloc
);
494 bnad_rxq_refill_page(bnad
, rcb
, to_alloc
);
497 #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
499 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \
500 BNA_CQ_EF_L4_CKSUM_OK)
502 #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
503 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
504 #define flags_tcp6 (BNA_CQ_EF_IPV6 | \
505 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
506 #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
507 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
508 #define flags_udp6 (BNA_CQ_EF_IPV6 | \
509 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
512 bnad_cq_drop_packet(struct bnad
*bnad
, struct bna_rcb
*rcb
,
513 u32 sop_ci
, u32 nvecs
)
515 struct bnad_rx_unmap_q
*unmap_q
;
516 struct bnad_rx_unmap
*unmap
;
519 unmap_q
= rcb
->unmap_q
;
520 for (vec
= 0, ci
= sop_ci
; vec
< nvecs
; vec
++) {
521 unmap
= &unmap_q
->unmap
[ci
];
522 BNA_QE_INDX_INC(ci
, rcb
->q_depth
);
524 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
525 bnad_rxq_cleanup_skb(bnad
, unmap
);
527 bnad_rxq_cleanup_page(bnad
, unmap
);
532 bnad_cq_setup_skb_frags(struct bna_rcb
*rcb
, struct sk_buff
*skb
,
533 u32 sop_ci
, u32 nvecs
, u32 last_fraglen
)
536 u32 ci
, vec
, len
, totlen
= 0;
537 struct bnad_rx_unmap_q
*unmap_q
;
538 struct bnad_rx_unmap
*unmap
;
540 unmap_q
= rcb
->unmap_q
;
543 /* prefetch header */
544 prefetch(page_address(unmap_q
->unmap
[sop_ci
].page
) +
545 unmap_q
->unmap
[sop_ci
].page_offset
);
547 for (vec
= 1, ci
= sop_ci
; vec
<= nvecs
; vec
++) {
548 unmap
= &unmap_q
->unmap
[ci
];
549 BNA_QE_INDX_INC(ci
, rcb
->q_depth
);
551 dma_unmap_page(&bnad
->pcidev
->dev
,
552 dma_unmap_addr(&unmap
->vector
, dma_addr
),
553 unmap
->vector
.len
, DMA_FROM_DEVICE
);
555 len
= (vec
== nvecs
) ?
556 last_fraglen
: unmap
->vector
.len
;
557 skb
->truesize
+= unmap
->vector
.len
;
560 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
561 unmap
->page
, unmap
->page_offset
, len
);
564 unmap
->vector
.len
= 0;
568 skb
->data_len
+= totlen
;
572 bnad_cq_setup_skb(struct bnad
*bnad
, struct sk_buff
*skb
,
573 struct bnad_rx_unmap
*unmap
, u32 len
)
577 dma_unmap_single(&bnad
->pcidev
->dev
,
578 dma_unmap_addr(&unmap
->vector
, dma_addr
),
579 unmap
->vector
.len
, DMA_FROM_DEVICE
);
582 skb
->protocol
= eth_type_trans(skb
, bnad
->netdev
);
585 unmap
->vector
.len
= 0;
589 bnad_cq_process(struct bnad
*bnad
, struct bna_ccb
*ccb
, int budget
)
591 struct bna_cq_entry
*cq
, *cmpl
, *next_cmpl
;
592 struct bna_rcb
*rcb
= NULL
;
593 struct bnad_rx_unmap_q
*unmap_q
;
594 struct bnad_rx_unmap
*unmap
= NULL
;
595 struct sk_buff
*skb
= NULL
;
596 struct bna_pkt_rate
*pkt_rt
= &ccb
->pkt_rate
;
597 struct bnad_rx_ctrl
*rx_ctrl
= ccb
->ctrl
;
598 u32 packets
= 0, len
= 0, totlen
= 0;
599 u32 pi
, vec
, sop_ci
= 0, nvecs
= 0;
600 u32 flags
, masked_flags
;
602 prefetch(bnad
->netdev
);
606 while (packets
< budget
) {
607 cmpl
= &cq
[ccb
->producer_index
];
610 /* The 'valid' field is set by the adapter, only after writing
611 * the other fields of completion entry. Hence, do not load
612 * other fields of completion entry *before* the 'valid' is
613 * loaded. Adding the rmb() here prevents the compiler and/or
614 * CPU from reordering the reads which would potentially result
615 * in reading stale values in completion entry.
619 BNA_UPDATE_PKT_CNT(pkt_rt
, ntohs(cmpl
->length
));
621 if (bna_is_small_rxq(cmpl
->rxq_id
))
626 unmap_q
= rcb
->unmap_q
;
628 /* start of packet ci */
629 sop_ci
= rcb
->consumer_index
;
631 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
)) {
632 unmap
= &unmap_q
->unmap
[sop_ci
];
635 skb
= napi_get_frags(&rx_ctrl
->napi
);
641 flags
= ntohl(cmpl
->flags
);
642 len
= ntohs(cmpl
->length
);
646 /* Check all the completions for this frame.
647 * busy-wait doesn't help much, break here.
649 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q
->type
) &&
650 (flags
& BNA_CQ_EF_EOP
) == 0) {
651 pi
= ccb
->producer_index
;
653 BNA_QE_INDX_INC(pi
, ccb
->q_depth
);
656 if (!next_cmpl
->valid
)
658 /* The 'valid' field is set by the adapter, only
659 * after writing the other fields of completion
660 * entry. Hence, do not load other fields of
661 * completion entry *before* the 'valid' is
662 * loaded. Adding the rmb() here prevents the
663 * compiler and/or CPU from reordering the reads
664 * which would potentially result in reading
665 * stale values in completion entry.
669 len
= ntohs(next_cmpl
->length
);
670 flags
= ntohl(next_cmpl
->flags
);
674 } while ((flags
& BNA_CQ_EF_EOP
) == 0);
676 if (!next_cmpl
->valid
)
681 /* TODO: BNA_CQ_EF_LOCAL ? */
682 if (unlikely(flags
& (BNA_CQ_EF_MAC_ERROR
|
683 BNA_CQ_EF_FCS_ERROR
|
684 BNA_CQ_EF_TOO_LONG
))) {
685 bnad_cq_drop_packet(bnad
, rcb
, sop_ci
, nvecs
);
686 rcb
->rxq
->rx_packets_with_error
++;
691 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
692 bnad_cq_setup_skb(bnad
, skb
, unmap
, len
);
694 bnad_cq_setup_skb_frags(rcb
, skb
, sop_ci
, nvecs
, len
);
696 rcb
->rxq
->rx_packets
++;
697 rcb
->rxq
->rx_bytes
+= totlen
;
698 ccb
->bytes_per_intr
+= totlen
;
700 masked_flags
= flags
& flags_cksum_prot_mask
;
703 ((bnad
->netdev
->features
& NETIF_F_RXCSUM
) &&
704 ((masked_flags
== flags_tcp4
) ||
705 (masked_flags
== flags_udp4
) ||
706 (masked_flags
== flags_tcp6
) ||
707 (masked_flags
== flags_udp6
))))
708 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
710 skb_checksum_none_assert(skb
);
712 if ((flags
& BNA_CQ_EF_VLAN
) &&
713 (bnad
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
))
714 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), ntohs(cmpl
->vlan_tag
));
716 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q
->type
))
717 netif_receive_skb(skb
);
719 napi_gro_frags(&rx_ctrl
->napi
);
722 BNA_QE_INDX_ADD(rcb
->consumer_index
, nvecs
, rcb
->q_depth
);
723 for (vec
= 0; vec
< nvecs
; vec
++) {
724 cmpl
= &cq
[ccb
->producer_index
];
726 BNA_QE_INDX_INC(ccb
->producer_index
, ccb
->q_depth
);
730 napi_gro_flush(&rx_ctrl
->napi
, false);
731 if (likely(test_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
)))
732 bna_ib_ack_disable_irq(ccb
->i_dbell
, packets
);
734 bnad_rxq_post(bnad
, ccb
->rcb
[0]);
736 bnad_rxq_post(bnad
, ccb
->rcb
[1]);
742 bnad_netif_rx_schedule_poll(struct bnad
*bnad
, struct bna_ccb
*ccb
)
744 struct bnad_rx_ctrl
*rx_ctrl
= (struct bnad_rx_ctrl
*)(ccb
->ctrl
);
745 struct napi_struct
*napi
= &rx_ctrl
->napi
;
747 if (likely(napi_schedule_prep(napi
))) {
748 __napi_schedule(napi
);
749 rx_ctrl
->rx_schedule
++;
753 /* MSIX Rx Path Handler */
755 bnad_msix_rx(int irq
, void *data
)
757 struct bna_ccb
*ccb
= (struct bna_ccb
*)data
;
760 ((struct bnad_rx_ctrl
*)ccb
->ctrl
)->rx_intr_ctr
++;
761 bnad_netif_rx_schedule_poll(ccb
->bnad
, ccb
);
767 /* Interrupt handlers */
769 /* Mbox Interrupt Handlers */
771 bnad_msix_mbox_handler(int irq
, void *data
)
775 struct bnad
*bnad
= (struct bnad
*)data
;
777 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
778 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
))) {
779 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
783 bna_intr_status_get(&bnad
->bna
, intr_status
);
785 if (BNA_IS_MBOX_ERR_INTR(&bnad
->bna
, intr_status
))
786 bna_mbox_handler(&bnad
->bna
, intr_status
);
788 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
794 bnad_isr(int irq
, void *data
)
799 struct bnad
*bnad
= (struct bnad
*)data
;
800 struct bnad_rx_info
*rx_info
;
801 struct bnad_rx_ctrl
*rx_ctrl
;
802 struct bna_tcb
*tcb
= NULL
;
804 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
805 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
))) {
806 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
810 bna_intr_status_get(&bnad
->bna
, intr_status
);
812 if (unlikely(!intr_status
)) {
813 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
817 if (BNA_IS_MBOX_ERR_INTR(&bnad
->bna
, intr_status
))
818 bna_mbox_handler(&bnad
->bna
, intr_status
);
820 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
822 if (!BNA_IS_INTX_DATA_INTR(intr_status
))
825 /* Process data interrupts */
827 for (i
= 0; i
< bnad
->num_tx
; i
++) {
828 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
829 tcb
= bnad
->tx_info
[i
].tcb
[j
];
830 if (tcb
&& test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))
831 bnad_tx_complete(bnad
, bnad
->tx_info
[i
].tcb
[j
]);
835 for (i
= 0; i
< bnad
->num_rx
; i
++) {
836 rx_info
= &bnad
->rx_info
[i
];
839 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
840 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
842 bnad_netif_rx_schedule_poll(bnad
,
850 * Called in interrupt / callback context
851 * with bna_lock held, so cfg_flags access is OK
854 bnad_enable_mbox_irq(struct bnad
*bnad
)
856 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
858 BNAD_UPDATE_CTR(bnad
, mbox_intr_enabled
);
862 * Called with bnad->bna_lock held b'cos of
863 * bnad->cfg_flags access.
866 bnad_disable_mbox_irq(struct bnad
*bnad
)
868 set_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
870 BNAD_UPDATE_CTR(bnad
, mbox_intr_disabled
);
874 bnad_set_netdev_perm_addr(struct bnad
*bnad
)
876 struct net_device
*netdev
= bnad
->netdev
;
878 ether_addr_copy(netdev
->perm_addr
, bnad
->perm_addr
);
879 if (is_zero_ether_addr(netdev
->dev_addr
))
880 ether_addr_copy(netdev
->dev_addr
, bnad
->perm_addr
);
883 /* Control Path Handlers */
887 bnad_cb_mbox_intr_enable(struct bnad
*bnad
)
889 bnad_enable_mbox_irq(bnad
);
893 bnad_cb_mbox_intr_disable(struct bnad
*bnad
)
895 bnad_disable_mbox_irq(bnad
);
899 bnad_cb_ioceth_ready(struct bnad
*bnad
)
901 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_SUCCESS
;
902 complete(&bnad
->bnad_completions
.ioc_comp
);
906 bnad_cb_ioceth_failed(struct bnad
*bnad
)
908 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_FAIL
;
909 complete(&bnad
->bnad_completions
.ioc_comp
);
913 bnad_cb_ioceth_disabled(struct bnad
*bnad
)
915 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_SUCCESS
;
916 complete(&bnad
->bnad_completions
.ioc_comp
);
920 bnad_cb_enet_disabled(void *arg
)
922 struct bnad
*bnad
= (struct bnad
*)arg
;
924 netif_carrier_off(bnad
->netdev
);
925 complete(&bnad
->bnad_completions
.enet_comp
);
929 bnad_cb_ethport_link_status(struct bnad
*bnad
,
930 enum bna_link_status link_status
)
932 bool link_up
= false;
934 link_up
= (link_status
== BNA_LINK_UP
) || (link_status
== BNA_CEE_UP
);
936 if (link_status
== BNA_CEE_UP
) {
937 if (!test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
))
938 BNAD_UPDATE_CTR(bnad
, cee_toggle
);
939 set_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
);
941 if (test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
))
942 BNAD_UPDATE_CTR(bnad
, cee_toggle
);
943 clear_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
);
947 if (!netif_carrier_ok(bnad
->netdev
)) {
949 netdev_info(bnad
->netdev
, "link up\n");
950 netif_carrier_on(bnad
->netdev
);
951 BNAD_UPDATE_CTR(bnad
, link_toggle
);
952 for (tx_id
= 0; tx_id
< bnad
->num_tx
; tx_id
++) {
953 for (tcb_id
= 0; tcb_id
< bnad
->num_txq_per_tx
;
955 struct bna_tcb
*tcb
=
956 bnad
->tx_info
[tx_id
].tcb
[tcb_id
];
963 if (test_bit(BNAD_TXQ_TX_STARTED
,
967 * Transmit Schedule */
971 BNAD_UPDATE_CTR(bnad
,
977 BNAD_UPDATE_CTR(bnad
,
984 if (netif_carrier_ok(bnad
->netdev
)) {
985 netdev_info(bnad
->netdev
, "link down\n");
986 netif_carrier_off(bnad
->netdev
);
987 BNAD_UPDATE_CTR(bnad
, link_toggle
);
993 bnad_cb_tx_disabled(void *arg
, struct bna_tx
*tx
)
995 struct bnad
*bnad
= (struct bnad
*)arg
;
997 complete(&bnad
->bnad_completions
.tx_comp
);
1001 bnad_cb_tcb_setup(struct bnad
*bnad
, struct bna_tcb
*tcb
)
1003 struct bnad_tx_info
*tx_info
=
1004 (struct bnad_tx_info
*)tcb
->txq
->tx
->priv
;
1007 tx_info
->tcb
[tcb
->id
] = tcb
;
1011 bnad_cb_tcb_destroy(struct bnad
*bnad
, struct bna_tcb
*tcb
)
1013 struct bnad_tx_info
*tx_info
=
1014 (struct bnad_tx_info
*)tcb
->txq
->tx
->priv
;
1016 tx_info
->tcb
[tcb
->id
] = NULL
;
1021 bnad_cb_ccb_setup(struct bnad
*bnad
, struct bna_ccb
*ccb
)
1023 struct bnad_rx_info
*rx_info
=
1024 (struct bnad_rx_info
*)ccb
->cq
->rx
->priv
;
1026 rx_info
->rx_ctrl
[ccb
->id
].ccb
= ccb
;
1027 ccb
->ctrl
= &rx_info
->rx_ctrl
[ccb
->id
];
1031 bnad_cb_ccb_destroy(struct bnad
*bnad
, struct bna_ccb
*ccb
)
1033 struct bnad_rx_info
*rx_info
=
1034 (struct bnad_rx_info
*)ccb
->cq
->rx
->priv
;
1036 rx_info
->rx_ctrl
[ccb
->id
].ccb
= NULL
;
1040 bnad_cb_tx_stall(struct bnad
*bnad
, struct bna_tx
*tx
)
1042 struct bnad_tx_info
*tx_info
=
1043 (struct bnad_tx_info
*)tx
->priv
;
1044 struct bna_tcb
*tcb
;
1048 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
1049 tcb
= tx_info
->tcb
[i
];
1053 clear_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
);
1054 netif_stop_subqueue(bnad
->netdev
, txq_id
);
1059 bnad_cb_tx_resume(struct bnad
*bnad
, struct bna_tx
*tx
)
1061 struct bnad_tx_info
*tx_info
= (struct bnad_tx_info
*)tx
->priv
;
1062 struct bna_tcb
*tcb
;
1066 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
1067 tcb
= tx_info
->tcb
[i
];
1072 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
));
1073 set_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
);
1074 BUG_ON(*(tcb
->hw_consumer_index
) != 0);
1076 if (netif_carrier_ok(bnad
->netdev
)) {
1077 netif_wake_subqueue(bnad
->netdev
, txq_id
);
1078 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
1083 * Workaround for first ioceth enable failure & we
1084 * get a 0 MAC address. We try to get the MAC address
1087 if (is_zero_ether_addr(bnad
->perm_addr
)) {
1088 bna_enet_perm_mac_get(&bnad
->bna
.enet
, bnad
->perm_addr
);
1089 bnad_set_netdev_perm_addr(bnad
);
1094 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
1097 bnad_tx_cleanup(struct delayed_work
*work
)
1099 struct bnad_tx_info
*tx_info
=
1100 container_of(work
, struct bnad_tx_info
, tx_cleanup_work
);
1101 struct bnad
*bnad
= NULL
;
1102 struct bna_tcb
*tcb
;
1103 unsigned long flags
;
1106 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
1107 tcb
= tx_info
->tcb
[i
];
1113 if (test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
)) {
1118 bnad_txq_cleanup(bnad
, tcb
);
1120 smp_mb__before_atomic();
1121 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
1125 queue_delayed_work(bnad
->work_q
, &tx_info
->tx_cleanup_work
,
1126 msecs_to_jiffies(1));
1130 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1131 bna_tx_cleanup_complete(tx_info
->tx
);
1132 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1136 bnad_cb_tx_cleanup(struct bnad
*bnad
, struct bna_tx
*tx
)
1138 struct bnad_tx_info
*tx_info
= (struct bnad_tx_info
*)tx
->priv
;
1139 struct bna_tcb
*tcb
;
1142 for (i
= 0; i
< BNAD_MAX_TXQ_PER_TX
; i
++) {
1143 tcb
= tx_info
->tcb
[i
];
1148 queue_delayed_work(bnad
->work_q
, &tx_info
->tx_cleanup_work
, 0);
1152 bnad_cb_rx_stall(struct bnad
*bnad
, struct bna_rx
*rx
)
1154 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
1155 struct bna_ccb
*ccb
;
1156 struct bnad_rx_ctrl
*rx_ctrl
;
1159 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1160 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1165 clear_bit(BNAD_RXQ_POST_OK
, &ccb
->rcb
[0]->flags
);
1168 clear_bit(BNAD_RXQ_POST_OK
, &ccb
->rcb
[1]->flags
);
1173 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1176 bnad_rx_cleanup(void *work
)
1178 struct bnad_rx_info
*rx_info
=
1179 container_of(work
, struct bnad_rx_info
, rx_cleanup_work
);
1180 struct bnad_rx_ctrl
*rx_ctrl
;
1181 struct bnad
*bnad
= NULL
;
1182 unsigned long flags
;
1185 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1186 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1191 bnad
= rx_ctrl
->ccb
->bnad
;
1194 * Wait till the poll handler has exited
1195 * and nothing can be scheduled anymore
1197 napi_disable(&rx_ctrl
->napi
);
1199 bnad_cq_cleanup(bnad
, rx_ctrl
->ccb
);
1200 bnad_rxq_cleanup(bnad
, rx_ctrl
->ccb
->rcb
[0]);
1201 if (rx_ctrl
->ccb
->rcb
[1])
1202 bnad_rxq_cleanup(bnad
, rx_ctrl
->ccb
->rcb
[1]);
1205 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1206 bna_rx_cleanup_complete(rx_info
->rx
);
1207 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1211 bnad_cb_rx_cleanup(struct bnad
*bnad
, struct bna_rx
*rx
)
1213 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
1214 struct bna_ccb
*ccb
;
1215 struct bnad_rx_ctrl
*rx_ctrl
;
1218 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1219 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1224 clear_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[0]->flags
);
1227 clear_bit(BNAD_RXQ_STARTED
, &ccb
->rcb
[1]->flags
);
1230 queue_work(bnad
->work_q
, &rx_info
->rx_cleanup_work
);
1234 bnad_cb_rx_post(struct bnad
*bnad
, struct bna_rx
*rx
)
1236 struct bnad_rx_info
*rx_info
= (struct bnad_rx_info
*)rx
->priv
;
1237 struct bna_ccb
*ccb
;
1238 struct bna_rcb
*rcb
;
1239 struct bnad_rx_ctrl
*rx_ctrl
;
1242 for (i
= 0; i
< BNAD_MAX_RXP_PER_RX
; i
++) {
1243 rx_ctrl
= &rx_info
->rx_ctrl
[i
];
1248 napi_enable(&rx_ctrl
->napi
);
1250 for (j
= 0; j
< BNAD_MAX_RXQ_PER_RXP
; j
++) {
1255 bnad_rxq_alloc_init(bnad
, rcb
);
1256 set_bit(BNAD_RXQ_STARTED
, &rcb
->flags
);
1257 set_bit(BNAD_RXQ_POST_OK
, &rcb
->flags
);
1258 bnad_rxq_post(bnad
, rcb
);
1264 bnad_cb_rx_disabled(void *arg
, struct bna_rx
*rx
)
1266 struct bnad
*bnad
= (struct bnad
*)arg
;
1268 complete(&bnad
->bnad_completions
.rx_comp
);
1272 bnad_cb_rx_mcast_add(struct bnad
*bnad
, struct bna_rx
*rx
)
1274 bnad
->bnad_completions
.mcast_comp_status
= BNA_CB_SUCCESS
;
1275 complete(&bnad
->bnad_completions
.mcast_comp
);
1279 bnad_cb_stats_get(struct bnad
*bnad
, enum bna_cb_status status
,
1280 struct bna_stats
*stats
)
1282 if (status
== BNA_CB_SUCCESS
)
1283 BNAD_UPDATE_CTR(bnad
, hw_stats_updates
);
1285 if (!netif_running(bnad
->netdev
) ||
1286 !test_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1289 mod_timer(&bnad
->stats_timer
,
1290 jiffies
+ msecs_to_jiffies(BNAD_STATS_TIMER_FREQ
));
1294 bnad_cb_enet_mtu_set(struct bnad
*bnad
)
1296 bnad
->bnad_completions
.mtu_comp_status
= BNA_CB_SUCCESS
;
1297 complete(&bnad
->bnad_completions
.mtu_comp
);
1301 bnad_cb_completion(void *arg
, enum bfa_status status
)
1303 struct bnad_iocmd_comp
*iocmd_comp
=
1304 (struct bnad_iocmd_comp
*)arg
;
1306 iocmd_comp
->comp_status
= (u32
) status
;
1307 complete(&iocmd_comp
->comp
);
1310 /* Resource allocation, free functions */
1313 bnad_mem_free(struct bnad
*bnad
,
1314 struct bna_mem_info
*mem_info
)
1319 if (mem_info
->mdl
== NULL
)
1322 for (i
= 0; i
< mem_info
->num
; i
++) {
1323 if (mem_info
->mdl
[i
].kva
!= NULL
) {
1324 if (mem_info
->mem_type
== BNA_MEM_T_DMA
) {
1325 BNA_GET_DMA_ADDR(&(mem_info
->mdl
[i
].dma
),
1327 dma_free_coherent(&bnad
->pcidev
->dev
,
1328 mem_info
->mdl
[i
].len
,
1329 mem_info
->mdl
[i
].kva
, dma_pa
);
1331 kfree(mem_info
->mdl
[i
].kva
);
1334 kfree(mem_info
->mdl
);
1335 mem_info
->mdl
= NULL
;
1339 bnad_mem_alloc(struct bnad
*bnad
,
1340 struct bna_mem_info
*mem_info
)
1345 if ((mem_info
->num
== 0) || (mem_info
->len
== 0)) {
1346 mem_info
->mdl
= NULL
;
1350 mem_info
->mdl
= kcalloc(mem_info
->num
, sizeof(struct bna_mem_descr
),
1352 if (mem_info
->mdl
== NULL
)
1355 if (mem_info
->mem_type
== BNA_MEM_T_DMA
) {
1356 for (i
= 0; i
< mem_info
->num
; i
++) {
1357 mem_info
->mdl
[i
].len
= mem_info
->len
;
1358 mem_info
->mdl
[i
].kva
=
1359 dma_alloc_coherent(&bnad
->pcidev
->dev
,
1360 mem_info
->len
, &dma_pa
,
1362 if (mem_info
->mdl
[i
].kva
== NULL
)
1365 BNA_SET_DMA_ADDR(dma_pa
,
1366 &(mem_info
->mdl
[i
].dma
));
1369 for (i
= 0; i
< mem_info
->num
; i
++) {
1370 mem_info
->mdl
[i
].len
= mem_info
->len
;
1371 mem_info
->mdl
[i
].kva
= kzalloc(mem_info
->len
,
1373 if (mem_info
->mdl
[i
].kva
== NULL
)
1381 bnad_mem_free(bnad
, mem_info
);
1385 /* Free IRQ for Mailbox */
1387 bnad_mbox_irq_free(struct bnad
*bnad
)
1390 unsigned long flags
;
1392 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1393 bnad_disable_mbox_irq(bnad
);
1394 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1396 irq
= BNAD_GET_MBOX_IRQ(bnad
);
1397 free_irq(irq
, bnad
);
1401 * Allocates IRQ for Mailbox, but keep it disabled
1402 * This will be enabled once we get the mbox enable callback
1406 bnad_mbox_irq_alloc(struct bnad
*bnad
)
1409 unsigned long irq_flags
, flags
;
1411 irq_handler_t irq_handler
;
1413 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1414 if (bnad
->cfg_flags
& BNAD_CF_MSIX
) {
1415 irq_handler
= (irq_handler_t
)bnad_msix_mbox_handler
;
1416 irq
= bnad
->msix_table
[BNAD_MAILBOX_MSIX_INDEX
].vector
;
1419 irq_handler
= (irq_handler_t
)bnad_isr
;
1420 irq
= bnad
->pcidev
->irq
;
1421 irq_flags
= IRQF_SHARED
;
1424 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1425 sprintf(bnad
->mbox_irq_name
, "%s", BNAD_NAME
);
1428 * Set the Mbox IRQ disable flag, so that the IRQ handler
1429 * called from request_irq() for SHARED IRQs do not execute
1431 set_bit(BNAD_RF_MBOX_IRQ_DISABLED
, &bnad
->run_flags
);
1433 BNAD_UPDATE_CTR(bnad
, mbox_intr_disabled
);
1435 err
= request_irq(irq
, irq_handler
, irq_flags
,
1436 bnad
->mbox_irq_name
, bnad
);
1442 bnad_txrx_irq_free(struct bnad
*bnad
, struct bna_intr_info
*intr_info
)
1444 kfree(intr_info
->idl
);
1445 intr_info
->idl
= NULL
;
1448 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1450 bnad_txrx_irq_alloc(struct bnad
*bnad
, enum bnad_intr_source src
,
1451 u32 txrx_id
, struct bna_intr_info
*intr_info
)
1453 int i
, vector_start
= 0;
1455 unsigned long flags
;
1457 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1458 cfg_flags
= bnad
->cfg_flags
;
1459 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1461 if (cfg_flags
& BNAD_CF_MSIX
) {
1462 intr_info
->intr_type
= BNA_INTR_T_MSIX
;
1463 intr_info
->idl
= kcalloc(intr_info
->num
,
1464 sizeof(struct bna_intr_descr
),
1466 if (!intr_info
->idl
)
1471 vector_start
= BNAD_MAILBOX_MSIX_VECTORS
+ txrx_id
;
1475 vector_start
= BNAD_MAILBOX_MSIX_VECTORS
+
1476 (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
1484 for (i
= 0; i
< intr_info
->num
; i
++)
1485 intr_info
->idl
[i
].vector
= vector_start
+ i
;
1487 intr_info
->intr_type
= BNA_INTR_T_INTX
;
1489 intr_info
->idl
= kcalloc(intr_info
->num
,
1490 sizeof(struct bna_intr_descr
),
1492 if (!intr_info
->idl
)
1497 intr_info
->idl
[0].vector
= BNAD_INTX_TX_IB_BITMASK
;
1501 intr_info
->idl
[0].vector
= BNAD_INTX_RX_IB_BITMASK
;
1508 /* NOTE: Should be called for MSIX only
1509 * Unregisters Tx MSIX vector(s) from the kernel
1512 bnad_tx_msix_unregister(struct bnad
*bnad
, struct bnad_tx_info
*tx_info
,
1518 for (i
= 0; i
< num_txqs
; i
++) {
1519 if (tx_info
->tcb
[i
] == NULL
)
1522 vector_num
= tx_info
->tcb
[i
]->intr_vector
;
1523 free_irq(bnad
->msix_table
[vector_num
].vector
, tx_info
->tcb
[i
]);
1527 /* NOTE: Should be called for MSIX only
1528 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1531 bnad_tx_msix_register(struct bnad
*bnad
, struct bnad_tx_info
*tx_info
,
1532 u32 tx_id
, int num_txqs
)
1538 for (i
= 0; i
< num_txqs
; i
++) {
1539 vector_num
= tx_info
->tcb
[i
]->intr_vector
;
1540 sprintf(tx_info
->tcb
[i
]->name
, "%s TXQ %d", bnad
->netdev
->name
,
1541 tx_id
+ tx_info
->tcb
[i
]->id
);
1542 err
= request_irq(bnad
->msix_table
[vector_num
].vector
,
1543 (irq_handler_t
)bnad_msix_tx
, 0,
1544 tx_info
->tcb
[i
]->name
,
1554 bnad_tx_msix_unregister(bnad
, tx_info
, (i
- 1));
1558 /* NOTE: Should be called for MSIX only
1559 * Unregisters Rx MSIX vector(s) from the kernel
1562 bnad_rx_msix_unregister(struct bnad
*bnad
, struct bnad_rx_info
*rx_info
,
1568 for (i
= 0; i
< num_rxps
; i
++) {
1569 if (rx_info
->rx_ctrl
[i
].ccb
== NULL
)
1572 vector_num
= rx_info
->rx_ctrl
[i
].ccb
->intr_vector
;
1573 free_irq(bnad
->msix_table
[vector_num
].vector
,
1574 rx_info
->rx_ctrl
[i
].ccb
);
1578 /* NOTE: Should be called for MSIX only
1579 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1582 bnad_rx_msix_register(struct bnad
*bnad
, struct bnad_rx_info
*rx_info
,
1583 u32 rx_id
, int num_rxps
)
1589 for (i
= 0; i
< num_rxps
; i
++) {
1590 vector_num
= rx_info
->rx_ctrl
[i
].ccb
->intr_vector
;
1591 sprintf(rx_info
->rx_ctrl
[i
].ccb
->name
, "%s CQ %d",
1593 rx_id
+ rx_info
->rx_ctrl
[i
].ccb
->id
);
1594 err
= request_irq(bnad
->msix_table
[vector_num
].vector
,
1595 (irq_handler_t
)bnad_msix_rx
, 0,
1596 rx_info
->rx_ctrl
[i
].ccb
->name
,
1597 rx_info
->rx_ctrl
[i
].ccb
);
1606 bnad_rx_msix_unregister(bnad
, rx_info
, (i
- 1));
1610 /* Free Tx object Resources */
1612 bnad_tx_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
)
1616 for (i
= 0; i
< BNA_TX_RES_T_MAX
; i
++) {
1617 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1618 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
1619 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1620 bnad_txrx_irq_free(bnad
, &res_info
[i
].res_u
.intr_info
);
1624 /* Allocates memory and interrupt resources for Tx object */
1626 bnad_tx_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
1631 for (i
= 0; i
< BNA_TX_RES_T_MAX
; i
++) {
1632 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1633 err
= bnad_mem_alloc(bnad
,
1634 &res_info
[i
].res_u
.mem_info
);
1635 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1636 err
= bnad_txrx_irq_alloc(bnad
, BNAD_INTR_TX
, tx_id
,
1637 &res_info
[i
].res_u
.intr_info
);
1644 bnad_tx_res_free(bnad
, res_info
);
1648 /* Free Rx object Resources */
1650 bnad_rx_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
)
1654 for (i
= 0; i
< BNA_RX_RES_T_MAX
; i
++) {
1655 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1656 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
1657 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1658 bnad_txrx_irq_free(bnad
, &res_info
[i
].res_u
.intr_info
);
1662 /* Allocates memory and interrupt resources for Rx object */
1664 bnad_rx_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
1669 /* All memory needs to be allocated before setup_ccbs */
1670 for (i
= 0; i
< BNA_RX_RES_T_MAX
; i
++) {
1671 if (res_info
[i
].res_type
== BNA_RES_T_MEM
)
1672 err
= bnad_mem_alloc(bnad
,
1673 &res_info
[i
].res_u
.mem_info
);
1674 else if (res_info
[i
].res_type
== BNA_RES_T_INTR
)
1675 err
= bnad_txrx_irq_alloc(bnad
, BNAD_INTR_RX
, rx_id
,
1676 &res_info
[i
].res_u
.intr_info
);
1683 bnad_rx_res_free(bnad
, res_info
);
1687 /* Timer callbacks */
1690 bnad_ioc_timeout(unsigned long data
)
1692 struct bnad
*bnad
= (struct bnad
*)data
;
1693 unsigned long flags
;
1695 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1696 bfa_nw_ioc_timeout(&bnad
->bna
.ioceth
.ioc
);
1697 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1701 bnad_ioc_hb_check(unsigned long data
)
1703 struct bnad
*bnad
= (struct bnad
*)data
;
1704 unsigned long flags
;
1706 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1707 bfa_nw_ioc_hb_check(&bnad
->bna
.ioceth
.ioc
);
1708 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1712 bnad_iocpf_timeout(unsigned long data
)
1714 struct bnad
*bnad
= (struct bnad
*)data
;
1715 unsigned long flags
;
1717 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1718 bfa_nw_iocpf_timeout(&bnad
->bna
.ioceth
.ioc
);
1719 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1723 bnad_iocpf_sem_timeout(unsigned long data
)
1725 struct bnad
*bnad
= (struct bnad
*)data
;
1726 unsigned long flags
;
1728 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1729 bfa_nw_iocpf_sem_timeout(&bnad
->bna
.ioceth
.ioc
);
1730 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1734 * All timer routines use bnad->bna_lock to protect against
1735 * the following race, which may occur in case of no locking:
1743 /* b) Dynamic Interrupt Moderation Timer */
1745 bnad_dim_timeout(unsigned long data
)
1747 struct bnad
*bnad
= (struct bnad
*)data
;
1748 struct bnad_rx_info
*rx_info
;
1749 struct bnad_rx_ctrl
*rx_ctrl
;
1751 unsigned long flags
;
1753 if (!netif_carrier_ok(bnad
->netdev
))
1756 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1757 for (i
= 0; i
< bnad
->num_rx
; i
++) {
1758 rx_info
= &bnad
->rx_info
[i
];
1761 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
1762 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
1765 bna_rx_dim_update(rx_ctrl
->ccb
);
1769 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1770 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
))
1771 mod_timer(&bnad
->dim_timer
,
1772 jiffies
+ msecs_to_jiffies(BNAD_DIM_TIMER_FREQ
));
1773 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1776 /* c) Statistics Timer */
1778 bnad_stats_timeout(unsigned long data
)
1780 struct bnad
*bnad
= (struct bnad
*)data
;
1781 unsigned long flags
;
1783 if (!netif_running(bnad
->netdev
) ||
1784 !test_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1787 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1788 bna_hw_stats_get(&bnad
->bna
);
1789 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1793 * Set up timer for DIM
1794 * Called with bnad->bna_lock held
1797 bnad_dim_timer_start(struct bnad
*bnad
)
1799 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
&&
1800 !test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
)) {
1801 setup_timer(&bnad
->dim_timer
, bnad_dim_timeout
,
1802 (unsigned long)bnad
);
1803 set_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
);
1804 mod_timer(&bnad
->dim_timer
,
1805 jiffies
+ msecs_to_jiffies(BNAD_DIM_TIMER_FREQ
));
1810 * Set up timer for statistics
1811 * Called with mutex_lock(&bnad->conf_mutex) held
1814 bnad_stats_timer_start(struct bnad
*bnad
)
1816 unsigned long flags
;
1818 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1819 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
)) {
1820 setup_timer(&bnad
->stats_timer
, bnad_stats_timeout
,
1821 (unsigned long)bnad
);
1822 mod_timer(&bnad
->stats_timer
,
1823 jiffies
+ msecs_to_jiffies(BNAD_STATS_TIMER_FREQ
));
1825 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1829 * Stops the stats timer
1830 * Called with mutex_lock(&bnad->conf_mutex) held
1833 bnad_stats_timer_stop(struct bnad
*bnad
)
1836 unsigned long flags
;
1838 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1839 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING
, &bnad
->run_flags
))
1841 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1843 del_timer_sync(&bnad
->stats_timer
);
1849 bnad_netdev_mc_list_get(struct net_device
*netdev
, u8
*mc_list
)
1851 int i
= 1; /* Index 0 has broadcast address */
1852 struct netdev_hw_addr
*mc_addr
;
1854 netdev_for_each_mc_addr(mc_addr
, netdev
) {
1855 ether_addr_copy(&mc_list
[i
* ETH_ALEN
], &mc_addr
->addr
[0]);
1861 bnad_napi_poll_rx(struct napi_struct
*napi
, int budget
)
1863 struct bnad_rx_ctrl
*rx_ctrl
=
1864 container_of(napi
, struct bnad_rx_ctrl
, napi
);
1865 struct bnad
*bnad
= rx_ctrl
->bnad
;
1868 rx_ctrl
->rx_poll_ctr
++;
1870 if (!netif_carrier_ok(bnad
->netdev
))
1873 rcvd
= bnad_cq_process(bnad
, rx_ctrl
->ccb
, budget
);
1878 napi_complete(napi
);
1880 rx_ctrl
->rx_complete
++;
1883 bnad_enable_rx_irq_unsafe(rx_ctrl
->ccb
);
1888 #define BNAD_NAPI_POLL_QUOTA 64
1890 bnad_napi_add(struct bnad
*bnad
, u32 rx_id
)
1892 struct bnad_rx_ctrl
*rx_ctrl
;
1895 /* Initialize & enable NAPI */
1896 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++) {
1897 rx_ctrl
= &bnad
->rx_info
[rx_id
].rx_ctrl
[i
];
1898 netif_napi_add(bnad
->netdev
, &rx_ctrl
->napi
,
1899 bnad_napi_poll_rx
, BNAD_NAPI_POLL_QUOTA
);
1904 bnad_napi_delete(struct bnad
*bnad
, u32 rx_id
)
1908 /* First disable and then clean up */
1909 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++)
1910 netif_napi_del(&bnad
->rx_info
[rx_id
].rx_ctrl
[i
].napi
);
1913 /* Should be held with conf_lock held */
1915 bnad_destroy_tx(struct bnad
*bnad
, u32 tx_id
)
1917 struct bnad_tx_info
*tx_info
= &bnad
->tx_info
[tx_id
];
1918 struct bna_res_info
*res_info
= &bnad
->tx_res_info
[tx_id
].res_info
[0];
1919 unsigned long flags
;
1924 init_completion(&bnad
->bnad_completions
.tx_comp
);
1925 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1926 bna_tx_disable(tx_info
->tx
, BNA_HARD_CLEANUP
, bnad_cb_tx_disabled
);
1927 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1928 wait_for_completion(&bnad
->bnad_completions
.tx_comp
);
1930 if (tx_info
->tcb
[0]->intr_type
== BNA_INTR_T_MSIX
)
1931 bnad_tx_msix_unregister(bnad
, tx_info
,
1932 bnad
->num_txq_per_tx
);
1934 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1935 bna_tx_destroy(tx_info
->tx
);
1936 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1941 bnad_tx_res_free(bnad
, res_info
);
1944 /* Should be held with conf_lock held */
1946 bnad_setup_tx(struct bnad
*bnad
, u32 tx_id
)
1949 struct bnad_tx_info
*tx_info
= &bnad
->tx_info
[tx_id
];
1950 struct bna_res_info
*res_info
= &bnad
->tx_res_info
[tx_id
].res_info
[0];
1951 struct bna_intr_info
*intr_info
=
1952 &res_info
[BNA_TX_RES_INTR_T_TXCMPL
].res_u
.intr_info
;
1953 struct bna_tx_config
*tx_config
= &bnad
->tx_config
[tx_id
];
1954 static const struct bna_tx_event_cbfn tx_cbfn
= {
1955 .tcb_setup_cbfn
= bnad_cb_tcb_setup
,
1956 .tcb_destroy_cbfn
= bnad_cb_tcb_destroy
,
1957 .tx_stall_cbfn
= bnad_cb_tx_stall
,
1958 .tx_resume_cbfn
= bnad_cb_tx_resume
,
1959 .tx_cleanup_cbfn
= bnad_cb_tx_cleanup
,
1963 unsigned long flags
;
1965 tx_info
->tx_id
= tx_id
;
1967 /* Initialize the Tx object configuration */
1968 tx_config
->num_txq
= bnad
->num_txq_per_tx
;
1969 tx_config
->txq_depth
= bnad
->txq_depth
;
1970 tx_config
->tx_type
= BNA_TX_T_REGULAR
;
1971 tx_config
->coalescing_timeo
= bnad
->tx_coalescing_timeo
;
1973 /* Get BNA's resource requirement for one tx object */
1974 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1975 bna_tx_res_req(bnad
->num_txq_per_tx
,
1976 bnad
->txq_depth
, res_info
);
1977 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
1979 /* Fill Unmap Q memory requirements */
1980 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info
[BNA_TX_RES_MEM_T_UNMAPQ
],
1981 bnad
->num_txq_per_tx
, (sizeof(struct bnad_tx_unmap
) *
1984 /* Allocate resources */
1985 err
= bnad_tx_res_alloc(bnad
, res_info
, tx_id
);
1989 /* Ask BNA to create one Tx object, supplying required resources */
1990 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
1991 tx
= bna_tx_create(&bnad
->bna
, bnad
, tx_config
, &tx_cbfn
, res_info
,
1993 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2000 INIT_DELAYED_WORK(&tx_info
->tx_cleanup_work
,
2001 (work_func_t
)bnad_tx_cleanup
);
2003 /* Register ISR for the Tx object */
2004 if (intr_info
->intr_type
== BNA_INTR_T_MSIX
) {
2005 err
= bnad_tx_msix_register(bnad
, tx_info
,
2006 tx_id
, bnad
->num_txq_per_tx
);
2011 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2013 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2018 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2019 bna_tx_destroy(tx_info
->tx
);
2020 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2024 bnad_tx_res_free(bnad
, res_info
);
2028 /* Setup the rx config for bna_rx_create */
2029 /* bnad decides the configuration */
2031 bnad_init_rx_config(struct bnad
*bnad
, struct bna_rx_config
*rx_config
)
2033 memset(rx_config
, 0, sizeof(*rx_config
));
2034 rx_config
->rx_type
= BNA_RX_T_REGULAR
;
2035 rx_config
->num_paths
= bnad
->num_rxp_per_rx
;
2036 rx_config
->coalescing_timeo
= bnad
->rx_coalescing_timeo
;
2038 if (bnad
->num_rxp_per_rx
> 1) {
2039 rx_config
->rss_status
= BNA_STATUS_T_ENABLED
;
2040 rx_config
->rss_config
.hash_type
=
2041 (BFI_ENET_RSS_IPV6
|
2042 BFI_ENET_RSS_IPV6_TCP
|
2044 BFI_ENET_RSS_IPV4_TCP
);
2045 rx_config
->rss_config
.hash_mask
=
2046 bnad
->num_rxp_per_rx
- 1;
2047 netdev_rss_key_fill(rx_config
->rss_config
.toeplitz_hash_key
,
2048 sizeof(rx_config
->rss_config
.toeplitz_hash_key
));
2050 rx_config
->rss_status
= BNA_STATUS_T_DISABLED
;
2051 memset(&rx_config
->rss_config
, 0,
2052 sizeof(rx_config
->rss_config
));
2055 rx_config
->frame_size
= BNAD_FRAME_SIZE(bnad
->netdev
->mtu
);
2056 rx_config
->q0_multi_buf
= BNA_STATUS_T_DISABLED
;
2058 /* BNA_RXP_SINGLE - one data-buffer queue
2059 * BNA_RXP_SLR - one small-buffer and one large-buffer queues
2060 * BNA_RXP_HDS - one header-buffer and one data-buffer queues
2062 /* TODO: configurable param for queue type */
2063 rx_config
->rxp_type
= BNA_RXP_SLR
;
2065 if (BNAD_PCI_DEV_IS_CAT2(bnad
) &&
2066 rx_config
->frame_size
> 4096) {
2067 /* though size_routing_enable is set in SLR,
2068 * small packets may get routed to same rxq.
2069 * set buf_size to 2048 instead of PAGE_SIZE.
2071 rx_config
->q0_buf_size
= 2048;
2072 /* this should be in multiples of 2 */
2073 rx_config
->q0_num_vecs
= 4;
2074 rx_config
->q0_depth
= bnad
->rxq_depth
* rx_config
->q0_num_vecs
;
2075 rx_config
->q0_multi_buf
= BNA_STATUS_T_ENABLED
;
2077 rx_config
->q0_buf_size
= rx_config
->frame_size
;
2078 rx_config
->q0_num_vecs
= 1;
2079 rx_config
->q0_depth
= bnad
->rxq_depth
;
2082 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */
2083 if (rx_config
->rxp_type
== BNA_RXP_SLR
) {
2084 rx_config
->q1_depth
= bnad
->rxq_depth
;
2085 rx_config
->q1_buf_size
= BFI_SMALL_RXBUF_SIZE
;
2088 rx_config
->vlan_strip_status
=
2089 (bnad
->netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ?
2090 BNA_STATUS_T_ENABLED
: BNA_STATUS_T_DISABLED
;
2094 bnad_rx_ctrl_init(struct bnad
*bnad
, u32 rx_id
)
2096 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
2099 for (i
= 0; i
< bnad
->num_rxp_per_rx
; i
++)
2100 rx_info
->rx_ctrl
[i
].bnad
= bnad
;
2103 /* Called with mutex_lock(&bnad->conf_mutex) held */
2105 bnad_reinit_rx(struct bnad
*bnad
)
2107 struct net_device
*netdev
= bnad
->netdev
;
2108 u32 err
= 0, current_err
= 0;
2109 u32 rx_id
= 0, count
= 0;
2110 unsigned long flags
;
2112 /* destroy and create new rx objects */
2113 for (rx_id
= 0; rx_id
< bnad
->num_rx
; rx_id
++) {
2114 if (!bnad
->rx_info
[rx_id
].rx
)
2116 bnad_destroy_rx(bnad
, rx_id
);
2119 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2120 bna_enet_mtu_set(&bnad
->bna
.enet
,
2121 BNAD_FRAME_SIZE(bnad
->netdev
->mtu
), NULL
);
2122 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2124 for (rx_id
= 0; rx_id
< bnad
->num_rx
; rx_id
++) {
2126 current_err
= bnad_setup_rx(bnad
, rx_id
);
2127 if (current_err
&& !err
) {
2129 netdev_err(netdev
, "RXQ:%u setup failed\n", rx_id
);
2133 /* restore rx configuration */
2134 if (bnad
->rx_info
[0].rx
&& !err
) {
2135 bnad_restore_vlans(bnad
, 0);
2136 bnad_enable_default_bcast(bnad
);
2137 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2138 bnad_mac_addr_set_locked(bnad
, netdev
->dev_addr
);
2139 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2140 bnad_set_rx_mode(netdev
);
2146 /* Called with bnad_conf_lock() held */
2148 bnad_destroy_rx(struct bnad
*bnad
, u32 rx_id
)
2150 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
2151 struct bna_rx_config
*rx_config
= &bnad
->rx_config
[rx_id
];
2152 struct bna_res_info
*res_info
= &bnad
->rx_res_info
[rx_id
].res_info
[0];
2153 unsigned long flags
;
2160 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2161 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
&&
2162 test_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
)) {
2163 clear_bit(BNAD_RF_DIM_TIMER_RUNNING
, &bnad
->run_flags
);
2166 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2168 del_timer_sync(&bnad
->dim_timer
);
2171 init_completion(&bnad
->bnad_completions
.rx_comp
);
2172 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2173 bna_rx_disable(rx_info
->rx
, BNA_HARD_CLEANUP
, bnad_cb_rx_disabled
);
2174 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2175 wait_for_completion(&bnad
->bnad_completions
.rx_comp
);
2177 if (rx_info
->rx_ctrl
[0].ccb
->intr_type
== BNA_INTR_T_MSIX
)
2178 bnad_rx_msix_unregister(bnad
, rx_info
, rx_config
->num_paths
);
2180 bnad_napi_delete(bnad
, rx_id
);
2182 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2183 bna_rx_destroy(rx_info
->rx
);
2187 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2189 bnad_rx_res_free(bnad
, res_info
);
2192 /* Called with mutex_lock(&bnad->conf_mutex) held */
2194 bnad_setup_rx(struct bnad
*bnad
, u32 rx_id
)
2197 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[rx_id
];
2198 struct bna_res_info
*res_info
= &bnad
->rx_res_info
[rx_id
].res_info
[0];
2199 struct bna_intr_info
*intr_info
=
2200 &res_info
[BNA_RX_RES_T_INTR
].res_u
.intr_info
;
2201 struct bna_rx_config
*rx_config
= &bnad
->rx_config
[rx_id
];
2202 static const struct bna_rx_event_cbfn rx_cbfn
= {
2203 .rcb_setup_cbfn
= NULL
,
2204 .rcb_destroy_cbfn
= NULL
,
2205 .ccb_setup_cbfn
= bnad_cb_ccb_setup
,
2206 .ccb_destroy_cbfn
= bnad_cb_ccb_destroy
,
2207 .rx_stall_cbfn
= bnad_cb_rx_stall
,
2208 .rx_cleanup_cbfn
= bnad_cb_rx_cleanup
,
2209 .rx_post_cbfn
= bnad_cb_rx_post
,
2212 unsigned long flags
;
2214 rx_info
->rx_id
= rx_id
;
2216 /* Initialize the Rx object configuration */
2217 bnad_init_rx_config(bnad
, rx_config
);
2219 /* Get BNA's resource requirement for one Rx object */
2220 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2221 bna_rx_res_req(rx_config
, res_info
);
2222 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2224 /* Fill Unmap Q memory requirements */
2225 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info
[BNA_RX_RES_MEM_T_UNMAPDQ
],
2226 rx_config
->num_paths
,
2227 (rx_config
->q0_depth
*
2228 sizeof(struct bnad_rx_unmap
)) +
2229 sizeof(struct bnad_rx_unmap_q
));
2231 if (rx_config
->rxp_type
!= BNA_RXP_SINGLE
) {
2232 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info
[BNA_RX_RES_MEM_T_UNMAPHQ
],
2233 rx_config
->num_paths
,
2234 (rx_config
->q1_depth
*
2235 sizeof(struct bnad_rx_unmap
) +
2236 sizeof(struct bnad_rx_unmap_q
)));
2238 /* Allocate resource */
2239 err
= bnad_rx_res_alloc(bnad
, res_info
, rx_id
);
2243 bnad_rx_ctrl_init(bnad
, rx_id
);
2245 /* Ask BNA to create one Rx object, supplying required resources */
2246 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2247 rx
= bna_rx_create(&bnad
->bna
, bnad
, rx_config
, &rx_cbfn
, res_info
,
2251 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2255 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2257 INIT_WORK(&rx_info
->rx_cleanup_work
,
2258 (work_func_t
)(bnad_rx_cleanup
));
2261 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2262 * so that IRQ handler cannot schedule NAPI at this point.
2264 bnad_napi_add(bnad
, rx_id
);
2266 /* Register ISR for the Rx object */
2267 if (intr_info
->intr_type
== BNA_INTR_T_MSIX
) {
2268 err
= bnad_rx_msix_register(bnad
, rx_info
, rx_id
,
2269 rx_config
->num_paths
);
2274 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2276 /* Set up Dynamic Interrupt Moderation Vector */
2277 if (bnad
->cfg_flags
& BNAD_CF_DIM_ENABLED
)
2278 bna_rx_dim_reconfig(&bnad
->bna
, bna_napi_dim_vector
);
2280 /* Enable VLAN filtering only on the default Rx */
2281 bna_rx_vlanfilter_enable(rx
);
2283 /* Start the DIM timer */
2284 bnad_dim_timer_start(bnad
);
2288 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2293 bnad_destroy_rx(bnad
, rx_id
);
2297 /* Called with conf_lock & bnad->bna_lock held */
2299 bnad_tx_coalescing_timeo_set(struct bnad
*bnad
)
2301 struct bnad_tx_info
*tx_info
;
2303 tx_info
= &bnad
->tx_info
[0];
2307 bna_tx_coalescing_timeo_set(tx_info
->tx
, bnad
->tx_coalescing_timeo
);
2310 /* Called with conf_lock & bnad->bna_lock held */
2312 bnad_rx_coalescing_timeo_set(struct bnad
*bnad
)
2314 struct bnad_rx_info
*rx_info
;
2317 for (i
= 0; i
< bnad
->num_rx
; i
++) {
2318 rx_info
= &bnad
->rx_info
[i
];
2321 bna_rx_coalescing_timeo_set(rx_info
->rx
,
2322 bnad
->rx_coalescing_timeo
);
2327 * Called with bnad->bna_lock held
2330 bnad_mac_addr_set_locked(struct bnad
*bnad
, const u8
*mac_addr
)
2334 if (!is_valid_ether_addr(mac_addr
))
2335 return -EADDRNOTAVAIL
;
2337 /* If datapath is down, pretend everything went through */
2338 if (!bnad
->rx_info
[0].rx
)
2341 ret
= bna_rx_ucast_set(bnad
->rx_info
[0].rx
, mac_addr
);
2342 if (ret
!= BNA_CB_SUCCESS
)
2343 return -EADDRNOTAVAIL
;
2348 /* Should be called with conf_lock held */
2350 bnad_enable_default_bcast(struct bnad
*bnad
)
2352 struct bnad_rx_info
*rx_info
= &bnad
->rx_info
[0];
2354 unsigned long flags
;
2356 init_completion(&bnad
->bnad_completions
.mcast_comp
);
2358 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2359 ret
= bna_rx_mcast_add(rx_info
->rx
, bnad_bcast_addr
,
2360 bnad_cb_rx_mcast_add
);
2361 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2363 if (ret
== BNA_CB_SUCCESS
)
2364 wait_for_completion(&bnad
->bnad_completions
.mcast_comp
);
2368 if (bnad
->bnad_completions
.mcast_comp_status
!= BNA_CB_SUCCESS
)
2374 /* Called with mutex_lock(&bnad->conf_mutex) held */
2376 bnad_restore_vlans(struct bnad
*bnad
, u32 rx_id
)
2379 unsigned long flags
;
2381 for_each_set_bit(vid
, bnad
->active_vlans
, VLAN_N_VID
) {
2382 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2383 bna_rx_vlan_add(bnad
->rx_info
[rx_id
].rx
, vid
);
2384 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2388 /* Statistics utilities */
2390 bnad_netdev_qstats_fill(struct bnad
*bnad
, struct rtnl_link_stats64
*stats
)
2394 for (i
= 0; i
< bnad
->num_rx
; i
++) {
2395 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
2396 if (bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
) {
2397 stats
->rx_packets
+= bnad
->rx_info
[i
].
2398 rx_ctrl
[j
].ccb
->rcb
[0]->rxq
->rx_packets
;
2399 stats
->rx_bytes
+= bnad
->rx_info
[i
].
2400 rx_ctrl
[j
].ccb
->rcb
[0]->rxq
->rx_bytes
;
2401 if (bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
->rcb
[1] &&
2402 bnad
->rx_info
[i
].rx_ctrl
[j
].ccb
->
2404 stats
->rx_packets
+=
2405 bnad
->rx_info
[i
].rx_ctrl
[j
].
2406 ccb
->rcb
[1]->rxq
->rx_packets
;
2408 bnad
->rx_info
[i
].rx_ctrl
[j
].
2409 ccb
->rcb
[1]->rxq
->rx_bytes
;
2414 for (i
= 0; i
< bnad
->num_tx
; i
++) {
2415 for (j
= 0; j
< bnad
->num_txq_per_tx
; j
++) {
2416 if (bnad
->tx_info
[i
].tcb
[j
]) {
2417 stats
->tx_packets
+=
2418 bnad
->tx_info
[i
].tcb
[j
]->txq
->tx_packets
;
2420 bnad
->tx_info
[i
].tcb
[j
]->txq
->tx_bytes
;
2427 * Must be called with the bna_lock held.
2430 bnad_netdev_hwstats_fill(struct bnad
*bnad
, struct rtnl_link_stats64
*stats
)
2432 struct bfi_enet_stats_mac
*mac_stats
;
2436 mac_stats
= &bnad
->stats
.bna_stats
->hw_stats
.mac_stats
;
2438 mac_stats
->rx_fcs_error
+ mac_stats
->rx_alignment_error
+
2439 mac_stats
->rx_frame_length_error
+ mac_stats
->rx_code_error
+
2440 mac_stats
->rx_undersize
;
2441 stats
->tx_errors
= mac_stats
->tx_fcs_error
+
2442 mac_stats
->tx_undersize
;
2443 stats
->rx_dropped
= mac_stats
->rx_drop
;
2444 stats
->tx_dropped
= mac_stats
->tx_drop
;
2445 stats
->multicast
= mac_stats
->rx_multicast
;
2446 stats
->collisions
= mac_stats
->tx_total_collision
;
2448 stats
->rx_length_errors
= mac_stats
->rx_frame_length_error
;
2450 /* receive ring buffer overflow ?? */
2452 stats
->rx_crc_errors
= mac_stats
->rx_fcs_error
;
2453 stats
->rx_frame_errors
= mac_stats
->rx_alignment_error
;
2454 /* recv'r fifo overrun */
2455 bmap
= bna_rx_rid_mask(&bnad
->bna
);
2456 for (i
= 0; bmap
; i
++) {
2458 stats
->rx_fifo_errors
+=
2459 bnad
->stats
.bna_stats
->
2460 hw_stats
.rxf_stats
[i
].frame_drops
;
2468 bnad_mbox_irq_sync(struct bnad
*bnad
)
2471 unsigned long flags
;
2473 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2474 if (bnad
->cfg_flags
& BNAD_CF_MSIX
)
2475 irq
= bnad
->msix_table
[BNAD_MAILBOX_MSIX_INDEX
].vector
;
2477 irq
= bnad
->pcidev
->irq
;
2478 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2480 synchronize_irq(irq
);
2483 /* Utility used by bnad_start_xmit, for doing TSO */
2485 bnad_tso_prepare(struct bnad
*bnad
, struct sk_buff
*skb
)
2489 err
= skb_cow_head(skb
, 0);
2491 BNAD_UPDATE_CTR(bnad
, tso_err
);
2496 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2497 * excluding the length field.
2499 if (vlan_get_protocol(skb
) == htons(ETH_P_IP
)) {
2500 struct iphdr
*iph
= ip_hdr(skb
);
2502 /* Do we really need these? */
2506 tcp_hdr(skb
)->check
=
2507 ~csum_tcpudp_magic(iph
->saddr
, iph
->daddr
, 0,
2509 BNAD_UPDATE_CTR(bnad
, tso4
);
2511 struct ipv6hdr
*ipv6h
= ipv6_hdr(skb
);
2513 ipv6h
->payload_len
= 0;
2514 tcp_hdr(skb
)->check
=
2515 ~csum_ipv6_magic(&ipv6h
->saddr
, &ipv6h
->daddr
, 0,
2517 BNAD_UPDATE_CTR(bnad
, tso6
);
2524 * Initialize Q numbers depending on Rx Paths
2525 * Called with bnad->bna_lock held, because of cfg_flags
2529 bnad_q_num_init(struct bnad
*bnad
)
2533 rxps
= min((uint
)num_online_cpus(),
2534 (uint
)(BNAD_MAX_RX
* BNAD_MAX_RXP_PER_RX
));
2536 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
))
2537 rxps
= 1; /* INTx */
2541 bnad
->num_rxp_per_rx
= rxps
;
2542 bnad
->num_txq_per_tx
= BNAD_TXQ_NUM
;
2546 * Adjusts the Q numbers, given a number of msix vectors
2547 * Give preference to RSS as opposed to Tx priority Queues,
2548 * in such a case, just use 1 Tx Q
2549 * Called with bnad->bna_lock held b'cos of cfg_flags access
2552 bnad_q_num_adjust(struct bnad
*bnad
, int msix_vectors
, int temp
)
2554 bnad
->num_txq_per_tx
= 1;
2555 if ((msix_vectors
>= (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
2556 bnad_rxqs_per_cq
+ BNAD_MAILBOX_MSIX_VECTORS
) &&
2557 (bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2558 bnad
->num_rxp_per_rx
= msix_vectors
-
2559 (bnad
->num_tx
* bnad
->num_txq_per_tx
) -
2560 BNAD_MAILBOX_MSIX_VECTORS
;
2562 bnad
->num_rxp_per_rx
= 1;
2565 /* Enable / disable ioceth */
2567 bnad_ioceth_disable(struct bnad
*bnad
)
2569 unsigned long flags
;
2572 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2573 init_completion(&bnad
->bnad_completions
.ioc_comp
);
2574 bna_ioceth_disable(&bnad
->bna
.ioceth
, BNA_HARD_CLEANUP
);
2575 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2577 wait_for_completion_timeout(&bnad
->bnad_completions
.ioc_comp
,
2578 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT
));
2580 err
= bnad
->bnad_completions
.ioc_comp_status
;
2585 bnad_ioceth_enable(struct bnad
*bnad
)
2588 unsigned long flags
;
2590 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2591 init_completion(&bnad
->bnad_completions
.ioc_comp
);
2592 bnad
->bnad_completions
.ioc_comp_status
= BNA_CB_WAITING
;
2593 bna_ioceth_enable(&bnad
->bna
.ioceth
);
2594 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2596 wait_for_completion_timeout(&bnad
->bnad_completions
.ioc_comp
,
2597 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT
));
2599 err
= bnad
->bnad_completions
.ioc_comp_status
;
2604 /* Free BNA resources */
2606 bnad_res_free(struct bnad
*bnad
, struct bna_res_info
*res_info
,
2611 for (i
= 0; i
< res_val_max
; i
++)
2612 bnad_mem_free(bnad
, &res_info
[i
].res_u
.mem_info
);
2615 /* Allocates memory and interrupt resources for BNA */
2617 bnad_res_alloc(struct bnad
*bnad
, struct bna_res_info
*res_info
,
2622 for (i
= 0; i
< res_val_max
; i
++) {
2623 err
= bnad_mem_alloc(bnad
, &res_info
[i
].res_u
.mem_info
);
2630 bnad_res_free(bnad
, res_info
, res_val_max
);
2634 /* Interrupt enable / disable */
2636 bnad_enable_msix(struct bnad
*bnad
)
2639 unsigned long flags
;
2641 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2642 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
2643 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2646 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2648 if (bnad
->msix_table
)
2652 kcalloc(bnad
->msix_num
, sizeof(struct msix_entry
), GFP_KERNEL
);
2654 if (!bnad
->msix_table
)
2657 for (i
= 0; i
< bnad
->msix_num
; i
++)
2658 bnad
->msix_table
[i
].entry
= i
;
2660 ret
= pci_enable_msix_range(bnad
->pcidev
, bnad
->msix_table
,
2664 } else if (ret
< bnad
->msix_num
) {
2665 dev_warn(&bnad
->pcidev
->dev
,
2666 "%d MSI-X vectors allocated < %d requested\n",
2667 ret
, bnad
->msix_num
);
2669 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2670 /* ret = #of vectors that we got */
2671 bnad_q_num_adjust(bnad
, (ret
- BNAD_MAILBOX_MSIX_VECTORS
) / 2,
2672 (ret
- BNAD_MAILBOX_MSIX_VECTORS
) / 2);
2673 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2675 bnad
->msix_num
= BNAD_NUM_TXQ
+ BNAD_NUM_RXP
+
2676 BNAD_MAILBOX_MSIX_VECTORS
;
2678 if (bnad
->msix_num
> ret
) {
2679 pci_disable_msix(bnad
->pcidev
);
2684 pci_intx(bnad
->pcidev
, 0);
2689 dev_warn(&bnad
->pcidev
->dev
,
2690 "MSI-X enable failed - operating in INTx mode\n");
2692 kfree(bnad
->msix_table
);
2693 bnad
->msix_table
= NULL
;
2695 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2696 bnad
->cfg_flags
&= ~BNAD_CF_MSIX
;
2697 bnad_q_num_init(bnad
);
2698 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2702 bnad_disable_msix(struct bnad
*bnad
)
2705 unsigned long flags
;
2707 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2708 cfg_flags
= bnad
->cfg_flags
;
2709 if (bnad
->cfg_flags
& BNAD_CF_MSIX
)
2710 bnad
->cfg_flags
&= ~BNAD_CF_MSIX
;
2711 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2713 if (cfg_flags
& BNAD_CF_MSIX
) {
2714 pci_disable_msix(bnad
->pcidev
);
2715 kfree(bnad
->msix_table
);
2716 bnad
->msix_table
= NULL
;
2720 /* Netdev entry points */
2722 bnad_open(struct net_device
*netdev
)
2725 struct bnad
*bnad
= netdev_priv(netdev
);
2726 struct bna_pause_config pause_config
;
2727 unsigned long flags
;
2729 mutex_lock(&bnad
->conf_mutex
);
2732 err
= bnad_setup_tx(bnad
, 0);
2737 err
= bnad_setup_rx(bnad
, 0);
2742 pause_config
.tx_pause
= 0;
2743 pause_config
.rx_pause
= 0;
2745 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2746 bna_enet_mtu_set(&bnad
->bna
.enet
,
2747 BNAD_FRAME_SIZE(bnad
->netdev
->mtu
), NULL
);
2748 bna_enet_pause_config(&bnad
->bna
.enet
, &pause_config
);
2749 bna_enet_enable(&bnad
->bna
.enet
);
2750 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2752 /* Enable broadcast */
2753 bnad_enable_default_bcast(bnad
);
2755 /* Restore VLANs, if any */
2756 bnad_restore_vlans(bnad
, 0);
2758 /* Set the UCAST address */
2759 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2760 bnad_mac_addr_set_locked(bnad
, netdev
->dev_addr
);
2761 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2763 /* Start the stats timer */
2764 bnad_stats_timer_start(bnad
);
2766 mutex_unlock(&bnad
->conf_mutex
);
2771 bnad_destroy_tx(bnad
, 0);
2774 mutex_unlock(&bnad
->conf_mutex
);
2779 bnad_stop(struct net_device
*netdev
)
2781 struct bnad
*bnad
= netdev_priv(netdev
);
2782 unsigned long flags
;
2784 mutex_lock(&bnad
->conf_mutex
);
2786 /* Stop the stats timer */
2787 bnad_stats_timer_stop(bnad
);
2789 init_completion(&bnad
->bnad_completions
.enet_comp
);
2791 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
2792 bna_enet_disable(&bnad
->bna
.enet
, BNA_HARD_CLEANUP
,
2793 bnad_cb_enet_disabled
);
2794 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
2796 wait_for_completion(&bnad
->bnad_completions
.enet_comp
);
2798 bnad_destroy_tx(bnad
, 0);
2799 bnad_destroy_rx(bnad
, 0);
2801 /* Synchronize mailbox IRQ */
2802 bnad_mbox_irq_sync(bnad
);
2804 mutex_unlock(&bnad
->conf_mutex
);
2810 /* Returns 0 for success */
2812 bnad_txq_wi_prepare(struct bnad
*bnad
, struct bna_tcb
*tcb
,
2813 struct sk_buff
*skb
, struct bna_txq_entry
*txqent
)
2819 if (skb_vlan_tag_present(skb
)) {
2820 vlan_tag
= (u16
)skb_vlan_tag_get(skb
);
2821 flags
|= (BNA_TXQ_WI_CF_INS_PRIO
| BNA_TXQ_WI_CF_INS_VLAN
);
2823 if (test_bit(BNAD_RF_CEE_RUNNING
, &bnad
->run_flags
)) {
2824 vlan_tag
= ((tcb
->priority
& 0x7) << VLAN_PRIO_SHIFT
)
2825 | (vlan_tag
& 0x1fff);
2826 flags
|= (BNA_TXQ_WI_CF_INS_PRIO
| BNA_TXQ_WI_CF_INS_VLAN
);
2828 txqent
->hdr
.wi
.vlan_tag
= htons(vlan_tag
);
2830 if (skb_is_gso(skb
)) {
2831 gso_size
= skb_shinfo(skb
)->gso_size
;
2832 if (unlikely(gso_size
> bnad
->netdev
->mtu
)) {
2833 BNAD_UPDATE_CTR(bnad
, tx_skb_mss_too_long
);
2836 if (unlikely((gso_size
+ skb_transport_offset(skb
) +
2837 tcp_hdrlen(skb
)) >= skb
->len
)) {
2838 txqent
->hdr
.wi
.opcode
= htons(BNA_TXQ_WI_SEND
);
2839 txqent
->hdr
.wi
.lso_mss
= 0;
2840 BNAD_UPDATE_CTR(bnad
, tx_skb_tso_too_short
);
2842 txqent
->hdr
.wi
.opcode
= htons(BNA_TXQ_WI_SEND_LSO
);
2843 txqent
->hdr
.wi
.lso_mss
= htons(gso_size
);
2846 if (bnad_tso_prepare(bnad
, skb
)) {
2847 BNAD_UPDATE_CTR(bnad
, tx_skb_tso_prepare
);
2851 flags
|= (BNA_TXQ_WI_CF_IP_CKSUM
| BNA_TXQ_WI_CF_TCP_CKSUM
);
2852 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2853 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET(
2854 tcp_hdrlen(skb
) >> 2, skb_transport_offset(skb
)));
2856 txqent
->hdr
.wi
.opcode
= htons(BNA_TXQ_WI_SEND
);
2857 txqent
->hdr
.wi
.lso_mss
= 0;
2859 if (unlikely(skb
->len
> (bnad
->netdev
->mtu
+ VLAN_ETH_HLEN
))) {
2860 BNAD_UPDATE_CTR(bnad
, tx_skb_non_tso_too_long
);
2864 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2865 __be16 net_proto
= vlan_get_protocol(skb
);
2868 if (net_proto
== htons(ETH_P_IP
))
2869 proto
= ip_hdr(skb
)->protocol
;
2870 #ifdef NETIF_F_IPV6_CSUM
2871 else if (net_proto
== htons(ETH_P_IPV6
)) {
2872 /* nexthdr may not be TCP immediately. */
2873 proto
= ipv6_hdr(skb
)->nexthdr
;
2876 if (proto
== IPPROTO_TCP
) {
2877 flags
|= BNA_TXQ_WI_CF_TCP_CKSUM
;
2878 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2879 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2880 (0, skb_transport_offset(skb
)));
2882 BNAD_UPDATE_CTR(bnad
, tcpcsum_offload
);
2884 if (unlikely(skb_headlen(skb
) <
2885 skb_transport_offset(skb
) +
2887 BNAD_UPDATE_CTR(bnad
, tx_skb_tcp_hdr
);
2890 } else if (proto
== IPPROTO_UDP
) {
2891 flags
|= BNA_TXQ_WI_CF_UDP_CKSUM
;
2892 txqent
->hdr
.wi
.l4_hdr_size_n_offset
=
2893 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2894 (0, skb_transport_offset(skb
)));
2896 BNAD_UPDATE_CTR(bnad
, udpcsum_offload
);
2897 if (unlikely(skb_headlen(skb
) <
2898 skb_transport_offset(skb
) +
2899 sizeof(struct udphdr
))) {
2900 BNAD_UPDATE_CTR(bnad
, tx_skb_udp_hdr
);
2905 BNAD_UPDATE_CTR(bnad
, tx_skb_csum_err
);
2909 txqent
->hdr
.wi
.l4_hdr_size_n_offset
= 0;
2912 txqent
->hdr
.wi
.flags
= htons(flags
);
2913 txqent
->hdr
.wi
.frame_length
= htonl(skb
->len
);
2919 * bnad_start_xmit : Netdev entry point for Transmit
2920 * Called under lock held by net_device
2923 bnad_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
2925 struct bnad
*bnad
= netdev_priv(netdev
);
2927 struct bna_tcb
*tcb
= NULL
;
2928 struct bnad_tx_unmap
*unmap_q
, *unmap
, *head_unmap
;
2929 u32 prod
, q_depth
, vect_id
;
2930 u32 wis
, vectors
, len
;
2932 dma_addr_t dma_addr
;
2933 struct bna_txq_entry
*txqent
;
2935 len
= skb_headlen(skb
);
2937 /* Sanity checks for the skb */
2939 if (unlikely(skb
->len
<= ETH_HLEN
)) {
2940 dev_kfree_skb_any(skb
);
2941 BNAD_UPDATE_CTR(bnad
, tx_skb_too_short
);
2942 return NETDEV_TX_OK
;
2944 if (unlikely(len
> BFI_TX_MAX_DATA_PER_VECTOR
)) {
2945 dev_kfree_skb_any(skb
);
2946 BNAD_UPDATE_CTR(bnad
, tx_skb_headlen_zero
);
2947 return NETDEV_TX_OK
;
2949 if (unlikely(len
== 0)) {
2950 dev_kfree_skb_any(skb
);
2951 BNAD_UPDATE_CTR(bnad
, tx_skb_headlen_zero
);
2952 return NETDEV_TX_OK
;
2955 tcb
= bnad
->tx_info
[0].tcb
[txq_id
];
2958 * Takes care of the Tx that is scheduled between clearing the flag
2959 * and the netif_tx_stop_all_queues() call.
2961 if (unlikely(!tcb
|| !test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
))) {
2962 dev_kfree_skb_any(skb
);
2963 BNAD_UPDATE_CTR(bnad
, tx_skb_stopping
);
2964 return NETDEV_TX_OK
;
2967 q_depth
= tcb
->q_depth
;
2968 prod
= tcb
->producer_index
;
2969 unmap_q
= tcb
->unmap_q
;
2971 vectors
= 1 + skb_shinfo(skb
)->nr_frags
;
2972 wis
= BNA_TXQ_WI_NEEDED(vectors
); /* 4 vectors per work item */
2974 if (unlikely(vectors
> BFI_TX_MAX_VECTORS_PER_PKT
)) {
2975 dev_kfree_skb_any(skb
);
2976 BNAD_UPDATE_CTR(bnad
, tx_skb_max_vectors
);
2977 return NETDEV_TX_OK
;
2980 /* Check for available TxQ resources */
2981 if (unlikely(wis
> BNA_QE_FREE_CNT(tcb
, q_depth
))) {
2982 if ((*tcb
->hw_consumer_index
!= tcb
->consumer_index
) &&
2983 !test_and_set_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
)) {
2985 sent
= bnad_txcmpl_process(bnad
, tcb
);
2986 if (likely(test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
2987 bna_ib_ack(tcb
->i_dbell
, sent
);
2988 smp_mb__before_atomic();
2989 clear_bit(BNAD_TXQ_FREE_SENT
, &tcb
->flags
);
2991 netif_stop_queue(netdev
);
2992 BNAD_UPDATE_CTR(bnad
, netif_queue_stop
);
2997 * Check again to deal with race condition between
2998 * netif_stop_queue here, and netif_wake_queue in
2999 * interrupt handler which is not inside netif tx lock.
3001 if (likely(wis
> BNA_QE_FREE_CNT(tcb
, q_depth
))) {
3002 BNAD_UPDATE_CTR(bnad
, netif_queue_stop
);
3003 return NETDEV_TX_BUSY
;
3005 netif_wake_queue(netdev
);
3006 BNAD_UPDATE_CTR(bnad
, netif_queue_wakeup
);
3010 txqent
= &((struct bna_txq_entry
*)tcb
->sw_q
)[prod
];
3011 head_unmap
= &unmap_q
[prod
];
3013 /* Program the opcode, flags, frame_len, num_vectors in WI */
3014 if (bnad_txq_wi_prepare(bnad
, tcb
, skb
, txqent
)) {
3015 dev_kfree_skb_any(skb
);
3016 return NETDEV_TX_OK
;
3018 txqent
->hdr
.wi
.reserved
= 0;
3019 txqent
->hdr
.wi
.num_vectors
= vectors
;
3021 head_unmap
->skb
= skb
;
3022 head_unmap
->nvecs
= 0;
3024 /* Program the vectors */
3026 dma_addr
= dma_map_single(&bnad
->pcidev
->dev
, skb
->data
,
3027 len
, DMA_TO_DEVICE
);
3028 BNA_SET_DMA_ADDR(dma_addr
, &txqent
->vector
[0].host_addr
);
3029 txqent
->vector
[0].length
= htons(len
);
3030 dma_unmap_addr_set(&unmap
->vectors
[0], dma_addr
, dma_addr
);
3031 head_unmap
->nvecs
++;
3033 for (i
= 0, vect_id
= 0; i
< vectors
- 1; i
++) {
3034 const struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
3035 u32 size
= skb_frag_size(frag
);
3037 if (unlikely(size
== 0)) {
3038 /* Undo the changes starting at tcb->producer_index */
3039 bnad_tx_buff_unmap(bnad
, unmap_q
, q_depth
,
3040 tcb
->producer_index
);
3041 dev_kfree_skb_any(skb
);
3042 BNAD_UPDATE_CTR(bnad
, tx_skb_frag_zero
);
3043 return NETDEV_TX_OK
;
3049 if (vect_id
== BFI_TX_MAX_VECTORS_PER_WI
) {
3051 BNA_QE_INDX_INC(prod
, q_depth
);
3052 txqent
= &((struct bna_txq_entry
*)tcb
->sw_q
)[prod
];
3053 txqent
->hdr
.wi_ext
.opcode
= htons(BNA_TXQ_WI_EXTENSION
);
3054 unmap
= &unmap_q
[prod
];
3057 dma_addr
= skb_frag_dma_map(&bnad
->pcidev
->dev
, frag
,
3058 0, size
, DMA_TO_DEVICE
);
3059 dma_unmap_len_set(&unmap
->vectors
[vect_id
], dma_len
, size
);
3060 BNA_SET_DMA_ADDR(dma_addr
, &txqent
->vector
[vect_id
].host_addr
);
3061 txqent
->vector
[vect_id
].length
= htons(size
);
3062 dma_unmap_addr_set(&unmap
->vectors
[vect_id
], dma_addr
,
3064 head_unmap
->nvecs
++;
3067 if (unlikely(len
!= skb
->len
)) {
3068 /* Undo the changes starting at tcb->producer_index */
3069 bnad_tx_buff_unmap(bnad
, unmap_q
, q_depth
, tcb
->producer_index
);
3070 dev_kfree_skb_any(skb
);
3071 BNAD_UPDATE_CTR(bnad
, tx_skb_len_mismatch
);
3072 return NETDEV_TX_OK
;
3075 BNA_QE_INDX_INC(prod
, q_depth
);
3076 tcb
->producer_index
= prod
;
3080 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED
, &tcb
->flags
)))
3081 return NETDEV_TX_OK
;
3083 skb_tx_timestamp(skb
);
3085 bna_txq_prod_indx_doorbell(tcb
);
3088 return NETDEV_TX_OK
;
3092 * Used spin_lock to synchronize reading of stats structures, which
3093 * is written by BNA under the same lock.
3095 static struct rtnl_link_stats64
*
3096 bnad_get_stats64(struct net_device
*netdev
, struct rtnl_link_stats64
*stats
)
3098 struct bnad
*bnad
= netdev_priv(netdev
);
3099 unsigned long flags
;
3101 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3103 bnad_netdev_qstats_fill(bnad
, stats
);
3104 bnad_netdev_hwstats_fill(bnad
, stats
);
3106 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3112 bnad_set_rx_ucast_fltr(struct bnad
*bnad
)
3114 struct net_device
*netdev
= bnad
->netdev
;
3115 int uc_count
= netdev_uc_count(netdev
);
3116 enum bna_cb_status ret
;
3118 struct netdev_hw_addr
*ha
;
3121 if (netdev_uc_empty(bnad
->netdev
)) {
3122 bna_rx_ucast_listset(bnad
->rx_info
[0].rx
, 0, NULL
);
3126 if (uc_count
> bna_attr(&bnad
->bna
)->num_ucmac
)
3129 mac_list
= kzalloc(uc_count
* ETH_ALEN
, GFP_ATOMIC
);
3130 if (mac_list
== NULL
)
3134 netdev_for_each_uc_addr(ha
, netdev
) {
3135 ether_addr_copy(&mac_list
[entry
* ETH_ALEN
], &ha
->addr
[0]);
3139 ret
= bna_rx_ucast_listset(bnad
->rx_info
[0].rx
, entry
, mac_list
);
3142 if (ret
!= BNA_CB_SUCCESS
)
3147 /* ucast packets not in UCAM are routed to default function */
3149 bnad
->cfg_flags
|= BNAD_CF_DEFAULT
;
3150 bna_rx_ucast_listset(bnad
->rx_info
[0].rx
, 0, NULL
);
3154 bnad_set_rx_mcast_fltr(struct bnad
*bnad
)
3156 struct net_device
*netdev
= bnad
->netdev
;
3157 int mc_count
= netdev_mc_count(netdev
);
3158 enum bna_cb_status ret
;
3161 if (netdev
->flags
& IFF_ALLMULTI
)
3164 if (netdev_mc_empty(netdev
))
3167 if (mc_count
> bna_attr(&bnad
->bna
)->num_mcmac
)
3170 mac_list
= kzalloc((mc_count
+ 1) * ETH_ALEN
, GFP_ATOMIC
);
3172 if (mac_list
== NULL
)
3175 ether_addr_copy(&mac_list
[0], &bnad_bcast_addr
[0]);
3177 /* copy rest of the MCAST addresses */
3178 bnad_netdev_mc_list_get(netdev
, mac_list
);
3179 ret
= bna_rx_mcast_listset(bnad
->rx_info
[0].rx
, mc_count
+ 1, mac_list
);
3182 if (ret
!= BNA_CB_SUCCESS
)
3188 bnad
->cfg_flags
|= BNAD_CF_ALLMULTI
;
3189 bna_rx_mcast_delall(bnad
->rx_info
[0].rx
);
3193 bnad_set_rx_mode(struct net_device
*netdev
)
3195 struct bnad
*bnad
= netdev_priv(netdev
);
3196 enum bna_rxmode new_mode
, mode_mask
;
3197 unsigned long flags
;
3199 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3201 if (bnad
->rx_info
[0].rx
== NULL
) {
3202 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3206 /* clear bnad flags to update it with new settings */
3207 bnad
->cfg_flags
&= ~(BNAD_CF_PROMISC
| BNAD_CF_DEFAULT
|
3211 if (netdev
->flags
& IFF_PROMISC
) {
3212 new_mode
|= BNAD_RXMODE_PROMISC_DEFAULT
;
3213 bnad
->cfg_flags
|= BNAD_CF_PROMISC
;
3215 bnad_set_rx_mcast_fltr(bnad
);
3217 if (bnad
->cfg_flags
& BNAD_CF_ALLMULTI
)
3218 new_mode
|= BNA_RXMODE_ALLMULTI
;
3220 bnad_set_rx_ucast_fltr(bnad
);
3222 if (bnad
->cfg_flags
& BNAD_CF_DEFAULT
)
3223 new_mode
|= BNA_RXMODE_DEFAULT
;
3226 mode_mask
= BNA_RXMODE_PROMISC
| BNA_RXMODE_DEFAULT
|
3227 BNA_RXMODE_ALLMULTI
;
3228 bna_rx_mode_set(bnad
->rx_info
[0].rx
, new_mode
, mode_mask
);
3230 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3234 * bna_lock is used to sync writes to netdev->addr
3235 * conf_lock cannot be used since this call may be made
3236 * in a non-blocking context.
3239 bnad_set_mac_address(struct net_device
*netdev
, void *addr
)
3242 struct bnad
*bnad
= netdev_priv(netdev
);
3243 struct sockaddr
*sa
= (struct sockaddr
*)addr
;
3244 unsigned long flags
;
3246 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3248 err
= bnad_mac_addr_set_locked(bnad
, sa
->sa_data
);
3250 ether_addr_copy(netdev
->dev_addr
, sa
->sa_data
);
3252 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3258 bnad_mtu_set(struct bnad
*bnad
, int frame_size
)
3260 unsigned long flags
;
3262 init_completion(&bnad
->bnad_completions
.mtu_comp
);
3264 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3265 bna_enet_mtu_set(&bnad
->bna
.enet
, frame_size
, bnad_cb_enet_mtu_set
);
3266 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3268 wait_for_completion(&bnad
->bnad_completions
.mtu_comp
);
3270 return bnad
->bnad_completions
.mtu_comp_status
;
3274 bnad_change_mtu(struct net_device
*netdev
, int new_mtu
)
3277 struct bnad
*bnad
= netdev_priv(netdev
);
3278 u32 rx_count
= 0, frame
, new_frame
;
3280 if (new_mtu
+ ETH_HLEN
< ETH_ZLEN
|| new_mtu
> BNAD_JUMBO_MTU
)
3283 mutex_lock(&bnad
->conf_mutex
);
3286 netdev
->mtu
= new_mtu
;
3288 frame
= BNAD_FRAME_SIZE(mtu
);
3289 new_frame
= BNAD_FRAME_SIZE(new_mtu
);
3291 /* check if multi-buffer needs to be enabled */
3292 if (BNAD_PCI_DEV_IS_CAT2(bnad
) &&
3293 netif_running(bnad
->netdev
)) {
3294 /* only when transition is over 4K */
3295 if ((frame
<= 4096 && new_frame
> 4096) ||
3296 (frame
> 4096 && new_frame
<= 4096))
3297 rx_count
= bnad_reinit_rx(bnad
);
3300 /* rx_count > 0 - new rx created
3301 * - Linux set err = 0 and return
3303 err
= bnad_mtu_set(bnad
, new_frame
);
3307 mutex_unlock(&bnad
->conf_mutex
);
3312 bnad_vlan_rx_add_vid(struct net_device
*netdev
, __be16 proto
, u16 vid
)
3314 struct bnad
*bnad
= netdev_priv(netdev
);
3315 unsigned long flags
;
3317 if (!bnad
->rx_info
[0].rx
)
3320 mutex_lock(&bnad
->conf_mutex
);
3322 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3323 bna_rx_vlan_add(bnad
->rx_info
[0].rx
, vid
);
3324 set_bit(vid
, bnad
->active_vlans
);
3325 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3327 mutex_unlock(&bnad
->conf_mutex
);
3333 bnad_vlan_rx_kill_vid(struct net_device
*netdev
, __be16 proto
, u16 vid
)
3335 struct bnad
*bnad
= netdev_priv(netdev
);
3336 unsigned long flags
;
3338 if (!bnad
->rx_info
[0].rx
)
3341 mutex_lock(&bnad
->conf_mutex
);
3343 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3344 clear_bit(vid
, bnad
->active_vlans
);
3345 bna_rx_vlan_del(bnad
->rx_info
[0].rx
, vid
);
3346 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3348 mutex_unlock(&bnad
->conf_mutex
);
3353 static int bnad_set_features(struct net_device
*dev
, netdev_features_t features
)
3355 struct bnad
*bnad
= netdev_priv(dev
);
3356 netdev_features_t changed
= features
^ dev
->features
;
3358 if ((changed
& NETIF_F_HW_VLAN_CTAG_RX
) && netif_running(dev
)) {
3359 unsigned long flags
;
3361 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3363 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
3364 bna_rx_vlan_strip_enable(bnad
->rx_info
[0].rx
);
3366 bna_rx_vlan_strip_disable(bnad
->rx_info
[0].rx
);
3368 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3374 #ifdef CONFIG_NET_POLL_CONTROLLER
3376 bnad_netpoll(struct net_device
*netdev
)
3378 struct bnad
*bnad
= netdev_priv(netdev
);
3379 struct bnad_rx_info
*rx_info
;
3380 struct bnad_rx_ctrl
*rx_ctrl
;
3384 if (!(bnad
->cfg_flags
& BNAD_CF_MSIX
)) {
3385 bna_intx_disable(&bnad
->bna
, curr_mask
);
3386 bnad_isr(bnad
->pcidev
->irq
, netdev
);
3387 bna_intx_enable(&bnad
->bna
, curr_mask
);
3390 * Tx processing may happen in sending context, so no need
3391 * to explicitly process completions here
3395 for (i
= 0; i
< bnad
->num_rx
; i
++) {
3396 rx_info
= &bnad
->rx_info
[i
];
3399 for (j
= 0; j
< bnad
->num_rxp_per_rx
; j
++) {
3400 rx_ctrl
= &rx_info
->rx_ctrl
[j
];
3402 bnad_netif_rx_schedule_poll(bnad
,
3410 static const struct net_device_ops bnad_netdev_ops
= {
3411 .ndo_open
= bnad_open
,
3412 .ndo_stop
= bnad_stop
,
3413 .ndo_start_xmit
= bnad_start_xmit
,
3414 .ndo_get_stats64
= bnad_get_stats64
,
3415 .ndo_set_rx_mode
= bnad_set_rx_mode
,
3416 .ndo_validate_addr
= eth_validate_addr
,
3417 .ndo_set_mac_address
= bnad_set_mac_address
,
3418 .ndo_change_mtu
= bnad_change_mtu
,
3419 .ndo_vlan_rx_add_vid
= bnad_vlan_rx_add_vid
,
3420 .ndo_vlan_rx_kill_vid
= bnad_vlan_rx_kill_vid
,
3421 .ndo_set_features
= bnad_set_features
,
3422 #ifdef CONFIG_NET_POLL_CONTROLLER
3423 .ndo_poll_controller
= bnad_netpoll
3428 bnad_netdev_init(struct bnad
*bnad
, bool using_dac
)
3430 struct net_device
*netdev
= bnad
->netdev
;
3432 netdev
->hw_features
= NETIF_F_SG
| NETIF_F_RXCSUM
|
3433 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3434 NETIF_F_TSO
| NETIF_F_TSO6
| NETIF_F_HW_VLAN_CTAG_TX
|
3435 NETIF_F_HW_VLAN_CTAG_RX
;
3437 netdev
->vlan_features
= NETIF_F_SG
| NETIF_F_HIGHDMA
|
3438 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3439 NETIF_F_TSO
| NETIF_F_TSO6
;
3441 netdev
->features
|= netdev
->hw_features
| NETIF_F_HW_VLAN_CTAG_FILTER
;
3444 netdev
->features
|= NETIF_F_HIGHDMA
;
3446 netdev
->mem_start
= bnad
->mmio_start
;
3447 netdev
->mem_end
= bnad
->mmio_start
+ bnad
->mmio_len
- 1;
3449 netdev
->netdev_ops
= &bnad_netdev_ops
;
3450 bnad_set_ethtool_ops(netdev
);
3454 * 1. Initialize the bnad structure
3455 * 2. Setup netdev pointer in pci_dev
3456 * 3. Initialize no. of TxQ & CQs & MSIX vectors
3457 * 4. Initialize work queue.
3460 bnad_init(struct bnad
*bnad
,
3461 struct pci_dev
*pdev
, struct net_device
*netdev
)
3463 unsigned long flags
;
3465 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
3466 pci_set_drvdata(pdev
, netdev
);
3468 bnad
->netdev
= netdev
;
3469 bnad
->pcidev
= pdev
;
3470 bnad
->mmio_start
= pci_resource_start(pdev
, 0);
3471 bnad
->mmio_len
= pci_resource_len(pdev
, 0);
3472 bnad
->bar0
= ioremap_nocache(bnad
->mmio_start
, bnad
->mmio_len
);
3474 dev_err(&pdev
->dev
, "ioremap for bar0 failed\n");
3477 dev_info(&pdev
->dev
, "bar0 mapped to %p, len %llu\n", bnad
->bar0
,
3478 (unsigned long long) bnad
->mmio_len
);
3480 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3481 if (!bnad_msix_disable
)
3482 bnad
->cfg_flags
= BNAD_CF_MSIX
;
3484 bnad
->cfg_flags
|= BNAD_CF_DIM_ENABLED
;
3486 bnad_q_num_init(bnad
);
3487 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3489 bnad
->msix_num
= (bnad
->num_tx
* bnad
->num_txq_per_tx
) +
3490 (bnad
->num_rx
* bnad
->num_rxp_per_rx
) +
3491 BNAD_MAILBOX_MSIX_VECTORS
;
3493 bnad
->txq_depth
= BNAD_TXQ_DEPTH
;
3494 bnad
->rxq_depth
= BNAD_RXQ_DEPTH
;
3496 bnad
->tx_coalescing_timeo
= BFI_TX_COALESCING_TIMEO
;
3497 bnad
->rx_coalescing_timeo
= BFI_RX_COALESCING_TIMEO
;
3499 sprintf(bnad
->wq_name
, "%s_wq_%d", BNAD_NAME
, bnad
->id
);
3500 bnad
->work_q
= create_singlethread_workqueue(bnad
->wq_name
);
3501 if (!bnad
->work_q
) {
3502 iounmap(bnad
->bar0
);
3510 * Must be called after bnad_pci_uninit()
3511 * so that iounmap() and pci_set_drvdata(NULL)
3512 * happens only after PCI uninitialization.
3515 bnad_uninit(struct bnad
*bnad
)
3518 flush_workqueue(bnad
->work_q
);
3519 destroy_workqueue(bnad
->work_q
);
3520 bnad
->work_q
= NULL
;
3524 iounmap(bnad
->bar0
);
3529 a) Per ioceth mutes used for serializing configuration
3530 changes from OS interface
3531 b) spin lock used to protect bna state machine
3534 bnad_lock_init(struct bnad
*bnad
)
3536 spin_lock_init(&bnad
->bna_lock
);
3537 mutex_init(&bnad
->conf_mutex
);
3538 mutex_init(&bnad_list_mutex
);
3542 bnad_lock_uninit(struct bnad
*bnad
)
3544 mutex_destroy(&bnad
->conf_mutex
);
3545 mutex_destroy(&bnad_list_mutex
);
3548 /* PCI Initialization */
3550 bnad_pci_init(struct bnad
*bnad
,
3551 struct pci_dev
*pdev
, bool *using_dac
)
3555 err
= pci_enable_device(pdev
);
3558 err
= pci_request_regions(pdev
, BNAD_NAME
);
3560 goto disable_device
;
3561 if (!dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64))) {
3564 err
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
3566 goto release_regions
;
3569 pci_set_master(pdev
);
3573 pci_release_regions(pdev
);
3575 pci_disable_device(pdev
);
3581 bnad_pci_uninit(struct pci_dev
*pdev
)
3583 pci_release_regions(pdev
);
3584 pci_disable_device(pdev
);
3588 bnad_pci_probe(struct pci_dev
*pdev
,
3589 const struct pci_device_id
*pcidev_id
)
3595 struct net_device
*netdev
;
3596 struct bfa_pcidev pcidev_info
;
3597 unsigned long flags
;
3599 mutex_lock(&bnad_fwimg_mutex
);
3600 if (!cna_get_firmware_buf(pdev
)) {
3601 mutex_unlock(&bnad_fwimg_mutex
);
3602 dev_err(&pdev
->dev
, "failed to load firmware image!\n");
3605 mutex_unlock(&bnad_fwimg_mutex
);
3608 * Allocates sizeof(struct net_device + struct bnad)
3609 * bnad = netdev->priv
3611 netdev
= alloc_etherdev(sizeof(struct bnad
));
3616 bnad
= netdev_priv(netdev
);
3617 bnad_lock_init(bnad
);
3618 bnad_add_to_list(bnad
);
3620 mutex_lock(&bnad
->conf_mutex
);
3622 * PCI initialization
3623 * Output : using_dac = 1 for 64 bit DMA
3624 * = 0 for 32 bit DMA
3627 err
= bnad_pci_init(bnad
, pdev
, &using_dac
);
3632 * Initialize bnad structure
3633 * Setup relation between pci_dev & netdev
3635 err
= bnad_init(bnad
, pdev
, netdev
);
3639 /* Initialize netdev structure, set up ethtool ops */
3640 bnad_netdev_init(bnad
, using_dac
);
3642 /* Set link to down state */
3643 netif_carrier_off(netdev
);
3645 /* Setup the debugfs node for this bfad */
3646 if (bna_debugfs_enable
)
3647 bnad_debugfs_init(bnad
);
3649 /* Get resource requirement form bna */
3650 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3651 bna_res_req(&bnad
->res_info
[0]);
3652 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3654 /* Allocate resources from bna */
3655 err
= bnad_res_alloc(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3661 /* Setup pcidev_info for bna_init() */
3662 pcidev_info
.pci_slot
= PCI_SLOT(bnad
->pcidev
->devfn
);
3663 pcidev_info
.pci_func
= PCI_FUNC(bnad
->pcidev
->devfn
);
3664 pcidev_info
.device_id
= bnad
->pcidev
->device
;
3665 pcidev_info
.pci_bar_kva
= bnad
->bar0
;
3667 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3668 bna_init(bna
, bnad
, &pcidev_info
, &bnad
->res_info
[0]);
3669 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3671 bnad
->stats
.bna_stats
= &bna
->stats
;
3673 bnad_enable_msix(bnad
);
3674 err
= bnad_mbox_irq_alloc(bnad
);
3679 setup_timer(&bnad
->bna
.ioceth
.ioc
.ioc_timer
, bnad_ioc_timeout
,
3680 (unsigned long)bnad
);
3681 setup_timer(&bnad
->bna
.ioceth
.ioc
.hb_timer
, bnad_ioc_hb_check
,
3682 (unsigned long)bnad
);
3683 setup_timer(&bnad
->bna
.ioceth
.ioc
.iocpf_timer
, bnad_iocpf_timeout
,
3684 (unsigned long)bnad
);
3685 setup_timer(&bnad
->bna
.ioceth
.ioc
.sem_timer
, bnad_iocpf_sem_timeout
,
3686 (unsigned long)bnad
);
3690 * If the call back comes with error, we bail out.
3691 * This is a catastrophic error.
3693 err
= bnad_ioceth_enable(bnad
);
3695 dev_err(&pdev
->dev
, "initialization failed err=%d\n", err
);
3699 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3700 if (bna_num_txq_set(bna
, BNAD_NUM_TXQ
+ 1) ||
3701 bna_num_rxp_set(bna
, BNAD_NUM_RXP
+ 1)) {
3702 bnad_q_num_adjust(bnad
, bna_attr(bna
)->num_txq
- 1,
3703 bna_attr(bna
)->num_rxp
- 1);
3704 if (bna_num_txq_set(bna
, BNAD_NUM_TXQ
+ 1) ||
3705 bna_num_rxp_set(bna
, BNAD_NUM_RXP
+ 1))
3708 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3710 goto disable_ioceth
;
3712 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3713 bna_mod_res_req(&bnad
->bna
, &bnad
->mod_res_info
[0]);
3714 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3716 err
= bnad_res_alloc(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3719 goto disable_ioceth
;
3722 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3723 bna_mod_init(&bnad
->bna
, &bnad
->mod_res_info
[0]);
3724 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3726 /* Get the burnt-in mac */
3727 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3728 bna_enet_perm_mac_get(&bna
->enet
, bnad
->perm_addr
);
3729 bnad_set_netdev_perm_addr(bnad
);
3730 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3732 mutex_unlock(&bnad
->conf_mutex
);
3734 /* Finally, reguister with net_device layer */
3735 err
= register_netdev(netdev
);
3737 dev_err(&pdev
->dev
, "registering net device failed\n");
3740 set_bit(BNAD_RF_NETDEV_REGISTERED
, &bnad
->run_flags
);
3745 mutex_unlock(&bnad
->conf_mutex
);
3749 mutex_lock(&bnad
->conf_mutex
);
3750 bnad_res_free(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3752 bnad_ioceth_disable(bnad
);
3753 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.ioc_timer
);
3754 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.sem_timer
);
3755 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.hb_timer
);
3756 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3758 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3759 bnad_mbox_irq_free(bnad
);
3760 bnad_disable_msix(bnad
);
3762 bnad_res_free(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3764 /* Remove the debugfs node for this bnad */
3765 kfree(bnad
->regdata
);
3766 bnad_debugfs_uninit(bnad
);
3769 bnad_pci_uninit(pdev
);
3771 mutex_unlock(&bnad
->conf_mutex
);
3772 bnad_remove_from_list(bnad
);
3773 bnad_lock_uninit(bnad
);
3774 free_netdev(netdev
);
3779 bnad_pci_remove(struct pci_dev
*pdev
)
3781 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3784 unsigned long flags
;
3789 bnad
= netdev_priv(netdev
);
3792 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED
, &bnad
->run_flags
))
3793 unregister_netdev(netdev
);
3795 mutex_lock(&bnad
->conf_mutex
);
3796 bnad_ioceth_disable(bnad
);
3797 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.ioc_timer
);
3798 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.sem_timer
);
3799 del_timer_sync(&bnad
->bna
.ioceth
.ioc
.hb_timer
);
3800 spin_lock_irqsave(&bnad
->bna_lock
, flags
);
3802 spin_unlock_irqrestore(&bnad
->bna_lock
, flags
);
3804 bnad_res_free(bnad
, &bnad
->mod_res_info
[0], BNA_MOD_RES_T_MAX
);
3805 bnad_res_free(bnad
, &bnad
->res_info
[0], BNA_RES_T_MAX
);
3806 bnad_mbox_irq_free(bnad
);
3807 bnad_disable_msix(bnad
);
3808 bnad_pci_uninit(pdev
);
3809 mutex_unlock(&bnad
->conf_mutex
);
3810 bnad_remove_from_list(bnad
);
3811 bnad_lock_uninit(bnad
);
3812 /* Remove the debugfs node for this bnad */
3813 kfree(bnad
->regdata
);
3814 bnad_debugfs_uninit(bnad
);
3816 free_netdev(netdev
);
3819 static const struct pci_device_id bnad_pci_id_table
[] = {
3821 PCI_DEVICE(PCI_VENDOR_ID_BROCADE
,
3822 PCI_DEVICE_ID_BROCADE_CT
),
3823 .class = PCI_CLASS_NETWORK_ETHERNET
<< 8,
3824 .class_mask
= 0xffff00
3827 PCI_DEVICE(PCI_VENDOR_ID_BROCADE
,
3828 BFA_PCI_DEVICE_ID_CT2
),
3829 .class = PCI_CLASS_NETWORK_ETHERNET
<< 8,
3830 .class_mask
= 0xffff00
3835 MODULE_DEVICE_TABLE(pci
, bnad_pci_id_table
);
3837 static struct pci_driver bnad_pci_driver
= {
3839 .id_table
= bnad_pci_id_table
,
3840 .probe
= bnad_pci_probe
,
3841 .remove
= bnad_pci_remove
,
3845 bnad_module_init(void)
3849 pr_info("bna: QLogic BR-series 10G Ethernet driver - version: %s\n",
3852 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover
);
3854 err
= pci_register_driver(&bnad_pci_driver
);
3856 pr_err("bna: PCI driver registration failed err=%d\n", err
);
3864 bnad_module_exit(void)
3866 pci_unregister_driver(&bnad_pci_driver
);
3867 release_firmware(bfi_fw
);
3870 module_init(bnad_module_init
);
3871 module_exit(bnad_module_exit
);
3873 MODULE_AUTHOR("Brocade");
3874 MODULE_LICENSE("GPL");
3875 MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver");
3876 MODULE_VERSION(BNAD_VERSION
);
3877 MODULE_FIRMWARE(CNA_FW_FILE_CT
);
3878 MODULE_FIRMWARE(CNA_FW_FILE_CT2
);