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Merge branches 'acpi-video' and 'cpufreq-fixes'
[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bnad.c
1 /*
2 * Linux network driver for QLogic BR-series Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13 /*
14 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
15 * Copyright (c) 2014-2015 QLogic Corporation
16 * All rights reserved
17 * www.qlogic.com
18 */
19 #include <linux/bitops.h>
20 #include <linux/netdevice.h>
21 #include <linux/skbuff.h>
22 #include <linux/etherdevice.h>
23 #include <linux/in.h>
24 #include <linux/ethtool.h>
25 #include <linux/if_vlan.h>
26 #include <linux/if_ether.h>
27 #include <linux/ip.h>
28 #include <linux/prefetch.h>
29 #include <linux/module.h>
30
31 #include "bnad.h"
32 #include "bna.h"
33 #include "cna.h"
34
35 static DEFINE_MUTEX(bnad_fwimg_mutex);
36
37 /*
38 * Module params
39 */
40 static uint bnad_msix_disable;
41 module_param(bnad_msix_disable, uint, 0444);
42 MODULE_PARM_DESC(bnad_msix_disable, "Disable MSIX mode");
43
44 static uint bnad_ioc_auto_recover = 1;
45 module_param(bnad_ioc_auto_recover, uint, 0444);
46 MODULE_PARM_DESC(bnad_ioc_auto_recover, "Enable / Disable auto recovery");
47
48 static uint bna_debugfs_enable = 1;
49 module_param(bna_debugfs_enable, uint, S_IRUGO | S_IWUSR);
50 MODULE_PARM_DESC(bna_debugfs_enable, "Enables debugfs feature, default=1,"
51 " Range[false:0|true:1]");
52
53 /*
54 * Global variables
55 */
56 static u32 bnad_rxqs_per_cq = 2;
57 static u32 bna_id;
58 static struct mutex bnad_list_mutex;
59 static LIST_HEAD(bnad_list);
60 static const u8 bnad_bcast_addr[] __aligned(2) =
61 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
62
63 /*
64 * Local MACROS
65 */
66 #define BNAD_GET_MBOX_IRQ(_bnad) \
67 (((_bnad)->cfg_flags & BNAD_CF_MSIX) ? \
68 ((_bnad)->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector) : \
69 ((_bnad)->pcidev->irq))
70
71 #define BNAD_FILL_UNMAPQ_MEM_REQ(_res_info, _num, _size) \
72 do { \
73 (_res_info)->res_type = BNA_RES_T_MEM; \
74 (_res_info)->res_u.mem_info.mem_type = BNA_MEM_T_KVA; \
75 (_res_info)->res_u.mem_info.num = (_num); \
76 (_res_info)->res_u.mem_info.len = (_size); \
77 } while (0)
78
79 static void
80 bnad_add_to_list(struct bnad *bnad)
81 {
82 mutex_lock(&bnad_list_mutex);
83 list_add_tail(&bnad->list_entry, &bnad_list);
84 bnad->id = bna_id++;
85 mutex_unlock(&bnad_list_mutex);
86 }
87
88 static void
89 bnad_remove_from_list(struct bnad *bnad)
90 {
91 mutex_lock(&bnad_list_mutex);
92 list_del(&bnad->list_entry);
93 mutex_unlock(&bnad_list_mutex);
94 }
95
96 /*
97 * Reinitialize completions in CQ, once Rx is taken down
98 */
99 static void
100 bnad_cq_cleanup(struct bnad *bnad, struct bna_ccb *ccb)
101 {
102 struct bna_cq_entry *cmpl;
103 int i;
104
105 for (i = 0; i < ccb->q_depth; i++) {
106 cmpl = &((struct bna_cq_entry *)ccb->sw_q)[i];
107 cmpl->valid = 0;
108 }
109 }
110
111 /* Tx Datapath functions */
112
113
114 /* Caller should ensure that the entry at unmap_q[index] is valid */
115 static u32
116 bnad_tx_buff_unmap(struct bnad *bnad,
117 struct bnad_tx_unmap *unmap_q,
118 u32 q_depth, u32 index)
119 {
120 struct bnad_tx_unmap *unmap;
121 struct sk_buff *skb;
122 int vector, nvecs;
123
124 unmap = &unmap_q[index];
125 nvecs = unmap->nvecs;
126
127 skb = unmap->skb;
128 unmap->skb = NULL;
129 unmap->nvecs = 0;
130 dma_unmap_single(&bnad->pcidev->dev,
131 dma_unmap_addr(&unmap->vectors[0], dma_addr),
132 skb_headlen(skb), DMA_TO_DEVICE);
133 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, 0);
134 nvecs--;
135
136 vector = 0;
137 while (nvecs) {
138 vector++;
139 if (vector == BFI_TX_MAX_VECTORS_PER_WI) {
140 vector = 0;
141 BNA_QE_INDX_INC(index, q_depth);
142 unmap = &unmap_q[index];
143 }
144
145 dma_unmap_page(&bnad->pcidev->dev,
146 dma_unmap_addr(&unmap->vectors[vector], dma_addr),
147 dma_unmap_len(&unmap->vectors[vector], dma_len),
148 DMA_TO_DEVICE);
149 dma_unmap_addr_set(&unmap->vectors[vector], dma_addr, 0);
150 nvecs--;
151 }
152
153 BNA_QE_INDX_INC(index, q_depth);
154
155 return index;
156 }
157
158 /*
159 * Frees all pending Tx Bufs
160 * At this point no activity is expected on the Q,
161 * so DMA unmap & freeing is fine.
162 */
163 static void
164 bnad_txq_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
165 {
166 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
167 struct sk_buff *skb;
168 int i;
169
170 for (i = 0; i < tcb->q_depth; i++) {
171 skb = unmap_q[i].skb;
172 if (!skb)
173 continue;
174 bnad_tx_buff_unmap(bnad, unmap_q, tcb->q_depth, i);
175
176 dev_kfree_skb_any(skb);
177 }
178 }
179
180 /*
181 * bnad_txcmpl_process : Frees the Tx bufs on Tx completion
182 * Can be called in a) Interrupt context
183 * b) Sending context
184 */
185 static u32
186 bnad_txcmpl_process(struct bnad *bnad, struct bna_tcb *tcb)
187 {
188 u32 sent_packets = 0, sent_bytes = 0;
189 u32 wis, unmap_wis, hw_cons, cons, q_depth;
190 struct bnad_tx_unmap *unmap_q = tcb->unmap_q;
191 struct bnad_tx_unmap *unmap;
192 struct sk_buff *skb;
193
194 /* Just return if TX is stopped */
195 if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
196 return 0;
197
198 hw_cons = *(tcb->hw_consumer_index);
199 cons = tcb->consumer_index;
200 q_depth = tcb->q_depth;
201
202 wis = BNA_Q_INDEX_CHANGE(cons, hw_cons, q_depth);
203 BUG_ON(!(wis <= BNA_QE_IN_USE_CNT(tcb, tcb->q_depth)));
204
205 while (wis) {
206 unmap = &unmap_q[cons];
207
208 skb = unmap->skb;
209
210 sent_packets++;
211 sent_bytes += skb->len;
212
213 unmap_wis = BNA_TXQ_WI_NEEDED(unmap->nvecs);
214 wis -= unmap_wis;
215
216 cons = bnad_tx_buff_unmap(bnad, unmap_q, q_depth, cons);
217 dev_kfree_skb_any(skb);
218 }
219
220 /* Update consumer pointers. */
221 tcb->consumer_index = hw_cons;
222
223 tcb->txq->tx_packets += sent_packets;
224 tcb->txq->tx_bytes += sent_bytes;
225
226 return sent_packets;
227 }
228
229 static u32
230 bnad_tx_complete(struct bnad *bnad, struct bna_tcb *tcb)
231 {
232 struct net_device *netdev = bnad->netdev;
233 u32 sent = 0;
234
235 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
236 return 0;
237
238 sent = bnad_txcmpl_process(bnad, tcb);
239 if (sent) {
240 if (netif_queue_stopped(netdev) &&
241 netif_carrier_ok(netdev) &&
242 BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
243 BNAD_NETIF_WAKE_THRESHOLD) {
244 if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
245 netif_wake_queue(netdev);
246 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
247 }
248 }
249 }
250
251 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
252 bna_ib_ack(tcb->i_dbell, sent);
253
254 smp_mb__before_atomic();
255 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
256
257 return sent;
258 }
259
260 /* MSIX Tx Completion Handler */
261 static irqreturn_t
262 bnad_msix_tx(int irq, void *data)
263 {
264 struct bna_tcb *tcb = (struct bna_tcb *)data;
265 struct bnad *bnad = tcb->bnad;
266
267 bnad_tx_complete(bnad, tcb);
268
269 return IRQ_HANDLED;
270 }
271
272 static inline void
273 bnad_rxq_alloc_uninit(struct bnad *bnad, struct bna_rcb *rcb)
274 {
275 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
276
277 unmap_q->reuse_pi = -1;
278 unmap_q->alloc_order = -1;
279 unmap_q->map_size = 0;
280 unmap_q->type = BNAD_RXBUF_NONE;
281 }
282
283 /* Default is page-based allocation. Multi-buffer support - TBD */
284 static int
285 bnad_rxq_alloc_init(struct bnad *bnad, struct bna_rcb *rcb)
286 {
287 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
288 int order;
289
290 bnad_rxq_alloc_uninit(bnad, rcb);
291
292 order = get_order(rcb->rxq->buffer_size);
293
294 unmap_q->type = BNAD_RXBUF_PAGE;
295
296 if (bna_is_small_rxq(rcb->id)) {
297 unmap_q->alloc_order = 0;
298 unmap_q->map_size = rcb->rxq->buffer_size;
299 } else {
300 if (rcb->rxq->multi_buffer) {
301 unmap_q->alloc_order = 0;
302 unmap_q->map_size = rcb->rxq->buffer_size;
303 unmap_q->type = BNAD_RXBUF_MULTI_BUFF;
304 } else {
305 unmap_q->alloc_order = order;
306 unmap_q->map_size =
307 (rcb->rxq->buffer_size > 2048) ?
308 PAGE_SIZE << order : 2048;
309 }
310 }
311
312 BUG_ON((PAGE_SIZE << order) % unmap_q->map_size);
313
314 return 0;
315 }
316
317 static inline void
318 bnad_rxq_cleanup_page(struct bnad *bnad, struct bnad_rx_unmap *unmap)
319 {
320 if (!unmap->page)
321 return;
322
323 dma_unmap_page(&bnad->pcidev->dev,
324 dma_unmap_addr(&unmap->vector, dma_addr),
325 unmap->vector.len, DMA_FROM_DEVICE);
326 put_page(unmap->page);
327 unmap->page = NULL;
328 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
329 unmap->vector.len = 0;
330 }
331
332 static inline void
333 bnad_rxq_cleanup_skb(struct bnad *bnad, struct bnad_rx_unmap *unmap)
334 {
335 if (!unmap->skb)
336 return;
337
338 dma_unmap_single(&bnad->pcidev->dev,
339 dma_unmap_addr(&unmap->vector, dma_addr),
340 unmap->vector.len, DMA_FROM_DEVICE);
341 dev_kfree_skb_any(unmap->skb);
342 unmap->skb = NULL;
343 dma_unmap_addr_set(&unmap->vector, dma_addr, 0);
344 unmap->vector.len = 0;
345 }
346
347 static void
348 bnad_rxq_cleanup(struct bnad *bnad, struct bna_rcb *rcb)
349 {
350 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
351 int i;
352
353 for (i = 0; i < rcb->q_depth; i++) {
354 struct bnad_rx_unmap *unmap = &unmap_q->unmap[i];
355
356 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
357 bnad_rxq_cleanup_skb(bnad, unmap);
358 else
359 bnad_rxq_cleanup_page(bnad, unmap);
360 }
361 bnad_rxq_alloc_uninit(bnad, rcb);
362 }
363
364 static u32
365 bnad_rxq_refill_page(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
366 {
367 u32 alloced, prod, q_depth;
368 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
369 struct bnad_rx_unmap *unmap, *prev;
370 struct bna_rxq_entry *rxent;
371 struct page *page;
372 u32 page_offset, alloc_size;
373 dma_addr_t dma_addr;
374
375 prod = rcb->producer_index;
376 q_depth = rcb->q_depth;
377
378 alloc_size = PAGE_SIZE << unmap_q->alloc_order;
379 alloced = 0;
380
381 while (nalloc--) {
382 unmap = &unmap_q->unmap[prod];
383
384 if (unmap_q->reuse_pi < 0) {
385 page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
386 unmap_q->alloc_order);
387 page_offset = 0;
388 } else {
389 prev = &unmap_q->unmap[unmap_q->reuse_pi];
390 page = prev->page;
391 page_offset = prev->page_offset + unmap_q->map_size;
392 get_page(page);
393 }
394
395 if (unlikely(!page)) {
396 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
397 rcb->rxq->rxbuf_alloc_failed++;
398 goto finishing;
399 }
400
401 dma_addr = dma_map_page(&bnad->pcidev->dev, page, page_offset,
402 unmap_q->map_size, DMA_FROM_DEVICE);
403
404 unmap->page = page;
405 unmap->page_offset = page_offset;
406 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
407 unmap->vector.len = unmap_q->map_size;
408 page_offset += unmap_q->map_size;
409
410 if (page_offset < alloc_size)
411 unmap_q->reuse_pi = prod;
412 else
413 unmap_q->reuse_pi = -1;
414
415 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
416 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
417 BNA_QE_INDX_INC(prod, q_depth);
418 alloced++;
419 }
420
421 finishing:
422 if (likely(alloced)) {
423 rcb->producer_index = prod;
424 smp_mb();
425 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
426 bna_rxq_prod_indx_doorbell(rcb);
427 }
428
429 return alloced;
430 }
431
432 static u32
433 bnad_rxq_refill_skb(struct bnad *bnad, struct bna_rcb *rcb, u32 nalloc)
434 {
435 u32 alloced, prod, q_depth, buff_sz;
436 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
437 struct bnad_rx_unmap *unmap;
438 struct bna_rxq_entry *rxent;
439 struct sk_buff *skb;
440 dma_addr_t dma_addr;
441
442 buff_sz = rcb->rxq->buffer_size;
443 prod = rcb->producer_index;
444 q_depth = rcb->q_depth;
445
446 alloced = 0;
447 while (nalloc--) {
448 unmap = &unmap_q->unmap[prod];
449
450 skb = netdev_alloc_skb_ip_align(bnad->netdev, buff_sz);
451
452 if (unlikely(!skb)) {
453 BNAD_UPDATE_CTR(bnad, rxbuf_alloc_failed);
454 rcb->rxq->rxbuf_alloc_failed++;
455 goto finishing;
456 }
457 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
458 buff_sz, DMA_FROM_DEVICE);
459
460 unmap->skb = skb;
461 dma_unmap_addr_set(&unmap->vector, dma_addr, dma_addr);
462 unmap->vector.len = buff_sz;
463
464 rxent = &((struct bna_rxq_entry *)rcb->sw_q)[prod];
465 BNA_SET_DMA_ADDR(dma_addr, &rxent->host_addr);
466 BNA_QE_INDX_INC(prod, q_depth);
467 alloced++;
468 }
469
470 finishing:
471 if (likely(alloced)) {
472 rcb->producer_index = prod;
473 smp_mb();
474 if (likely(test_bit(BNAD_RXQ_POST_OK, &rcb->flags)))
475 bna_rxq_prod_indx_doorbell(rcb);
476 }
477
478 return alloced;
479 }
480
481 static inline void
482 bnad_rxq_post(struct bnad *bnad, struct bna_rcb *rcb)
483 {
484 struct bnad_rx_unmap_q *unmap_q = rcb->unmap_q;
485 u32 to_alloc;
486
487 to_alloc = BNA_QE_FREE_CNT(rcb, rcb->q_depth);
488 if (!(to_alloc >> BNAD_RXQ_REFILL_THRESHOLD_SHIFT))
489 return;
490
491 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
492 bnad_rxq_refill_skb(bnad, rcb, to_alloc);
493 else
494 bnad_rxq_refill_page(bnad, rcb, to_alloc);
495 }
496
497 #define flags_cksum_prot_mask (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
498 BNA_CQ_EF_IPV6 | \
499 BNA_CQ_EF_TCP | BNA_CQ_EF_UDP | \
500 BNA_CQ_EF_L4_CKSUM_OK)
501
502 #define flags_tcp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
503 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
504 #define flags_tcp6 (BNA_CQ_EF_IPV6 | \
505 BNA_CQ_EF_TCP | BNA_CQ_EF_L4_CKSUM_OK)
506 #define flags_udp4 (BNA_CQ_EF_IPV4 | BNA_CQ_EF_L3_CKSUM_OK | \
507 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
508 #define flags_udp6 (BNA_CQ_EF_IPV6 | \
509 BNA_CQ_EF_UDP | BNA_CQ_EF_L4_CKSUM_OK)
510
511 static void
512 bnad_cq_drop_packet(struct bnad *bnad, struct bna_rcb *rcb,
513 u32 sop_ci, u32 nvecs)
514 {
515 struct bnad_rx_unmap_q *unmap_q;
516 struct bnad_rx_unmap *unmap;
517 u32 ci, vec;
518
519 unmap_q = rcb->unmap_q;
520 for (vec = 0, ci = sop_ci; vec < nvecs; vec++) {
521 unmap = &unmap_q->unmap[ci];
522 BNA_QE_INDX_INC(ci, rcb->q_depth);
523
524 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
525 bnad_rxq_cleanup_skb(bnad, unmap);
526 else
527 bnad_rxq_cleanup_page(bnad, unmap);
528 }
529 }
530
531 static void
532 bnad_cq_setup_skb_frags(struct bna_rcb *rcb, struct sk_buff *skb,
533 u32 sop_ci, u32 nvecs, u32 last_fraglen)
534 {
535 struct bnad *bnad;
536 u32 ci, vec, len, totlen = 0;
537 struct bnad_rx_unmap_q *unmap_q;
538 struct bnad_rx_unmap *unmap;
539
540 unmap_q = rcb->unmap_q;
541 bnad = rcb->bnad;
542
543 /* prefetch header */
544 prefetch(page_address(unmap_q->unmap[sop_ci].page) +
545 unmap_q->unmap[sop_ci].page_offset);
546
547 for (vec = 1, ci = sop_ci; vec <= nvecs; vec++) {
548 unmap = &unmap_q->unmap[ci];
549 BNA_QE_INDX_INC(ci, rcb->q_depth);
550
551 dma_unmap_page(&bnad->pcidev->dev,
552 dma_unmap_addr(&unmap->vector, dma_addr),
553 unmap->vector.len, DMA_FROM_DEVICE);
554
555 len = (vec == nvecs) ?
556 last_fraglen : unmap->vector.len;
557 skb->truesize += unmap->vector.len;
558 totlen += len;
559
560 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
561 unmap->page, unmap->page_offset, len);
562
563 unmap->page = NULL;
564 unmap->vector.len = 0;
565 }
566
567 skb->len += totlen;
568 skb->data_len += totlen;
569 }
570
571 static inline void
572 bnad_cq_setup_skb(struct bnad *bnad, struct sk_buff *skb,
573 struct bnad_rx_unmap *unmap, u32 len)
574 {
575 prefetch(skb->data);
576
577 dma_unmap_single(&bnad->pcidev->dev,
578 dma_unmap_addr(&unmap->vector, dma_addr),
579 unmap->vector.len, DMA_FROM_DEVICE);
580
581 skb_put(skb, len);
582 skb->protocol = eth_type_trans(skb, bnad->netdev);
583
584 unmap->skb = NULL;
585 unmap->vector.len = 0;
586 }
587
588 static u32
589 bnad_cq_process(struct bnad *bnad, struct bna_ccb *ccb, int budget)
590 {
591 struct bna_cq_entry *cq, *cmpl, *next_cmpl;
592 struct bna_rcb *rcb = NULL;
593 struct bnad_rx_unmap_q *unmap_q;
594 struct bnad_rx_unmap *unmap = NULL;
595 struct sk_buff *skb = NULL;
596 struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
597 struct bnad_rx_ctrl *rx_ctrl = ccb->ctrl;
598 u32 packets = 0, len = 0, totlen = 0;
599 u32 pi, vec, sop_ci = 0, nvecs = 0;
600 u32 flags, masked_flags;
601
602 prefetch(bnad->netdev);
603
604 cq = ccb->sw_q;
605
606 while (packets < budget) {
607 cmpl = &cq[ccb->producer_index];
608 if (!cmpl->valid)
609 break;
610 /* The 'valid' field is set by the adapter, only after writing
611 * the other fields of completion entry. Hence, do not load
612 * other fields of completion entry *before* the 'valid' is
613 * loaded. Adding the rmb() here prevents the compiler and/or
614 * CPU from reordering the reads which would potentially result
615 * in reading stale values in completion entry.
616 */
617 rmb();
618
619 BNA_UPDATE_PKT_CNT(pkt_rt, ntohs(cmpl->length));
620
621 if (bna_is_small_rxq(cmpl->rxq_id))
622 rcb = ccb->rcb[1];
623 else
624 rcb = ccb->rcb[0];
625
626 unmap_q = rcb->unmap_q;
627
628 /* start of packet ci */
629 sop_ci = rcb->consumer_index;
630
631 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type)) {
632 unmap = &unmap_q->unmap[sop_ci];
633 skb = unmap->skb;
634 } else {
635 skb = napi_get_frags(&rx_ctrl->napi);
636 if (unlikely(!skb))
637 break;
638 }
639 prefetch(skb);
640
641 flags = ntohl(cmpl->flags);
642 len = ntohs(cmpl->length);
643 totlen = len;
644 nvecs = 1;
645
646 /* Check all the completions for this frame.
647 * busy-wait doesn't help much, break here.
648 */
649 if (BNAD_RXBUF_IS_MULTI_BUFF(unmap_q->type) &&
650 (flags & BNA_CQ_EF_EOP) == 0) {
651 pi = ccb->producer_index;
652 do {
653 BNA_QE_INDX_INC(pi, ccb->q_depth);
654 next_cmpl = &cq[pi];
655
656 if (!next_cmpl->valid)
657 break;
658 /* The 'valid' field is set by the adapter, only
659 * after writing the other fields of completion
660 * entry. Hence, do not load other fields of
661 * completion entry *before* the 'valid' is
662 * loaded. Adding the rmb() here prevents the
663 * compiler and/or CPU from reordering the reads
664 * which would potentially result in reading
665 * stale values in completion entry.
666 */
667 rmb();
668
669 len = ntohs(next_cmpl->length);
670 flags = ntohl(next_cmpl->flags);
671
672 nvecs++;
673 totlen += len;
674 } while ((flags & BNA_CQ_EF_EOP) == 0);
675
676 if (!next_cmpl->valid)
677 break;
678 }
679 packets++;
680
681 /* TODO: BNA_CQ_EF_LOCAL ? */
682 if (unlikely(flags & (BNA_CQ_EF_MAC_ERROR |
683 BNA_CQ_EF_FCS_ERROR |
684 BNA_CQ_EF_TOO_LONG))) {
685 bnad_cq_drop_packet(bnad, rcb, sop_ci, nvecs);
686 rcb->rxq->rx_packets_with_error++;
687
688 goto next;
689 }
690
691 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
692 bnad_cq_setup_skb(bnad, skb, unmap, len);
693 else
694 bnad_cq_setup_skb_frags(rcb, skb, sop_ci, nvecs, len);
695
696 rcb->rxq->rx_packets++;
697 rcb->rxq->rx_bytes += totlen;
698 ccb->bytes_per_intr += totlen;
699
700 masked_flags = flags & flags_cksum_prot_mask;
701
702 if (likely
703 ((bnad->netdev->features & NETIF_F_RXCSUM) &&
704 ((masked_flags == flags_tcp4) ||
705 (masked_flags == flags_udp4) ||
706 (masked_flags == flags_tcp6) ||
707 (masked_flags == flags_udp6))))
708 skb->ip_summed = CHECKSUM_UNNECESSARY;
709 else
710 skb_checksum_none_assert(skb);
711
712 if ((flags & BNA_CQ_EF_VLAN) &&
713 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX))
714 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(cmpl->vlan_tag));
715
716 if (BNAD_RXBUF_IS_SK_BUFF(unmap_q->type))
717 netif_receive_skb(skb);
718 else
719 napi_gro_frags(&rx_ctrl->napi);
720
721 next:
722 BNA_QE_INDX_ADD(rcb->consumer_index, nvecs, rcb->q_depth);
723 for (vec = 0; vec < nvecs; vec++) {
724 cmpl = &cq[ccb->producer_index];
725 cmpl->valid = 0;
726 BNA_QE_INDX_INC(ccb->producer_index, ccb->q_depth);
727 }
728 }
729
730 napi_gro_flush(&rx_ctrl->napi, false);
731 if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
732 bna_ib_ack_disable_irq(ccb->i_dbell, packets);
733
734 bnad_rxq_post(bnad, ccb->rcb[0]);
735 if (ccb->rcb[1])
736 bnad_rxq_post(bnad, ccb->rcb[1]);
737
738 return packets;
739 }
740
741 static void
742 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
743 {
744 struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
745 struct napi_struct *napi = &rx_ctrl->napi;
746
747 if (likely(napi_schedule_prep(napi))) {
748 __napi_schedule(napi);
749 rx_ctrl->rx_schedule++;
750 }
751 }
752
753 /* MSIX Rx Path Handler */
754 static irqreturn_t
755 bnad_msix_rx(int irq, void *data)
756 {
757 struct bna_ccb *ccb = (struct bna_ccb *)data;
758
759 if (ccb) {
760 ((struct bnad_rx_ctrl *)ccb->ctrl)->rx_intr_ctr++;
761 bnad_netif_rx_schedule_poll(ccb->bnad, ccb);
762 }
763
764 return IRQ_HANDLED;
765 }
766
767 /* Interrupt handlers */
768
769 /* Mbox Interrupt Handlers */
770 static irqreturn_t
771 bnad_msix_mbox_handler(int irq, void *data)
772 {
773 u32 intr_status;
774 unsigned long flags;
775 struct bnad *bnad = (struct bnad *)data;
776
777 spin_lock_irqsave(&bnad->bna_lock, flags);
778 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
779 spin_unlock_irqrestore(&bnad->bna_lock, flags);
780 return IRQ_HANDLED;
781 }
782
783 bna_intr_status_get(&bnad->bna, intr_status);
784
785 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
786 bna_mbox_handler(&bnad->bna, intr_status);
787
788 spin_unlock_irqrestore(&bnad->bna_lock, flags);
789
790 return IRQ_HANDLED;
791 }
792
793 static irqreturn_t
794 bnad_isr(int irq, void *data)
795 {
796 int i, j;
797 u32 intr_status;
798 unsigned long flags;
799 struct bnad *bnad = (struct bnad *)data;
800 struct bnad_rx_info *rx_info;
801 struct bnad_rx_ctrl *rx_ctrl;
802 struct bna_tcb *tcb = NULL;
803
804 spin_lock_irqsave(&bnad->bna_lock, flags);
805 if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))) {
806 spin_unlock_irqrestore(&bnad->bna_lock, flags);
807 return IRQ_NONE;
808 }
809
810 bna_intr_status_get(&bnad->bna, intr_status);
811
812 if (unlikely(!intr_status)) {
813 spin_unlock_irqrestore(&bnad->bna_lock, flags);
814 return IRQ_NONE;
815 }
816
817 if (BNA_IS_MBOX_ERR_INTR(&bnad->bna, intr_status))
818 bna_mbox_handler(&bnad->bna, intr_status);
819
820 spin_unlock_irqrestore(&bnad->bna_lock, flags);
821
822 if (!BNA_IS_INTX_DATA_INTR(intr_status))
823 return IRQ_HANDLED;
824
825 /* Process data interrupts */
826 /* Tx processing */
827 for (i = 0; i < bnad->num_tx; i++) {
828 for (j = 0; j < bnad->num_txq_per_tx; j++) {
829 tcb = bnad->tx_info[i].tcb[j];
830 if (tcb && test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
831 bnad_tx_complete(bnad, bnad->tx_info[i].tcb[j]);
832 }
833 }
834 /* Rx processing */
835 for (i = 0; i < bnad->num_rx; i++) {
836 rx_info = &bnad->rx_info[i];
837 if (!rx_info->rx)
838 continue;
839 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
840 rx_ctrl = &rx_info->rx_ctrl[j];
841 if (rx_ctrl->ccb)
842 bnad_netif_rx_schedule_poll(bnad,
843 rx_ctrl->ccb);
844 }
845 }
846 return IRQ_HANDLED;
847 }
848
849 /*
850 * Called in interrupt / callback context
851 * with bna_lock held, so cfg_flags access is OK
852 */
853 static void
854 bnad_enable_mbox_irq(struct bnad *bnad)
855 {
856 clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
857
858 BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
859 }
860
861 /*
862 * Called with bnad->bna_lock held b'cos of
863 * bnad->cfg_flags access.
864 */
865 static void
866 bnad_disable_mbox_irq(struct bnad *bnad)
867 {
868 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
869
870 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
871 }
872
873 static void
874 bnad_set_netdev_perm_addr(struct bnad *bnad)
875 {
876 struct net_device *netdev = bnad->netdev;
877
878 ether_addr_copy(netdev->perm_addr, bnad->perm_addr);
879 if (is_zero_ether_addr(netdev->dev_addr))
880 ether_addr_copy(netdev->dev_addr, bnad->perm_addr);
881 }
882
883 /* Control Path Handlers */
884
885 /* Callbacks */
886 void
887 bnad_cb_mbox_intr_enable(struct bnad *bnad)
888 {
889 bnad_enable_mbox_irq(bnad);
890 }
891
892 void
893 bnad_cb_mbox_intr_disable(struct bnad *bnad)
894 {
895 bnad_disable_mbox_irq(bnad);
896 }
897
898 void
899 bnad_cb_ioceth_ready(struct bnad *bnad)
900 {
901 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
902 complete(&bnad->bnad_completions.ioc_comp);
903 }
904
905 void
906 bnad_cb_ioceth_failed(struct bnad *bnad)
907 {
908 bnad->bnad_completions.ioc_comp_status = BNA_CB_FAIL;
909 complete(&bnad->bnad_completions.ioc_comp);
910 }
911
912 void
913 bnad_cb_ioceth_disabled(struct bnad *bnad)
914 {
915 bnad->bnad_completions.ioc_comp_status = BNA_CB_SUCCESS;
916 complete(&bnad->bnad_completions.ioc_comp);
917 }
918
919 static void
920 bnad_cb_enet_disabled(void *arg)
921 {
922 struct bnad *bnad = (struct bnad *)arg;
923
924 netif_carrier_off(bnad->netdev);
925 complete(&bnad->bnad_completions.enet_comp);
926 }
927
928 void
929 bnad_cb_ethport_link_status(struct bnad *bnad,
930 enum bna_link_status link_status)
931 {
932 bool link_up = false;
933
934 link_up = (link_status == BNA_LINK_UP) || (link_status == BNA_CEE_UP);
935
936 if (link_status == BNA_CEE_UP) {
937 if (!test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
938 BNAD_UPDATE_CTR(bnad, cee_toggle);
939 set_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
940 } else {
941 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags))
942 BNAD_UPDATE_CTR(bnad, cee_toggle);
943 clear_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags);
944 }
945
946 if (link_up) {
947 if (!netif_carrier_ok(bnad->netdev)) {
948 uint tx_id, tcb_id;
949 netdev_info(bnad->netdev, "link up\n");
950 netif_carrier_on(bnad->netdev);
951 BNAD_UPDATE_CTR(bnad, link_toggle);
952 for (tx_id = 0; tx_id < bnad->num_tx; tx_id++) {
953 for (tcb_id = 0; tcb_id < bnad->num_txq_per_tx;
954 tcb_id++) {
955 struct bna_tcb *tcb =
956 bnad->tx_info[tx_id].tcb[tcb_id];
957 u32 txq_id;
958 if (!tcb)
959 continue;
960
961 txq_id = tcb->id;
962
963 if (test_bit(BNAD_TXQ_TX_STARTED,
964 &tcb->flags)) {
965 /*
966 * Force an immediate
967 * Transmit Schedule */
968 netif_wake_subqueue(
969 bnad->netdev,
970 txq_id);
971 BNAD_UPDATE_CTR(bnad,
972 netif_queue_wakeup);
973 } else {
974 netif_stop_subqueue(
975 bnad->netdev,
976 txq_id);
977 BNAD_UPDATE_CTR(bnad,
978 netif_queue_stop);
979 }
980 }
981 }
982 }
983 } else {
984 if (netif_carrier_ok(bnad->netdev)) {
985 netdev_info(bnad->netdev, "link down\n");
986 netif_carrier_off(bnad->netdev);
987 BNAD_UPDATE_CTR(bnad, link_toggle);
988 }
989 }
990 }
991
992 static void
993 bnad_cb_tx_disabled(void *arg, struct bna_tx *tx)
994 {
995 struct bnad *bnad = (struct bnad *)arg;
996
997 complete(&bnad->bnad_completions.tx_comp);
998 }
999
1000 static void
1001 bnad_cb_tcb_setup(struct bnad *bnad, struct bna_tcb *tcb)
1002 {
1003 struct bnad_tx_info *tx_info =
1004 (struct bnad_tx_info *)tcb->txq->tx->priv;
1005
1006 tcb->priv = tcb;
1007 tx_info->tcb[tcb->id] = tcb;
1008 }
1009
1010 static void
1011 bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
1012 {
1013 struct bnad_tx_info *tx_info =
1014 (struct bnad_tx_info *)tcb->txq->tx->priv;
1015
1016 tx_info->tcb[tcb->id] = NULL;
1017 tcb->priv = NULL;
1018 }
1019
1020 static void
1021 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
1022 {
1023 struct bnad_rx_info *rx_info =
1024 (struct bnad_rx_info *)ccb->cq->rx->priv;
1025
1026 rx_info->rx_ctrl[ccb->id].ccb = ccb;
1027 ccb->ctrl = &rx_info->rx_ctrl[ccb->id];
1028 }
1029
1030 static void
1031 bnad_cb_ccb_destroy(struct bnad *bnad, struct bna_ccb *ccb)
1032 {
1033 struct bnad_rx_info *rx_info =
1034 (struct bnad_rx_info *)ccb->cq->rx->priv;
1035
1036 rx_info->rx_ctrl[ccb->id].ccb = NULL;
1037 }
1038
1039 static void
1040 bnad_cb_tx_stall(struct bnad *bnad, struct bna_tx *tx)
1041 {
1042 struct bnad_tx_info *tx_info =
1043 (struct bnad_tx_info *)tx->priv;
1044 struct bna_tcb *tcb;
1045 u32 txq_id;
1046 int i;
1047
1048 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1049 tcb = tx_info->tcb[i];
1050 if (!tcb)
1051 continue;
1052 txq_id = tcb->id;
1053 clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1054 netif_stop_subqueue(bnad->netdev, txq_id);
1055 }
1056 }
1057
1058 static void
1059 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tx *tx)
1060 {
1061 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1062 struct bna_tcb *tcb;
1063 u32 txq_id;
1064 int i;
1065
1066 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1067 tcb = tx_info->tcb[i];
1068 if (!tcb)
1069 continue;
1070 txq_id = tcb->id;
1071
1072 BUG_ON(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags));
1073 set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
1074 BUG_ON(*(tcb->hw_consumer_index) != 0);
1075
1076 if (netif_carrier_ok(bnad->netdev)) {
1077 netif_wake_subqueue(bnad->netdev, txq_id);
1078 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
1079 }
1080 }
1081
1082 /*
1083 * Workaround for first ioceth enable failure & we
1084 * get a 0 MAC address. We try to get the MAC address
1085 * again here.
1086 */
1087 if (is_zero_ether_addr(bnad->perm_addr)) {
1088 bna_enet_perm_mac_get(&bnad->bna.enet, bnad->perm_addr);
1089 bnad_set_netdev_perm_addr(bnad);
1090 }
1091 }
1092
1093 /*
1094 * Free all TxQs buffers and then notify TX_E_CLEANUP_DONE to Tx fsm.
1095 */
1096 static void
1097 bnad_tx_cleanup(struct delayed_work *work)
1098 {
1099 struct bnad_tx_info *tx_info =
1100 container_of(work, struct bnad_tx_info, tx_cleanup_work);
1101 struct bnad *bnad = NULL;
1102 struct bna_tcb *tcb;
1103 unsigned long flags;
1104 u32 i, pending = 0;
1105
1106 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1107 tcb = tx_info->tcb[i];
1108 if (!tcb)
1109 continue;
1110
1111 bnad = tcb->bnad;
1112
1113 if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
1114 pending++;
1115 continue;
1116 }
1117
1118 bnad_txq_cleanup(bnad, tcb);
1119
1120 smp_mb__before_atomic();
1121 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
1122 }
1123
1124 if (pending) {
1125 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work,
1126 msecs_to_jiffies(1));
1127 return;
1128 }
1129
1130 spin_lock_irqsave(&bnad->bna_lock, flags);
1131 bna_tx_cleanup_complete(tx_info->tx);
1132 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1133 }
1134
1135 static void
1136 bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tx *tx)
1137 {
1138 struct bnad_tx_info *tx_info = (struct bnad_tx_info *)tx->priv;
1139 struct bna_tcb *tcb;
1140 int i;
1141
1142 for (i = 0; i < BNAD_MAX_TXQ_PER_TX; i++) {
1143 tcb = tx_info->tcb[i];
1144 if (!tcb)
1145 continue;
1146 }
1147
1148 queue_delayed_work(bnad->work_q, &tx_info->tx_cleanup_work, 0);
1149 }
1150
1151 static void
1152 bnad_cb_rx_stall(struct bnad *bnad, struct bna_rx *rx)
1153 {
1154 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1155 struct bna_ccb *ccb;
1156 struct bnad_rx_ctrl *rx_ctrl;
1157 int i;
1158
1159 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1160 rx_ctrl = &rx_info->rx_ctrl[i];
1161 ccb = rx_ctrl->ccb;
1162 if (!ccb)
1163 continue;
1164
1165 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[0]->flags);
1166
1167 if (ccb->rcb[1])
1168 clear_bit(BNAD_RXQ_POST_OK, &ccb->rcb[1]->flags);
1169 }
1170 }
1171
1172 /*
1173 * Free all RxQs buffers and then notify RX_E_CLEANUP_DONE to Rx fsm.
1174 */
1175 static void
1176 bnad_rx_cleanup(void *work)
1177 {
1178 struct bnad_rx_info *rx_info =
1179 container_of(work, struct bnad_rx_info, rx_cleanup_work);
1180 struct bnad_rx_ctrl *rx_ctrl;
1181 struct bnad *bnad = NULL;
1182 unsigned long flags;
1183 u32 i;
1184
1185 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1186 rx_ctrl = &rx_info->rx_ctrl[i];
1187
1188 if (!rx_ctrl->ccb)
1189 continue;
1190
1191 bnad = rx_ctrl->ccb->bnad;
1192
1193 /*
1194 * Wait till the poll handler has exited
1195 * and nothing can be scheduled anymore
1196 */
1197 napi_disable(&rx_ctrl->napi);
1198
1199 bnad_cq_cleanup(bnad, rx_ctrl->ccb);
1200 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[0]);
1201 if (rx_ctrl->ccb->rcb[1])
1202 bnad_rxq_cleanup(bnad, rx_ctrl->ccb->rcb[1]);
1203 }
1204
1205 spin_lock_irqsave(&bnad->bna_lock, flags);
1206 bna_rx_cleanup_complete(rx_info->rx);
1207 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1208 }
1209
1210 static void
1211 bnad_cb_rx_cleanup(struct bnad *bnad, struct bna_rx *rx)
1212 {
1213 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1214 struct bna_ccb *ccb;
1215 struct bnad_rx_ctrl *rx_ctrl;
1216 int i;
1217
1218 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1219 rx_ctrl = &rx_info->rx_ctrl[i];
1220 ccb = rx_ctrl->ccb;
1221 if (!ccb)
1222 continue;
1223
1224 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
1225
1226 if (ccb->rcb[1])
1227 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
1228 }
1229
1230 queue_work(bnad->work_q, &rx_info->rx_cleanup_work);
1231 }
1232
1233 static void
1234 bnad_cb_rx_post(struct bnad *bnad, struct bna_rx *rx)
1235 {
1236 struct bnad_rx_info *rx_info = (struct bnad_rx_info *)rx->priv;
1237 struct bna_ccb *ccb;
1238 struct bna_rcb *rcb;
1239 struct bnad_rx_ctrl *rx_ctrl;
1240 int i, j;
1241
1242 for (i = 0; i < BNAD_MAX_RXP_PER_RX; i++) {
1243 rx_ctrl = &rx_info->rx_ctrl[i];
1244 ccb = rx_ctrl->ccb;
1245 if (!ccb)
1246 continue;
1247
1248 napi_enable(&rx_ctrl->napi);
1249
1250 for (j = 0; j < BNAD_MAX_RXQ_PER_RXP; j++) {
1251 rcb = ccb->rcb[j];
1252 if (!rcb)
1253 continue;
1254
1255 bnad_rxq_alloc_init(bnad, rcb);
1256 set_bit(BNAD_RXQ_STARTED, &rcb->flags);
1257 set_bit(BNAD_RXQ_POST_OK, &rcb->flags);
1258 bnad_rxq_post(bnad, rcb);
1259 }
1260 }
1261 }
1262
1263 static void
1264 bnad_cb_rx_disabled(void *arg, struct bna_rx *rx)
1265 {
1266 struct bnad *bnad = (struct bnad *)arg;
1267
1268 complete(&bnad->bnad_completions.rx_comp);
1269 }
1270
1271 static void
1272 bnad_cb_rx_mcast_add(struct bnad *bnad, struct bna_rx *rx)
1273 {
1274 bnad->bnad_completions.mcast_comp_status = BNA_CB_SUCCESS;
1275 complete(&bnad->bnad_completions.mcast_comp);
1276 }
1277
1278 void
1279 bnad_cb_stats_get(struct bnad *bnad, enum bna_cb_status status,
1280 struct bna_stats *stats)
1281 {
1282 if (status == BNA_CB_SUCCESS)
1283 BNAD_UPDATE_CTR(bnad, hw_stats_updates);
1284
1285 if (!netif_running(bnad->netdev) ||
1286 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1287 return;
1288
1289 mod_timer(&bnad->stats_timer,
1290 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1291 }
1292
1293 static void
1294 bnad_cb_enet_mtu_set(struct bnad *bnad)
1295 {
1296 bnad->bnad_completions.mtu_comp_status = BNA_CB_SUCCESS;
1297 complete(&bnad->bnad_completions.mtu_comp);
1298 }
1299
1300 void
1301 bnad_cb_completion(void *arg, enum bfa_status status)
1302 {
1303 struct bnad_iocmd_comp *iocmd_comp =
1304 (struct bnad_iocmd_comp *)arg;
1305
1306 iocmd_comp->comp_status = (u32) status;
1307 complete(&iocmd_comp->comp);
1308 }
1309
1310 /* Resource allocation, free functions */
1311
1312 static void
1313 bnad_mem_free(struct bnad *bnad,
1314 struct bna_mem_info *mem_info)
1315 {
1316 int i;
1317 dma_addr_t dma_pa;
1318
1319 if (mem_info->mdl == NULL)
1320 return;
1321
1322 for (i = 0; i < mem_info->num; i++) {
1323 if (mem_info->mdl[i].kva != NULL) {
1324 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1325 BNA_GET_DMA_ADDR(&(mem_info->mdl[i].dma),
1326 dma_pa);
1327 dma_free_coherent(&bnad->pcidev->dev,
1328 mem_info->mdl[i].len,
1329 mem_info->mdl[i].kva, dma_pa);
1330 } else
1331 kfree(mem_info->mdl[i].kva);
1332 }
1333 }
1334 kfree(mem_info->mdl);
1335 mem_info->mdl = NULL;
1336 }
1337
1338 static int
1339 bnad_mem_alloc(struct bnad *bnad,
1340 struct bna_mem_info *mem_info)
1341 {
1342 int i;
1343 dma_addr_t dma_pa;
1344
1345 if ((mem_info->num == 0) || (mem_info->len == 0)) {
1346 mem_info->mdl = NULL;
1347 return 0;
1348 }
1349
1350 mem_info->mdl = kcalloc(mem_info->num, sizeof(struct bna_mem_descr),
1351 GFP_KERNEL);
1352 if (mem_info->mdl == NULL)
1353 return -ENOMEM;
1354
1355 if (mem_info->mem_type == BNA_MEM_T_DMA) {
1356 for (i = 0; i < mem_info->num; i++) {
1357 mem_info->mdl[i].len = mem_info->len;
1358 mem_info->mdl[i].kva =
1359 dma_alloc_coherent(&bnad->pcidev->dev,
1360 mem_info->len, &dma_pa,
1361 GFP_KERNEL);
1362 if (mem_info->mdl[i].kva == NULL)
1363 goto err_return;
1364
1365 BNA_SET_DMA_ADDR(dma_pa,
1366 &(mem_info->mdl[i].dma));
1367 }
1368 } else {
1369 for (i = 0; i < mem_info->num; i++) {
1370 mem_info->mdl[i].len = mem_info->len;
1371 mem_info->mdl[i].kva = kzalloc(mem_info->len,
1372 GFP_KERNEL);
1373 if (mem_info->mdl[i].kva == NULL)
1374 goto err_return;
1375 }
1376 }
1377
1378 return 0;
1379
1380 err_return:
1381 bnad_mem_free(bnad, mem_info);
1382 return -ENOMEM;
1383 }
1384
1385 /* Free IRQ for Mailbox */
1386 static void
1387 bnad_mbox_irq_free(struct bnad *bnad)
1388 {
1389 int irq;
1390 unsigned long flags;
1391
1392 spin_lock_irqsave(&bnad->bna_lock, flags);
1393 bnad_disable_mbox_irq(bnad);
1394 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1395
1396 irq = BNAD_GET_MBOX_IRQ(bnad);
1397 free_irq(irq, bnad);
1398 }
1399
1400 /*
1401 * Allocates IRQ for Mailbox, but keep it disabled
1402 * This will be enabled once we get the mbox enable callback
1403 * from bna
1404 */
1405 static int
1406 bnad_mbox_irq_alloc(struct bnad *bnad)
1407 {
1408 int err = 0;
1409 unsigned long irq_flags, flags;
1410 u32 irq;
1411 irq_handler_t irq_handler;
1412
1413 spin_lock_irqsave(&bnad->bna_lock, flags);
1414 if (bnad->cfg_flags & BNAD_CF_MSIX) {
1415 irq_handler = (irq_handler_t)bnad_msix_mbox_handler;
1416 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
1417 irq_flags = 0;
1418 } else {
1419 irq_handler = (irq_handler_t)bnad_isr;
1420 irq = bnad->pcidev->irq;
1421 irq_flags = IRQF_SHARED;
1422 }
1423
1424 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1425 sprintf(bnad->mbox_irq_name, "%s", BNAD_NAME);
1426
1427 /*
1428 * Set the Mbox IRQ disable flag, so that the IRQ handler
1429 * called from request_irq() for SHARED IRQs do not execute
1430 */
1431 set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
1432
1433 BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
1434
1435 err = request_irq(irq, irq_handler, irq_flags,
1436 bnad->mbox_irq_name, bnad);
1437
1438 return err;
1439 }
1440
1441 static void
1442 bnad_txrx_irq_free(struct bnad *bnad, struct bna_intr_info *intr_info)
1443 {
1444 kfree(intr_info->idl);
1445 intr_info->idl = NULL;
1446 }
1447
1448 /* Allocates Interrupt Descriptor List for MSIX/INT-X vectors */
1449 static int
1450 bnad_txrx_irq_alloc(struct bnad *bnad, enum bnad_intr_source src,
1451 u32 txrx_id, struct bna_intr_info *intr_info)
1452 {
1453 int i, vector_start = 0;
1454 u32 cfg_flags;
1455 unsigned long flags;
1456
1457 spin_lock_irqsave(&bnad->bna_lock, flags);
1458 cfg_flags = bnad->cfg_flags;
1459 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1460
1461 if (cfg_flags & BNAD_CF_MSIX) {
1462 intr_info->intr_type = BNA_INTR_T_MSIX;
1463 intr_info->idl = kcalloc(intr_info->num,
1464 sizeof(struct bna_intr_descr),
1465 GFP_KERNEL);
1466 if (!intr_info->idl)
1467 return -ENOMEM;
1468
1469 switch (src) {
1470 case BNAD_INTR_TX:
1471 vector_start = BNAD_MAILBOX_MSIX_VECTORS + txrx_id;
1472 break;
1473
1474 case BNAD_INTR_RX:
1475 vector_start = BNAD_MAILBOX_MSIX_VECTORS +
1476 (bnad->num_tx * bnad->num_txq_per_tx) +
1477 txrx_id;
1478 break;
1479
1480 default:
1481 BUG();
1482 }
1483
1484 for (i = 0; i < intr_info->num; i++)
1485 intr_info->idl[i].vector = vector_start + i;
1486 } else {
1487 intr_info->intr_type = BNA_INTR_T_INTX;
1488 intr_info->num = 1;
1489 intr_info->idl = kcalloc(intr_info->num,
1490 sizeof(struct bna_intr_descr),
1491 GFP_KERNEL);
1492 if (!intr_info->idl)
1493 return -ENOMEM;
1494
1495 switch (src) {
1496 case BNAD_INTR_TX:
1497 intr_info->idl[0].vector = BNAD_INTX_TX_IB_BITMASK;
1498 break;
1499
1500 case BNAD_INTR_RX:
1501 intr_info->idl[0].vector = BNAD_INTX_RX_IB_BITMASK;
1502 break;
1503 }
1504 }
1505 return 0;
1506 }
1507
1508 /* NOTE: Should be called for MSIX only
1509 * Unregisters Tx MSIX vector(s) from the kernel
1510 */
1511 static void
1512 bnad_tx_msix_unregister(struct bnad *bnad, struct bnad_tx_info *tx_info,
1513 int num_txqs)
1514 {
1515 int i;
1516 int vector_num;
1517
1518 for (i = 0; i < num_txqs; i++) {
1519 if (tx_info->tcb[i] == NULL)
1520 continue;
1521
1522 vector_num = tx_info->tcb[i]->intr_vector;
1523 free_irq(bnad->msix_table[vector_num].vector, tx_info->tcb[i]);
1524 }
1525 }
1526
1527 /* NOTE: Should be called for MSIX only
1528 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1529 */
1530 static int
1531 bnad_tx_msix_register(struct bnad *bnad, struct bnad_tx_info *tx_info,
1532 u32 tx_id, int num_txqs)
1533 {
1534 int i;
1535 int err;
1536 int vector_num;
1537
1538 for (i = 0; i < num_txqs; i++) {
1539 vector_num = tx_info->tcb[i]->intr_vector;
1540 sprintf(tx_info->tcb[i]->name, "%s TXQ %d", bnad->netdev->name,
1541 tx_id + tx_info->tcb[i]->id);
1542 err = request_irq(bnad->msix_table[vector_num].vector,
1543 (irq_handler_t)bnad_msix_tx, 0,
1544 tx_info->tcb[i]->name,
1545 tx_info->tcb[i]);
1546 if (err)
1547 goto err_return;
1548 }
1549
1550 return 0;
1551
1552 err_return:
1553 if (i > 0)
1554 bnad_tx_msix_unregister(bnad, tx_info, (i - 1));
1555 return -1;
1556 }
1557
1558 /* NOTE: Should be called for MSIX only
1559 * Unregisters Rx MSIX vector(s) from the kernel
1560 */
1561 static void
1562 bnad_rx_msix_unregister(struct bnad *bnad, struct bnad_rx_info *rx_info,
1563 int num_rxps)
1564 {
1565 int i;
1566 int vector_num;
1567
1568 for (i = 0; i < num_rxps; i++) {
1569 if (rx_info->rx_ctrl[i].ccb == NULL)
1570 continue;
1571
1572 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1573 free_irq(bnad->msix_table[vector_num].vector,
1574 rx_info->rx_ctrl[i].ccb);
1575 }
1576 }
1577
1578 /* NOTE: Should be called for MSIX only
1579 * Registers Tx MSIX vector(s) and ISR(s), cookie with the kernel
1580 */
1581 static int
1582 bnad_rx_msix_register(struct bnad *bnad, struct bnad_rx_info *rx_info,
1583 u32 rx_id, int num_rxps)
1584 {
1585 int i;
1586 int err;
1587 int vector_num;
1588
1589 for (i = 0; i < num_rxps; i++) {
1590 vector_num = rx_info->rx_ctrl[i].ccb->intr_vector;
1591 sprintf(rx_info->rx_ctrl[i].ccb->name, "%s CQ %d",
1592 bnad->netdev->name,
1593 rx_id + rx_info->rx_ctrl[i].ccb->id);
1594 err = request_irq(bnad->msix_table[vector_num].vector,
1595 (irq_handler_t)bnad_msix_rx, 0,
1596 rx_info->rx_ctrl[i].ccb->name,
1597 rx_info->rx_ctrl[i].ccb);
1598 if (err)
1599 goto err_return;
1600 }
1601
1602 return 0;
1603
1604 err_return:
1605 if (i > 0)
1606 bnad_rx_msix_unregister(bnad, rx_info, (i - 1));
1607 return -1;
1608 }
1609
1610 /* Free Tx object Resources */
1611 static void
1612 bnad_tx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1613 {
1614 int i;
1615
1616 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1617 if (res_info[i].res_type == BNA_RES_T_MEM)
1618 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1619 else if (res_info[i].res_type == BNA_RES_T_INTR)
1620 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1621 }
1622 }
1623
1624 /* Allocates memory and interrupt resources for Tx object */
1625 static int
1626 bnad_tx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1627 u32 tx_id)
1628 {
1629 int i, err = 0;
1630
1631 for (i = 0; i < BNA_TX_RES_T_MAX; i++) {
1632 if (res_info[i].res_type == BNA_RES_T_MEM)
1633 err = bnad_mem_alloc(bnad,
1634 &res_info[i].res_u.mem_info);
1635 else if (res_info[i].res_type == BNA_RES_T_INTR)
1636 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_TX, tx_id,
1637 &res_info[i].res_u.intr_info);
1638 if (err)
1639 goto err_return;
1640 }
1641 return 0;
1642
1643 err_return:
1644 bnad_tx_res_free(bnad, res_info);
1645 return err;
1646 }
1647
1648 /* Free Rx object Resources */
1649 static void
1650 bnad_rx_res_free(struct bnad *bnad, struct bna_res_info *res_info)
1651 {
1652 int i;
1653
1654 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1655 if (res_info[i].res_type == BNA_RES_T_MEM)
1656 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
1657 else if (res_info[i].res_type == BNA_RES_T_INTR)
1658 bnad_txrx_irq_free(bnad, &res_info[i].res_u.intr_info);
1659 }
1660 }
1661
1662 /* Allocates memory and interrupt resources for Rx object */
1663 static int
1664 bnad_rx_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
1665 uint rx_id)
1666 {
1667 int i, err = 0;
1668
1669 /* All memory needs to be allocated before setup_ccbs */
1670 for (i = 0; i < BNA_RX_RES_T_MAX; i++) {
1671 if (res_info[i].res_type == BNA_RES_T_MEM)
1672 err = bnad_mem_alloc(bnad,
1673 &res_info[i].res_u.mem_info);
1674 else if (res_info[i].res_type == BNA_RES_T_INTR)
1675 err = bnad_txrx_irq_alloc(bnad, BNAD_INTR_RX, rx_id,
1676 &res_info[i].res_u.intr_info);
1677 if (err)
1678 goto err_return;
1679 }
1680 return 0;
1681
1682 err_return:
1683 bnad_rx_res_free(bnad, res_info);
1684 return err;
1685 }
1686
1687 /* Timer callbacks */
1688 /* a) IOC timer */
1689 static void
1690 bnad_ioc_timeout(unsigned long data)
1691 {
1692 struct bnad *bnad = (struct bnad *)data;
1693 unsigned long flags;
1694
1695 spin_lock_irqsave(&bnad->bna_lock, flags);
1696 bfa_nw_ioc_timeout(&bnad->bna.ioceth.ioc);
1697 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1698 }
1699
1700 static void
1701 bnad_ioc_hb_check(unsigned long data)
1702 {
1703 struct bnad *bnad = (struct bnad *)data;
1704 unsigned long flags;
1705
1706 spin_lock_irqsave(&bnad->bna_lock, flags);
1707 bfa_nw_ioc_hb_check(&bnad->bna.ioceth.ioc);
1708 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1709 }
1710
1711 static void
1712 bnad_iocpf_timeout(unsigned long data)
1713 {
1714 struct bnad *bnad = (struct bnad *)data;
1715 unsigned long flags;
1716
1717 spin_lock_irqsave(&bnad->bna_lock, flags);
1718 bfa_nw_iocpf_timeout(&bnad->bna.ioceth.ioc);
1719 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1720 }
1721
1722 static void
1723 bnad_iocpf_sem_timeout(unsigned long data)
1724 {
1725 struct bnad *bnad = (struct bnad *)data;
1726 unsigned long flags;
1727
1728 spin_lock_irqsave(&bnad->bna_lock, flags);
1729 bfa_nw_iocpf_sem_timeout(&bnad->bna.ioceth.ioc);
1730 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1731 }
1732
1733 /*
1734 * All timer routines use bnad->bna_lock to protect against
1735 * the following race, which may occur in case of no locking:
1736 * Time CPU m CPU n
1737 * 0 1 = test_bit
1738 * 1 clear_bit
1739 * 2 del_timer_sync
1740 * 3 mod_timer
1741 */
1742
1743 /* b) Dynamic Interrupt Moderation Timer */
1744 static void
1745 bnad_dim_timeout(unsigned long data)
1746 {
1747 struct bnad *bnad = (struct bnad *)data;
1748 struct bnad_rx_info *rx_info;
1749 struct bnad_rx_ctrl *rx_ctrl;
1750 int i, j;
1751 unsigned long flags;
1752
1753 if (!netif_carrier_ok(bnad->netdev))
1754 return;
1755
1756 spin_lock_irqsave(&bnad->bna_lock, flags);
1757 for (i = 0; i < bnad->num_rx; i++) {
1758 rx_info = &bnad->rx_info[i];
1759 if (!rx_info->rx)
1760 continue;
1761 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
1762 rx_ctrl = &rx_info->rx_ctrl[j];
1763 if (!rx_ctrl->ccb)
1764 continue;
1765 bna_rx_dim_update(rx_ctrl->ccb);
1766 }
1767 }
1768
1769 /* Check for BNAD_CF_DIM_ENABLED, does not eleminate a race */
1770 if (test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags))
1771 mod_timer(&bnad->dim_timer,
1772 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1773 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1774 }
1775
1776 /* c) Statistics Timer */
1777 static void
1778 bnad_stats_timeout(unsigned long data)
1779 {
1780 struct bnad *bnad = (struct bnad *)data;
1781 unsigned long flags;
1782
1783 if (!netif_running(bnad->netdev) ||
1784 !test_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1785 return;
1786
1787 spin_lock_irqsave(&bnad->bna_lock, flags);
1788 bna_hw_stats_get(&bnad->bna);
1789 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1790 }
1791
1792 /*
1793 * Set up timer for DIM
1794 * Called with bnad->bna_lock held
1795 */
1796 void
1797 bnad_dim_timer_start(struct bnad *bnad)
1798 {
1799 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
1800 !test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
1801 setup_timer(&bnad->dim_timer, bnad_dim_timeout,
1802 (unsigned long)bnad);
1803 set_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
1804 mod_timer(&bnad->dim_timer,
1805 jiffies + msecs_to_jiffies(BNAD_DIM_TIMER_FREQ));
1806 }
1807 }
1808
1809 /*
1810 * Set up timer for statistics
1811 * Called with mutex_lock(&bnad->conf_mutex) held
1812 */
1813 static void
1814 bnad_stats_timer_start(struct bnad *bnad)
1815 {
1816 unsigned long flags;
1817
1818 spin_lock_irqsave(&bnad->bna_lock, flags);
1819 if (!test_and_set_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags)) {
1820 setup_timer(&bnad->stats_timer, bnad_stats_timeout,
1821 (unsigned long)bnad);
1822 mod_timer(&bnad->stats_timer,
1823 jiffies + msecs_to_jiffies(BNAD_STATS_TIMER_FREQ));
1824 }
1825 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1826 }
1827
1828 /*
1829 * Stops the stats timer
1830 * Called with mutex_lock(&bnad->conf_mutex) held
1831 */
1832 static void
1833 bnad_stats_timer_stop(struct bnad *bnad)
1834 {
1835 int to_del = 0;
1836 unsigned long flags;
1837
1838 spin_lock_irqsave(&bnad->bna_lock, flags);
1839 if (test_and_clear_bit(BNAD_RF_STATS_TIMER_RUNNING, &bnad->run_flags))
1840 to_del = 1;
1841 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1842 if (to_del)
1843 del_timer_sync(&bnad->stats_timer);
1844 }
1845
1846 /* Utilities */
1847
1848 static void
1849 bnad_netdev_mc_list_get(struct net_device *netdev, u8 *mc_list)
1850 {
1851 int i = 1; /* Index 0 has broadcast address */
1852 struct netdev_hw_addr *mc_addr;
1853
1854 netdev_for_each_mc_addr(mc_addr, netdev) {
1855 ether_addr_copy(&mc_list[i * ETH_ALEN], &mc_addr->addr[0]);
1856 i++;
1857 }
1858 }
1859
1860 static int
1861 bnad_napi_poll_rx(struct napi_struct *napi, int budget)
1862 {
1863 struct bnad_rx_ctrl *rx_ctrl =
1864 container_of(napi, struct bnad_rx_ctrl, napi);
1865 struct bnad *bnad = rx_ctrl->bnad;
1866 int rcvd = 0;
1867
1868 rx_ctrl->rx_poll_ctr++;
1869
1870 if (!netif_carrier_ok(bnad->netdev))
1871 goto poll_exit;
1872
1873 rcvd = bnad_cq_process(bnad, rx_ctrl->ccb, budget);
1874 if (rcvd >= budget)
1875 return rcvd;
1876
1877 poll_exit:
1878 napi_complete(napi);
1879
1880 rx_ctrl->rx_complete++;
1881
1882 if (rx_ctrl->ccb)
1883 bnad_enable_rx_irq_unsafe(rx_ctrl->ccb);
1884
1885 return rcvd;
1886 }
1887
1888 #define BNAD_NAPI_POLL_QUOTA 64
1889 static void
1890 bnad_napi_add(struct bnad *bnad, u32 rx_id)
1891 {
1892 struct bnad_rx_ctrl *rx_ctrl;
1893 int i;
1894
1895 /* Initialize & enable NAPI */
1896 for (i = 0; i < bnad->num_rxp_per_rx; i++) {
1897 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
1898 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
1899 bnad_napi_poll_rx, BNAD_NAPI_POLL_QUOTA);
1900 }
1901 }
1902
1903 static void
1904 bnad_napi_delete(struct bnad *bnad, u32 rx_id)
1905 {
1906 int i;
1907
1908 /* First disable and then clean up */
1909 for (i = 0; i < bnad->num_rxp_per_rx; i++)
1910 netif_napi_del(&bnad->rx_info[rx_id].rx_ctrl[i].napi);
1911 }
1912
1913 /* Should be held with conf_lock held */
1914 void
1915 bnad_destroy_tx(struct bnad *bnad, u32 tx_id)
1916 {
1917 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1918 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1919 unsigned long flags;
1920
1921 if (!tx_info->tx)
1922 return;
1923
1924 init_completion(&bnad->bnad_completions.tx_comp);
1925 spin_lock_irqsave(&bnad->bna_lock, flags);
1926 bna_tx_disable(tx_info->tx, BNA_HARD_CLEANUP, bnad_cb_tx_disabled);
1927 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1928 wait_for_completion(&bnad->bnad_completions.tx_comp);
1929
1930 if (tx_info->tcb[0]->intr_type == BNA_INTR_T_MSIX)
1931 bnad_tx_msix_unregister(bnad, tx_info,
1932 bnad->num_txq_per_tx);
1933
1934 spin_lock_irqsave(&bnad->bna_lock, flags);
1935 bna_tx_destroy(tx_info->tx);
1936 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1937
1938 tx_info->tx = NULL;
1939 tx_info->tx_id = 0;
1940
1941 bnad_tx_res_free(bnad, res_info);
1942 }
1943
1944 /* Should be held with conf_lock held */
1945 int
1946 bnad_setup_tx(struct bnad *bnad, u32 tx_id)
1947 {
1948 int err;
1949 struct bnad_tx_info *tx_info = &bnad->tx_info[tx_id];
1950 struct bna_res_info *res_info = &bnad->tx_res_info[tx_id].res_info[0];
1951 struct bna_intr_info *intr_info =
1952 &res_info[BNA_TX_RES_INTR_T_TXCMPL].res_u.intr_info;
1953 struct bna_tx_config *tx_config = &bnad->tx_config[tx_id];
1954 static const struct bna_tx_event_cbfn tx_cbfn = {
1955 .tcb_setup_cbfn = bnad_cb_tcb_setup,
1956 .tcb_destroy_cbfn = bnad_cb_tcb_destroy,
1957 .tx_stall_cbfn = bnad_cb_tx_stall,
1958 .tx_resume_cbfn = bnad_cb_tx_resume,
1959 .tx_cleanup_cbfn = bnad_cb_tx_cleanup,
1960 };
1961
1962 struct bna_tx *tx;
1963 unsigned long flags;
1964
1965 tx_info->tx_id = tx_id;
1966
1967 /* Initialize the Tx object configuration */
1968 tx_config->num_txq = bnad->num_txq_per_tx;
1969 tx_config->txq_depth = bnad->txq_depth;
1970 tx_config->tx_type = BNA_TX_T_REGULAR;
1971 tx_config->coalescing_timeo = bnad->tx_coalescing_timeo;
1972
1973 /* Get BNA's resource requirement for one tx object */
1974 spin_lock_irqsave(&bnad->bna_lock, flags);
1975 bna_tx_res_req(bnad->num_txq_per_tx,
1976 bnad->txq_depth, res_info);
1977 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1978
1979 /* Fill Unmap Q memory requirements */
1980 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_TX_RES_MEM_T_UNMAPQ],
1981 bnad->num_txq_per_tx, (sizeof(struct bnad_tx_unmap) *
1982 bnad->txq_depth));
1983
1984 /* Allocate resources */
1985 err = bnad_tx_res_alloc(bnad, res_info, tx_id);
1986 if (err)
1987 return err;
1988
1989 /* Ask BNA to create one Tx object, supplying required resources */
1990 spin_lock_irqsave(&bnad->bna_lock, flags);
1991 tx = bna_tx_create(&bnad->bna, bnad, tx_config, &tx_cbfn, res_info,
1992 tx_info);
1993 spin_unlock_irqrestore(&bnad->bna_lock, flags);
1994 if (!tx) {
1995 err = -ENOMEM;
1996 goto err_return;
1997 }
1998 tx_info->tx = tx;
1999
2000 INIT_DELAYED_WORK(&tx_info->tx_cleanup_work,
2001 (work_func_t)bnad_tx_cleanup);
2002
2003 /* Register ISR for the Tx object */
2004 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2005 err = bnad_tx_msix_register(bnad, tx_info,
2006 tx_id, bnad->num_txq_per_tx);
2007 if (err)
2008 goto cleanup_tx;
2009 }
2010
2011 spin_lock_irqsave(&bnad->bna_lock, flags);
2012 bna_tx_enable(tx);
2013 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2014
2015 return 0;
2016
2017 cleanup_tx:
2018 spin_lock_irqsave(&bnad->bna_lock, flags);
2019 bna_tx_destroy(tx_info->tx);
2020 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2021 tx_info->tx = NULL;
2022 tx_info->tx_id = 0;
2023 err_return:
2024 bnad_tx_res_free(bnad, res_info);
2025 return err;
2026 }
2027
2028 /* Setup the rx config for bna_rx_create */
2029 /* bnad decides the configuration */
2030 static void
2031 bnad_init_rx_config(struct bnad *bnad, struct bna_rx_config *rx_config)
2032 {
2033 memset(rx_config, 0, sizeof(*rx_config));
2034 rx_config->rx_type = BNA_RX_T_REGULAR;
2035 rx_config->num_paths = bnad->num_rxp_per_rx;
2036 rx_config->coalescing_timeo = bnad->rx_coalescing_timeo;
2037
2038 if (bnad->num_rxp_per_rx > 1) {
2039 rx_config->rss_status = BNA_STATUS_T_ENABLED;
2040 rx_config->rss_config.hash_type =
2041 (BFI_ENET_RSS_IPV6 |
2042 BFI_ENET_RSS_IPV6_TCP |
2043 BFI_ENET_RSS_IPV4 |
2044 BFI_ENET_RSS_IPV4_TCP);
2045 rx_config->rss_config.hash_mask =
2046 bnad->num_rxp_per_rx - 1;
2047 netdev_rss_key_fill(rx_config->rss_config.toeplitz_hash_key,
2048 sizeof(rx_config->rss_config.toeplitz_hash_key));
2049 } else {
2050 rx_config->rss_status = BNA_STATUS_T_DISABLED;
2051 memset(&rx_config->rss_config, 0,
2052 sizeof(rx_config->rss_config));
2053 }
2054
2055 rx_config->frame_size = BNAD_FRAME_SIZE(bnad->netdev->mtu);
2056 rx_config->q0_multi_buf = BNA_STATUS_T_DISABLED;
2057
2058 /* BNA_RXP_SINGLE - one data-buffer queue
2059 * BNA_RXP_SLR - one small-buffer and one large-buffer queues
2060 * BNA_RXP_HDS - one header-buffer and one data-buffer queues
2061 */
2062 /* TODO: configurable param for queue type */
2063 rx_config->rxp_type = BNA_RXP_SLR;
2064
2065 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
2066 rx_config->frame_size > 4096) {
2067 /* though size_routing_enable is set in SLR,
2068 * small packets may get routed to same rxq.
2069 * set buf_size to 2048 instead of PAGE_SIZE.
2070 */
2071 rx_config->q0_buf_size = 2048;
2072 /* this should be in multiples of 2 */
2073 rx_config->q0_num_vecs = 4;
2074 rx_config->q0_depth = bnad->rxq_depth * rx_config->q0_num_vecs;
2075 rx_config->q0_multi_buf = BNA_STATUS_T_ENABLED;
2076 } else {
2077 rx_config->q0_buf_size = rx_config->frame_size;
2078 rx_config->q0_num_vecs = 1;
2079 rx_config->q0_depth = bnad->rxq_depth;
2080 }
2081
2082 /* initialize for q1 for BNA_RXP_SLR/BNA_RXP_HDS */
2083 if (rx_config->rxp_type == BNA_RXP_SLR) {
2084 rx_config->q1_depth = bnad->rxq_depth;
2085 rx_config->q1_buf_size = BFI_SMALL_RXBUF_SIZE;
2086 }
2087
2088 rx_config->vlan_strip_status =
2089 (bnad->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) ?
2090 BNA_STATUS_T_ENABLED : BNA_STATUS_T_DISABLED;
2091 }
2092
2093 static void
2094 bnad_rx_ctrl_init(struct bnad *bnad, u32 rx_id)
2095 {
2096 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2097 int i;
2098
2099 for (i = 0; i < bnad->num_rxp_per_rx; i++)
2100 rx_info->rx_ctrl[i].bnad = bnad;
2101 }
2102
2103 /* Called with mutex_lock(&bnad->conf_mutex) held */
2104 static u32
2105 bnad_reinit_rx(struct bnad *bnad)
2106 {
2107 struct net_device *netdev = bnad->netdev;
2108 u32 err = 0, current_err = 0;
2109 u32 rx_id = 0, count = 0;
2110 unsigned long flags;
2111
2112 /* destroy and create new rx objects */
2113 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2114 if (!bnad->rx_info[rx_id].rx)
2115 continue;
2116 bnad_destroy_rx(bnad, rx_id);
2117 }
2118
2119 spin_lock_irqsave(&bnad->bna_lock, flags);
2120 bna_enet_mtu_set(&bnad->bna.enet,
2121 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2122 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2123
2124 for (rx_id = 0; rx_id < bnad->num_rx; rx_id++) {
2125 count++;
2126 current_err = bnad_setup_rx(bnad, rx_id);
2127 if (current_err && !err) {
2128 err = current_err;
2129 netdev_err(netdev, "RXQ:%u setup failed\n", rx_id);
2130 }
2131 }
2132
2133 /* restore rx configuration */
2134 if (bnad->rx_info[0].rx && !err) {
2135 bnad_restore_vlans(bnad, 0);
2136 bnad_enable_default_bcast(bnad);
2137 spin_lock_irqsave(&bnad->bna_lock, flags);
2138 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2139 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2140 bnad_set_rx_mode(netdev);
2141 }
2142
2143 return count;
2144 }
2145
2146 /* Called with bnad_conf_lock() held */
2147 void
2148 bnad_destroy_rx(struct bnad *bnad, u32 rx_id)
2149 {
2150 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2151 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2152 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2153 unsigned long flags;
2154 int to_del = 0;
2155
2156 if (!rx_info->rx)
2157 return;
2158
2159 if (0 == rx_id) {
2160 spin_lock_irqsave(&bnad->bna_lock, flags);
2161 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED &&
2162 test_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags)) {
2163 clear_bit(BNAD_RF_DIM_TIMER_RUNNING, &bnad->run_flags);
2164 to_del = 1;
2165 }
2166 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2167 if (to_del)
2168 del_timer_sync(&bnad->dim_timer);
2169 }
2170
2171 init_completion(&bnad->bnad_completions.rx_comp);
2172 spin_lock_irqsave(&bnad->bna_lock, flags);
2173 bna_rx_disable(rx_info->rx, BNA_HARD_CLEANUP, bnad_cb_rx_disabled);
2174 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2175 wait_for_completion(&bnad->bnad_completions.rx_comp);
2176
2177 if (rx_info->rx_ctrl[0].ccb->intr_type == BNA_INTR_T_MSIX)
2178 bnad_rx_msix_unregister(bnad, rx_info, rx_config->num_paths);
2179
2180 bnad_napi_delete(bnad, rx_id);
2181
2182 spin_lock_irqsave(&bnad->bna_lock, flags);
2183 bna_rx_destroy(rx_info->rx);
2184
2185 rx_info->rx = NULL;
2186 rx_info->rx_id = 0;
2187 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2188
2189 bnad_rx_res_free(bnad, res_info);
2190 }
2191
2192 /* Called with mutex_lock(&bnad->conf_mutex) held */
2193 int
2194 bnad_setup_rx(struct bnad *bnad, u32 rx_id)
2195 {
2196 int err;
2197 struct bnad_rx_info *rx_info = &bnad->rx_info[rx_id];
2198 struct bna_res_info *res_info = &bnad->rx_res_info[rx_id].res_info[0];
2199 struct bna_intr_info *intr_info =
2200 &res_info[BNA_RX_RES_T_INTR].res_u.intr_info;
2201 struct bna_rx_config *rx_config = &bnad->rx_config[rx_id];
2202 static const struct bna_rx_event_cbfn rx_cbfn = {
2203 .rcb_setup_cbfn = NULL,
2204 .rcb_destroy_cbfn = NULL,
2205 .ccb_setup_cbfn = bnad_cb_ccb_setup,
2206 .ccb_destroy_cbfn = bnad_cb_ccb_destroy,
2207 .rx_stall_cbfn = bnad_cb_rx_stall,
2208 .rx_cleanup_cbfn = bnad_cb_rx_cleanup,
2209 .rx_post_cbfn = bnad_cb_rx_post,
2210 };
2211 struct bna_rx *rx;
2212 unsigned long flags;
2213
2214 rx_info->rx_id = rx_id;
2215
2216 /* Initialize the Rx object configuration */
2217 bnad_init_rx_config(bnad, rx_config);
2218
2219 /* Get BNA's resource requirement for one Rx object */
2220 spin_lock_irqsave(&bnad->bna_lock, flags);
2221 bna_rx_res_req(rx_config, res_info);
2222 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2223
2224 /* Fill Unmap Q memory requirements */
2225 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPDQ],
2226 rx_config->num_paths,
2227 (rx_config->q0_depth *
2228 sizeof(struct bnad_rx_unmap)) +
2229 sizeof(struct bnad_rx_unmap_q));
2230
2231 if (rx_config->rxp_type != BNA_RXP_SINGLE) {
2232 BNAD_FILL_UNMAPQ_MEM_REQ(&res_info[BNA_RX_RES_MEM_T_UNMAPHQ],
2233 rx_config->num_paths,
2234 (rx_config->q1_depth *
2235 sizeof(struct bnad_rx_unmap) +
2236 sizeof(struct bnad_rx_unmap_q)));
2237 }
2238 /* Allocate resource */
2239 err = bnad_rx_res_alloc(bnad, res_info, rx_id);
2240 if (err)
2241 return err;
2242
2243 bnad_rx_ctrl_init(bnad, rx_id);
2244
2245 /* Ask BNA to create one Rx object, supplying required resources */
2246 spin_lock_irqsave(&bnad->bna_lock, flags);
2247 rx = bna_rx_create(&bnad->bna, bnad, rx_config, &rx_cbfn, res_info,
2248 rx_info);
2249 if (!rx) {
2250 err = -ENOMEM;
2251 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2252 goto err_return;
2253 }
2254 rx_info->rx = rx;
2255 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2256
2257 INIT_WORK(&rx_info->rx_cleanup_work,
2258 (work_func_t)(bnad_rx_cleanup));
2259
2260 /*
2261 * Init NAPI, so that state is set to NAPI_STATE_SCHED,
2262 * so that IRQ handler cannot schedule NAPI at this point.
2263 */
2264 bnad_napi_add(bnad, rx_id);
2265
2266 /* Register ISR for the Rx object */
2267 if (intr_info->intr_type == BNA_INTR_T_MSIX) {
2268 err = bnad_rx_msix_register(bnad, rx_info, rx_id,
2269 rx_config->num_paths);
2270 if (err)
2271 goto err_return;
2272 }
2273
2274 spin_lock_irqsave(&bnad->bna_lock, flags);
2275 if (0 == rx_id) {
2276 /* Set up Dynamic Interrupt Moderation Vector */
2277 if (bnad->cfg_flags & BNAD_CF_DIM_ENABLED)
2278 bna_rx_dim_reconfig(&bnad->bna, bna_napi_dim_vector);
2279
2280 /* Enable VLAN filtering only on the default Rx */
2281 bna_rx_vlanfilter_enable(rx);
2282
2283 /* Start the DIM timer */
2284 bnad_dim_timer_start(bnad);
2285 }
2286
2287 bna_rx_enable(rx);
2288 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2289
2290 return 0;
2291
2292 err_return:
2293 bnad_destroy_rx(bnad, rx_id);
2294 return err;
2295 }
2296
2297 /* Called with conf_lock & bnad->bna_lock held */
2298 void
2299 bnad_tx_coalescing_timeo_set(struct bnad *bnad)
2300 {
2301 struct bnad_tx_info *tx_info;
2302
2303 tx_info = &bnad->tx_info[0];
2304 if (!tx_info->tx)
2305 return;
2306
2307 bna_tx_coalescing_timeo_set(tx_info->tx, bnad->tx_coalescing_timeo);
2308 }
2309
2310 /* Called with conf_lock & bnad->bna_lock held */
2311 void
2312 bnad_rx_coalescing_timeo_set(struct bnad *bnad)
2313 {
2314 struct bnad_rx_info *rx_info;
2315 int i;
2316
2317 for (i = 0; i < bnad->num_rx; i++) {
2318 rx_info = &bnad->rx_info[i];
2319 if (!rx_info->rx)
2320 continue;
2321 bna_rx_coalescing_timeo_set(rx_info->rx,
2322 bnad->rx_coalescing_timeo);
2323 }
2324 }
2325
2326 /*
2327 * Called with bnad->bna_lock held
2328 */
2329 int
2330 bnad_mac_addr_set_locked(struct bnad *bnad, const u8 *mac_addr)
2331 {
2332 int ret;
2333
2334 if (!is_valid_ether_addr(mac_addr))
2335 return -EADDRNOTAVAIL;
2336
2337 /* If datapath is down, pretend everything went through */
2338 if (!bnad->rx_info[0].rx)
2339 return 0;
2340
2341 ret = bna_rx_ucast_set(bnad->rx_info[0].rx, mac_addr);
2342 if (ret != BNA_CB_SUCCESS)
2343 return -EADDRNOTAVAIL;
2344
2345 return 0;
2346 }
2347
2348 /* Should be called with conf_lock held */
2349 int
2350 bnad_enable_default_bcast(struct bnad *bnad)
2351 {
2352 struct bnad_rx_info *rx_info = &bnad->rx_info[0];
2353 int ret;
2354 unsigned long flags;
2355
2356 init_completion(&bnad->bnad_completions.mcast_comp);
2357
2358 spin_lock_irqsave(&bnad->bna_lock, flags);
2359 ret = bna_rx_mcast_add(rx_info->rx, bnad_bcast_addr,
2360 bnad_cb_rx_mcast_add);
2361 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2362
2363 if (ret == BNA_CB_SUCCESS)
2364 wait_for_completion(&bnad->bnad_completions.mcast_comp);
2365 else
2366 return -ENODEV;
2367
2368 if (bnad->bnad_completions.mcast_comp_status != BNA_CB_SUCCESS)
2369 return -ENODEV;
2370
2371 return 0;
2372 }
2373
2374 /* Called with mutex_lock(&bnad->conf_mutex) held */
2375 void
2376 bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
2377 {
2378 u16 vid;
2379 unsigned long flags;
2380
2381 for_each_set_bit(vid, bnad->active_vlans, VLAN_N_VID) {
2382 spin_lock_irqsave(&bnad->bna_lock, flags);
2383 bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vid);
2384 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2385 }
2386 }
2387
2388 /* Statistics utilities */
2389 void
2390 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2391 {
2392 int i, j;
2393
2394 for (i = 0; i < bnad->num_rx; i++) {
2395 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
2396 if (bnad->rx_info[i].rx_ctrl[j].ccb) {
2397 stats->rx_packets += bnad->rx_info[i].
2398 rx_ctrl[j].ccb->rcb[0]->rxq->rx_packets;
2399 stats->rx_bytes += bnad->rx_info[i].
2400 rx_ctrl[j].ccb->rcb[0]->rxq->rx_bytes;
2401 if (bnad->rx_info[i].rx_ctrl[j].ccb->rcb[1] &&
2402 bnad->rx_info[i].rx_ctrl[j].ccb->
2403 rcb[1]->rxq) {
2404 stats->rx_packets +=
2405 bnad->rx_info[i].rx_ctrl[j].
2406 ccb->rcb[1]->rxq->rx_packets;
2407 stats->rx_bytes +=
2408 bnad->rx_info[i].rx_ctrl[j].
2409 ccb->rcb[1]->rxq->rx_bytes;
2410 }
2411 }
2412 }
2413 }
2414 for (i = 0; i < bnad->num_tx; i++) {
2415 for (j = 0; j < bnad->num_txq_per_tx; j++) {
2416 if (bnad->tx_info[i].tcb[j]) {
2417 stats->tx_packets +=
2418 bnad->tx_info[i].tcb[j]->txq->tx_packets;
2419 stats->tx_bytes +=
2420 bnad->tx_info[i].tcb[j]->txq->tx_bytes;
2421 }
2422 }
2423 }
2424 }
2425
2426 /*
2427 * Must be called with the bna_lock held.
2428 */
2429 void
2430 bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
2431 {
2432 struct bfi_enet_stats_mac *mac_stats;
2433 u32 bmap;
2434 int i;
2435
2436 mac_stats = &bnad->stats.bna_stats->hw_stats.mac_stats;
2437 stats->rx_errors =
2438 mac_stats->rx_fcs_error + mac_stats->rx_alignment_error +
2439 mac_stats->rx_frame_length_error + mac_stats->rx_code_error +
2440 mac_stats->rx_undersize;
2441 stats->tx_errors = mac_stats->tx_fcs_error +
2442 mac_stats->tx_undersize;
2443 stats->rx_dropped = mac_stats->rx_drop;
2444 stats->tx_dropped = mac_stats->tx_drop;
2445 stats->multicast = mac_stats->rx_multicast;
2446 stats->collisions = mac_stats->tx_total_collision;
2447
2448 stats->rx_length_errors = mac_stats->rx_frame_length_error;
2449
2450 /* receive ring buffer overflow ?? */
2451
2452 stats->rx_crc_errors = mac_stats->rx_fcs_error;
2453 stats->rx_frame_errors = mac_stats->rx_alignment_error;
2454 /* recv'r fifo overrun */
2455 bmap = bna_rx_rid_mask(&bnad->bna);
2456 for (i = 0; bmap; i++) {
2457 if (bmap & 1) {
2458 stats->rx_fifo_errors +=
2459 bnad->stats.bna_stats->
2460 hw_stats.rxf_stats[i].frame_drops;
2461 break;
2462 }
2463 bmap >>= 1;
2464 }
2465 }
2466
2467 static void
2468 bnad_mbox_irq_sync(struct bnad *bnad)
2469 {
2470 u32 irq;
2471 unsigned long flags;
2472
2473 spin_lock_irqsave(&bnad->bna_lock, flags);
2474 if (bnad->cfg_flags & BNAD_CF_MSIX)
2475 irq = bnad->msix_table[BNAD_MAILBOX_MSIX_INDEX].vector;
2476 else
2477 irq = bnad->pcidev->irq;
2478 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2479
2480 synchronize_irq(irq);
2481 }
2482
2483 /* Utility used by bnad_start_xmit, for doing TSO */
2484 static int
2485 bnad_tso_prepare(struct bnad *bnad, struct sk_buff *skb)
2486 {
2487 int err;
2488
2489 err = skb_cow_head(skb, 0);
2490 if (err < 0) {
2491 BNAD_UPDATE_CTR(bnad, tso_err);
2492 return err;
2493 }
2494
2495 /*
2496 * For TSO, the TCP checksum field is seeded with pseudo-header sum
2497 * excluding the length field.
2498 */
2499 if (vlan_get_protocol(skb) == htons(ETH_P_IP)) {
2500 struct iphdr *iph = ip_hdr(skb);
2501
2502 /* Do we really need these? */
2503 iph->tot_len = 0;
2504 iph->check = 0;
2505
2506 tcp_hdr(skb)->check =
2507 ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
2508 IPPROTO_TCP, 0);
2509 BNAD_UPDATE_CTR(bnad, tso4);
2510 } else {
2511 struct ipv6hdr *ipv6h = ipv6_hdr(skb);
2512
2513 ipv6h->payload_len = 0;
2514 tcp_hdr(skb)->check =
2515 ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, 0,
2516 IPPROTO_TCP, 0);
2517 BNAD_UPDATE_CTR(bnad, tso6);
2518 }
2519
2520 return 0;
2521 }
2522
2523 /*
2524 * Initialize Q numbers depending on Rx Paths
2525 * Called with bnad->bna_lock held, because of cfg_flags
2526 * access.
2527 */
2528 static void
2529 bnad_q_num_init(struct bnad *bnad)
2530 {
2531 int rxps;
2532
2533 rxps = min((uint)num_online_cpus(),
2534 (uint)(BNAD_MAX_RX * BNAD_MAX_RXP_PER_RX));
2535
2536 if (!(bnad->cfg_flags & BNAD_CF_MSIX))
2537 rxps = 1; /* INTx */
2538
2539 bnad->num_rx = 1;
2540 bnad->num_tx = 1;
2541 bnad->num_rxp_per_rx = rxps;
2542 bnad->num_txq_per_tx = BNAD_TXQ_NUM;
2543 }
2544
2545 /*
2546 * Adjusts the Q numbers, given a number of msix vectors
2547 * Give preference to RSS as opposed to Tx priority Queues,
2548 * in such a case, just use 1 Tx Q
2549 * Called with bnad->bna_lock held b'cos of cfg_flags access
2550 */
2551 static void
2552 bnad_q_num_adjust(struct bnad *bnad, int msix_vectors, int temp)
2553 {
2554 bnad->num_txq_per_tx = 1;
2555 if ((msix_vectors >= (bnad->num_tx * bnad->num_txq_per_tx) +
2556 bnad_rxqs_per_cq + BNAD_MAILBOX_MSIX_VECTORS) &&
2557 (bnad->cfg_flags & BNAD_CF_MSIX)) {
2558 bnad->num_rxp_per_rx = msix_vectors -
2559 (bnad->num_tx * bnad->num_txq_per_tx) -
2560 BNAD_MAILBOX_MSIX_VECTORS;
2561 } else
2562 bnad->num_rxp_per_rx = 1;
2563 }
2564
2565 /* Enable / disable ioceth */
2566 static int
2567 bnad_ioceth_disable(struct bnad *bnad)
2568 {
2569 unsigned long flags;
2570 int err = 0;
2571
2572 spin_lock_irqsave(&bnad->bna_lock, flags);
2573 init_completion(&bnad->bnad_completions.ioc_comp);
2574 bna_ioceth_disable(&bnad->bna.ioceth, BNA_HARD_CLEANUP);
2575 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2576
2577 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2578 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2579
2580 err = bnad->bnad_completions.ioc_comp_status;
2581 return err;
2582 }
2583
2584 static int
2585 bnad_ioceth_enable(struct bnad *bnad)
2586 {
2587 int err = 0;
2588 unsigned long flags;
2589
2590 spin_lock_irqsave(&bnad->bna_lock, flags);
2591 init_completion(&bnad->bnad_completions.ioc_comp);
2592 bnad->bnad_completions.ioc_comp_status = BNA_CB_WAITING;
2593 bna_ioceth_enable(&bnad->bna.ioceth);
2594 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2595
2596 wait_for_completion_timeout(&bnad->bnad_completions.ioc_comp,
2597 msecs_to_jiffies(BNAD_IOCETH_TIMEOUT));
2598
2599 err = bnad->bnad_completions.ioc_comp_status;
2600
2601 return err;
2602 }
2603
2604 /* Free BNA resources */
2605 static void
2606 bnad_res_free(struct bnad *bnad, struct bna_res_info *res_info,
2607 u32 res_val_max)
2608 {
2609 int i;
2610
2611 for (i = 0; i < res_val_max; i++)
2612 bnad_mem_free(bnad, &res_info[i].res_u.mem_info);
2613 }
2614
2615 /* Allocates memory and interrupt resources for BNA */
2616 static int
2617 bnad_res_alloc(struct bnad *bnad, struct bna_res_info *res_info,
2618 u32 res_val_max)
2619 {
2620 int i, err;
2621
2622 for (i = 0; i < res_val_max; i++) {
2623 err = bnad_mem_alloc(bnad, &res_info[i].res_u.mem_info);
2624 if (err)
2625 goto err_return;
2626 }
2627 return 0;
2628
2629 err_return:
2630 bnad_res_free(bnad, res_info, res_val_max);
2631 return err;
2632 }
2633
2634 /* Interrupt enable / disable */
2635 static void
2636 bnad_enable_msix(struct bnad *bnad)
2637 {
2638 int i, ret;
2639 unsigned long flags;
2640
2641 spin_lock_irqsave(&bnad->bna_lock, flags);
2642 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
2643 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2644 return;
2645 }
2646 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2647
2648 if (bnad->msix_table)
2649 return;
2650
2651 bnad->msix_table =
2652 kcalloc(bnad->msix_num, sizeof(struct msix_entry), GFP_KERNEL);
2653
2654 if (!bnad->msix_table)
2655 goto intx_mode;
2656
2657 for (i = 0; i < bnad->msix_num; i++)
2658 bnad->msix_table[i].entry = i;
2659
2660 ret = pci_enable_msix_range(bnad->pcidev, bnad->msix_table,
2661 1, bnad->msix_num);
2662 if (ret < 0) {
2663 goto intx_mode;
2664 } else if (ret < bnad->msix_num) {
2665 dev_warn(&bnad->pcidev->dev,
2666 "%d MSI-X vectors allocated < %d requested\n",
2667 ret, bnad->msix_num);
2668
2669 spin_lock_irqsave(&bnad->bna_lock, flags);
2670 /* ret = #of vectors that we got */
2671 bnad_q_num_adjust(bnad, (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2,
2672 (ret - BNAD_MAILBOX_MSIX_VECTORS) / 2);
2673 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2674
2675 bnad->msix_num = BNAD_NUM_TXQ + BNAD_NUM_RXP +
2676 BNAD_MAILBOX_MSIX_VECTORS;
2677
2678 if (bnad->msix_num > ret) {
2679 pci_disable_msix(bnad->pcidev);
2680 goto intx_mode;
2681 }
2682 }
2683
2684 pci_intx(bnad->pcidev, 0);
2685
2686 return;
2687
2688 intx_mode:
2689 dev_warn(&bnad->pcidev->dev,
2690 "MSI-X enable failed - operating in INTx mode\n");
2691
2692 kfree(bnad->msix_table);
2693 bnad->msix_table = NULL;
2694 bnad->msix_num = 0;
2695 spin_lock_irqsave(&bnad->bna_lock, flags);
2696 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2697 bnad_q_num_init(bnad);
2698 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2699 }
2700
2701 static void
2702 bnad_disable_msix(struct bnad *bnad)
2703 {
2704 u32 cfg_flags;
2705 unsigned long flags;
2706
2707 spin_lock_irqsave(&bnad->bna_lock, flags);
2708 cfg_flags = bnad->cfg_flags;
2709 if (bnad->cfg_flags & BNAD_CF_MSIX)
2710 bnad->cfg_flags &= ~BNAD_CF_MSIX;
2711 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2712
2713 if (cfg_flags & BNAD_CF_MSIX) {
2714 pci_disable_msix(bnad->pcidev);
2715 kfree(bnad->msix_table);
2716 bnad->msix_table = NULL;
2717 }
2718 }
2719
2720 /* Netdev entry points */
2721 static int
2722 bnad_open(struct net_device *netdev)
2723 {
2724 int err;
2725 struct bnad *bnad = netdev_priv(netdev);
2726 struct bna_pause_config pause_config;
2727 unsigned long flags;
2728
2729 mutex_lock(&bnad->conf_mutex);
2730
2731 /* Tx */
2732 err = bnad_setup_tx(bnad, 0);
2733 if (err)
2734 goto err_return;
2735
2736 /* Rx */
2737 err = bnad_setup_rx(bnad, 0);
2738 if (err)
2739 goto cleanup_tx;
2740
2741 /* Port */
2742 pause_config.tx_pause = 0;
2743 pause_config.rx_pause = 0;
2744
2745 spin_lock_irqsave(&bnad->bna_lock, flags);
2746 bna_enet_mtu_set(&bnad->bna.enet,
2747 BNAD_FRAME_SIZE(bnad->netdev->mtu), NULL);
2748 bna_enet_pause_config(&bnad->bna.enet, &pause_config);
2749 bna_enet_enable(&bnad->bna.enet);
2750 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2751
2752 /* Enable broadcast */
2753 bnad_enable_default_bcast(bnad);
2754
2755 /* Restore VLANs, if any */
2756 bnad_restore_vlans(bnad, 0);
2757
2758 /* Set the UCAST address */
2759 spin_lock_irqsave(&bnad->bna_lock, flags);
2760 bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
2761 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2762
2763 /* Start the stats timer */
2764 bnad_stats_timer_start(bnad);
2765
2766 mutex_unlock(&bnad->conf_mutex);
2767
2768 return 0;
2769
2770 cleanup_tx:
2771 bnad_destroy_tx(bnad, 0);
2772
2773 err_return:
2774 mutex_unlock(&bnad->conf_mutex);
2775 return err;
2776 }
2777
2778 static int
2779 bnad_stop(struct net_device *netdev)
2780 {
2781 struct bnad *bnad = netdev_priv(netdev);
2782 unsigned long flags;
2783
2784 mutex_lock(&bnad->conf_mutex);
2785
2786 /* Stop the stats timer */
2787 bnad_stats_timer_stop(bnad);
2788
2789 init_completion(&bnad->bnad_completions.enet_comp);
2790
2791 spin_lock_irqsave(&bnad->bna_lock, flags);
2792 bna_enet_disable(&bnad->bna.enet, BNA_HARD_CLEANUP,
2793 bnad_cb_enet_disabled);
2794 spin_unlock_irqrestore(&bnad->bna_lock, flags);
2795
2796 wait_for_completion(&bnad->bnad_completions.enet_comp);
2797
2798 bnad_destroy_tx(bnad, 0);
2799 bnad_destroy_rx(bnad, 0);
2800
2801 /* Synchronize mailbox IRQ */
2802 bnad_mbox_irq_sync(bnad);
2803
2804 mutex_unlock(&bnad->conf_mutex);
2805
2806 return 0;
2807 }
2808
2809 /* TX */
2810 /* Returns 0 for success */
2811 static int
2812 bnad_txq_wi_prepare(struct bnad *bnad, struct bna_tcb *tcb,
2813 struct sk_buff *skb, struct bna_txq_entry *txqent)
2814 {
2815 u16 flags = 0;
2816 u32 gso_size;
2817 u16 vlan_tag = 0;
2818
2819 if (skb_vlan_tag_present(skb)) {
2820 vlan_tag = (u16)skb_vlan_tag_get(skb);
2821 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2822 }
2823 if (test_bit(BNAD_RF_CEE_RUNNING, &bnad->run_flags)) {
2824 vlan_tag = ((tcb->priority & 0x7) << VLAN_PRIO_SHIFT)
2825 | (vlan_tag & 0x1fff);
2826 flags |= (BNA_TXQ_WI_CF_INS_PRIO | BNA_TXQ_WI_CF_INS_VLAN);
2827 }
2828 txqent->hdr.wi.vlan_tag = htons(vlan_tag);
2829
2830 if (skb_is_gso(skb)) {
2831 gso_size = skb_shinfo(skb)->gso_size;
2832 if (unlikely(gso_size > bnad->netdev->mtu)) {
2833 BNAD_UPDATE_CTR(bnad, tx_skb_mss_too_long);
2834 return -EINVAL;
2835 }
2836 if (unlikely((gso_size + skb_transport_offset(skb) +
2837 tcp_hdrlen(skb)) >= skb->len)) {
2838 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND);
2839 txqent->hdr.wi.lso_mss = 0;
2840 BNAD_UPDATE_CTR(bnad, tx_skb_tso_too_short);
2841 } else {
2842 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND_LSO);
2843 txqent->hdr.wi.lso_mss = htons(gso_size);
2844 }
2845
2846 if (bnad_tso_prepare(bnad, skb)) {
2847 BNAD_UPDATE_CTR(bnad, tx_skb_tso_prepare);
2848 return -EINVAL;
2849 }
2850
2851 flags |= (BNA_TXQ_WI_CF_IP_CKSUM | BNA_TXQ_WI_CF_TCP_CKSUM);
2852 txqent->hdr.wi.l4_hdr_size_n_offset =
2853 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET(
2854 tcp_hdrlen(skb) >> 2, skb_transport_offset(skb)));
2855 } else {
2856 txqent->hdr.wi.opcode = htons(BNA_TXQ_WI_SEND);
2857 txqent->hdr.wi.lso_mss = 0;
2858
2859 if (unlikely(skb->len > (bnad->netdev->mtu + VLAN_ETH_HLEN))) {
2860 BNAD_UPDATE_CTR(bnad, tx_skb_non_tso_too_long);
2861 return -EINVAL;
2862 }
2863
2864 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2865 __be16 net_proto = vlan_get_protocol(skb);
2866 u8 proto = 0;
2867
2868 if (net_proto == htons(ETH_P_IP))
2869 proto = ip_hdr(skb)->protocol;
2870 #ifdef NETIF_F_IPV6_CSUM
2871 else if (net_proto == htons(ETH_P_IPV6)) {
2872 /* nexthdr may not be TCP immediately. */
2873 proto = ipv6_hdr(skb)->nexthdr;
2874 }
2875 #endif
2876 if (proto == IPPROTO_TCP) {
2877 flags |= BNA_TXQ_WI_CF_TCP_CKSUM;
2878 txqent->hdr.wi.l4_hdr_size_n_offset =
2879 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2880 (0, skb_transport_offset(skb)));
2881
2882 BNAD_UPDATE_CTR(bnad, tcpcsum_offload);
2883
2884 if (unlikely(skb_headlen(skb) <
2885 skb_transport_offset(skb) +
2886 tcp_hdrlen(skb))) {
2887 BNAD_UPDATE_CTR(bnad, tx_skb_tcp_hdr);
2888 return -EINVAL;
2889 }
2890 } else if (proto == IPPROTO_UDP) {
2891 flags |= BNA_TXQ_WI_CF_UDP_CKSUM;
2892 txqent->hdr.wi.l4_hdr_size_n_offset =
2893 htons(BNA_TXQ_WI_L4_HDR_N_OFFSET
2894 (0, skb_transport_offset(skb)));
2895
2896 BNAD_UPDATE_CTR(bnad, udpcsum_offload);
2897 if (unlikely(skb_headlen(skb) <
2898 skb_transport_offset(skb) +
2899 sizeof(struct udphdr))) {
2900 BNAD_UPDATE_CTR(bnad, tx_skb_udp_hdr);
2901 return -EINVAL;
2902 }
2903 } else {
2904
2905 BNAD_UPDATE_CTR(bnad, tx_skb_csum_err);
2906 return -EINVAL;
2907 }
2908 } else
2909 txqent->hdr.wi.l4_hdr_size_n_offset = 0;
2910 }
2911
2912 txqent->hdr.wi.flags = htons(flags);
2913 txqent->hdr.wi.frame_length = htonl(skb->len);
2914
2915 return 0;
2916 }
2917
2918 /*
2919 * bnad_start_xmit : Netdev entry point for Transmit
2920 * Called under lock held by net_device
2921 */
2922 static netdev_tx_t
2923 bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2924 {
2925 struct bnad *bnad = netdev_priv(netdev);
2926 u32 txq_id = 0;
2927 struct bna_tcb *tcb = NULL;
2928 struct bnad_tx_unmap *unmap_q, *unmap, *head_unmap;
2929 u32 prod, q_depth, vect_id;
2930 u32 wis, vectors, len;
2931 int i;
2932 dma_addr_t dma_addr;
2933 struct bna_txq_entry *txqent;
2934
2935 len = skb_headlen(skb);
2936
2937 /* Sanity checks for the skb */
2938
2939 if (unlikely(skb->len <= ETH_HLEN)) {
2940 dev_kfree_skb_any(skb);
2941 BNAD_UPDATE_CTR(bnad, tx_skb_too_short);
2942 return NETDEV_TX_OK;
2943 }
2944 if (unlikely(len > BFI_TX_MAX_DATA_PER_VECTOR)) {
2945 dev_kfree_skb_any(skb);
2946 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2947 return NETDEV_TX_OK;
2948 }
2949 if (unlikely(len == 0)) {
2950 dev_kfree_skb_any(skb);
2951 BNAD_UPDATE_CTR(bnad, tx_skb_headlen_zero);
2952 return NETDEV_TX_OK;
2953 }
2954
2955 tcb = bnad->tx_info[0].tcb[txq_id];
2956
2957 /*
2958 * Takes care of the Tx that is scheduled between clearing the flag
2959 * and the netif_tx_stop_all_queues() call.
2960 */
2961 if (unlikely(!tcb || !test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
2962 dev_kfree_skb_any(skb);
2963 BNAD_UPDATE_CTR(bnad, tx_skb_stopping);
2964 return NETDEV_TX_OK;
2965 }
2966
2967 q_depth = tcb->q_depth;
2968 prod = tcb->producer_index;
2969 unmap_q = tcb->unmap_q;
2970
2971 vectors = 1 + skb_shinfo(skb)->nr_frags;
2972 wis = BNA_TXQ_WI_NEEDED(vectors); /* 4 vectors per work item */
2973
2974 if (unlikely(vectors > BFI_TX_MAX_VECTORS_PER_PKT)) {
2975 dev_kfree_skb_any(skb);
2976 BNAD_UPDATE_CTR(bnad, tx_skb_max_vectors);
2977 return NETDEV_TX_OK;
2978 }
2979
2980 /* Check for available TxQ resources */
2981 if (unlikely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
2982 if ((*tcb->hw_consumer_index != tcb->consumer_index) &&
2983 !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
2984 u32 sent;
2985 sent = bnad_txcmpl_process(bnad, tcb);
2986 if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
2987 bna_ib_ack(tcb->i_dbell, sent);
2988 smp_mb__before_atomic();
2989 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
2990 } else {
2991 netif_stop_queue(netdev);
2992 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
2993 }
2994
2995 smp_mb();
2996 /*
2997 * Check again to deal with race condition between
2998 * netif_stop_queue here, and netif_wake_queue in
2999 * interrupt handler which is not inside netif tx lock.
3000 */
3001 if (likely(wis > BNA_QE_FREE_CNT(tcb, q_depth))) {
3002 BNAD_UPDATE_CTR(bnad, netif_queue_stop);
3003 return NETDEV_TX_BUSY;
3004 } else {
3005 netif_wake_queue(netdev);
3006 BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
3007 }
3008 }
3009
3010 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3011 head_unmap = &unmap_q[prod];
3012
3013 /* Program the opcode, flags, frame_len, num_vectors in WI */
3014 if (bnad_txq_wi_prepare(bnad, tcb, skb, txqent)) {
3015 dev_kfree_skb_any(skb);
3016 return NETDEV_TX_OK;
3017 }
3018 txqent->hdr.wi.reserved = 0;
3019 txqent->hdr.wi.num_vectors = vectors;
3020
3021 head_unmap->skb = skb;
3022 head_unmap->nvecs = 0;
3023
3024 /* Program the vectors */
3025 unmap = head_unmap;
3026 dma_addr = dma_map_single(&bnad->pcidev->dev, skb->data,
3027 len, DMA_TO_DEVICE);
3028 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[0].host_addr);
3029 txqent->vector[0].length = htons(len);
3030 dma_unmap_addr_set(&unmap->vectors[0], dma_addr, dma_addr);
3031 head_unmap->nvecs++;
3032
3033 for (i = 0, vect_id = 0; i < vectors - 1; i++) {
3034 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
3035 u32 size = skb_frag_size(frag);
3036
3037 if (unlikely(size == 0)) {
3038 /* Undo the changes starting at tcb->producer_index */
3039 bnad_tx_buff_unmap(bnad, unmap_q, q_depth,
3040 tcb->producer_index);
3041 dev_kfree_skb_any(skb);
3042 BNAD_UPDATE_CTR(bnad, tx_skb_frag_zero);
3043 return NETDEV_TX_OK;
3044 }
3045
3046 len += size;
3047
3048 vect_id++;
3049 if (vect_id == BFI_TX_MAX_VECTORS_PER_WI) {
3050 vect_id = 0;
3051 BNA_QE_INDX_INC(prod, q_depth);
3052 txqent = &((struct bna_txq_entry *)tcb->sw_q)[prod];
3053 txqent->hdr.wi_ext.opcode = htons(BNA_TXQ_WI_EXTENSION);
3054 unmap = &unmap_q[prod];
3055 }
3056
3057 dma_addr = skb_frag_dma_map(&bnad->pcidev->dev, frag,
3058 0, size, DMA_TO_DEVICE);
3059 dma_unmap_len_set(&unmap->vectors[vect_id], dma_len, size);
3060 BNA_SET_DMA_ADDR(dma_addr, &txqent->vector[vect_id].host_addr);
3061 txqent->vector[vect_id].length = htons(size);
3062 dma_unmap_addr_set(&unmap->vectors[vect_id], dma_addr,
3063 dma_addr);
3064 head_unmap->nvecs++;
3065 }
3066
3067 if (unlikely(len != skb->len)) {
3068 /* Undo the changes starting at tcb->producer_index */
3069 bnad_tx_buff_unmap(bnad, unmap_q, q_depth, tcb->producer_index);
3070 dev_kfree_skb_any(skb);
3071 BNAD_UPDATE_CTR(bnad, tx_skb_len_mismatch);
3072 return NETDEV_TX_OK;
3073 }
3074
3075 BNA_QE_INDX_INC(prod, q_depth);
3076 tcb->producer_index = prod;
3077
3078 smp_mb();
3079
3080 if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
3081 return NETDEV_TX_OK;
3082
3083 skb_tx_timestamp(skb);
3084
3085 bna_txq_prod_indx_doorbell(tcb);
3086 smp_mb();
3087
3088 return NETDEV_TX_OK;
3089 }
3090
3091 /*
3092 * Used spin_lock to synchronize reading of stats structures, which
3093 * is written by BNA under the same lock.
3094 */
3095 static struct rtnl_link_stats64 *
3096 bnad_get_stats64(struct net_device *netdev, struct rtnl_link_stats64 *stats)
3097 {
3098 struct bnad *bnad = netdev_priv(netdev);
3099 unsigned long flags;
3100
3101 spin_lock_irqsave(&bnad->bna_lock, flags);
3102
3103 bnad_netdev_qstats_fill(bnad, stats);
3104 bnad_netdev_hwstats_fill(bnad, stats);
3105
3106 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3107
3108 return stats;
3109 }
3110
3111 static void
3112 bnad_set_rx_ucast_fltr(struct bnad *bnad)
3113 {
3114 struct net_device *netdev = bnad->netdev;
3115 int uc_count = netdev_uc_count(netdev);
3116 enum bna_cb_status ret;
3117 u8 *mac_list;
3118 struct netdev_hw_addr *ha;
3119 int entry;
3120
3121 if (netdev_uc_empty(bnad->netdev)) {
3122 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
3123 return;
3124 }
3125
3126 if (uc_count > bna_attr(&bnad->bna)->num_ucmac)
3127 goto mode_default;
3128
3129 mac_list = kzalloc(uc_count * ETH_ALEN, GFP_ATOMIC);
3130 if (mac_list == NULL)
3131 goto mode_default;
3132
3133 entry = 0;
3134 netdev_for_each_uc_addr(ha, netdev) {
3135 ether_addr_copy(&mac_list[entry * ETH_ALEN], &ha->addr[0]);
3136 entry++;
3137 }
3138
3139 ret = bna_rx_ucast_listset(bnad->rx_info[0].rx, entry, mac_list);
3140 kfree(mac_list);
3141
3142 if (ret != BNA_CB_SUCCESS)
3143 goto mode_default;
3144
3145 return;
3146
3147 /* ucast packets not in UCAM are routed to default function */
3148 mode_default:
3149 bnad->cfg_flags |= BNAD_CF_DEFAULT;
3150 bna_rx_ucast_listset(bnad->rx_info[0].rx, 0, NULL);
3151 }
3152
3153 static void
3154 bnad_set_rx_mcast_fltr(struct bnad *bnad)
3155 {
3156 struct net_device *netdev = bnad->netdev;
3157 int mc_count = netdev_mc_count(netdev);
3158 enum bna_cb_status ret;
3159 u8 *mac_list;
3160
3161 if (netdev->flags & IFF_ALLMULTI)
3162 goto mode_allmulti;
3163
3164 if (netdev_mc_empty(netdev))
3165 return;
3166
3167 if (mc_count > bna_attr(&bnad->bna)->num_mcmac)
3168 goto mode_allmulti;
3169
3170 mac_list = kzalloc((mc_count + 1) * ETH_ALEN, GFP_ATOMIC);
3171
3172 if (mac_list == NULL)
3173 goto mode_allmulti;
3174
3175 ether_addr_copy(&mac_list[0], &bnad_bcast_addr[0]);
3176
3177 /* copy rest of the MCAST addresses */
3178 bnad_netdev_mc_list_get(netdev, mac_list);
3179 ret = bna_rx_mcast_listset(bnad->rx_info[0].rx, mc_count + 1, mac_list);
3180 kfree(mac_list);
3181
3182 if (ret != BNA_CB_SUCCESS)
3183 goto mode_allmulti;
3184
3185 return;
3186
3187 mode_allmulti:
3188 bnad->cfg_flags |= BNAD_CF_ALLMULTI;
3189 bna_rx_mcast_delall(bnad->rx_info[0].rx);
3190 }
3191
3192 void
3193 bnad_set_rx_mode(struct net_device *netdev)
3194 {
3195 struct bnad *bnad = netdev_priv(netdev);
3196 enum bna_rxmode new_mode, mode_mask;
3197 unsigned long flags;
3198
3199 spin_lock_irqsave(&bnad->bna_lock, flags);
3200
3201 if (bnad->rx_info[0].rx == NULL) {
3202 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3203 return;
3204 }
3205
3206 /* clear bnad flags to update it with new settings */
3207 bnad->cfg_flags &= ~(BNAD_CF_PROMISC | BNAD_CF_DEFAULT |
3208 BNAD_CF_ALLMULTI);
3209
3210 new_mode = 0;
3211 if (netdev->flags & IFF_PROMISC) {
3212 new_mode |= BNAD_RXMODE_PROMISC_DEFAULT;
3213 bnad->cfg_flags |= BNAD_CF_PROMISC;
3214 } else {
3215 bnad_set_rx_mcast_fltr(bnad);
3216
3217 if (bnad->cfg_flags & BNAD_CF_ALLMULTI)
3218 new_mode |= BNA_RXMODE_ALLMULTI;
3219
3220 bnad_set_rx_ucast_fltr(bnad);
3221
3222 if (bnad->cfg_flags & BNAD_CF_DEFAULT)
3223 new_mode |= BNA_RXMODE_DEFAULT;
3224 }
3225
3226 mode_mask = BNA_RXMODE_PROMISC | BNA_RXMODE_DEFAULT |
3227 BNA_RXMODE_ALLMULTI;
3228 bna_rx_mode_set(bnad->rx_info[0].rx, new_mode, mode_mask);
3229
3230 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3231 }
3232
3233 /*
3234 * bna_lock is used to sync writes to netdev->addr
3235 * conf_lock cannot be used since this call may be made
3236 * in a non-blocking context.
3237 */
3238 static int
3239 bnad_set_mac_address(struct net_device *netdev, void *addr)
3240 {
3241 int err;
3242 struct bnad *bnad = netdev_priv(netdev);
3243 struct sockaddr *sa = (struct sockaddr *)addr;
3244 unsigned long flags;
3245
3246 spin_lock_irqsave(&bnad->bna_lock, flags);
3247
3248 err = bnad_mac_addr_set_locked(bnad, sa->sa_data);
3249 if (!err)
3250 ether_addr_copy(netdev->dev_addr, sa->sa_data);
3251
3252 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3253
3254 return err;
3255 }
3256
3257 static int
3258 bnad_mtu_set(struct bnad *bnad, int frame_size)
3259 {
3260 unsigned long flags;
3261
3262 init_completion(&bnad->bnad_completions.mtu_comp);
3263
3264 spin_lock_irqsave(&bnad->bna_lock, flags);
3265 bna_enet_mtu_set(&bnad->bna.enet, frame_size, bnad_cb_enet_mtu_set);
3266 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3267
3268 wait_for_completion(&bnad->bnad_completions.mtu_comp);
3269
3270 return bnad->bnad_completions.mtu_comp_status;
3271 }
3272
3273 static int
3274 bnad_change_mtu(struct net_device *netdev, int new_mtu)
3275 {
3276 int err, mtu;
3277 struct bnad *bnad = netdev_priv(netdev);
3278 u32 rx_count = 0, frame, new_frame;
3279
3280 if (new_mtu + ETH_HLEN < ETH_ZLEN || new_mtu > BNAD_JUMBO_MTU)
3281 return -EINVAL;
3282
3283 mutex_lock(&bnad->conf_mutex);
3284
3285 mtu = netdev->mtu;
3286 netdev->mtu = new_mtu;
3287
3288 frame = BNAD_FRAME_SIZE(mtu);
3289 new_frame = BNAD_FRAME_SIZE(new_mtu);
3290
3291 /* check if multi-buffer needs to be enabled */
3292 if (BNAD_PCI_DEV_IS_CAT2(bnad) &&
3293 netif_running(bnad->netdev)) {
3294 /* only when transition is over 4K */
3295 if ((frame <= 4096 && new_frame > 4096) ||
3296 (frame > 4096 && new_frame <= 4096))
3297 rx_count = bnad_reinit_rx(bnad);
3298 }
3299
3300 /* rx_count > 0 - new rx created
3301 * - Linux set err = 0 and return
3302 */
3303 err = bnad_mtu_set(bnad, new_frame);
3304 if (err)
3305 err = -EBUSY;
3306
3307 mutex_unlock(&bnad->conf_mutex);
3308 return err;
3309 }
3310
3311 static int
3312 bnad_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
3313 {
3314 struct bnad *bnad = netdev_priv(netdev);
3315 unsigned long flags;
3316
3317 if (!bnad->rx_info[0].rx)
3318 return 0;
3319
3320 mutex_lock(&bnad->conf_mutex);
3321
3322 spin_lock_irqsave(&bnad->bna_lock, flags);
3323 bna_rx_vlan_add(bnad->rx_info[0].rx, vid);
3324 set_bit(vid, bnad->active_vlans);
3325 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3326
3327 mutex_unlock(&bnad->conf_mutex);
3328
3329 return 0;
3330 }
3331
3332 static int
3333 bnad_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
3334 {
3335 struct bnad *bnad = netdev_priv(netdev);
3336 unsigned long flags;
3337
3338 if (!bnad->rx_info[0].rx)
3339 return 0;
3340
3341 mutex_lock(&bnad->conf_mutex);
3342
3343 spin_lock_irqsave(&bnad->bna_lock, flags);
3344 clear_bit(vid, bnad->active_vlans);
3345 bna_rx_vlan_del(bnad->rx_info[0].rx, vid);
3346 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3347
3348 mutex_unlock(&bnad->conf_mutex);
3349
3350 return 0;
3351 }
3352
3353 static int bnad_set_features(struct net_device *dev, netdev_features_t features)
3354 {
3355 struct bnad *bnad = netdev_priv(dev);
3356 netdev_features_t changed = features ^ dev->features;
3357
3358 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(dev)) {
3359 unsigned long flags;
3360
3361 spin_lock_irqsave(&bnad->bna_lock, flags);
3362
3363 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3364 bna_rx_vlan_strip_enable(bnad->rx_info[0].rx);
3365 else
3366 bna_rx_vlan_strip_disable(bnad->rx_info[0].rx);
3367
3368 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3369 }
3370
3371 return 0;
3372 }
3373
3374 #ifdef CONFIG_NET_POLL_CONTROLLER
3375 static void
3376 bnad_netpoll(struct net_device *netdev)
3377 {
3378 struct bnad *bnad = netdev_priv(netdev);
3379 struct bnad_rx_info *rx_info;
3380 struct bnad_rx_ctrl *rx_ctrl;
3381 u32 curr_mask;
3382 int i, j;
3383
3384 if (!(bnad->cfg_flags & BNAD_CF_MSIX)) {
3385 bna_intx_disable(&bnad->bna, curr_mask);
3386 bnad_isr(bnad->pcidev->irq, netdev);
3387 bna_intx_enable(&bnad->bna, curr_mask);
3388 } else {
3389 /*
3390 * Tx processing may happen in sending context, so no need
3391 * to explicitly process completions here
3392 */
3393
3394 /* Rx processing */
3395 for (i = 0; i < bnad->num_rx; i++) {
3396 rx_info = &bnad->rx_info[i];
3397 if (!rx_info->rx)
3398 continue;
3399 for (j = 0; j < bnad->num_rxp_per_rx; j++) {
3400 rx_ctrl = &rx_info->rx_ctrl[j];
3401 if (rx_ctrl->ccb)
3402 bnad_netif_rx_schedule_poll(bnad,
3403 rx_ctrl->ccb);
3404 }
3405 }
3406 }
3407 }
3408 #endif
3409
3410 static const struct net_device_ops bnad_netdev_ops = {
3411 .ndo_open = bnad_open,
3412 .ndo_stop = bnad_stop,
3413 .ndo_start_xmit = bnad_start_xmit,
3414 .ndo_get_stats64 = bnad_get_stats64,
3415 .ndo_set_rx_mode = bnad_set_rx_mode,
3416 .ndo_validate_addr = eth_validate_addr,
3417 .ndo_set_mac_address = bnad_set_mac_address,
3418 .ndo_change_mtu = bnad_change_mtu,
3419 .ndo_vlan_rx_add_vid = bnad_vlan_rx_add_vid,
3420 .ndo_vlan_rx_kill_vid = bnad_vlan_rx_kill_vid,
3421 .ndo_set_features = bnad_set_features,
3422 #ifdef CONFIG_NET_POLL_CONTROLLER
3423 .ndo_poll_controller = bnad_netpoll
3424 #endif
3425 };
3426
3427 static void
3428 bnad_netdev_init(struct bnad *bnad, bool using_dac)
3429 {
3430 struct net_device *netdev = bnad->netdev;
3431
3432 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
3433 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3434 NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_TX |
3435 NETIF_F_HW_VLAN_CTAG_RX;
3436
3437 netdev->vlan_features = NETIF_F_SG | NETIF_F_HIGHDMA |
3438 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
3439 NETIF_F_TSO | NETIF_F_TSO6;
3440
3441 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
3442
3443 if (using_dac)
3444 netdev->features |= NETIF_F_HIGHDMA;
3445
3446 netdev->mem_start = bnad->mmio_start;
3447 netdev->mem_end = bnad->mmio_start + bnad->mmio_len - 1;
3448
3449 netdev->netdev_ops = &bnad_netdev_ops;
3450 bnad_set_ethtool_ops(netdev);
3451 }
3452
3453 /*
3454 * 1. Initialize the bnad structure
3455 * 2. Setup netdev pointer in pci_dev
3456 * 3. Initialize no. of TxQ & CQs & MSIX vectors
3457 * 4. Initialize work queue.
3458 */
3459 static int
3460 bnad_init(struct bnad *bnad,
3461 struct pci_dev *pdev, struct net_device *netdev)
3462 {
3463 unsigned long flags;
3464
3465 SET_NETDEV_DEV(netdev, &pdev->dev);
3466 pci_set_drvdata(pdev, netdev);
3467
3468 bnad->netdev = netdev;
3469 bnad->pcidev = pdev;
3470 bnad->mmio_start = pci_resource_start(pdev, 0);
3471 bnad->mmio_len = pci_resource_len(pdev, 0);
3472 bnad->bar0 = ioremap_nocache(bnad->mmio_start, bnad->mmio_len);
3473 if (!bnad->bar0) {
3474 dev_err(&pdev->dev, "ioremap for bar0 failed\n");
3475 return -ENOMEM;
3476 }
3477 dev_info(&pdev->dev, "bar0 mapped to %p, len %llu\n", bnad->bar0,
3478 (unsigned long long) bnad->mmio_len);
3479
3480 spin_lock_irqsave(&bnad->bna_lock, flags);
3481 if (!bnad_msix_disable)
3482 bnad->cfg_flags = BNAD_CF_MSIX;
3483
3484 bnad->cfg_flags |= BNAD_CF_DIM_ENABLED;
3485
3486 bnad_q_num_init(bnad);
3487 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3488
3489 bnad->msix_num = (bnad->num_tx * bnad->num_txq_per_tx) +
3490 (bnad->num_rx * bnad->num_rxp_per_rx) +
3491 BNAD_MAILBOX_MSIX_VECTORS;
3492
3493 bnad->txq_depth = BNAD_TXQ_DEPTH;
3494 bnad->rxq_depth = BNAD_RXQ_DEPTH;
3495
3496 bnad->tx_coalescing_timeo = BFI_TX_COALESCING_TIMEO;
3497 bnad->rx_coalescing_timeo = BFI_RX_COALESCING_TIMEO;
3498
3499 sprintf(bnad->wq_name, "%s_wq_%d", BNAD_NAME, bnad->id);
3500 bnad->work_q = create_singlethread_workqueue(bnad->wq_name);
3501 if (!bnad->work_q) {
3502 iounmap(bnad->bar0);
3503 return -ENOMEM;
3504 }
3505
3506 return 0;
3507 }
3508
3509 /*
3510 * Must be called after bnad_pci_uninit()
3511 * so that iounmap() and pci_set_drvdata(NULL)
3512 * happens only after PCI uninitialization.
3513 */
3514 static void
3515 bnad_uninit(struct bnad *bnad)
3516 {
3517 if (bnad->work_q) {
3518 flush_workqueue(bnad->work_q);
3519 destroy_workqueue(bnad->work_q);
3520 bnad->work_q = NULL;
3521 }
3522
3523 if (bnad->bar0)
3524 iounmap(bnad->bar0);
3525 }
3526
3527 /*
3528 * Initialize locks
3529 a) Per ioceth mutes used for serializing configuration
3530 changes from OS interface
3531 b) spin lock used to protect bna state machine
3532 */
3533 static void
3534 bnad_lock_init(struct bnad *bnad)
3535 {
3536 spin_lock_init(&bnad->bna_lock);
3537 mutex_init(&bnad->conf_mutex);
3538 mutex_init(&bnad_list_mutex);
3539 }
3540
3541 static void
3542 bnad_lock_uninit(struct bnad *bnad)
3543 {
3544 mutex_destroy(&bnad->conf_mutex);
3545 mutex_destroy(&bnad_list_mutex);
3546 }
3547
3548 /* PCI Initialization */
3549 static int
3550 bnad_pci_init(struct bnad *bnad,
3551 struct pci_dev *pdev, bool *using_dac)
3552 {
3553 int err;
3554
3555 err = pci_enable_device(pdev);
3556 if (err)
3557 return err;
3558 err = pci_request_regions(pdev, BNAD_NAME);
3559 if (err)
3560 goto disable_device;
3561 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
3562 *using_dac = true;
3563 } else {
3564 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3565 if (err)
3566 goto release_regions;
3567 *using_dac = false;
3568 }
3569 pci_set_master(pdev);
3570 return 0;
3571
3572 release_regions:
3573 pci_release_regions(pdev);
3574 disable_device:
3575 pci_disable_device(pdev);
3576
3577 return err;
3578 }
3579
3580 static void
3581 bnad_pci_uninit(struct pci_dev *pdev)
3582 {
3583 pci_release_regions(pdev);
3584 pci_disable_device(pdev);
3585 }
3586
3587 static int
3588 bnad_pci_probe(struct pci_dev *pdev,
3589 const struct pci_device_id *pcidev_id)
3590 {
3591 bool using_dac;
3592 int err;
3593 struct bnad *bnad;
3594 struct bna *bna;
3595 struct net_device *netdev;
3596 struct bfa_pcidev pcidev_info;
3597 unsigned long flags;
3598
3599 mutex_lock(&bnad_fwimg_mutex);
3600 if (!cna_get_firmware_buf(pdev)) {
3601 mutex_unlock(&bnad_fwimg_mutex);
3602 dev_err(&pdev->dev, "failed to load firmware image!\n");
3603 return -ENODEV;
3604 }
3605 mutex_unlock(&bnad_fwimg_mutex);
3606
3607 /*
3608 * Allocates sizeof(struct net_device + struct bnad)
3609 * bnad = netdev->priv
3610 */
3611 netdev = alloc_etherdev(sizeof(struct bnad));
3612 if (!netdev) {
3613 err = -ENOMEM;
3614 return err;
3615 }
3616 bnad = netdev_priv(netdev);
3617 bnad_lock_init(bnad);
3618 bnad_add_to_list(bnad);
3619
3620 mutex_lock(&bnad->conf_mutex);
3621 /*
3622 * PCI initialization
3623 * Output : using_dac = 1 for 64 bit DMA
3624 * = 0 for 32 bit DMA
3625 */
3626 using_dac = false;
3627 err = bnad_pci_init(bnad, pdev, &using_dac);
3628 if (err)
3629 goto unlock_mutex;
3630
3631 /*
3632 * Initialize bnad structure
3633 * Setup relation between pci_dev & netdev
3634 */
3635 err = bnad_init(bnad, pdev, netdev);
3636 if (err)
3637 goto pci_uninit;
3638
3639 /* Initialize netdev structure, set up ethtool ops */
3640 bnad_netdev_init(bnad, using_dac);
3641
3642 /* Set link to down state */
3643 netif_carrier_off(netdev);
3644
3645 /* Setup the debugfs node for this bfad */
3646 if (bna_debugfs_enable)
3647 bnad_debugfs_init(bnad);
3648
3649 /* Get resource requirement form bna */
3650 spin_lock_irqsave(&bnad->bna_lock, flags);
3651 bna_res_req(&bnad->res_info[0]);
3652 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3653
3654 /* Allocate resources from bna */
3655 err = bnad_res_alloc(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3656 if (err)
3657 goto drv_uninit;
3658
3659 bna = &bnad->bna;
3660
3661 /* Setup pcidev_info for bna_init() */
3662 pcidev_info.pci_slot = PCI_SLOT(bnad->pcidev->devfn);
3663 pcidev_info.pci_func = PCI_FUNC(bnad->pcidev->devfn);
3664 pcidev_info.device_id = bnad->pcidev->device;
3665 pcidev_info.pci_bar_kva = bnad->bar0;
3666
3667 spin_lock_irqsave(&bnad->bna_lock, flags);
3668 bna_init(bna, bnad, &pcidev_info, &bnad->res_info[0]);
3669 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3670
3671 bnad->stats.bna_stats = &bna->stats;
3672
3673 bnad_enable_msix(bnad);
3674 err = bnad_mbox_irq_alloc(bnad);
3675 if (err)
3676 goto res_free;
3677
3678 /* Set up timers */
3679 setup_timer(&bnad->bna.ioceth.ioc.ioc_timer, bnad_ioc_timeout,
3680 (unsigned long)bnad);
3681 setup_timer(&bnad->bna.ioceth.ioc.hb_timer, bnad_ioc_hb_check,
3682 (unsigned long)bnad);
3683 setup_timer(&bnad->bna.ioceth.ioc.iocpf_timer, bnad_iocpf_timeout,
3684 (unsigned long)bnad);
3685 setup_timer(&bnad->bna.ioceth.ioc.sem_timer, bnad_iocpf_sem_timeout,
3686 (unsigned long)bnad);
3687
3688 /*
3689 * Start the chip
3690 * If the call back comes with error, we bail out.
3691 * This is a catastrophic error.
3692 */
3693 err = bnad_ioceth_enable(bnad);
3694 if (err) {
3695 dev_err(&pdev->dev, "initialization failed err=%d\n", err);
3696 goto probe_success;
3697 }
3698
3699 spin_lock_irqsave(&bnad->bna_lock, flags);
3700 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3701 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1)) {
3702 bnad_q_num_adjust(bnad, bna_attr(bna)->num_txq - 1,
3703 bna_attr(bna)->num_rxp - 1);
3704 if (bna_num_txq_set(bna, BNAD_NUM_TXQ + 1) ||
3705 bna_num_rxp_set(bna, BNAD_NUM_RXP + 1))
3706 err = -EIO;
3707 }
3708 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3709 if (err)
3710 goto disable_ioceth;
3711
3712 spin_lock_irqsave(&bnad->bna_lock, flags);
3713 bna_mod_res_req(&bnad->bna, &bnad->mod_res_info[0]);
3714 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3715
3716 err = bnad_res_alloc(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3717 if (err) {
3718 err = -EIO;
3719 goto disable_ioceth;
3720 }
3721
3722 spin_lock_irqsave(&bnad->bna_lock, flags);
3723 bna_mod_init(&bnad->bna, &bnad->mod_res_info[0]);
3724 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3725
3726 /* Get the burnt-in mac */
3727 spin_lock_irqsave(&bnad->bna_lock, flags);
3728 bna_enet_perm_mac_get(&bna->enet, bnad->perm_addr);
3729 bnad_set_netdev_perm_addr(bnad);
3730 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3731
3732 mutex_unlock(&bnad->conf_mutex);
3733
3734 /* Finally, reguister with net_device layer */
3735 err = register_netdev(netdev);
3736 if (err) {
3737 dev_err(&pdev->dev, "registering net device failed\n");
3738 goto probe_uninit;
3739 }
3740 set_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags);
3741
3742 return 0;
3743
3744 probe_success:
3745 mutex_unlock(&bnad->conf_mutex);
3746 return 0;
3747
3748 probe_uninit:
3749 mutex_lock(&bnad->conf_mutex);
3750 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3751 disable_ioceth:
3752 bnad_ioceth_disable(bnad);
3753 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3754 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3755 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3756 spin_lock_irqsave(&bnad->bna_lock, flags);
3757 bna_uninit(bna);
3758 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3759 bnad_mbox_irq_free(bnad);
3760 bnad_disable_msix(bnad);
3761 res_free:
3762 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3763 drv_uninit:
3764 /* Remove the debugfs node for this bnad */
3765 kfree(bnad->regdata);
3766 bnad_debugfs_uninit(bnad);
3767 bnad_uninit(bnad);
3768 pci_uninit:
3769 bnad_pci_uninit(pdev);
3770 unlock_mutex:
3771 mutex_unlock(&bnad->conf_mutex);
3772 bnad_remove_from_list(bnad);
3773 bnad_lock_uninit(bnad);
3774 free_netdev(netdev);
3775 return err;
3776 }
3777
3778 static void
3779 bnad_pci_remove(struct pci_dev *pdev)
3780 {
3781 struct net_device *netdev = pci_get_drvdata(pdev);
3782 struct bnad *bnad;
3783 struct bna *bna;
3784 unsigned long flags;
3785
3786 if (!netdev)
3787 return;
3788
3789 bnad = netdev_priv(netdev);
3790 bna = &bnad->bna;
3791
3792 if (test_and_clear_bit(BNAD_RF_NETDEV_REGISTERED, &bnad->run_flags))
3793 unregister_netdev(netdev);
3794
3795 mutex_lock(&bnad->conf_mutex);
3796 bnad_ioceth_disable(bnad);
3797 del_timer_sync(&bnad->bna.ioceth.ioc.ioc_timer);
3798 del_timer_sync(&bnad->bna.ioceth.ioc.sem_timer);
3799 del_timer_sync(&bnad->bna.ioceth.ioc.hb_timer);
3800 spin_lock_irqsave(&bnad->bna_lock, flags);
3801 bna_uninit(bna);
3802 spin_unlock_irqrestore(&bnad->bna_lock, flags);
3803
3804 bnad_res_free(bnad, &bnad->mod_res_info[0], BNA_MOD_RES_T_MAX);
3805 bnad_res_free(bnad, &bnad->res_info[0], BNA_RES_T_MAX);
3806 bnad_mbox_irq_free(bnad);
3807 bnad_disable_msix(bnad);
3808 bnad_pci_uninit(pdev);
3809 mutex_unlock(&bnad->conf_mutex);
3810 bnad_remove_from_list(bnad);
3811 bnad_lock_uninit(bnad);
3812 /* Remove the debugfs node for this bnad */
3813 kfree(bnad->regdata);
3814 bnad_debugfs_uninit(bnad);
3815 bnad_uninit(bnad);
3816 free_netdev(netdev);
3817 }
3818
3819 static const struct pci_device_id bnad_pci_id_table[] = {
3820 {
3821 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3822 PCI_DEVICE_ID_BROCADE_CT),
3823 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3824 .class_mask = 0xffff00
3825 },
3826 {
3827 PCI_DEVICE(PCI_VENDOR_ID_BROCADE,
3828 BFA_PCI_DEVICE_ID_CT2),
3829 .class = PCI_CLASS_NETWORK_ETHERNET << 8,
3830 .class_mask = 0xffff00
3831 },
3832 {0, },
3833 };
3834
3835 MODULE_DEVICE_TABLE(pci, bnad_pci_id_table);
3836
3837 static struct pci_driver bnad_pci_driver = {
3838 .name = BNAD_NAME,
3839 .id_table = bnad_pci_id_table,
3840 .probe = bnad_pci_probe,
3841 .remove = bnad_pci_remove,
3842 };
3843
3844 static int __init
3845 bnad_module_init(void)
3846 {
3847 int err;
3848
3849 pr_info("bna: QLogic BR-series 10G Ethernet driver - version: %s\n",
3850 BNAD_VERSION);
3851
3852 bfa_nw_ioc_auto_recover(bnad_ioc_auto_recover);
3853
3854 err = pci_register_driver(&bnad_pci_driver);
3855 if (err < 0) {
3856 pr_err("bna: PCI driver registration failed err=%d\n", err);
3857 return err;
3858 }
3859
3860 return 0;
3861 }
3862
3863 static void __exit
3864 bnad_module_exit(void)
3865 {
3866 pci_unregister_driver(&bnad_pci_driver);
3867 release_firmware(bfi_fw);
3868 }
3869
3870 module_init(bnad_module_init);
3871 module_exit(bnad_module_exit);
3872
3873 MODULE_AUTHOR("Brocade");
3874 MODULE_LICENSE("GPL");
3875 MODULE_DESCRIPTION("QLogic BR-series 10G PCIe Ethernet driver");
3876 MODULE_VERSION(BNAD_VERSION);
3877 MODULE_FIRMWARE(CNA_FW_FILE_CT);
3878 MODULE_FIRMWARE(CNA_FW_FILE_CT2);
Linux kernel - Deliverables
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