drivers/net/ethernet/cavium/liquidio/liquidio_common.h

   1 /**********************************************************************
   2 * Author: Cavium, Inc.
   3 *
   4 * Contact: support@cavium.com
   5 *          Please include "LiquidIO" in the subject.
   6 *
   7 * Copyright (c) 2003-2015 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * This file may also be available under a different license from Cavium.
  20 * Contact Cavium, Inc. for more information
  21 **********************************************************************/
  22
  23 /*!  \file  liquidio_common.h
  24  *   \brief Common: Structures and macros used in PCI-NIC package by core and
  25  *   host driver.
  26  */
  27
  28 #ifndef __LIQUIDIO_COMMON_H__
  29 #define __LIQUIDIO_COMMON_H__
  30
  31 #include "octeon_config.h"
  32
  33 #define LIQUIDIO_VERSION        "1.1.9"
  34 #define LIQUIDIO_MAJOR_VERSION  1
  35 #define LIQUIDIO_MINOR_VERSION  1
  36 #define LIQUIDIO_MICRO_VERSION  9
  37
  38 #define CONTROL_IQ 0
  39 /** Tag types used by Octeon cores in its work. */
  40 enum octeon_tag_type {
  41         ORDERED_TAG = 0,
  42         ATOMIC_TAG = 1,
  43         NULL_TAG = 2,
  44         NULL_NULL_TAG = 3
  45 };
  46
  47 /* pre-defined host->NIC tag values */
  48 #define LIO_CONTROL  (0x11111110)
  49 #define LIO_DATA(i)  (0x11111111 + (i))
  50
  51 /* Opcodes used by host driver/apps to perform operations on the core.
  52  * These are used to identify the major subsystem that the operation
  53  * is for.
  54  */
  55 #define OPCODE_CORE 0           /* used for generic core operations */
  56 #define OPCODE_NIC  1           /* used for NIC operations */
  57 #define OPCODE_LAST OPCODE_NIC
  58
  59 /* Subcodes are used by host driver/apps to identify the sub-operation
  60  * for the core. They only need to by unique for a given subsystem.
  61  */
  62 #define OPCODE_SUBCODE(op, sub)       (((op & 0x0f) << 8) | ((sub) & 0x7f))
  63
  64 /** OPCODE_CORE subcodes. For future use. */
  65
  66 /** OPCODE_NIC subcodes */
  67
  68 /* This subcode is sent by core PCI driver to indicate cores are ready. */
  69 #define OPCODE_NIC_CORE_DRV_ACTIVE     0x01
  70 #define OPCODE_NIC_NW_DATA             0x02     /* network packet data */
  71 #define OPCODE_NIC_CMD                 0x03
  72 #define OPCODE_NIC_INFO                0x04
  73 #define OPCODE_NIC_PORT_STATS          0x05
  74 #define OPCODE_NIC_MDIO45              0x06
  75 #define OPCODE_NIC_TIMESTAMP           0x07
  76 #define OPCODE_NIC_INTRMOD_CFG         0x08
  77 #define OPCODE_NIC_IF_CFG              0x09
  78
  79 #define CORE_DRV_TEST_SCATTER_OP    0xFFF5
  80
  81 #define OPCODE_SLOW_PATH(rh)  \
  82         (OPCODE_SUBCODE(rh->r.opcode, rh->r.subcode) != \
  83                 OPCODE_SUBCODE(OPCODE_NIC, OPCODE_NIC_NW_DATA))
  84
  85 /* Application codes advertised by the core driver initialization packet. */
  86 #define CVM_DRV_APP_START           0x0
  87 #define CVM_DRV_NO_APP              0
  88 #define CVM_DRV_APP_COUNT           0x2
  89 #define CVM_DRV_BASE_APP            (CVM_DRV_APP_START + 0x0)
  90 #define CVM_DRV_NIC_APP             (CVM_DRV_APP_START + 0x1)
  91 #define CVM_DRV_INVALID_APP         (CVM_DRV_APP_START + 0x2)
  92 #define CVM_DRV_APP_END             (CVM_DRV_INVALID_APP - 1)
  93
  94 /* Macro to increment index.
  95  * Index is incremented by count; if the sum exceeds
  96  * max, index is wrapped-around to the start.
  97  */
  98 #define INCR_INDEX(index, count, max)                \
  99 do {                                                 \
 100         if (((index) + (count)) >= (max))            \
 101                 index = ((index) + (count)) - (max); \
 102         else                                         \
 103                 index += (count);                    \
 104 } while (0)
 105
 106 #define INCR_INDEX_BY1(index, max)      \
 107 do {                                    \
 108         if ((++(index)) == (max))       \
 109                 index = 0;              \
 110 } while (0)
 111
 112 #define DECR_INDEX(index, count, max)                  \
 113 do {                                                   \
 114         if ((count) > (index))                         \
 115                 index = ((max) - ((count - index)));   \
 116         else                                           \
 117                 index -= count;                        \
 118 } while (0)
 119
 120 #define OCT_BOARD_NAME 32
 121 #define OCT_SERIAL_LEN 64
 122
 123 /* Structure used by core driver to send indication that the Octeon
 124  * application is ready.
 125  */
 126 struct octeon_core_setup {
 127         u64 corefreq;
 128
 129         char boardname[OCT_BOARD_NAME];
 130
 131         char board_serial_number[OCT_SERIAL_LEN];
 132
 133         u64 board_rev_major;
 134
 135         u64 board_rev_minor;
 136
 137 };
 138
 139 /*---------------------------  SCATTER GATHER ENTRY  -----------------------*/
 140
 141 /* The Scatter-Gather List Entry. The scatter or gather component used with
 142  * a Octeon input instruction has this format.
 143  */
 144 struct octeon_sg_entry {
 145         /** The first 64 bit gives the size of data in each dptr.*/
 146         union {
 147                 u16 size[4];
 148                 u64 size64;
 149         } u;
 150
 151         /** The 4 dptr pointers for this entry. */
 152         u64 ptr[4];
 153
 154 };
 155
 156 #define OCT_SG_ENTRY_SIZE    (sizeof(struct octeon_sg_entry))
 157
 158 /* \brief Add size to gather list
 159  * @param sg_entry scatter/gather entry
 160  * @param size size to add
 161  * @param pos position to add it.
 162  */
 163 static inline void add_sg_size(struct octeon_sg_entry *sg_entry,
 164                                u16 size,
 165                                u32 pos)
 166 {
 167 #ifdef __BIG_ENDIAN_BITFIELD
 168         sg_entry->u.size[pos] = size;
 169 #else
 170         sg_entry->u.size[3 - pos] = size;
 171 #endif
 172 }
 173
 174 /*------------------------- End Scatter/Gather ---------------------------*/
 175
 176 #define   OCTNET_FRM_PTP_HEADER_SIZE  8
 177 #define   OCTNET_FRM_HEADER_SIZE     30 /* PTP timestamp + VLAN + Ethernet */
 178
 179 #define   OCTNET_MIN_FRM_SIZE        (64  + OCTNET_FRM_PTP_HEADER_SIZE)
 180 #define   OCTNET_MAX_FRM_SIZE        (16000 + OCTNET_FRM_HEADER_SIZE)
 181
 182 #define   OCTNET_DEFAULT_FRM_SIZE    (1500 + OCTNET_FRM_HEADER_SIZE)
 183
 184 /** NIC Commands are sent using this Octeon Input Queue */
 185 #define   OCTNET_CMD_Q                0
 186
 187 /* NIC Command types */
 188 #define   OCTNET_CMD_CHANGE_MTU       0x1
 189 #define   OCTNET_CMD_CHANGE_MACADDR   0x2
 190 #define   OCTNET_CMD_CHANGE_DEVFLAGS  0x3
 191 #define   OCTNET_CMD_RX_CTL           0x4
 192
 193 #define   OCTNET_CMD_SET_MULTI_LIST   0x5
 194 #define   OCTNET_CMD_CLEAR_STATS      0x6
 195
 196 /* command for setting the speed, duplex & autoneg */
 197 #define   OCTNET_CMD_SET_SETTINGS     0x7
 198 #define   OCTNET_CMD_SET_FLOW_CTL     0x8
 199
 200 #define   OCTNET_CMD_MDIO_READ_WRITE  0x9
 201 #define   OCTNET_CMD_GPIO_ACCESS      0xA
 202 #define   OCTNET_CMD_LRO_ENABLE       0xB
 203 #define   OCTNET_CMD_LRO_DISABLE      0xC
 204 #define   OCTNET_CMD_SET_RSS          0xD
 205 #define   OCTNET_CMD_WRITE_SA         0xE
 206 #define   OCTNET_CMD_DELETE_SA        0xF
 207 #define   OCTNET_CMD_UPDATE_SA        0x12
 208
 209 #define   OCTNET_CMD_TNL_RX_CSUM_CTL 0x10
 210 #define   OCTNET_CMD_TNL_TX_CSUM_CTL 0x11
 211 #define   OCTNET_CMD_IPSECV2_AH_ESP_CTL 0x13
 212 #define   OCTNET_CMD_VERBOSE_ENABLE   0x14
 213 #define   OCTNET_CMD_VERBOSE_DISABLE  0x15
 214
 215 /* RX(packets coming from wire) Checksum verification flags */
 216 /* TCP/UDP csum */
 217 #define   CNNIC_L4SUM_VERIFIED             0x1
 218 #define   CNNIC_IPSUM_VERIFIED             0x2
 219 #define   CNNIC_TUN_CSUM_VERIFIED          0x4
 220 #define   CNNIC_CSUM_VERIFIED (CNNIC_IPSUM_VERIFIED | CNNIC_L4SUM_VERIFIED)
 221
 222 /*LROIPV4 and LROIPV6 Flags*/
 223 #define   OCTNIC_LROIPV4    0x1
 224 #define   OCTNIC_LROIPV6    0x2
 225
 226 /* Interface flags communicated between host driver and core app. */
 227 enum octnet_ifflags {
 228         OCTNET_IFFLAG_PROMISC   = 0x01,
 229         OCTNET_IFFLAG_ALLMULTI  = 0x02,
 230         OCTNET_IFFLAG_MULTICAST = 0x04,
 231         OCTNET_IFFLAG_BROADCAST = 0x08,
 232         OCTNET_IFFLAG_UNICAST   = 0x10
 233 };
 234
 235 /*   wqe
 236  *  ---------------  0
 237  * |  wqe  word0-3 |
 238  *  ---------------  32
 239  * |    PCI IH     |
 240  *  ---------------  40
 241  * |     RPTR      |
 242  *  ---------------  48
 243  * |    PCI IRH    |
 244  *  ---------------  56
 245  * |  OCT_NET_CMD  |
 246  *  ---------------  64
 247  * | Addtl 8-BData |
 248  * |               |
 249  *  ---------------
 250  */
 251
 252 union octnet_cmd {
 253         u64 u64;
 254
 255         struct {
 256 #ifdef __BIG_ENDIAN_BITFIELD
 257                 u64 cmd:5;
 258
 259                 u64 more:6; /* How many udd words follow the command */
 260
 261                 u64 param1:29;
 262
 263                 u64 param2:16;
 264
 265                 u64 param3:8;
 266
 267 #else
 268
 269                 u64 param3:8;
 270
 271                 u64 param2:16;
 272
 273                 u64 param1:29;
 274
 275                 u64 more:6;
 276
 277                 u64 cmd:5;
 278
 279 #endif
 280         } s;
 281
 282 };
 283
 284 #define   OCTNET_CMD_SIZE     (sizeof(union octnet_cmd))
 285
 286 /** Instruction Header */
 287 struct octeon_instr_ih {
 288 #ifdef __BIG_ENDIAN_BITFIELD
 289         /** Raw mode indicator 1 = RAW */
 290         u64 raw:1;
 291
 292         /** Gather indicator 1=gather*/
 293         u64 gather:1;
 294
 295         /** Data length OR no. of entries in gather list */
 296         u64 dlengsz:14;
 297
 298         /** Front Data size */
 299         u64 fsz:6;
 300
 301         /** Packet Order / Work Unit selection (1 of 8)*/
 302         u64 qos:3;
 303
 304         /** Core group selection (1 of 16) */
 305         u64 grp:4;
 306
 307         /** Short Raw Packet Indicator 1=short raw pkt */
 308         u64 rs:1;
 309
 310         /** Tag type */
 311         u64 tagtype:2;
 312
 313         /** Tag Value */
 314         u64 tag:32;
 315 #else
 316         /** Tag Value */
 317         u64 tag:32;
 318
 319         /** Tag type */
 320         u64 tagtype:2;
 321
 322         /** Short Raw Packet Indicator 1=short raw pkt */
 323         u64 rs:1;
 324
 325         /** Core group selection (1 of 16) */
 326         u64 grp:4;
 327
 328         /** Packet Order / Work Unit selection (1 of 8)*/
 329         u64 qos:3;
 330
 331         /** Front Data size */
 332         u64 fsz:6;
 333
 334         /** Data length OR no. of entries in gather list */
 335         u64 dlengsz:14;
 336
 337         /** Gather indicator 1=gather*/
 338         u64 gather:1;
 339
 340         /** Raw mode indicator 1 = RAW */
 341         u64 raw:1;
 342 #endif
 343 };
 344
 345 /** Input Request Header */
 346 struct octeon_instr_irh {
 347 #ifdef __BIG_ENDIAN_BITFIELD
 348         u64 opcode:4;
 349         u64 rflag:1;
 350         u64 subcode:7;
 351         u64 len:3;
 352         u64 rid:13;
 353         u64 reserved:4;
 354         u64 ossp:32;             /* opcode/subcode specific parameters */
 355 #else
 356         u64 ossp:32;             /* opcode/subcode specific parameters */
 357         u64 reserved:4;
 358         u64 rid:13;
 359         u64 len:3;
 360         u64 subcode:7;
 361         u64 rflag:1;
 362         u64 opcode:4;
 363 #endif
 364 };
 365
 366 /** Return Data Parameters */
 367 struct octeon_instr_rdp {
 368 #ifdef __BIG_ENDIAN_BITFIELD
 369         u64 reserved:49;
 370         u64 pcie_port:3;
 371         u64 rlen:12;
 372 #else
 373         u64 rlen:12;
 374         u64 pcie_port:3;
 375         u64 reserved:49;
 376 #endif
 377 };
 378
 379 /** Receive Header */
 380 union octeon_rh {
 381 #ifdef __BIG_ENDIAN_BITFIELD
 382         u64 u64;
 383         struct {
 384                 u64 opcode:4;
 385                 u64 subcode:8;
 386                 u64 len:3;       /** additional 64-bit words */
 387                 u64 rid:13;      /** request id in response to pkt sent by host */
 388                 u64 reserved:4;
 389                 u64 ossp:32;     /** opcode/subcode specific parameters */
 390         } r;
 391         struct {
 392                 u64 opcode:4;
 393                 u64 subcode:8;
 394                 u64 len:3;       /** additional 64-bit words */
 395                 u64 rid:13;      /** request id in response to pkt sent by host */
 396                 u64 extra:24;
 397                 u64 link:8;
 398                 u64 csum_verified:3;     /** checksum verified. */
 399                 u64 has_hwtstamp:1;      /** Has hardware timestamp. 1 = yes. */
 400         } r_dh;
 401         struct {
 402                 u64 opcode:4;
 403                 u64 subcode:8;
 404                 u64 len:3;       /** additional 64-bit words */
 405                 u64 rid:13;      /** request id in response to pkt sent by host */
 406                 u64 num_gmx_ports:8;
 407                 u64 max_nic_ports:8;
 408                 u64 app_cap_flags:4;
 409                 u64 app_mode:16;
 410         } r_core_drv_init;
 411         struct {
 412                 u64 opcode:4;
 413                 u64 subcode:8;
 414                 u64 len:3;       /** additional 64-bit words */
 415                 u64 rid:13;
 416                 u64 reserved:4;
 417                 u64 extra:25;
 418                 u64 ifidx:7;
 419         } r_nic_info;
 420 #else
 421         u64 u64;
 422         struct {
 423                 u64 ossp:32;  /** opcode/subcode specific parameters */
 424                 u64 reserved:4;
 425                 u64 rid:13;   /** req id in response to pkt sent by host */
 426                 u64 len:3;    /** additional 64-bit words */
 427                 u64 subcode:8;
 428                 u64 opcode:4;
 429         } r;
 430         struct {
 431                 u64 has_hwtstamp:1;      /** 1 = has hwtstamp */
 432                 u64 csum_verified:3;     /** checksum verified. */
 433                 u64 link:8;
 434                 u64 extra:24;
 435                 u64 rid:13;   /** req id in response to pkt sent by host */
 436                 u64 len:3;    /** additional 64-bit words */
 437                 u64 subcode:8;
 438                 u64 opcode:4;
 439         } r_dh;
 440         struct {
 441                 u64 app_mode:16;
 442                 u64 app_cap_flags:4;
 443                 u64 max_nic_ports:8;
 444                 u64 num_gmx_ports:8;
 445                 u64 rid:13;
 446                 u64 len:3;       /** additional 64-bit words */
 447                 u64 subcode:8;
 448                 u64 opcode:4;
 449         } r_core_drv_init;
 450         struct {
 451                 u64 ifidx:7;
 452                 u64 extra:25;
 453                 u64 reserved:4;
 454                 u64 rid:13;
 455                 u64 len:3;       /** additional 64-bit words */
 456                 u64 subcode:8;
 457                 u64 opcode:4;
 458         } r_nic_info;
 459 #endif
 460 };
 461
 462 #define  OCT_RH_SIZE   (sizeof(union  octeon_rh))
 463
 464 #define OCT_PKT_PARAM_IPV4OPTS   1
 465 #define OCT_PKT_PARAM_IPV6EXTHDR 2
 466
 467 union octnic_packet_params {
 468         u32 u32;
 469         struct {
 470 #ifdef __BIG_ENDIAN_BITFIELD
 471                 u32 reserved:6;
 472                 u32 tnl_csum:1;
 473                 u32 ip_csum:1;
 474                 u32 ipv4opts_ipv6exthdr:2;
 475                 u32 ipsec_ops:4;
 476                 u32 tsflag:1;
 477                 u32 csoffset:9;
 478                 u32 ifidx:8;
 479 #else
 480                 u32 ifidx:8;
 481                 u32 csoffset:9;
 482                 u32 tsflag:1;
 483                 u32 ipsec_ops:4;
 484                 u32 ipv4opts_ipv6exthdr:2;
 485                 u32 ip_csum:1;
 486                 u32 tnl_csum:1;
 487                 u32 reserved:6;
 488 #endif
 489         } s;
 490 };
 491
 492 /** Status of a RGMII Link on Octeon as seen by core driver. */
 493 union oct_link_status {
 494         u64 u64;
 495
 496         struct {
 497 #ifdef __BIG_ENDIAN_BITFIELD
 498                 u64 duplex:8;
 499                 u64 status:8;
 500                 u64 mtu:16;
 501                 u64 speed:16;
 502                 u64 autoneg:1;
 503                 u64 interface:4;
 504                 u64 pause:1;
 505                 u64 reserved:10;
 506 #else
 507                 u64 reserved:10;
 508                 u64 pause:1;
 509                 u64 interface:4;
 510                 u64 autoneg:1;
 511                 u64 speed:16;
 512                 u64 mtu:16;
 513                 u64 status:8;
 514                 u64 duplex:8;
 515 #endif
 516         } s;
 517 };
 518
 519 /** Information for a OCTEON ethernet interface shared between core & host. */
 520 struct oct_link_info {
 521         union oct_link_status link;
 522         u64 hw_addr;
 523
 524 #ifdef __BIG_ENDIAN_BITFIELD
 525         u16 gmxport;
 526         u8 rsvd[3];
 527         u8 num_txpciq;
 528         u8 num_rxpciq;
 529         u8 ifidx;
 530 #else
 531         u8 ifidx;
 532         u8 num_rxpciq;
 533         u8 num_txpciq;
 534         u8 rsvd[3];
 535         u16 gmxport;
 536 #endif
 537
 538         u8 txpciq[MAX_IOQS_PER_NICIF];
 539         u8 rxpciq[MAX_IOQS_PER_NICIF];
 540 };
 541
 542 #define OCT_LINK_INFO_SIZE   (sizeof(struct oct_link_info))
 543
 544 struct liquidio_if_cfg_info {
 545         u64 ifidx;
 546         u64 iqmask; /** mask for IQs enabled for  the port */
 547         u64 oqmask; /** mask for OQs enabled for the port */
 548         struct oct_link_info linfo; /** initial link information */
 549 };
 550
 551 /** Stats for each NIC port in RX direction. */
 552 struct nic_rx_stats {
 553         /* link-level stats */
 554         u64 total_rcvd;
 555         u64 bytes_rcvd;
 556         u64 total_bcst;
 557         u64 total_mcst;
 558         u64 runts;
 559         u64 ctl_rcvd;
 560         u64 fifo_err;      /* Accounts for over/under-run of buffers */
 561         u64 dmac_drop;
 562         u64 fcs_err;
 563         u64 jabber_err;
 564         u64 l2_err;
 565         u64 frame_err;
 566
 567         /* firmware stats */
 568         u64 fw_total_rcvd;
 569         u64 fw_total_fwd;
 570         u64 fw_err_pko;
 571         u64 fw_err_link;
 572         u64 fw_err_drop;
 573         u64 fw_lro_pkts;   /* Number of packets that are LROed      */
 574         u64 fw_lro_octs;   /* Number of octets that are LROed       */
 575         u64 fw_total_lro;  /* Number of LRO packets formed          */
 576         u64 fw_lro_aborts; /* Number of times lRO of packet aborted */
 577         /* intrmod: packet forward rate */
 578         u64 fwd_rate;
 579 };
 580
 581 /** Stats for each NIC port in RX direction. */
 582 struct nic_tx_stats {
 583         /* link-level stats */
 584         u64 total_pkts_sent;
 585         u64 total_bytes_sent;
 586         u64 mcast_pkts_sent;
 587         u64 bcast_pkts_sent;
 588         u64 ctl_sent;
 589         u64 one_collision_sent;   /* Packets sent after one collision*/
 590         u64 multi_collision_sent; /* Packets sent after multiple collision*/
 591         u64 max_collision_fail;   /* Packets not sent due to max collisions */
 592         u64 max_deferral_fail;   /* Packets not sent due to max deferrals */
 593         u64 fifo_err;       /* Accounts for over/under-run of buffers */
 594         u64 runts;
 595         u64 total_collisions; /* Total number of collisions detected */
 596
 597         /* firmware stats */
 598         u64 fw_total_sent;
 599         u64 fw_total_fwd;
 600         u64 fw_err_pko;
 601         u64 fw_err_link;
 602         u64 fw_err_drop;
 603 };
 604
 605 struct oct_link_stats {
 606         struct nic_rx_stats fromwire;
 607         struct nic_tx_stats fromhost;
 608
 609 };
 610
 611 #define LIO68XX_LED_CTRL_ADDR     0x3501
 612 #define LIO68XX_LED_CTRL_CFGON    0x1f
 613 #define LIO68XX_LED_CTRL_CFGOFF   0x100
 614 #define LIO68XX_LED_BEACON_ADDR   0x3508
 615 #define LIO68XX_LED_BEACON_CFGON  0x47fd
 616 #define LIO68XX_LED_BEACON_CFGOFF 0x11fc
 617 #define VITESSE_PHY_GPIO_DRIVEON  0x1
 618 #define VITESSE_PHY_GPIO_CFG      0x8
 619 #define VITESSE_PHY_GPIO_DRIVEOFF 0x4
 620 #define VITESSE_PHY_GPIO_HIGH     0x2
 621 #define VITESSE_PHY_GPIO_LOW      0x3
 622
 623 struct oct_mdio_cmd {
 624         u64 op;
 625         u64 mdio_addr;
 626         u64 value1;
 627         u64 value2;
 628         u64 value3;
 629 };
 630
 631 #define OCT_LINK_STATS_SIZE   (sizeof(struct oct_link_stats))
 632
 633 #define LIO_INTRMOD_CHECK_INTERVAL  1
 634 #define LIO_INTRMOD_MAXPKT_RATETHR  196608 /* max pkt rate threshold */
 635 #define LIO_INTRMOD_MINPKT_RATETHR  9216   /* min pkt rate threshold */
 636 #define LIO_INTRMOD_MAXCNT_TRIGGER  384    /* max pkts to trigger interrupt */
 637 #define LIO_INTRMOD_MINCNT_TRIGGER  1      /* min pkts to trigger interrupt */
 638 #define LIO_INTRMOD_MAXTMR_TRIGGER  128    /* max time to trigger interrupt */
 639 #define LIO_INTRMOD_MINTMR_TRIGGER  32     /* min time to trigger interrupt */
 640
 641 struct oct_intrmod_cfg {
 642         u64 intrmod_enable;
 643         u64 intrmod_check_intrvl;
 644         u64 intrmod_maxpkt_ratethr;
 645         u64 intrmod_minpkt_ratethr;
 646         u64 intrmod_maxcnt_trigger;
 647         u64 intrmod_maxtmr_trigger;
 648         u64 intrmod_mincnt_trigger;
 649         u64 intrmod_mintmr_trigger;
 650 };
 651
 652 #define BASE_QUEUE_NOT_REQUESTED 65535
 653
 654 union oct_nic_if_cfg {
 655         u64 u64;
 656         struct {
 657 #ifdef __BIG_ENDIAN_BITFIELD
 658                 u64 base_queue:16;
 659                 u64 num_iqueues:16;
 660                 u64 num_oqueues:16;
 661                 u64 gmx_port_id:8;
 662                 u64 reserved:8;
 663 #else
 664                 u64 reserved:8;
 665                 u64 gmx_port_id:8;
 666                 u64 num_oqueues:16;
 667                 u64 num_iqueues:16;
 668                 u64 base_queue:16;
 669 #endif
 670         } s;
 671 };
 672
 673 #endif