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Merge branch 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
[deliverable/linux.git] / drivers / net / ethernet / cavium / liquidio / octeon_device.c
1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2015 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
22 #include <linux/version.h>
23 #include <linux/types.h>
24 #include <linux/list.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/crc32.h>
28 #include <linux/kthread.h>
29 #include <linux/netdevice.h>
30 #include <linux/vmalloc.h>
31 #include "octeon_config.h"
32 #include "liquidio_common.h"
33 #include "octeon_droq.h"
34 #include "octeon_iq.h"
35 #include "response_manager.h"
36 #include "octeon_device.h"
37 #include "octeon_nic.h"
38 #include "octeon_main.h"
39 #include "octeon_network.h"
40 #include "cn66xx_regs.h"
41 #include "cn66xx_device.h"
42 #include "cn68xx_regs.h"
43 #include "cn68xx_device.h"
44 #include "liquidio_image.h"
45 #include "octeon_mem_ops.h"
46
47 /** Default configuration
48 * for CN66XX OCTEON Models.
49 */
50 static struct octeon_config default_cn66xx_conf = {
51 .card_type = LIO_210SV,
52 .card_name = LIO_210SV_NAME,
53
54 /** IQ attributes */
55 .iq = {
56 .max_iqs = CN6XXX_CFG_IO_QUEUES,
57 .pending_list_size =
58 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
59 .instr_type = OCTEON_64BYTE_INSTR,
60 .db_min = CN6XXX_DB_MIN,
61 .db_timeout = CN6XXX_DB_TIMEOUT,
62 }
63 ,
64
65 /** OQ attributes */
66 .oq = {
67 .max_oqs = CN6XXX_CFG_IO_QUEUES,
68 .info_ptr = OCTEON_OQ_INFOPTR_MODE,
69 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
70 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
71 .oq_intr_time = CN6XXX_OQ_INTR_TIME,
72 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
73 }
74 ,
75
76 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_66XX,
77 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
78 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
79 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
80
81 /* For ethernet interface 0: Port cfg Attributes */
82 .nic_if_cfg[0] = {
83 /* Max Txqs: Half for each of the two ports :max_iq/2 */
84 .max_txqs = MAX_TXQS_PER_INTF,
85
86 /* Actual configured value. Range could be: 1...max_txqs */
87 .num_txqs = DEF_TXQS_PER_INTF,
88
89 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
90 .max_rxqs = MAX_RXQS_PER_INTF,
91
92 /* Actual configured value. Range could be: 1...max_rxqs */
93 .num_rxqs = DEF_RXQS_PER_INTF,
94
95 /* Num of desc for rx rings */
96 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
97
98 /* Num of desc for tx rings */
99 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
100
101 /* SKB size, We need not change buf size even for Jumbo frames.
102 * Octeon can send jumbo frames in 4 consecutive descriptors,
103 */
104 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
105
106 .base_queue = BASE_QUEUE_NOT_REQUESTED,
107
108 .gmx_port_id = 0,
109 },
110
111 .nic_if_cfg[1] = {
112 /* Max Txqs: Half for each of the two ports :max_iq/2 */
113 .max_txqs = MAX_TXQS_PER_INTF,
114
115 /* Actual configured value. Range could be: 1...max_txqs */
116 .num_txqs = DEF_TXQS_PER_INTF,
117
118 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
119 .max_rxqs = MAX_RXQS_PER_INTF,
120
121 /* Actual configured value. Range could be: 1...max_rxqs */
122 .num_rxqs = DEF_RXQS_PER_INTF,
123
124 /* Num of desc for rx rings */
125 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
126
127 /* Num of desc for tx rings */
128 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
129
130 /* SKB size, We need not change buf size even for Jumbo frames.
131 * Octeon can send jumbo frames in 4 consecutive descriptors,
132 */
133 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
134
135 .base_queue = BASE_QUEUE_NOT_REQUESTED,
136
137 .gmx_port_id = 1,
138 },
139
140 /** Miscellaneous attributes */
141 .misc = {
142 /* Host driver link query interval */
143 .oct_link_query_interval = 100,
144
145 /* Octeon link query interval */
146 .host_link_query_interval = 500,
147
148 .enable_sli_oq_bp = 0,
149
150 /* Control queue group */
151 .ctrlq_grp = 1,
152 }
153 ,
154 };
155
156 /** Default configuration
157 * for CN68XX OCTEON Model.
158 */
159
160 static struct octeon_config default_cn68xx_conf = {
161 .card_type = LIO_410NV,
162 .card_name = LIO_410NV_NAME,
163
164 /** IQ attributes */
165 .iq = {
166 .max_iqs = CN6XXX_CFG_IO_QUEUES,
167 .pending_list_size =
168 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
169 .instr_type = OCTEON_64BYTE_INSTR,
170 .db_min = CN6XXX_DB_MIN,
171 .db_timeout = CN6XXX_DB_TIMEOUT,
172 }
173 ,
174
175 /** OQ attributes */
176 .oq = {
177 .max_oqs = CN6XXX_CFG_IO_QUEUES,
178 .info_ptr = OCTEON_OQ_INFOPTR_MODE,
179 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
180 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
181 .oq_intr_time = CN6XXX_OQ_INTR_TIME,
182 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
183 }
184 ,
185
186 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX,
187 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
188 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
189 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
190
191 .nic_if_cfg[0] = {
192 /* Max Txqs: Half for each of the two ports :max_iq/2 */
193 .max_txqs = MAX_TXQS_PER_INTF,
194
195 /* Actual configured value. Range could be: 1...max_txqs */
196 .num_txqs = DEF_TXQS_PER_INTF,
197
198 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
199 .max_rxqs = MAX_RXQS_PER_INTF,
200
201 /* Actual configured value. Range could be: 1...max_rxqs */
202 .num_rxqs = DEF_RXQS_PER_INTF,
203
204 /* Num of desc for rx rings */
205 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
206
207 /* Num of desc for tx rings */
208 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
209
210 /* SKB size, We need not change buf size even for Jumbo frames.
211 * Octeon can send jumbo frames in 4 consecutive descriptors,
212 */
213 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
214
215 .base_queue = BASE_QUEUE_NOT_REQUESTED,
216
217 .gmx_port_id = 0,
218 },
219
220 .nic_if_cfg[1] = {
221 /* Max Txqs: Half for each of the two ports :max_iq/2 */
222 .max_txqs = MAX_TXQS_PER_INTF,
223
224 /* Actual configured value. Range could be: 1...max_txqs */
225 .num_txqs = DEF_TXQS_PER_INTF,
226
227 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
228 .max_rxqs = MAX_RXQS_PER_INTF,
229
230 /* Actual configured value. Range could be: 1...max_rxqs */
231 .num_rxqs = DEF_RXQS_PER_INTF,
232
233 /* Num of desc for rx rings */
234 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
235
236 /* Num of desc for tx rings */
237 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
238
239 /* SKB size, We need not change buf size even for Jumbo frames.
240 * Octeon can send jumbo frames in 4 consecutive descriptors,
241 */
242 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
243
244 .base_queue = BASE_QUEUE_NOT_REQUESTED,
245
246 .gmx_port_id = 1,
247 },
248
249 .nic_if_cfg[2] = {
250 /* Max Txqs: Half for each of the two ports :max_iq/2 */
251 .max_txqs = MAX_TXQS_PER_INTF,
252
253 /* Actual configured value. Range could be: 1...max_txqs */
254 .num_txqs = DEF_TXQS_PER_INTF,
255
256 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
257 .max_rxqs = MAX_RXQS_PER_INTF,
258
259 /* Actual configured value. Range could be: 1...max_rxqs */
260 .num_rxqs = DEF_RXQS_PER_INTF,
261
262 /* Num of desc for rx rings */
263 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
264
265 /* Num of desc for tx rings */
266 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
267
268 /* SKB size, We need not change buf size even for Jumbo frames.
269 * Octeon can send jumbo frames in 4 consecutive descriptors,
270 */
271 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
272
273 .base_queue = BASE_QUEUE_NOT_REQUESTED,
274
275 .gmx_port_id = 2,
276 },
277
278 .nic_if_cfg[3] = {
279 /* Max Txqs: Half for each of the two ports :max_iq/2 */
280 .max_txqs = MAX_TXQS_PER_INTF,
281
282 /* Actual configured value. Range could be: 1...max_txqs */
283 .num_txqs = DEF_TXQS_PER_INTF,
284
285 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
286 .max_rxqs = MAX_RXQS_PER_INTF,
287
288 /* Actual configured value. Range could be: 1...max_rxqs */
289 .num_rxqs = DEF_RXQS_PER_INTF,
290
291 /* Num of desc for rx rings */
292 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
293
294 /* Num of desc for tx rings */
295 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
296
297 /* SKB size, We need not change buf size even for Jumbo frames.
298 * Octeon can send jumbo frames in 4 consecutive descriptors,
299 */
300 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
301
302 .base_queue = BASE_QUEUE_NOT_REQUESTED,
303
304 .gmx_port_id = 3,
305 },
306
307 /** Miscellaneous attributes */
308 .misc = {
309 /* Host driver link query interval */
310 .oct_link_query_interval = 100,
311
312 /* Octeon link query interval */
313 .host_link_query_interval = 500,
314
315 .enable_sli_oq_bp = 0,
316
317 /* Control queue group */
318 .ctrlq_grp = 1,
319 }
320 ,
321 };
322
323 /** Default configuration
324 * for CN68XX OCTEON Model.
325 */
326 static struct octeon_config default_cn68xx_210nv_conf = {
327 .card_type = LIO_210NV,
328 .card_name = LIO_210NV_NAME,
329
330 /** IQ attributes */
331
332 .iq = {
333 .max_iqs = CN6XXX_CFG_IO_QUEUES,
334 .pending_list_size =
335 (CN6XXX_MAX_IQ_DESCRIPTORS * CN6XXX_CFG_IO_QUEUES),
336 .instr_type = OCTEON_64BYTE_INSTR,
337 .db_min = CN6XXX_DB_MIN,
338 .db_timeout = CN6XXX_DB_TIMEOUT,
339 }
340 ,
341
342 /** OQ attributes */
343 .oq = {
344 .max_oqs = CN6XXX_CFG_IO_QUEUES,
345 .info_ptr = OCTEON_OQ_INFOPTR_MODE,
346 .refill_threshold = CN6XXX_OQ_REFIL_THRESHOLD,
347 .oq_intr_pkt = CN6XXX_OQ_INTR_PKT,
348 .oq_intr_time = CN6XXX_OQ_INTR_TIME,
349 .pkts_per_intr = CN6XXX_OQ_PKTSPER_INTR,
350 }
351 ,
352
353 .num_nic_ports = DEFAULT_NUM_NIC_PORTS_68XX_210NV,
354 .num_def_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
355 .num_def_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
356 .def_rx_buf_size = CN6XXX_OQ_BUF_SIZE,
357
358 .nic_if_cfg[0] = {
359 /* Max Txqs: Half for each of the two ports :max_iq/2 */
360 .max_txqs = MAX_TXQS_PER_INTF,
361
362 /* Actual configured value. Range could be: 1...max_txqs */
363 .num_txqs = DEF_TXQS_PER_INTF,
364
365 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
366 .max_rxqs = MAX_RXQS_PER_INTF,
367
368 /* Actual configured value. Range could be: 1...max_rxqs */
369 .num_rxqs = DEF_RXQS_PER_INTF,
370
371 /* Num of desc for rx rings */
372 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
373
374 /* Num of desc for tx rings */
375 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
376
377 /* SKB size, We need not change buf size even for Jumbo frames.
378 * Octeon can send jumbo frames in 4 consecutive descriptors,
379 */
380 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
381
382 .base_queue = BASE_QUEUE_NOT_REQUESTED,
383
384 .gmx_port_id = 0,
385 },
386
387 .nic_if_cfg[1] = {
388 /* Max Txqs: Half for each of the two ports :max_iq/2 */
389 .max_txqs = MAX_TXQS_PER_INTF,
390
391 /* Actual configured value. Range could be: 1...max_txqs */
392 .num_txqs = DEF_TXQS_PER_INTF,
393
394 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
395 .max_rxqs = MAX_RXQS_PER_INTF,
396
397 /* Actual configured value. Range could be: 1...max_rxqs */
398 .num_rxqs = DEF_RXQS_PER_INTF,
399
400 /* Num of desc for rx rings */
401 .num_rx_descs = CN6XXX_MAX_OQ_DESCRIPTORS,
402
403 /* Num of desc for tx rings */
404 .num_tx_descs = CN6XXX_MAX_IQ_DESCRIPTORS,
405
406 /* SKB size, We need not change buf size even for Jumbo frames.
407 * Octeon can send jumbo frames in 4 consecutive descriptors,
408 */
409 .rx_buf_size = CN6XXX_OQ_BUF_SIZE,
410
411 .base_queue = BASE_QUEUE_NOT_REQUESTED,
412
413 .gmx_port_id = 1,
414 },
415
416 /** Miscellaneous attributes */
417 .misc = {
418 /* Host driver link query interval */
419 .oct_link_query_interval = 100,
420
421 /* Octeon link query interval */
422 .host_link_query_interval = 500,
423
424 .enable_sli_oq_bp = 0,
425
426 /* Control queue group */
427 .ctrlq_grp = 1,
428 }
429 ,
430 };
431
432 enum {
433 OCTEON_CONFIG_TYPE_DEFAULT = 0,
434 NUM_OCTEON_CONFS,
435 };
436
437 static struct octeon_config_ptr {
438 u32 conf_type;
439 } oct_conf_info[MAX_OCTEON_DEVICES] = {
440 {
441 OCTEON_CONFIG_TYPE_DEFAULT,
442 }, {
443 OCTEON_CONFIG_TYPE_DEFAULT,
444 }, {
445 OCTEON_CONFIG_TYPE_DEFAULT,
446 }, {
447 OCTEON_CONFIG_TYPE_DEFAULT,
448 },
449 };
450
451 static char oct_dev_state_str[OCT_DEV_STATES + 1][32] = {
452 "BEGIN", "PCI-MAP-DONE", "DISPATCH-INIT-DONE",
453 "IQ-INIT-DONE", "SCBUFF-POOL-INIT-DONE", "RESPLIST-INIT-DONE",
454 "DROQ-INIT-DONE", "IO-QUEUES-INIT-DONE", "CONSOLE-INIT-DONE",
455 "HOST-READY", "CORE-READY", "RUNNING", "IN-RESET",
456 "INVALID"
457 };
458
459 static char oct_dev_app_str[CVM_DRV_APP_COUNT + 1][32] = {
460 "BASE", "NIC", "UNKNOWN"};
461
462 static struct octeon_device *octeon_device[MAX_OCTEON_DEVICES];
463 static u32 octeon_device_count;
464
465 static struct octeon_core_setup core_setup[MAX_OCTEON_DEVICES];
466
467 static void oct_set_config_info(int oct_id, int conf_type)
468 {
469 if (conf_type < 0 || conf_type > (NUM_OCTEON_CONFS - 1))
470 conf_type = OCTEON_CONFIG_TYPE_DEFAULT;
471 oct_conf_info[oct_id].conf_type = conf_type;
472 }
473
474 void octeon_init_device_list(int conf_type)
475 {
476 int i;
477
478 memset(octeon_device, 0, (sizeof(void *) * MAX_OCTEON_DEVICES));
479 for (i = 0; i < MAX_OCTEON_DEVICES; i++)
480 oct_set_config_info(i, conf_type);
481 }
482
483 static void *__retrieve_octeon_config_info(struct octeon_device *oct,
484 u16 card_type)
485 {
486 u32 oct_id = oct->octeon_id;
487 void *ret = NULL;
488
489 switch (oct_conf_info[oct_id].conf_type) {
490 case OCTEON_CONFIG_TYPE_DEFAULT:
491 if (oct->chip_id == OCTEON_CN66XX) {
492 ret = (void *)&default_cn66xx_conf;
493 } else if ((oct->chip_id == OCTEON_CN68XX) &&
494 (card_type == LIO_210NV)) {
495 ret = (void *)&default_cn68xx_210nv_conf;
496 } else if ((oct->chip_id == OCTEON_CN68XX) &&
497 (card_type == LIO_410NV)) {
498 ret = (void *)&default_cn68xx_conf;
499 }
500 break;
501 default:
502 break;
503 }
504 return ret;
505 }
506
507 static int __verify_octeon_config_info(struct octeon_device *oct, void *conf)
508 {
509 switch (oct->chip_id) {
510 case OCTEON_CN66XX:
511 case OCTEON_CN68XX:
512 return lio_validate_cn6xxx_config_info(oct, conf);
513
514 default:
515 break;
516 }
517
518 return 1;
519 }
520
521 void *oct_get_config_info(struct octeon_device *oct, u16 card_type)
522 {
523 void *conf = NULL;
524
525 conf = __retrieve_octeon_config_info(oct, card_type);
526 if (!conf)
527 return NULL;
528
529 if (__verify_octeon_config_info(oct, conf)) {
530 dev_err(&oct->pci_dev->dev, "Configuration verification failed\n");
531 return NULL;
532 }
533
534 return conf;
535 }
536
537 char *lio_get_state_string(atomic_t *state_ptr)
538 {
539 s32 istate = (s32)atomic_read(state_ptr);
540
541 if (istate > OCT_DEV_STATES || istate < 0)
542 return oct_dev_state_str[OCT_DEV_STATE_INVALID];
543 return oct_dev_state_str[istate];
544 }
545
546 static char *get_oct_app_string(u32 app_mode)
547 {
548 if (app_mode <= CVM_DRV_APP_END)
549 return oct_dev_app_str[app_mode - CVM_DRV_APP_START];
550 return oct_dev_app_str[CVM_DRV_INVALID_APP - CVM_DRV_APP_START];
551 }
552
553 int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
554 size_t size)
555 {
556 int ret = 0;
557 u8 *p;
558 u8 *buffer;
559 u32 crc32_result;
560 u64 load_addr;
561 u32 image_len;
562 struct octeon_firmware_file_header *h;
563 u32 i;
564
565 if (size < sizeof(struct octeon_firmware_file_header)) {
566 dev_err(&oct->pci_dev->dev, "Firmware file too small (%d < %d).\n",
567 (u32)size,
568 (u32)sizeof(struct octeon_firmware_file_header));
569 return -EINVAL;
570 }
571
572 h = (struct octeon_firmware_file_header *)data;
573
574 if (be32_to_cpu(h->magic) != LIO_NIC_MAGIC) {
575 dev_err(&oct->pci_dev->dev, "Unrecognized firmware file.\n");
576 return -EINVAL;
577 }
578
579 crc32_result =
580 crc32(~0, data,
581 sizeof(struct octeon_firmware_file_header) -
582 sizeof(u32)) ^ ~0U;
583 if (crc32_result != be32_to_cpu(h->crc32)) {
584 dev_err(&oct->pci_dev->dev, "Firmware CRC mismatch (0x%08x != 0x%08x).\n",
585 crc32_result, be32_to_cpu(h->crc32));
586 return -EINVAL;
587 }
588
589 if (memcmp(LIQUIDIO_VERSION, h->version, strlen(LIQUIDIO_VERSION))) {
590 dev_err(&oct->pci_dev->dev, "Unmatched firmware version. Expected %s, got %s.\n",
591 LIQUIDIO_VERSION, h->version);
592 return -EINVAL;
593 }
594
595 if (be32_to_cpu(h->num_images) > LIO_MAX_IMAGES) {
596 dev_err(&oct->pci_dev->dev, "Too many images in firmware file (%d).\n",
597 be32_to_cpu(h->num_images));
598 return -EINVAL;
599 }
600
601 dev_info(&oct->pci_dev->dev, "Firmware version: %s\n", h->version);
602 snprintf(oct->fw_info.liquidio_firmware_version, 32, "LIQUIDIO: %s",
603 h->version);
604
605 buffer = kmemdup(data, size, GFP_KERNEL);
606 if (!buffer)
607 return -ENOMEM;
608
609 p = buffer + sizeof(struct octeon_firmware_file_header);
610
611 /* load all images */
612 for (i = 0; i < be32_to_cpu(h->num_images); i++) {
613 load_addr = be64_to_cpu(h->desc[i].addr);
614 image_len = be32_to_cpu(h->desc[i].len);
615
616 /* validate the image */
617 crc32_result = crc32(~0, p, image_len) ^ ~0U;
618 if (crc32_result != be32_to_cpu(h->desc[i].crc32)) {
619 dev_err(&oct->pci_dev->dev,
620 "Firmware CRC mismatch in image %d (0x%08x != 0x%08x).\n",
621 i, crc32_result,
622 be32_to_cpu(h->desc[i].crc32));
623 ret = -EINVAL;
624 goto done_downloading;
625 }
626
627 /* download the image */
628 octeon_pci_write_core_mem(oct, load_addr, p, image_len);
629
630 p += image_len;
631 dev_dbg(&oct->pci_dev->dev,
632 "Downloaded image %d (%d bytes) to address 0x%016llx\n",
633 i, image_len, load_addr);
634 }
635
636 /* Invoke the bootcmd */
637 ret = octeon_console_send_cmd(oct, h->bootcmd, 50);
638
639 done_downloading:
640 kfree(buffer);
641
642 return ret;
643 }
644
645 void octeon_free_device_mem(struct octeon_device *oct)
646 {
647 u32 i;
648
649 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES; i++) {
650 /* could check mask as well */
651 vfree(oct->droq[i]);
652 }
653
654 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES; i++) {
655 /* could check mask as well */
656 vfree(oct->instr_queue[i]);
657 }
658
659 i = oct->octeon_id;
660 vfree(oct);
661
662 octeon_device[i] = NULL;
663 octeon_device_count--;
664 }
665
666 static struct octeon_device *octeon_allocate_device_mem(u32 pci_id,
667 u32 priv_size)
668 {
669 struct octeon_device *oct;
670 u8 *buf = NULL;
671 u32 octdevsize = 0, configsize = 0, size;
672
673 switch (pci_id) {
674 case OCTEON_CN68XX:
675 case OCTEON_CN66XX:
676 configsize = sizeof(struct octeon_cn6xxx);
677 break;
678
679 default:
680 pr_err("%s: Unknown PCI Device: 0x%x\n",
681 __func__,
682 pci_id);
683 return NULL;
684 }
685
686 if (configsize & 0x7)
687 configsize += (8 - (configsize & 0x7));
688
689 octdevsize = sizeof(struct octeon_device);
690 if (octdevsize & 0x7)
691 octdevsize += (8 - (octdevsize & 0x7));
692
693 if (priv_size & 0x7)
694 priv_size += (8 - (priv_size & 0x7));
695
696 size = octdevsize + priv_size + configsize +
697 (sizeof(struct octeon_dispatch) * DISPATCH_LIST_SIZE);
698
699 buf = vmalloc(size);
700 if (!buf)
701 return NULL;
702
703 memset(buf, 0, size);
704
705 oct = (struct octeon_device *)buf;
706 oct->priv = (void *)(buf + octdevsize);
707 oct->chip = (void *)(buf + octdevsize + priv_size);
708 oct->dispatch.dlist = (struct octeon_dispatch *)
709 (buf + octdevsize + priv_size + configsize);
710
711 return oct;
712 }
713
714 struct octeon_device *octeon_allocate_device(u32 pci_id,
715 u32 priv_size)
716 {
717 u32 oct_idx = 0;
718 struct octeon_device *oct = NULL;
719
720 for (oct_idx = 0; oct_idx < MAX_OCTEON_DEVICES; oct_idx++)
721 if (!octeon_device[oct_idx])
722 break;
723
724 if (oct_idx == MAX_OCTEON_DEVICES)
725 return NULL;
726
727 oct = octeon_allocate_device_mem(pci_id, priv_size);
728 if (!oct)
729 return NULL;
730
731 spin_lock_init(&oct->pci_win_lock);
732 spin_lock_init(&oct->mem_access_lock);
733
734 octeon_device_count++;
735 octeon_device[oct_idx] = oct;
736
737 oct->octeon_id = oct_idx;
738 snprintf((oct->device_name), sizeof(oct->device_name),
739 "LiquidIO%d", (oct->octeon_id));
740
741 return oct;
742 }
743
744 int octeon_setup_instr_queues(struct octeon_device *oct)
745 {
746 u32 i, num_iqs = 0;
747 u32 num_descs = 0;
748
749 /* this causes queue 0 to be default queue */
750 if (OCTEON_CN6XXX(oct)) {
751 num_iqs = 1;
752 num_descs =
753 CFG_GET_NUM_DEF_TX_DESCS(CHIP_FIELD(oct, cn6xxx, conf));
754 }
755
756 oct->num_iqs = 0;
757
758 for (i = 0; i < num_iqs; i++) {
759 oct->instr_queue[i] =
760 vmalloc(sizeof(struct octeon_instr_queue));
761 if (!oct->instr_queue[i])
762 return 1;
763
764 memset(oct->instr_queue[i], 0,
765 sizeof(struct octeon_instr_queue));
766
767 oct->instr_queue[i]->app_ctx = (void *)(size_t)i;
768 if (octeon_init_instr_queue(oct, i, num_descs))
769 return 1;
770
771 oct->num_iqs++;
772 }
773
774 return 0;
775 }
776
777 int octeon_setup_output_queues(struct octeon_device *oct)
778 {
779 u32 i, num_oqs = 0;
780 u32 num_descs = 0;
781 u32 desc_size = 0;
782
783 /* this causes queue 0 to be default queue */
784 if (OCTEON_CN6XXX(oct)) {
785 /* CFG_GET_OQ_MAX_BASE_Q(CHIP_FIELD(oct, cn6xxx, conf)); */
786 num_oqs = 1;
787 num_descs =
788 CFG_GET_NUM_DEF_RX_DESCS(CHIP_FIELD(oct, cn6xxx, conf));
789 desc_size =
790 CFG_GET_DEF_RX_BUF_SIZE(CHIP_FIELD(oct, cn6xxx, conf));
791 }
792
793 oct->num_oqs = 0;
794
795 for (i = 0; i < num_oqs; i++) {
796 oct->droq[i] = vmalloc(sizeof(*oct->droq[i]));
797 if (!oct->droq[i])
798 return 1;
799
800 memset(oct->droq[i], 0, sizeof(struct octeon_droq));
801
802 if (octeon_init_droq(oct, i, num_descs, desc_size, NULL))
803 return 1;
804
805 oct->num_oqs++;
806 }
807
808 return 0;
809 }
810
811 void octeon_set_io_queues_off(struct octeon_device *oct)
812 {
813 /* Disable the i/p and o/p queues for this Octeon. */
814
815 octeon_write_csr(oct, CN6XXX_SLI_PKT_INSTR_ENB, 0);
816 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, 0);
817 }
818
819 void octeon_set_droq_pkt_op(struct octeon_device *oct,
820 u32 q_no,
821 u32 enable)
822 {
823 u32 reg_val = 0;
824
825 /* Disable the i/p and o/p queues for this Octeon. */
826 reg_val = octeon_read_csr(oct, CN6XXX_SLI_PKT_OUT_ENB);
827
828 if (enable)
829 reg_val = reg_val | (1 << q_no);
830 else
831 reg_val = reg_val & (~(1 << q_no));
832
833 octeon_write_csr(oct, CN6XXX_SLI_PKT_OUT_ENB, reg_val);
834 }
835
836 int octeon_init_dispatch_list(struct octeon_device *oct)
837 {
838 u32 i;
839
840 oct->dispatch.count = 0;
841
842 for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
843 oct->dispatch.dlist[i].opcode = 0;
844 INIT_LIST_HEAD(&oct->dispatch.dlist[i].list);
845 }
846
847 for (i = 0; i <= REQTYPE_LAST; i++)
848 octeon_register_reqtype_free_fn(oct, i, NULL);
849
850 spin_lock_init(&oct->dispatch.lock);
851
852 return 0;
853 }
854
855 void octeon_delete_dispatch_list(struct octeon_device *oct)
856 {
857 u32 i;
858 struct list_head freelist, *temp, *tmp2;
859
860 INIT_LIST_HEAD(&freelist);
861
862 spin_lock_bh(&oct->dispatch.lock);
863
864 for (i = 0; i < DISPATCH_LIST_SIZE; i++) {
865 struct list_head *dispatch;
866
867 dispatch = &oct->dispatch.dlist[i].list;
868 while (dispatch->next != dispatch) {
869 temp = dispatch->next;
870 list_del(temp);
871 list_add_tail(temp, &freelist);
872 }
873
874 oct->dispatch.dlist[i].opcode = 0;
875 }
876
877 oct->dispatch.count = 0;
878
879 spin_unlock_bh(&oct->dispatch.lock);
880
881 list_for_each_safe(temp, tmp2, &freelist) {
882 list_del(temp);
883 vfree(temp);
884 }
885 }
886
887 octeon_dispatch_fn_t
888 octeon_get_dispatch(struct octeon_device *octeon_dev, u16 opcode,
889 u16 subcode)
890 {
891 u32 idx;
892 struct list_head *dispatch;
893 octeon_dispatch_fn_t fn = NULL;
894 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
895
896 idx = combined_opcode & OCTEON_OPCODE_MASK;
897
898 spin_lock_bh(&octeon_dev->dispatch.lock);
899
900 if (octeon_dev->dispatch.count == 0) {
901 spin_unlock_bh(&octeon_dev->dispatch.lock);
902 return NULL;
903 }
904
905 if (!(octeon_dev->dispatch.dlist[idx].opcode)) {
906 spin_unlock_bh(&octeon_dev->dispatch.lock);
907 return NULL;
908 }
909
910 if (octeon_dev->dispatch.dlist[idx].opcode == combined_opcode) {
911 fn = octeon_dev->dispatch.dlist[idx].dispatch_fn;
912 } else {
913 list_for_each(dispatch,
914 &octeon_dev->dispatch.dlist[idx].list) {
915 if (((struct octeon_dispatch *)dispatch)->opcode ==
916 combined_opcode) {
917 fn = ((struct octeon_dispatch *)
918 dispatch)->dispatch_fn;
919 break;
920 }
921 }
922 }
923
924 spin_unlock_bh(&octeon_dev->dispatch.lock);
925 return fn;
926 }
927
928 /* octeon_register_dispatch_fn
929 * Parameters:
930 * octeon_id - id of the octeon device.
931 * opcode - opcode for which driver should call the registered function
932 * subcode - subcode for which driver should call the registered function
933 * fn - The function to call when a packet with "opcode" arrives in
934 * octeon output queues.
935 * fn_arg - The argument to be passed when calling function "fn".
936 * Description:
937 * Registers a function and its argument to be called when a packet
938 * arrives in Octeon output queues with "opcode".
939 * Returns:
940 * Success: 0
941 * Failure: 1
942 * Locks:
943 * No locks are held.
944 */
945 int
946 octeon_register_dispatch_fn(struct octeon_device *oct,
947 u16 opcode,
948 u16 subcode,
949 octeon_dispatch_fn_t fn, void *fn_arg)
950 {
951 u32 idx;
952 octeon_dispatch_fn_t pfn;
953 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
954
955 idx = combined_opcode & OCTEON_OPCODE_MASK;
956
957 spin_lock_bh(&oct->dispatch.lock);
958 /* Add dispatch function to first level of lookup table */
959 if (oct->dispatch.dlist[idx].opcode == 0) {
960 oct->dispatch.dlist[idx].opcode = combined_opcode;
961 oct->dispatch.dlist[idx].dispatch_fn = fn;
962 oct->dispatch.dlist[idx].arg = fn_arg;
963 oct->dispatch.count++;
964 spin_unlock_bh(&oct->dispatch.lock);
965 return 0;
966 }
967
968 spin_unlock_bh(&oct->dispatch.lock);
969
970 /* Check if there was a function already registered for this
971 * opcode/subcode.
972 */
973 pfn = octeon_get_dispatch(oct, opcode, subcode);
974 if (!pfn) {
975 struct octeon_dispatch *dispatch;
976
977 dev_dbg(&oct->pci_dev->dev,
978 "Adding opcode to dispatch list linked list\n");
979 dispatch = (struct octeon_dispatch *)
980 vmalloc(sizeof(struct octeon_dispatch));
981 if (!dispatch) {
982 dev_err(&oct->pci_dev->dev,
983 "No memory to add dispatch function\n");
984 return 1;
985 }
986 dispatch->opcode = combined_opcode;
987 dispatch->dispatch_fn = fn;
988 dispatch->arg = fn_arg;
989
990 /* Add dispatch function to linked list of fn ptrs
991 * at the hashed index.
992 */
993 spin_lock_bh(&oct->dispatch.lock);
994 list_add(&dispatch->list, &oct->dispatch.dlist[idx].list);
995 oct->dispatch.count++;
996 spin_unlock_bh(&oct->dispatch.lock);
997
998 } else {
999 dev_err(&oct->pci_dev->dev,
1000 "Found previously registered dispatch fn for opcode/subcode: %x/%x\n",
1001 opcode, subcode);
1002 return 1;
1003 }
1004
1005 return 0;
1006 }
1007
1008 /* octeon_unregister_dispatch_fn
1009 * Parameters:
1010 * oct - octeon device
1011 * opcode - driver should unregister the function for this opcode
1012 * subcode - driver should unregister the function for this subcode
1013 * Description:
1014 * Unregister the function set for this opcode+subcode.
1015 * Returns:
1016 * Success: 0
1017 * Failure: 1
1018 * Locks:
1019 * No locks are held.
1020 */
1021 int
1022 octeon_unregister_dispatch_fn(struct octeon_device *oct, u16 opcode,
1023 u16 subcode)
1024 {
1025 int retval = 0;
1026 u32 idx;
1027 struct list_head *dispatch, *dfree = NULL, *tmp2;
1028 u16 combined_opcode = OPCODE_SUBCODE(opcode, subcode);
1029
1030 idx = combined_opcode & OCTEON_OPCODE_MASK;
1031
1032 spin_lock_bh(&oct->dispatch.lock);
1033
1034 if (oct->dispatch.count == 0) {
1035 spin_unlock_bh(&oct->dispatch.lock);
1036 dev_err(&oct->pci_dev->dev,
1037 "No dispatch functions registered for this device\n");
1038 return 1;
1039 }
1040
1041 if (oct->dispatch.dlist[idx].opcode == combined_opcode) {
1042 dispatch = &oct->dispatch.dlist[idx].list;
1043 if (dispatch->next != dispatch) {
1044 dispatch = dispatch->next;
1045 oct->dispatch.dlist[idx].opcode =
1046 ((struct octeon_dispatch *)dispatch)->opcode;
1047 oct->dispatch.dlist[idx].dispatch_fn =
1048 ((struct octeon_dispatch *)
1049 dispatch)->dispatch_fn;
1050 oct->dispatch.dlist[idx].arg =
1051 ((struct octeon_dispatch *)dispatch)->arg;
1052 list_del(dispatch);
1053 dfree = dispatch;
1054 } else {
1055 oct->dispatch.dlist[idx].opcode = 0;
1056 oct->dispatch.dlist[idx].dispatch_fn = NULL;
1057 oct->dispatch.dlist[idx].arg = NULL;
1058 }
1059 } else {
1060 retval = 1;
1061 list_for_each_safe(dispatch, tmp2,
1062 &(oct->dispatch.dlist[idx].
1063 list)) {
1064 if (((struct octeon_dispatch *)dispatch)->opcode ==
1065 combined_opcode) {
1066 list_del(dispatch);
1067 dfree = dispatch;
1068 retval = 0;
1069 }
1070 }
1071 }
1072
1073 if (!retval)
1074 oct->dispatch.count--;
1075
1076 spin_unlock_bh(&oct->dispatch.lock);
1077 vfree(dfree);
1078 return retval;
1079 }
1080
1081 int octeon_core_drv_init(struct octeon_recv_info *recv_info, void *buf)
1082 {
1083 u32 i;
1084 char app_name[16];
1085 struct octeon_device *oct = (struct octeon_device *)buf;
1086 struct octeon_recv_pkt *recv_pkt = recv_info->recv_pkt;
1087 struct octeon_core_setup *cs = NULL;
1088 u32 num_nic_ports = 0;
1089
1090 if (OCTEON_CN6XXX(oct))
1091 num_nic_ports =
1092 CFG_GET_NUM_NIC_PORTS(CHIP_FIELD(oct, cn6xxx, conf));
1093
1094 if (atomic_read(&oct->status) >= OCT_DEV_RUNNING) {
1095 dev_err(&oct->pci_dev->dev, "Received CORE OK when device state is 0x%x\n",
1096 atomic_read(&oct->status));
1097 goto core_drv_init_err;
1098 }
1099
1100 strncpy(app_name,
1101 get_oct_app_string(
1102 (u32)recv_pkt->rh.r_core_drv_init.app_mode),
1103 sizeof(app_name) - 1);
1104 oct->app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1105 if (recv_pkt->rh.r_core_drv_init.app_mode == CVM_DRV_NIC_APP) {
1106 oct->fw_info.max_nic_ports =
1107 (u32)recv_pkt->rh.r_core_drv_init.max_nic_ports;
1108 oct->fw_info.num_gmx_ports =
1109 (u32)recv_pkt->rh.r_core_drv_init.num_gmx_ports;
1110 }
1111
1112 if (oct->fw_info.max_nic_ports < num_nic_ports) {
1113 dev_err(&oct->pci_dev->dev,
1114 "Config has more ports than firmware allows (%d > %d).\n",
1115 num_nic_ports, oct->fw_info.max_nic_ports);
1116 goto core_drv_init_err;
1117 }
1118 oct->fw_info.app_cap_flags = recv_pkt->rh.r_core_drv_init.app_cap_flags;
1119 oct->fw_info.app_mode = (u32)recv_pkt->rh.r_core_drv_init.app_mode;
1120
1121 atomic_set(&oct->status, OCT_DEV_CORE_OK);
1122
1123 cs = &core_setup[oct->octeon_id];
1124
1125 if (recv_pkt->buffer_size[0] != sizeof(*cs)) {
1126 dev_dbg(&oct->pci_dev->dev, "Core setup bytes expected %u found %d\n",
1127 (u32)sizeof(*cs),
1128 recv_pkt->buffer_size[0]);
1129 }
1130
1131 memcpy(cs, get_rbd(recv_pkt->buffer_ptr[0]), sizeof(*cs));
1132 strncpy(oct->boardinfo.name, cs->boardname, OCT_BOARD_NAME);
1133 strncpy(oct->boardinfo.serial_number, cs->board_serial_number,
1134 OCT_SERIAL_LEN);
1135
1136 octeon_swap_8B_data((u64 *)cs, (sizeof(*cs) >> 3));
1137
1138 oct->boardinfo.major = cs->board_rev_major;
1139 oct->boardinfo.minor = cs->board_rev_minor;
1140
1141 dev_info(&oct->pci_dev->dev,
1142 "Running %s (%llu Hz)\n",
1143 app_name, CVM_CAST64(cs->corefreq));
1144
1145 core_drv_init_err:
1146 for (i = 0; i < recv_pkt->buffer_count; i++)
1147 recv_buffer_free(recv_pkt->buffer_ptr[i]);
1148 octeon_free_recv_info(recv_info);
1149 return 0;
1150 }
1151
1152 int octeon_get_tx_qsize(struct octeon_device *oct, u32 q_no)
1153
1154 {
1155 if (oct && (q_no < MAX_OCTEON_INSTR_QUEUES) &&
1156 (oct->io_qmask.iq & (1UL << q_no)))
1157 return oct->instr_queue[q_no]->max_count;
1158
1159 return -1;
1160 }
1161
1162 int octeon_get_rx_qsize(struct octeon_device *oct, u32 q_no)
1163 {
1164 if (oct && (q_no < MAX_OCTEON_OUTPUT_QUEUES) &&
1165 (oct->io_qmask.oq & (1UL << q_no)))
1166 return oct->droq[q_no]->max_count;
1167 return -1;
1168 }
1169
1170 /* Retruns the host firmware handshake OCTEON specific configuration */
1171 struct octeon_config *octeon_get_conf(struct octeon_device *oct)
1172 {
1173 struct octeon_config *default_oct_conf = NULL;
1174
1175 /* check the OCTEON Device model & return the corresponding octeon
1176 * configuration
1177 */
1178
1179 if (OCTEON_CN6XXX(oct)) {
1180 default_oct_conf =
1181 (struct octeon_config *)(CHIP_FIELD(oct, cn6xxx, conf));
1182 }
1183
1184 return default_oct_conf;
1185 }
1186
1187 /* scratch register address is same in all the OCT-II and CN70XX models */
1188 #define CNXX_SLI_SCRATCH1 0x3C0
1189
1190 /** Get the octeon device pointer.
1191 * @param octeon_id - The id for which the octeon device pointer is required.
1192 * @return Success: Octeon device pointer.
1193 * @return Failure: NULL.
1194 */
1195 struct octeon_device *lio_get_device(u32 octeon_id)
1196 {
1197 if (octeon_id >= MAX_OCTEON_DEVICES)
1198 return NULL;
1199 else
1200 return octeon_device[octeon_id];
1201 }
1202
1203 u64 lio_pci_readq(struct octeon_device *oct, u64 addr)
1204 {
1205 u64 val64;
1206 unsigned long flags;
1207 u32 val32, addrhi;
1208
1209 spin_lock_irqsave(&oct->pci_win_lock, flags);
1210
1211 /* The windowed read happens when the LSB of the addr is written.
1212 * So write MSB first
1213 */
1214 addrhi = (addr >> 32);
1215 if ((oct->chip_id == OCTEON_CN66XX) || (oct->chip_id == OCTEON_CN68XX))
1216 addrhi |= 0x00060000;
1217 writel(addrhi, oct->reg_list.pci_win_rd_addr_hi);
1218
1219 /* Read back to preserve ordering of writes */
1220 val32 = readl(oct->reg_list.pci_win_rd_addr_hi);
1221
1222 writel(addr & 0xffffffff, oct->reg_list.pci_win_rd_addr_lo);
1223 val32 = readl(oct->reg_list.pci_win_rd_addr_lo);
1224
1225 val64 = readq(oct->reg_list.pci_win_rd_data);
1226
1227 spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1228
1229 return val64;
1230 }
1231
1232 void lio_pci_writeq(struct octeon_device *oct,
1233 u64 val,
1234 u64 addr)
1235 {
1236 u32 val32;
1237 unsigned long flags;
1238
1239 spin_lock_irqsave(&oct->pci_win_lock, flags);
1240
1241 writeq(addr, oct->reg_list.pci_win_wr_addr);
1242
1243 /* The write happens when the LSB is written. So write MSB first. */
1244 writel(val >> 32, oct->reg_list.pci_win_wr_data_hi);
1245 /* Read the MSB to ensure ordering of writes. */
1246 val32 = readl(oct->reg_list.pci_win_wr_data_hi);
1247
1248 writel(val & 0xffffffff, oct->reg_list.pci_win_wr_data_lo);
1249
1250 spin_unlock_irqrestore(&oct->pci_win_lock, flags);
1251 }
1252
1253 int octeon_mem_access_ok(struct octeon_device *oct)
1254 {
1255 u64 access_okay = 0;
1256
1257 /* Check to make sure a DDR interface is enabled */
1258 u64 lmc0_reset_ctl = lio_pci_readq(oct, CN6XXX_LMC0_RESET_CTL);
1259
1260 access_okay = (lmc0_reset_ctl & CN6XXX_LMC0_RESET_CTL_DDR3RST_MASK);
1261
1262 return access_okay ? 0 : 1;
1263 }
1264
1265 int octeon_wait_for_ddr_init(struct octeon_device *oct, u32 *timeout)
1266 {
1267 int ret = 1;
1268 u32 ms;
1269
1270 if (!timeout)
1271 return ret;
1272
1273 while (*timeout == 0)
1274 schedule_timeout_uninterruptible(HZ / 10);
1275
1276 for (ms = 0; (ret != 0) && ((*timeout == 0) || (ms <= *timeout));
1277 ms += HZ / 10) {
1278 ret = octeon_mem_access_ok(oct);
1279
1280 /* wait 100 ms */
1281 if (ret)
1282 schedule_timeout_uninterruptible(HZ / 10);
1283 }
1284
1285 return ret;
1286 }
1287
1288 /** Get the octeon id assigned to the octeon device passed as argument.
1289 * This function is exported to other modules.
1290 * @param dev - octeon device pointer passed as a void *.
1291 * @return octeon device id
1292 */
1293 int lio_get_device_id(void *dev)
1294 {
1295 struct octeon_device *octeon_dev = (struct octeon_device *)dev;
1296 u32 i;
1297
1298 for (i = 0; i < MAX_OCTEON_DEVICES; i++)
1299 if (octeon_device[i] == octeon_dev)
1300 return octeon_dev->octeon_id;
1301 return -1;
1302 }
Linux kernel - Deliverables
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