2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/etherdevice.h>
50 #include <linux/net_tstamp.h>
52 #include "t4_chip_type.h"
53 #include "cxgb4_uld.h"
55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
58 MAX_NPORTS
= 4, /* max # of ports */
59 SERNUM_LEN
= 24, /* Serial # length */
60 EC_LEN
= 16, /* E/C length */
61 ID_LEN
= 16, /* ID length */
62 PN_LEN
= 16, /* Part Number length */
63 MACADDR_LEN
= 12, /* MAC Address length */
67 T4_REGMAP_SIZE
= (160 * 1024),
68 T5_REGMAP_SIZE
= (332 * 1024),
80 MEMWIN0_APERTURE
= 2048,
81 MEMWIN0_BASE
= 0x1b800,
82 MEMWIN1_APERTURE
= 32768,
83 MEMWIN1_BASE
= 0x28000,
84 MEMWIN1_BASE_T5
= 0x52000,
85 MEMWIN2_APERTURE
= 65536,
86 MEMWIN2_BASE
= 0x30000,
87 MEMWIN2_APERTURE_T5
= 131072,
88 MEMWIN2_BASE_T5
= 0x60000,
106 PAUSE_AUTONEG
= 1 << 2
110 u64 tx_octets
; /* total # of octets in good frames */
111 u64 tx_frames
; /* all good frames */
112 u64 tx_bcast_frames
; /* all broadcast frames */
113 u64 tx_mcast_frames
; /* all multicast frames */
114 u64 tx_ucast_frames
; /* all unicast frames */
115 u64 tx_error_frames
; /* all error frames */
117 u64 tx_frames_64
; /* # of Tx frames in a particular range */
118 u64 tx_frames_65_127
;
119 u64 tx_frames_128_255
;
120 u64 tx_frames_256_511
;
121 u64 tx_frames_512_1023
;
122 u64 tx_frames_1024_1518
;
123 u64 tx_frames_1519_max
;
125 u64 tx_drop
; /* # of dropped Tx frames */
126 u64 tx_pause
; /* # of transmitted pause frames */
127 u64 tx_ppp0
; /* # of transmitted PPP prio 0 frames */
128 u64 tx_ppp1
; /* # of transmitted PPP prio 1 frames */
129 u64 tx_ppp2
; /* # of transmitted PPP prio 2 frames */
130 u64 tx_ppp3
; /* # of transmitted PPP prio 3 frames */
131 u64 tx_ppp4
; /* # of transmitted PPP prio 4 frames */
132 u64 tx_ppp5
; /* # of transmitted PPP prio 5 frames */
133 u64 tx_ppp6
; /* # of transmitted PPP prio 6 frames */
134 u64 tx_ppp7
; /* # of transmitted PPP prio 7 frames */
136 u64 rx_octets
; /* total # of octets in good frames */
137 u64 rx_frames
; /* all good frames */
138 u64 rx_bcast_frames
; /* all broadcast frames */
139 u64 rx_mcast_frames
; /* all multicast frames */
140 u64 rx_ucast_frames
; /* all unicast frames */
141 u64 rx_too_long
; /* # of frames exceeding MTU */
142 u64 rx_jabber
; /* # of jabber frames */
143 u64 rx_fcs_err
; /* # of received frames with bad FCS */
144 u64 rx_len_err
; /* # of received frames with length error */
145 u64 rx_symbol_err
; /* symbol errors */
146 u64 rx_runt
; /* # of short frames */
148 u64 rx_frames_64
; /* # of Rx frames in a particular range */
149 u64 rx_frames_65_127
;
150 u64 rx_frames_128_255
;
151 u64 rx_frames_256_511
;
152 u64 rx_frames_512_1023
;
153 u64 rx_frames_1024_1518
;
154 u64 rx_frames_1519_max
;
156 u64 rx_pause
; /* # of received pause frames */
157 u64 rx_ppp0
; /* # of received PPP prio 0 frames */
158 u64 rx_ppp1
; /* # of received PPP prio 1 frames */
159 u64 rx_ppp2
; /* # of received PPP prio 2 frames */
160 u64 rx_ppp3
; /* # of received PPP prio 3 frames */
161 u64 rx_ppp4
; /* # of received PPP prio 4 frames */
162 u64 rx_ppp5
; /* # of received PPP prio 5 frames */
163 u64 rx_ppp6
; /* # of received PPP prio 6 frames */
164 u64 rx_ppp7
; /* # of received PPP prio 7 frames */
166 u64 rx_ovflow0
; /* drops due to buffer-group 0 overflows */
167 u64 rx_ovflow1
; /* drops due to buffer-group 1 overflows */
168 u64 rx_ovflow2
; /* drops due to buffer-group 2 overflows */
169 u64 rx_ovflow3
; /* drops due to buffer-group 3 overflows */
170 u64 rx_trunc0
; /* buffer-group 0 truncated packets */
171 u64 rx_trunc1
; /* buffer-group 1 truncated packets */
172 u64 rx_trunc2
; /* buffer-group 2 truncated packets */
173 u64 rx_trunc3
; /* buffer-group 3 truncated packets */
176 struct lb_port_stats
{
189 u64 frames_1024_1518
;
204 struct tp_tcp_stats
{
208 u64 tcp_retrans_segs
;
211 struct tp_usm_stats
{
217 struct tp_fcoe_stats
{
223 struct tp_err_stats
{
227 u32 tnl_cong_drops
[4];
228 u32 ofld_chan_drops
[4];
230 u32 ofld_vlan_drops
[4];
236 struct tp_cpl_stats
{
241 struct tp_rdma_stats
{
247 u32 hps
; /* host page size for our PF/VF */
248 u32 eq_qpp
; /* egress queues/page for our PF/VF */
249 u32 iq_qpp
; /* egress queues/page for our PF/VF */
253 unsigned int tre
; /* log2 of core clocks per TP tick */
254 unsigned int la_mask
; /* what events are recorded by TP LA */
255 unsigned short tx_modq_map
; /* TX modulation scheduler queue to */
258 uint32_t dack_re
; /* DACK timer resolution */
259 unsigned short tx_modq
[NCHAN
]; /* channel to modulation queue map */
261 u32 vlan_pri_map
; /* cached TP_VLAN_PRI_MAP */
262 u32 ingress_config
; /* cached TP_INGRESS_CONFIG */
264 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
265 * subset of the set of fields which may be present in the Compressed
266 * Filter Tuple portion of filters and TCP TCB connections. The
267 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
268 * Since a variable number of fields may or may not be present, their
269 * shifted field positions within the Compressed Filter Tuple may
270 * vary, or not even be present if the field isn't selected in
271 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
272 * places we store their offsets here, or a -1 if the field isn't
284 u8 sn
[SERNUM_LEN
+ 1];
287 u8 na
[MACADDR_LEN
+ 1];
295 struct devlog_params
{
296 u32 memtype
; /* which memory (EDC0, EDC1, MC) */
297 u32 start
; /* start of log in firmware memory */
298 u32 size
; /* size of log */
301 /* Stores chip specific parameters */
302 struct arch_specific_params
{
305 u8 cng_ch_bits_log
; /* congestion channel map bits width */
312 struct adapter_params
{
313 struct sge_params sge
;
315 struct vpd_params vpd
;
316 struct pci_params pci
;
317 struct devlog_params devlog
;
318 enum pcie_memwin drv_memwin
;
320 unsigned int cim_la_size
;
322 unsigned int sf_size
; /* serial flash size in bytes */
323 unsigned int sf_nsec
; /* # of flash sectors */
324 unsigned int sf_fw_start
; /* start of FW image in flash */
326 unsigned int fw_vers
;
327 unsigned int bs_vers
; /* bootstrap version */
328 unsigned int tp_vers
;
329 unsigned int er_vers
; /* expansion ROM version */
332 unsigned short mtus
[NMTUS
];
333 unsigned short a_wnd
[NCCTRL_WIN
];
334 unsigned short b_wnd
[NCCTRL_WIN
];
336 unsigned char nports
; /* # of ethernet ports */
337 unsigned char portvec
;
338 enum chip_type chip
; /* chip code */
339 struct arch_specific_params arch
; /* chip specific params */
340 unsigned char offload
;
342 unsigned char bypass
;
344 unsigned int ofldq_wr_cred
;
345 bool ulptx_memwrite_dsgl
; /* use of T5 DSGL allowed */
347 unsigned int max_ordird_qp
; /* Max read depth per RDMA QP */
348 unsigned int max_ird_adapter
; /* Max read depth per adapter */
351 /* State needed to monitor the forward progress of SGE Ingress DMA activities
352 * and possible hangs.
354 struct sge_idma_monitor_state
{
355 unsigned int idma_1s_thresh
; /* 1s threshold in Core Clock ticks */
356 unsigned int idma_stalled
[2]; /* synthesized stalled timers in HZ */
357 unsigned int idma_state
[2]; /* IDMA Hang detect state */
358 unsigned int idma_qid
[2]; /* IDMA Hung Ingress Queue ID */
359 unsigned int idma_warn
[2]; /* time to warning in HZ */
362 #include "t4fw_api.h"
364 #define FW_VERSION(chip) ( \
365 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
366 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
367 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
368 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
369 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
375 struct fw_hdr fw_hdr
;
379 struct trace_params
{
380 u32 data
[TRACE_LEN
/ 4];
381 u32 mask
[TRACE_LEN
/ 4];
382 unsigned short snap_len
;
383 unsigned short min_len
;
384 unsigned char skip_ofst
;
385 unsigned char skip_len
;
386 unsigned char invert
;
391 unsigned short supported
; /* link capabilities */
392 unsigned short advertising
; /* advertised capabilities */
393 unsigned short requested_speed
; /* speed user has requested */
394 unsigned short speed
; /* actual link speed */
395 unsigned char requested_fc
; /* flow control user has requested */
396 unsigned char fc
; /* actual link flow control */
397 unsigned char autoneg
; /* autonegotiating? */
398 unsigned char link_ok
; /* link up? */
401 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
404 MAX_ETH_QSETS
= 32, /* # of Ethernet Tx/Rx queue sets */
405 MAX_OFLD_QSETS
= 16, /* # of offload Tx, iscsi Rx queue sets */
406 MAX_CTRL_QUEUES
= NCHAN
, /* # of control Tx queues */
407 MAX_RDMA_QUEUES
= NCHAN
, /* # of streaming RDMA Rx queues */
408 MAX_RDMA_CIQS
= 32, /* # of RDMA concentrator IQs */
410 /* # of streaming iSCSIT Rx queues */
411 MAX_ISCSIT_QUEUES
= MAX_OFLD_QSETS
,
415 MAX_TXQ_ENTRIES
= 16384,
416 MAX_CTRL_TXQ_ENTRIES
= 1024,
417 MAX_RSPQ_ENTRIES
= 16384,
418 MAX_RX_BUFFERS
= 16384,
419 MIN_TXQ_ENTRIES
= 32,
420 MIN_CTRL_TXQ_ENTRIES
= 32,
421 MIN_RSPQ_ENTRIES
= 128,
426 INGQ_EXTRAS
= 2, /* firmware event queue and */
427 /* forwarded interrupts */
428 MAX_INGQ
= MAX_ETH_QSETS
+ MAX_OFLD_QSETS
+ MAX_RDMA_QUEUES
+
429 MAX_RDMA_CIQS
+ MAX_ISCSIT_QUEUES
+ INGQ_EXTRAS
,
435 #include "cxgb4_dcb.h"
437 #ifdef CONFIG_CHELSIO_T4_FCOE
438 #include "cxgb4_fcoe.h"
439 #endif /* CONFIG_CHELSIO_T4_FCOE */
442 struct adapter
*adapter
;
444 s16 xact_addr_filt
; /* index of exact MAC address filter */
445 u16 rss_size
; /* size of VI's RSS table slice */
447 enum fw_port_type port_type
;
451 u8 lport
; /* associated offload logical port */
452 u8 nqsets
; /* # of qsets */
453 u8 first_qset
; /* index of first qset */
455 struct link_config link_cfg
;
457 struct port_stats stats_base
;
458 #ifdef CONFIG_CHELSIO_T4_DCB
459 struct port_dcb_info dcb
; /* Data Center Bridging support */
461 #ifdef CONFIG_CHELSIO_T4_FCOE
462 struct cxgb_fcoe fcoe
;
463 #endif /* CONFIG_CHELSIO_T4_FCOE */
464 bool rxtstamp
; /* Enable TS */
465 struct hwtstamp_config tstamp_config
;
471 enum { /* adapter flags */
472 FULL_INIT_DONE
= (1 << 0),
473 DEV_ENABLED
= (1 << 1),
474 USING_MSI
= (1 << 2),
475 USING_MSIX
= (1 << 3),
477 RSS_TNLALLLOOKUP
= (1 << 5),
478 USING_SOFT_PARAMS
= (1 << 6),
479 MASTER_PF
= (1 << 7),
480 FW_OFLD_CONN
= (1 << 9),
485 struct sge_fl
{ /* SGE free-buffer queue state */
486 unsigned int avail
; /* # of available Rx buffers */
487 unsigned int pend_cred
; /* new buffers since last FL DB ring */
488 unsigned int cidx
; /* consumer index */
489 unsigned int pidx
; /* producer index */
490 unsigned long alloc_failed
; /* # of times buffer allocation failed */
491 unsigned long large_alloc_failed
;
492 unsigned long mapping_err
; /* # of RX Buffer DMA Mapping failures */
493 unsigned long low
; /* # of times momentarily starving */
494 unsigned long starving
;
496 unsigned int cntxt_id
; /* SGE context id for the free list */
497 unsigned int size
; /* capacity of free list */
498 struct rx_sw_desc
*sdesc
; /* address of SW Rx descriptor ring */
499 __be64
*desc
; /* address of HW Rx descriptor ring */
500 dma_addr_t addr
; /* bus address of HW ring start */
501 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
502 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
505 /* A packet gather list */
507 u64 sgetstamp
; /* SGE Time Stamp for Ingress Packet */
508 struct page_frag frags
[MAX_SKB_FRAGS
];
509 void *va
; /* virtual address of first byte */
510 unsigned int nfrags
; /* # of fragments */
511 unsigned int tot_len
; /* total length of fragments */
514 typedef int (*rspq_handler_t
)(struct sge_rspq
*q
, const __be64
*rsp
,
515 const struct pkt_gl
*gl
);
516 typedef void (*rspq_flush_handler_t
)(struct sge_rspq
*q
);
517 /* LRO related declarations for ULD */
519 #define MAX_LRO_SESSIONS 64
520 u8 lro_session_cnt
; /* # of sessions to aggregate */
521 unsigned long lro_pkts
; /* # of LRO super packets */
522 unsigned long lro_merged
; /* # of wire packets merged by LRO */
523 struct sk_buff_head lroq
; /* list of aggregated sessions */
526 struct sge_rspq
{ /* state for an SGE response queue */
527 struct napi_struct napi
;
528 const __be64
*cur_desc
; /* current descriptor in queue */
529 unsigned int cidx
; /* consumer index */
530 u8 gen
; /* current generation bit */
531 u8 intr_params
; /* interrupt holdoff parameters */
532 u8 next_intr_params
; /* holdoff params for next interrupt */
534 u8 pktcnt_idx
; /* interrupt packet threshold */
535 u8 uld
; /* ULD handling this queue */
536 u8 idx
; /* queue index within its group */
537 int offset
; /* offset into current Rx buffer */
538 u16 cntxt_id
; /* SGE context id for the response q */
539 u16 abs_id
; /* absolute SGE id for the response q */
540 __be64
*desc
; /* address of HW response ring */
541 dma_addr_t phys_addr
; /* physical address of the ring */
542 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
543 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
544 unsigned int iqe_len
; /* entry size */
545 unsigned int size
; /* capacity of response queue */
546 struct adapter
*adap
;
547 struct net_device
*netdev
; /* associated net device */
548 rspq_handler_t handler
;
549 rspq_flush_handler_t flush_handler
;
550 struct t4_lro_mgr lro_mgr
;
551 #ifdef CONFIG_NET_RX_BUSY_POLL
552 #define CXGB_POLL_STATE_IDLE 0
553 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
554 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
555 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
556 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
557 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
558 CXGB_POLL_STATE_POLL_YIELD)
559 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
560 CXGB_POLL_STATE_POLL)
561 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
562 CXGB_POLL_STATE_POLL_YIELD)
563 unsigned int bpoll_state
;
564 spinlock_t bpoll_lock
; /* lock for busy poll */
565 #endif /* CONFIG_NET_RX_BUSY_POLL */
569 struct sge_eth_stats
{ /* Ethernet queue statistics */
570 unsigned long pkts
; /* # of ethernet packets */
571 unsigned long lro_pkts
; /* # of LRO super packets */
572 unsigned long lro_merged
; /* # of wire packets merged by LRO */
573 unsigned long rx_cso
; /* # of Rx checksum offloads */
574 unsigned long vlan_ex
; /* # of Rx VLAN extractions */
575 unsigned long rx_drops
; /* # of packets dropped due to no mem */
578 struct sge_eth_rxq
{ /* SW Ethernet Rx queue */
579 struct sge_rspq rspq
;
581 struct sge_eth_stats stats
;
582 } ____cacheline_aligned_in_smp
;
584 struct sge_ofld_stats
{ /* offload queue statistics */
585 unsigned long pkts
; /* # of packets */
586 unsigned long imm
; /* # of immediate-data packets */
587 unsigned long an
; /* # of asynchronous notifications */
588 unsigned long nomem
; /* # of responses deferred due to no mem */
591 struct sge_ofld_rxq
{ /* SW offload Rx queue */
592 struct sge_rspq rspq
;
594 struct sge_ofld_stats stats
;
595 } ____cacheline_aligned_in_smp
;
604 unsigned int in_use
; /* # of in-use Tx descriptors */
605 unsigned int size
; /* # of descriptors */
606 unsigned int cidx
; /* SW consumer index */
607 unsigned int pidx
; /* producer index */
608 unsigned long stops
; /* # of times q has been stopped */
609 unsigned long restarts
; /* # of queue restarts */
610 unsigned int cntxt_id
; /* SGE context id for the Tx q */
611 struct tx_desc
*desc
; /* address of HW Tx descriptor ring */
612 struct tx_sw_desc
*sdesc
; /* address of SW Tx descriptor ring */
613 struct sge_qstat
*stat
; /* queue status entry */
614 dma_addr_t phys_addr
; /* physical address of the ring */
617 unsigned short db_pidx
;
618 unsigned short db_pidx_inc
;
619 void __iomem
*bar2_addr
; /* address of BAR2 Queue registers */
620 unsigned int bar2_qid
; /* Queue ID for BAR2 Queue registers */
623 struct sge_eth_txq
{ /* state for an SGE Ethernet Tx queue */
625 struct netdev_queue
*txq
; /* associated netdev TX queue */
626 #ifdef CONFIG_CHELSIO_T4_DCB
627 u8 dcb_prio
; /* DCB Priority bound to queue */
629 unsigned long tso
; /* # of TSO requests */
630 unsigned long tx_cso
; /* # of Tx checksum offloads */
631 unsigned long vlan_ins
; /* # of Tx VLAN insertions */
632 unsigned long mapping_err
; /* # of I/O MMU packet mapping errors */
633 } ____cacheline_aligned_in_smp
;
635 struct sge_ofld_txq
{ /* state for an SGE offload Tx queue */
637 struct adapter
*adap
;
638 struct sk_buff_head sendq
; /* list of backpressured packets */
639 struct tasklet_struct qresume_tsk
; /* restarts the queue */
640 bool service_ofldq_running
; /* service_ofldq() is processing sendq */
641 u8 full
; /* the Tx ring is full */
642 unsigned long mapping_err
; /* # of I/O MMU packet mapping errors */
643 } ____cacheline_aligned_in_smp
;
645 struct sge_ctrl_txq
{ /* state for an SGE control Tx queue */
647 struct adapter
*adap
;
648 struct sk_buff_head sendq
; /* list of backpressured packets */
649 struct tasklet_struct qresume_tsk
; /* restarts the queue */
650 u8 full
; /* the Tx ring is full */
651 } ____cacheline_aligned_in_smp
;
654 struct sge_eth_txq ethtxq
[MAX_ETH_QSETS
];
655 struct sge_ofld_txq ofldtxq
[MAX_OFLD_QSETS
];
656 struct sge_ctrl_txq ctrlq
[MAX_CTRL_QUEUES
];
658 struct sge_eth_rxq ethrxq
[MAX_ETH_QSETS
];
659 struct sge_ofld_rxq iscsirxq
[MAX_OFLD_QSETS
];
660 struct sge_ofld_rxq iscsitrxq
[MAX_ISCSIT_QUEUES
];
661 struct sge_ofld_rxq rdmarxq
[MAX_RDMA_QUEUES
];
662 struct sge_ofld_rxq rdmaciq
[MAX_RDMA_CIQS
];
663 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp
;
665 struct sge_rspq intrq ____cacheline_aligned_in_smp
;
666 spinlock_t intrq_lock
;
668 u16 max_ethqsets
; /* # of available Ethernet queue sets */
669 u16 ethqsets
; /* # of active Ethernet queue sets */
670 u16 ethtxq_rover
; /* Tx queue to clean up next */
671 u16 iscsiqsets
; /* # of active iSCSI queue sets */
672 u16 niscsitq
; /* # of available iSCST Rx queues */
673 u16 rdmaqs
; /* # of available RDMA Rx queues */
674 u16 rdmaciqs
; /* # of available RDMA concentrator IQs */
675 u16 iscsi_rxq
[MAX_OFLD_QSETS
];
676 u16 iscsit_rxq
[MAX_ISCSIT_QUEUES
];
677 u16 rdma_rxq
[MAX_RDMA_QUEUES
];
678 u16 rdma_ciq
[MAX_RDMA_CIQS
];
679 u16 timer_val
[SGE_NTIMERS
];
680 u8 counter_val
[SGE_NCOUNTERS
];
681 u32 fl_pg_order
; /* large page allocation size */
682 u32 stat_len
; /* length of status page at ring end */
683 u32 pktshift
; /* padding between CPL & packet data */
684 u32 fl_align
; /* response queue message alignment */
685 u32 fl_starve_thres
; /* Free List starvation threshold */
687 struct sge_idma_monitor_state idma_monitor
;
688 unsigned int egr_start
;
690 unsigned int ingr_start
;
691 unsigned int ingr_sz
;
692 void **egr_map
; /* qid->queue egress queue map */
693 struct sge_rspq
**ingr_map
; /* qid->queue ingress queue map */
694 unsigned long *starving_fl
;
695 unsigned long *txq_maperr
;
696 unsigned long *blocked_fl
;
697 struct timer_list rx_timer
; /* refills starving FLs */
698 struct timer_list tx_timer
; /* checks Tx queues */
701 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
702 #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++)
703 #define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++)
704 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
705 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
709 #ifdef CONFIG_PCI_IOV
711 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
712 * Configuration initialization for T5 only has SR-IOV functionality enabled
713 * on PF0-3 in order to simplify everything.
715 #define NUM_OF_PF_WITH_SRIOV 4
719 struct doorbell_stats
{
725 struct hash_mac_addr
{
726 struct list_head list
;
734 struct pci_dev
*pdev
;
735 struct device
*pdev_dev
;
744 struct adapter_params params
;
745 struct cxgb4_virt_res vres
;
750 char desc
[IFNAMSIZ
+ 10];
751 } msix_info
[MAX_INGQ
+ 1];
753 struct doorbell_stats db_stats
;
756 struct net_device
*port
[MAX_NPORTS
];
757 u8 chan_map
[NCHAN
]; /* channel -> port map */
760 unsigned int l2t_start
;
761 unsigned int l2t_end
;
762 struct l2t_data
*l2t
;
763 unsigned int clipt_start
;
764 unsigned int clipt_end
;
765 struct clip_tbl
*clipt
;
766 void *uld_handle
[CXGB4_ULD_MAX
];
767 struct list_head list_node
;
768 struct list_head rcu_node
;
769 struct list_head mac_hlist
; /* list of MAC addresses in MPS Hash */
773 struct tid_info tids
;
774 void **tid_release_head
;
775 spinlock_t tid_release_lock
;
776 struct workqueue_struct
*workq
;
777 struct work_struct tid_release_task
;
778 struct work_struct db_full_task
;
779 struct work_struct db_drop_task
;
780 bool tid_release_task_busy
;
782 struct dentry
*debugfs_root
;
783 bool use_bd
; /* Use SGE Back Door intfc for reading SGE Contexts */
784 bool trace_rss
; /* 1 implies that different RSS flit per filter is
785 * used per filter else if 0 default RSS flit is
786 * used for all 4 filters.
789 spinlock_t stats_lock
;
790 spinlock_t win0_lock ____cacheline_aligned_in_smp
;
793 /* Defined bit width of user definable filter tuples
795 #define ETHTYPE_BITWIDTH 16
796 #define FRAG_BITWIDTH 1
797 #define MACIDX_BITWIDTH 9
798 #define FCOE_BITWIDTH 1
799 #define IPORT_BITWIDTH 3
800 #define MATCHTYPE_BITWIDTH 3
801 #define PROTO_BITWIDTH 8
802 #define TOS_BITWIDTH 8
803 #define PF_BITWIDTH 8
804 #define VF_BITWIDTH 8
805 #define IVLAN_BITWIDTH 16
806 #define OVLAN_BITWIDTH 16
808 /* Filter matching rules. These consist of a set of ingress packet field
809 * (value, mask) tuples. The associated ingress packet field matches the
810 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
811 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
812 * matches an ingress packet when all of the individual individual field
813 * matching rules are true.
815 * Partial field masks are always valid, however, while it may be easy to
816 * understand their meanings for some fields (e.g. IP address to match a
817 * subnet), for others making sensible partial masks is less intuitive (e.g.
818 * MPS match type) ...
820 * Most of the following data structures are modeled on T4 capabilities.
821 * Drivers for earlier chips use the subsets which make sense for those chips.
822 * We really need to come up with a hardware-independent mechanism to
823 * represent hardware filter capabilities ...
825 struct ch_filter_tuple
{
826 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
827 * register selects which of these fields will participate in the
828 * filter match rules -- up to a maximum of 36 bits. Because
829 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
832 uint32_t ethtype
:ETHTYPE_BITWIDTH
; /* Ethernet type */
833 uint32_t frag
:FRAG_BITWIDTH
; /* IP fragmentation header */
834 uint32_t ivlan_vld
:1; /* inner VLAN valid */
835 uint32_t ovlan_vld
:1; /* outer VLAN valid */
836 uint32_t pfvf_vld
:1; /* PF/VF valid */
837 uint32_t macidx
:MACIDX_BITWIDTH
; /* exact match MAC index */
838 uint32_t fcoe
:FCOE_BITWIDTH
; /* FCoE packet */
839 uint32_t iport
:IPORT_BITWIDTH
; /* ingress port */
840 uint32_t matchtype
:MATCHTYPE_BITWIDTH
; /* MPS match type */
841 uint32_t proto
:PROTO_BITWIDTH
; /* protocol type */
842 uint32_t tos
:TOS_BITWIDTH
; /* TOS/Traffic Type */
843 uint32_t pf
:PF_BITWIDTH
; /* PCI-E PF ID */
844 uint32_t vf
:VF_BITWIDTH
; /* PCI-E VF ID */
845 uint32_t ivlan
:IVLAN_BITWIDTH
; /* inner VLAN */
846 uint32_t ovlan
:OVLAN_BITWIDTH
; /* outer VLAN */
848 /* Uncompressed header matching field rules. These are always
849 * available for field rules.
851 uint8_t lip
[16]; /* local IP address (IPv4 in [3:0]) */
852 uint8_t fip
[16]; /* foreign IP address (IPv4 in [3:0]) */
853 uint16_t lport
; /* local port */
854 uint16_t fport
; /* foreign port */
857 /* A filter ioctl command.
859 struct ch_filter_specification
{
860 /* Administrative fields for filter.
862 uint32_t hitcnts
:1; /* count filter hits in TCB */
863 uint32_t prio
:1; /* filter has priority over active/server */
865 /* Fundamental filter typing. This is the one element of filter
866 * matching that doesn't exist as a (value, mask) tuple.
868 uint32_t type
:1; /* 0 => IPv4, 1 => IPv6 */
870 /* Packet dispatch information. Ingress packets which match the
871 * filter rules will be dropped, passed to the host or switched back
872 * out as egress packets.
874 uint32_t action
:2; /* drop, pass, switch */
876 uint32_t rpttid
:1; /* report TID in RSS hash field */
878 uint32_t dirsteer
:1; /* 0 => RSS, 1 => steer to iq */
879 uint32_t iq
:10; /* ingress queue */
881 uint32_t maskhash
:1; /* dirsteer=0: store RSS hash in TCB */
882 uint32_t dirsteerhash
:1;/* dirsteer=1: 0 => TCB contains RSS hash */
883 /* 1 => TCB contains IQ ID */
885 /* Switch proxy/rewrite fields. An ingress packet which matches a
886 * filter with "switch" set will be looped back out as an egress
887 * packet -- potentially with some Ethernet header rewriting.
889 uint32_t eport
:2; /* egress port to switch packet out */
890 uint32_t newdmac
:1; /* rewrite destination MAC address */
891 uint32_t newsmac
:1; /* rewrite source MAC address */
892 uint32_t newvlan
:2; /* rewrite VLAN Tag */
893 uint8_t dmac
[ETH_ALEN
]; /* new destination MAC address */
894 uint8_t smac
[ETH_ALEN
]; /* new source MAC address */
895 uint16_t vlan
; /* VLAN Tag to insert */
897 /* Filter rule value/mask pairs.
899 struct ch_filter_tuple val
;
900 struct ch_filter_tuple mask
;
904 FILTER_PASS
= 0, /* default */
910 VLAN_NOCHANGE
= 0, /* default */
916 static inline int is_offload(const struct adapter
*adap
)
918 return adap
->params
.offload
;
921 static inline u32
t4_read_reg(struct adapter
*adap
, u32 reg_addr
)
923 return readl(adap
->regs
+ reg_addr
);
926 static inline void t4_write_reg(struct adapter
*adap
, u32 reg_addr
, u32 val
)
928 writel(val
, adap
->regs
+ reg_addr
);
932 static inline u64
readq(const volatile void __iomem
*addr
)
934 return readl(addr
) + ((u64
)readl(addr
+ 4) << 32);
937 static inline void writeq(u64 val
, volatile void __iomem
*addr
)
940 writel(val
>> 32, addr
+ 4);
944 static inline u64
t4_read_reg64(struct adapter
*adap
, u32 reg_addr
)
946 return readq(adap
->regs
+ reg_addr
);
949 static inline void t4_write_reg64(struct adapter
*adap
, u32 reg_addr
, u64 val
)
951 writeq(val
, adap
->regs
+ reg_addr
);
955 * t4_set_hw_addr - store a port's MAC address in SW
956 * @adapter: the adapter
957 * @port_idx: the port index
958 * @hw_addr: the Ethernet address
960 * Store the Ethernet address of the given port in SW. Called by the common
961 * code when it retrieves a port's Ethernet address from EEPROM.
963 static inline void t4_set_hw_addr(struct adapter
*adapter
, int port_idx
,
966 ether_addr_copy(adapter
->port
[port_idx
]->dev_addr
, hw_addr
);
967 ether_addr_copy(adapter
->port
[port_idx
]->perm_addr
, hw_addr
);
971 * netdev2pinfo - return the port_info structure associated with a net_device
974 * Return the struct port_info associated with a net_device
976 static inline struct port_info
*netdev2pinfo(const struct net_device
*dev
)
978 return netdev_priv(dev
);
982 * adap2pinfo - return the port_info of a port
984 * @idx: the port index
986 * Return the port_info structure for the port of the given index.
988 static inline struct port_info
*adap2pinfo(struct adapter
*adap
, int idx
)
990 return netdev_priv(adap
->port
[idx
]);
994 * netdev2adap - return the adapter structure associated with a net_device
997 * Return the struct adapter associated with a net_device
999 static inline struct adapter
*netdev2adap(const struct net_device
*dev
)
1001 return netdev2pinfo(dev
)->adapter
;
1004 #ifdef CONFIG_NET_RX_BUSY_POLL
1005 static inline void cxgb_busy_poll_init_lock(struct sge_rspq
*q
)
1007 spin_lock_init(&q
->bpoll_lock
);
1008 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1011 static inline bool cxgb_poll_lock_napi(struct sge_rspq
*q
)
1015 spin_lock(&q
->bpoll_lock
);
1016 if (q
->bpoll_state
& CXGB_POLL_LOCKED
) {
1017 q
->bpoll_state
|= CXGB_POLL_STATE_NAPI_YIELD
;
1020 q
->bpoll_state
= CXGB_POLL_STATE_NAPI
;
1022 spin_unlock(&q
->bpoll_lock
);
1026 static inline bool cxgb_poll_unlock_napi(struct sge_rspq
*q
)
1030 spin_lock(&q
->bpoll_lock
);
1031 if (q
->bpoll_state
& CXGB_POLL_STATE_POLL_YIELD
)
1033 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1034 spin_unlock(&q
->bpoll_lock
);
1038 static inline bool cxgb_poll_lock_poll(struct sge_rspq
*q
)
1042 spin_lock_bh(&q
->bpoll_lock
);
1043 if (q
->bpoll_state
& CXGB_POLL_LOCKED
) {
1044 q
->bpoll_state
|= CXGB_POLL_STATE_POLL_YIELD
;
1047 q
->bpoll_state
|= CXGB_POLL_STATE_POLL
;
1049 spin_unlock_bh(&q
->bpoll_lock
);
1053 static inline bool cxgb_poll_unlock_poll(struct sge_rspq
*q
)
1057 spin_lock_bh(&q
->bpoll_lock
);
1058 if (q
->bpoll_state
& CXGB_POLL_STATE_POLL_YIELD
)
1060 q
->bpoll_state
= CXGB_POLL_STATE_IDLE
;
1061 spin_unlock_bh(&q
->bpoll_lock
);
1065 static inline bool cxgb_poll_busy_polling(struct sge_rspq
*q
)
1067 return q
->bpoll_state
& CXGB_POLL_USER_PEND
;
1070 static inline void cxgb_busy_poll_init_lock(struct sge_rspq
*q
)
1074 static inline bool cxgb_poll_lock_napi(struct sge_rspq
*q
)
1079 static inline bool cxgb_poll_unlock_napi(struct sge_rspq
*q
)
1084 static inline bool cxgb_poll_lock_poll(struct sge_rspq
*q
)
1089 static inline bool cxgb_poll_unlock_poll(struct sge_rspq
*q
)
1094 static inline bool cxgb_poll_busy_polling(struct sge_rspq
*q
)
1098 #endif /* CONFIG_NET_RX_BUSY_POLL */
1100 /* Return a version number to identify the type of adapter. The scheme is:
1101 * - bits 0..9: chip version
1102 * - bits 10..15: chip revision
1103 * - bits 16..23: register dump version
1105 static inline unsigned int mk_adap_vers(struct adapter
*ap
)
1107 return CHELSIO_CHIP_VERSION(ap
->params
.chip
) |
1108 (CHELSIO_CHIP_RELEASE(ap
->params
.chip
) << 10) | (1 << 16);
1111 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1112 static inline unsigned int qtimer_val(const struct adapter
*adap
,
1113 const struct sge_rspq
*q
)
1115 unsigned int idx
= q
->intr_params
>> 1;
1117 return idx
< SGE_NTIMERS
? adap
->sge
.timer_val
[idx
] : 0;
1120 /* driver version & name used for ethtool_drvinfo */
1121 extern char cxgb4_driver_name
[];
1122 extern const char cxgb4_driver_version
[];
1124 void t4_os_portmod_changed(const struct adapter
*adap
, int port_id
);
1125 void t4_os_link_changed(struct adapter
*adap
, int port_id
, int link_stat
);
1127 void *t4_alloc_mem(size_t size
);
1129 void t4_free_sge_resources(struct adapter
*adap
);
1130 void t4_free_ofld_rxqs(struct adapter
*adap
, int n
, struct sge_ofld_rxq
*q
);
1131 irq_handler_t
t4_intr_handler(struct adapter
*adap
);
1132 netdev_tx_t
t4_eth_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
1133 int t4_ethrx_handler(struct sge_rspq
*q
, const __be64
*rsp
,
1134 const struct pkt_gl
*gl
);
1135 int t4_mgmt_tx(struct adapter
*adap
, struct sk_buff
*skb
);
1136 int t4_ofld_send(struct adapter
*adap
, struct sk_buff
*skb
);
1137 int t4_sge_alloc_rxq(struct adapter
*adap
, struct sge_rspq
*iq
, bool fwevtq
,
1138 struct net_device
*dev
, int intr_idx
,
1139 struct sge_fl
*fl
, rspq_handler_t hnd
,
1140 rspq_flush_handler_t flush_handler
, int cong
);
1141 int t4_sge_alloc_eth_txq(struct adapter
*adap
, struct sge_eth_txq
*txq
,
1142 struct net_device
*dev
, struct netdev_queue
*netdevq
,
1144 int t4_sge_alloc_ctrl_txq(struct adapter
*adap
, struct sge_ctrl_txq
*txq
,
1145 struct net_device
*dev
, unsigned int iqid
,
1146 unsigned int cmplqid
);
1147 int t4_sge_alloc_ofld_txq(struct adapter
*adap
, struct sge_ofld_txq
*txq
,
1148 struct net_device
*dev
, unsigned int iqid
);
1149 irqreturn_t
t4_sge_intr_msix(int irq
, void *cookie
);
1150 int t4_sge_init(struct adapter
*adap
);
1151 void t4_sge_start(struct adapter
*adap
);
1152 void t4_sge_stop(struct adapter
*adap
);
1153 int cxgb_busy_poll(struct napi_struct
*napi
);
1154 int cxgb4_set_rspq_intr_params(struct sge_rspq
*q
, unsigned int us
,
1156 void cxgb4_set_ethtool_ops(struct net_device
*netdev
);
1157 int cxgb4_write_rss(const struct port_info
*pi
, const u16
*queues
);
1158 extern int dbfifo_int_thresh
;
1160 #define for_each_port(adapter, iter) \
1161 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1163 static inline int is_bypass(struct adapter
*adap
)
1165 return adap
->params
.bypass
;
1168 static inline int is_bypass_device(int device
)
1170 /* this should be set based upon device capabilities */
1180 static inline int is_10gbt_device(int device
)
1182 /* this should be set based upon device capabilities */
1193 static inline unsigned int core_ticks_per_usec(const struct adapter
*adap
)
1195 return adap
->params
.vpd
.cclk
/ 1000;
1198 static inline unsigned int us_to_core_ticks(const struct adapter
*adap
,
1201 return (us
* adap
->params
.vpd
.cclk
) / 1000;
1204 static inline unsigned int core_ticks_to_us(const struct adapter
*adapter
,
1207 /* add Core Clock / 2 to round ticks to nearest uS */
1208 return ((ticks
* 1000 + adapter
->params
.vpd
.cclk
/2) /
1209 adapter
->params
.vpd
.cclk
);
1212 void t4_set_reg_field(struct adapter
*adap
, unsigned int addr
, u32 mask
,
1215 int t4_wr_mbox_meat_timeout(struct adapter
*adap
, int mbox
, const void *cmd
,
1216 int size
, void *rpl
, bool sleep_ok
, int timeout
);
1217 int t4_wr_mbox_meat(struct adapter
*adap
, int mbox
, const void *cmd
, int size
,
1218 void *rpl
, bool sleep_ok
);
1220 static inline int t4_wr_mbox_timeout(struct adapter
*adap
, int mbox
,
1221 const void *cmd
, int size
, void *rpl
,
1224 return t4_wr_mbox_meat_timeout(adap
, mbox
, cmd
, size
, rpl
, true,
1228 static inline int t4_wr_mbox(struct adapter
*adap
, int mbox
, const void *cmd
,
1229 int size
, void *rpl
)
1231 return t4_wr_mbox_meat(adap
, mbox
, cmd
, size
, rpl
, true);
1234 static inline int t4_wr_mbox_ns(struct adapter
*adap
, int mbox
, const void *cmd
,
1235 int size
, void *rpl
)
1237 return t4_wr_mbox_meat(adap
, mbox
, cmd
, size
, rpl
, false);
1241 * hash_mac_addr - return the hash value of a MAC address
1242 * @addr: the 48-bit Ethernet MAC address
1244 * Hashes a MAC address according to the hash function used by HW inexact
1245 * (hash) address matching.
1247 static inline int hash_mac_addr(const u8
*addr
)
1249 u32 a
= ((u32
)addr
[0] << 16) | ((u32
)addr
[1] << 8) | addr
[2];
1250 u32 b
= ((u32
)addr
[3] << 16) | ((u32
)addr
[4] << 8) | addr
[5];
1258 void t4_write_indirect(struct adapter
*adap
, unsigned int addr_reg
,
1259 unsigned int data_reg
, const u32
*vals
,
1260 unsigned int nregs
, unsigned int start_idx
);
1261 void t4_read_indirect(struct adapter
*adap
, unsigned int addr_reg
,
1262 unsigned int data_reg
, u32
*vals
, unsigned int nregs
,
1263 unsigned int start_idx
);
1264 void t4_hw_pci_read_cfg4(struct adapter
*adapter
, int reg
, u32
*val
);
1266 struct fw_filter_wr
;
1268 void t4_intr_enable(struct adapter
*adapter
);
1269 void t4_intr_disable(struct adapter
*adapter
);
1270 int t4_slow_intr_handler(struct adapter
*adapter
);
1272 int t4_wait_dev_ready(void __iomem
*regs
);
1273 int t4_link_l1cfg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
1274 struct link_config
*lc
);
1275 int t4_restart_aneg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
);
1277 u32
t4_read_pcie_cfg4(struct adapter
*adap
, int reg
);
1278 u32
t4_get_util_window(struct adapter
*adap
);
1279 void t4_setup_memwin(struct adapter
*adap
, u32 memwin_base
, u32 window
);
1281 #define T4_MEMORY_WRITE 0
1282 #define T4_MEMORY_READ 1
1283 int t4_memory_rw(struct adapter
*adap
, int win
, int mtype
, u32 addr
, u32 len
,
1284 void *buf
, int dir
);
1285 static inline int t4_memory_write(struct adapter
*adap
, int mtype
, u32 addr
,
1286 u32 len
, __be32
*buf
)
1288 return t4_memory_rw(adap
, 0, mtype
, addr
, len
, buf
, 0);
1291 unsigned int t4_get_regs_len(struct adapter
*adapter
);
1292 void t4_get_regs(struct adapter
*adap
, void *buf
, size_t buf_size
);
1294 int t4_seeprom_wp(struct adapter
*adapter
, bool enable
);
1295 int t4_get_raw_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
);
1296 int t4_get_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
);
1297 int t4_read_flash(struct adapter
*adapter
, unsigned int addr
,
1298 unsigned int nwords
, u32
*data
, int byte_oriented
);
1299 int t4_load_fw(struct adapter
*adapter
, const u8
*fw_data
, unsigned int size
);
1300 int t4_load_phy_fw(struct adapter
*adap
,
1301 int win
, spinlock_t
*lock
,
1302 int (*phy_fw_version
)(const u8
*, size_t),
1303 const u8
*phy_fw_data
, size_t phy_fw_size
);
1304 int t4_phy_fw_ver(struct adapter
*adap
, int *phy_fw_ver
);
1305 int t4_fwcache(struct adapter
*adap
, enum fw_params_param_dev_fwcache op
);
1306 int t4_fw_upgrade(struct adapter
*adap
, unsigned int mbox
,
1307 const u8
*fw_data
, unsigned int size
, int force
);
1308 int t4_fl_pkt_align(struct adapter
*adap
);
1309 unsigned int t4_flash_cfg_addr(struct adapter
*adapter
);
1310 int t4_check_fw_version(struct adapter
*adap
);
1311 int t4_get_fw_version(struct adapter
*adapter
, u32
*vers
);
1312 int t4_get_bs_version(struct adapter
*adapter
, u32
*vers
);
1313 int t4_get_tp_version(struct adapter
*adapter
, u32
*vers
);
1314 int t4_get_exprom_version(struct adapter
*adapter
, u32
*vers
);
1315 int t4_prep_fw(struct adapter
*adap
, struct fw_info
*fw_info
,
1316 const u8
*fw_data
, unsigned int fw_size
,
1317 struct fw_hdr
*card_fw
, enum dev_state state
, int *reset
);
1318 int t4_prep_adapter(struct adapter
*adapter
);
1320 enum t4_bar2_qtype
{ T4_BAR2_QTYPE_EGRESS
, T4_BAR2_QTYPE_INGRESS
};
1321 int t4_bar2_sge_qregs(struct adapter
*adapter
,
1323 enum t4_bar2_qtype qtype
,
1326 unsigned int *pbar2_qid
);
1328 unsigned int qtimer_val(const struct adapter
*adap
,
1329 const struct sge_rspq
*q
);
1331 int t4_init_devlog_params(struct adapter
*adapter
);
1332 int t4_init_sge_params(struct adapter
*adapter
);
1333 int t4_init_tp_params(struct adapter
*adap
);
1334 int t4_filter_field_shift(const struct adapter
*adap
, int filter_sel
);
1335 int t4_init_rss_mode(struct adapter
*adap
, int mbox
);
1336 int t4_port_init(struct adapter
*adap
, int mbox
, int pf
, int vf
);
1337 void t4_fatal_err(struct adapter
*adapter
);
1338 int t4_config_rss_range(struct adapter
*adapter
, int mbox
, unsigned int viid
,
1339 int start
, int n
, const u16
*rspq
, unsigned int nrspq
);
1340 int t4_config_glbl_rss(struct adapter
*adapter
, int mbox
, unsigned int mode
,
1341 unsigned int flags
);
1342 int t4_config_vi_rss(struct adapter
*adapter
, int mbox
, unsigned int viid
,
1343 unsigned int flags
, unsigned int defq
);
1344 int t4_read_rss(struct adapter
*adapter
, u16
*entries
);
1345 void t4_read_rss_key(struct adapter
*adapter
, u32
*key
);
1346 void t4_write_rss_key(struct adapter
*adap
, const u32
*key
, int idx
);
1347 void t4_read_rss_pf_config(struct adapter
*adapter
, unsigned int index
,
1349 void t4_read_rss_vf_config(struct adapter
*adapter
, unsigned int index
,
1350 u32
*vfl
, u32
*vfh
);
1351 u32
t4_read_rss_pf_map(struct adapter
*adapter
);
1352 u32
t4_read_rss_pf_mask(struct adapter
*adapter
);
1354 unsigned int t4_get_mps_bg_map(struct adapter
*adapter
, int idx
);
1355 void t4_pmtx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[]);
1356 void t4_pmrx_get_stats(struct adapter
*adap
, u32 cnt
[], u64 cycles
[]);
1357 int t4_read_cim_ibq(struct adapter
*adap
, unsigned int qid
, u32
*data
,
1359 int t4_read_cim_obq(struct adapter
*adap
, unsigned int qid
, u32
*data
,
1361 int t4_cim_read(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
1362 unsigned int *valp
);
1363 int t4_cim_write(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
1364 const unsigned int *valp
);
1365 int t4_cim_read_la(struct adapter
*adap
, u32
*la_buf
, unsigned int *wrptr
);
1366 void t4_cim_read_pif_la(struct adapter
*adap
, u32
*pif_req
, u32
*pif_rsp
,
1367 unsigned int *pif_req_wrptr
,
1368 unsigned int *pif_rsp_wrptr
);
1369 void t4_cim_read_ma_la(struct adapter
*adap
, u32
*ma_req
, u32
*ma_rsp
);
1370 void t4_read_cimq_cfg(struct adapter
*adap
, u16
*base
, u16
*size
, u16
*thres
);
1371 const char *t4_get_port_type_description(enum fw_port_type port_type
);
1372 void t4_get_port_stats(struct adapter
*adap
, int idx
, struct port_stats
*p
);
1373 void t4_get_port_stats_offset(struct adapter
*adap
, int idx
,
1374 struct port_stats
*stats
,
1375 struct port_stats
*offset
);
1376 void t4_get_lb_stats(struct adapter
*adap
, int idx
, struct lb_port_stats
*p
);
1377 void t4_read_mtu_tbl(struct adapter
*adap
, u16
*mtus
, u8
*mtu_log
);
1378 void t4_read_cong_tbl(struct adapter
*adap
, u16 incr
[NMTUS
][NCCTRL_WIN
]);
1379 void t4_tp_wr_bits_indirect(struct adapter
*adap
, unsigned int addr
,
1380 unsigned int mask
, unsigned int val
);
1381 void t4_tp_read_la(struct adapter
*adap
, u64
*la_buf
, unsigned int *wrptr
);
1382 void t4_tp_get_err_stats(struct adapter
*adap
, struct tp_err_stats
*st
);
1383 void t4_tp_get_cpl_stats(struct adapter
*adap
, struct tp_cpl_stats
*st
);
1384 void t4_tp_get_rdma_stats(struct adapter
*adap
, struct tp_rdma_stats
*st
);
1385 void t4_get_usm_stats(struct adapter
*adap
, struct tp_usm_stats
*st
);
1386 void t4_tp_get_tcp_stats(struct adapter
*adap
, struct tp_tcp_stats
*v4
,
1387 struct tp_tcp_stats
*v6
);
1388 void t4_get_fcoe_stats(struct adapter
*adap
, unsigned int idx
,
1389 struct tp_fcoe_stats
*st
);
1390 void t4_load_mtus(struct adapter
*adap
, const unsigned short *mtus
,
1391 const unsigned short *alpha
, const unsigned short *beta
);
1393 void t4_ulprx_read_la(struct adapter
*adap
, u32
*la_buf
);
1395 void t4_get_chan_txrate(struct adapter
*adap
, u64
*nic_rate
, u64
*ofld_rate
);
1396 void t4_mk_filtdelwr(unsigned int ftid
, struct fw_filter_wr
*wr
, int qid
);
1398 void t4_wol_magic_enable(struct adapter
*adap
, unsigned int port
,
1400 int t4_wol_pat_enable(struct adapter
*adap
, unsigned int port
, unsigned int map
,
1401 u64 mask0
, u64 mask1
, unsigned int crc
, bool enable
);
1403 int t4_fw_hello(struct adapter
*adap
, unsigned int mbox
, unsigned int evt_mbox
,
1404 enum dev_master master
, enum dev_state
*state
);
1405 int t4_fw_bye(struct adapter
*adap
, unsigned int mbox
);
1406 int t4_early_init(struct adapter
*adap
, unsigned int mbox
);
1407 int t4_fw_reset(struct adapter
*adap
, unsigned int mbox
, int reset
);
1408 int t4_fixup_host_params(struct adapter
*adap
, unsigned int page_size
,
1409 unsigned int cache_line_size
);
1410 int t4_fw_initialize(struct adapter
*adap
, unsigned int mbox
);
1411 int t4_query_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1412 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1414 int t4_query_params_rw(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1415 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1417 int t4_set_params_timeout(struct adapter
*adap
, unsigned int mbox
,
1418 unsigned int pf
, unsigned int vf
,
1419 unsigned int nparams
, const u32
*params
,
1420 const u32
*val
, int timeout
);
1421 int t4_set_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1422 unsigned int vf
, unsigned int nparams
, const u32
*params
,
1424 int t4_cfg_pfvf(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1425 unsigned int vf
, unsigned int txq
, unsigned int txq_eth_ctrl
,
1426 unsigned int rxqi
, unsigned int rxq
, unsigned int tc
,
1427 unsigned int vi
, unsigned int cmask
, unsigned int pmask
,
1428 unsigned int nexact
, unsigned int rcaps
, unsigned int wxcaps
);
1429 int t4_alloc_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
1430 unsigned int pf
, unsigned int vf
, unsigned int nmac
, u8
*mac
,
1431 unsigned int *rss_size
);
1432 int t4_free_vi(struct adapter
*adap
, unsigned int mbox
,
1433 unsigned int pf
, unsigned int vf
,
1435 int t4_set_rxmode(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1436 int mtu
, int promisc
, int all_multi
, int bcast
, int vlanex
,
1438 int t4_alloc_mac_filt(struct adapter
*adap
, unsigned int mbox
,
1439 unsigned int viid
, bool free
, unsigned int naddr
,
1440 const u8
**addr
, u16
*idx
, u64
*hash
, bool sleep_ok
);
1441 int t4_free_mac_filt(struct adapter
*adap
, unsigned int mbox
,
1442 unsigned int viid
, unsigned int naddr
,
1443 const u8
**addr
, bool sleep_ok
);
1444 int t4_change_mac(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1445 int idx
, const u8
*addr
, bool persist
, bool add_smt
);
1446 int t4_set_addr_hash(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1447 bool ucast
, u64 vec
, bool sleep_ok
);
1448 int t4_enable_vi_params(struct adapter
*adap
, unsigned int mbox
,
1449 unsigned int viid
, bool rx_en
, bool tx_en
, bool dcb_en
);
1450 int t4_enable_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1451 bool rx_en
, bool tx_en
);
1452 int t4_identify_port(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
1453 unsigned int nblinks
);
1454 int t4_mdio_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
1455 unsigned int mmd
, unsigned int reg
, u16
*valp
);
1456 int t4_mdio_wr(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
1457 unsigned int mmd
, unsigned int reg
, u16 val
);
1458 int t4_iq_stop(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1459 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
1460 unsigned int fl0id
, unsigned int fl1id
);
1461 int t4_iq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1462 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
1463 unsigned int fl0id
, unsigned int fl1id
);
1464 int t4_eth_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1465 unsigned int vf
, unsigned int eqid
);
1466 int t4_ctrl_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1467 unsigned int vf
, unsigned int eqid
);
1468 int t4_ofld_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
1469 unsigned int vf
, unsigned int eqid
);
1470 int t4_sge_ctxt_flush(struct adapter
*adap
, unsigned int mbox
);
1471 int t4_handle_fw_rpl(struct adapter
*adap
, const __be64
*rpl
);
1472 void t4_db_full(struct adapter
*adapter
);
1473 void t4_db_dropped(struct adapter
*adapter
);
1474 int t4_set_trace_filter(struct adapter
*adapter
, const struct trace_params
*tp
,
1475 int filter_index
, int enable
);
1476 void t4_get_trace_filter(struct adapter
*adapter
, struct trace_params
*tp
,
1477 int filter_index
, int *enabled
);
1478 int t4_fwaddrspace_write(struct adapter
*adap
, unsigned int mbox
,
1480 void t4_sge_decode_idma_state(struct adapter
*adapter
, int state
);
1481 void t4_free_mem(void *addr
);
1482 void t4_idma_monitor_init(struct adapter
*adapter
,
1483 struct sge_idma_monitor_state
*idma
);
1484 void t4_idma_monitor(struct adapter
*adapter
,
1485 struct sge_idma_monitor_state
*idma
,
1487 #endif /* __CXGB4_H__ */