drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed successfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_OFLD_CONNECTION_WR          = 0x2f,
  91         FW_FLOWC_WR                    = 0x0a,
  92         FW_OFLD_TX_DATA_WR             = 0x0b,
  93         FW_CMD_WR                      = 0x10,
  94         FW_ETH_TX_PKT_VM_WR            = 0x11,
  95         FW_RI_RES_WR                   = 0x0c,
  96         FW_RI_INIT_WR                  = 0x0d,
  97         FW_RI_RDMA_WRITE_WR            = 0x14,
  98         FW_RI_SEND_WR                  = 0x15,
  99         FW_RI_RDMA_READ_WR             = 0x16,
 100         FW_RI_RECV_WR                  = 0x17,
 101         FW_RI_BIND_MW_WR               = 0x18,
 102         FW_RI_FR_NSMR_WR               = 0x19,
 103         FW_RI_INV_LSTAG_WR             = 0x1a,
 104         FW_LASTC2E_WR                  = 0x70
 105 };
 106
 107 struct fw_wr_hdr {
 108         __be32 hi;
 109         __be32 lo;
 110 };
 111
 112 /* work request opcode (hi) */
 113 #define FW_WR_OP_S      24
 114 #define FW_WR_OP_M      0xff
 115 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 116 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 117
 118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 119 #define FW_WR_ATOMIC_S          23
 120 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 121
 122 /* flush flag (hi) - firmware flushes flushable work request buffered
 123  * in the flow context.
 124  */
 125 #define FW_WR_FLUSH_S     22
 126 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 127
 128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 129 #define FW_WR_COMPL_S     21
 130 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 131 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 132
 133 /* work request immediate data length (hi) */
 134 #define FW_WR_IMMDLEN_S 0
 135 #define FW_WR_IMMDLEN_M 0xff
 136 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 137
 138 /* egress queue status update to associated ingress queue entry (lo) */
 139 #define FW_WR_EQUIQ_S           31
 140 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 141 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 142
 143 /* egress queue status update to egress queue status entry (lo) */
 144 #define FW_WR_EQUEQ_S           30
 145 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 146 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 147
 148 /* flow context identifier (lo) */
 149 #define FW_WR_FLOWID_S          8
 150 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 151
 152 /* length in units of 16-bytes (lo) */
 153 #define FW_WR_LEN16_S           0
 154 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 155
 156 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 157 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 158
 159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 160 enum fw_filter_wr_cookie {
 161         FW_FILTER_WR_SUCCESS,
 162         FW_FILTER_WR_FLT_ADDED,
 163         FW_FILTER_WR_FLT_DELETED,
 164         FW_FILTER_WR_SMT_TBL_FULL,
 165         FW_FILTER_WR_EINVAL,
 166 };
 167
 168 struct fw_filter_wr {
 169         __be32 op_pkd;
 170         __be32 len16_pkd;
 171         __be64 r3;
 172         __be32 tid_to_iq;
 173         __be32 del_filter_to_l2tix;
 174         __be16 ethtype;
 175         __be16 ethtypem;
 176         __u8   frag_to_ovlan_vldm;
 177         __u8   smac_sel;
 178         __be16 rx_chan_rx_rpl_iq;
 179         __be32 maci_to_matchtypem;
 180         __u8   ptcl;
 181         __u8   ptclm;
 182         __u8   ttyp;
 183         __u8   ttypm;
 184         __be16 ivlan;
 185         __be16 ivlanm;
 186         __be16 ovlan;
 187         __be16 ovlanm;
 188         __u8   lip[16];
 189         __u8   lipm[16];
 190         __u8   fip[16];
 191         __u8   fipm[16];
 192         __be16 lp;
 193         __be16 lpm;
 194         __be16 fp;
 195         __be16 fpm;
 196         __be16 r7;
 197         __u8   sma[6];
 198 };
 199
 200 #define FW_FILTER_WR_TID_S      12
 201 #define FW_FILTER_WR_TID_M      0xfffff
 202 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 203 #define FW_FILTER_WR_TID_G(x)   \
 204         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 205
 206 #define FW_FILTER_WR_RQTYPE_S           11
 207 #define FW_FILTER_WR_RQTYPE_M           0x1
 208 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 209 #define FW_FILTER_WR_RQTYPE_G(x)        \
 210         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 211 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 212
 213 #define FW_FILTER_WR_NOREPLY_S          10
 214 #define FW_FILTER_WR_NOREPLY_M          0x1
 215 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 216 #define FW_FILTER_WR_NOREPLY_G(x)       \
 217         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 218 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 219
 220 #define FW_FILTER_WR_IQ_S       0
 221 #define FW_FILTER_WR_IQ_M       0x3ff
 222 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 223 #define FW_FILTER_WR_IQ_G(x)    \
 224         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 225
 226 #define FW_FILTER_WR_DEL_FILTER_S       31
 227 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 228 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 229 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 230         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 231 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 232
 233 #define FW_FILTER_WR_RPTTID_S           25
 234 #define FW_FILTER_WR_RPTTID_M           0x1
 235 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 236 #define FW_FILTER_WR_RPTTID_G(x)        \
 237         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 238 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 239
 240 #define FW_FILTER_WR_DROP_S     24
 241 #define FW_FILTER_WR_DROP_M     0x1
 242 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 243 #define FW_FILTER_WR_DROP_G(x)  \
 244         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 245 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 246
 247 #define FW_FILTER_WR_DIRSTEER_S         23
 248 #define FW_FILTER_WR_DIRSTEER_M         0x1
 249 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 250 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 251         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 252 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 253
 254 #define FW_FILTER_WR_MASKHASH_S         22
 255 #define FW_FILTER_WR_MASKHASH_M         0x1
 256 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 257 #define FW_FILTER_WR_MASKHASH_G(x)      \
 258         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 259 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 260
 261 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 262 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 263 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 264 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 265         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 266 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 267
 268 #define FW_FILTER_WR_LPBK_S     20
 269 #define FW_FILTER_WR_LPBK_M     0x1
 270 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 271 #define FW_FILTER_WR_LPBK_G(x)  \
 272         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 273 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 274
 275 #define FW_FILTER_WR_DMAC_S     19
 276 #define FW_FILTER_WR_DMAC_M     0x1
 277 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 278 #define FW_FILTER_WR_DMAC_G(x)  \
 279         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 280 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 281
 282 #define FW_FILTER_WR_SMAC_S     18
 283 #define FW_FILTER_WR_SMAC_M     0x1
 284 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 285 #define FW_FILTER_WR_SMAC_G(x)  \
 286         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 287 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 288
 289 #define FW_FILTER_WR_INSVLAN_S          17
 290 #define FW_FILTER_WR_INSVLAN_M          0x1
 291 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 292 #define FW_FILTER_WR_INSVLAN_G(x)       \
 293         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 294 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 295
 296 #define FW_FILTER_WR_RMVLAN_S           16
 297 #define FW_FILTER_WR_RMVLAN_M           0x1
 298 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 299 #define FW_FILTER_WR_RMVLAN_G(x)        \
 300         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 301 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 302
 303 #define FW_FILTER_WR_HITCNTS_S          15
 304 #define FW_FILTER_WR_HITCNTS_M          0x1
 305 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 306 #define FW_FILTER_WR_HITCNTS_G(x)       \
 307         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 308 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 309
 310 #define FW_FILTER_WR_TXCHAN_S           13
 311 #define FW_FILTER_WR_TXCHAN_M           0x3
 312 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 313 #define FW_FILTER_WR_TXCHAN_G(x)        \
 314         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 315
 316 #define FW_FILTER_WR_PRIO_S     12
 317 #define FW_FILTER_WR_PRIO_M     0x1
 318 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 319 #define FW_FILTER_WR_PRIO_G(x)  \
 320         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 321 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 322
 323 #define FW_FILTER_WR_L2TIX_S    0
 324 #define FW_FILTER_WR_L2TIX_M    0xfff
 325 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 326 #define FW_FILTER_WR_L2TIX_G(x) \
 327         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 328
 329 #define FW_FILTER_WR_FRAG_S     7
 330 #define FW_FILTER_WR_FRAG_M     0x1
 331 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 332 #define FW_FILTER_WR_FRAG_G(x)  \
 333         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 334 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 335
 336 #define FW_FILTER_WR_FRAGM_S    6
 337 #define FW_FILTER_WR_FRAGM_M    0x1
 338 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 339 #define FW_FILTER_WR_FRAGM_G(x) \
 340         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 341 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 342
 343 #define FW_FILTER_WR_IVLAN_VLD_S        5
 344 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 345 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 346 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 347         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 348 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 349
 350 #define FW_FILTER_WR_OVLAN_VLD_S        4
 351 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 352 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 353 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 354         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 355 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 356
 357 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 358 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 359 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 360 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 361         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 362 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 363
 364 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 365 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 366 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 367 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 368         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 369 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 370
 371 #define FW_FILTER_WR_RX_CHAN_S          15
 372 #define FW_FILTER_WR_RX_CHAN_M          0x1
 373 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 374 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 375         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 376 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 377
 378 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 379 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 380 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 381 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 382         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 383
 384 #define FW_FILTER_WR_MACI_S     23
 385 #define FW_FILTER_WR_MACI_M     0x1ff
 386 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 387 #define FW_FILTER_WR_MACI_G(x)  \
 388         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 389
 390 #define FW_FILTER_WR_MACIM_S    14
 391 #define FW_FILTER_WR_MACIM_M    0x1ff
 392 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 393 #define FW_FILTER_WR_MACIM_G(x) \
 394         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 395
 396 #define FW_FILTER_WR_FCOE_S     13
 397 #define FW_FILTER_WR_FCOE_M     0x1
 398 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 399 #define FW_FILTER_WR_FCOE_G(x)  \
 400         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 401 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 402
 403 #define FW_FILTER_WR_FCOEM_S    12
 404 #define FW_FILTER_WR_FCOEM_M    0x1
 405 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 406 #define FW_FILTER_WR_FCOEM_G(x) \
 407         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 408 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 409
 410 #define FW_FILTER_WR_PORT_S     9
 411 #define FW_FILTER_WR_PORT_M     0x7
 412 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 413 #define FW_FILTER_WR_PORT_G(x)  \
 414         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 415
 416 #define FW_FILTER_WR_PORTM_S    6
 417 #define FW_FILTER_WR_PORTM_M    0x7
 418 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 419 #define FW_FILTER_WR_PORTM_G(x) \
 420         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 421
 422 #define FW_FILTER_WR_MATCHTYPE_S        3
 423 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 424 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 425 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 426         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 427
 428 #define FW_FILTER_WR_MATCHTYPEM_S       0
 429 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 430 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 431 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 432         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 433
 434 struct fw_ulptx_wr {
 435         __be32 op_to_compl;
 436         __be32 flowid_len16;
 437         u64 cookie;
 438 };
 439
 440 struct fw_tp_wr {
 441         __be32 op_to_immdlen;
 442         __be32 flowid_len16;
 443         u64 cookie;
 444 };
 445
 446 struct fw_eth_tx_pkt_wr {
 447         __be32 op_immdlen;
 448         __be32 equiq_to_len16;
 449         __be64 r3;
 450 };
 451
 452 struct fw_ofld_connection_wr {
 453         __be32 op_compl;
 454         __be32 len16_pkd;
 455         __u64  cookie;
 456         __be64 r2;
 457         __be64 r3;
 458         struct fw_ofld_connection_le {
 459                 __be32 version_cpl;
 460                 __be32 filter;
 461                 __be32 r1;
 462                 __be16 lport;
 463                 __be16 pport;
 464                 union fw_ofld_connection_leip {
 465                         struct fw_ofld_connection_le_ipv4 {
 466                                 __be32 pip;
 467                                 __be32 lip;
 468                                 __be64 r0;
 469                                 __be64 r1;
 470                                 __be64 r2;
 471                         } ipv4;
 472                         struct fw_ofld_connection_le_ipv6 {
 473                                 __be64 pip_hi;
 474                                 __be64 pip_lo;
 475                                 __be64 lip_hi;
 476                                 __be64 lip_lo;
 477                         } ipv6;
 478                 } u;
 479         } le;
 480         struct fw_ofld_connection_tcb {
 481                 __be32 t_state_to_astid;
 482                 __be16 cplrxdataack_cplpassacceptrpl;
 483                 __be16 rcv_adv;
 484                 __be32 rcv_nxt;
 485                 __be32 tx_max;
 486                 __be64 opt0;
 487                 __be32 opt2;
 488                 __be32 r1;
 489                 __be64 r2;
 490                 __be64 r3;
 491         } tcb;
 492 };
 493
 494 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 495 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 496 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 497         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 498 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 499         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 500         FW_OFLD_CONNECTION_WR_VERSION_M)
 501 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 502         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 503
 504 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 505 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 506 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 507 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 508         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 509 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 510
 511 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 512 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 513 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 514         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 515 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 516         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 517         FW_OFLD_CONNECTION_WR_T_STATE_M)
 518
 519 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 522         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 524         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 525         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 526
 527 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 528 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 529 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 530         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 531 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 532         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 533
 534 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 537         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 539         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 540         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 542         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 543
 544 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 547         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 549         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 550         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 552         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 553
 554 enum fw_flowc_mnem {
 555         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 556         FW_FLOWC_MNEM_CH,
 557         FW_FLOWC_MNEM_PORT,
 558         FW_FLOWC_MNEM_IQID,
 559         FW_FLOWC_MNEM_SNDNXT,
 560         FW_FLOWC_MNEM_RCVNXT,
 561         FW_FLOWC_MNEM_SNDBUF,
 562         FW_FLOWC_MNEM_MSS,
 563         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 564         FW_FLOWC_MNEM_SCHEDCLASS = 11,
 565 };
 566
 567 struct fw_flowc_mnemval {
 568         u8 mnemonic;
 569         u8 r4[3];
 570         __be32 val;
 571 };
 572
 573 struct fw_flowc_wr {
 574         __be32 op_to_nparams;
 575         __be32 flowid_len16;
 576         struct fw_flowc_mnemval mnemval[0];
 577 };
 578
 579 #define FW_FLOWC_WR_NPARAMS_S           0
 580 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 581
 582 struct fw_ofld_tx_data_wr {
 583         __be32 op_to_immdlen;
 584         __be32 flowid_len16;
 585         __be32 plen;
 586         __be32 tunnel_to_proxy;
 587 };
 588
 589 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 590 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 591
 592 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 593 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 594
 595 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 596 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 597 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 598
 599 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 600 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 601
 602 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 603 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 604
 605 #define FW_OFLD_TX_DATA_WR_SHOVE_S      14
 606 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 607 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 608
 609 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 610 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 611
 612 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 613 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 614         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 615
 616 struct fw_cmd_wr {
 617         __be32 op_dma;
 618         __be32 len16_pkd;
 619         __be64 cookie_daddr;
 620 };
 621
 622 #define FW_CMD_WR_DMA_S         17
 623 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 624
 625 struct fw_eth_tx_pkt_vm_wr {
 626         __be32 op_immdlen;
 627         __be32 equiq_to_len16;
 628         __be32 r3[2];
 629         u8 ethmacdst[6];
 630         u8 ethmacsrc[6];
 631         __be16 ethtype;
 632         __be16 vlantci;
 633 };
 634
 635 #define FW_CMD_MAX_TIMEOUT 10000
 636
 637 /*
 638  * If a host driver does a HELLO and discovers that there's already a MASTER
 639  * selected, we may have to wait for that MASTER to finish issuing RESET,
 640  * configuration and INITIALIZE commands.  Also, there's a possibility that
 641  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 642  * RESET command, so we need to be willing to make a few retries of our HELLO.
 643  */
 644 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 645 #define FW_CMD_HELLO_RETRIES    3
 646
 647
 648 enum fw_cmd_opcodes {
 649         FW_LDST_CMD                    = 0x01,
 650         FW_RESET_CMD                   = 0x03,
 651         FW_HELLO_CMD                   = 0x04,
 652         FW_BYE_CMD                     = 0x05,
 653         FW_INITIALIZE_CMD              = 0x06,
 654         FW_CAPS_CONFIG_CMD             = 0x07,
 655         FW_PARAMS_CMD                  = 0x08,
 656         FW_PFVF_CMD                    = 0x09,
 657         FW_IQ_CMD                      = 0x10,
 658         FW_EQ_MNGT_CMD                 = 0x11,
 659         FW_EQ_ETH_CMD                  = 0x12,
 660         FW_EQ_CTRL_CMD                 = 0x13,
 661         FW_EQ_OFLD_CMD                 = 0x21,
 662         FW_VI_CMD                      = 0x14,
 663         FW_VI_MAC_CMD                  = 0x15,
 664         FW_VI_RXMODE_CMD               = 0x16,
 665         FW_VI_ENABLE_CMD               = 0x17,
 666         FW_ACL_MAC_CMD                 = 0x18,
 667         FW_ACL_VLAN_CMD                = 0x19,
 668         FW_VI_STATS_CMD                = 0x1a,
 669         FW_PORT_CMD                    = 0x1b,
 670         FW_PORT_STATS_CMD              = 0x1c,
 671         FW_PORT_LB_STATS_CMD           = 0x1d,
 672         FW_PORT_TRACE_CMD              = 0x1e,
 673         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 674         FW_RSS_IND_TBL_CMD             = 0x20,
 675         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 676         FW_RSS_VI_CONFIG_CMD           = 0x23,
 677         FW_DEVLOG_CMD                  = 0x25,
 678         FW_CLIP_CMD                    = 0x28,
 679         FW_LASTC2E_CMD                 = 0x40,
 680         FW_ERROR_CMD                   = 0x80,
 681         FW_DEBUG_CMD                   = 0x81,
 682 };
 683
 684 enum fw_cmd_cap {
 685         FW_CMD_CAP_PF                  = 0x01,
 686         FW_CMD_CAP_DMAQ                = 0x02,
 687         FW_CMD_CAP_PORT                = 0x04,
 688         FW_CMD_CAP_PORTPROMISC         = 0x08,
 689         FW_CMD_CAP_PORTSTATS           = 0x10,
 690         FW_CMD_CAP_VF                  = 0x80,
 691 };
 692
 693 /*
 694  * Generic command header flit0
 695  */
 696 struct fw_cmd_hdr {
 697         __be32 hi;
 698         __be32 lo;
 699 };
 700
 701 #define FW_CMD_OP_S             24
 702 #define FW_CMD_OP_M             0xff
 703 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 704 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 705
 706 #define FW_CMD_REQUEST_S        23
 707 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 708 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 709
 710 #define FW_CMD_READ_S           22
 711 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 712 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 713
 714 #define FW_CMD_WRITE_S          21
 715 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 716 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 717
 718 #define FW_CMD_EXEC_S           20
 719 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 720 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 721
 722 #define FW_CMD_RAMASK_S         20
 723 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 724
 725 #define FW_CMD_RETVAL_S         8
 726 #define FW_CMD_RETVAL_M         0xff
 727 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 728 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 729
 730 #define FW_CMD_LEN16_S          0
 731 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 732
 733 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 734
 735 enum fw_ldst_addrspc {
 736         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 737         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 738         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 739         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 740         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 741         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 742         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 743         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 744         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 745         FW_LDST_ADDRSPC_MPS       = 0x0020,
 746         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 747         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 748 };
 749
 750 enum fw_ldst_mps_fid {
 751         FW_LDST_MPS_ATRB,
 752         FW_LDST_MPS_RPLC
 753 };
 754
 755 enum fw_ldst_func_access_ctl {
 756         FW_LDST_FUNC_ACC_CTL_VIID,
 757         FW_LDST_FUNC_ACC_CTL_FID
 758 };
 759
 760 enum fw_ldst_func_mod_index {
 761         FW_LDST_FUNC_MPS
 762 };
 763
 764 struct fw_ldst_cmd {
 765         __be32 op_to_addrspace;
 766         __be32 cycles_to_len16;
 767         union fw_ldst {
 768                 struct fw_ldst_addrval {
 769                         __be32 addr;
 770                         __be32 val;
 771                 } addrval;
 772                 struct fw_ldst_idctxt {
 773                         __be32 physid;
 774                         __be32 msg_ctxtflush;
 775                         __be32 ctxt_data7;
 776                         __be32 ctxt_data6;
 777                         __be32 ctxt_data5;
 778                         __be32 ctxt_data4;
 779                         __be32 ctxt_data3;
 780                         __be32 ctxt_data2;
 781                         __be32 ctxt_data1;
 782                         __be32 ctxt_data0;
 783                 } idctxt;
 784                 struct fw_ldst_mdio {
 785                         __be16 paddr_mmd;
 786                         __be16 raddr;
 787                         __be16 vctl;
 788                         __be16 rval;
 789                 } mdio;
 790                 struct fw_ldst_cim_rq {
 791                         u8 req_first64[8];
 792                         u8 req_second64[8];
 793                         u8 resp_first64[8];
 794                         u8 resp_second64[8];
 795                         __be32 r3[2];
 796                 } cim_rq;
 797                 union fw_ldst_mps {
 798                         struct fw_ldst_mps_rplc {
 799                                 __be16 fid_idx;
 800                                 __be16 rplcpf_pkd;
 801                                 __be32 rplc255_224;
 802                                 __be32 rplc223_192;
 803                                 __be32 rplc191_160;
 804                                 __be32 rplc159_128;
 805                                 __be32 rplc127_96;
 806                                 __be32 rplc95_64;
 807                                 __be32 rplc63_32;
 808                                 __be32 rplc31_0;
 809                         } rplc;
 810                         struct fw_ldst_mps_atrb {
 811                                 __be16 fid_mpsid;
 812                                 __be16 r2[3];
 813                                 __be32 r3[2];
 814                                 __be32 r4;
 815                                 __be32 atrb;
 816                                 __be16 vlan[16];
 817                         } atrb;
 818                 } mps;
 819                 struct fw_ldst_func {
 820                         u8 access_ctl;
 821                         u8 mod_index;
 822                         __be16 ctl_id;
 823                         __be32 offset;
 824                         __be64 data0;
 825                         __be64 data1;
 826                 } func;
 827                 struct fw_ldst_pcie {
 828                         u8 ctrl_to_fn;
 829                         u8 bnum;
 830                         u8 r;
 831                         u8 ext_r;
 832                         u8 select_naccess;
 833                         u8 pcie_fn;
 834                         __be16 nset_pkd;
 835                         __be32 data[12];
 836                 } pcie;
 837                 struct fw_ldst_i2c_deprecated {
 838                         u8 pid_pkd;
 839                         u8 base;
 840                         u8 boffset;
 841                         u8 data;
 842                         __be32 r9;
 843                 } i2c_deprecated;
 844                 struct fw_ldst_i2c {
 845                         u8 pid;
 846                         u8 did;
 847                         u8 boffset;
 848                         u8 blen;
 849                         __be32 r9;
 850                         __u8   data[48];
 851                 } i2c;
 852                 struct fw_ldst_le {
 853                         __be32 index;
 854                         __be32 r9;
 855                         u8 val[33];
 856                         u8 r11[7];
 857                 } le;
 858         } u;
 859 };
 860
 861 #define FW_LDST_CMD_ADDRSPACE_S         0
 862 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
 863
 864 #define FW_LDST_CMD_MSG_S       31
 865 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
 866
 867 #define FW_LDST_CMD_CTXTFLUSH_S         30
 868 #define FW_LDST_CMD_CTXTFLUSH_V(x)      ((x) << FW_LDST_CMD_CTXTFLUSH_S)
 869 #define FW_LDST_CMD_CTXTFLUSH_F         FW_LDST_CMD_CTXTFLUSH_V(1U)
 870
 871 #define FW_LDST_CMD_PADDR_S     8
 872 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
 873
 874 #define FW_LDST_CMD_MMD_S       0
 875 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
 876
 877 #define FW_LDST_CMD_FID_S       15
 878 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
 879
 880 #define FW_LDST_CMD_IDX_S       0
 881 #define FW_LDST_CMD_IDX_V(x)    ((x) << FW_LDST_CMD_IDX_S)
 882
 883 #define FW_LDST_CMD_RPLCPF_S    0
 884 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
 885
 886 #define FW_LDST_CMD_LC_S        4
 887 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
 888 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
 889
 890 #define FW_LDST_CMD_FN_S        0
 891 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
 892
 893 #define FW_LDST_CMD_NACCESS_S           0
 894 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
 895
 896 struct fw_reset_cmd {
 897         __be32 op_to_write;
 898         __be32 retval_len16;
 899         __be32 val;
 900         __be32 halt_pkd;
 901 };
 902
 903 #define FW_RESET_CMD_HALT_S     31
 904 #define FW_RESET_CMD_HALT_M     0x1
 905 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
 906 #define FW_RESET_CMD_HALT_G(x)  \
 907         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
 908 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
 909
 910 enum fw_hellow_cmd {
 911         fw_hello_cmd_stage_os           = 0x0
 912 };
 913
 914 struct fw_hello_cmd {
 915         __be32 op_to_write;
 916         __be32 retval_len16;
 917         __be32 err_to_clearinit;
 918         __be32 fwrev;
 919 };
 920
 921 #define FW_HELLO_CMD_ERR_S      31
 922 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
 923 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
 924
 925 #define FW_HELLO_CMD_INIT_S     30
 926 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
 927 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
 928
 929 #define FW_HELLO_CMD_MASTERDIS_S        29
 930 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
 931
 932 #define FW_HELLO_CMD_MASTERFORCE_S      28
 933 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
 934
 935 #define FW_HELLO_CMD_MBMASTER_S         24
 936 #define FW_HELLO_CMD_MBMASTER_M         0xfU
 937 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
 938 #define FW_HELLO_CMD_MBMASTER_G(x)      \
 939         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
 940
 941 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
 942 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
 943
 944 #define FW_HELLO_CMD_MBASYNCNOT_S       20
 945 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
 946
 947 #define FW_HELLO_CMD_STAGE_S            17
 948 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
 949
 950 #define FW_HELLO_CMD_CLEARINIT_S        16
 951 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
 952 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
 953
 954 struct fw_bye_cmd {
 955         __be32 op_to_write;
 956         __be32 retval_len16;
 957         __be64 r3;
 958 };
 959
 960 struct fw_initialize_cmd {
 961         __be32 op_to_write;
 962         __be32 retval_len16;
 963         __be64 r3;
 964 };
 965
 966 enum fw_caps_config_hm {
 967         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
 968         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
 969         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
 970         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
 971         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
 972         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
 973         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
 974         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
 975         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
 976         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
 977         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
 978         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
 979         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
 980         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
 981         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
 982         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
 983         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
 984         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
 985         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
 986         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
 987         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
 988         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
 989         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
 990         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
 991 };
 992
 993 enum fw_caps_config_nbm {
 994         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
 995         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
 996 };
 997
 998 enum fw_caps_config_link {
 999         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
1000         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
1001         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
1002 };
1003
1004 enum fw_caps_config_switch {
1005         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
1006         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
1007 };
1008
1009 enum fw_caps_config_nic {
1010         FW_CAPS_CONFIG_NIC              = 0x00000001,
1011         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
1012 };
1013
1014 enum fw_caps_config_ofld {
1015         FW_CAPS_CONFIG_OFLD             = 0x00000001,
1016 };
1017
1018 enum fw_caps_config_rdma {
1019         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
1020         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
1021 };
1022
1023 enum fw_caps_config_iscsi {
1024         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1025         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1026         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1027         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1028 };
1029
1030 enum fw_caps_config_fcoe {
1031         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
1032         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
1033         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
1034 };
1035
1036 enum fw_memtype_cf {
1037         FW_MEMTYPE_CF_EDC0              = 0x0,
1038         FW_MEMTYPE_CF_EDC1              = 0x1,
1039         FW_MEMTYPE_CF_EXTMEM            = 0x2,
1040         FW_MEMTYPE_CF_FLASH             = 0x4,
1041         FW_MEMTYPE_CF_INTERNAL          = 0x5,
1042         FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1043 };
1044
1045 struct fw_caps_config_cmd {
1046         __be32 op_to_write;
1047         __be32 cfvalid_to_len16;
1048         __be32 r2;
1049         __be32 hwmbitmap;
1050         __be16 nbmcaps;
1051         __be16 linkcaps;
1052         __be16 switchcaps;
1053         __be16 r3;
1054         __be16 niccaps;
1055         __be16 ofldcaps;
1056         __be16 rdmacaps;
1057         __be16 r4;
1058         __be16 iscsicaps;
1059         __be16 fcoecaps;
1060         __be32 cfcsum;
1061         __be32 finiver;
1062         __be32 finicsum;
1063 };
1064
1065 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1066 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1067 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1068
1069 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1070 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1071         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1072
1073 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1074 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1075         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1076
1077 /*
1078  * params command mnemonics
1079  */
1080 enum fw_params_mnem {
1081         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1082         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1083         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1084         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1085         FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1086         FW_PARAMS_MNEM_LAST
1087 };
1088
1089 /*
1090  * device parameters
1091  */
1092 enum fw_params_param_dev {
1093         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1094         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1095         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1096                                                  * allocated by the device's
1097                                                  * Lookup Engine
1098                                                  */
1099         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1100         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1101         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1102         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1103         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1104         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1105         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1106         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1107         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1108         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1109         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1110         FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1111         FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1112         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1113         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1114         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1115         FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1116 };
1117
1118 /*
1119  * physical and virtual function parameters
1120  */
1121 enum fw_params_param_pfvf {
1122         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1123         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1124         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1125         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1126         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1127         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1128         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1129         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1130         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1131         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1132         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1133         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1134         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1135         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1136         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1137         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1138         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1139         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1140         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1141         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1142         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1143         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1144         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1145         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1146         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1147         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1148         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1149         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1150         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1151         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1152         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1153         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1154         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1155         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1156         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1157         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1158         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1159         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1160         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1161 };
1162
1163 /*
1164  * dma queue parameters
1165  */
1166 enum fw_params_param_dmaq {
1167         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1168         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1169         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1170         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1171         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1172         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1173         FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1174 };
1175
1176 enum fw_params_param_dev_phyfw {
1177         FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1178         FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1179 };
1180
1181 enum fw_params_param_dev_diag {
1182         FW_PARAM_DEV_DIAG_TMP           = 0x00,
1183         FW_PARAM_DEV_DIAG_VDD           = 0x01,
1184 };
1185
1186 enum fw_params_param_dev_fwcache {
1187         FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1188         FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1189 };
1190
1191 #define FW_PARAMS_MNEM_S        24
1192 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1193
1194 #define FW_PARAMS_PARAM_X_S     16
1195 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1196
1197 #define FW_PARAMS_PARAM_Y_S     8
1198 #define FW_PARAMS_PARAM_Y_M     0xffU
1199 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1200 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1201                 FW_PARAMS_PARAM_Y_M)
1202
1203 #define FW_PARAMS_PARAM_Z_S     0
1204 #define FW_PARAMS_PARAM_Z_M     0xffu
1205 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1206 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1207                 FW_PARAMS_PARAM_Z_M)
1208
1209 #define FW_PARAMS_PARAM_XYZ_S           0
1210 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1211
1212 #define FW_PARAMS_PARAM_YZ_S            0
1213 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1214
1215 struct fw_params_cmd {
1216         __be32 op_to_vfn;
1217         __be32 retval_len16;
1218         struct fw_params_param {
1219                 __be32 mnem;
1220                 __be32 val;
1221         } param[7];
1222 };
1223
1224 #define FW_PARAMS_CMD_PFN_S     8
1225 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1226
1227 #define FW_PARAMS_CMD_VFN_S     0
1228 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1229
1230 struct fw_pfvf_cmd {
1231         __be32 op_to_vfn;
1232         __be32 retval_len16;
1233         __be32 niqflint_niq;
1234         __be32 type_to_neq;
1235         __be32 tc_to_nexactf;
1236         __be32 r_caps_to_nethctrl;
1237         __be16 nricq;
1238         __be16 nriqp;
1239         __be32 r4;
1240 };
1241
1242 #define FW_PFVF_CMD_PFN_S       8
1243 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1244
1245 #define FW_PFVF_CMD_VFN_S       0
1246 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1247
1248 #define FW_PFVF_CMD_NIQFLINT_S          20
1249 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1250 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1251 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1252         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1253
1254 #define FW_PFVF_CMD_NIQ_S       0
1255 #define FW_PFVF_CMD_NIQ_M       0xfffff
1256 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1257 #define FW_PFVF_CMD_NIQ_G(x)    \
1258         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1259
1260 #define FW_PFVF_CMD_TYPE_S      31
1261 #define FW_PFVF_CMD_TYPE_M      0x1
1262 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1263 #define FW_PFVF_CMD_TYPE_G(x)   \
1264         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1265 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1266
1267 #define FW_PFVF_CMD_CMASK_S     24
1268 #define FW_PFVF_CMD_CMASK_M     0xf
1269 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1270 #define FW_PFVF_CMD_CMASK_G(x)  \
1271         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1272
1273 #define FW_PFVF_CMD_PMASK_S     20
1274 #define FW_PFVF_CMD_PMASK_M     0xf
1275 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1276 #define FW_PFVF_CMD_PMASK_G(x) \
1277         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1278
1279 #define FW_PFVF_CMD_NEQ_S       0
1280 #define FW_PFVF_CMD_NEQ_M       0xfffff
1281 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1282 #define FW_PFVF_CMD_NEQ_G(x)    \
1283         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1284
1285 #define FW_PFVF_CMD_TC_S        24
1286 #define FW_PFVF_CMD_TC_M        0xff
1287 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1288 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1289
1290 #define FW_PFVF_CMD_NVI_S       16
1291 #define FW_PFVF_CMD_NVI_M       0xff
1292 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1293 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1294
1295 #define FW_PFVF_CMD_NEXACTF_S           0
1296 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1297 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1298 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1299         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1300
1301 #define FW_PFVF_CMD_R_CAPS_S    24
1302 #define FW_PFVF_CMD_R_CAPS_M    0xff
1303 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1304 #define FW_PFVF_CMD_R_CAPS_G(x) \
1305         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1306
1307 #define FW_PFVF_CMD_WX_CAPS_S           16
1308 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1309 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1310 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1311         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1312
1313 #define FW_PFVF_CMD_NETHCTRL_S          0
1314 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1315 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1316 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1317         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1318
1319 enum fw_iq_type {
1320         FW_IQ_TYPE_FL_INT_CAP,
1321         FW_IQ_TYPE_NO_FL_INT_CAP
1322 };
1323
1324 struct fw_iq_cmd {
1325         __be32 op_to_vfn;
1326         __be32 alloc_to_len16;
1327         __be16 physiqid;
1328         __be16 iqid;
1329         __be16 fl0id;
1330         __be16 fl1id;
1331         __be32 type_to_iqandstindex;
1332         __be16 iqdroprss_to_iqesize;
1333         __be16 iqsize;
1334         __be64 iqaddr;
1335         __be32 iqns_to_fl0congen;
1336         __be16 fl0dcaen_to_fl0cidxfthresh;
1337         __be16 fl0size;
1338         __be64 fl0addr;
1339         __be32 fl1cngchmap_to_fl1congen;
1340         __be16 fl1dcaen_to_fl1cidxfthresh;
1341         __be16 fl1size;
1342         __be64 fl1addr;
1343 };
1344
1345 #define FW_IQ_CMD_PFN_S         8
1346 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1347
1348 #define FW_IQ_CMD_VFN_S         0
1349 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1350
1351 #define FW_IQ_CMD_ALLOC_S       31
1352 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1353 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1354
1355 #define FW_IQ_CMD_FREE_S        30
1356 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1357 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1358
1359 #define FW_IQ_CMD_MODIFY_S      29
1360 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1361 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1362
1363 #define FW_IQ_CMD_IQSTART_S     28
1364 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1365 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1366
1367 #define FW_IQ_CMD_IQSTOP_S      27
1368 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1369 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1370
1371 #define FW_IQ_CMD_TYPE_S        29
1372 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1373
1374 #define FW_IQ_CMD_IQASYNCH_S    28
1375 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1376
1377 #define FW_IQ_CMD_VIID_S        16
1378 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1379
1380 #define FW_IQ_CMD_IQANDST_S     15
1381 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1382
1383 #define FW_IQ_CMD_IQANUS_S      14
1384 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1385
1386 #define FW_IQ_CMD_IQANUD_S      12
1387 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1388
1389 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1390 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1391
1392 #define FW_IQ_CMD_IQDROPRSS_S           15
1393 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1394 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1395
1396 #define FW_IQ_CMD_IQGTSMODE_S           14
1397 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1398 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1399
1400 #define FW_IQ_CMD_IQPCIECH_S    12
1401 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1402
1403 #define FW_IQ_CMD_IQDCAEN_S     11
1404 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1405
1406 #define FW_IQ_CMD_IQDCACPU_S    6
1407 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1408
1409 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1410 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1411
1412 #define FW_IQ_CMD_IQO_S         3
1413 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1414 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1415
1416 #define FW_IQ_CMD_IQCPRIO_S     2
1417 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1418
1419 #define FW_IQ_CMD_IQESIZE_S     0
1420 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1421
1422 #define FW_IQ_CMD_IQNS_S        31
1423 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1424
1425 #define FW_IQ_CMD_IQRO_S        30
1426 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1427
1428 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1429 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1430
1431 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1432 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1433 #define FW_IQ_CMD_IQFLINTCONGEN_F       FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1434
1435 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1436 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1437
1438 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1439 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1440
1441 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1442 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1443
1444 #define FW_IQ_CMD_FL0DBP_S      14
1445 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1446
1447 #define FW_IQ_CMD_FL0DATANS_S           13
1448 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1449
1450 #define FW_IQ_CMD_FL0DATARO_S           12
1451 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1452 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1453
1454 #define FW_IQ_CMD_FL0CONGCIF_S          11
1455 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1456 #define FW_IQ_CMD_FL0CONGCIF_F          FW_IQ_CMD_FL0CONGCIF_V(1U)
1457
1458 #define FW_IQ_CMD_FL0ONCHIP_S           10
1459 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1460
1461 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1462 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1463
1464 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1465 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1466
1467 #define FW_IQ_CMD_FL0FETCHNS_S          7
1468 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1469
1470 #define FW_IQ_CMD_FL0FETCHRO_S          6
1471 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1472 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1473
1474 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1475 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1476
1477 #define FW_IQ_CMD_FL0CPRIO_S    3
1478 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1479
1480 #define FW_IQ_CMD_FL0PADEN_S    2
1481 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1482 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1483
1484 #define FW_IQ_CMD_FL0PACKEN_S           1
1485 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1486 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1487
1488 #define FW_IQ_CMD_FL0CONGEN_S           0
1489 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1490 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1491
1492 #define FW_IQ_CMD_FL0DCAEN_S    15
1493 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1494
1495 #define FW_IQ_CMD_FL0DCACPU_S           10
1496 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1497
1498 #define FW_IQ_CMD_FL0FBMIN_S    7
1499 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1500
1501 #define FW_IQ_CMD_FL0FBMAX_S    4
1502 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1503
1504 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1505 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1506 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1507
1508 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1509 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1510
1511 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1512 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1513
1514 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1515 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1516
1517 #define FW_IQ_CMD_FL1DBP_S      14
1518 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1519
1520 #define FW_IQ_CMD_FL1DATANS_S           13
1521 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1522
1523 #define FW_IQ_CMD_FL1DATARO_S           12
1524 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1525
1526 #define FW_IQ_CMD_FL1CONGCIF_S          11
1527 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1528
1529 #define FW_IQ_CMD_FL1ONCHIP_S           10
1530 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1531
1532 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1533 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1534
1535 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1536 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1537
1538 #define FW_IQ_CMD_FL1FETCHNS_S          7
1539 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1540
1541 #define FW_IQ_CMD_FL1FETCHRO_S          6
1542 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1543
1544 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1545 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1546
1547 #define FW_IQ_CMD_FL1CPRIO_S    3
1548 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1549
1550 #define FW_IQ_CMD_FL1PADEN_S    2
1551 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1552 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1553
1554 #define FW_IQ_CMD_FL1PACKEN_S           1
1555 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1556 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1557
1558 #define FW_IQ_CMD_FL1CONGEN_S           0
1559 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1560 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1561
1562 #define FW_IQ_CMD_FL1DCAEN_S    15
1563 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1564
1565 #define FW_IQ_CMD_FL1DCACPU_S           10
1566 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1567
1568 #define FW_IQ_CMD_FL1FBMIN_S    7
1569 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1570
1571 #define FW_IQ_CMD_FL1FBMAX_S    4
1572 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1573
1574 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1575 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1576 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1577
1578 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1579 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1580
1581 struct fw_eq_eth_cmd {
1582         __be32 op_to_vfn;
1583         __be32 alloc_to_len16;
1584         __be32 eqid_pkd;
1585         __be32 physeqid_pkd;
1586         __be32 fetchszm_to_iqid;
1587         __be32 dcaen_to_eqsize;
1588         __be64 eqaddr;
1589         __be32 viid_pkd;
1590         __be32 r8_lo;
1591         __be64 r9;
1592 };
1593
1594 #define FW_EQ_ETH_CMD_PFN_S     8
1595 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1596
1597 #define FW_EQ_ETH_CMD_VFN_S     0
1598 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1599
1600 #define FW_EQ_ETH_CMD_ALLOC_S           31
1601 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1602 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1603
1604 #define FW_EQ_ETH_CMD_FREE_S    30
1605 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1606 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1607
1608 #define FW_EQ_ETH_CMD_MODIFY_S          29
1609 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1610 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1611
1612 #define FW_EQ_ETH_CMD_EQSTART_S         28
1613 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1614 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1615
1616 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1617 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1618 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1619
1620 #define FW_EQ_ETH_CMD_EQID_S    0
1621 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1622 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1623 #define FW_EQ_ETH_CMD_EQID_G(x) \
1624         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1625
1626 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1627 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1628 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1629 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1630         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1631
1632 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1633 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1634 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1635
1636 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1637 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1638
1639 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1640 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1641
1642 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1643 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1644
1645 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1646 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1647 #define FW_EQ_ETH_CMD_FETCHRO_F         FW_EQ_ETH_CMD_FETCHRO_V(1U)
1648
1649 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1650 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1651
1652 #define FW_EQ_ETH_CMD_CPRIO_S           19
1653 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1654
1655 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1656 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1657
1658 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1659 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1660
1661 #define FW_EQ_ETH_CMD_IQID_S    0
1662 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1663
1664 #define FW_EQ_ETH_CMD_DCAEN_S           31
1665 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1666
1667 #define FW_EQ_ETH_CMD_DCACPU_S          26
1668 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1669
1670 #define FW_EQ_ETH_CMD_FBMIN_S           23
1671 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1672
1673 #define FW_EQ_ETH_CMD_FBMAX_S           20
1674 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1675
1676 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1677 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1678
1679 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1680 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1681
1682 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1683 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1684
1685 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1686 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1687 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1688
1689 #define FW_EQ_ETH_CMD_VIID_S    16
1690 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1691
1692 struct fw_eq_ctrl_cmd {
1693         __be32 op_to_vfn;
1694         __be32 alloc_to_len16;
1695         __be32 cmpliqid_eqid;
1696         __be32 physeqid_pkd;
1697         __be32 fetchszm_to_iqid;
1698         __be32 dcaen_to_eqsize;
1699         __be64 eqaddr;
1700 };
1701
1702 #define FW_EQ_CTRL_CMD_PFN_S    8
1703 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1704
1705 #define FW_EQ_CTRL_CMD_VFN_S    0
1706 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1707
1708 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1709 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1710 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1711
1712 #define FW_EQ_CTRL_CMD_FREE_S           30
1713 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1714 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1715
1716 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1717 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1718 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1719
1720 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1721 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1722 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1723
1724 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1725 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1726 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1727
1728 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1729 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1730
1731 #define FW_EQ_CTRL_CMD_EQID_S           0
1732 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1733 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1734 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1735         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1736
1737 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1738 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1739 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1740         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1741
1742 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1743 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1744 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1745
1746 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
1747 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1748 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1749
1750 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
1751 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1752 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1753
1754 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
1755 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1756 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1757
1758 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
1759 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1760 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1761
1762 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
1763 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1764
1765 #define FW_EQ_CTRL_CMD_CPRIO_S          19
1766 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1767
1768 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
1769 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1770
1771 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
1772 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1773
1774 #define FW_EQ_CTRL_CMD_IQID_S           0
1775 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
1776
1777 #define FW_EQ_CTRL_CMD_DCAEN_S          31
1778 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1779
1780 #define FW_EQ_CTRL_CMD_DCACPU_S         26
1781 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1782
1783 #define FW_EQ_CTRL_CMD_FBMIN_S          23
1784 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1785
1786 #define FW_EQ_CTRL_CMD_FBMAX_S          20
1787 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1788
1789 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
1790 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
1791         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1792
1793 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
1794 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1795
1796 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
1797 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1798
1799 struct fw_eq_ofld_cmd {
1800         __be32 op_to_vfn;
1801         __be32 alloc_to_len16;
1802         __be32 eqid_pkd;
1803         __be32 physeqid_pkd;
1804         __be32 fetchszm_to_iqid;
1805         __be32 dcaen_to_eqsize;
1806         __be64 eqaddr;
1807 };
1808
1809 #define FW_EQ_OFLD_CMD_PFN_S    8
1810 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1811
1812 #define FW_EQ_OFLD_CMD_VFN_S    0
1813 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1814
1815 #define FW_EQ_OFLD_CMD_ALLOC_S          31
1816 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1817 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
1818
1819 #define FW_EQ_OFLD_CMD_FREE_S           30
1820 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
1821 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
1822
1823 #define FW_EQ_OFLD_CMD_MODIFY_S         29
1824 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1825 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
1826
1827 #define FW_EQ_OFLD_CMD_EQSTART_S        28
1828 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1829 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
1830
1831 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
1832 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1833 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1834
1835 #define FW_EQ_OFLD_CMD_EQID_S           0
1836 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
1837 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
1838 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
1839         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1840
1841 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
1842 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
1843 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
1844         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1845
1846 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
1847 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1848
1849 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
1850 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1851
1852 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
1853 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1854
1855 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
1856 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1857
1858 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
1859 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1860 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1861
1862 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
1863 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1864
1865 #define FW_EQ_OFLD_CMD_CPRIO_S          19
1866 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1867
1868 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
1869 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1870
1871 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
1872 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1873
1874 #define FW_EQ_OFLD_CMD_IQID_S           0
1875 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
1876
1877 #define FW_EQ_OFLD_CMD_DCAEN_S          31
1878 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1879
1880 #define FW_EQ_OFLD_CMD_DCACPU_S         26
1881 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1882
1883 #define FW_EQ_OFLD_CMD_FBMIN_S          23
1884 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1885
1886 #define FW_EQ_OFLD_CMD_FBMAX_S          20
1887 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1888
1889 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
1890 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
1891         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1892
1893 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
1894 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1895
1896 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
1897 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1898
1899 /*
1900  * Macros for VIID parsing:
1901  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1902  */
1903
1904 #define FW_VIID_PFN_S           8
1905 #define FW_VIID_PFN_M           0x7
1906 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1907
1908 #define FW_VIID_VIVLD_S         7
1909 #define FW_VIID_VIVLD_M         0x1
1910 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1911
1912 #define FW_VIID_VIN_S           0
1913 #define FW_VIID_VIN_M           0x7F
1914 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1915
1916 struct fw_vi_cmd {
1917         __be32 op_to_vfn;
1918         __be32 alloc_to_len16;
1919         __be16 type_viid;
1920         u8 mac[6];
1921         u8 portid_pkd;
1922         u8 nmac;
1923         u8 nmac0[6];
1924         __be16 rsssize_pkd;
1925         u8 nmac1[6];
1926         __be16 idsiiq_pkd;
1927         u8 nmac2[6];
1928         __be16 idseiq_pkd;
1929         u8 nmac3[6];
1930         __be64 r9;
1931         __be64 r10;
1932 };
1933
1934 #define FW_VI_CMD_PFN_S         8
1935 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
1936
1937 #define FW_VI_CMD_VFN_S         0
1938 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
1939
1940 #define FW_VI_CMD_ALLOC_S       31
1941 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
1942 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
1943
1944 #define FW_VI_CMD_FREE_S        30
1945 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
1946 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
1947
1948 #define FW_VI_CMD_VIID_S        0
1949 #define FW_VI_CMD_VIID_M        0xfff
1950 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
1951 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1952
1953 #define FW_VI_CMD_PORTID_S      4
1954 #define FW_VI_CMD_PORTID_M      0xf
1955 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
1956 #define FW_VI_CMD_PORTID_G(x)   \
1957         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1958
1959 #define FW_VI_CMD_RSSSIZE_S     0
1960 #define FW_VI_CMD_RSSSIZE_M     0x7ff
1961 #define FW_VI_CMD_RSSSIZE_G(x)  \
1962         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1963
1964 /* Special VI_MAC command index ids */
1965 #define FW_VI_MAC_ADD_MAC               0x3FF
1966 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
1967 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
1968 #define FW_CLS_TCAM_NUM_ENTRIES         336
1969
1970 enum fw_vi_mac_smac {
1971         FW_VI_MAC_MPS_TCAM_ENTRY,
1972         FW_VI_MAC_MPS_TCAM_ONLY,
1973         FW_VI_MAC_SMT_ONLY,
1974         FW_VI_MAC_SMT_AND_MPSTCAM
1975 };
1976
1977 enum fw_vi_mac_result {
1978         FW_VI_MAC_R_SUCCESS,
1979         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1980         FW_VI_MAC_R_SMAC_FAIL,
1981         FW_VI_MAC_R_F_ACL_CHECK
1982 };
1983
1984 struct fw_vi_mac_cmd {
1985         __be32 op_to_viid;
1986         __be32 freemacs_to_len16;
1987         union fw_vi_mac {
1988                 struct fw_vi_mac_exact {
1989                         __be16 valid_to_idx;
1990                         u8 macaddr[6];
1991                 } exact[7];
1992                 struct fw_vi_mac_hash {
1993                         __be64 hashvec;
1994                 } hash;
1995         } u;
1996 };
1997
1998 #define FW_VI_MAC_CMD_VIID_S    0
1999 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2000
2001 #define FW_VI_MAC_CMD_FREEMACS_S        31
2002 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2003
2004 #define FW_VI_MAC_CMD_HASHVECEN_S       23
2005 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2006 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
2007
2008 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
2009 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2010
2011 #define FW_VI_MAC_CMD_VALID_S           15
2012 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
2013 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
2014
2015 #define FW_VI_MAC_CMD_PRIO_S    12
2016 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2017
2018 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
2019 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
2020 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2021 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
2022         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2023
2024 #define FW_VI_MAC_CMD_IDX_S     0
2025 #define FW_VI_MAC_CMD_IDX_M     0x3ff
2026 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
2027 #define FW_VI_MAC_CMD_IDX_G(x)  \
2028         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2029
2030 #define FW_RXMODE_MTU_NO_CHG    65535
2031
2032 struct fw_vi_rxmode_cmd {
2033         __be32 op_to_viid;
2034         __be32 retval_len16;
2035         __be32 mtu_to_vlanexen;
2036         __be32 r4_lo;
2037 };
2038
2039 #define FW_VI_RXMODE_CMD_VIID_S         0
2040 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
2041
2042 #define FW_VI_RXMODE_CMD_MTU_S          16
2043 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
2044 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
2045
2046 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
2047 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
2048 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2049
2050 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
2051 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
2052 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
2053         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2054
2055 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
2056 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
2057 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
2058         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2059
2060 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
2061 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
2062 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2063
2064 struct fw_vi_enable_cmd {
2065         __be32 op_to_viid;
2066         __be32 ien_to_len16;
2067         __be16 blinkdur;
2068         __be16 r3;
2069         __be32 r4;
2070 };
2071
2072 #define FW_VI_ENABLE_CMD_VIID_S         0
2073 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2074
2075 #define FW_VI_ENABLE_CMD_IEN_S          31
2076 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2077
2078 #define FW_VI_ENABLE_CMD_EEN_S          30
2079 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2080
2081 #define FW_VI_ENABLE_CMD_LED_S          29
2082 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2083 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2084
2085 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2086 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2087
2088 /* VI VF stats offset definitions */
2089 #define VI_VF_NUM_STATS 16
2090 enum fw_vi_stats_vf_index {
2091         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2092         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2093         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2094         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2095         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2096         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2097         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2098         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2099         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2100         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2101         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2102         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2103         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2104         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2105         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2106         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2107 };
2108
2109 /* VI PF stats offset definitions */
2110 #define VI_PF_NUM_STATS 17
2111 enum fw_vi_stats_pf_index {
2112         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2113         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2114         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2115         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2116         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2117         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2118         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2119         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2120         FW_VI_PF_STAT_RX_BYTES_IX,
2121         FW_VI_PF_STAT_RX_FRAMES_IX,
2122         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2123         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2124         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2125         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2126         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2127         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2128         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2129 };
2130
2131 struct fw_vi_stats_cmd {
2132         __be32 op_to_viid;
2133         __be32 retval_len16;
2134         union fw_vi_stats {
2135                 struct fw_vi_stats_ctl {
2136                         __be16 nstats_ix;
2137                         __be16 r6;
2138                         __be32 r7;
2139                         __be64 stat0;
2140                         __be64 stat1;
2141                         __be64 stat2;
2142                         __be64 stat3;
2143                         __be64 stat4;
2144                         __be64 stat5;
2145                 } ctl;
2146                 struct fw_vi_stats_pf {
2147                         __be64 tx_bcast_bytes;
2148                         __be64 tx_bcast_frames;
2149                         __be64 tx_mcast_bytes;
2150                         __be64 tx_mcast_frames;
2151                         __be64 tx_ucast_bytes;
2152                         __be64 tx_ucast_frames;
2153                         __be64 tx_offload_bytes;
2154                         __be64 tx_offload_frames;
2155                         __be64 rx_pf_bytes;
2156                         __be64 rx_pf_frames;
2157                         __be64 rx_bcast_bytes;
2158                         __be64 rx_bcast_frames;
2159                         __be64 rx_mcast_bytes;
2160                         __be64 rx_mcast_frames;
2161                         __be64 rx_ucast_bytes;
2162                         __be64 rx_ucast_frames;
2163                         __be64 rx_err_frames;
2164                 } pf;
2165                 struct fw_vi_stats_vf {
2166                         __be64 tx_bcast_bytes;
2167                         __be64 tx_bcast_frames;
2168                         __be64 tx_mcast_bytes;
2169                         __be64 tx_mcast_frames;
2170                         __be64 tx_ucast_bytes;
2171                         __be64 tx_ucast_frames;
2172                         __be64 tx_drop_frames;
2173                         __be64 tx_offload_bytes;
2174                         __be64 tx_offload_frames;
2175                         __be64 rx_bcast_bytes;
2176                         __be64 rx_bcast_frames;
2177                         __be64 rx_mcast_bytes;
2178                         __be64 rx_mcast_frames;
2179                         __be64 rx_ucast_bytes;
2180                         __be64 rx_ucast_frames;
2181                         __be64 rx_err_frames;
2182                 } vf;
2183         } u;
2184 };
2185
2186 #define FW_VI_STATS_CMD_VIID_S          0
2187 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2188
2189 #define FW_VI_STATS_CMD_NSTATS_S        12
2190 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2191
2192 #define FW_VI_STATS_CMD_IX_S    0
2193 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2194
2195 struct fw_acl_mac_cmd {
2196         __be32 op_to_vfn;
2197         __be32 en_to_len16;
2198         u8 nmac;
2199         u8 r3[7];
2200         __be16 r4;
2201         u8 macaddr0[6];
2202         __be16 r5;
2203         u8 macaddr1[6];
2204         __be16 r6;
2205         u8 macaddr2[6];
2206         __be16 r7;
2207         u8 macaddr3[6];
2208 };
2209
2210 #define FW_ACL_MAC_CMD_PFN_S    8
2211 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2212
2213 #define FW_ACL_MAC_CMD_VFN_S    0
2214 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2215
2216 #define FW_ACL_MAC_CMD_EN_S     31
2217 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2218
2219 struct fw_acl_vlan_cmd {
2220         __be32 op_to_vfn;
2221         __be32 en_to_len16;
2222         u8 nvlan;
2223         u8 dropnovlan_fm;
2224         u8 r3_lo[6];
2225         __be16 vlanid[16];
2226 };
2227
2228 #define FW_ACL_VLAN_CMD_PFN_S           8
2229 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2230
2231 #define FW_ACL_VLAN_CMD_VFN_S           0
2232 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2233
2234 #define FW_ACL_VLAN_CMD_EN_S    31
2235 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2236
2237 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2238 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2239
2240 #define FW_ACL_VLAN_CMD_FM_S    6
2241 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2242
2243 enum fw_port_cap {
2244         FW_PORT_CAP_SPEED_100M          = 0x0001,
2245         FW_PORT_CAP_SPEED_1G            = 0x0002,
2246         FW_PORT_CAP_SPEED_2_5G          = 0x0004,
2247         FW_PORT_CAP_SPEED_10G           = 0x0008,
2248         FW_PORT_CAP_SPEED_40G           = 0x0010,
2249         FW_PORT_CAP_SPEED_100G          = 0x0020,
2250         FW_PORT_CAP_FC_RX               = 0x0040,
2251         FW_PORT_CAP_FC_TX               = 0x0080,
2252         FW_PORT_CAP_ANEG                = 0x0100,
2253         FW_PORT_CAP_MDI_0               = 0x0200,
2254         FW_PORT_CAP_MDI_1               = 0x0400,
2255         FW_PORT_CAP_BEAN                = 0x0800,
2256         FW_PORT_CAP_PMA_LPBK            = 0x1000,
2257         FW_PORT_CAP_PCS_LPBK            = 0x2000,
2258         FW_PORT_CAP_PHYXS_LPBK          = 0x4000,
2259         FW_PORT_CAP_FAR_END_LPBK        = 0x8000,
2260 };
2261
2262 enum fw_port_mdi {
2263         FW_PORT_CAP_MDI_UNCHANGED,
2264         FW_PORT_CAP_MDI_AUTO,
2265         FW_PORT_CAP_MDI_F_STRAIGHT,
2266         FW_PORT_CAP_MDI_F_CROSSOVER
2267 };
2268
2269 #define FW_PORT_CAP_MDI_S 9
2270 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2271
2272 enum fw_port_action {
2273         FW_PORT_ACTION_L1_CFG           = 0x0001,
2274         FW_PORT_ACTION_L2_CFG           = 0x0002,
2275         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2276         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2277         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2278         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2279         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2280         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2281         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2282         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2283         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2284         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2285         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2286         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2287         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2288         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2289         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2290         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2291         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2292         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2293         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2294         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2295         FW_PORT_ACTION_AN_RESET         = 0x0045
2296 };
2297
2298 enum fw_port_l2cfg_ctlbf {
2299         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2300         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2301         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2302         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2303         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2304         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2305 };
2306
2307 enum fw_port_dcb_versions {
2308         FW_PORT_DCB_VER_UNKNOWN,
2309         FW_PORT_DCB_VER_CEE1D0,
2310         FW_PORT_DCB_VER_CEE1D01,
2311         FW_PORT_DCB_VER_IEEE,
2312         FW_PORT_DCB_VER_AUTO = 7
2313 };
2314
2315 enum fw_port_dcb_cfg {
2316         FW_PORT_DCB_CFG_PG      = 0x01,
2317         FW_PORT_DCB_CFG_PFC     = 0x02,
2318         FW_PORT_DCB_CFG_APPL    = 0x04
2319 };
2320
2321 enum fw_port_dcb_cfg_rc {
2322         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2323         FW_PORT_DCB_CFG_ERROR   = 0x1
2324 };
2325
2326 enum fw_port_dcb_type {
2327         FW_PORT_DCB_TYPE_PGID           = 0x00,
2328         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2329         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2330         FW_PORT_DCB_TYPE_PFC            = 0x03,
2331         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2332         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2333 };
2334
2335 enum fw_port_dcb_feature_state {
2336         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2337         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2338         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2339         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2340 };
2341
2342 struct fw_port_cmd {
2343         __be32 op_to_portid;
2344         __be32 action_to_len16;
2345         union fw_port {
2346                 struct fw_port_l1cfg {
2347                         __be32 rcap;
2348                         __be32 r;
2349                 } l1cfg;
2350                 struct fw_port_l2cfg {
2351                         __u8   ctlbf;
2352                         __u8   ovlan3_to_ivlan0;
2353                         __be16 ivlantype;
2354                         __be16 txipg_force_pinfo;
2355                         __be16 mtu;
2356                         __be16 ovlan0mask;
2357                         __be16 ovlan0type;
2358                         __be16 ovlan1mask;
2359                         __be16 ovlan1type;
2360                         __be16 ovlan2mask;
2361                         __be16 ovlan2type;
2362                         __be16 ovlan3mask;
2363                         __be16 ovlan3type;
2364                 } l2cfg;
2365                 struct fw_port_info {
2366                         __be32 lstatus_to_modtype;
2367                         __be16 pcap;
2368                         __be16 acap;
2369                         __be16 mtu;
2370                         __u8   cbllen;
2371                         __u8   auxlinfo;
2372                         __u8   dcbxdis_pkd;
2373                         __u8   r8_lo[3];
2374                         __be64 r9;
2375                 } info;
2376                 struct fw_port_diags {
2377                         __u8   diagop;
2378                         __u8   r[3];
2379                         __be32 diagval;
2380                 } diags;
2381                 union fw_port_dcb {
2382                         struct fw_port_dcb_pgid {
2383                                 __u8   type;
2384                                 __u8   apply_pkd;
2385                                 __u8   r10_lo[2];
2386                                 __be32 pgid;
2387                                 __be64 r11;
2388                         } pgid;
2389                         struct fw_port_dcb_pgrate {
2390                                 __u8   type;
2391                                 __u8   apply_pkd;
2392                                 __u8   r10_lo[5];
2393                                 __u8   num_tcs_supported;
2394                                 __u8   pgrate[8];
2395                                 __u8   tsa[8];
2396                         } pgrate;
2397                         struct fw_port_dcb_priorate {
2398                                 __u8   type;
2399                                 __u8   apply_pkd;
2400                                 __u8   r10_lo[6];
2401                                 __u8   strict_priorate[8];
2402                         } priorate;
2403                         struct fw_port_dcb_pfc {
2404                                 __u8   type;
2405                                 __u8   pfcen;
2406                                 __u8   r10[5];
2407                                 __u8   max_pfc_tcs;
2408                                 __be64 r11;
2409                         } pfc;
2410                         struct fw_port_app_priority {
2411                                 __u8   type;
2412                                 __u8   r10[2];
2413                                 __u8   idx;
2414                                 __u8   user_prio_map;
2415                                 __u8   sel_field;
2416                                 __be16 protocolid;
2417                                 __be64 r12;
2418                         } app_priority;
2419                         struct fw_port_dcb_control {
2420                                 __u8   type;
2421                                 __u8   all_syncd_pkd;
2422                                 __be16 dcb_version_to_app_state;
2423                                 __be32 r11;
2424                                 __be64 r12;
2425                         } control;
2426                 } dcb;
2427         } u;
2428 };
2429
2430 #define FW_PORT_CMD_READ_S      22
2431 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2432 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2433
2434 #define FW_PORT_CMD_PORTID_S    0
2435 #define FW_PORT_CMD_PORTID_M    0xf
2436 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2437 #define FW_PORT_CMD_PORTID_G(x) \
2438         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2439
2440 #define FW_PORT_CMD_ACTION_S    16
2441 #define FW_PORT_CMD_ACTION_M    0xffff
2442 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2443 #define FW_PORT_CMD_ACTION_G(x) \
2444         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2445
2446 #define FW_PORT_CMD_OVLAN3_S    7
2447 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2448
2449 #define FW_PORT_CMD_OVLAN2_S    6
2450 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2451
2452 #define FW_PORT_CMD_OVLAN1_S    5
2453 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2454
2455 #define FW_PORT_CMD_OVLAN0_S    4
2456 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2457
2458 #define FW_PORT_CMD_IVLAN0_S    3
2459 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2460
2461 #define FW_PORT_CMD_TXIPG_S     3
2462 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2463
2464 #define FW_PORT_CMD_LSTATUS_S           31
2465 #define FW_PORT_CMD_LSTATUS_M           0x1
2466 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2467 #define FW_PORT_CMD_LSTATUS_G(x)        \
2468         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2469 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2470
2471 #define FW_PORT_CMD_LSPEED_S    24
2472 #define FW_PORT_CMD_LSPEED_M    0x3f
2473 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2474 #define FW_PORT_CMD_LSPEED_G(x) \
2475         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2476
2477 #define FW_PORT_CMD_TXPAUSE_S           23
2478 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2479 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2480
2481 #define FW_PORT_CMD_RXPAUSE_S           22
2482 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2483 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2484
2485 #define FW_PORT_CMD_MDIOCAP_S           21
2486 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2487 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2488
2489 #define FW_PORT_CMD_MDIOADDR_S          16
2490 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2491 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2492         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2493
2494 #define FW_PORT_CMD_LPTXPAUSE_S         15
2495 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2496 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2497
2498 #define FW_PORT_CMD_LPRXPAUSE_S         14
2499 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2500 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2501
2502 #define FW_PORT_CMD_PTYPE_S     8
2503 #define FW_PORT_CMD_PTYPE_M     0x1f
2504 #define FW_PORT_CMD_PTYPE_G(x)  \
2505         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2506
2507 #define FW_PORT_CMD_MODTYPE_S           0
2508 #define FW_PORT_CMD_MODTYPE_M           0x1f
2509 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2510 #define FW_PORT_CMD_MODTYPE_G(x)        \
2511         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2512
2513 #define FW_PORT_CMD_DCBXDIS_S           7
2514 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2515 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2516
2517 #define FW_PORT_CMD_APPLY_S     7
2518 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2519 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2520
2521 #define FW_PORT_CMD_ALL_SYNCD_S         7
2522 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2523 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2524
2525 #define FW_PORT_CMD_DCB_VERSION_S       12
2526 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2527 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2528         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2529
2530 enum fw_port_type {
2531         FW_PORT_TYPE_FIBER_XFI,
2532         FW_PORT_TYPE_FIBER_XAUI,
2533         FW_PORT_TYPE_BT_SGMII,
2534         FW_PORT_TYPE_BT_XFI,
2535         FW_PORT_TYPE_BT_XAUI,
2536         FW_PORT_TYPE_KX4,
2537         FW_PORT_TYPE_CX4,
2538         FW_PORT_TYPE_KX,
2539         FW_PORT_TYPE_KR,
2540         FW_PORT_TYPE_SFP,
2541         FW_PORT_TYPE_BP_AP,
2542         FW_PORT_TYPE_BP4_AP,
2543         FW_PORT_TYPE_QSFP_10G,
2544         FW_PORT_TYPE_QSA,
2545         FW_PORT_TYPE_QSFP,
2546         FW_PORT_TYPE_BP40_BA,
2547
2548         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2549 };
2550
2551 enum fw_port_module_type {
2552         FW_PORT_MOD_TYPE_NA,
2553         FW_PORT_MOD_TYPE_LR,
2554         FW_PORT_MOD_TYPE_SR,
2555         FW_PORT_MOD_TYPE_ER,
2556         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2557         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2558         FW_PORT_MOD_TYPE_LRM,
2559         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
2560         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
2561         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
2562
2563         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2564 };
2565
2566 enum fw_port_mod_sub_type {
2567         FW_PORT_MOD_SUB_TYPE_NA,
2568         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2569         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2570         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2571         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2572         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2573         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2574
2575         /* The following will never been in the VPD.  They are TWINAX cable
2576          * lengths decoded from SFP+ module i2c PROMs.  These should
2577          * almost certainly go somewhere else ...
2578          */
2579         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2580         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2581         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2582         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2583 };
2584
2585 enum fw_port_stats_tx_index {
2586         FW_STAT_TX_PORT_BYTES_IX = 0,
2587         FW_STAT_TX_PORT_FRAMES_IX,
2588         FW_STAT_TX_PORT_BCAST_IX,
2589         FW_STAT_TX_PORT_MCAST_IX,
2590         FW_STAT_TX_PORT_UCAST_IX,
2591         FW_STAT_TX_PORT_ERROR_IX,
2592         FW_STAT_TX_PORT_64B_IX,
2593         FW_STAT_TX_PORT_65B_127B_IX,
2594         FW_STAT_TX_PORT_128B_255B_IX,
2595         FW_STAT_TX_PORT_256B_511B_IX,
2596         FW_STAT_TX_PORT_512B_1023B_IX,
2597         FW_STAT_TX_PORT_1024B_1518B_IX,
2598         FW_STAT_TX_PORT_1519B_MAX_IX,
2599         FW_STAT_TX_PORT_DROP_IX,
2600         FW_STAT_TX_PORT_PAUSE_IX,
2601         FW_STAT_TX_PORT_PPP0_IX,
2602         FW_STAT_TX_PORT_PPP1_IX,
2603         FW_STAT_TX_PORT_PPP2_IX,
2604         FW_STAT_TX_PORT_PPP3_IX,
2605         FW_STAT_TX_PORT_PPP4_IX,
2606         FW_STAT_TX_PORT_PPP5_IX,
2607         FW_STAT_TX_PORT_PPP6_IX,
2608         FW_STAT_TX_PORT_PPP7_IX,
2609         FW_NUM_PORT_TX_STATS
2610 };
2611
2612 enum fw_port_stat_rx_index {
2613         FW_STAT_RX_PORT_BYTES_IX = 0,
2614         FW_STAT_RX_PORT_FRAMES_IX,
2615         FW_STAT_RX_PORT_BCAST_IX,
2616         FW_STAT_RX_PORT_MCAST_IX,
2617         FW_STAT_RX_PORT_UCAST_IX,
2618         FW_STAT_RX_PORT_MTU_ERROR_IX,
2619         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2620         FW_STAT_RX_PORT_CRC_ERROR_IX,
2621         FW_STAT_RX_PORT_LEN_ERROR_IX,
2622         FW_STAT_RX_PORT_SYM_ERROR_IX,
2623         FW_STAT_RX_PORT_64B_IX,
2624         FW_STAT_RX_PORT_65B_127B_IX,
2625         FW_STAT_RX_PORT_128B_255B_IX,
2626         FW_STAT_RX_PORT_256B_511B_IX,
2627         FW_STAT_RX_PORT_512B_1023B_IX,
2628         FW_STAT_RX_PORT_1024B_1518B_IX,
2629         FW_STAT_RX_PORT_1519B_MAX_IX,
2630         FW_STAT_RX_PORT_PAUSE_IX,
2631         FW_STAT_RX_PORT_PPP0_IX,
2632         FW_STAT_RX_PORT_PPP1_IX,
2633         FW_STAT_RX_PORT_PPP2_IX,
2634         FW_STAT_RX_PORT_PPP3_IX,
2635         FW_STAT_RX_PORT_PPP4_IX,
2636         FW_STAT_RX_PORT_PPP5_IX,
2637         FW_STAT_RX_PORT_PPP6_IX,
2638         FW_STAT_RX_PORT_PPP7_IX,
2639         FW_STAT_RX_PORT_LESS_64B_IX,
2640         FW_STAT_RX_PORT_MAC_ERROR_IX,
2641         FW_NUM_PORT_RX_STATS
2642 };
2643
2644 /* port stats */
2645 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
2646
2647 struct fw_port_stats_cmd {
2648         __be32 op_to_portid;
2649         __be32 retval_len16;
2650         union fw_port_stats {
2651                 struct fw_port_stats_ctl {
2652                         u8 nstats_bg_bm;
2653                         u8 tx_ix;
2654                         __be16 r6;
2655                         __be32 r7;
2656                         __be64 stat0;
2657                         __be64 stat1;
2658                         __be64 stat2;
2659                         __be64 stat3;
2660                         __be64 stat4;
2661                         __be64 stat5;
2662                 } ctl;
2663                 struct fw_port_stats_all {
2664                         __be64 tx_bytes;
2665                         __be64 tx_frames;
2666                         __be64 tx_bcast;
2667                         __be64 tx_mcast;
2668                         __be64 tx_ucast;
2669                         __be64 tx_error;
2670                         __be64 tx_64b;
2671                         __be64 tx_65b_127b;
2672                         __be64 tx_128b_255b;
2673                         __be64 tx_256b_511b;
2674                         __be64 tx_512b_1023b;
2675                         __be64 tx_1024b_1518b;
2676                         __be64 tx_1519b_max;
2677                         __be64 tx_drop;
2678                         __be64 tx_pause;
2679                         __be64 tx_ppp0;
2680                         __be64 tx_ppp1;
2681                         __be64 tx_ppp2;
2682                         __be64 tx_ppp3;
2683                         __be64 tx_ppp4;
2684                         __be64 tx_ppp5;
2685                         __be64 tx_ppp6;
2686                         __be64 tx_ppp7;
2687                         __be64 rx_bytes;
2688                         __be64 rx_frames;
2689                         __be64 rx_bcast;
2690                         __be64 rx_mcast;
2691                         __be64 rx_ucast;
2692                         __be64 rx_mtu_error;
2693                         __be64 rx_mtu_crc_error;
2694                         __be64 rx_crc_error;
2695                         __be64 rx_len_error;
2696                         __be64 rx_sym_error;
2697                         __be64 rx_64b;
2698                         __be64 rx_65b_127b;
2699                         __be64 rx_128b_255b;
2700                         __be64 rx_256b_511b;
2701                         __be64 rx_512b_1023b;
2702                         __be64 rx_1024b_1518b;
2703                         __be64 rx_1519b_max;
2704                         __be64 rx_pause;
2705                         __be64 rx_ppp0;
2706                         __be64 rx_ppp1;
2707                         __be64 rx_ppp2;
2708                         __be64 rx_ppp3;
2709                         __be64 rx_ppp4;
2710                         __be64 rx_ppp5;
2711                         __be64 rx_ppp6;
2712                         __be64 rx_ppp7;
2713                         __be64 rx_less_64b;
2714                         __be64 rx_bg_drop;
2715                         __be64 rx_bg_trunc;
2716                 } all;
2717         } u;
2718 };
2719
2720 /* port loopback stats */
2721 #define FW_NUM_LB_STATS 16
2722 enum fw_port_lb_stats_index {
2723         FW_STAT_LB_PORT_BYTES_IX,
2724         FW_STAT_LB_PORT_FRAMES_IX,
2725         FW_STAT_LB_PORT_BCAST_IX,
2726         FW_STAT_LB_PORT_MCAST_IX,
2727         FW_STAT_LB_PORT_UCAST_IX,
2728         FW_STAT_LB_PORT_ERROR_IX,
2729         FW_STAT_LB_PORT_64B_IX,
2730         FW_STAT_LB_PORT_65B_127B_IX,
2731         FW_STAT_LB_PORT_128B_255B_IX,
2732         FW_STAT_LB_PORT_256B_511B_IX,
2733         FW_STAT_LB_PORT_512B_1023B_IX,
2734         FW_STAT_LB_PORT_1024B_1518B_IX,
2735         FW_STAT_LB_PORT_1519B_MAX_IX,
2736         FW_STAT_LB_PORT_DROP_FRAMES_IX
2737 };
2738
2739 struct fw_port_lb_stats_cmd {
2740         __be32 op_to_lbport;
2741         __be32 retval_len16;
2742         union fw_port_lb_stats {
2743                 struct fw_port_lb_stats_ctl {
2744                         u8 nstats_bg_bm;
2745                         u8 ix_pkd;
2746                         __be16 r6;
2747                         __be32 r7;
2748                         __be64 stat0;
2749                         __be64 stat1;
2750                         __be64 stat2;
2751                         __be64 stat3;
2752                         __be64 stat4;
2753                         __be64 stat5;
2754                 } ctl;
2755                 struct fw_port_lb_stats_all {
2756                         __be64 tx_bytes;
2757                         __be64 tx_frames;
2758                         __be64 tx_bcast;
2759                         __be64 tx_mcast;
2760                         __be64 tx_ucast;
2761                         __be64 tx_error;
2762                         __be64 tx_64b;
2763                         __be64 tx_65b_127b;
2764                         __be64 tx_128b_255b;
2765                         __be64 tx_256b_511b;
2766                         __be64 tx_512b_1023b;
2767                         __be64 tx_1024b_1518b;
2768                         __be64 tx_1519b_max;
2769                         __be64 rx_lb_drop;
2770                         __be64 rx_lb_trunc;
2771                 } all;
2772         } u;
2773 };
2774
2775 struct fw_rss_ind_tbl_cmd {
2776         __be32 op_to_viid;
2777         __be32 retval_len16;
2778         __be16 niqid;
2779         __be16 startidx;
2780         __be32 r3;
2781         __be32 iq0_to_iq2;
2782         __be32 iq3_to_iq5;
2783         __be32 iq6_to_iq8;
2784         __be32 iq9_to_iq11;
2785         __be32 iq12_to_iq14;
2786         __be32 iq15_to_iq17;
2787         __be32 iq18_to_iq20;
2788         __be32 iq21_to_iq23;
2789         __be32 iq24_to_iq26;
2790         __be32 iq27_to_iq29;
2791         __be32 iq30_iq31;
2792         __be32 r15_lo;
2793 };
2794
2795 #define FW_RSS_IND_TBL_CMD_VIID_S       0
2796 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2797
2798 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
2799 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2800
2801 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
2802 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2803
2804 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
2805 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2806
2807 struct fw_rss_glb_config_cmd {
2808         __be32 op_to_write;
2809         __be32 retval_len16;
2810         union fw_rss_glb_config {
2811                 struct fw_rss_glb_config_manual {
2812                         __be32 mode_pkd;
2813                         __be32 r3;
2814                         __be64 r4;
2815                         __be64 r5;
2816                 } manual;
2817                 struct fw_rss_glb_config_basicvirtual {
2818                         __be32 mode_pkd;
2819                         __be32 synmapen_to_hashtoeplitz;
2820                         __be64 r8;
2821                         __be64 r9;
2822                 } basicvirtual;
2823         } u;
2824 };
2825
2826 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
2827 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
2828 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2829 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2830         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2831
2832 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
2833 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2834
2835 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
2836 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
2837         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2838 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
2839         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2840
2841 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
2842 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
2843         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2844 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
2845         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2846
2847 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
2848 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
2849         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2850 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
2851         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2852
2853 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
2854 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
2855         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2856 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
2857         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2858
2859 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
2860 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
2861         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2862 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
2863         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2864
2865 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
2866 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
2867         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2868 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
2869         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2870
2871 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
2872 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
2873         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2874 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
2875         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2876
2877 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
2878 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
2879         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2880 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
2881         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2882
2883 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
2884 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2885         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2886 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
2887         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2888
2889 struct fw_rss_vi_config_cmd {
2890         __be32 op_to_viid;
2891 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2892         __be32 retval_len16;
2893         union fw_rss_vi_config {
2894                 struct fw_rss_vi_config_manual {
2895                         __be64 r3;
2896                         __be64 r4;
2897                         __be64 r5;
2898                 } manual;
2899                 struct fw_rss_vi_config_basicvirtual {
2900                         __be32 r6;
2901                         __be32 defaultq_to_udpen;
2902                         __be64 r9;
2903                         __be64 r10;
2904                 } basicvirtual;
2905         } u;
2906 };
2907
2908 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
2909 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2910
2911 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
2912 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
2913 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
2914         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2915 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
2916         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2917          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2918
2919 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
2920 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
2921         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2922 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
2923         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2924
2925 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
2926 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
2927         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2928 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
2929         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2930
2931 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
2932 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
2933         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2934 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
2935         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2936
2937 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
2938 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
2939         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2940 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
2941         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2942
2943 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
2944 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2945 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2946
2947 struct fw_clip_cmd {
2948         __be32 op_to_write;
2949         __be32 alloc_to_len16;
2950         __be64 ip_hi;
2951         __be64 ip_lo;
2952         __be32 r4[2];
2953 };
2954
2955 #define FW_CLIP_CMD_ALLOC_S     31
2956 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
2957 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
2958
2959 #define FW_CLIP_CMD_FREE_S      30
2960 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
2961 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
2962
2963 enum fw_error_type {
2964         FW_ERROR_TYPE_EXCEPTION         = 0x0,
2965         FW_ERROR_TYPE_HWMODULE          = 0x1,
2966         FW_ERROR_TYPE_WR                = 0x2,
2967         FW_ERROR_TYPE_ACL               = 0x3,
2968 };
2969
2970 struct fw_error_cmd {
2971         __be32 op_to_type;
2972         __be32 len16_pkd;
2973         union fw_error {
2974                 struct fw_error_exception {
2975                         __be32 info[6];
2976                 } exception;
2977                 struct fw_error_hwmodule {
2978                         __be32 regaddr;
2979                         __be32 regval;
2980                 } hwmodule;
2981                 struct fw_error_wr {
2982                         __be16 cidx;
2983                         __be16 pfn_vfn;
2984                         __be32 eqid;
2985                         u8 wrhdr[16];
2986                 } wr;
2987                 struct fw_error_acl {
2988                         __be16 cidx;
2989                         __be16 pfn_vfn;
2990                         __be32 eqid;
2991                         __be16 mv_pkd;
2992                         u8 val[6];
2993                         __be64 r4;
2994                 } acl;
2995         } u;
2996 };
2997
2998 struct fw_debug_cmd {
2999         __be32 op_type;
3000         __be32 len16_pkd;
3001         union fw_debug {
3002                 struct fw_debug_assert {
3003                         __be32 fcid;
3004                         __be32 line;
3005                         __be32 x;
3006                         __be32 y;
3007                         u8 filename_0_7[8];
3008                         u8 filename_8_15[8];
3009                         __be64 r3;
3010                 } assert;
3011                 struct fw_debug_prt {
3012                         __be16 dprtstridx;
3013                         __be16 r3[3];
3014                         __be32 dprtstrparam0;
3015                         __be32 dprtstrparam1;
3016                         __be32 dprtstrparam2;
3017                         __be32 dprtstrparam3;
3018                 } prt;
3019         } u;
3020 };
3021
3022 #define FW_DEBUG_CMD_TYPE_S     0
3023 #define FW_DEBUG_CMD_TYPE_M     0xff
3024 #define FW_DEBUG_CMD_TYPE_G(x)  \
3025         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3026
3027 #define PCIE_FW_ERR_S           31
3028 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
3029 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
3030
3031 #define PCIE_FW_INIT_S          30
3032 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
3033 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
3034
3035 #define PCIE_FW_HALT_S          29
3036 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3037 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3038
3039 #define PCIE_FW_EVAL_S          24
3040 #define PCIE_FW_EVAL_M          0x7
3041 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3042
3043 #define PCIE_FW_MASTER_VLD_S    15
3044 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3045 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
3046
3047 #define PCIE_FW_MASTER_S        12
3048 #define PCIE_FW_MASTER_M        0x7
3049 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
3050 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3051
3052 struct fw_hdr {
3053         u8 ver;
3054         u8 chip;                        /* terminator chip type */
3055         __be16  len512;                 /* bin length in units of 512-bytes */
3056         __be32  fw_ver;                 /* firmware version */
3057         __be32  tp_microcode_ver;
3058         u8 intfver_nic;
3059         u8 intfver_vnic;
3060         u8 intfver_ofld;
3061         u8 intfver_ri;
3062         u8 intfver_iscsipdu;
3063         u8 intfver_iscsi;
3064         u8 intfver_fcoepdu;
3065         u8 intfver_fcoe;
3066         __u32   reserved2;
3067         __u32   reserved3;
3068         __u32   reserved4;
3069         __be32  flags;
3070         __be32  reserved6[23];
3071 };
3072
3073 enum fw_hdr_chip {
3074         FW_HDR_CHIP_T4,
3075         FW_HDR_CHIP_T5,
3076         FW_HDR_CHIP_T6
3077 };
3078
3079 #define FW_HDR_FW_VER_MAJOR_S   24
3080 #define FW_HDR_FW_VER_MAJOR_M   0xff
3081 #define FW_HDR_FW_VER_MAJOR_V(x) \
3082         ((x) << FW_HDR_FW_VER_MAJOR_S)
3083 #define FW_HDR_FW_VER_MAJOR_G(x) \
3084         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3085
3086 #define FW_HDR_FW_VER_MINOR_S   16
3087 #define FW_HDR_FW_VER_MINOR_M   0xff
3088 #define FW_HDR_FW_VER_MINOR_V(x) \
3089         ((x) << FW_HDR_FW_VER_MINOR_S)
3090 #define FW_HDR_FW_VER_MINOR_G(x) \
3091         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3092
3093 #define FW_HDR_FW_VER_MICRO_S   8
3094 #define FW_HDR_FW_VER_MICRO_M   0xff
3095 #define FW_HDR_FW_VER_MICRO_V(x) \
3096         ((x) << FW_HDR_FW_VER_MICRO_S)
3097 #define FW_HDR_FW_VER_MICRO_G(x) \
3098         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3099
3100 #define FW_HDR_FW_VER_BUILD_S   0
3101 #define FW_HDR_FW_VER_BUILD_M   0xff
3102 #define FW_HDR_FW_VER_BUILD_V(x) \
3103         ((x) << FW_HDR_FW_VER_BUILD_S)
3104 #define FW_HDR_FW_VER_BUILD_G(x) \
3105         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3106
3107 enum fw_hdr_intfver {
3108         FW_HDR_INTFVER_NIC      = 0x00,
3109         FW_HDR_INTFVER_VNIC     = 0x00,
3110         FW_HDR_INTFVER_OFLD     = 0x00,
3111         FW_HDR_INTFVER_RI       = 0x00,
3112         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3113         FW_HDR_INTFVER_ISCSI    = 0x00,
3114         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3115         FW_HDR_INTFVER_FCOE     = 0x00,
3116 };
3117
3118 enum fw_hdr_flags {
3119         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3120 };
3121
3122 /* length of the formatting string  */
3123 #define FW_DEVLOG_FMT_LEN       192
3124
3125 /* maximum number of the formatting string parameters */
3126 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3127
3128 /* priority levels */
3129 enum fw_devlog_level {
3130         FW_DEVLOG_LEVEL_EMERG   = 0x0,
3131         FW_DEVLOG_LEVEL_CRIT    = 0x1,
3132         FW_DEVLOG_LEVEL_ERR     = 0x2,
3133         FW_DEVLOG_LEVEL_NOTICE  = 0x3,
3134         FW_DEVLOG_LEVEL_INFO    = 0x4,
3135         FW_DEVLOG_LEVEL_DEBUG   = 0x5,
3136         FW_DEVLOG_LEVEL_MAX     = 0x5,
3137 };
3138
3139 /* facilities that may send a log message */
3140 enum fw_devlog_facility {
3141         FW_DEVLOG_FACILITY_CORE         = 0x00,
3142         FW_DEVLOG_FACILITY_CF           = 0x01,
3143         FW_DEVLOG_FACILITY_SCHED        = 0x02,
3144         FW_DEVLOG_FACILITY_TIMER        = 0x04,
3145         FW_DEVLOG_FACILITY_RES          = 0x06,
3146         FW_DEVLOG_FACILITY_HW           = 0x08,
3147         FW_DEVLOG_FACILITY_FLR          = 0x10,
3148         FW_DEVLOG_FACILITY_DMAQ         = 0x12,
3149         FW_DEVLOG_FACILITY_PHY          = 0x14,
3150         FW_DEVLOG_FACILITY_MAC          = 0x16,
3151         FW_DEVLOG_FACILITY_PORT         = 0x18,
3152         FW_DEVLOG_FACILITY_VI           = 0x1A,
3153         FW_DEVLOG_FACILITY_FILTER       = 0x1C,
3154         FW_DEVLOG_FACILITY_ACL          = 0x1E,
3155         FW_DEVLOG_FACILITY_TM           = 0x20,
3156         FW_DEVLOG_FACILITY_QFC          = 0x22,
3157         FW_DEVLOG_FACILITY_DCB          = 0x24,
3158         FW_DEVLOG_FACILITY_ETH          = 0x26,
3159         FW_DEVLOG_FACILITY_OFLD         = 0x28,
3160         FW_DEVLOG_FACILITY_RI           = 0x2A,
3161         FW_DEVLOG_FACILITY_ISCSI        = 0x2C,
3162         FW_DEVLOG_FACILITY_FCOE         = 0x2E,
3163         FW_DEVLOG_FACILITY_FOISCSI      = 0x30,
3164         FW_DEVLOG_FACILITY_FOFCOE       = 0x32,
3165         FW_DEVLOG_FACILITY_CHNET        = 0x34,
3166         FW_DEVLOG_FACILITY_MAX          = 0x34,
3167 };
3168
3169 /* log message format */
3170 struct fw_devlog_e {
3171         __be64  timestamp;
3172         __be32  seqno;
3173         __be16  reserved1;
3174         __u8    level;
3175         __u8    facility;
3176         __u8    fmt[FW_DEVLOG_FMT_LEN];
3177         __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];
3178         __be32  reserved3[4];
3179 };
3180
3181 struct fw_devlog_cmd {
3182         __be32 op_to_write;
3183         __be32 retval_len16;
3184         __u8   level;
3185         __u8   r2[7];
3186         __be32 memtype_devlog_memaddr16_devlog;
3187         __be32 memsize_devlog;
3188         __be32 r3[2];
3189 };
3190
3191 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S          28
3192 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M          0xf
3193 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)       \
3194         (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3195          FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3196
3197 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S        0
3198 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M        0xfffffff
3199 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)     \
3200         (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3201          FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3202
3203 /* P C I E   F W   P F 7   R E G I S T E R */
3204
3205 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3206  * access the "devlog" which needing to contact firmware.  The encoding is
3207  * mostly the same as that returned by the DEVLOG command except for the size
3208  * which is encoded as the number of entries in multiples-1 of 128 here rather
3209  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3210  * and 15 means 2048.  This of course in turn constrains the allowed values
3211  * for the devlog size ...
3212  */
3213 #define PCIE_FW_PF_DEVLOG               7
3214
3215 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3216 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3217 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3218         ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3219 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3220         (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3221          PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3222
3223 #define PCIE_FW_PF_DEVLOG_ADDR16_S      4
3224 #define PCIE_FW_PF_DEVLOG_ADDR16_M      0xffffff
3225 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)   ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3226 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3227         (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3228
3229 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S     0
3230 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M     0xf
3231 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)  ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3232 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3233         (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3234
3235 #endif /* _T4FW_INTERFACE_H_ */