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enet: fec: fix fail resume from suspend state
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
41 #include <linux/io.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
47 #include <linux/of.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
51 #include <linux/pinctrl/consumer.h>
52 #include <linux/regulator/consumer.h>
53
54 #include <asm/cacheflush.h>
55
56 #ifndef CONFIG_ARM
57 #include <asm/coldfire.h>
58 #include <asm/mcfsim.h>
59 #endif
60
61 #include "fec.h"
62
63 #if defined(CONFIG_ARM)
64 #define FEC_ALIGNMENT 0xf
65 #else
66 #define FEC_ALIGNMENT 0x3
67 #endif
68
69 #define DRIVER_NAME "fec"
70 #define FEC_NAPI_WEIGHT 64
71
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
79
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90
91 static struct platform_device_id fec_devtype[] = {
92 {
93 /* keep it for coldfire */
94 .name = DRIVER_NAME,
95 .driver_data = 0,
96 }, {
97 .name = "imx25-fec",
98 .driver_data = FEC_QUIRK_USE_GASKET,
99 }, {
100 .name = "imx27-fec",
101 .driver_data = 0,
102 }, {
103 .name = "imx28-fec",
104 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
105 }, {
106 .name = "imx6q-fec",
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
108 FEC_QUIRK_HAS_BUFDESC_EX,
109 }, {
110 /* sentinel */
111 }
112 };
113 MODULE_DEVICE_TABLE(platform, fec_devtype);
114
115 enum imx_fec_type {
116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
117 IMX27_FEC, /* runs on i.mx27/35/51 */
118 IMX28_FEC,
119 IMX6Q_FEC,
120 };
121
122 static const struct of_device_id fec_dt_ids[] = {
123 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
124 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
125 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
126 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
127 { /* sentinel */ }
128 };
129 MODULE_DEVICE_TABLE(of, fec_dt_ids);
130
131 static unsigned char macaddr[ETH_ALEN];
132 module_param_array(macaddr, byte, NULL, 0);
133 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
134
135 #if defined(CONFIG_M5272)
136 /*
137 * Some hardware gets it MAC address out of local flash memory.
138 * if this is non-zero then assume it is the address to get MAC from.
139 */
140 #if defined(CONFIG_NETtel)
141 #define FEC_FLASHMAC 0xf0006006
142 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
143 #define FEC_FLASHMAC 0xf0006000
144 #elif defined(CONFIG_CANCam)
145 #define FEC_FLASHMAC 0xf0020000
146 #elif defined (CONFIG_M5272C3)
147 #define FEC_FLASHMAC (0xffe04000 + 4)
148 #elif defined(CONFIG_MOD5272)
149 #define FEC_FLASHMAC 0xffc0406b
150 #else
151 #define FEC_FLASHMAC 0
152 #endif
153 #endif /* CONFIG_M5272 */
154
155 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
156 #error "FEC: descriptor ring size constants too large"
157 #endif
158
159 /* Interrupt events/masks. */
160 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
161 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
162 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
163 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
164 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
165 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
166 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
167 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
168 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
169 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
170
171 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
172 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
173
174 /* The FEC stores dest/src/type, data, and checksum for receive packets.
175 */
176 #define PKT_MAXBUF_SIZE 1518
177 #define PKT_MINBUF_SIZE 64
178 #define PKT_MAXBLR_SIZE 1520
179
180 /*
181 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
182 * size bits. Other FEC hardware does not, so we need to take that into
183 * account when setting it.
184 */
185 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
186 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
187 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
188 #else
189 #define OPT_FRAME_SIZE 0
190 #endif
191
192 /* FEC MII MMFR bits definition */
193 #define FEC_MMFR_ST (1 << 30)
194 #define FEC_MMFR_OP_READ (2 << 28)
195 #define FEC_MMFR_OP_WRITE (1 << 28)
196 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
197 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
198 #define FEC_MMFR_TA (2 << 16)
199 #define FEC_MMFR_DATA(v) (v & 0xffff)
200
201 #define FEC_MII_TIMEOUT 30000 /* us */
202
203 /* Transmitter timeout */
204 #define TX_TIMEOUT (2 * HZ)
205
206 #define FEC_PAUSE_FLAG_AUTONEG 0x1
207 #define FEC_PAUSE_FLAG_ENABLE 0x2
208
209 static int mii_cnt;
210
211 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
212 {
213 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
214 if (is_ex)
215 return (struct bufdesc *)(ex + 1);
216 else
217 return bdp + 1;
218 }
219
220 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
221 {
222 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
223 if (is_ex)
224 return (struct bufdesc *)(ex - 1);
225 else
226 return bdp - 1;
227 }
228
229 static void *swap_buffer(void *bufaddr, int len)
230 {
231 int i;
232 unsigned int *buf = bufaddr;
233
234 for (i = 0; i < (len + 3) / 4; i++, buf++)
235 *buf = cpu_to_be32(*buf);
236
237 return bufaddr;
238 }
239
240 static netdev_tx_t
241 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
242 {
243 struct fec_enet_private *fep = netdev_priv(ndev);
244 const struct platform_device_id *id_entry =
245 platform_get_device_id(fep->pdev);
246 struct bufdesc *bdp;
247 void *bufaddr;
248 unsigned short status;
249 unsigned int index;
250
251 if (!fep->link) {
252 /* Link is down or autonegotiation is in progress. */
253 return NETDEV_TX_BUSY;
254 }
255
256 /* Fill in a Tx ring entry */
257 bdp = fep->cur_tx;
258
259 status = bdp->cbd_sc;
260
261 if (status & BD_ENET_TX_READY) {
262 /* Ooops. All transmit buffers are full. Bail out.
263 * This should not happen, since ndev->tbusy should be set.
264 */
265 printk("%s: tx queue full!.\n", ndev->name);
266 return NETDEV_TX_BUSY;
267 }
268
269 /* Clear all of the status flags */
270 status &= ~BD_ENET_TX_STATS;
271
272 /* Set buffer length and buffer pointer */
273 bufaddr = skb->data;
274 bdp->cbd_datlen = skb->len;
275
276 /*
277 * On some FEC implementations data must be aligned on
278 * 4-byte boundaries. Use bounce buffers to copy data
279 * and get it aligned. Ugh.
280 */
281 if (fep->bufdesc_ex)
282 index = (struct bufdesc_ex *)bdp -
283 (struct bufdesc_ex *)fep->tx_bd_base;
284 else
285 index = bdp - fep->tx_bd_base;
286
287 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
288 memcpy(fep->tx_bounce[index], skb->data, skb->len);
289 bufaddr = fep->tx_bounce[index];
290 }
291
292 /*
293 * Some design made an incorrect assumption on endian mode of
294 * the system that it's running on. As the result, driver has to
295 * swap every frame going to and coming from the controller.
296 */
297 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
298 swap_buffer(bufaddr, skb->len);
299
300 /* Save skb pointer */
301 fep->tx_skbuff[index] = skb;
302
303 /* Push the data cache so the CPM does not get stale memory
304 * data.
305 */
306 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
307 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
308
309 /* Send it on its way. Tell FEC it's ready, interrupt when done,
310 * it's the last BD of the frame, and to put the CRC on the end.
311 */
312 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
313 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
314 bdp->cbd_sc = status;
315
316 if (fep->bufdesc_ex) {
317
318 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
319 ebdp->cbd_bdu = 0;
320 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
321 fep->hwts_tx_en)) {
322 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
323 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
324 } else {
325
326 ebdp->cbd_esc = BD_ENET_TX_INT;
327 }
328 }
329 /* If this was the last BD in the ring, start at the beginning again. */
330 if (status & BD_ENET_TX_WRAP)
331 bdp = fep->tx_bd_base;
332 else
333 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
334
335 fep->cur_tx = bdp;
336
337 if (fep->cur_tx == fep->dirty_tx)
338 netif_stop_queue(ndev);
339
340 /* Trigger transmission start */
341 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
342
343 skb_tx_timestamp(skb);
344
345 return NETDEV_TX_OK;
346 }
347
348 /* Init RX & TX buffer descriptors
349 */
350 static void fec_enet_bd_init(struct net_device *dev)
351 {
352 struct fec_enet_private *fep = netdev_priv(dev);
353 struct bufdesc *bdp;
354 unsigned int i;
355
356 /* Initialize the receive buffer descriptors. */
357 bdp = fep->rx_bd_base;
358 for (i = 0; i < RX_RING_SIZE; i++) {
359
360 /* Initialize the BD for every fragment in the page. */
361 if (bdp->cbd_bufaddr)
362 bdp->cbd_sc = BD_ENET_RX_EMPTY;
363 else
364 bdp->cbd_sc = 0;
365 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
366 }
367
368 /* Set the last buffer to wrap */
369 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
370 bdp->cbd_sc |= BD_SC_WRAP;
371
372 fep->cur_rx = fep->rx_bd_base;
373
374 /* ...and the same for transmit */
375 bdp = fep->tx_bd_base;
376 fep->cur_tx = bdp;
377 for (i = 0; i < TX_RING_SIZE; i++) {
378
379 /* Initialize the BD for every fragment in the page. */
380 bdp->cbd_sc = 0;
381 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
382 dev_kfree_skb_any(fep->tx_skbuff[i]);
383 fep->tx_skbuff[i] = NULL;
384 }
385 bdp->cbd_bufaddr = 0;
386 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
387 }
388
389 /* Set the last buffer to wrap */
390 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
391 bdp->cbd_sc |= BD_SC_WRAP;
392 fep->dirty_tx = bdp;
393 }
394
395 /* This function is called to start or restart the FEC during a link
396 * change. This only happens when switching between half and full
397 * duplex.
398 */
399 static void
400 fec_restart(struct net_device *ndev, int duplex)
401 {
402 struct fec_enet_private *fep = netdev_priv(ndev);
403 const struct platform_device_id *id_entry =
404 platform_get_device_id(fep->pdev);
405 int i;
406 u32 temp_mac[2];
407 u32 rcntl = OPT_FRAME_SIZE | 0x04;
408 u32 ecntl = 0x2; /* ETHEREN */
409
410 /* Whack a reset. We should wait for this. */
411 writel(1, fep->hwp + FEC_ECNTRL);
412 udelay(10);
413
414 /*
415 * enet-mac reset will reset mac address registers too,
416 * so need to reconfigure it.
417 */
418 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
419 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
420 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
421 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
422 }
423
424 /* Clear any outstanding interrupt. */
425 writel(0xffc00000, fep->hwp + FEC_IEVENT);
426
427 /* Reset all multicast. */
428 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
429 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
430 #ifndef CONFIG_M5272
431 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
432 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
433 #endif
434
435 /* Set maximum receive buffer size. */
436 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
437
438 fec_enet_bd_init(ndev);
439
440 /* Set receive and transmit descriptor base. */
441 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
442 if (fep->bufdesc_ex)
443 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
444 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
445 else
446 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
447 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
448
449
450 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
451 if (fep->tx_skbuff[i]) {
452 dev_kfree_skb_any(fep->tx_skbuff[i]);
453 fep->tx_skbuff[i] = NULL;
454 }
455 }
456
457 /* Enable MII mode */
458 if (duplex) {
459 /* FD enable */
460 writel(0x04, fep->hwp + FEC_X_CNTRL);
461 } else {
462 /* No Rcv on Xmit */
463 rcntl |= 0x02;
464 writel(0x0, fep->hwp + FEC_X_CNTRL);
465 }
466
467 fep->full_duplex = duplex;
468
469 /* Set MII speed */
470 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
471
472 /*
473 * The phy interface and speed need to get configured
474 * differently on enet-mac.
475 */
476 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
477 /* Enable flow control and length check */
478 rcntl |= 0x40000000 | 0x00000020;
479
480 /* RGMII, RMII or MII */
481 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
482 rcntl |= (1 << 6);
483 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
484 rcntl |= (1 << 8);
485 else
486 rcntl &= ~(1 << 8);
487
488 /* 1G, 100M or 10M */
489 if (fep->phy_dev) {
490 if (fep->phy_dev->speed == SPEED_1000)
491 ecntl |= (1 << 5);
492 else if (fep->phy_dev->speed == SPEED_100)
493 rcntl &= ~(1 << 9);
494 else
495 rcntl |= (1 << 9);
496 }
497 } else {
498 #ifdef FEC_MIIGSK_ENR
499 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
500 u32 cfgr;
501 /* disable the gasket and wait */
502 writel(0, fep->hwp + FEC_MIIGSK_ENR);
503 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
504 udelay(1);
505
506 /*
507 * configure the gasket:
508 * RMII, 50 MHz, no loopback, no echo
509 * MII, 25 MHz, no loopback, no echo
510 */
511 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
512 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
513 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
514 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
515 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
516
517 /* re-enable the gasket */
518 writel(2, fep->hwp + FEC_MIIGSK_ENR);
519 }
520 #endif
521 }
522
523 /* enable pause frame*/
524 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
525 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
526 fep->phy_dev && fep->phy_dev->pause)) {
527 rcntl |= FEC_ENET_FCE;
528
529 /* set FIFO thresh hold parameter to reduce overrun */
530 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
531 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
532 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
533 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
534
535 /* OPD */
536 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
537 } else {
538 rcntl &= ~FEC_ENET_FCE;
539 }
540
541 writel(rcntl, fep->hwp + FEC_R_CNTRL);
542
543 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
544 /* enable ENET endian swap */
545 ecntl |= (1 << 8);
546 /* enable ENET store and forward mode */
547 writel(1 << 8, fep->hwp + FEC_X_WMRK);
548 }
549
550 if (fep->bufdesc_ex)
551 ecntl |= (1 << 4);
552
553 /* And last, enable the transmit and receive processing */
554 writel(ecntl, fep->hwp + FEC_ECNTRL);
555 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
556
557 if (fep->bufdesc_ex)
558 fec_ptp_start_cyclecounter(ndev);
559
560 /* Enable interrupts we wish to service */
561 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
562 }
563
564 static void
565 fec_stop(struct net_device *ndev)
566 {
567 struct fec_enet_private *fep = netdev_priv(ndev);
568 const struct platform_device_id *id_entry =
569 platform_get_device_id(fep->pdev);
570 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
571
572 /* We cannot expect a graceful transmit stop without link !!! */
573 if (fep->link) {
574 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
575 udelay(10);
576 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
577 printk("fec_stop : Graceful transmit stop did not complete !\n");
578 }
579
580 /* Whack a reset. We should wait for this. */
581 writel(1, fep->hwp + FEC_ECNTRL);
582 udelay(10);
583 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
584 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
585
586 /* We have to keep ENET enabled to have MII interrupt stay working */
587 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
588 writel(2, fep->hwp + FEC_ECNTRL);
589 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
590 }
591 }
592
593
594 static void
595 fec_timeout(struct net_device *ndev)
596 {
597 struct fec_enet_private *fep = netdev_priv(ndev);
598
599 ndev->stats.tx_errors++;
600
601 fec_restart(ndev, fep->full_duplex);
602 netif_wake_queue(ndev);
603 }
604
605 static void
606 fec_enet_tx(struct net_device *ndev)
607 {
608 struct fec_enet_private *fep;
609 struct bufdesc *bdp;
610 unsigned short status;
611 struct sk_buff *skb;
612 int index = 0;
613
614 fep = netdev_priv(ndev);
615 bdp = fep->dirty_tx;
616
617 /* get next bdp of dirty_tx */
618 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
619 bdp = fep->tx_bd_base;
620 else
621 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
622
623 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
624
625 /* current queue is empty */
626 if (bdp == fep->cur_tx)
627 break;
628
629 if (fep->bufdesc_ex)
630 index = (struct bufdesc_ex *)bdp -
631 (struct bufdesc_ex *)fep->tx_bd_base;
632 else
633 index = bdp - fep->tx_bd_base;
634
635 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
636 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
637 bdp->cbd_bufaddr = 0;
638
639 skb = fep->tx_skbuff[index];
640
641 /* Check for errors. */
642 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
643 BD_ENET_TX_RL | BD_ENET_TX_UN |
644 BD_ENET_TX_CSL)) {
645 ndev->stats.tx_errors++;
646 if (status & BD_ENET_TX_HB) /* No heartbeat */
647 ndev->stats.tx_heartbeat_errors++;
648 if (status & BD_ENET_TX_LC) /* Late collision */
649 ndev->stats.tx_window_errors++;
650 if (status & BD_ENET_TX_RL) /* Retrans limit */
651 ndev->stats.tx_aborted_errors++;
652 if (status & BD_ENET_TX_UN) /* Underrun */
653 ndev->stats.tx_fifo_errors++;
654 if (status & BD_ENET_TX_CSL) /* Carrier lost */
655 ndev->stats.tx_carrier_errors++;
656 } else {
657 ndev->stats.tx_packets++;
658 }
659
660 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
661 fep->bufdesc_ex) {
662 struct skb_shared_hwtstamps shhwtstamps;
663 unsigned long flags;
664 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
665
666 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
667 spin_lock_irqsave(&fep->tmreg_lock, flags);
668 shhwtstamps.hwtstamp = ns_to_ktime(
669 timecounter_cyc2time(&fep->tc, ebdp->ts));
670 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
671 skb_tstamp_tx(skb, &shhwtstamps);
672 }
673
674 if (status & BD_ENET_TX_READY)
675 printk("HEY! Enet xmit interrupt and TX_READY.\n");
676
677 /* Deferred means some collisions occurred during transmit,
678 * but we eventually sent the packet OK.
679 */
680 if (status & BD_ENET_TX_DEF)
681 ndev->stats.collisions++;
682
683 /* Free the sk buffer associated with this last transmit */
684 dev_kfree_skb_any(skb);
685 fep->tx_skbuff[index] = NULL;
686
687 fep->dirty_tx = bdp;
688
689 /* Update pointer to next buffer descriptor to be transmitted */
690 if (status & BD_ENET_TX_WRAP)
691 bdp = fep->tx_bd_base;
692 else
693 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
694
695 /* Since we have freed up a buffer, the ring is no longer full
696 */
697 if (fep->dirty_tx != fep->cur_tx) {
698 if (netif_queue_stopped(ndev))
699 netif_wake_queue(ndev);
700 }
701 }
702 return;
703 }
704
705
706 /* During a receive, the cur_rx points to the current incoming buffer.
707 * When we update through the ring, if the next incoming buffer has
708 * not been given to the system, we just set the empty indicator,
709 * effectively tossing the packet.
710 */
711 static int
712 fec_enet_rx(struct net_device *ndev, int budget)
713 {
714 struct fec_enet_private *fep = netdev_priv(ndev);
715 const struct platform_device_id *id_entry =
716 platform_get_device_id(fep->pdev);
717 struct bufdesc *bdp;
718 unsigned short status;
719 struct sk_buff *skb;
720 ushort pkt_len;
721 __u8 *data;
722 int pkt_received = 0;
723
724 #ifdef CONFIG_M532x
725 flush_cache_all();
726 #endif
727
728 /* First, grab all of the stats for the incoming packet.
729 * These get messed up if we get called due to a busy condition.
730 */
731 bdp = fep->cur_rx;
732
733 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
734
735 if (pkt_received >= budget)
736 break;
737 pkt_received++;
738
739 /* Since we have allocated space to hold a complete frame,
740 * the last indicator should be set.
741 */
742 if ((status & BD_ENET_RX_LAST) == 0)
743 printk("FEC ENET: rcv is not +last\n");
744
745 if (!fep->opened)
746 goto rx_processing_done;
747
748 /* Check for errors. */
749 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
750 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
751 ndev->stats.rx_errors++;
752 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
753 /* Frame too long or too short. */
754 ndev->stats.rx_length_errors++;
755 }
756 if (status & BD_ENET_RX_NO) /* Frame alignment */
757 ndev->stats.rx_frame_errors++;
758 if (status & BD_ENET_RX_CR) /* CRC Error */
759 ndev->stats.rx_crc_errors++;
760 if (status & BD_ENET_RX_OV) /* FIFO overrun */
761 ndev->stats.rx_fifo_errors++;
762 }
763
764 /* Report late collisions as a frame error.
765 * On this error, the BD is closed, but we don't know what we
766 * have in the buffer. So, just drop this frame on the floor.
767 */
768 if (status & BD_ENET_RX_CL) {
769 ndev->stats.rx_errors++;
770 ndev->stats.rx_frame_errors++;
771 goto rx_processing_done;
772 }
773
774 /* Process the incoming frame. */
775 ndev->stats.rx_packets++;
776 pkt_len = bdp->cbd_datlen;
777 ndev->stats.rx_bytes += pkt_len;
778 data = (__u8*)__va(bdp->cbd_bufaddr);
779
780 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
781 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
782
783 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
784 swap_buffer(data, pkt_len);
785
786 /* This does 16 byte alignment, exactly what we need.
787 * The packet length includes FCS, but we don't want to
788 * include that when passing upstream as it messes up
789 * bridging applications.
790 */
791 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
792
793 if (unlikely(!skb)) {
794 printk("%s: Memory squeeze, dropping packet.\n",
795 ndev->name);
796 ndev->stats.rx_dropped++;
797 } else {
798 skb_reserve(skb, NET_IP_ALIGN);
799 skb_put(skb, pkt_len - 4); /* Make room */
800 skb_copy_to_linear_data(skb, data, pkt_len - 4);
801 skb->protocol = eth_type_trans(skb, ndev);
802
803 /* Get receive timestamp from the skb */
804 if (fep->hwts_rx_en && fep->bufdesc_ex) {
805 struct skb_shared_hwtstamps *shhwtstamps =
806 skb_hwtstamps(skb);
807 unsigned long flags;
808 struct bufdesc_ex *ebdp =
809 (struct bufdesc_ex *)bdp;
810
811 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
812
813 spin_lock_irqsave(&fep->tmreg_lock, flags);
814 shhwtstamps->hwtstamp = ns_to_ktime(
815 timecounter_cyc2time(&fep->tc, ebdp->ts));
816 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
817 }
818
819 if (!skb_defer_rx_timestamp(skb))
820 napi_gro_receive(&fep->napi, skb);
821 }
822
823 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
824 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
825 rx_processing_done:
826 /* Clear the status flags for this buffer */
827 status &= ~BD_ENET_RX_STATS;
828
829 /* Mark the buffer empty */
830 status |= BD_ENET_RX_EMPTY;
831 bdp->cbd_sc = status;
832
833 if (fep->bufdesc_ex) {
834 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
835
836 ebdp->cbd_esc = BD_ENET_RX_INT;
837 ebdp->cbd_prot = 0;
838 ebdp->cbd_bdu = 0;
839 }
840
841 /* Update BD pointer to next entry */
842 if (status & BD_ENET_RX_WRAP)
843 bdp = fep->rx_bd_base;
844 else
845 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
846 /* Doing this here will keep the FEC running while we process
847 * incoming frames. On a heavily loaded network, we should be
848 * able to keep up at the expense of system resources.
849 */
850 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
851 }
852 fep->cur_rx = bdp;
853
854 return pkt_received;
855 }
856
857 static irqreturn_t
858 fec_enet_interrupt(int irq, void *dev_id)
859 {
860 struct net_device *ndev = dev_id;
861 struct fec_enet_private *fep = netdev_priv(ndev);
862 uint int_events;
863 irqreturn_t ret = IRQ_NONE;
864
865 do {
866 int_events = readl(fep->hwp + FEC_IEVENT);
867 writel(int_events, fep->hwp + FEC_IEVENT);
868
869 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
870 ret = IRQ_HANDLED;
871
872 /* Disable the RX interrupt */
873 if (napi_schedule_prep(&fep->napi)) {
874 writel(FEC_RX_DISABLED_IMASK,
875 fep->hwp + FEC_IMASK);
876 __napi_schedule(&fep->napi);
877 }
878 }
879
880 if (int_events & FEC_ENET_MII) {
881 ret = IRQ_HANDLED;
882 complete(&fep->mdio_done);
883 }
884 } while (int_events);
885
886 return ret;
887 }
888
889 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
890 {
891 struct net_device *ndev = napi->dev;
892 int pkts = fec_enet_rx(ndev, budget);
893 struct fec_enet_private *fep = netdev_priv(ndev);
894
895 fec_enet_tx(ndev);
896
897 if (pkts < budget) {
898 napi_complete(napi);
899 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
900 }
901 return pkts;
902 }
903
904 /* ------------------------------------------------------------------------- */
905 static void fec_get_mac(struct net_device *ndev)
906 {
907 struct fec_enet_private *fep = netdev_priv(ndev);
908 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
909 unsigned char *iap, tmpaddr[ETH_ALEN];
910
911 /*
912 * try to get mac address in following order:
913 *
914 * 1) module parameter via kernel command line in form
915 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
916 */
917 iap = macaddr;
918
919 #ifdef CONFIG_OF
920 /*
921 * 2) from device tree data
922 */
923 if (!is_valid_ether_addr(iap)) {
924 struct device_node *np = fep->pdev->dev.of_node;
925 if (np) {
926 const char *mac = of_get_mac_address(np);
927 if (mac)
928 iap = (unsigned char *) mac;
929 }
930 }
931 #endif
932
933 /*
934 * 3) from flash or fuse (via platform data)
935 */
936 if (!is_valid_ether_addr(iap)) {
937 #ifdef CONFIG_M5272
938 if (FEC_FLASHMAC)
939 iap = (unsigned char *)FEC_FLASHMAC;
940 #else
941 if (pdata)
942 iap = (unsigned char *)&pdata->mac;
943 #endif
944 }
945
946 /*
947 * 4) FEC mac registers set by bootloader
948 */
949 if (!is_valid_ether_addr(iap)) {
950 *((unsigned long *) &tmpaddr[0]) =
951 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
952 *((unsigned short *) &tmpaddr[4]) =
953 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
954 iap = &tmpaddr[0];
955 }
956
957 memcpy(ndev->dev_addr, iap, ETH_ALEN);
958
959 /* Adjust MAC if using macaddr */
960 if (iap == macaddr)
961 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
962 }
963
964 /* ------------------------------------------------------------------------- */
965
966 /*
967 * Phy section
968 */
969 static void fec_enet_adjust_link(struct net_device *ndev)
970 {
971 struct fec_enet_private *fep = netdev_priv(ndev);
972 struct phy_device *phy_dev = fep->phy_dev;
973 unsigned long flags;
974
975 int status_change = 0;
976
977 spin_lock_irqsave(&fep->hw_lock, flags);
978
979 /* Prevent a state halted on mii error */
980 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
981 phy_dev->state = PHY_RESUMING;
982 goto spin_unlock;
983 }
984
985 if (phy_dev->link) {
986 if (!fep->link) {
987 fep->link = phy_dev->link;
988 status_change = 1;
989 }
990
991 if (fep->full_duplex != phy_dev->duplex)
992 status_change = 1;
993
994 if (phy_dev->speed != fep->speed) {
995 fep->speed = phy_dev->speed;
996 status_change = 1;
997 }
998
999 /* if any of the above changed restart the FEC */
1000 if (status_change)
1001 fec_restart(ndev, phy_dev->duplex);
1002 } else {
1003 if (fep->link) {
1004 fec_stop(ndev);
1005 status_change = 1;
1006 }
1007 }
1008
1009 spin_unlock:
1010 spin_unlock_irqrestore(&fep->hw_lock, flags);
1011
1012 if (status_change)
1013 phy_print_status(phy_dev);
1014 }
1015
1016 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1017 {
1018 struct fec_enet_private *fep = bus->priv;
1019 unsigned long time_left;
1020
1021 fep->mii_timeout = 0;
1022 init_completion(&fep->mdio_done);
1023
1024 /* start a read op */
1025 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1026 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1027 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1028
1029 /* wait for end of transfer */
1030 time_left = wait_for_completion_timeout(&fep->mdio_done,
1031 usecs_to_jiffies(FEC_MII_TIMEOUT));
1032 if (time_left == 0) {
1033 fep->mii_timeout = 1;
1034 printk(KERN_ERR "FEC: MDIO read timeout\n");
1035 return -ETIMEDOUT;
1036 }
1037
1038 /* return value */
1039 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1040 }
1041
1042 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1043 u16 value)
1044 {
1045 struct fec_enet_private *fep = bus->priv;
1046 unsigned long time_left;
1047
1048 fep->mii_timeout = 0;
1049 init_completion(&fep->mdio_done);
1050
1051 /* start a write op */
1052 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1053 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1054 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1055 fep->hwp + FEC_MII_DATA);
1056
1057 /* wait for end of transfer */
1058 time_left = wait_for_completion_timeout(&fep->mdio_done,
1059 usecs_to_jiffies(FEC_MII_TIMEOUT));
1060 if (time_left == 0) {
1061 fep->mii_timeout = 1;
1062 printk(KERN_ERR "FEC: MDIO write timeout\n");
1063 return -ETIMEDOUT;
1064 }
1065
1066 return 0;
1067 }
1068
1069 static int fec_enet_mdio_reset(struct mii_bus *bus)
1070 {
1071 return 0;
1072 }
1073
1074 static int fec_enet_mii_probe(struct net_device *ndev)
1075 {
1076 struct fec_enet_private *fep = netdev_priv(ndev);
1077 const struct platform_device_id *id_entry =
1078 platform_get_device_id(fep->pdev);
1079 struct phy_device *phy_dev = NULL;
1080 char mdio_bus_id[MII_BUS_ID_SIZE];
1081 char phy_name[MII_BUS_ID_SIZE + 3];
1082 int phy_id;
1083 int dev_id = fep->dev_id;
1084
1085 fep->phy_dev = NULL;
1086
1087 /* check for attached phy */
1088 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1089 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1090 continue;
1091 if (fep->mii_bus->phy_map[phy_id] == NULL)
1092 continue;
1093 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1094 continue;
1095 if (dev_id--)
1096 continue;
1097 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1098 break;
1099 }
1100
1101 if (phy_id >= PHY_MAX_ADDR) {
1102 printk(KERN_INFO
1103 "%s: no PHY, assuming direct connection to switch\n",
1104 ndev->name);
1105 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1106 phy_id = 0;
1107 }
1108
1109 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1110 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1111 fep->phy_interface);
1112 if (IS_ERR(phy_dev)) {
1113 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
1114 return PTR_ERR(phy_dev);
1115 }
1116
1117 /* mask with MAC supported features */
1118 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1119 phy_dev->supported &= PHY_GBIT_FEATURES;
1120 phy_dev->supported |= SUPPORTED_Pause;
1121 }
1122 else
1123 phy_dev->supported &= PHY_BASIC_FEATURES;
1124
1125 phy_dev->advertising = phy_dev->supported;
1126
1127 fep->phy_dev = phy_dev;
1128 fep->link = 0;
1129 fep->full_duplex = 0;
1130
1131 printk(KERN_INFO
1132 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1133 ndev->name,
1134 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1135 fep->phy_dev->irq);
1136
1137 return 0;
1138 }
1139
1140 static int fec_enet_mii_init(struct platform_device *pdev)
1141 {
1142 static struct mii_bus *fec0_mii_bus;
1143 struct net_device *ndev = platform_get_drvdata(pdev);
1144 struct fec_enet_private *fep = netdev_priv(ndev);
1145 const struct platform_device_id *id_entry =
1146 platform_get_device_id(fep->pdev);
1147 int err = -ENXIO, i;
1148
1149 /*
1150 * The dual fec interfaces are not equivalent with enet-mac.
1151 * Here are the differences:
1152 *
1153 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1154 * - fec0 acts as the 1588 time master while fec1 is slave
1155 * - external phys can only be configured by fec0
1156 *
1157 * That is to say fec1 can not work independently. It only works
1158 * when fec0 is working. The reason behind this design is that the
1159 * second interface is added primarily for Switch mode.
1160 *
1161 * Because of the last point above, both phys are attached on fec0
1162 * mdio interface in board design, and need to be configured by
1163 * fec0 mii_bus.
1164 */
1165 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1166 /* fec1 uses fec0 mii_bus */
1167 if (mii_cnt && fec0_mii_bus) {
1168 fep->mii_bus = fec0_mii_bus;
1169 mii_cnt++;
1170 return 0;
1171 }
1172 return -ENOENT;
1173 }
1174
1175 fep->mii_timeout = 0;
1176
1177 /*
1178 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1179 *
1180 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1181 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1182 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1183 * document.
1184 */
1185 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1186 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1187 fep->phy_speed--;
1188 fep->phy_speed <<= 1;
1189 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1190
1191 fep->mii_bus = mdiobus_alloc();
1192 if (fep->mii_bus == NULL) {
1193 err = -ENOMEM;
1194 goto err_out;
1195 }
1196
1197 fep->mii_bus->name = "fec_enet_mii_bus";
1198 fep->mii_bus->read = fec_enet_mdio_read;
1199 fep->mii_bus->write = fec_enet_mdio_write;
1200 fep->mii_bus->reset = fec_enet_mdio_reset;
1201 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1202 pdev->name, fep->dev_id + 1);
1203 fep->mii_bus->priv = fep;
1204 fep->mii_bus->parent = &pdev->dev;
1205
1206 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1207 if (!fep->mii_bus->irq) {
1208 err = -ENOMEM;
1209 goto err_out_free_mdiobus;
1210 }
1211
1212 for (i = 0; i < PHY_MAX_ADDR; i++)
1213 fep->mii_bus->irq[i] = PHY_POLL;
1214
1215 if (mdiobus_register(fep->mii_bus))
1216 goto err_out_free_mdio_irq;
1217
1218 mii_cnt++;
1219
1220 /* save fec0 mii_bus */
1221 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1222 fec0_mii_bus = fep->mii_bus;
1223
1224 return 0;
1225
1226 err_out_free_mdio_irq:
1227 kfree(fep->mii_bus->irq);
1228 err_out_free_mdiobus:
1229 mdiobus_free(fep->mii_bus);
1230 err_out:
1231 return err;
1232 }
1233
1234 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1235 {
1236 if (--mii_cnt == 0) {
1237 mdiobus_unregister(fep->mii_bus);
1238 kfree(fep->mii_bus->irq);
1239 mdiobus_free(fep->mii_bus);
1240 }
1241 }
1242
1243 static int fec_enet_get_settings(struct net_device *ndev,
1244 struct ethtool_cmd *cmd)
1245 {
1246 struct fec_enet_private *fep = netdev_priv(ndev);
1247 struct phy_device *phydev = fep->phy_dev;
1248
1249 if (!phydev)
1250 return -ENODEV;
1251
1252 return phy_ethtool_gset(phydev, cmd);
1253 }
1254
1255 static int fec_enet_set_settings(struct net_device *ndev,
1256 struct ethtool_cmd *cmd)
1257 {
1258 struct fec_enet_private *fep = netdev_priv(ndev);
1259 struct phy_device *phydev = fep->phy_dev;
1260
1261 if (!phydev)
1262 return -ENODEV;
1263
1264 return phy_ethtool_sset(phydev, cmd);
1265 }
1266
1267 static void fec_enet_get_drvinfo(struct net_device *ndev,
1268 struct ethtool_drvinfo *info)
1269 {
1270 struct fec_enet_private *fep = netdev_priv(ndev);
1271
1272 strlcpy(info->driver, fep->pdev->dev.driver->name,
1273 sizeof(info->driver));
1274 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1275 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1276 }
1277
1278 static int fec_enet_get_ts_info(struct net_device *ndev,
1279 struct ethtool_ts_info *info)
1280 {
1281 struct fec_enet_private *fep = netdev_priv(ndev);
1282
1283 if (fep->bufdesc_ex) {
1284
1285 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1286 SOF_TIMESTAMPING_RX_SOFTWARE |
1287 SOF_TIMESTAMPING_SOFTWARE |
1288 SOF_TIMESTAMPING_TX_HARDWARE |
1289 SOF_TIMESTAMPING_RX_HARDWARE |
1290 SOF_TIMESTAMPING_RAW_HARDWARE;
1291 if (fep->ptp_clock)
1292 info->phc_index = ptp_clock_index(fep->ptp_clock);
1293 else
1294 info->phc_index = -1;
1295
1296 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1297 (1 << HWTSTAMP_TX_ON);
1298
1299 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1300 (1 << HWTSTAMP_FILTER_ALL);
1301 return 0;
1302 } else {
1303 return ethtool_op_get_ts_info(ndev, info);
1304 }
1305 }
1306
1307 static void fec_enet_get_pauseparam(struct net_device *ndev,
1308 struct ethtool_pauseparam *pause)
1309 {
1310 struct fec_enet_private *fep = netdev_priv(ndev);
1311
1312 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1313 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1314 pause->rx_pause = pause->tx_pause;
1315 }
1316
1317 static int fec_enet_set_pauseparam(struct net_device *ndev,
1318 struct ethtool_pauseparam *pause)
1319 {
1320 struct fec_enet_private *fep = netdev_priv(ndev);
1321
1322 if (pause->tx_pause != pause->rx_pause) {
1323 netdev_info(ndev,
1324 "hardware only support enable/disable both tx and rx");
1325 return -EINVAL;
1326 }
1327
1328 fep->pause_flag = 0;
1329
1330 /* tx pause must be same as rx pause */
1331 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1332 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1333
1334 if (pause->rx_pause || pause->autoneg) {
1335 fep->phy_dev->supported |= ADVERTISED_Pause;
1336 fep->phy_dev->advertising |= ADVERTISED_Pause;
1337 } else {
1338 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1339 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1340 }
1341
1342 if (pause->autoneg) {
1343 if (netif_running(ndev))
1344 fec_stop(ndev);
1345 phy_start_aneg(fep->phy_dev);
1346 }
1347 if (netif_running(ndev))
1348 fec_restart(ndev, 0);
1349
1350 return 0;
1351 }
1352
1353 static const struct ethtool_ops fec_enet_ethtool_ops = {
1354 .get_pauseparam = fec_enet_get_pauseparam,
1355 .set_pauseparam = fec_enet_set_pauseparam,
1356 .get_settings = fec_enet_get_settings,
1357 .set_settings = fec_enet_set_settings,
1358 .get_drvinfo = fec_enet_get_drvinfo,
1359 .get_link = ethtool_op_get_link,
1360 .get_ts_info = fec_enet_get_ts_info,
1361 };
1362
1363 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1364 {
1365 struct fec_enet_private *fep = netdev_priv(ndev);
1366 struct phy_device *phydev = fep->phy_dev;
1367
1368 if (!netif_running(ndev))
1369 return -EINVAL;
1370
1371 if (!phydev)
1372 return -ENODEV;
1373
1374 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1375 return fec_ptp_ioctl(ndev, rq, cmd);
1376
1377 return phy_mii_ioctl(phydev, rq, cmd);
1378 }
1379
1380 static void fec_enet_free_buffers(struct net_device *ndev)
1381 {
1382 struct fec_enet_private *fep = netdev_priv(ndev);
1383 unsigned int i;
1384 struct sk_buff *skb;
1385 struct bufdesc *bdp;
1386
1387 bdp = fep->rx_bd_base;
1388 for (i = 0; i < RX_RING_SIZE; i++) {
1389 skb = fep->rx_skbuff[i];
1390
1391 if (bdp->cbd_bufaddr)
1392 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1393 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1394 if (skb)
1395 dev_kfree_skb(skb);
1396 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1397 }
1398
1399 bdp = fep->tx_bd_base;
1400 for (i = 0; i < TX_RING_SIZE; i++)
1401 kfree(fep->tx_bounce[i]);
1402 }
1403
1404 static int fec_enet_alloc_buffers(struct net_device *ndev)
1405 {
1406 struct fec_enet_private *fep = netdev_priv(ndev);
1407 unsigned int i;
1408 struct sk_buff *skb;
1409 struct bufdesc *bdp;
1410
1411 bdp = fep->rx_bd_base;
1412 for (i = 0; i < RX_RING_SIZE; i++) {
1413 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1414 if (!skb) {
1415 fec_enet_free_buffers(ndev);
1416 return -ENOMEM;
1417 }
1418 fep->rx_skbuff[i] = skb;
1419
1420 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1421 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1422 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1423
1424 if (fep->bufdesc_ex) {
1425 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1426 ebdp->cbd_esc = BD_ENET_RX_INT;
1427 }
1428
1429 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1430 }
1431
1432 /* Set the last buffer to wrap. */
1433 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1434 bdp->cbd_sc |= BD_SC_WRAP;
1435
1436 bdp = fep->tx_bd_base;
1437 for (i = 0; i < TX_RING_SIZE; i++) {
1438 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1439
1440 bdp->cbd_sc = 0;
1441 bdp->cbd_bufaddr = 0;
1442
1443 if (fep->bufdesc_ex) {
1444 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1445 ebdp->cbd_esc = BD_ENET_RX_INT;
1446 }
1447
1448 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1449 }
1450
1451 /* Set the last buffer to wrap. */
1452 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1453 bdp->cbd_sc |= BD_SC_WRAP;
1454
1455 return 0;
1456 }
1457
1458 static int
1459 fec_enet_open(struct net_device *ndev)
1460 {
1461 struct fec_enet_private *fep = netdev_priv(ndev);
1462 int ret;
1463
1464 napi_enable(&fep->napi);
1465
1466 /* I should reset the ring buffers here, but I don't yet know
1467 * a simple way to do that.
1468 */
1469
1470 ret = fec_enet_alloc_buffers(ndev);
1471 if (ret)
1472 return ret;
1473
1474 /* Probe and connect to PHY when open the interface */
1475 ret = fec_enet_mii_probe(ndev);
1476 if (ret) {
1477 fec_enet_free_buffers(ndev);
1478 return ret;
1479 }
1480 phy_start(fep->phy_dev);
1481 netif_start_queue(ndev);
1482 fep->opened = 1;
1483 return 0;
1484 }
1485
1486 static int
1487 fec_enet_close(struct net_device *ndev)
1488 {
1489 struct fec_enet_private *fep = netdev_priv(ndev);
1490
1491 /* Don't know what to do yet. */
1492 napi_disable(&fep->napi);
1493 fep->opened = 0;
1494 netif_stop_queue(ndev);
1495 fec_stop(ndev);
1496
1497 if (fep->phy_dev) {
1498 phy_stop(fep->phy_dev);
1499 phy_disconnect(fep->phy_dev);
1500 }
1501
1502 fec_enet_free_buffers(ndev);
1503
1504 return 0;
1505 }
1506
1507 /* Set or clear the multicast filter for this adaptor.
1508 * Skeleton taken from sunlance driver.
1509 * The CPM Ethernet implementation allows Multicast as well as individual
1510 * MAC address filtering. Some of the drivers check to make sure it is
1511 * a group multicast address, and discard those that are not. I guess I
1512 * will do the same for now, but just remove the test if you want
1513 * individual filtering as well (do the upper net layers want or support
1514 * this kind of feature?).
1515 */
1516
1517 #define HASH_BITS 6 /* #bits in hash */
1518 #define CRC32_POLY 0xEDB88320
1519
1520 static void set_multicast_list(struct net_device *ndev)
1521 {
1522 struct fec_enet_private *fep = netdev_priv(ndev);
1523 struct netdev_hw_addr *ha;
1524 unsigned int i, bit, data, crc, tmp;
1525 unsigned char hash;
1526
1527 if (ndev->flags & IFF_PROMISC) {
1528 tmp = readl(fep->hwp + FEC_R_CNTRL);
1529 tmp |= 0x8;
1530 writel(tmp, fep->hwp + FEC_R_CNTRL);
1531 return;
1532 }
1533
1534 tmp = readl(fep->hwp + FEC_R_CNTRL);
1535 tmp &= ~0x8;
1536 writel(tmp, fep->hwp + FEC_R_CNTRL);
1537
1538 if (ndev->flags & IFF_ALLMULTI) {
1539 /* Catch all multicast addresses, so set the
1540 * filter to all 1's
1541 */
1542 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1543 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1544
1545 return;
1546 }
1547
1548 /* Clear filter and add the addresses in hash register
1549 */
1550 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1551 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1552
1553 netdev_for_each_mc_addr(ha, ndev) {
1554 /* calculate crc32 value of mac address */
1555 crc = 0xffffffff;
1556
1557 for (i = 0; i < ndev->addr_len; i++) {
1558 data = ha->addr[i];
1559 for (bit = 0; bit < 8; bit++, data >>= 1) {
1560 crc = (crc >> 1) ^
1561 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1562 }
1563 }
1564
1565 /* only upper 6 bits (HASH_BITS) are used
1566 * which point to specific bit in he hash registers
1567 */
1568 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1569
1570 if (hash > 31) {
1571 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1572 tmp |= 1 << (hash - 32);
1573 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1574 } else {
1575 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1576 tmp |= 1 << hash;
1577 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1578 }
1579 }
1580 }
1581
1582 /* Set a MAC change in hardware. */
1583 static int
1584 fec_set_mac_address(struct net_device *ndev, void *p)
1585 {
1586 struct fec_enet_private *fep = netdev_priv(ndev);
1587 struct sockaddr *addr = p;
1588
1589 if (!is_valid_ether_addr(addr->sa_data))
1590 return -EADDRNOTAVAIL;
1591
1592 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1593
1594 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1595 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1596 fep->hwp + FEC_ADDR_LOW);
1597 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1598 fep->hwp + FEC_ADDR_HIGH);
1599 return 0;
1600 }
1601
1602 #ifdef CONFIG_NET_POLL_CONTROLLER
1603 /**
1604 * fec_poll_controller - FEC Poll controller function
1605 * @dev: The FEC network adapter
1606 *
1607 * Polled functionality used by netconsole and others in non interrupt mode
1608 *
1609 */
1610 void fec_poll_controller(struct net_device *dev)
1611 {
1612 int i;
1613 struct fec_enet_private *fep = netdev_priv(dev);
1614
1615 for (i = 0; i < FEC_IRQ_NUM; i++) {
1616 if (fep->irq[i] > 0) {
1617 disable_irq(fep->irq[i]);
1618 fec_enet_interrupt(fep->irq[i], dev);
1619 enable_irq(fep->irq[i]);
1620 }
1621 }
1622 }
1623 #endif
1624
1625 static const struct net_device_ops fec_netdev_ops = {
1626 .ndo_open = fec_enet_open,
1627 .ndo_stop = fec_enet_close,
1628 .ndo_start_xmit = fec_enet_start_xmit,
1629 .ndo_set_rx_mode = set_multicast_list,
1630 .ndo_change_mtu = eth_change_mtu,
1631 .ndo_validate_addr = eth_validate_addr,
1632 .ndo_tx_timeout = fec_timeout,
1633 .ndo_set_mac_address = fec_set_mac_address,
1634 .ndo_do_ioctl = fec_enet_ioctl,
1635 #ifdef CONFIG_NET_POLL_CONTROLLER
1636 .ndo_poll_controller = fec_poll_controller,
1637 #endif
1638 };
1639
1640 /*
1641 * XXX: We need to clean up on failure exits here.
1642 *
1643 */
1644 static int fec_enet_init(struct net_device *ndev)
1645 {
1646 struct fec_enet_private *fep = netdev_priv(ndev);
1647 struct bufdesc *cbd_base;
1648
1649 /* Allocate memory for buffer descriptors. */
1650 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1651 GFP_KERNEL);
1652 if (!cbd_base) {
1653 printk("FEC: allocate descriptor memory failed?\n");
1654 return -ENOMEM;
1655 }
1656
1657 memset(cbd_base, 0, PAGE_SIZE);
1658 spin_lock_init(&fep->hw_lock);
1659
1660 fep->netdev = ndev;
1661
1662 /* Get the Ethernet address */
1663 fec_get_mac(ndev);
1664
1665 /* Set receive and transmit descriptor base. */
1666 fep->rx_bd_base = cbd_base;
1667 if (fep->bufdesc_ex)
1668 fep->tx_bd_base = (struct bufdesc *)
1669 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1670 else
1671 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1672
1673 /* The FEC Ethernet specific entries in the device structure */
1674 ndev->watchdog_timeo = TX_TIMEOUT;
1675 ndev->netdev_ops = &fec_netdev_ops;
1676 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1677
1678 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1679 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1680
1681 fec_restart(ndev, 0);
1682
1683 return 0;
1684 }
1685
1686 #ifdef CONFIG_OF
1687 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1688 {
1689 struct device_node *np = pdev->dev.of_node;
1690
1691 if (np)
1692 return of_get_phy_mode(np);
1693
1694 return -ENODEV;
1695 }
1696
1697 static void fec_reset_phy(struct platform_device *pdev)
1698 {
1699 int err, phy_reset;
1700 int msec = 1;
1701 struct device_node *np = pdev->dev.of_node;
1702
1703 if (!np)
1704 return;
1705
1706 of_property_read_u32(np, "phy-reset-duration", &msec);
1707 /* A sane reset duration should not be longer than 1s */
1708 if (msec > 1000)
1709 msec = 1;
1710
1711 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1712 if (!gpio_is_valid(phy_reset))
1713 return;
1714
1715 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1716 GPIOF_OUT_INIT_LOW, "phy-reset");
1717 if (err) {
1718 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1719 return;
1720 }
1721 msleep(msec);
1722 gpio_set_value(phy_reset, 1);
1723 }
1724 #else /* CONFIG_OF */
1725 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1726 {
1727 return -ENODEV;
1728 }
1729
1730 static void fec_reset_phy(struct platform_device *pdev)
1731 {
1732 /*
1733 * In case of platform probe, the reset has been done
1734 * by machine code.
1735 */
1736 }
1737 #endif /* CONFIG_OF */
1738
1739 static int
1740 fec_probe(struct platform_device *pdev)
1741 {
1742 struct fec_enet_private *fep;
1743 struct fec_platform_data *pdata;
1744 struct net_device *ndev;
1745 int i, irq, ret = 0;
1746 struct resource *r;
1747 const struct of_device_id *of_id;
1748 static int dev_id;
1749 struct pinctrl *pinctrl;
1750 struct regulator *reg_phy;
1751
1752 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1753 if (of_id)
1754 pdev->id_entry = of_id->data;
1755
1756 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1757 if (!r)
1758 return -ENXIO;
1759
1760 r = request_mem_region(r->start, resource_size(r), pdev->name);
1761 if (!r)
1762 return -EBUSY;
1763
1764 /* Init network device */
1765 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1766 if (!ndev) {
1767 ret = -ENOMEM;
1768 goto failed_alloc_etherdev;
1769 }
1770
1771 SET_NETDEV_DEV(ndev, &pdev->dev);
1772
1773 /* setup board info structure */
1774 fep = netdev_priv(ndev);
1775
1776 /* default enable pause frame auto negotiation */
1777 if (pdev->id_entry &&
1778 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1779 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1780
1781 fep->hwp = ioremap(r->start, resource_size(r));
1782 fep->pdev = pdev;
1783 fep->dev_id = dev_id++;
1784
1785 fep->bufdesc_ex = 0;
1786
1787 if (!fep->hwp) {
1788 ret = -ENOMEM;
1789 goto failed_ioremap;
1790 }
1791
1792 platform_set_drvdata(pdev, ndev);
1793
1794 ret = fec_get_phy_mode_dt(pdev);
1795 if (ret < 0) {
1796 pdata = pdev->dev.platform_data;
1797 if (pdata)
1798 fep->phy_interface = pdata->phy;
1799 else
1800 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1801 } else {
1802 fep->phy_interface = ret;
1803 }
1804
1805 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1806 if (IS_ERR(pinctrl)) {
1807 ret = PTR_ERR(pinctrl);
1808 goto failed_pin;
1809 }
1810
1811 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1812 if (IS_ERR(fep->clk_ipg)) {
1813 ret = PTR_ERR(fep->clk_ipg);
1814 goto failed_clk;
1815 }
1816
1817 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1818 if (IS_ERR(fep->clk_ahb)) {
1819 ret = PTR_ERR(fep->clk_ahb);
1820 goto failed_clk;
1821 }
1822
1823 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1824 fep->bufdesc_ex =
1825 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1826 if (IS_ERR(fep->clk_ptp)) {
1827 ret = PTR_ERR(fep->clk_ptp);
1828 fep->bufdesc_ex = 0;
1829 }
1830
1831 clk_prepare_enable(fep->clk_ahb);
1832 clk_prepare_enable(fep->clk_ipg);
1833 if (!IS_ERR(fep->clk_ptp))
1834 clk_prepare_enable(fep->clk_ptp);
1835
1836 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1837 if (!IS_ERR(reg_phy)) {
1838 ret = regulator_enable(reg_phy);
1839 if (ret) {
1840 dev_err(&pdev->dev,
1841 "Failed to enable phy regulator: %d\n", ret);
1842 goto failed_regulator;
1843 }
1844 }
1845
1846 fec_reset_phy(pdev);
1847
1848 if (fep->bufdesc_ex)
1849 fec_ptp_init(ndev, pdev);
1850
1851 ret = fec_enet_init(ndev);
1852 if (ret)
1853 goto failed_init;
1854
1855 for (i = 0; i < FEC_IRQ_NUM; i++) {
1856 irq = platform_get_irq(pdev, i);
1857 if (irq < 0) {
1858 if (i)
1859 break;
1860 ret = irq;
1861 goto failed_irq;
1862 }
1863 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1864 if (ret) {
1865 while (--i >= 0) {
1866 irq = platform_get_irq(pdev, i);
1867 free_irq(irq, ndev);
1868 }
1869 goto failed_irq;
1870 }
1871 }
1872
1873 ret = fec_enet_mii_init(pdev);
1874 if (ret)
1875 goto failed_mii_init;
1876
1877 /* Carrier starts down, phylib will bring it up */
1878 netif_carrier_off(ndev);
1879
1880 ret = register_netdev(ndev);
1881 if (ret)
1882 goto failed_register;
1883
1884 return 0;
1885
1886 failed_register:
1887 fec_enet_mii_remove(fep);
1888 failed_mii_init:
1889 failed_init:
1890 for (i = 0; i < FEC_IRQ_NUM; i++) {
1891 irq = platform_get_irq(pdev, i);
1892 if (irq > 0)
1893 free_irq(irq, ndev);
1894 }
1895 failed_irq:
1896 failed_regulator:
1897 clk_disable_unprepare(fep->clk_ahb);
1898 clk_disable_unprepare(fep->clk_ipg);
1899 if (!IS_ERR(fep->clk_ptp))
1900 clk_disable_unprepare(fep->clk_ptp);
1901 failed_pin:
1902 failed_clk:
1903 iounmap(fep->hwp);
1904 failed_ioremap:
1905 free_netdev(ndev);
1906 failed_alloc_etherdev:
1907 release_mem_region(r->start, resource_size(r));
1908
1909 return ret;
1910 }
1911
1912 static int
1913 fec_drv_remove(struct platform_device *pdev)
1914 {
1915 struct net_device *ndev = platform_get_drvdata(pdev);
1916 struct fec_enet_private *fep = netdev_priv(ndev);
1917 struct resource *r;
1918 int i;
1919
1920 unregister_netdev(ndev);
1921 fec_enet_mii_remove(fep);
1922 del_timer_sync(&fep->time_keep);
1923 clk_disable_unprepare(fep->clk_ptp);
1924 if (fep->ptp_clock)
1925 ptp_clock_unregister(fep->ptp_clock);
1926 clk_disable_unprepare(fep->clk_ahb);
1927 clk_disable_unprepare(fep->clk_ipg);
1928 for (i = 0; i < FEC_IRQ_NUM; i++) {
1929 int irq = platform_get_irq(pdev, i);
1930 if (irq > 0)
1931 free_irq(irq, ndev);
1932 }
1933 iounmap(fep->hwp);
1934 free_netdev(ndev);
1935
1936 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1937 BUG_ON(!r);
1938 release_mem_region(r->start, resource_size(r));
1939
1940 platform_set_drvdata(pdev, NULL);
1941
1942 return 0;
1943 }
1944
1945 #ifdef CONFIG_PM
1946 static int
1947 fec_suspend(struct device *dev)
1948 {
1949 struct net_device *ndev = dev_get_drvdata(dev);
1950 struct fec_enet_private *fep = netdev_priv(ndev);
1951
1952 if (netif_running(ndev)) {
1953 fec_stop(ndev);
1954 netif_device_detach(ndev);
1955 }
1956 clk_disable_unprepare(fep->clk_ahb);
1957 clk_disable_unprepare(fep->clk_ipg);
1958
1959 return 0;
1960 }
1961
1962 static int
1963 fec_resume(struct device *dev)
1964 {
1965 struct net_device *ndev = dev_get_drvdata(dev);
1966 struct fec_enet_private *fep = netdev_priv(ndev);
1967
1968 clk_prepare_enable(fep->clk_ahb);
1969 clk_prepare_enable(fep->clk_ipg);
1970 if (netif_running(ndev)) {
1971 fec_restart(ndev, fep->full_duplex);
1972 netif_device_attach(ndev);
1973 }
1974
1975 return 0;
1976 }
1977
1978 static const struct dev_pm_ops fec_pm_ops = {
1979 .suspend = fec_suspend,
1980 .resume = fec_resume,
1981 .freeze = fec_suspend,
1982 .thaw = fec_resume,
1983 .poweroff = fec_suspend,
1984 .restore = fec_resume,
1985 };
1986 #endif
1987
1988 static struct platform_driver fec_driver = {
1989 .driver = {
1990 .name = DRIVER_NAME,
1991 .owner = THIS_MODULE,
1992 #ifdef CONFIG_PM
1993 .pm = &fec_pm_ops,
1994 #endif
1995 .of_match_table = fec_dt_ids,
1996 },
1997 .id_table = fec_devtype,
1998 .probe = fec_probe,
1999 .remove = fec_drv_remove,
2000 };
2001
2002 module_platform_driver(fec_driver);
2003
2004 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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