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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[deliverable/linux.git] / drivers / net / ethernet / freescale / fec_main.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/in.h>
37 #include <linux/ip.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/icmp.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
45 #include <linux/io.h>
46 #include <linux/irq.h>
47 #include <linux/clk.h>
48 #include <linux/platform_device.h>
49 #include <linux/phy.h>
50 #include <linux/fec.h>
51 #include <linux/of.h>
52 #include <linux/of_device.h>
53 #include <linux/of_gpio.h>
54 #include <linux/of_net.h>
55 #include <linux/regulator/consumer.h>
56 #include <linux/if_vlan.h>
57
58 #include <asm/cacheflush.h>
59
60 #include "fec.h"
61
62 static void set_multicast_list(struct net_device *ndev);
63
64 #if defined(CONFIG_ARM)
65 #define FEC_ALIGNMENT 0xf
66 #else
67 #define FEC_ALIGNMENT 0x3
68 #endif
69
70 #define DRIVER_NAME "fec"
71
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
79
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90 /* Controller has hardware checksum support */
91 #define FEC_QUIRK_HAS_CSUM (1 << 5)
92 /* Controller has hardware vlan support */
93 #define FEC_QUIRK_HAS_VLAN (1 << 6)
94 /* ENET IP errata ERR006358
95 *
96 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
97 * detected as not set during a prior frame transmission, then the
98 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
99 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
100 * frames not being transmitted until there is a 0-to-1 transition on
101 * ENET_TDAR[TDAR].
102 */
103 #define FEC_QUIRK_ERR006358 (1 << 7)
104
105 static struct platform_device_id fec_devtype[] = {
106 {
107 /* keep it for coldfire */
108 .name = DRIVER_NAME,
109 .driver_data = 0,
110 }, {
111 .name = "imx25-fec",
112 .driver_data = FEC_QUIRK_USE_GASKET,
113 }, {
114 .name = "imx27-fec",
115 .driver_data = 0,
116 }, {
117 .name = "imx28-fec",
118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
119 }, {
120 .name = "imx6q-fec",
121 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
122 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
123 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
124 }, {
125 .name = "mvf600-fec",
126 .driver_data = FEC_QUIRK_ENET_MAC,
127 }, {
128 /* sentinel */
129 }
130 };
131 MODULE_DEVICE_TABLE(platform, fec_devtype);
132
133 enum imx_fec_type {
134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
135 IMX27_FEC, /* runs on i.mx27/35/51 */
136 IMX28_FEC,
137 IMX6Q_FEC,
138 MVF600_FEC,
139 };
140
141 static const struct of_device_id fec_dt_ids[] = {
142 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
143 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
144 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
145 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
146 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
147 { /* sentinel */ }
148 };
149 MODULE_DEVICE_TABLE(of, fec_dt_ids);
150
151 static unsigned char macaddr[ETH_ALEN];
152 module_param_array(macaddr, byte, NULL, 0);
153 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
154
155 #if defined(CONFIG_M5272)
156 /*
157 * Some hardware gets it MAC address out of local flash memory.
158 * if this is non-zero then assume it is the address to get MAC from.
159 */
160 #if defined(CONFIG_NETtel)
161 #define FEC_FLASHMAC 0xf0006006
162 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
163 #define FEC_FLASHMAC 0xf0006000
164 #elif defined(CONFIG_CANCam)
165 #define FEC_FLASHMAC 0xf0020000
166 #elif defined (CONFIG_M5272C3)
167 #define FEC_FLASHMAC (0xffe04000 + 4)
168 #elif defined(CONFIG_MOD5272)
169 #define FEC_FLASHMAC 0xffc0406b
170 #else
171 #define FEC_FLASHMAC 0
172 #endif
173 #endif /* CONFIG_M5272 */
174
175 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
176 #error "FEC: descriptor ring size constants too large"
177 #endif
178
179 /* Interrupt events/masks. */
180 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
181 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
182 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
183 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
184 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
185 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
186 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
187 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
188 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
189 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
190
191 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
192 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
193
194 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
195 */
196 #define PKT_MAXBUF_SIZE 1522
197 #define PKT_MINBUF_SIZE 64
198 #define PKT_MAXBLR_SIZE 1536
199
200 /* FEC receive acceleration */
201 #define FEC_RACC_IPDIS (1 << 1)
202 #define FEC_RACC_PRODIS (1 << 2)
203 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
204
205 /*
206 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
207 * size bits. Other FEC hardware does not, so we need to take that into
208 * account when setting it.
209 */
210 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
211 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
212 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
213 #else
214 #define OPT_FRAME_SIZE 0
215 #endif
216
217 /* FEC MII MMFR bits definition */
218 #define FEC_MMFR_ST (1 << 30)
219 #define FEC_MMFR_OP_READ (2 << 28)
220 #define FEC_MMFR_OP_WRITE (1 << 28)
221 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
222 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
223 #define FEC_MMFR_TA (2 << 16)
224 #define FEC_MMFR_DATA(v) (v & 0xffff)
225
226 #define FEC_MII_TIMEOUT 30000 /* us */
227
228 /* Transmitter timeout */
229 #define TX_TIMEOUT (2 * HZ)
230
231 #define FEC_PAUSE_FLAG_AUTONEG 0x1
232 #define FEC_PAUSE_FLAG_ENABLE 0x2
233
234 static int mii_cnt;
235
236 static inline
237 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
238 {
239 struct bufdesc *new_bd = bdp + 1;
240 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
241 struct bufdesc_ex *ex_base;
242 struct bufdesc *base;
243 int ring_size;
244
245 if (bdp >= fep->tx_bd_base) {
246 base = fep->tx_bd_base;
247 ring_size = fep->tx_ring_size;
248 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
249 } else {
250 base = fep->rx_bd_base;
251 ring_size = fep->rx_ring_size;
252 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
253 }
254
255 if (fep->bufdesc_ex)
256 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
257 ex_base : ex_new_bd);
258 else
259 return (new_bd >= (base + ring_size)) ?
260 base : new_bd;
261 }
262
263 static inline
264 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
265 {
266 struct bufdesc *new_bd = bdp - 1;
267 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
268 struct bufdesc_ex *ex_base;
269 struct bufdesc *base;
270 int ring_size;
271
272 if (bdp >= fep->tx_bd_base) {
273 base = fep->tx_bd_base;
274 ring_size = fep->tx_ring_size;
275 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
276 } else {
277 base = fep->rx_bd_base;
278 ring_size = fep->rx_ring_size;
279 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
280 }
281
282 if (fep->bufdesc_ex)
283 return (struct bufdesc *)((ex_new_bd < ex_base) ?
284 (ex_new_bd + ring_size) : ex_new_bd);
285 else
286 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
287 }
288
289 static void *swap_buffer(void *bufaddr, int len)
290 {
291 int i;
292 unsigned int *buf = bufaddr;
293
294 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
295 *buf = cpu_to_be32(*buf);
296
297 return bufaddr;
298 }
299
300 static int
301 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
302 {
303 /* Only run for packets requiring a checksum. */
304 if (skb->ip_summed != CHECKSUM_PARTIAL)
305 return 0;
306
307 if (unlikely(skb_cow_head(skb, 0)))
308 return -1;
309
310 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
311
312 return 0;
313 }
314
315 static netdev_tx_t
316 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
317 {
318 struct fec_enet_private *fep = netdev_priv(ndev);
319 const struct platform_device_id *id_entry =
320 platform_get_device_id(fep->pdev);
321 struct bufdesc *bdp, *bdp_pre;
322 void *bufaddr;
323 unsigned short status;
324 unsigned int index;
325
326 /* Fill in a Tx ring entry */
327 bdp = fep->cur_tx;
328
329 status = bdp->cbd_sc;
330
331 if (status & BD_ENET_TX_READY) {
332 /* Ooops. All transmit buffers are full. Bail out.
333 * This should not happen, since ndev->tbusy should be set.
334 */
335 netdev_err(ndev, "tx queue full!\n");
336 return NETDEV_TX_BUSY;
337 }
338
339 /* Protocol checksum off-load for TCP and UDP. */
340 if (fec_enet_clear_csum(skb, ndev)) {
341 dev_kfree_skb_any(skb);
342 return NETDEV_TX_OK;
343 }
344
345 /* Clear all of the status flags */
346 status &= ~BD_ENET_TX_STATS;
347
348 /* Set buffer length and buffer pointer */
349 bufaddr = skb->data;
350 bdp->cbd_datlen = skb->len;
351
352 /*
353 * On some FEC implementations data must be aligned on
354 * 4-byte boundaries. Use bounce buffers to copy data
355 * and get it aligned. Ugh.
356 */
357 if (fep->bufdesc_ex)
358 index = (struct bufdesc_ex *)bdp -
359 (struct bufdesc_ex *)fep->tx_bd_base;
360 else
361 index = bdp - fep->tx_bd_base;
362
363 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
364 memcpy(fep->tx_bounce[index], skb->data, skb->len);
365 bufaddr = fep->tx_bounce[index];
366 }
367
368 /*
369 * Some design made an incorrect assumption on endian mode of
370 * the system that it's running on. As the result, driver has to
371 * swap every frame going to and coming from the controller.
372 */
373 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
374 swap_buffer(bufaddr, skb->len);
375
376 /* Save skb pointer */
377 fep->tx_skbuff[index] = skb;
378
379 /* Push the data cache so the CPM does not get stale memory
380 * data.
381 */
382 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
383 skb->len, DMA_TO_DEVICE);
384 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
385 bdp->cbd_bufaddr = 0;
386 fep->tx_skbuff[index] = NULL;
387 dev_kfree_skb_any(skb);
388 if (net_ratelimit())
389 netdev_err(ndev, "Tx DMA memory map failed\n");
390 return NETDEV_TX_OK;
391 }
392
393 if (fep->bufdesc_ex) {
394
395 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
396 ebdp->cbd_bdu = 0;
397 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
398 fep->hwts_tx_en)) {
399 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
400 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
401 } else {
402 ebdp->cbd_esc = BD_ENET_TX_INT;
403
404 /* Enable protocol checksum flags
405 * We do not bother with the IP Checksum bits as they
406 * are done by the kernel
407 */
408 if (skb->ip_summed == CHECKSUM_PARTIAL)
409 ebdp->cbd_esc |= BD_ENET_TX_PINS;
410 }
411 }
412
413 /* Send it on its way. Tell FEC it's ready, interrupt when done,
414 * it's the last BD of the frame, and to put the CRC on the end.
415 */
416 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
417 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
418 bdp->cbd_sc = status;
419
420 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
421 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
422 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
423 fep->delay_work.trig_tx = true;
424 schedule_delayed_work(&(fep->delay_work.delay_work),
425 msecs_to_jiffies(1));
426 }
427
428 /* If this was the last BD in the ring, start at the beginning again. */
429 bdp = fec_enet_get_nextdesc(bdp, fep);
430
431 skb_tx_timestamp(skb);
432
433 fep->cur_tx = bdp;
434
435 if (fep->cur_tx == fep->dirty_tx)
436 netif_stop_queue(ndev);
437
438 /* Trigger transmission start */
439 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
440
441 return NETDEV_TX_OK;
442 }
443
444 /* Init RX & TX buffer descriptors
445 */
446 static void fec_enet_bd_init(struct net_device *dev)
447 {
448 struct fec_enet_private *fep = netdev_priv(dev);
449 struct bufdesc *bdp;
450 unsigned int i;
451
452 /* Initialize the receive buffer descriptors. */
453 bdp = fep->rx_bd_base;
454 for (i = 0; i < fep->rx_ring_size; i++) {
455
456 /* Initialize the BD for every fragment in the page. */
457 if (bdp->cbd_bufaddr)
458 bdp->cbd_sc = BD_ENET_RX_EMPTY;
459 else
460 bdp->cbd_sc = 0;
461 bdp = fec_enet_get_nextdesc(bdp, fep);
462 }
463
464 /* Set the last buffer to wrap */
465 bdp = fec_enet_get_prevdesc(bdp, fep);
466 bdp->cbd_sc |= BD_SC_WRAP;
467
468 fep->cur_rx = fep->rx_bd_base;
469
470 /* ...and the same for transmit */
471 bdp = fep->tx_bd_base;
472 fep->cur_tx = bdp;
473 for (i = 0; i < fep->tx_ring_size; i++) {
474
475 /* Initialize the BD for every fragment in the page. */
476 bdp->cbd_sc = 0;
477 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
478 dev_kfree_skb_any(fep->tx_skbuff[i]);
479 fep->tx_skbuff[i] = NULL;
480 }
481 bdp->cbd_bufaddr = 0;
482 bdp = fec_enet_get_nextdesc(bdp, fep);
483 }
484
485 /* Set the last buffer to wrap */
486 bdp = fec_enet_get_prevdesc(bdp, fep);
487 bdp->cbd_sc |= BD_SC_WRAP;
488 fep->dirty_tx = bdp;
489 }
490
491 /* This function is called to start or restart the FEC during a link
492 * change. This only happens when switching between half and full
493 * duplex.
494 */
495 static void
496 fec_restart(struct net_device *ndev, int duplex)
497 {
498 struct fec_enet_private *fep = netdev_priv(ndev);
499 const struct platform_device_id *id_entry =
500 platform_get_device_id(fep->pdev);
501 int i;
502 u32 val;
503 u32 temp_mac[2];
504 u32 rcntl = OPT_FRAME_SIZE | 0x04;
505 u32 ecntl = 0x2; /* ETHEREN */
506
507 if (netif_running(ndev)) {
508 netif_device_detach(ndev);
509 napi_disable(&fep->napi);
510 netif_stop_queue(ndev);
511 netif_tx_lock_bh(ndev);
512 }
513
514 /* Whack a reset. We should wait for this. */
515 writel(1, fep->hwp + FEC_ECNTRL);
516 udelay(10);
517
518 /*
519 * enet-mac reset will reset mac address registers too,
520 * so need to reconfigure it.
521 */
522 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
523 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
524 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
525 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
526 }
527
528 /* Clear any outstanding interrupt. */
529 writel(0xffc00000, fep->hwp + FEC_IEVENT);
530
531 /* Set maximum receive buffer size. */
532 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
533
534 fec_enet_bd_init(ndev);
535
536 /* Set receive and transmit descriptor base. */
537 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
538 if (fep->bufdesc_ex)
539 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
540 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
541 else
542 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
543 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
544
545
546 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
547 if (fep->tx_skbuff[i]) {
548 dev_kfree_skb_any(fep->tx_skbuff[i]);
549 fep->tx_skbuff[i] = NULL;
550 }
551 }
552
553 /* Enable MII mode */
554 if (duplex) {
555 /* FD enable */
556 writel(0x04, fep->hwp + FEC_X_CNTRL);
557 } else {
558 /* No Rcv on Xmit */
559 rcntl |= 0x02;
560 writel(0x0, fep->hwp + FEC_X_CNTRL);
561 }
562
563 fep->full_duplex = duplex;
564
565 /* Set MII speed */
566 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
567
568 #if !defined(CONFIG_M5272)
569 /* set RX checksum */
570 val = readl(fep->hwp + FEC_RACC);
571 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
572 val |= FEC_RACC_OPTIONS;
573 else
574 val &= ~FEC_RACC_OPTIONS;
575 writel(val, fep->hwp + FEC_RACC);
576 #endif
577
578 /*
579 * The phy interface and speed need to get configured
580 * differently on enet-mac.
581 */
582 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
583 /* Enable flow control and length check */
584 rcntl |= 0x40000000 | 0x00000020;
585
586 /* RGMII, RMII or MII */
587 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
588 rcntl |= (1 << 6);
589 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
590 rcntl |= (1 << 8);
591 else
592 rcntl &= ~(1 << 8);
593
594 /* 1G, 100M or 10M */
595 if (fep->phy_dev) {
596 if (fep->phy_dev->speed == SPEED_1000)
597 ecntl |= (1 << 5);
598 else if (fep->phy_dev->speed == SPEED_100)
599 rcntl &= ~(1 << 9);
600 else
601 rcntl |= (1 << 9);
602 }
603 } else {
604 #ifdef FEC_MIIGSK_ENR
605 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
606 u32 cfgr;
607 /* disable the gasket and wait */
608 writel(0, fep->hwp + FEC_MIIGSK_ENR);
609 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
610 udelay(1);
611
612 /*
613 * configure the gasket:
614 * RMII, 50 MHz, no loopback, no echo
615 * MII, 25 MHz, no loopback, no echo
616 */
617 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
618 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
619 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
620 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
621 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
622
623 /* re-enable the gasket */
624 writel(2, fep->hwp + FEC_MIIGSK_ENR);
625 }
626 #endif
627 }
628
629 #if !defined(CONFIG_M5272)
630 /* enable pause frame*/
631 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
632 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
633 fep->phy_dev && fep->phy_dev->pause)) {
634 rcntl |= FEC_ENET_FCE;
635
636 /* set FIFO threshold parameter to reduce overrun */
637 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
638 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
639 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
640 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
641
642 /* OPD */
643 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
644 } else {
645 rcntl &= ~FEC_ENET_FCE;
646 }
647 #endif /* !defined(CONFIG_M5272) */
648
649 writel(rcntl, fep->hwp + FEC_R_CNTRL);
650
651 /* Setup multicast filter. */
652 set_multicast_list(ndev);
653 #ifndef CONFIG_M5272
654 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
655 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
656 #endif
657
658 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
659 /* enable ENET endian swap */
660 ecntl |= (1 << 8);
661 /* enable ENET store and forward mode */
662 writel(1 << 8, fep->hwp + FEC_X_WMRK);
663 }
664
665 if (fep->bufdesc_ex)
666 ecntl |= (1 << 4);
667
668 #ifndef CONFIG_M5272
669 /* Enable the MIB statistic event counters */
670 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
671 #endif
672
673 /* And last, enable the transmit and receive processing */
674 writel(ecntl, fep->hwp + FEC_ECNTRL);
675 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
676
677 if (fep->bufdesc_ex)
678 fec_ptp_start_cyclecounter(ndev);
679
680 /* Enable interrupts we wish to service */
681 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
682
683 if (netif_running(ndev)) {
684 netif_tx_unlock_bh(ndev);
685 netif_wake_queue(ndev);
686 napi_enable(&fep->napi);
687 netif_device_attach(ndev);
688 }
689 }
690
691 static void
692 fec_stop(struct net_device *ndev)
693 {
694 struct fec_enet_private *fep = netdev_priv(ndev);
695 const struct platform_device_id *id_entry =
696 platform_get_device_id(fep->pdev);
697 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
698
699 /* We cannot expect a graceful transmit stop without link !!! */
700 if (fep->link) {
701 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
702 udelay(10);
703 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
704 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
705 }
706
707 /* Whack a reset. We should wait for this. */
708 writel(1, fep->hwp + FEC_ECNTRL);
709 udelay(10);
710 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
711 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
712
713 /* We have to keep ENET enabled to have MII interrupt stay working */
714 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
715 writel(2, fep->hwp + FEC_ECNTRL);
716 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
717 }
718 }
719
720
721 static void
722 fec_timeout(struct net_device *ndev)
723 {
724 struct fec_enet_private *fep = netdev_priv(ndev);
725
726 ndev->stats.tx_errors++;
727
728 fep->delay_work.timeout = true;
729 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
730 }
731
732 static void fec_enet_work(struct work_struct *work)
733 {
734 struct fec_enet_private *fep =
735 container_of(work,
736 struct fec_enet_private,
737 delay_work.delay_work.work);
738
739 if (fep->delay_work.timeout) {
740 fep->delay_work.timeout = false;
741 fec_restart(fep->netdev, fep->full_duplex);
742 netif_wake_queue(fep->netdev);
743 }
744
745 if (fep->delay_work.trig_tx) {
746 fep->delay_work.trig_tx = false;
747 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
748 }
749 }
750
751 static void
752 fec_enet_tx(struct net_device *ndev)
753 {
754 struct fec_enet_private *fep;
755 struct bufdesc *bdp;
756 unsigned short status;
757 struct sk_buff *skb;
758 int index = 0;
759
760 fep = netdev_priv(ndev);
761 bdp = fep->dirty_tx;
762
763 /* get next bdp of dirty_tx */
764 bdp = fec_enet_get_nextdesc(bdp, fep);
765
766 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
767
768 /* current queue is empty */
769 if (bdp == fep->cur_tx)
770 break;
771
772 if (fep->bufdesc_ex)
773 index = (struct bufdesc_ex *)bdp -
774 (struct bufdesc_ex *)fep->tx_bd_base;
775 else
776 index = bdp - fep->tx_bd_base;
777
778 skb = fep->tx_skbuff[index];
779 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
780 DMA_TO_DEVICE);
781 bdp->cbd_bufaddr = 0;
782
783 /* Check for errors. */
784 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
785 BD_ENET_TX_RL | BD_ENET_TX_UN |
786 BD_ENET_TX_CSL)) {
787 ndev->stats.tx_errors++;
788 if (status & BD_ENET_TX_HB) /* No heartbeat */
789 ndev->stats.tx_heartbeat_errors++;
790 if (status & BD_ENET_TX_LC) /* Late collision */
791 ndev->stats.tx_window_errors++;
792 if (status & BD_ENET_TX_RL) /* Retrans limit */
793 ndev->stats.tx_aborted_errors++;
794 if (status & BD_ENET_TX_UN) /* Underrun */
795 ndev->stats.tx_fifo_errors++;
796 if (status & BD_ENET_TX_CSL) /* Carrier lost */
797 ndev->stats.tx_carrier_errors++;
798 } else {
799 ndev->stats.tx_packets++;
800 ndev->stats.tx_bytes += bdp->cbd_datlen;
801 }
802
803 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
804 fep->bufdesc_ex) {
805 struct skb_shared_hwtstamps shhwtstamps;
806 unsigned long flags;
807 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
808
809 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
810 spin_lock_irqsave(&fep->tmreg_lock, flags);
811 shhwtstamps.hwtstamp = ns_to_ktime(
812 timecounter_cyc2time(&fep->tc, ebdp->ts));
813 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
814 skb_tstamp_tx(skb, &shhwtstamps);
815 }
816
817 if (status & BD_ENET_TX_READY)
818 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
819
820 /* Deferred means some collisions occurred during transmit,
821 * but we eventually sent the packet OK.
822 */
823 if (status & BD_ENET_TX_DEF)
824 ndev->stats.collisions++;
825
826 /* Free the sk buffer associated with this last transmit */
827 dev_kfree_skb_any(skb);
828 fep->tx_skbuff[index] = NULL;
829
830 fep->dirty_tx = bdp;
831
832 /* Update pointer to next buffer descriptor to be transmitted */
833 bdp = fec_enet_get_nextdesc(bdp, fep);
834
835 /* Since we have freed up a buffer, the ring is no longer full
836 */
837 if (fep->dirty_tx != fep->cur_tx) {
838 if (netif_queue_stopped(ndev))
839 netif_wake_queue(ndev);
840 }
841 }
842 return;
843 }
844
845
846 /* During a receive, the cur_rx points to the current incoming buffer.
847 * When we update through the ring, if the next incoming buffer has
848 * not been given to the system, we just set the empty indicator,
849 * effectively tossing the packet.
850 */
851 static int
852 fec_enet_rx(struct net_device *ndev, int budget)
853 {
854 struct fec_enet_private *fep = netdev_priv(ndev);
855 const struct platform_device_id *id_entry =
856 platform_get_device_id(fep->pdev);
857 struct bufdesc *bdp;
858 unsigned short status;
859 struct sk_buff *skb;
860 ushort pkt_len;
861 __u8 *data;
862 int pkt_received = 0;
863 struct bufdesc_ex *ebdp = NULL;
864 bool vlan_packet_rcvd = false;
865 u16 vlan_tag;
866 int index = 0;
867
868 #ifdef CONFIG_M532x
869 flush_cache_all();
870 #endif
871
872 /* First, grab all of the stats for the incoming packet.
873 * These get messed up if we get called due to a busy condition.
874 */
875 bdp = fep->cur_rx;
876
877 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
878
879 if (pkt_received >= budget)
880 break;
881 pkt_received++;
882
883 /* Since we have allocated space to hold a complete frame,
884 * the last indicator should be set.
885 */
886 if ((status & BD_ENET_RX_LAST) == 0)
887 netdev_err(ndev, "rcv is not +last\n");
888
889 if (!fep->opened)
890 goto rx_processing_done;
891
892 /* Check for errors. */
893 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
894 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
895 ndev->stats.rx_errors++;
896 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
897 /* Frame too long or too short. */
898 ndev->stats.rx_length_errors++;
899 }
900 if (status & BD_ENET_RX_NO) /* Frame alignment */
901 ndev->stats.rx_frame_errors++;
902 if (status & BD_ENET_RX_CR) /* CRC Error */
903 ndev->stats.rx_crc_errors++;
904 if (status & BD_ENET_RX_OV) /* FIFO overrun */
905 ndev->stats.rx_fifo_errors++;
906 }
907
908 /* Report late collisions as a frame error.
909 * On this error, the BD is closed, but we don't know what we
910 * have in the buffer. So, just drop this frame on the floor.
911 */
912 if (status & BD_ENET_RX_CL) {
913 ndev->stats.rx_errors++;
914 ndev->stats.rx_frame_errors++;
915 goto rx_processing_done;
916 }
917
918 /* Process the incoming frame. */
919 ndev->stats.rx_packets++;
920 pkt_len = bdp->cbd_datlen;
921 ndev->stats.rx_bytes += pkt_len;
922
923 if (fep->bufdesc_ex)
924 index = (struct bufdesc_ex *)bdp -
925 (struct bufdesc_ex *)fep->rx_bd_base;
926 else
927 index = bdp - fep->rx_bd_base;
928 data = fep->rx_skbuff[index]->data;
929 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
930 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
931
932 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
933 swap_buffer(data, pkt_len);
934
935 /* Extract the enhanced buffer descriptor */
936 ebdp = NULL;
937 if (fep->bufdesc_ex)
938 ebdp = (struct bufdesc_ex *)bdp;
939
940 /* If this is a VLAN packet remove the VLAN Tag */
941 vlan_packet_rcvd = false;
942 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
943 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
944 /* Push and remove the vlan tag */
945 struct vlan_hdr *vlan_header =
946 (struct vlan_hdr *) (data + ETH_HLEN);
947 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
948 pkt_len -= VLAN_HLEN;
949
950 vlan_packet_rcvd = true;
951 }
952
953 /* This does 16 byte alignment, exactly what we need.
954 * The packet length includes FCS, but we don't want to
955 * include that when passing upstream as it messes up
956 * bridging applications.
957 */
958 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
959
960 if (unlikely(!skb)) {
961 ndev->stats.rx_dropped++;
962 } else {
963 int payload_offset = (2 * ETH_ALEN);
964 skb_reserve(skb, NET_IP_ALIGN);
965 skb_put(skb, pkt_len - 4); /* Make room */
966
967 /* Extract the frame data without the VLAN header. */
968 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
969 if (vlan_packet_rcvd)
970 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
971 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
972 data + payload_offset,
973 pkt_len - 4 - (2 * ETH_ALEN));
974
975 skb->protocol = eth_type_trans(skb, ndev);
976
977 /* Get receive timestamp from the skb */
978 if (fep->hwts_rx_en && fep->bufdesc_ex) {
979 struct skb_shared_hwtstamps *shhwtstamps =
980 skb_hwtstamps(skb);
981 unsigned long flags;
982
983 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
984
985 spin_lock_irqsave(&fep->tmreg_lock, flags);
986 shhwtstamps->hwtstamp = ns_to_ktime(
987 timecounter_cyc2time(&fep->tc, ebdp->ts));
988 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
989 }
990
991 if (fep->bufdesc_ex &&
992 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
993 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
994 /* don't check it */
995 skb->ip_summed = CHECKSUM_UNNECESSARY;
996 } else {
997 skb_checksum_none_assert(skb);
998 }
999 }
1000
1001 /* Handle received VLAN packets */
1002 if (vlan_packet_rcvd)
1003 __vlan_hwaccel_put_tag(skb,
1004 htons(ETH_P_8021Q),
1005 vlan_tag);
1006
1007 napi_gro_receive(&fep->napi, skb);
1008 }
1009
1010 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1011 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1012 rx_processing_done:
1013 /* Clear the status flags for this buffer */
1014 status &= ~BD_ENET_RX_STATS;
1015
1016 /* Mark the buffer empty */
1017 status |= BD_ENET_RX_EMPTY;
1018 bdp->cbd_sc = status;
1019
1020 if (fep->bufdesc_ex) {
1021 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1022
1023 ebdp->cbd_esc = BD_ENET_RX_INT;
1024 ebdp->cbd_prot = 0;
1025 ebdp->cbd_bdu = 0;
1026 }
1027
1028 /* Update BD pointer to next entry */
1029 bdp = fec_enet_get_nextdesc(bdp, fep);
1030
1031 /* Doing this here will keep the FEC running while we process
1032 * incoming frames. On a heavily loaded network, we should be
1033 * able to keep up at the expense of system resources.
1034 */
1035 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1036 }
1037 fep->cur_rx = bdp;
1038
1039 return pkt_received;
1040 }
1041
1042 static irqreturn_t
1043 fec_enet_interrupt(int irq, void *dev_id)
1044 {
1045 struct net_device *ndev = dev_id;
1046 struct fec_enet_private *fep = netdev_priv(ndev);
1047 uint int_events;
1048 irqreturn_t ret = IRQ_NONE;
1049
1050 do {
1051 int_events = readl(fep->hwp + FEC_IEVENT);
1052 writel(int_events, fep->hwp + FEC_IEVENT);
1053
1054 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1055 ret = IRQ_HANDLED;
1056
1057 /* Disable the RX interrupt */
1058 if (napi_schedule_prep(&fep->napi)) {
1059 writel(FEC_RX_DISABLED_IMASK,
1060 fep->hwp + FEC_IMASK);
1061 __napi_schedule(&fep->napi);
1062 }
1063 }
1064
1065 if (int_events & FEC_ENET_MII) {
1066 ret = IRQ_HANDLED;
1067 complete(&fep->mdio_done);
1068 }
1069 } while (int_events);
1070
1071 return ret;
1072 }
1073
1074 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1075 {
1076 struct net_device *ndev = napi->dev;
1077 int pkts = fec_enet_rx(ndev, budget);
1078 struct fec_enet_private *fep = netdev_priv(ndev);
1079
1080 fec_enet_tx(ndev);
1081
1082 if (pkts < budget) {
1083 napi_complete(napi);
1084 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1085 }
1086 return pkts;
1087 }
1088
1089 /* ------------------------------------------------------------------------- */
1090 static void fec_get_mac(struct net_device *ndev)
1091 {
1092 struct fec_enet_private *fep = netdev_priv(ndev);
1093 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1094 unsigned char *iap, tmpaddr[ETH_ALEN];
1095
1096 /*
1097 * try to get mac address in following order:
1098 *
1099 * 1) module parameter via kernel command line in form
1100 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1101 */
1102 iap = macaddr;
1103
1104 /*
1105 * 2) from device tree data
1106 */
1107 if (!is_valid_ether_addr(iap)) {
1108 struct device_node *np = fep->pdev->dev.of_node;
1109 if (np) {
1110 const char *mac = of_get_mac_address(np);
1111 if (mac)
1112 iap = (unsigned char *) mac;
1113 }
1114 }
1115
1116 /*
1117 * 3) from flash or fuse (via platform data)
1118 */
1119 if (!is_valid_ether_addr(iap)) {
1120 #ifdef CONFIG_M5272
1121 if (FEC_FLASHMAC)
1122 iap = (unsigned char *)FEC_FLASHMAC;
1123 #else
1124 if (pdata)
1125 iap = (unsigned char *)&pdata->mac;
1126 #endif
1127 }
1128
1129 /*
1130 * 4) FEC mac registers set by bootloader
1131 */
1132 if (!is_valid_ether_addr(iap)) {
1133 *((__be32 *) &tmpaddr[0]) =
1134 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1135 *((__be16 *) &tmpaddr[4]) =
1136 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1137 iap = &tmpaddr[0];
1138 }
1139
1140 /*
1141 * 5) random mac address
1142 */
1143 if (!is_valid_ether_addr(iap)) {
1144 /* Report it and use a random ethernet address instead */
1145 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1146 eth_hw_addr_random(ndev);
1147 netdev_info(ndev, "Using random MAC address: %pM\n",
1148 ndev->dev_addr);
1149 return;
1150 }
1151
1152 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1153
1154 /* Adjust MAC if using macaddr */
1155 if (iap == macaddr)
1156 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1157 }
1158
1159 /* ------------------------------------------------------------------------- */
1160
1161 /*
1162 * Phy section
1163 */
1164 static void fec_enet_adjust_link(struct net_device *ndev)
1165 {
1166 struct fec_enet_private *fep = netdev_priv(ndev);
1167 struct phy_device *phy_dev = fep->phy_dev;
1168 int status_change = 0;
1169
1170 /* Prevent a state halted on mii error */
1171 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1172 phy_dev->state = PHY_RESUMING;
1173 return;
1174 }
1175
1176 if (phy_dev->link) {
1177 if (!fep->link) {
1178 fep->link = phy_dev->link;
1179 status_change = 1;
1180 }
1181
1182 if (fep->full_duplex != phy_dev->duplex)
1183 status_change = 1;
1184
1185 if (phy_dev->speed != fep->speed) {
1186 fep->speed = phy_dev->speed;
1187 status_change = 1;
1188 }
1189
1190 /* if any of the above changed restart the FEC */
1191 if (status_change)
1192 fec_restart(ndev, phy_dev->duplex);
1193 } else {
1194 if (fep->link) {
1195 fec_stop(ndev);
1196 fep->link = phy_dev->link;
1197 status_change = 1;
1198 }
1199 }
1200
1201 if (status_change)
1202 phy_print_status(phy_dev);
1203 }
1204
1205 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1206 {
1207 struct fec_enet_private *fep = bus->priv;
1208 unsigned long time_left;
1209
1210 fep->mii_timeout = 0;
1211 init_completion(&fep->mdio_done);
1212
1213 /* start a read op */
1214 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1215 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1216 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1217
1218 /* wait for end of transfer */
1219 time_left = wait_for_completion_timeout(&fep->mdio_done,
1220 usecs_to_jiffies(FEC_MII_TIMEOUT));
1221 if (time_left == 0) {
1222 fep->mii_timeout = 1;
1223 netdev_err(fep->netdev, "MDIO read timeout\n");
1224 return -ETIMEDOUT;
1225 }
1226
1227 /* return value */
1228 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1229 }
1230
1231 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1232 u16 value)
1233 {
1234 struct fec_enet_private *fep = bus->priv;
1235 unsigned long time_left;
1236
1237 fep->mii_timeout = 0;
1238 init_completion(&fep->mdio_done);
1239
1240 /* start a write op */
1241 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1242 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1243 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1244 fep->hwp + FEC_MII_DATA);
1245
1246 /* wait for end of transfer */
1247 time_left = wait_for_completion_timeout(&fep->mdio_done,
1248 usecs_to_jiffies(FEC_MII_TIMEOUT));
1249 if (time_left == 0) {
1250 fep->mii_timeout = 1;
1251 netdev_err(fep->netdev, "MDIO write timeout\n");
1252 return -ETIMEDOUT;
1253 }
1254
1255 return 0;
1256 }
1257
1258 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1259 {
1260 struct fec_enet_private *fep = netdev_priv(ndev);
1261 int ret;
1262
1263 if (enable) {
1264 ret = clk_prepare_enable(fep->clk_ahb);
1265 if (ret)
1266 return ret;
1267 ret = clk_prepare_enable(fep->clk_ipg);
1268 if (ret)
1269 goto failed_clk_ipg;
1270 if (fep->clk_enet_out) {
1271 ret = clk_prepare_enable(fep->clk_enet_out);
1272 if (ret)
1273 goto failed_clk_enet_out;
1274 }
1275 if (fep->clk_ptp) {
1276 ret = clk_prepare_enable(fep->clk_ptp);
1277 if (ret)
1278 goto failed_clk_ptp;
1279 }
1280 } else {
1281 clk_disable_unprepare(fep->clk_ahb);
1282 clk_disable_unprepare(fep->clk_ipg);
1283 if (fep->clk_enet_out)
1284 clk_disable_unprepare(fep->clk_enet_out);
1285 if (fep->clk_ptp)
1286 clk_disable_unprepare(fep->clk_ptp);
1287 }
1288
1289 return 0;
1290 failed_clk_ptp:
1291 if (fep->clk_enet_out)
1292 clk_disable_unprepare(fep->clk_enet_out);
1293 failed_clk_enet_out:
1294 clk_disable_unprepare(fep->clk_ipg);
1295 failed_clk_ipg:
1296 clk_disable_unprepare(fep->clk_ahb);
1297
1298 return ret;
1299 }
1300
1301 static int fec_enet_mii_probe(struct net_device *ndev)
1302 {
1303 struct fec_enet_private *fep = netdev_priv(ndev);
1304 const struct platform_device_id *id_entry =
1305 platform_get_device_id(fep->pdev);
1306 struct phy_device *phy_dev = NULL;
1307 char mdio_bus_id[MII_BUS_ID_SIZE];
1308 char phy_name[MII_BUS_ID_SIZE + 3];
1309 int phy_id;
1310 int dev_id = fep->dev_id;
1311
1312 fep->phy_dev = NULL;
1313
1314 /* check for attached phy */
1315 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1316 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1317 continue;
1318 if (fep->mii_bus->phy_map[phy_id] == NULL)
1319 continue;
1320 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1321 continue;
1322 if (dev_id--)
1323 continue;
1324 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1325 break;
1326 }
1327
1328 if (phy_id >= PHY_MAX_ADDR) {
1329 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1330 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1331 phy_id = 0;
1332 }
1333
1334 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1335 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1336 fep->phy_interface);
1337 if (IS_ERR(phy_dev)) {
1338 netdev_err(ndev, "could not attach to PHY\n");
1339 return PTR_ERR(phy_dev);
1340 }
1341
1342 /* mask with MAC supported features */
1343 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1344 phy_dev->supported &= PHY_GBIT_FEATURES;
1345 #if !defined(CONFIG_M5272)
1346 phy_dev->supported |= SUPPORTED_Pause;
1347 #endif
1348 }
1349 else
1350 phy_dev->supported &= PHY_BASIC_FEATURES;
1351
1352 phy_dev->advertising = phy_dev->supported;
1353
1354 fep->phy_dev = phy_dev;
1355 fep->link = 0;
1356 fep->full_duplex = 0;
1357
1358 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1359 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1360 fep->phy_dev->irq);
1361
1362 return 0;
1363 }
1364
1365 static int fec_enet_mii_init(struct platform_device *pdev)
1366 {
1367 static struct mii_bus *fec0_mii_bus;
1368 struct net_device *ndev = platform_get_drvdata(pdev);
1369 struct fec_enet_private *fep = netdev_priv(ndev);
1370 const struct platform_device_id *id_entry =
1371 platform_get_device_id(fep->pdev);
1372 int err = -ENXIO, i;
1373
1374 /*
1375 * The dual fec interfaces are not equivalent with enet-mac.
1376 * Here are the differences:
1377 *
1378 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1379 * - fec0 acts as the 1588 time master while fec1 is slave
1380 * - external phys can only be configured by fec0
1381 *
1382 * That is to say fec1 can not work independently. It only works
1383 * when fec0 is working. The reason behind this design is that the
1384 * second interface is added primarily for Switch mode.
1385 *
1386 * Because of the last point above, both phys are attached on fec0
1387 * mdio interface in board design, and need to be configured by
1388 * fec0 mii_bus.
1389 */
1390 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1391 /* fec1 uses fec0 mii_bus */
1392 if (mii_cnt && fec0_mii_bus) {
1393 fep->mii_bus = fec0_mii_bus;
1394 mii_cnt++;
1395 return 0;
1396 }
1397 return -ENOENT;
1398 }
1399
1400 fep->mii_timeout = 0;
1401
1402 /*
1403 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1404 *
1405 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1406 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1407 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1408 * document.
1409 */
1410 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1411 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1412 fep->phy_speed--;
1413 fep->phy_speed <<= 1;
1414 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1415
1416 fep->mii_bus = mdiobus_alloc();
1417 if (fep->mii_bus == NULL) {
1418 err = -ENOMEM;
1419 goto err_out;
1420 }
1421
1422 fep->mii_bus->name = "fec_enet_mii_bus";
1423 fep->mii_bus->read = fec_enet_mdio_read;
1424 fep->mii_bus->write = fec_enet_mdio_write;
1425 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1426 pdev->name, fep->dev_id + 1);
1427 fep->mii_bus->priv = fep;
1428 fep->mii_bus->parent = &pdev->dev;
1429
1430 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1431 if (!fep->mii_bus->irq) {
1432 err = -ENOMEM;
1433 goto err_out_free_mdiobus;
1434 }
1435
1436 for (i = 0; i < PHY_MAX_ADDR; i++)
1437 fep->mii_bus->irq[i] = PHY_POLL;
1438
1439 if (mdiobus_register(fep->mii_bus))
1440 goto err_out_free_mdio_irq;
1441
1442 mii_cnt++;
1443
1444 /* save fec0 mii_bus */
1445 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1446 fec0_mii_bus = fep->mii_bus;
1447
1448 return 0;
1449
1450 err_out_free_mdio_irq:
1451 kfree(fep->mii_bus->irq);
1452 err_out_free_mdiobus:
1453 mdiobus_free(fep->mii_bus);
1454 err_out:
1455 return err;
1456 }
1457
1458 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1459 {
1460 if (--mii_cnt == 0) {
1461 mdiobus_unregister(fep->mii_bus);
1462 kfree(fep->mii_bus->irq);
1463 mdiobus_free(fep->mii_bus);
1464 }
1465 }
1466
1467 static int fec_enet_get_settings(struct net_device *ndev,
1468 struct ethtool_cmd *cmd)
1469 {
1470 struct fec_enet_private *fep = netdev_priv(ndev);
1471 struct phy_device *phydev = fep->phy_dev;
1472
1473 if (!phydev)
1474 return -ENODEV;
1475
1476 return phy_ethtool_gset(phydev, cmd);
1477 }
1478
1479 static int fec_enet_set_settings(struct net_device *ndev,
1480 struct ethtool_cmd *cmd)
1481 {
1482 struct fec_enet_private *fep = netdev_priv(ndev);
1483 struct phy_device *phydev = fep->phy_dev;
1484
1485 if (!phydev)
1486 return -ENODEV;
1487
1488 return phy_ethtool_sset(phydev, cmd);
1489 }
1490
1491 static void fec_enet_get_drvinfo(struct net_device *ndev,
1492 struct ethtool_drvinfo *info)
1493 {
1494 struct fec_enet_private *fep = netdev_priv(ndev);
1495
1496 strlcpy(info->driver, fep->pdev->dev.driver->name,
1497 sizeof(info->driver));
1498 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1499 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1500 }
1501
1502 static int fec_enet_get_ts_info(struct net_device *ndev,
1503 struct ethtool_ts_info *info)
1504 {
1505 struct fec_enet_private *fep = netdev_priv(ndev);
1506
1507 if (fep->bufdesc_ex) {
1508
1509 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1510 SOF_TIMESTAMPING_RX_SOFTWARE |
1511 SOF_TIMESTAMPING_SOFTWARE |
1512 SOF_TIMESTAMPING_TX_HARDWARE |
1513 SOF_TIMESTAMPING_RX_HARDWARE |
1514 SOF_TIMESTAMPING_RAW_HARDWARE;
1515 if (fep->ptp_clock)
1516 info->phc_index = ptp_clock_index(fep->ptp_clock);
1517 else
1518 info->phc_index = -1;
1519
1520 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1521 (1 << HWTSTAMP_TX_ON);
1522
1523 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1524 (1 << HWTSTAMP_FILTER_ALL);
1525 return 0;
1526 } else {
1527 return ethtool_op_get_ts_info(ndev, info);
1528 }
1529 }
1530
1531 #if !defined(CONFIG_M5272)
1532
1533 static void fec_enet_get_pauseparam(struct net_device *ndev,
1534 struct ethtool_pauseparam *pause)
1535 {
1536 struct fec_enet_private *fep = netdev_priv(ndev);
1537
1538 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1539 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1540 pause->rx_pause = pause->tx_pause;
1541 }
1542
1543 static int fec_enet_set_pauseparam(struct net_device *ndev,
1544 struct ethtool_pauseparam *pause)
1545 {
1546 struct fec_enet_private *fep = netdev_priv(ndev);
1547
1548 if (pause->tx_pause != pause->rx_pause) {
1549 netdev_info(ndev,
1550 "hardware only support enable/disable both tx and rx");
1551 return -EINVAL;
1552 }
1553
1554 fep->pause_flag = 0;
1555
1556 /* tx pause must be same as rx pause */
1557 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1558 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1559
1560 if (pause->rx_pause || pause->autoneg) {
1561 fep->phy_dev->supported |= ADVERTISED_Pause;
1562 fep->phy_dev->advertising |= ADVERTISED_Pause;
1563 } else {
1564 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1565 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1566 }
1567
1568 if (pause->autoneg) {
1569 if (netif_running(ndev))
1570 fec_stop(ndev);
1571 phy_start_aneg(fep->phy_dev);
1572 }
1573 if (netif_running(ndev))
1574 fec_restart(ndev, 0);
1575
1576 return 0;
1577 }
1578
1579 static const struct fec_stat {
1580 char name[ETH_GSTRING_LEN];
1581 u16 offset;
1582 } fec_stats[] = {
1583 /* RMON TX */
1584 { "tx_dropped", RMON_T_DROP },
1585 { "tx_packets", RMON_T_PACKETS },
1586 { "tx_broadcast", RMON_T_BC_PKT },
1587 { "tx_multicast", RMON_T_MC_PKT },
1588 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1589 { "tx_undersize", RMON_T_UNDERSIZE },
1590 { "tx_oversize", RMON_T_OVERSIZE },
1591 { "tx_fragment", RMON_T_FRAG },
1592 { "tx_jabber", RMON_T_JAB },
1593 { "tx_collision", RMON_T_COL },
1594 { "tx_64byte", RMON_T_P64 },
1595 { "tx_65to127byte", RMON_T_P65TO127 },
1596 { "tx_128to255byte", RMON_T_P128TO255 },
1597 { "tx_256to511byte", RMON_T_P256TO511 },
1598 { "tx_512to1023byte", RMON_T_P512TO1023 },
1599 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1600 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1601 { "tx_octets", RMON_T_OCTETS },
1602
1603 /* IEEE TX */
1604 { "IEEE_tx_drop", IEEE_T_DROP },
1605 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1606 { "IEEE_tx_1col", IEEE_T_1COL },
1607 { "IEEE_tx_mcol", IEEE_T_MCOL },
1608 { "IEEE_tx_def", IEEE_T_DEF },
1609 { "IEEE_tx_lcol", IEEE_T_LCOL },
1610 { "IEEE_tx_excol", IEEE_T_EXCOL },
1611 { "IEEE_tx_macerr", IEEE_T_MACERR },
1612 { "IEEE_tx_cserr", IEEE_T_CSERR },
1613 { "IEEE_tx_sqe", IEEE_T_SQE },
1614 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1615 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1616
1617 /* RMON RX */
1618 { "rx_packets", RMON_R_PACKETS },
1619 { "rx_broadcast", RMON_R_BC_PKT },
1620 { "rx_multicast", RMON_R_MC_PKT },
1621 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1622 { "rx_undersize", RMON_R_UNDERSIZE },
1623 { "rx_oversize", RMON_R_OVERSIZE },
1624 { "rx_fragment", RMON_R_FRAG },
1625 { "rx_jabber", RMON_R_JAB },
1626 { "rx_64byte", RMON_R_P64 },
1627 { "rx_65to127byte", RMON_R_P65TO127 },
1628 { "rx_128to255byte", RMON_R_P128TO255 },
1629 { "rx_256to511byte", RMON_R_P256TO511 },
1630 { "rx_512to1023byte", RMON_R_P512TO1023 },
1631 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1632 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1633 { "rx_octets", RMON_R_OCTETS },
1634
1635 /* IEEE RX */
1636 { "IEEE_rx_drop", IEEE_R_DROP },
1637 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1638 { "IEEE_rx_crc", IEEE_R_CRC },
1639 { "IEEE_rx_align", IEEE_R_ALIGN },
1640 { "IEEE_rx_macerr", IEEE_R_MACERR },
1641 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1642 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1643 };
1644
1645 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1646 struct ethtool_stats *stats, u64 *data)
1647 {
1648 struct fec_enet_private *fep = netdev_priv(dev);
1649 int i;
1650
1651 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1652 data[i] = readl(fep->hwp + fec_stats[i].offset);
1653 }
1654
1655 static void fec_enet_get_strings(struct net_device *netdev,
1656 u32 stringset, u8 *data)
1657 {
1658 int i;
1659 switch (stringset) {
1660 case ETH_SS_STATS:
1661 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1662 memcpy(data + i * ETH_GSTRING_LEN,
1663 fec_stats[i].name, ETH_GSTRING_LEN);
1664 break;
1665 }
1666 }
1667
1668 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1669 {
1670 switch (sset) {
1671 case ETH_SS_STATS:
1672 return ARRAY_SIZE(fec_stats);
1673 default:
1674 return -EOPNOTSUPP;
1675 }
1676 }
1677 #endif /* !defined(CONFIG_M5272) */
1678
1679 static int fec_enet_nway_reset(struct net_device *dev)
1680 {
1681 struct fec_enet_private *fep = netdev_priv(dev);
1682 struct phy_device *phydev = fep->phy_dev;
1683
1684 if (!phydev)
1685 return -ENODEV;
1686
1687 return genphy_restart_aneg(phydev);
1688 }
1689
1690 static const struct ethtool_ops fec_enet_ethtool_ops = {
1691 #if !defined(CONFIG_M5272)
1692 .get_pauseparam = fec_enet_get_pauseparam,
1693 .set_pauseparam = fec_enet_set_pauseparam,
1694 #endif
1695 .get_settings = fec_enet_get_settings,
1696 .set_settings = fec_enet_set_settings,
1697 .get_drvinfo = fec_enet_get_drvinfo,
1698 .get_link = ethtool_op_get_link,
1699 .get_ts_info = fec_enet_get_ts_info,
1700 .nway_reset = fec_enet_nway_reset,
1701 #ifndef CONFIG_M5272
1702 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1703 .get_strings = fec_enet_get_strings,
1704 .get_sset_count = fec_enet_get_sset_count,
1705 #endif
1706 };
1707
1708 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1709 {
1710 struct fec_enet_private *fep = netdev_priv(ndev);
1711 struct phy_device *phydev = fep->phy_dev;
1712
1713 if (!netif_running(ndev))
1714 return -EINVAL;
1715
1716 if (!phydev)
1717 return -ENODEV;
1718
1719 if (fep->bufdesc_ex) {
1720 if (cmd == SIOCSHWTSTAMP)
1721 return fec_ptp_set(ndev, rq);
1722 if (cmd == SIOCGHWTSTAMP)
1723 return fec_ptp_get(ndev, rq);
1724 }
1725
1726 return phy_mii_ioctl(phydev, rq, cmd);
1727 }
1728
1729 static void fec_enet_free_buffers(struct net_device *ndev)
1730 {
1731 struct fec_enet_private *fep = netdev_priv(ndev);
1732 unsigned int i;
1733 struct sk_buff *skb;
1734 struct bufdesc *bdp;
1735
1736 bdp = fep->rx_bd_base;
1737 for (i = 0; i < fep->rx_ring_size; i++) {
1738 skb = fep->rx_skbuff[i];
1739
1740 if (bdp->cbd_bufaddr)
1741 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1742 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1743 if (skb)
1744 dev_kfree_skb(skb);
1745 bdp = fec_enet_get_nextdesc(bdp, fep);
1746 }
1747
1748 bdp = fep->tx_bd_base;
1749 for (i = 0; i < fep->tx_ring_size; i++)
1750 kfree(fep->tx_bounce[i]);
1751 }
1752
1753 static int fec_enet_alloc_buffers(struct net_device *ndev)
1754 {
1755 struct fec_enet_private *fep = netdev_priv(ndev);
1756 unsigned int i;
1757 struct sk_buff *skb;
1758 struct bufdesc *bdp;
1759
1760 bdp = fep->rx_bd_base;
1761 for (i = 0; i < fep->rx_ring_size; i++) {
1762 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1763 if (!skb) {
1764 fec_enet_free_buffers(ndev);
1765 return -ENOMEM;
1766 }
1767 fep->rx_skbuff[i] = skb;
1768
1769 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1770 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1771 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1772 fec_enet_free_buffers(ndev);
1773 if (net_ratelimit())
1774 netdev_err(ndev, "Rx DMA memory map failed\n");
1775 return -ENOMEM;
1776 }
1777 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1778
1779 if (fep->bufdesc_ex) {
1780 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1781 ebdp->cbd_esc = BD_ENET_RX_INT;
1782 }
1783
1784 bdp = fec_enet_get_nextdesc(bdp, fep);
1785 }
1786
1787 /* Set the last buffer to wrap. */
1788 bdp = fec_enet_get_prevdesc(bdp, fep);
1789 bdp->cbd_sc |= BD_SC_WRAP;
1790
1791 bdp = fep->tx_bd_base;
1792 for (i = 0; i < fep->tx_ring_size; i++) {
1793 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1794
1795 bdp->cbd_sc = 0;
1796 bdp->cbd_bufaddr = 0;
1797
1798 if (fep->bufdesc_ex) {
1799 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1800 ebdp->cbd_esc = BD_ENET_TX_INT;
1801 }
1802
1803 bdp = fec_enet_get_nextdesc(bdp, fep);
1804 }
1805
1806 /* Set the last buffer to wrap. */
1807 bdp = fec_enet_get_prevdesc(bdp, fep);
1808 bdp->cbd_sc |= BD_SC_WRAP;
1809
1810 return 0;
1811 }
1812
1813 static int
1814 fec_enet_open(struct net_device *ndev)
1815 {
1816 struct fec_enet_private *fep = netdev_priv(ndev);
1817 int ret;
1818
1819 ret = fec_enet_clk_enable(ndev, true);
1820 if (ret)
1821 return ret;
1822
1823 /* I should reset the ring buffers here, but I don't yet know
1824 * a simple way to do that.
1825 */
1826
1827 ret = fec_enet_alloc_buffers(ndev);
1828 if (ret)
1829 return ret;
1830
1831 /* Probe and connect to PHY when open the interface */
1832 ret = fec_enet_mii_probe(ndev);
1833 if (ret) {
1834 fec_enet_free_buffers(ndev);
1835 return ret;
1836 }
1837
1838 napi_enable(&fep->napi);
1839 phy_start(fep->phy_dev);
1840 netif_start_queue(ndev);
1841 fep->opened = 1;
1842 return 0;
1843 }
1844
1845 static int
1846 fec_enet_close(struct net_device *ndev)
1847 {
1848 struct fec_enet_private *fep = netdev_priv(ndev);
1849
1850 /* Don't know what to do yet. */
1851 napi_disable(&fep->napi);
1852 fep->opened = 0;
1853 netif_stop_queue(ndev);
1854 fec_stop(ndev);
1855
1856 if (fep->phy_dev) {
1857 phy_stop(fep->phy_dev);
1858 phy_disconnect(fep->phy_dev);
1859 }
1860
1861 fec_enet_clk_enable(ndev, false);
1862 fec_enet_free_buffers(ndev);
1863
1864 return 0;
1865 }
1866
1867 /* Set or clear the multicast filter for this adaptor.
1868 * Skeleton taken from sunlance driver.
1869 * The CPM Ethernet implementation allows Multicast as well as individual
1870 * MAC address filtering. Some of the drivers check to make sure it is
1871 * a group multicast address, and discard those that are not. I guess I
1872 * will do the same for now, but just remove the test if you want
1873 * individual filtering as well (do the upper net layers want or support
1874 * this kind of feature?).
1875 */
1876
1877 #define HASH_BITS 6 /* #bits in hash */
1878 #define CRC32_POLY 0xEDB88320
1879
1880 static void set_multicast_list(struct net_device *ndev)
1881 {
1882 struct fec_enet_private *fep = netdev_priv(ndev);
1883 struct netdev_hw_addr *ha;
1884 unsigned int i, bit, data, crc, tmp;
1885 unsigned char hash;
1886
1887 if (ndev->flags & IFF_PROMISC) {
1888 tmp = readl(fep->hwp + FEC_R_CNTRL);
1889 tmp |= 0x8;
1890 writel(tmp, fep->hwp + FEC_R_CNTRL);
1891 return;
1892 }
1893
1894 tmp = readl(fep->hwp + FEC_R_CNTRL);
1895 tmp &= ~0x8;
1896 writel(tmp, fep->hwp + FEC_R_CNTRL);
1897
1898 if (ndev->flags & IFF_ALLMULTI) {
1899 /* Catch all multicast addresses, so set the
1900 * filter to all 1's
1901 */
1902 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1903 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1904
1905 return;
1906 }
1907
1908 /* Clear filter and add the addresses in hash register
1909 */
1910 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1911 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1912
1913 netdev_for_each_mc_addr(ha, ndev) {
1914 /* calculate crc32 value of mac address */
1915 crc = 0xffffffff;
1916
1917 for (i = 0; i < ndev->addr_len; i++) {
1918 data = ha->addr[i];
1919 for (bit = 0; bit < 8; bit++, data >>= 1) {
1920 crc = (crc >> 1) ^
1921 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1922 }
1923 }
1924
1925 /* only upper 6 bits (HASH_BITS) are used
1926 * which point to specific bit in he hash registers
1927 */
1928 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1929
1930 if (hash > 31) {
1931 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1932 tmp |= 1 << (hash - 32);
1933 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1934 } else {
1935 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1936 tmp |= 1 << hash;
1937 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1938 }
1939 }
1940 }
1941
1942 /* Set a MAC change in hardware. */
1943 static int
1944 fec_set_mac_address(struct net_device *ndev, void *p)
1945 {
1946 struct fec_enet_private *fep = netdev_priv(ndev);
1947 struct sockaddr *addr = p;
1948
1949 if (addr) {
1950 if (!is_valid_ether_addr(addr->sa_data))
1951 return -EADDRNOTAVAIL;
1952 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1953 }
1954
1955 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1956 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1957 fep->hwp + FEC_ADDR_LOW);
1958 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1959 fep->hwp + FEC_ADDR_HIGH);
1960 return 0;
1961 }
1962
1963 #ifdef CONFIG_NET_POLL_CONTROLLER
1964 /**
1965 * fec_poll_controller - FEC Poll controller function
1966 * @dev: The FEC network adapter
1967 *
1968 * Polled functionality used by netconsole and others in non interrupt mode
1969 *
1970 */
1971 static void fec_poll_controller(struct net_device *dev)
1972 {
1973 int i;
1974 struct fec_enet_private *fep = netdev_priv(dev);
1975
1976 for (i = 0; i < FEC_IRQ_NUM; i++) {
1977 if (fep->irq[i] > 0) {
1978 disable_irq(fep->irq[i]);
1979 fec_enet_interrupt(fep->irq[i], dev);
1980 enable_irq(fep->irq[i]);
1981 }
1982 }
1983 }
1984 #endif
1985
1986 static int fec_set_features(struct net_device *netdev,
1987 netdev_features_t features)
1988 {
1989 struct fec_enet_private *fep = netdev_priv(netdev);
1990 netdev_features_t changed = features ^ netdev->features;
1991
1992 netdev->features = features;
1993
1994 /* Receive checksum has been changed */
1995 if (changed & NETIF_F_RXCSUM) {
1996 if (features & NETIF_F_RXCSUM)
1997 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1998 else
1999 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2000
2001 if (netif_running(netdev)) {
2002 fec_stop(netdev);
2003 fec_restart(netdev, fep->phy_dev->duplex);
2004 netif_wake_queue(netdev);
2005 } else {
2006 fec_restart(netdev, fep->phy_dev->duplex);
2007 }
2008 }
2009
2010 return 0;
2011 }
2012
2013 static const struct net_device_ops fec_netdev_ops = {
2014 .ndo_open = fec_enet_open,
2015 .ndo_stop = fec_enet_close,
2016 .ndo_start_xmit = fec_enet_start_xmit,
2017 .ndo_set_rx_mode = set_multicast_list,
2018 .ndo_change_mtu = eth_change_mtu,
2019 .ndo_validate_addr = eth_validate_addr,
2020 .ndo_tx_timeout = fec_timeout,
2021 .ndo_set_mac_address = fec_set_mac_address,
2022 .ndo_do_ioctl = fec_enet_ioctl,
2023 #ifdef CONFIG_NET_POLL_CONTROLLER
2024 .ndo_poll_controller = fec_poll_controller,
2025 #endif
2026 .ndo_set_features = fec_set_features,
2027 };
2028
2029 /*
2030 * XXX: We need to clean up on failure exits here.
2031 *
2032 */
2033 static int fec_enet_init(struct net_device *ndev)
2034 {
2035 struct fec_enet_private *fep = netdev_priv(ndev);
2036 const struct platform_device_id *id_entry =
2037 platform_get_device_id(fep->pdev);
2038 struct bufdesc *cbd_base;
2039
2040 /* Allocate memory for buffer descriptors. */
2041 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
2042 GFP_KERNEL);
2043 if (!cbd_base)
2044 return -ENOMEM;
2045
2046 memset(cbd_base, 0, PAGE_SIZE);
2047
2048 fep->netdev = ndev;
2049
2050 /* Get the Ethernet address */
2051 fec_get_mac(ndev);
2052 /* make sure MAC we just acquired is programmed into the hw */
2053 fec_set_mac_address(ndev, NULL);
2054
2055 /* init the tx & rx ring size */
2056 fep->tx_ring_size = TX_RING_SIZE;
2057 fep->rx_ring_size = RX_RING_SIZE;
2058
2059 /* Set receive and transmit descriptor base. */
2060 fep->rx_bd_base = cbd_base;
2061 if (fep->bufdesc_ex)
2062 fep->tx_bd_base = (struct bufdesc *)
2063 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2064 else
2065 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2066
2067 /* The FEC Ethernet specific entries in the device structure */
2068 ndev->watchdog_timeo = TX_TIMEOUT;
2069 ndev->netdev_ops = &fec_netdev_ops;
2070 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2071
2072 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2073 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2074
2075 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
2076 /* enable hw VLAN support */
2077 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2078 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2079 }
2080
2081 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2082 /* enable hw accelerator */
2083 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2084 | NETIF_F_RXCSUM);
2085 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2086 | NETIF_F_RXCSUM);
2087 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2088 }
2089
2090 fec_restart(ndev, 0);
2091
2092 return 0;
2093 }
2094
2095 #ifdef CONFIG_OF
2096 static void fec_reset_phy(struct platform_device *pdev)
2097 {
2098 int err, phy_reset;
2099 int msec = 1;
2100 struct device_node *np = pdev->dev.of_node;
2101
2102 if (!np)
2103 return;
2104
2105 of_property_read_u32(np, "phy-reset-duration", &msec);
2106 /* A sane reset duration should not be longer than 1s */
2107 if (msec > 1000)
2108 msec = 1;
2109
2110 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2111 if (!gpio_is_valid(phy_reset))
2112 return;
2113
2114 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2115 GPIOF_OUT_INIT_LOW, "phy-reset");
2116 if (err) {
2117 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2118 return;
2119 }
2120 msleep(msec);
2121 gpio_set_value(phy_reset, 1);
2122 }
2123 #else /* CONFIG_OF */
2124 static void fec_reset_phy(struct platform_device *pdev)
2125 {
2126 /*
2127 * In case of platform probe, the reset has been done
2128 * by machine code.
2129 */
2130 }
2131 #endif /* CONFIG_OF */
2132
2133 static int
2134 fec_probe(struct platform_device *pdev)
2135 {
2136 struct fec_enet_private *fep;
2137 struct fec_platform_data *pdata;
2138 struct net_device *ndev;
2139 int i, irq, ret = 0;
2140 struct resource *r;
2141 const struct of_device_id *of_id;
2142 static int dev_id;
2143
2144 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2145 if (of_id)
2146 pdev->id_entry = of_id->data;
2147
2148 /* Init network device */
2149 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2150 if (!ndev)
2151 return -ENOMEM;
2152
2153 SET_NETDEV_DEV(ndev, &pdev->dev);
2154
2155 /* setup board info structure */
2156 fep = netdev_priv(ndev);
2157
2158 #if !defined(CONFIG_M5272)
2159 /* default enable pause frame auto negotiation */
2160 if (pdev->id_entry &&
2161 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2162 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2163 #endif
2164
2165 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2166 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2167 if (IS_ERR(fep->hwp)) {
2168 ret = PTR_ERR(fep->hwp);
2169 goto failed_ioremap;
2170 }
2171
2172 fep->pdev = pdev;
2173 fep->dev_id = dev_id++;
2174
2175 fep->bufdesc_ex = 0;
2176
2177 platform_set_drvdata(pdev, ndev);
2178
2179 ret = of_get_phy_mode(pdev->dev.of_node);
2180 if (ret < 0) {
2181 pdata = dev_get_platdata(&pdev->dev);
2182 if (pdata)
2183 fep->phy_interface = pdata->phy;
2184 else
2185 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2186 } else {
2187 fep->phy_interface = ret;
2188 }
2189
2190 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2191 if (IS_ERR(fep->clk_ipg)) {
2192 ret = PTR_ERR(fep->clk_ipg);
2193 goto failed_clk;
2194 }
2195
2196 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2197 if (IS_ERR(fep->clk_ahb)) {
2198 ret = PTR_ERR(fep->clk_ahb);
2199 goto failed_clk;
2200 }
2201
2202 /* enet_out is optional, depends on board */
2203 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2204 if (IS_ERR(fep->clk_enet_out))
2205 fep->clk_enet_out = NULL;
2206
2207 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2208 fep->bufdesc_ex =
2209 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2210 if (IS_ERR(fep->clk_ptp)) {
2211 fep->clk_ptp = NULL;
2212 fep->bufdesc_ex = 0;
2213 }
2214
2215 ret = fec_enet_clk_enable(ndev, true);
2216 if (ret)
2217 goto failed_clk;
2218
2219 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2220 if (!IS_ERR(fep->reg_phy)) {
2221 ret = regulator_enable(fep->reg_phy);
2222 if (ret) {
2223 dev_err(&pdev->dev,
2224 "Failed to enable phy regulator: %d\n", ret);
2225 goto failed_regulator;
2226 }
2227 } else {
2228 fep->reg_phy = NULL;
2229 }
2230
2231 fec_reset_phy(pdev);
2232
2233 if (fep->bufdesc_ex)
2234 fec_ptp_init(pdev);
2235
2236 ret = fec_enet_init(ndev);
2237 if (ret)
2238 goto failed_init;
2239
2240 for (i = 0; i < FEC_IRQ_NUM; i++) {
2241 irq = platform_get_irq(pdev, i);
2242 if (irq < 0) {
2243 if (i)
2244 break;
2245 ret = irq;
2246 goto failed_irq;
2247 }
2248 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2249 0, pdev->name, ndev);
2250 if (ret)
2251 goto failed_irq;
2252 }
2253
2254 ret = fec_enet_mii_init(pdev);
2255 if (ret)
2256 goto failed_mii_init;
2257
2258 /* Carrier starts down, phylib will bring it up */
2259 netif_carrier_off(ndev);
2260 fec_enet_clk_enable(ndev, false);
2261
2262 ret = register_netdev(ndev);
2263 if (ret)
2264 goto failed_register;
2265
2266 if (fep->bufdesc_ex && fep->ptp_clock)
2267 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2268
2269 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2270 return 0;
2271
2272 failed_register:
2273 fec_enet_mii_remove(fep);
2274 failed_mii_init:
2275 failed_irq:
2276 failed_init:
2277 if (fep->reg_phy)
2278 regulator_disable(fep->reg_phy);
2279 failed_regulator:
2280 fec_enet_clk_enable(ndev, false);
2281 failed_clk:
2282 failed_ioremap:
2283 free_netdev(ndev);
2284
2285 return ret;
2286 }
2287
2288 static int
2289 fec_drv_remove(struct platform_device *pdev)
2290 {
2291 struct net_device *ndev = platform_get_drvdata(pdev);
2292 struct fec_enet_private *fep = netdev_priv(ndev);
2293
2294 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2295 unregister_netdev(ndev);
2296 fec_enet_mii_remove(fep);
2297 del_timer_sync(&fep->time_keep);
2298 if (fep->reg_phy)
2299 regulator_disable(fep->reg_phy);
2300 if (fep->ptp_clock)
2301 ptp_clock_unregister(fep->ptp_clock);
2302 fec_enet_clk_enable(ndev, false);
2303 free_netdev(ndev);
2304
2305 return 0;
2306 }
2307
2308 #ifdef CONFIG_PM_SLEEP
2309 static int
2310 fec_suspend(struct device *dev)
2311 {
2312 struct net_device *ndev = dev_get_drvdata(dev);
2313 struct fec_enet_private *fep = netdev_priv(ndev);
2314
2315 if (netif_running(ndev)) {
2316 fec_stop(ndev);
2317 netif_device_detach(ndev);
2318 }
2319 fec_enet_clk_enable(ndev, false);
2320
2321 if (fep->reg_phy)
2322 regulator_disable(fep->reg_phy);
2323
2324 return 0;
2325 }
2326
2327 static int
2328 fec_resume(struct device *dev)
2329 {
2330 struct net_device *ndev = dev_get_drvdata(dev);
2331 struct fec_enet_private *fep = netdev_priv(ndev);
2332 int ret;
2333
2334 if (fep->reg_phy) {
2335 ret = regulator_enable(fep->reg_phy);
2336 if (ret)
2337 return ret;
2338 }
2339
2340 ret = fec_enet_clk_enable(ndev, true);
2341 if (ret)
2342 goto failed_clk;
2343
2344 if (netif_running(ndev)) {
2345 fec_restart(ndev, fep->full_duplex);
2346 netif_device_attach(ndev);
2347 }
2348
2349 return 0;
2350
2351 failed_clk:
2352 if (fep->reg_phy)
2353 regulator_disable(fep->reg_phy);
2354 return ret;
2355 }
2356 #endif /* CONFIG_PM_SLEEP */
2357
2358 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2359
2360 static struct platform_driver fec_driver = {
2361 .driver = {
2362 .name = DRIVER_NAME,
2363 .owner = THIS_MODULE,
2364 .pm = &fec_pm_ops,
2365 .of_match_table = fec_dt_ids,
2366 },
2367 .id_table = fec_devtype,
2368 .probe = fec_probe,
2369 .remove = fec_drv_remove,
2370 };
2371
2372 module_platform_driver(fec_driver);
2373
2374 MODULE_ALIAS("platform:"DRIVER_NAME);
2375 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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