2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QE UCC Gigabit Ethernet Driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/stddef.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/mii.h>
32 #include <linux/phy.h>
33 #include <linux/workqueue.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/of_mdio.h>
37 #include <linux/of_net.h>
38 #include <linux/of_platform.h>
40 #include <asm/uaccess.h>
43 #include <asm/immap_qe.h>
46 #include <asm/ucc_fast.h>
47 #include <asm/machdep.h>
53 #define ugeth_printk(level, format, arg...) \
54 printk(level format "\n", ## arg)
56 #define ugeth_dbg(format, arg...) \
57 ugeth_printk(KERN_DEBUG , format , ## arg)
59 #ifdef UGETH_VERBOSE_DEBUG
60 #define ugeth_vdbg ugeth_dbg
62 #define ugeth_vdbg(fmt, args...) do { } while (0)
63 #endif /* UGETH_VERBOSE_DEBUG */
64 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
67 static DEFINE_SPINLOCK(ugeth_lock
);
73 module_param_named(debug
, debug
.msg_enable
, int, 0);
74 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 0xffff=all)");
76 static struct ucc_geth_info ugeth_primary_info
= {
78 .bd_mem_part
= MEM_PART_SYSTEM
,
79 .rtsm
= UCC_FAST_SEND_IDLES_BETWEEN_FRAMES
,
80 .max_rx_buf_length
= 1536,
81 /* adjusted at startup if max-speed 1000 */
82 .urfs
= UCC_GETH_URFS_INIT
,
83 .urfet
= UCC_GETH_URFET_INIT
,
84 .urfset
= UCC_GETH_URFSET_INIT
,
85 .utfs
= UCC_GETH_UTFS_INIT
,
86 .utfet
= UCC_GETH_UTFET_INIT
,
87 .utftt
= UCC_GETH_UTFTT_INIT
,
89 .mode
= UCC_FAST_PROTOCOL_MODE_ETHERNET
,
90 .ttx_trx
= UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL
,
91 .tenc
= UCC_FAST_TX_ENCODING_NRZ
,
92 .renc
= UCC_FAST_RX_ENCODING_NRZ
,
93 .tcrc
= UCC_FAST_16_BIT_CRC
,
94 .synl
= UCC_FAST_SYNC_LEN_NOT_USED
,
98 .extendedFilteringChainPointer
= ((uint32_t) NULL
),
99 .typeorlen
= 3072 /*1536 */ ,
100 .nonBackToBackIfgPart1
= 0x40,
101 .nonBackToBackIfgPart2
= 0x60,
102 .miminumInterFrameGapEnforcement
= 0x50,
103 .backToBackInterFrameGap
= 0x60,
107 .strictpriorityq
= 0xff,
108 .altBebTruncation
= 0xa,
110 .maxRetransmission
= 0xf,
111 .collisionWindow
= 0x37,
112 .receiveFlowControl
= 1,
113 .transmitFlowControl
= 1,
114 .maxGroupAddrInHash
= 4,
115 .maxIndAddrInHash
= 4,
117 .maxFrameLength
= 1518+16, /* Add extra bytes for VLANs etc. */
118 .minFrameLength
= 64,
119 .maxD1Length
= 1520+16, /* Add extra bytes for VLANs etc. */
120 .maxD2Length
= 1520+16, /* Add extra bytes for VLANs etc. */
122 .ecamptr
= ((uint32_t) NULL
),
123 .eventRegMask
= UCCE_OTHER
,
124 .pausePeriod
= 0xf000,
125 .interruptcoalescingmaxvalue
= {1, 1, 1, 1, 1, 1, 1, 1},
146 .numStationAddresses
= UCC_GETH_NUM_OF_STATION_ADDRESSES_1
,
147 .largestexternallookupkeysize
=
148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
,
149 .statisticsMode
= UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
|
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
|
151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
,
152 .vlanOperationTagged
= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
,
153 .vlanOperationNonTagged
= UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
,
154 .rxQoSMode
= UCC_GETH_QOS_MODE_DEFAULT
,
155 .aufc
= UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE
,
156 .padAndCrc
= MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
,
157 .numThreadsTx
= UCC_GETH_NUM_OF_THREADS_1
,
158 .numThreadsRx
= UCC_GETH_NUM_OF_THREADS_1
,
159 .riscTx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
160 .riscRx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
163 static struct ucc_geth_info ugeth_info
[8];
166 static void mem_disp(u8
*addr
, int size
)
169 int size16Aling
= (size
>> 4) << 4;
170 int size4Aling
= (size
>> 2) << 2;
175 for (i
= addr
; (u32
) i
< (u32
) addr
+ size16Aling
; i
+= 16)
176 printk("0x%08x: %08x %08x %08x %08x\r\n",
180 *((u32
*) (i
+ 8)), *((u32
*) (i
+ 12)));
182 printk("0x%08x: ", (u32
) i
);
183 for (; (u32
) i
< (u32
) addr
+ size4Aling
; i
+= 4)
184 printk("%08x ", *((u32
*) (i
)));
185 for (; (u32
) i
< (u32
) addr
+ size
; i
++)
186 printk("%02x", *((i
)));
192 static struct list_head
*dequeue(struct list_head
*lh
)
196 spin_lock_irqsave(&ugeth_lock
, flags
);
197 if (!list_empty(lh
)) {
198 struct list_head
*node
= lh
->next
;
200 spin_unlock_irqrestore(&ugeth_lock
, flags
);
203 spin_unlock_irqrestore(&ugeth_lock
, flags
);
208 static struct sk_buff
*get_new_skb(struct ucc_geth_private
*ugeth
,
213 skb
= netdev_alloc_skb(ugeth
->ndev
,
214 ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
215 UCC_GETH_RX_DATA_BUF_ALIGNMENT
);
219 /* We need the data buffer to be aligned properly. We will reserve
220 * as many bytes as needed to align the data properly
223 UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
224 (((unsigned)skb
->data
) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
227 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
,
228 dma_map_single(ugeth
->dev
,
230 ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
231 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
234 out_be32((u32 __iomem
*)bd
,
235 (R_E
| R_I
| (in_be32((u32 __iomem
*)bd
) & R_W
)));
240 static int rx_bd_buffer_set(struct ucc_geth_private
*ugeth
, u8 rxQ
)
247 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
251 bd_status
= in_be32((u32 __iomem
*)bd
);
252 skb
= get_new_skb(ugeth
, bd
);
254 if (!skb
) /* If can not allocate data buffer,
255 abort. Cleanup will be elsewhere */
258 ugeth
->rx_skbuff
[rxQ
][i
] = skb
;
260 /* advance the BD pointer */
261 bd
+= sizeof(struct qe_bd
);
263 } while (!(bd_status
& R_W
));
268 static int fill_init_enet_entries(struct ucc_geth_private
*ugeth
,
272 u32 thread_alignment
,
274 int skip_page_for_first_entry
)
276 u32 init_enet_offset
;
280 for (i
= 0; i
< num_entries
; i
++) {
281 if ((snum
= qe_get_snum()) < 0) {
282 if (netif_msg_ifup(ugeth
))
283 pr_err("Can not get SNUM\n");
286 if ((i
== 0) && skip_page_for_first_entry
)
287 /* First entry of Rx does not have page */
288 init_enet_offset
= 0;
291 qe_muram_alloc(thread_size
, thread_alignment
);
292 if (IS_ERR_VALUE(init_enet_offset
)) {
293 if (netif_msg_ifup(ugeth
))
294 pr_err("Can not allocate DPRAM memory\n");
295 qe_put_snum((u8
) snum
);
300 ((u8
) snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) | init_enet_offset
307 static int return_init_enet_entries(struct ucc_geth_private
*ugeth
,
311 int skip_page_for_first_entry
)
313 u32 init_enet_offset
;
317 for (i
= 0; i
< num_entries
; i
++) {
320 /* Check that this entry was actually valid --
321 needed in case failed in allocations */
322 if ((val
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
324 (u32
) (val
& ENET_INIT_PARAM_SNUM_MASK
) >>
325 ENET_INIT_PARAM_SNUM_SHIFT
;
326 qe_put_snum((u8
) snum
);
327 if (!((i
== 0) && skip_page_for_first_entry
)) {
328 /* First entry of Rx does not have page */
330 (val
& ENET_INIT_PARAM_PTR_MASK
);
331 qe_muram_free(init_enet_offset
);
341 static int dump_init_enet_entries(struct ucc_geth_private
*ugeth
,
342 u32 __iomem
*p_start
,
346 int skip_page_for_first_entry
)
348 u32 init_enet_offset
;
352 for (i
= 0; i
< num_entries
; i
++) {
353 u32 val
= in_be32(p_start
);
355 /* Check that this entry was actually valid --
356 needed in case failed in allocations */
357 if ((val
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
359 (u32
) (val
& ENET_INIT_PARAM_SNUM_MASK
) >>
360 ENET_INIT_PARAM_SNUM_SHIFT
;
361 qe_put_snum((u8
) snum
);
362 if (!((i
== 0) && skip_page_for_first_entry
)) {
363 /* First entry of Rx does not have page */
366 ENET_INIT_PARAM_PTR_MASK
);
367 pr_info("Init enet entry %d:\n", i
);
368 pr_info("Base address: 0x%08x\n",
369 (u32
)qe_muram_addr(init_enet_offset
));
370 mem_disp(qe_muram_addr(init_enet_offset
),
381 static void put_enet_addr_container(struct enet_addr_container
*enet_addr_cont
)
383 kfree(enet_addr_cont
);
386 static void set_mac_addr(__be16 __iomem
*reg
, u8
*mac
)
388 out_be16(®
[0], ((u16
)mac
[5] << 8) | mac
[4]);
389 out_be16(®
[1], ((u16
)mac
[3] << 8) | mac
[2]);
390 out_be16(®
[2], ((u16
)mac
[1] << 8) | mac
[0]);
393 static int hw_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
, u8 paddr_num
)
395 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
397 if (paddr_num
>= NUM_OF_PADDRS
) {
398 pr_warn("%s: Invalid paddr_num: %u\n", __func__
, paddr_num
);
403 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->p_rx_glbl_pram
->
406 /* Writing address ff.ff.ff.ff.ff.ff disables address
407 recognition for this register */
408 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].h
, 0xffff);
409 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].m
, 0xffff);
410 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].l
, 0xffff);
415 static void hw_add_addr_in_hash(struct ucc_geth_private
*ugeth
,
418 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
422 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->p_rx_glbl_pram
->
426 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
428 /* Ethernet frames are defined in Little Endian mode,
429 therefore to insert */
430 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
432 set_mac_addr(&p_82xx_addr_filt
->taddr
.h
, p_enet_addr
);
434 qe_issue_cmd(QE_SET_GROUP_ADDRESS
, cecr_subblock
,
435 QE_CR_PROTOCOL_ETHERNET
, 0);
439 static void get_statistics(struct ucc_geth_private
*ugeth
,
440 struct ucc_geth_tx_firmware_statistics
*
441 tx_firmware_statistics
,
442 struct ucc_geth_rx_firmware_statistics
*
443 rx_firmware_statistics
,
444 struct ucc_geth_hardware_statistics
*hardware_statistics
)
446 struct ucc_fast __iomem
*uf_regs
;
447 struct ucc_geth __iomem
*ug_regs
;
448 struct ucc_geth_tx_firmware_statistics_pram
*p_tx_fw_statistics_pram
;
449 struct ucc_geth_rx_firmware_statistics_pram
*p_rx_fw_statistics_pram
;
451 ug_regs
= ugeth
->ug_regs
;
452 uf_regs
= (struct ucc_fast __iomem
*) ug_regs
;
453 p_tx_fw_statistics_pram
= ugeth
->p_tx_fw_statistics_pram
;
454 p_rx_fw_statistics_pram
= ugeth
->p_rx_fw_statistics_pram
;
456 /* Tx firmware only if user handed pointer and driver actually
457 gathers Tx firmware statistics */
458 if (tx_firmware_statistics
&& p_tx_fw_statistics_pram
) {
459 tx_firmware_statistics
->sicoltx
=
460 in_be32(&p_tx_fw_statistics_pram
->sicoltx
);
461 tx_firmware_statistics
->mulcoltx
=
462 in_be32(&p_tx_fw_statistics_pram
->mulcoltx
);
463 tx_firmware_statistics
->latecoltxfr
=
464 in_be32(&p_tx_fw_statistics_pram
->latecoltxfr
);
465 tx_firmware_statistics
->frabortduecol
=
466 in_be32(&p_tx_fw_statistics_pram
->frabortduecol
);
467 tx_firmware_statistics
->frlostinmactxer
=
468 in_be32(&p_tx_fw_statistics_pram
->frlostinmactxer
);
469 tx_firmware_statistics
->carriersenseertx
=
470 in_be32(&p_tx_fw_statistics_pram
->carriersenseertx
);
471 tx_firmware_statistics
->frtxok
=
472 in_be32(&p_tx_fw_statistics_pram
->frtxok
);
473 tx_firmware_statistics
->txfrexcessivedefer
=
474 in_be32(&p_tx_fw_statistics_pram
->txfrexcessivedefer
);
475 tx_firmware_statistics
->txpkts256
=
476 in_be32(&p_tx_fw_statistics_pram
->txpkts256
);
477 tx_firmware_statistics
->txpkts512
=
478 in_be32(&p_tx_fw_statistics_pram
->txpkts512
);
479 tx_firmware_statistics
->txpkts1024
=
480 in_be32(&p_tx_fw_statistics_pram
->txpkts1024
);
481 tx_firmware_statistics
->txpktsjumbo
=
482 in_be32(&p_tx_fw_statistics_pram
->txpktsjumbo
);
485 /* Rx firmware only if user handed pointer and driver actually
486 * gathers Rx firmware statistics */
487 if (rx_firmware_statistics
&& p_rx_fw_statistics_pram
) {
489 rx_firmware_statistics
->frrxfcser
=
490 in_be32(&p_rx_fw_statistics_pram
->frrxfcser
);
491 rx_firmware_statistics
->fraligner
=
492 in_be32(&p_rx_fw_statistics_pram
->fraligner
);
493 rx_firmware_statistics
->inrangelenrxer
=
494 in_be32(&p_rx_fw_statistics_pram
->inrangelenrxer
);
495 rx_firmware_statistics
->outrangelenrxer
=
496 in_be32(&p_rx_fw_statistics_pram
->outrangelenrxer
);
497 rx_firmware_statistics
->frtoolong
=
498 in_be32(&p_rx_fw_statistics_pram
->frtoolong
);
499 rx_firmware_statistics
->runt
=
500 in_be32(&p_rx_fw_statistics_pram
->runt
);
501 rx_firmware_statistics
->verylongevent
=
502 in_be32(&p_rx_fw_statistics_pram
->verylongevent
);
503 rx_firmware_statistics
->symbolerror
=
504 in_be32(&p_rx_fw_statistics_pram
->symbolerror
);
505 rx_firmware_statistics
->dropbsy
=
506 in_be32(&p_rx_fw_statistics_pram
->dropbsy
);
507 for (i
= 0; i
< 0x8; i
++)
508 rx_firmware_statistics
->res0
[i
] =
509 p_rx_fw_statistics_pram
->res0
[i
];
510 rx_firmware_statistics
->mismatchdrop
=
511 in_be32(&p_rx_fw_statistics_pram
->mismatchdrop
);
512 rx_firmware_statistics
->underpkts
=
513 in_be32(&p_rx_fw_statistics_pram
->underpkts
);
514 rx_firmware_statistics
->pkts256
=
515 in_be32(&p_rx_fw_statistics_pram
->pkts256
);
516 rx_firmware_statistics
->pkts512
=
517 in_be32(&p_rx_fw_statistics_pram
->pkts512
);
518 rx_firmware_statistics
->pkts1024
=
519 in_be32(&p_rx_fw_statistics_pram
->pkts1024
);
520 rx_firmware_statistics
->pktsjumbo
=
521 in_be32(&p_rx_fw_statistics_pram
->pktsjumbo
);
522 rx_firmware_statistics
->frlossinmacer
=
523 in_be32(&p_rx_fw_statistics_pram
->frlossinmacer
);
524 rx_firmware_statistics
->pausefr
=
525 in_be32(&p_rx_fw_statistics_pram
->pausefr
);
526 for (i
= 0; i
< 0x4; i
++)
527 rx_firmware_statistics
->res1
[i
] =
528 p_rx_fw_statistics_pram
->res1
[i
];
529 rx_firmware_statistics
->removevlan
=
530 in_be32(&p_rx_fw_statistics_pram
->removevlan
);
531 rx_firmware_statistics
->replacevlan
=
532 in_be32(&p_rx_fw_statistics_pram
->replacevlan
);
533 rx_firmware_statistics
->insertvlan
=
534 in_be32(&p_rx_fw_statistics_pram
->insertvlan
);
537 /* Hardware only if user handed pointer and driver actually
538 gathers hardware statistics */
539 if (hardware_statistics
&&
540 (in_be32(&uf_regs
->upsmr
) & UCC_GETH_UPSMR_HSE
)) {
541 hardware_statistics
->tx64
= in_be32(&ug_regs
->tx64
);
542 hardware_statistics
->tx127
= in_be32(&ug_regs
->tx127
);
543 hardware_statistics
->tx255
= in_be32(&ug_regs
->tx255
);
544 hardware_statistics
->rx64
= in_be32(&ug_regs
->rx64
);
545 hardware_statistics
->rx127
= in_be32(&ug_regs
->rx127
);
546 hardware_statistics
->rx255
= in_be32(&ug_regs
->rx255
);
547 hardware_statistics
->txok
= in_be32(&ug_regs
->txok
);
548 hardware_statistics
->txcf
= in_be16(&ug_regs
->txcf
);
549 hardware_statistics
->tmca
= in_be32(&ug_regs
->tmca
);
550 hardware_statistics
->tbca
= in_be32(&ug_regs
->tbca
);
551 hardware_statistics
->rxfok
= in_be32(&ug_regs
->rxfok
);
552 hardware_statistics
->rxbok
= in_be32(&ug_regs
->rxbok
);
553 hardware_statistics
->rbyt
= in_be32(&ug_regs
->rbyt
);
554 hardware_statistics
->rmca
= in_be32(&ug_regs
->rmca
);
555 hardware_statistics
->rbca
= in_be32(&ug_regs
->rbca
);
559 static void dump_bds(struct ucc_geth_private
*ugeth
)
564 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
565 if (ugeth
->p_tx_bd_ring
[i
]) {
567 (ugeth
->ug_info
->bdRingLenTx
[i
] *
568 sizeof(struct qe_bd
));
569 pr_info("TX BDs[%d]\n", i
);
570 mem_disp(ugeth
->p_tx_bd_ring
[i
], length
);
573 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
574 if (ugeth
->p_rx_bd_ring
[i
]) {
576 (ugeth
->ug_info
->bdRingLenRx
[i
] *
577 sizeof(struct qe_bd
));
578 pr_info("RX BDs[%d]\n", i
);
579 mem_disp(ugeth
->p_rx_bd_ring
[i
], length
);
584 static void dump_regs(struct ucc_geth_private
*ugeth
)
588 pr_info("UCC%d Geth registers:\n", ugeth
->ug_info
->uf_info
.ucc_num
+ 1);
589 pr_info("Base address: 0x%08x\n", (u32
)ugeth
->ug_regs
);
591 pr_info("maccfg1 : addr - 0x%08x, val - 0x%08x\n",
592 (u32
)&ugeth
->ug_regs
->maccfg1
,
593 in_be32(&ugeth
->ug_regs
->maccfg1
));
594 pr_info("maccfg2 : addr - 0x%08x, val - 0x%08x\n",
595 (u32
)&ugeth
->ug_regs
->maccfg2
,
596 in_be32(&ugeth
->ug_regs
->maccfg2
));
597 pr_info("ipgifg : addr - 0x%08x, val - 0x%08x\n",
598 (u32
)&ugeth
->ug_regs
->ipgifg
,
599 in_be32(&ugeth
->ug_regs
->ipgifg
));
600 pr_info("hafdup : addr - 0x%08x, val - 0x%08x\n",
601 (u32
)&ugeth
->ug_regs
->hafdup
,
602 in_be32(&ugeth
->ug_regs
->hafdup
));
603 pr_info("ifctl : addr - 0x%08x, val - 0x%08x\n",
604 (u32
)&ugeth
->ug_regs
->ifctl
,
605 in_be32(&ugeth
->ug_regs
->ifctl
));
606 pr_info("ifstat : addr - 0x%08x, val - 0x%08x\n",
607 (u32
)&ugeth
->ug_regs
->ifstat
,
608 in_be32(&ugeth
->ug_regs
->ifstat
));
609 pr_info("macstnaddr1: addr - 0x%08x, val - 0x%08x\n",
610 (u32
)&ugeth
->ug_regs
->macstnaddr1
,
611 in_be32(&ugeth
->ug_regs
->macstnaddr1
));
612 pr_info("macstnaddr2: addr - 0x%08x, val - 0x%08x\n",
613 (u32
)&ugeth
->ug_regs
->macstnaddr2
,
614 in_be32(&ugeth
->ug_regs
->macstnaddr2
));
615 pr_info("uempr : addr - 0x%08x, val - 0x%08x\n",
616 (u32
)&ugeth
->ug_regs
->uempr
,
617 in_be32(&ugeth
->ug_regs
->uempr
));
618 pr_info("utbipar : addr - 0x%08x, val - 0x%08x\n",
619 (u32
)&ugeth
->ug_regs
->utbipar
,
620 in_be32(&ugeth
->ug_regs
->utbipar
));
621 pr_info("uescr : addr - 0x%08x, val - 0x%04x\n",
622 (u32
)&ugeth
->ug_regs
->uescr
,
623 in_be16(&ugeth
->ug_regs
->uescr
));
624 pr_info("tx64 : addr - 0x%08x, val - 0x%08x\n",
625 (u32
)&ugeth
->ug_regs
->tx64
,
626 in_be32(&ugeth
->ug_regs
->tx64
));
627 pr_info("tx127 : addr - 0x%08x, val - 0x%08x\n",
628 (u32
)&ugeth
->ug_regs
->tx127
,
629 in_be32(&ugeth
->ug_regs
->tx127
));
630 pr_info("tx255 : addr - 0x%08x, val - 0x%08x\n",
631 (u32
)&ugeth
->ug_regs
->tx255
,
632 in_be32(&ugeth
->ug_regs
->tx255
));
633 pr_info("rx64 : addr - 0x%08x, val - 0x%08x\n",
634 (u32
)&ugeth
->ug_regs
->rx64
,
635 in_be32(&ugeth
->ug_regs
->rx64
));
636 pr_info("rx127 : addr - 0x%08x, val - 0x%08x\n",
637 (u32
)&ugeth
->ug_regs
->rx127
,
638 in_be32(&ugeth
->ug_regs
->rx127
));
639 pr_info("rx255 : addr - 0x%08x, val - 0x%08x\n",
640 (u32
)&ugeth
->ug_regs
->rx255
,
641 in_be32(&ugeth
->ug_regs
->rx255
));
642 pr_info("txok : addr - 0x%08x, val - 0x%08x\n",
643 (u32
)&ugeth
->ug_regs
->txok
,
644 in_be32(&ugeth
->ug_regs
->txok
));
645 pr_info("txcf : addr - 0x%08x, val - 0x%04x\n",
646 (u32
)&ugeth
->ug_regs
->txcf
,
647 in_be16(&ugeth
->ug_regs
->txcf
));
648 pr_info("tmca : addr - 0x%08x, val - 0x%08x\n",
649 (u32
)&ugeth
->ug_regs
->tmca
,
650 in_be32(&ugeth
->ug_regs
->tmca
));
651 pr_info("tbca : addr - 0x%08x, val - 0x%08x\n",
652 (u32
)&ugeth
->ug_regs
->tbca
,
653 in_be32(&ugeth
->ug_regs
->tbca
));
654 pr_info("rxfok : addr - 0x%08x, val - 0x%08x\n",
655 (u32
)&ugeth
->ug_regs
->rxfok
,
656 in_be32(&ugeth
->ug_regs
->rxfok
));
657 pr_info("rxbok : addr - 0x%08x, val - 0x%08x\n",
658 (u32
)&ugeth
->ug_regs
->rxbok
,
659 in_be32(&ugeth
->ug_regs
->rxbok
));
660 pr_info("rbyt : addr - 0x%08x, val - 0x%08x\n",
661 (u32
)&ugeth
->ug_regs
->rbyt
,
662 in_be32(&ugeth
->ug_regs
->rbyt
));
663 pr_info("rmca : addr - 0x%08x, val - 0x%08x\n",
664 (u32
)&ugeth
->ug_regs
->rmca
,
665 in_be32(&ugeth
->ug_regs
->rmca
));
666 pr_info("rbca : addr - 0x%08x, val - 0x%08x\n",
667 (u32
)&ugeth
->ug_regs
->rbca
,
668 in_be32(&ugeth
->ug_regs
->rbca
));
669 pr_info("scar : addr - 0x%08x, val - 0x%08x\n",
670 (u32
)&ugeth
->ug_regs
->scar
,
671 in_be32(&ugeth
->ug_regs
->scar
));
672 pr_info("scam : addr - 0x%08x, val - 0x%08x\n",
673 (u32
)&ugeth
->ug_regs
->scam
,
674 in_be32(&ugeth
->ug_regs
->scam
));
676 if (ugeth
->p_thread_data_tx
) {
677 int numThreadsTxNumerical
;
678 switch (ugeth
->ug_info
->numThreadsTx
) {
679 case UCC_GETH_NUM_OF_THREADS_1
:
680 numThreadsTxNumerical
= 1;
682 case UCC_GETH_NUM_OF_THREADS_2
:
683 numThreadsTxNumerical
= 2;
685 case UCC_GETH_NUM_OF_THREADS_4
:
686 numThreadsTxNumerical
= 4;
688 case UCC_GETH_NUM_OF_THREADS_6
:
689 numThreadsTxNumerical
= 6;
691 case UCC_GETH_NUM_OF_THREADS_8
:
692 numThreadsTxNumerical
= 8;
695 numThreadsTxNumerical
= 0;
699 pr_info("Thread data TXs:\n");
700 pr_info("Base address: 0x%08x\n",
701 (u32
)ugeth
->p_thread_data_tx
);
702 for (i
= 0; i
< numThreadsTxNumerical
; i
++) {
703 pr_info("Thread data TX[%d]:\n", i
);
704 pr_info("Base address: 0x%08x\n",
705 (u32
)&ugeth
->p_thread_data_tx
[i
]);
706 mem_disp((u8
*) & ugeth
->p_thread_data_tx
[i
],
707 sizeof(struct ucc_geth_thread_data_tx
));
710 if (ugeth
->p_thread_data_rx
) {
711 int numThreadsRxNumerical
;
712 switch (ugeth
->ug_info
->numThreadsRx
) {
713 case UCC_GETH_NUM_OF_THREADS_1
:
714 numThreadsRxNumerical
= 1;
716 case UCC_GETH_NUM_OF_THREADS_2
:
717 numThreadsRxNumerical
= 2;
719 case UCC_GETH_NUM_OF_THREADS_4
:
720 numThreadsRxNumerical
= 4;
722 case UCC_GETH_NUM_OF_THREADS_6
:
723 numThreadsRxNumerical
= 6;
725 case UCC_GETH_NUM_OF_THREADS_8
:
726 numThreadsRxNumerical
= 8;
729 numThreadsRxNumerical
= 0;
733 pr_info("Thread data RX:\n");
734 pr_info("Base address: 0x%08x\n",
735 (u32
)ugeth
->p_thread_data_rx
);
736 for (i
= 0; i
< numThreadsRxNumerical
; i
++) {
737 pr_info("Thread data RX[%d]:\n", i
);
738 pr_info("Base address: 0x%08x\n",
739 (u32
)&ugeth
->p_thread_data_rx
[i
]);
740 mem_disp((u8
*) & ugeth
->p_thread_data_rx
[i
],
741 sizeof(struct ucc_geth_thread_data_rx
));
744 if (ugeth
->p_exf_glbl_param
) {
745 pr_info("EXF global param:\n");
746 pr_info("Base address: 0x%08x\n",
747 (u32
)ugeth
->p_exf_glbl_param
);
748 mem_disp((u8
*) ugeth
->p_exf_glbl_param
,
749 sizeof(*ugeth
->p_exf_glbl_param
));
751 if (ugeth
->p_tx_glbl_pram
) {
752 pr_info("TX global param:\n");
753 pr_info("Base address: 0x%08x\n", (u32
)ugeth
->p_tx_glbl_pram
);
754 pr_info("temoder : addr - 0x%08x, val - 0x%04x\n",
755 (u32
)&ugeth
->p_tx_glbl_pram
->temoder
,
756 in_be16(&ugeth
->p_tx_glbl_pram
->temoder
));
757 pr_info("sqptr : addr - 0x%08x, val - 0x%08x\n",
758 (u32
)&ugeth
->p_tx_glbl_pram
->sqptr
,
759 in_be32(&ugeth
->p_tx_glbl_pram
->sqptr
));
760 pr_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x\n",
761 (u32
)&ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
762 in_be32(&ugeth
->p_tx_glbl_pram
->schedulerbasepointer
));
763 pr_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x\n",
764 (u32
)&ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
765 in_be32(&ugeth
->p_tx_glbl_pram
->txrmonbaseptr
));
766 pr_info("tstate : addr - 0x%08x, val - 0x%08x\n",
767 (u32
)&ugeth
->p_tx_glbl_pram
->tstate
,
768 in_be32(&ugeth
->p_tx_glbl_pram
->tstate
));
769 pr_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x\n",
770 (u32
)&ugeth
->p_tx_glbl_pram
->iphoffset
[0],
771 ugeth
->p_tx_glbl_pram
->iphoffset
[0]);
772 pr_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x\n",
773 (u32
)&ugeth
->p_tx_glbl_pram
->iphoffset
[1],
774 ugeth
->p_tx_glbl_pram
->iphoffset
[1]);
775 pr_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x\n",
776 (u32
)&ugeth
->p_tx_glbl_pram
->iphoffset
[2],
777 ugeth
->p_tx_glbl_pram
->iphoffset
[2]);
778 pr_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x\n",
779 (u32
)&ugeth
->p_tx_glbl_pram
->iphoffset
[3],
780 ugeth
->p_tx_glbl_pram
->iphoffset
[3]);
781 pr_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x\n",
782 (u32
)&ugeth
->p_tx_glbl_pram
->iphoffset
[4],
783 ugeth
->p_tx_glbl_pram
->iphoffset
[4]);
784 pr_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x\n",
785 (u32
)&ugeth
->p_tx_glbl_pram
->iphoffset
[5],
786 ugeth
->p_tx_glbl_pram
->iphoffset
[5]);
787 pr_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x\n",
788 (u32
)&ugeth
->p_tx_glbl_pram
->iphoffset
[6],
789 ugeth
->p_tx_glbl_pram
->iphoffset
[6]);
790 pr_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x\n",
791 (u32
)&ugeth
->p_tx_glbl_pram
->iphoffset
[7],
792 ugeth
->p_tx_glbl_pram
->iphoffset
[7]);
793 pr_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x\n",
794 (u32
)&ugeth
->p_tx_glbl_pram
->vtagtable
[0],
795 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[0]));
796 pr_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x\n",
797 (u32
)&ugeth
->p_tx_glbl_pram
->vtagtable
[1],
798 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[1]));
799 pr_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x\n",
800 (u32
)&ugeth
->p_tx_glbl_pram
->vtagtable
[2],
801 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[2]));
802 pr_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x\n",
803 (u32
)&ugeth
->p_tx_glbl_pram
->vtagtable
[3],
804 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[3]));
805 pr_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x\n",
806 (u32
)&ugeth
->p_tx_glbl_pram
->vtagtable
[4],
807 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[4]));
808 pr_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x\n",
809 (u32
)&ugeth
->p_tx_glbl_pram
->vtagtable
[5],
810 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[5]));
811 pr_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x\n",
812 (u32
)&ugeth
->p_tx_glbl_pram
->vtagtable
[6],
813 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[6]));
814 pr_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x\n",
815 (u32
)&ugeth
->p_tx_glbl_pram
->vtagtable
[7],
816 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[7]));
817 pr_info("tqptr : addr - 0x%08x, val - 0x%08x\n",
818 (u32
)&ugeth
->p_tx_glbl_pram
->tqptr
,
819 in_be32(&ugeth
->p_tx_glbl_pram
->tqptr
));
821 if (ugeth
->p_rx_glbl_pram
) {
822 pr_info("RX global param:\n");
823 pr_info("Base address: 0x%08x\n", (u32
)ugeth
->p_rx_glbl_pram
);
824 pr_info("remoder : addr - 0x%08x, val - 0x%08x\n",
825 (u32
)&ugeth
->p_rx_glbl_pram
->remoder
,
826 in_be32(&ugeth
->p_rx_glbl_pram
->remoder
));
827 pr_info("rqptr : addr - 0x%08x, val - 0x%08x\n",
828 (u32
)&ugeth
->p_rx_glbl_pram
->rqptr
,
829 in_be32(&ugeth
->p_rx_glbl_pram
->rqptr
));
830 pr_info("typeorlen : addr - 0x%08x, val - 0x%04x\n",
831 (u32
)&ugeth
->p_rx_glbl_pram
->typeorlen
,
832 in_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
));
833 pr_info("rxgstpack : addr - 0x%08x, val - 0x%02x\n",
834 (u32
)&ugeth
->p_rx_glbl_pram
->rxgstpack
,
835 ugeth
->p_rx_glbl_pram
->rxgstpack
);
836 pr_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x\n",
837 (u32
)&ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
838 in_be32(&ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
));
839 pr_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x\n",
840 (u32
)&ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
841 in_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
));
842 pr_info("rstate : addr - 0x%08x, val - 0x%02x\n",
843 (u32
)&ugeth
->p_rx_glbl_pram
->rstate
,
844 ugeth
->p_rx_glbl_pram
->rstate
);
845 pr_info("mrblr : addr - 0x%08x, val - 0x%04x\n",
846 (u32
)&ugeth
->p_rx_glbl_pram
->mrblr
,
847 in_be16(&ugeth
->p_rx_glbl_pram
->mrblr
));
848 pr_info("rbdqptr : addr - 0x%08x, val - 0x%08x\n",
849 (u32
)&ugeth
->p_rx_glbl_pram
->rbdqptr
,
850 in_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
));
851 pr_info("mflr : addr - 0x%08x, val - 0x%04x\n",
852 (u32
)&ugeth
->p_rx_glbl_pram
->mflr
,
853 in_be16(&ugeth
->p_rx_glbl_pram
->mflr
));
854 pr_info("minflr : addr - 0x%08x, val - 0x%04x\n",
855 (u32
)&ugeth
->p_rx_glbl_pram
->minflr
,
856 in_be16(&ugeth
->p_rx_glbl_pram
->minflr
));
857 pr_info("maxd1 : addr - 0x%08x, val - 0x%04x\n",
858 (u32
)&ugeth
->p_rx_glbl_pram
->maxd1
,
859 in_be16(&ugeth
->p_rx_glbl_pram
->maxd1
));
860 pr_info("maxd2 : addr - 0x%08x, val - 0x%04x\n",
861 (u32
)&ugeth
->p_rx_glbl_pram
->maxd2
,
862 in_be16(&ugeth
->p_rx_glbl_pram
->maxd2
));
863 pr_info("ecamptr : addr - 0x%08x, val - 0x%08x\n",
864 (u32
)&ugeth
->p_rx_glbl_pram
->ecamptr
,
865 in_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
));
866 pr_info("l2qt : addr - 0x%08x, val - 0x%08x\n",
867 (u32
)&ugeth
->p_rx_glbl_pram
->l2qt
,
868 in_be32(&ugeth
->p_rx_glbl_pram
->l2qt
));
869 pr_info("l3qt[0] : addr - 0x%08x, val - 0x%08x\n",
870 (u32
)&ugeth
->p_rx_glbl_pram
->l3qt
[0],
871 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[0]));
872 pr_info("l3qt[1] : addr - 0x%08x, val - 0x%08x\n",
873 (u32
)&ugeth
->p_rx_glbl_pram
->l3qt
[1],
874 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[1]));
875 pr_info("l3qt[2] : addr - 0x%08x, val - 0x%08x\n",
876 (u32
)&ugeth
->p_rx_glbl_pram
->l3qt
[2],
877 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[2]));
878 pr_info("l3qt[3] : addr - 0x%08x, val - 0x%08x\n",
879 (u32
)&ugeth
->p_rx_glbl_pram
->l3qt
[3],
880 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[3]));
881 pr_info("l3qt[4] : addr - 0x%08x, val - 0x%08x\n",
882 (u32
)&ugeth
->p_rx_glbl_pram
->l3qt
[4],
883 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[4]));
884 pr_info("l3qt[5] : addr - 0x%08x, val - 0x%08x\n",
885 (u32
)&ugeth
->p_rx_glbl_pram
->l3qt
[5],
886 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[5]));
887 pr_info("l3qt[6] : addr - 0x%08x, val - 0x%08x\n",
888 (u32
)&ugeth
->p_rx_glbl_pram
->l3qt
[6],
889 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[6]));
890 pr_info("l3qt[7] : addr - 0x%08x, val - 0x%08x\n",
891 (u32
)&ugeth
->p_rx_glbl_pram
->l3qt
[7],
892 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[7]));
893 pr_info("vlantype : addr - 0x%08x, val - 0x%04x\n",
894 (u32
)&ugeth
->p_rx_glbl_pram
->vlantype
,
895 in_be16(&ugeth
->p_rx_glbl_pram
->vlantype
));
896 pr_info("vlantci : addr - 0x%08x, val - 0x%04x\n",
897 (u32
)&ugeth
->p_rx_glbl_pram
->vlantci
,
898 in_be16(&ugeth
->p_rx_glbl_pram
->vlantci
));
899 for (i
= 0; i
< 64; i
++)
900 pr_info("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x\n",
902 (u32
)&ugeth
->p_rx_glbl_pram
->addressfiltering
[i
],
903 ugeth
->p_rx_glbl_pram
->addressfiltering
[i
]);
904 pr_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x\n",
905 (u32
)&ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
906 in_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
));
908 if (ugeth
->p_send_q_mem_reg
) {
909 pr_info("Send Q memory registers:\n");
910 pr_info("Base address: 0x%08x\n", (u32
)ugeth
->p_send_q_mem_reg
);
911 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
912 pr_info("SQQD[%d]:\n", i
);
913 pr_info("Base address: 0x%08x\n",
914 (u32
)&ugeth
->p_send_q_mem_reg
->sqqd
[i
]);
915 mem_disp((u8
*) & ugeth
->p_send_q_mem_reg
->sqqd
[i
],
916 sizeof(struct ucc_geth_send_queue_qd
));
919 if (ugeth
->p_scheduler
) {
920 pr_info("Scheduler:\n");
921 pr_info("Base address: 0x%08x\n", (u32
)ugeth
->p_scheduler
);
922 mem_disp((u8
*) ugeth
->p_scheduler
,
923 sizeof(*ugeth
->p_scheduler
));
925 if (ugeth
->p_tx_fw_statistics_pram
) {
926 pr_info("TX FW statistics pram:\n");
927 pr_info("Base address: 0x%08x\n",
928 (u32
)ugeth
->p_tx_fw_statistics_pram
);
929 mem_disp((u8
*) ugeth
->p_tx_fw_statistics_pram
,
930 sizeof(*ugeth
->p_tx_fw_statistics_pram
));
932 if (ugeth
->p_rx_fw_statistics_pram
) {
933 pr_info("RX FW statistics pram:\n");
934 pr_info("Base address: 0x%08x\n",
935 (u32
)ugeth
->p_rx_fw_statistics_pram
);
936 mem_disp((u8
*) ugeth
->p_rx_fw_statistics_pram
,
937 sizeof(*ugeth
->p_rx_fw_statistics_pram
));
939 if (ugeth
->p_rx_irq_coalescing_tbl
) {
940 pr_info("RX IRQ coalescing tables:\n");
941 pr_info("Base address: 0x%08x\n",
942 (u32
)ugeth
->p_rx_irq_coalescing_tbl
);
943 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
944 pr_info("RX IRQ coalescing table entry[%d]:\n", i
);
945 pr_info("Base address: 0x%08x\n",
946 (u32
)&ugeth
->p_rx_irq_coalescing_tbl
->
948 pr_info("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x\n",
949 (u32
)&ugeth
->p_rx_irq_coalescing_tbl
->
950 coalescingentry
[i
].interruptcoalescingmaxvalue
,
951 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
953 interruptcoalescingmaxvalue
));
954 pr_info("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x\n",
955 (u32
)&ugeth
->p_rx_irq_coalescing_tbl
->
956 coalescingentry
[i
].interruptcoalescingcounter
,
957 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
959 interruptcoalescingcounter
));
962 if (ugeth
->p_rx_bd_qs_tbl
) {
963 pr_info("RX BD QS tables:\n");
964 pr_info("Base address: 0x%08x\n", (u32
)ugeth
->p_rx_bd_qs_tbl
);
965 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
966 pr_info("RX BD QS table[%d]:\n", i
);
967 pr_info("Base address: 0x%08x\n",
968 (u32
)&ugeth
->p_rx_bd_qs_tbl
[i
]);
969 pr_info("bdbaseptr : addr - 0x%08x, val - 0x%08x\n",
970 (u32
)&ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
,
971 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
));
972 pr_info("bdptr : addr - 0x%08x, val - 0x%08x\n",
973 (u32
)&ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
,
974 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
));
975 pr_info("externalbdbaseptr: addr - 0x%08x, val - 0x%08x\n",
976 (u32
)&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
977 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].
979 pr_info("externalbdptr : addr - 0x%08x, val - 0x%08x\n",
980 (u32
)&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
,
981 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
));
982 pr_info("ucode RX Prefetched BDs:\n");
983 pr_info("Base address: 0x%08x\n",
984 (u32
)qe_muram_addr(in_be32
985 (&ugeth
->p_rx_bd_qs_tbl
[i
].
988 qe_muram_addr(in_be32
989 (&ugeth
->p_rx_bd_qs_tbl
[i
].
991 sizeof(struct ucc_geth_rx_prefetched_bds
));
994 if (ugeth
->p_init_enet_param_shadow
) {
996 pr_info("Init enet param shadow:\n");
997 pr_info("Base address: 0x%08x\n",
998 (u32
) ugeth
->p_init_enet_param_shadow
);
999 mem_disp((u8
*) ugeth
->p_init_enet_param_shadow
,
1000 sizeof(*ugeth
->p_init_enet_param_shadow
));
1002 size
= sizeof(struct ucc_geth_thread_rx_pram
);
1003 if (ugeth
->ug_info
->rxExtendedFiltering
) {
1005 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
1006 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1007 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
1009 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
1010 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1011 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
1013 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
1016 dump_init_enet_entries(ugeth
,
1017 &(ugeth
->p_init_enet_param_shadow
->
1019 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1020 sizeof(struct ucc_geth_thread_tx_pram
),
1021 ugeth
->ug_info
->riscTx
, 0);
1022 dump_init_enet_entries(ugeth
,
1023 &(ugeth
->p_init_enet_param_shadow
->
1025 ENET_INIT_PARAM_MAX_ENTRIES_RX
, size
,
1026 ugeth
->ug_info
->riscRx
, 1);
1031 static void init_default_reg_vals(u32 __iomem
*upsmr_register
,
1032 u32 __iomem
*maccfg1_register
,
1033 u32 __iomem
*maccfg2_register
)
1035 out_be32(upsmr_register
, UCC_GETH_UPSMR_INIT
);
1036 out_be32(maccfg1_register
, UCC_GETH_MACCFG1_INIT
);
1037 out_be32(maccfg2_register
, UCC_GETH_MACCFG2_INIT
);
1040 static int init_half_duplex_params(int alt_beb
,
1041 int back_pressure_no_backoff
,
1044 u8 alt_beb_truncation
,
1045 u8 max_retransmissions
,
1046 u8 collision_window
,
1047 u32 __iomem
*hafdup_register
)
1051 if ((alt_beb_truncation
> HALFDUP_ALT_BEB_TRUNCATION_MAX
) ||
1052 (max_retransmissions
> HALFDUP_MAX_RETRANSMISSION_MAX
) ||
1053 (collision_window
> HALFDUP_COLLISION_WINDOW_MAX
))
1056 value
= (u32
) (alt_beb_truncation
<< HALFDUP_ALT_BEB_TRUNCATION_SHIFT
);
1059 value
|= HALFDUP_ALT_BEB
;
1060 if (back_pressure_no_backoff
)
1061 value
|= HALFDUP_BACK_PRESSURE_NO_BACKOFF
;
1063 value
|= HALFDUP_NO_BACKOFF
;
1065 value
|= HALFDUP_EXCESSIVE_DEFER
;
1067 value
|= (max_retransmissions
<< HALFDUP_MAX_RETRANSMISSION_SHIFT
);
1069 value
|= collision_window
;
1071 out_be32(hafdup_register
, value
);
1075 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg
,
1079 u32 __iomem
*ipgifg_register
)
1083 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1085 if (non_btb_cs_ipg
> non_btb_ipg
)
1088 if ((non_btb_cs_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX
) ||
1089 (non_btb_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX
) ||
1090 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1091 (btb_ipg
> IPGIFG_BACK_TO_BACK_IFG_MAX
))
1095 ((non_btb_cs_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT
) &
1096 IPGIFG_NBTB_CS_IPG_MASK
);
1098 ((non_btb_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT
) &
1099 IPGIFG_NBTB_IPG_MASK
);
1101 ((min_ifg
<< IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT
) &
1102 IPGIFG_MIN_IFG_MASK
);
1103 value
|= (btb_ipg
& IPGIFG_BTB_IPG_MASK
);
1105 out_be32(ipgifg_register
, value
);
1109 int init_flow_control_params(u32 automatic_flow_control_mode
,
1110 int rx_flow_control_enable
,
1111 int tx_flow_control_enable
,
1113 u16 extension_field
,
1114 u32 __iomem
*upsmr_register
,
1115 u32 __iomem
*uempr_register
,
1116 u32 __iomem
*maccfg1_register
)
1120 /* Set UEMPR register */
1121 value
= (u32
) pause_period
<< UEMPR_PAUSE_TIME_VALUE_SHIFT
;
1122 value
|= (u32
) extension_field
<< UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT
;
1123 out_be32(uempr_register
, value
);
1125 /* Set UPSMR register */
1126 setbits32(upsmr_register
, automatic_flow_control_mode
);
1128 value
= in_be32(maccfg1_register
);
1129 if (rx_flow_control_enable
)
1130 value
|= MACCFG1_FLOW_RX
;
1131 if (tx_flow_control_enable
)
1132 value
|= MACCFG1_FLOW_TX
;
1133 out_be32(maccfg1_register
, value
);
1138 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics
,
1139 int auto_zero_hardware_statistics
,
1140 u32 __iomem
*upsmr_register
,
1141 u16 __iomem
*uescr_register
)
1143 u16 uescr_value
= 0;
1145 /* Enable hardware statistics gathering if requested */
1146 if (enable_hardware_statistics
)
1147 setbits32(upsmr_register
, UCC_GETH_UPSMR_HSE
);
1149 /* Clear hardware statistics counters */
1150 uescr_value
= in_be16(uescr_register
);
1151 uescr_value
|= UESCR_CLRCNT
;
1152 /* Automatically zero hardware statistics counters on read,
1154 if (auto_zero_hardware_statistics
)
1155 uescr_value
|= UESCR_AUTOZ
;
1156 out_be16(uescr_register
, uescr_value
);
1161 static int init_firmware_statistics_gathering_mode(int
1162 enable_tx_firmware_statistics
,
1163 int enable_rx_firmware_statistics
,
1164 u32 __iomem
*tx_rmon_base_ptr
,
1165 u32 tx_firmware_statistics_structure_address
,
1166 u32 __iomem
*rx_rmon_base_ptr
,
1167 u32 rx_firmware_statistics_structure_address
,
1168 u16 __iomem
*temoder_register
,
1169 u32 __iomem
*remoder_register
)
1171 /* Note: this function does not check if */
1172 /* the parameters it receives are NULL */
1174 if (enable_tx_firmware_statistics
) {
1175 out_be32(tx_rmon_base_ptr
,
1176 tx_firmware_statistics_structure_address
);
1177 setbits16(temoder_register
, TEMODER_TX_RMON_STATISTICS_ENABLE
);
1180 if (enable_rx_firmware_statistics
) {
1181 out_be32(rx_rmon_base_ptr
,
1182 rx_firmware_statistics_structure_address
);
1183 setbits32(remoder_register
, REMODER_RX_RMON_STATISTICS_ENABLE
);
1189 static int init_mac_station_addr_regs(u8 address_byte_0
,
1195 u32 __iomem
*macstnaddr1_register
,
1196 u32 __iomem
*macstnaddr2_register
)
1200 /* Example: for a station address of 0x12345678ABCD, */
1201 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1203 /* MACSTNADDR1 Register: */
1206 /* station address byte 5 station address byte 4 */
1208 /* station address byte 3 station address byte 2 */
1209 value
|= (u32
) ((address_byte_2
<< 0) & 0x000000FF);
1210 value
|= (u32
) ((address_byte_3
<< 8) & 0x0000FF00);
1211 value
|= (u32
) ((address_byte_4
<< 16) & 0x00FF0000);
1212 value
|= (u32
) ((address_byte_5
<< 24) & 0xFF000000);
1214 out_be32(macstnaddr1_register
, value
);
1216 /* MACSTNADDR2 Register: */
1219 /* station address byte 1 station address byte 0 */
1221 /* reserved reserved */
1223 value
|= (u32
) ((address_byte_0
<< 16) & 0x00FF0000);
1224 value
|= (u32
) ((address_byte_1
<< 24) & 0xFF000000);
1226 out_be32(macstnaddr2_register
, value
);
1231 static int init_check_frame_length_mode(int length_check
,
1232 u32 __iomem
*maccfg2_register
)
1236 value
= in_be32(maccfg2_register
);
1239 value
|= MACCFG2_LC
;
1241 value
&= ~MACCFG2_LC
;
1243 out_be32(maccfg2_register
, value
);
1247 static int init_preamble_length(u8 preamble_length
,
1248 u32 __iomem
*maccfg2_register
)
1250 if ((preamble_length
< 3) || (preamble_length
> 7))
1253 clrsetbits_be32(maccfg2_register
, MACCFG2_PREL_MASK
,
1254 preamble_length
<< MACCFG2_PREL_SHIFT
);
1259 static int init_rx_parameters(int reject_broadcast
,
1260 int receive_short_frames
,
1261 int promiscuous
, u32 __iomem
*upsmr_register
)
1265 value
= in_be32(upsmr_register
);
1267 if (reject_broadcast
)
1268 value
|= UCC_GETH_UPSMR_BRO
;
1270 value
&= ~UCC_GETH_UPSMR_BRO
;
1272 if (receive_short_frames
)
1273 value
|= UCC_GETH_UPSMR_RSH
;
1275 value
&= ~UCC_GETH_UPSMR_RSH
;
1278 value
|= UCC_GETH_UPSMR_PRO
;
1280 value
&= ~UCC_GETH_UPSMR_PRO
;
1282 out_be32(upsmr_register
, value
);
1287 static int init_max_rx_buff_len(u16 max_rx_buf_len
,
1288 u16 __iomem
*mrblr_register
)
1290 /* max_rx_buf_len value must be a multiple of 128 */
1291 if ((max_rx_buf_len
== 0) ||
1292 (max_rx_buf_len
% UCC_GETH_MRBLR_ALIGNMENT
))
1295 out_be16(mrblr_register
, max_rx_buf_len
);
1299 static int init_min_frame_len(u16 min_frame_length
,
1300 u16 __iomem
*minflr_register
,
1301 u16 __iomem
*mrblr_register
)
1303 u16 mrblr_value
= 0;
1305 mrblr_value
= in_be16(mrblr_register
);
1306 if (min_frame_length
>= (mrblr_value
- 4))
1309 out_be16(minflr_register
, min_frame_length
);
1313 static int adjust_enet_interface(struct ucc_geth_private
*ugeth
)
1315 struct ucc_geth_info
*ug_info
;
1316 struct ucc_geth __iomem
*ug_regs
;
1317 struct ucc_fast __iomem
*uf_regs
;
1322 ugeth_vdbg("%s: IN", __func__
);
1324 ug_info
= ugeth
->ug_info
;
1325 ug_regs
= ugeth
->ug_regs
;
1326 uf_regs
= ugeth
->uccf
->uf_regs
;
1329 maccfg2
= in_be32(&ug_regs
->maccfg2
);
1330 maccfg2
&= ~MACCFG2_INTERFACE_MODE_MASK
;
1331 if ((ugeth
->max_speed
== SPEED_10
) ||
1332 (ugeth
->max_speed
== SPEED_100
))
1333 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
1334 else if (ugeth
->max_speed
== SPEED_1000
)
1335 maccfg2
|= MACCFG2_INTERFACE_MODE_BYTE
;
1336 maccfg2
|= ug_info
->padAndCrc
;
1337 out_be32(&ug_regs
->maccfg2
, maccfg2
);
1340 upsmr
= in_be32(&uf_regs
->upsmr
);
1341 upsmr
&= ~(UCC_GETH_UPSMR_RPM
| UCC_GETH_UPSMR_R10M
|
1342 UCC_GETH_UPSMR_TBIM
| UCC_GETH_UPSMR_RMM
);
1343 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1344 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1345 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1346 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
1347 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
1348 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1349 if (ugeth
->phy_interface
!= PHY_INTERFACE_MODE_RMII
)
1350 upsmr
|= UCC_GETH_UPSMR_RPM
;
1351 switch (ugeth
->max_speed
) {
1353 upsmr
|= UCC_GETH_UPSMR_R10M
;
1356 if (ugeth
->phy_interface
!= PHY_INTERFACE_MODE_RTBI
)
1357 upsmr
|= UCC_GETH_UPSMR_RMM
;
1360 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1361 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1362 upsmr
|= UCC_GETH_UPSMR_TBIM
;
1364 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_SGMII
))
1365 upsmr
|= UCC_GETH_UPSMR_SGMM
;
1367 out_be32(&uf_regs
->upsmr
, upsmr
);
1369 /* Disable autonegotiation in tbi mode, because by default it
1370 comes up in autonegotiation mode. */
1371 /* Note that this depends on proper setting in utbipar register. */
1372 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1373 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1374 struct ucc_geth_info
*ug_info
= ugeth
->ug_info
;
1375 struct phy_device
*tbiphy
;
1377 if (!ug_info
->tbi_node
)
1378 pr_warn("TBI mode requires that the device tree specify a tbi-handle\n");
1380 tbiphy
= of_phy_find_device(ug_info
->tbi_node
);
1382 pr_warn("Could not get TBI device\n");
1384 value
= phy_read(tbiphy
, ENET_TBI_MII_CR
);
1385 value
&= ~0x1000; /* Turn off autonegotiation */
1386 phy_write(tbiphy
, ENET_TBI_MII_CR
, value
);
1389 init_check_frame_length_mode(ug_info
->lengthCheckRx
, &ug_regs
->maccfg2
);
1391 ret_val
= init_preamble_length(ug_info
->prel
, &ug_regs
->maccfg2
);
1393 if (netif_msg_probe(ugeth
))
1394 pr_err("Preamble length must be between 3 and 7 inclusive\n");
1401 static int ugeth_graceful_stop_tx(struct ucc_geth_private
*ugeth
)
1403 struct ucc_fast_private
*uccf
;
1410 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1411 clrbits32(uccf
->p_uccm
, UCC_GETH_UCCE_GRA
);
1412 out_be32(uccf
->p_ucce
, UCC_GETH_UCCE_GRA
); /* clear by writing 1 */
1414 /* Issue host command */
1416 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1417 qe_issue_cmd(QE_GRACEFUL_STOP_TX
, cecr_subblock
,
1418 QE_CR_PROTOCOL_ETHERNET
, 0);
1420 /* Wait for command to complete */
1423 temp
= in_be32(uccf
->p_ucce
);
1424 } while (!(temp
& UCC_GETH_UCCE_GRA
) && --i
);
1426 uccf
->stopped_tx
= 1;
1431 static int ugeth_graceful_stop_rx(struct ucc_geth_private
*ugeth
)
1433 struct ucc_fast_private
*uccf
;
1440 /* Clear acknowledge bit */
1441 temp
= in_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
);
1442 temp
&= ~GRACEFUL_STOP_ACKNOWLEDGE_RX
;
1443 out_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
, temp
);
1445 /* Keep issuing command and checking acknowledge bit until
1446 it is asserted, according to spec */
1448 /* Issue host command */
1450 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.
1452 qe_issue_cmd(QE_GRACEFUL_STOP_RX
, cecr_subblock
,
1453 QE_CR_PROTOCOL_ETHERNET
, 0);
1455 temp
= in_8(&ugeth
->p_rx_glbl_pram
->rxgstpack
);
1456 } while (!(temp
& GRACEFUL_STOP_ACKNOWLEDGE_RX
) && --i
);
1458 uccf
->stopped_rx
= 1;
1463 static int ugeth_restart_tx(struct ucc_geth_private
*ugeth
)
1465 struct ucc_fast_private
*uccf
;
1471 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1472 qe_issue_cmd(QE_RESTART_TX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
, 0);
1473 uccf
->stopped_tx
= 0;
1478 static int ugeth_restart_rx(struct ucc_geth_private
*ugeth
)
1480 struct ucc_fast_private
*uccf
;
1486 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1487 qe_issue_cmd(QE_RESTART_RX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
1489 uccf
->stopped_rx
= 0;
1494 static int ugeth_enable(struct ucc_geth_private
*ugeth
, enum comm_dir mode
)
1496 struct ucc_fast_private
*uccf
;
1497 int enabled_tx
, enabled_rx
;
1501 /* check if the UCC number is in range. */
1502 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1503 if (netif_msg_probe(ugeth
))
1504 pr_err("ucc_num out of range\n");
1508 enabled_tx
= uccf
->enabled_tx
;
1509 enabled_rx
= uccf
->enabled_rx
;
1511 /* Get Tx and Rx going again, in case this channel was actively
1513 if ((mode
& COMM_DIR_TX
) && (!enabled_tx
) && uccf
->stopped_tx
)
1514 ugeth_restart_tx(ugeth
);
1515 if ((mode
& COMM_DIR_RX
) && (!enabled_rx
) && uccf
->stopped_rx
)
1516 ugeth_restart_rx(ugeth
);
1518 ucc_fast_enable(uccf
, mode
); /* OK to do even if not disabled */
1524 static int ugeth_disable(struct ucc_geth_private
*ugeth
, enum comm_dir mode
)
1526 struct ucc_fast_private
*uccf
;
1530 /* check if the UCC number is in range. */
1531 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1532 if (netif_msg_probe(ugeth
))
1533 pr_err("ucc_num out of range\n");
1537 /* Stop any transmissions */
1538 if ((mode
& COMM_DIR_TX
) && uccf
->enabled_tx
&& !uccf
->stopped_tx
)
1539 ugeth_graceful_stop_tx(ugeth
);
1541 /* Stop any receptions */
1542 if ((mode
& COMM_DIR_RX
) && uccf
->enabled_rx
&& !uccf
->stopped_rx
)
1543 ugeth_graceful_stop_rx(ugeth
);
1545 ucc_fast_disable(ugeth
->uccf
, mode
); /* OK to do even if not enabled */
1550 static void ugeth_quiesce(struct ucc_geth_private
*ugeth
)
1552 /* Prevent any further xmits, plus detach the device. */
1553 netif_device_detach(ugeth
->ndev
);
1555 /* Wait for any current xmits to finish. */
1556 netif_tx_disable(ugeth
->ndev
);
1558 /* Disable the interrupt to avoid NAPI rescheduling. */
1559 disable_irq(ugeth
->ug_info
->uf_info
.irq
);
1561 /* Stop NAPI, and possibly wait for its completion. */
1562 napi_disable(&ugeth
->napi
);
1565 static void ugeth_activate(struct ucc_geth_private
*ugeth
)
1567 napi_enable(&ugeth
->napi
);
1568 enable_irq(ugeth
->ug_info
->uf_info
.irq
);
1569 netif_device_attach(ugeth
->ndev
);
1572 /* Called every time the controller might need to be made
1573 * aware of new link state. The PHY code conveys this
1574 * information through variables in the ugeth structure, and this
1575 * function converts those variables into the appropriate
1576 * register values, and can bring down the device if needed.
1579 static void adjust_link(struct net_device
*dev
)
1581 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
1582 struct ucc_geth __iomem
*ug_regs
;
1583 struct ucc_fast __iomem
*uf_regs
;
1584 struct phy_device
*phydev
= ugeth
->phydev
;
1587 ug_regs
= ugeth
->ug_regs
;
1588 uf_regs
= ugeth
->uccf
->uf_regs
;
1591 u32 tempval
= in_be32(&ug_regs
->maccfg2
);
1592 u32 upsmr
= in_be32(&uf_regs
->upsmr
);
1593 /* Now we make sure that we can be in full duplex mode.
1594 * If not, we operate in half-duplex mode. */
1595 if (phydev
->duplex
!= ugeth
->oldduplex
) {
1597 if (!(phydev
->duplex
))
1598 tempval
&= ~(MACCFG2_FDX
);
1600 tempval
|= MACCFG2_FDX
;
1601 ugeth
->oldduplex
= phydev
->duplex
;
1604 if (phydev
->speed
!= ugeth
->oldspeed
) {
1606 switch (phydev
->speed
) {
1608 tempval
= ((tempval
&
1609 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1610 MACCFG2_INTERFACE_MODE_BYTE
);
1614 tempval
= ((tempval
&
1615 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1616 MACCFG2_INTERFACE_MODE_NIBBLE
);
1617 /* if reduced mode, re-set UPSMR.R10M */
1618 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1619 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1620 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1621 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
1622 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_TXID
) ||
1623 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1624 if (phydev
->speed
== SPEED_10
)
1625 upsmr
|= UCC_GETH_UPSMR_R10M
;
1627 upsmr
&= ~UCC_GETH_UPSMR_R10M
;
1631 if (netif_msg_link(ugeth
))
1633 "%s: Ack! Speed (%d) is not 10/100/1000!",
1634 dev
->name
, phydev
->speed
);
1637 ugeth
->oldspeed
= phydev
->speed
;
1640 if (!ugeth
->oldlink
) {
1647 * To change the MAC configuration we need to disable
1648 * the controller. To do so, we have to either grab
1649 * ugeth->lock, which is a bad idea since 'graceful
1650 * stop' commands might take quite a while, or we can
1651 * quiesce driver's activity.
1653 ugeth_quiesce(ugeth
);
1654 ugeth_disable(ugeth
, COMM_DIR_RX_AND_TX
);
1656 out_be32(&ug_regs
->maccfg2
, tempval
);
1657 out_be32(&uf_regs
->upsmr
, upsmr
);
1659 ugeth_enable(ugeth
, COMM_DIR_RX_AND_TX
);
1660 ugeth_activate(ugeth
);
1662 } else if (ugeth
->oldlink
) {
1665 ugeth
->oldspeed
= 0;
1666 ugeth
->oldduplex
= -1;
1669 if (new_state
&& netif_msg_link(ugeth
))
1670 phy_print_status(phydev
);
1673 /* Initialize TBI PHY interface for communicating with the
1674 * SERDES lynx PHY on the chip. We communicate with this PHY
1675 * through the MDIO bus on each controller, treating it as a
1676 * "normal" PHY at the address found in the UTBIPA register. We assume
1677 * that the UTBIPA register is valid. Either the MDIO bus code will set
1678 * it to a value that doesn't conflict with other PHYs on the bus, or the
1679 * value doesn't matter, as there are no other PHYs on the bus.
1681 static void uec_configure_serdes(struct net_device
*dev
)
1683 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
1684 struct ucc_geth_info
*ug_info
= ugeth
->ug_info
;
1685 struct phy_device
*tbiphy
;
1687 if (!ug_info
->tbi_node
) {
1688 dev_warn(&dev
->dev
, "SGMII mode requires that the device "
1689 "tree specify a tbi-handle\n");
1693 tbiphy
= of_phy_find_device(ug_info
->tbi_node
);
1695 dev_err(&dev
->dev
, "error: Could not get TBI device\n");
1700 * If the link is already up, we must already be ok, and don't need to
1701 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1702 * everything for us? Resetting it takes the link down and requires
1703 * several seconds for it to come back.
1705 if (phy_read(tbiphy
, ENET_TBI_MII_SR
) & TBISR_LSTATUS
)
1708 /* Single clk mode, mii mode off(for serdes communication) */
1709 phy_write(tbiphy
, ENET_TBI_MII_ANA
, TBIANA_SETTINGS
);
1711 phy_write(tbiphy
, ENET_TBI_MII_TBICON
, TBICON_CLK_SELECT
);
1713 phy_write(tbiphy
, ENET_TBI_MII_CR
, TBICR_SETTINGS
);
1716 /* Configure the PHY for dev.
1717 * returns 0 if success. -1 if failure
1719 static int init_phy(struct net_device
*dev
)
1721 struct ucc_geth_private
*priv
= netdev_priv(dev
);
1722 struct ucc_geth_info
*ug_info
= priv
->ug_info
;
1723 struct phy_device
*phydev
;
1727 priv
->oldduplex
= -1;
1729 phydev
= of_phy_connect(dev
, ug_info
->phy_node
, &adjust_link
, 0,
1730 priv
->phy_interface
);
1732 dev_err(&dev
->dev
, "Could not attach to PHY\n");
1736 if (priv
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
1737 uec_configure_serdes(dev
);
1739 phydev
->supported
&= (SUPPORTED_MII
|
1741 ADVERTISED_10baseT_Half
|
1742 ADVERTISED_10baseT_Full
|
1743 ADVERTISED_100baseT_Half
|
1744 ADVERTISED_100baseT_Full
);
1746 if (priv
->max_speed
== SPEED_1000
)
1747 phydev
->supported
|= ADVERTISED_1000baseT_Full
;
1749 phydev
->advertising
= phydev
->supported
;
1751 priv
->phydev
= phydev
;
1756 static void ugeth_dump_regs(struct ucc_geth_private
*ugeth
)
1759 ucc_fast_dump_regs(ugeth
->uccf
);
1765 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private
*
1770 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
1771 struct ucc_fast_private
*uccf
;
1772 enum comm_dir comm_dir
;
1773 struct list_head
*p_lh
;
1775 u32 __iomem
*addr_h
;
1776 u32 __iomem
*addr_l
;
1782 (struct ucc_geth_82xx_address_filtering_pram __iomem
*)
1783 ugeth
->p_rx_glbl_pram
->addressfiltering
;
1785 if (enet_addr_type
== ENET_ADDR_TYPE_GROUP
) {
1786 addr_h
= &(p_82xx_addr_filt
->gaddr_h
);
1787 addr_l
= &(p_82xx_addr_filt
->gaddr_l
);
1788 p_lh
= &ugeth
->group_hash_q
;
1789 p_counter
= &(ugeth
->numGroupAddrInHash
);
1790 } else if (enet_addr_type
== ENET_ADDR_TYPE_INDIVIDUAL
) {
1791 addr_h
= &(p_82xx_addr_filt
->iaddr_h
);
1792 addr_l
= &(p_82xx_addr_filt
->iaddr_l
);
1793 p_lh
= &ugeth
->ind_hash_q
;
1794 p_counter
= &(ugeth
->numIndAddrInHash
);
1799 if (uccf
->enabled_tx
)
1800 comm_dir
|= COMM_DIR_TX
;
1801 if (uccf
->enabled_rx
)
1802 comm_dir
|= COMM_DIR_RX
;
1804 ugeth_disable(ugeth
, comm_dir
);
1806 /* Clear the hash table. */
1807 out_be32(addr_h
, 0x00000000);
1808 out_be32(addr_l
, 0x00000000);
1815 /* Delete all remaining CQ elements */
1816 for (i
= 0; i
< num
; i
++)
1817 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh
)));
1822 ugeth_enable(ugeth
, comm_dir
);
1827 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
,
1830 ugeth
->indAddrRegUsed
[paddr_num
] = 0; /* mark this paddr as not used */
1831 return hw_clear_addr_in_paddr(ugeth
, paddr_num
);/* clear in hardware */
1834 static void ucc_geth_free_rx(struct ucc_geth_private
*ugeth
)
1836 struct ucc_geth_info
*ug_info
;
1837 struct ucc_fast_info
*uf_info
;
1842 ug_info
= ugeth
->ug_info
;
1843 uf_info
= &ug_info
->uf_info
;
1845 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1846 if (ugeth
->p_rx_bd_ring
[i
]) {
1847 /* Return existing data buffers in ring */
1848 bd
= ugeth
->p_rx_bd_ring
[i
];
1849 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenRx
[i
]; j
++) {
1850 if (ugeth
->rx_skbuff
[i
][j
]) {
1851 dma_unmap_single(ugeth
->dev
,
1852 in_be32(&((struct qe_bd __iomem
*)bd
)->buf
),
1854 uf_info
.max_rx_buf_length
+
1855 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
1858 ugeth
->rx_skbuff
[i
][j
]);
1859 ugeth
->rx_skbuff
[i
][j
] = NULL
;
1861 bd
+= sizeof(struct qe_bd
);
1864 kfree(ugeth
->rx_skbuff
[i
]);
1866 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1868 kfree((void *)ugeth
->rx_bd_ring_offset
[i
]);
1869 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1871 qe_muram_free(ugeth
->rx_bd_ring_offset
[i
]);
1872 ugeth
->p_rx_bd_ring
[i
] = NULL
;
1878 static void ucc_geth_free_tx(struct ucc_geth_private
*ugeth
)
1880 struct ucc_geth_info
*ug_info
;
1881 struct ucc_fast_info
*uf_info
;
1885 ug_info
= ugeth
->ug_info
;
1886 uf_info
= &ug_info
->uf_info
;
1888 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
1889 bd
= ugeth
->p_tx_bd_ring
[i
];
1892 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenTx
[i
]; j
++) {
1893 if (ugeth
->tx_skbuff
[i
][j
]) {
1894 dma_unmap_single(ugeth
->dev
,
1895 in_be32(&((struct qe_bd __iomem
*)bd
)->buf
),
1896 (in_be32((u32 __iomem
*)bd
) &
1899 dev_kfree_skb_any(ugeth
->tx_skbuff
[i
][j
]);
1900 ugeth
->tx_skbuff
[i
][j
] = NULL
;
1904 kfree(ugeth
->tx_skbuff
[i
]);
1906 if (ugeth
->p_tx_bd_ring
[i
]) {
1907 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1909 kfree((void *)ugeth
->tx_bd_ring_offset
[i
]);
1910 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
1912 qe_muram_free(ugeth
->tx_bd_ring_offset
[i
]);
1913 ugeth
->p_tx_bd_ring
[i
] = NULL
;
1919 static void ucc_geth_memclean(struct ucc_geth_private
*ugeth
)
1925 ucc_fast_free(ugeth
->uccf
);
1929 if (ugeth
->p_thread_data_tx
) {
1930 qe_muram_free(ugeth
->thread_dat_tx_offset
);
1931 ugeth
->p_thread_data_tx
= NULL
;
1933 if (ugeth
->p_thread_data_rx
) {
1934 qe_muram_free(ugeth
->thread_dat_rx_offset
);
1935 ugeth
->p_thread_data_rx
= NULL
;
1937 if (ugeth
->p_exf_glbl_param
) {
1938 qe_muram_free(ugeth
->exf_glbl_param_offset
);
1939 ugeth
->p_exf_glbl_param
= NULL
;
1941 if (ugeth
->p_rx_glbl_pram
) {
1942 qe_muram_free(ugeth
->rx_glbl_pram_offset
);
1943 ugeth
->p_rx_glbl_pram
= NULL
;
1945 if (ugeth
->p_tx_glbl_pram
) {
1946 qe_muram_free(ugeth
->tx_glbl_pram_offset
);
1947 ugeth
->p_tx_glbl_pram
= NULL
;
1949 if (ugeth
->p_send_q_mem_reg
) {
1950 qe_muram_free(ugeth
->send_q_mem_reg_offset
);
1951 ugeth
->p_send_q_mem_reg
= NULL
;
1953 if (ugeth
->p_scheduler
) {
1954 qe_muram_free(ugeth
->scheduler_offset
);
1955 ugeth
->p_scheduler
= NULL
;
1957 if (ugeth
->p_tx_fw_statistics_pram
) {
1958 qe_muram_free(ugeth
->tx_fw_statistics_pram_offset
);
1959 ugeth
->p_tx_fw_statistics_pram
= NULL
;
1961 if (ugeth
->p_rx_fw_statistics_pram
) {
1962 qe_muram_free(ugeth
->rx_fw_statistics_pram_offset
);
1963 ugeth
->p_rx_fw_statistics_pram
= NULL
;
1965 if (ugeth
->p_rx_irq_coalescing_tbl
) {
1966 qe_muram_free(ugeth
->rx_irq_coalescing_tbl_offset
);
1967 ugeth
->p_rx_irq_coalescing_tbl
= NULL
;
1969 if (ugeth
->p_rx_bd_qs_tbl
) {
1970 qe_muram_free(ugeth
->rx_bd_qs_tbl_offset
);
1971 ugeth
->p_rx_bd_qs_tbl
= NULL
;
1973 if (ugeth
->p_init_enet_param_shadow
) {
1974 return_init_enet_entries(ugeth
,
1975 &(ugeth
->p_init_enet_param_shadow
->
1977 ENET_INIT_PARAM_MAX_ENTRIES_RX
,
1978 ugeth
->ug_info
->riscRx
, 1);
1979 return_init_enet_entries(ugeth
,
1980 &(ugeth
->p_init_enet_param_shadow
->
1982 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1983 ugeth
->ug_info
->riscTx
, 0);
1984 kfree(ugeth
->p_init_enet_param_shadow
);
1985 ugeth
->p_init_enet_param_shadow
= NULL
;
1987 ucc_geth_free_tx(ugeth
);
1988 ucc_geth_free_rx(ugeth
);
1989 while (!list_empty(&ugeth
->group_hash_q
))
1990 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1991 (dequeue(&ugeth
->group_hash_q
)));
1992 while (!list_empty(&ugeth
->ind_hash_q
))
1993 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1994 (dequeue(&ugeth
->ind_hash_q
)));
1995 if (ugeth
->ug_regs
) {
1996 iounmap(ugeth
->ug_regs
);
1997 ugeth
->ug_regs
= NULL
;
2001 static void ucc_geth_set_multi(struct net_device
*dev
)
2003 struct ucc_geth_private
*ugeth
;
2004 struct netdev_hw_addr
*ha
;
2005 struct ucc_fast __iomem
*uf_regs
;
2006 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
2008 ugeth
= netdev_priv(dev
);
2010 uf_regs
= ugeth
->uccf
->uf_regs
;
2012 if (dev
->flags
& IFF_PROMISC
) {
2013 setbits32(&uf_regs
->upsmr
, UCC_GETH_UPSMR_PRO
);
2015 clrbits32(&uf_regs
->upsmr
, UCC_GETH_UPSMR_PRO
);
2018 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->
2019 p_rx_glbl_pram
->addressfiltering
;
2021 if (dev
->flags
& IFF_ALLMULTI
) {
2022 /* Catch all multicast addresses, so set the
2023 * filter to all 1's.
2025 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0xffffffff);
2026 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0xffffffff);
2028 /* Clear filter and add the addresses in the list.
2030 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0x0);
2031 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0x0);
2033 netdev_for_each_mc_addr(ha
, dev
) {
2034 /* Ask CPM to run CRC and set bit in
2037 hw_add_addr_in_hash(ugeth
, ha
->addr
);
2043 static void ucc_geth_stop(struct ucc_geth_private
*ugeth
)
2045 struct ucc_geth __iomem
*ug_regs
= ugeth
->ug_regs
;
2046 struct phy_device
*phydev
= ugeth
->phydev
;
2048 ugeth_vdbg("%s: IN", __func__
);
2051 * Tell the kernel the link is down.
2052 * Must be done before disabling the controller
2053 * or deadlock may happen.
2057 /* Disable the controller */
2058 ugeth_disable(ugeth
, COMM_DIR_RX_AND_TX
);
2060 /* Mask all interrupts */
2061 out_be32(ugeth
->uccf
->p_uccm
, 0x00000000);
2063 /* Clear all interrupts */
2064 out_be32(ugeth
->uccf
->p_ucce
, 0xffffffff);
2066 /* Disable Rx and Tx */
2067 clrbits32(&ug_regs
->maccfg1
, MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2069 ucc_geth_memclean(ugeth
);
2072 static int ucc_struct_init(struct ucc_geth_private
*ugeth
)
2074 struct ucc_geth_info
*ug_info
;
2075 struct ucc_fast_info
*uf_info
;
2078 ug_info
= ugeth
->ug_info
;
2079 uf_info
= &ug_info
->uf_info
;
2081 if (!((uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) ||
2082 (uf_info
->bd_mem_part
== MEM_PART_MURAM
))) {
2083 if (netif_msg_probe(ugeth
))
2084 pr_err("Bad memory partition value\n");
2089 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2090 if ((ug_info
->bdRingLenRx
[i
] < UCC_GETH_RX_BD_RING_SIZE_MIN
) ||
2091 (ug_info
->bdRingLenRx
[i
] %
2092 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT
)) {
2093 if (netif_msg_probe(ugeth
))
2094 pr_err("Rx BD ring length must be multiple of 4, no smaller than 8\n");
2100 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2101 if (ug_info
->bdRingLenTx
[i
] < UCC_GETH_TX_BD_RING_SIZE_MIN
) {
2102 if (netif_msg_probe(ugeth
))
2103 pr_err("Tx BD ring length must be no smaller than 2\n");
2109 if ((uf_info
->max_rx_buf_length
== 0) ||
2110 (uf_info
->max_rx_buf_length
% UCC_GETH_MRBLR_ALIGNMENT
)) {
2111 if (netif_msg_probe(ugeth
))
2112 pr_err("max_rx_buf_length must be non-zero multiple of 128\n");
2117 if (ug_info
->numQueuesTx
> NUM_TX_QUEUES
) {
2118 if (netif_msg_probe(ugeth
))
2119 pr_err("number of tx queues too large\n");
2124 if (ug_info
->numQueuesRx
> NUM_RX_QUEUES
) {
2125 if (netif_msg_probe(ugeth
))
2126 pr_err("number of rx queues too large\n");
2131 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++) {
2132 if (ug_info
->l2qt
[i
] >= ug_info
->numQueuesRx
) {
2133 if (netif_msg_probe(ugeth
))
2134 pr_err("VLAN priority table entry must not be larger than number of Rx queues\n");
2140 for (i
= 0; i
< UCC_GETH_IP_PRIORITY_MAX
; i
++) {
2141 if (ug_info
->l3qt
[i
] >= ug_info
->numQueuesRx
) {
2142 if (netif_msg_probe(ugeth
))
2143 pr_err("IP priority table entry must not be larger than number of Rx queues\n");
2148 if (ug_info
->cam
&& !ug_info
->ecamptr
) {
2149 if (netif_msg_probe(ugeth
))
2150 pr_err("If cam mode is chosen, must supply cam ptr\n");
2154 if ((ug_info
->numStationAddresses
!=
2155 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
) &&
2156 ug_info
->rxExtendedFiltering
) {
2157 if (netif_msg_probe(ugeth
))
2158 pr_err("Number of station addresses greater than 1 not allowed in extended parsing mode\n");
2162 /* Generate uccm_mask for receive */
2163 uf_info
->uccm_mask
= ug_info
->eventRegMask
& UCCE_OTHER
;/* Errors */
2164 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
2165 uf_info
->uccm_mask
|= (UCC_GETH_UCCE_RXF0
<< i
);
2167 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++)
2168 uf_info
->uccm_mask
|= (UCC_GETH_UCCE_TXB0
<< i
);
2169 /* Initialize the general fast UCC block. */
2170 if (ucc_fast_init(uf_info
, &ugeth
->uccf
)) {
2171 if (netif_msg_probe(ugeth
))
2172 pr_err("Failed to init uccf\n");
2176 /* read the number of risc engines, update the riscTx and riscRx
2177 * if there are 4 riscs in QE
2179 if (qe_get_num_of_risc() == 4) {
2180 ug_info
->riscTx
= QE_RISC_ALLOCATION_FOUR_RISCS
;
2181 ug_info
->riscRx
= QE_RISC_ALLOCATION_FOUR_RISCS
;
2184 ugeth
->ug_regs
= ioremap(uf_info
->regs
, sizeof(*ugeth
->ug_regs
));
2185 if (!ugeth
->ug_regs
) {
2186 if (netif_msg_probe(ugeth
))
2187 pr_err("Failed to ioremap regs\n");
2194 static int ucc_geth_alloc_tx(struct ucc_geth_private
*ugeth
)
2196 struct ucc_geth_info
*ug_info
;
2197 struct ucc_fast_info
*uf_info
;
2202 ug_info
= ugeth
->ug_info
;
2203 uf_info
= &ug_info
->uf_info
;
2205 /* Allocate Tx bds */
2206 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2207 /* Allocate in multiple of
2208 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2209 according to spec */
2210 length
= ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
))
2211 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2212 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2213 if ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)) %
2214 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2215 length
+= UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2216 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2218 if (UCC_GETH_TX_BD_RING_ALIGNMENT
> 4)
2219 align
= UCC_GETH_TX_BD_RING_ALIGNMENT
;
2220 ugeth
->tx_bd_ring_offset
[j
] =
2221 (u32
) kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2223 if (ugeth
->tx_bd_ring_offset
[j
] != 0)
2224 ugeth
->p_tx_bd_ring
[j
] =
2225 (u8 __iomem
*)((ugeth
->tx_bd_ring_offset
[j
] +
2226 align
) & ~(align
- 1));
2227 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2228 ugeth
->tx_bd_ring_offset
[j
] =
2229 qe_muram_alloc(length
,
2230 UCC_GETH_TX_BD_RING_ALIGNMENT
);
2231 if (!IS_ERR_VALUE(ugeth
->tx_bd_ring_offset
[j
]))
2232 ugeth
->p_tx_bd_ring
[j
] =
2233 (u8 __iomem
*) qe_muram_addr(ugeth
->
2234 tx_bd_ring_offset
[j
]);
2236 if (!ugeth
->p_tx_bd_ring
[j
]) {
2237 if (netif_msg_ifup(ugeth
))
2238 pr_err("Can not allocate memory for Tx bd rings\n");
2241 /* Zero unused end of bd ring, according to spec */
2242 memset_io((void __iomem
*)(ugeth
->p_tx_bd_ring
[j
] +
2243 ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)), 0,
2244 length
- ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
));
2248 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2249 /* Setup the skbuff rings */
2250 ugeth
->tx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2251 ugeth
->ug_info
->bdRingLenTx
[j
],
2254 if (ugeth
->tx_skbuff
[j
] == NULL
) {
2255 if (netif_msg_ifup(ugeth
))
2256 pr_err("Could not allocate tx_skbuff\n");
2260 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenTx
[j
]; i
++)
2261 ugeth
->tx_skbuff
[j
][i
] = NULL
;
2263 ugeth
->skb_curtx
[j
] = ugeth
->skb_dirtytx
[j
] = 0;
2264 bd
= ugeth
->confBd
[j
] = ugeth
->txBd
[j
] = ugeth
->p_tx_bd_ring
[j
];
2265 for (i
= 0; i
< ug_info
->bdRingLenTx
[j
]; i
++) {
2266 /* clear bd buffer */
2267 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
, 0);
2268 /* set bd status and length */
2269 out_be32((u32 __iomem
*)bd
, 0);
2270 bd
+= sizeof(struct qe_bd
);
2272 bd
-= sizeof(struct qe_bd
);
2273 /* set bd status and length */
2274 out_be32((u32 __iomem
*)bd
, T_W
); /* for last BD set Wrap bit */
2280 static int ucc_geth_alloc_rx(struct ucc_geth_private
*ugeth
)
2282 struct ucc_geth_info
*ug_info
;
2283 struct ucc_fast_info
*uf_info
;
2288 ug_info
= ugeth
->ug_info
;
2289 uf_info
= &ug_info
->uf_info
;
2291 /* Allocate Rx bds */
2292 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2293 length
= ug_info
->bdRingLenRx
[j
] * sizeof(struct qe_bd
);
2294 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2296 if (UCC_GETH_RX_BD_RING_ALIGNMENT
> 4)
2297 align
= UCC_GETH_RX_BD_RING_ALIGNMENT
;
2298 ugeth
->rx_bd_ring_offset
[j
] =
2299 (u32
) kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2300 if (ugeth
->rx_bd_ring_offset
[j
] != 0)
2301 ugeth
->p_rx_bd_ring
[j
] =
2302 (u8 __iomem
*)((ugeth
->rx_bd_ring_offset
[j
] +
2303 align
) & ~(align
- 1));
2304 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2305 ugeth
->rx_bd_ring_offset
[j
] =
2306 qe_muram_alloc(length
,
2307 UCC_GETH_RX_BD_RING_ALIGNMENT
);
2308 if (!IS_ERR_VALUE(ugeth
->rx_bd_ring_offset
[j
]))
2309 ugeth
->p_rx_bd_ring
[j
] =
2310 (u8 __iomem
*) qe_muram_addr(ugeth
->
2311 rx_bd_ring_offset
[j
]);
2313 if (!ugeth
->p_rx_bd_ring
[j
]) {
2314 if (netif_msg_ifup(ugeth
))
2315 pr_err("Can not allocate memory for Rx bd rings\n");
2321 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2322 /* Setup the skbuff rings */
2323 ugeth
->rx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2324 ugeth
->ug_info
->bdRingLenRx
[j
],
2327 if (ugeth
->rx_skbuff
[j
] == NULL
) {
2328 if (netif_msg_ifup(ugeth
))
2329 pr_err("Could not allocate rx_skbuff\n");
2333 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenRx
[j
]; i
++)
2334 ugeth
->rx_skbuff
[j
][i
] = NULL
;
2336 ugeth
->skb_currx
[j
] = 0;
2337 bd
= ugeth
->rxBd
[j
] = ugeth
->p_rx_bd_ring
[j
];
2338 for (i
= 0; i
< ug_info
->bdRingLenRx
[j
]; i
++) {
2339 /* set bd status and length */
2340 out_be32((u32 __iomem
*)bd
, R_I
);
2341 /* clear bd buffer */
2342 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
, 0);
2343 bd
+= sizeof(struct qe_bd
);
2345 bd
-= sizeof(struct qe_bd
);
2346 /* set bd status and length */
2347 out_be32((u32 __iomem
*)bd
, R_W
); /* for last BD set Wrap bit */
2353 static int ucc_geth_startup(struct ucc_geth_private
*ugeth
)
2355 struct ucc_geth_82xx_address_filtering_pram __iomem
*p_82xx_addr_filt
;
2356 struct ucc_geth_init_pram __iomem
*p_init_enet_pram
;
2357 struct ucc_fast_private
*uccf
;
2358 struct ucc_geth_info
*ug_info
;
2359 struct ucc_fast_info
*uf_info
;
2360 struct ucc_fast __iomem
*uf_regs
;
2361 struct ucc_geth __iomem
*ug_regs
;
2362 int ret_val
= -EINVAL
;
2363 u32 remoder
= UCC_GETH_REMODER_INIT
;
2364 u32 init_enet_pram_offset
, cecr_subblock
, command
;
2365 u32 ifstat
, i
, j
, size
, l2qt
, l3qt
;
2366 u16 temoder
= UCC_GETH_TEMODER_INIT
;
2368 u8 function_code
= 0;
2369 u8 __iomem
*endOfRing
;
2370 u8 numThreadsRxNumerical
, numThreadsTxNumerical
;
2372 ugeth_vdbg("%s: IN", __func__
);
2374 ug_info
= ugeth
->ug_info
;
2375 uf_info
= &ug_info
->uf_info
;
2376 uf_regs
= uccf
->uf_regs
;
2377 ug_regs
= ugeth
->ug_regs
;
2379 switch (ug_info
->numThreadsRx
) {
2380 case UCC_GETH_NUM_OF_THREADS_1
:
2381 numThreadsRxNumerical
= 1;
2383 case UCC_GETH_NUM_OF_THREADS_2
:
2384 numThreadsRxNumerical
= 2;
2386 case UCC_GETH_NUM_OF_THREADS_4
:
2387 numThreadsRxNumerical
= 4;
2389 case UCC_GETH_NUM_OF_THREADS_6
:
2390 numThreadsRxNumerical
= 6;
2392 case UCC_GETH_NUM_OF_THREADS_8
:
2393 numThreadsRxNumerical
= 8;
2396 if (netif_msg_ifup(ugeth
))
2397 pr_err("Bad number of Rx threads value\n");
2401 switch (ug_info
->numThreadsTx
) {
2402 case UCC_GETH_NUM_OF_THREADS_1
:
2403 numThreadsTxNumerical
= 1;
2405 case UCC_GETH_NUM_OF_THREADS_2
:
2406 numThreadsTxNumerical
= 2;
2408 case UCC_GETH_NUM_OF_THREADS_4
:
2409 numThreadsTxNumerical
= 4;
2411 case UCC_GETH_NUM_OF_THREADS_6
:
2412 numThreadsTxNumerical
= 6;
2414 case UCC_GETH_NUM_OF_THREADS_8
:
2415 numThreadsTxNumerical
= 8;
2418 if (netif_msg_ifup(ugeth
))
2419 pr_err("Bad number of Tx threads value\n");
2423 /* Calculate rx_extended_features */
2424 ugeth
->rx_non_dynamic_extended_features
= ug_info
->ipCheckSumCheck
||
2425 ug_info
->ipAddressAlignment
||
2426 (ug_info
->numStationAddresses
!=
2427 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
);
2429 ugeth
->rx_extended_features
= ugeth
->rx_non_dynamic_extended_features
||
2430 (ug_info
->vlanOperationTagged
!= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
) ||
2431 (ug_info
->vlanOperationNonTagged
!=
2432 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
);
2434 init_default_reg_vals(&uf_regs
->upsmr
,
2435 &ug_regs
->maccfg1
, &ug_regs
->maccfg2
);
2438 /* For more details see the hardware spec. */
2439 init_rx_parameters(ug_info
->bro
,
2440 ug_info
->rsh
, ug_info
->pro
, &uf_regs
->upsmr
);
2442 /* We're going to ignore other registers for now, */
2443 /* except as needed to get up and running */
2446 /* For more details see the hardware spec. */
2447 init_flow_control_params(ug_info
->aufc
,
2448 ug_info
->receiveFlowControl
,
2449 ug_info
->transmitFlowControl
,
2450 ug_info
->pausePeriod
,
2451 ug_info
->extensionField
,
2453 &ug_regs
->uempr
, &ug_regs
->maccfg1
);
2455 setbits32(&ug_regs
->maccfg1
, MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2458 /* For more details see the hardware spec. */
2459 ret_val
= init_inter_frame_gap_params(ug_info
->nonBackToBackIfgPart1
,
2460 ug_info
->nonBackToBackIfgPart2
,
2462 miminumInterFrameGapEnforcement
,
2463 ug_info
->backToBackInterFrameGap
,
2466 if (netif_msg_ifup(ugeth
))
2467 pr_err("IPGIFG initialization parameter too large\n");
2472 /* For more details see the hardware spec. */
2473 ret_val
= init_half_duplex_params(ug_info
->altBeb
,
2474 ug_info
->backPressureNoBackoff
,
2476 ug_info
->excessDefer
,
2477 ug_info
->altBebTruncation
,
2478 ug_info
->maxRetransmission
,
2479 ug_info
->collisionWindow
,
2482 if (netif_msg_ifup(ugeth
))
2483 pr_err("Half Duplex initialization parameter too large\n");
2488 /* For more details see the hardware spec. */
2489 /* Read only - resets upon read */
2490 ifstat
= in_be32(&ug_regs
->ifstat
);
2493 /* For more details see the hardware spec. */
2494 out_be32(&ug_regs
->uempr
, 0);
2497 /* For more details see the hardware spec. */
2498 init_hw_statistics_gathering_mode((ug_info
->statisticsMode
&
2499 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
),
2500 0, &uf_regs
->upsmr
, &ug_regs
->uescr
);
2502 ret_val
= ucc_geth_alloc_tx(ugeth
);
2506 ret_val
= ucc_geth_alloc_rx(ugeth
);
2513 /* Tx global PRAM */
2514 /* Allocate global tx parameter RAM page */
2515 ugeth
->tx_glbl_pram_offset
=
2516 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram
),
2517 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT
);
2518 if (IS_ERR_VALUE(ugeth
->tx_glbl_pram_offset
)) {
2519 if (netif_msg_ifup(ugeth
))
2520 pr_err("Can not allocate DPRAM memory for p_tx_glbl_pram\n");
2523 ugeth
->p_tx_glbl_pram
=
2524 (struct ucc_geth_tx_global_pram __iomem
*) qe_muram_addr(ugeth
->
2525 tx_glbl_pram_offset
);
2526 /* Zero out p_tx_glbl_pram */
2527 memset_io((void __iomem
*)ugeth
->p_tx_glbl_pram
, 0, sizeof(struct ucc_geth_tx_global_pram
));
2529 /* Fill global PRAM */
2532 /* Size varies with number of Tx threads */
2533 ugeth
->thread_dat_tx_offset
=
2534 qe_muram_alloc(numThreadsTxNumerical
*
2535 sizeof(struct ucc_geth_thread_data_tx
) +
2536 32 * (numThreadsTxNumerical
== 1),
2537 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2538 if (IS_ERR_VALUE(ugeth
->thread_dat_tx_offset
)) {
2539 if (netif_msg_ifup(ugeth
))
2540 pr_err("Can not allocate DPRAM memory for p_thread_data_tx\n");
2544 ugeth
->p_thread_data_tx
=
2545 (struct ucc_geth_thread_data_tx __iomem
*) qe_muram_addr(ugeth
->
2546 thread_dat_tx_offset
);
2547 out_be32(&ugeth
->p_tx_glbl_pram
->tqptr
, ugeth
->thread_dat_tx_offset
);
2550 for (i
= 0; i
< UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX
; i
++)
2551 out_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[i
],
2552 ug_info
->vtagtable
[i
]);
2555 for (i
= 0; i
< TX_IP_OFFSET_ENTRY_MAX
; i
++)
2556 out_8(&ugeth
->p_tx_glbl_pram
->iphoffset
[i
],
2557 ug_info
->iphoffset
[i
]);
2560 /* Size varies with number of Tx queues */
2561 ugeth
->send_q_mem_reg_offset
=
2562 qe_muram_alloc(ug_info
->numQueuesTx
*
2563 sizeof(struct ucc_geth_send_queue_qd
),
2564 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
);
2565 if (IS_ERR_VALUE(ugeth
->send_q_mem_reg_offset
)) {
2566 if (netif_msg_ifup(ugeth
))
2567 pr_err("Can not allocate DPRAM memory for p_send_q_mem_reg\n");
2571 ugeth
->p_send_q_mem_reg
=
2572 (struct ucc_geth_send_queue_mem_region __iomem
*) qe_muram_addr(ugeth
->
2573 send_q_mem_reg_offset
);
2574 out_be32(&ugeth
->p_tx_glbl_pram
->sqptr
, ugeth
->send_q_mem_reg_offset
);
2576 /* Setup the table */
2577 /* Assume BD rings are already established */
2578 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2580 ugeth
->p_tx_bd_ring
[i
] + (ug_info
->bdRingLenTx
[i
] -
2581 1) * sizeof(struct qe_bd
);
2582 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2583 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2584 (u32
) virt_to_phys(ugeth
->p_tx_bd_ring
[i
]));
2585 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2586 last_bd_completed_address
,
2587 (u32
) virt_to_phys(endOfRing
));
2588 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2590 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2591 (u32
) immrbar_virt_to_phys(ugeth
->
2593 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2594 last_bd_completed_address
,
2595 (u32
) immrbar_virt_to_phys(endOfRing
));
2599 /* schedulerbasepointer */
2601 if (ug_info
->numQueuesTx
> 1) {
2602 /* scheduler exists only if more than 1 tx queue */
2603 ugeth
->scheduler_offset
=
2604 qe_muram_alloc(sizeof(struct ucc_geth_scheduler
),
2605 UCC_GETH_SCHEDULER_ALIGNMENT
);
2606 if (IS_ERR_VALUE(ugeth
->scheduler_offset
)) {
2607 if (netif_msg_ifup(ugeth
))
2608 pr_err("Can not allocate DPRAM memory for p_scheduler\n");
2612 ugeth
->p_scheduler
=
2613 (struct ucc_geth_scheduler __iomem
*) qe_muram_addr(ugeth
->
2615 out_be32(&ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
2616 ugeth
->scheduler_offset
);
2617 /* Zero out p_scheduler */
2618 memset_io((void __iomem
*)ugeth
->p_scheduler
, 0, sizeof(struct ucc_geth_scheduler
));
2620 /* Set values in scheduler */
2621 out_be32(&ugeth
->p_scheduler
->mblinterval
,
2622 ug_info
->mblinterval
);
2623 out_be16(&ugeth
->p_scheduler
->nortsrbytetime
,
2624 ug_info
->nortsrbytetime
);
2625 out_8(&ugeth
->p_scheduler
->fracsiz
, ug_info
->fracsiz
);
2626 out_8(&ugeth
->p_scheduler
->strictpriorityq
,
2627 ug_info
->strictpriorityq
);
2628 out_8(&ugeth
->p_scheduler
->txasap
, ug_info
->txasap
);
2629 out_8(&ugeth
->p_scheduler
->extrabw
, ug_info
->extrabw
);
2630 for (i
= 0; i
< NUM_TX_QUEUES
; i
++)
2631 out_8(&ugeth
->p_scheduler
->weightfactor
[i
],
2632 ug_info
->weightfactor
[i
]);
2634 /* Set pointers to cpucount registers in scheduler */
2635 ugeth
->p_cpucount
[0] = &(ugeth
->p_scheduler
->cpucount0
);
2636 ugeth
->p_cpucount
[1] = &(ugeth
->p_scheduler
->cpucount1
);
2637 ugeth
->p_cpucount
[2] = &(ugeth
->p_scheduler
->cpucount2
);
2638 ugeth
->p_cpucount
[3] = &(ugeth
->p_scheduler
->cpucount3
);
2639 ugeth
->p_cpucount
[4] = &(ugeth
->p_scheduler
->cpucount4
);
2640 ugeth
->p_cpucount
[5] = &(ugeth
->p_scheduler
->cpucount5
);
2641 ugeth
->p_cpucount
[6] = &(ugeth
->p_scheduler
->cpucount6
);
2642 ugeth
->p_cpucount
[7] = &(ugeth
->p_scheduler
->cpucount7
);
2645 /* schedulerbasepointer */
2646 /* TxRMON_PTR (statistics) */
2648 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
) {
2649 ugeth
->tx_fw_statistics_pram_offset
=
2650 qe_muram_alloc(sizeof
2651 (struct ucc_geth_tx_firmware_statistics_pram
),
2652 UCC_GETH_TX_STATISTICS_ALIGNMENT
);
2653 if (IS_ERR_VALUE(ugeth
->tx_fw_statistics_pram_offset
)) {
2654 if (netif_msg_ifup(ugeth
))
2655 pr_err("Can not allocate DPRAM memory for p_tx_fw_statistics_pram\n");
2658 ugeth
->p_tx_fw_statistics_pram
=
2659 (struct ucc_geth_tx_firmware_statistics_pram __iomem
*)
2660 qe_muram_addr(ugeth
->tx_fw_statistics_pram_offset
);
2661 /* Zero out p_tx_fw_statistics_pram */
2662 memset_io((void __iomem
*)ugeth
->p_tx_fw_statistics_pram
,
2663 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram
));
2667 /* Already has speed set */
2669 if (ug_info
->numQueuesTx
> 1)
2670 temoder
|= TEMODER_SCHEDULER_ENABLE
;
2671 if (ug_info
->ipCheckSumGenerate
)
2672 temoder
|= TEMODER_IP_CHECKSUM_GENERATE
;
2673 temoder
|= ((ug_info
->numQueuesTx
- 1) << TEMODER_NUM_OF_QUEUES_SHIFT
);
2674 out_be16(&ugeth
->p_tx_glbl_pram
->temoder
, temoder
);
2676 test
= in_be16(&ugeth
->p_tx_glbl_pram
->temoder
);
2678 /* Function code register value to be used later */
2679 function_code
= UCC_BMR_BO_BE
| UCC_BMR_GBL
;
2680 /* Required for QE */
2682 /* function code register */
2683 out_be32(&ugeth
->p_tx_glbl_pram
->tstate
, ((u32
) function_code
) << 24);
2685 /* Rx global PRAM */
2686 /* Allocate global rx parameter RAM page */
2687 ugeth
->rx_glbl_pram_offset
=
2688 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram
),
2689 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT
);
2690 if (IS_ERR_VALUE(ugeth
->rx_glbl_pram_offset
)) {
2691 if (netif_msg_ifup(ugeth
))
2692 pr_err("Can not allocate DPRAM memory for p_rx_glbl_pram\n");
2695 ugeth
->p_rx_glbl_pram
=
2696 (struct ucc_geth_rx_global_pram __iomem
*) qe_muram_addr(ugeth
->
2697 rx_glbl_pram_offset
);
2698 /* Zero out p_rx_glbl_pram */
2699 memset_io((void __iomem
*)ugeth
->p_rx_glbl_pram
, 0, sizeof(struct ucc_geth_rx_global_pram
));
2701 /* Fill global PRAM */
2704 /* Size varies with number of Rx threads */
2705 ugeth
->thread_dat_rx_offset
=
2706 qe_muram_alloc(numThreadsRxNumerical
*
2707 sizeof(struct ucc_geth_thread_data_rx
),
2708 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2709 if (IS_ERR_VALUE(ugeth
->thread_dat_rx_offset
)) {
2710 if (netif_msg_ifup(ugeth
))
2711 pr_err("Can not allocate DPRAM memory for p_thread_data_rx\n");
2715 ugeth
->p_thread_data_rx
=
2716 (struct ucc_geth_thread_data_rx __iomem
*) qe_muram_addr(ugeth
->
2717 thread_dat_rx_offset
);
2718 out_be32(&ugeth
->p_rx_glbl_pram
->rqptr
, ugeth
->thread_dat_rx_offset
);
2721 out_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
, ug_info
->typeorlen
);
2723 /* rxrmonbaseptr (statistics) */
2725 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
) {
2726 ugeth
->rx_fw_statistics_pram_offset
=
2727 qe_muram_alloc(sizeof
2728 (struct ucc_geth_rx_firmware_statistics_pram
),
2729 UCC_GETH_RX_STATISTICS_ALIGNMENT
);
2730 if (IS_ERR_VALUE(ugeth
->rx_fw_statistics_pram_offset
)) {
2731 if (netif_msg_ifup(ugeth
))
2732 pr_err("Can not allocate DPRAM memory for p_rx_fw_statistics_pram\n");
2735 ugeth
->p_rx_fw_statistics_pram
=
2736 (struct ucc_geth_rx_firmware_statistics_pram __iomem
*)
2737 qe_muram_addr(ugeth
->rx_fw_statistics_pram_offset
);
2738 /* Zero out p_rx_fw_statistics_pram */
2739 memset_io((void __iomem
*)ugeth
->p_rx_fw_statistics_pram
, 0,
2740 sizeof(struct ucc_geth_rx_firmware_statistics_pram
));
2743 /* intCoalescingPtr */
2745 /* Size varies with number of Rx queues */
2746 ugeth
->rx_irq_coalescing_tbl_offset
=
2747 qe_muram_alloc(ug_info
->numQueuesRx
*
2748 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry
)
2749 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT
);
2750 if (IS_ERR_VALUE(ugeth
->rx_irq_coalescing_tbl_offset
)) {
2751 if (netif_msg_ifup(ugeth
))
2752 pr_err("Can not allocate DPRAM memory for p_rx_irq_coalescing_tbl\n");
2756 ugeth
->p_rx_irq_coalescing_tbl
=
2757 (struct ucc_geth_rx_interrupt_coalescing_table __iomem
*)
2758 qe_muram_addr(ugeth
->rx_irq_coalescing_tbl_offset
);
2759 out_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
2760 ugeth
->rx_irq_coalescing_tbl_offset
);
2762 /* Fill interrupt coalescing table */
2763 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2764 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
2765 interruptcoalescingmaxvalue
,
2766 ug_info
->interruptcoalescingmaxvalue
[i
]);
2767 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
2768 interruptcoalescingcounter
,
2769 ug_info
->interruptcoalescingmaxvalue
[i
]);
2773 init_max_rx_buff_len(uf_info
->max_rx_buf_length
,
2774 &ugeth
->p_rx_glbl_pram
->mrblr
);
2776 out_be16(&ugeth
->p_rx_glbl_pram
->mflr
, ug_info
->maxFrameLength
);
2778 init_min_frame_len(ug_info
->minFrameLength
,
2779 &ugeth
->p_rx_glbl_pram
->minflr
,
2780 &ugeth
->p_rx_glbl_pram
->mrblr
);
2782 out_be16(&ugeth
->p_rx_glbl_pram
->maxd1
, ug_info
->maxD1Length
);
2784 out_be16(&ugeth
->p_rx_glbl_pram
->maxd2
, ug_info
->maxD2Length
);
2788 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++)
2789 l2qt
|= (ug_info
->l2qt
[i
] << (28 - 4 * i
));
2790 out_be32(&ugeth
->p_rx_glbl_pram
->l2qt
, l2qt
);
2793 for (j
= 0; j
< UCC_GETH_IP_PRIORITY_MAX
; j
+= 8) {
2795 for (i
= 0; i
< 8; i
++)
2796 l3qt
|= (ug_info
->l3qt
[j
+ i
] << (28 - 4 * i
));
2797 out_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[j
/8], l3qt
);
2801 out_be16(&ugeth
->p_rx_glbl_pram
->vlantype
, ug_info
->vlantype
);
2804 out_be16(&ugeth
->p_rx_glbl_pram
->vlantci
, ug_info
->vlantci
);
2807 out_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
, ug_info
->ecamptr
);
2810 /* Size varies with number of Rx queues */
2811 ugeth
->rx_bd_qs_tbl_offset
=
2812 qe_muram_alloc(ug_info
->numQueuesRx
*
2813 (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
2814 sizeof(struct ucc_geth_rx_prefetched_bds
)),
2815 UCC_GETH_RX_BD_QUEUES_ALIGNMENT
);
2816 if (IS_ERR_VALUE(ugeth
->rx_bd_qs_tbl_offset
)) {
2817 if (netif_msg_ifup(ugeth
))
2818 pr_err("Can not allocate DPRAM memory for p_rx_bd_qs_tbl\n");
2822 ugeth
->p_rx_bd_qs_tbl
=
2823 (struct ucc_geth_rx_bd_queues_entry __iomem
*) qe_muram_addr(ugeth
->
2824 rx_bd_qs_tbl_offset
);
2825 out_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
, ugeth
->rx_bd_qs_tbl_offset
);
2826 /* Zero out p_rx_bd_qs_tbl */
2827 memset_io((void __iomem
*)ugeth
->p_rx_bd_qs_tbl
,
2829 ug_info
->numQueuesRx
* (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
2830 sizeof(struct ucc_geth_rx_prefetched_bds
)));
2832 /* Setup the table */
2833 /* Assume BD rings are already established */
2834 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2835 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2836 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
2837 (u32
) virt_to_phys(ugeth
->p_rx_bd_ring
[i
]));
2838 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2840 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
2841 (u32
) immrbar_virt_to_phys(ugeth
->
2844 /* rest of fields handled by QE */
2848 /* Already has speed set */
2850 if (ugeth
->rx_extended_features
)
2851 remoder
|= REMODER_RX_EXTENDED_FEATURES
;
2852 if (ug_info
->rxExtendedFiltering
)
2853 remoder
|= REMODER_RX_EXTENDED_FILTERING
;
2854 if (ug_info
->dynamicMaxFrameLength
)
2855 remoder
|= REMODER_DYNAMIC_MAX_FRAME_LENGTH
;
2856 if (ug_info
->dynamicMinFrameLength
)
2857 remoder
|= REMODER_DYNAMIC_MIN_FRAME_LENGTH
;
2859 ug_info
->vlanOperationTagged
<< REMODER_VLAN_OPERATION_TAGGED_SHIFT
;
2862 vlanOperationNonTagged
<< REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT
;
2863 remoder
|= ug_info
->rxQoSMode
<< REMODER_RX_QOS_MODE_SHIFT
;
2864 remoder
|= ((ug_info
->numQueuesRx
- 1) << REMODER_NUM_OF_QUEUES_SHIFT
);
2865 if (ug_info
->ipCheckSumCheck
)
2866 remoder
|= REMODER_IP_CHECKSUM_CHECK
;
2867 if (ug_info
->ipAddressAlignment
)
2868 remoder
|= REMODER_IP_ADDRESS_ALIGNMENT
;
2869 out_be32(&ugeth
->p_rx_glbl_pram
->remoder
, remoder
);
2871 /* Note that this function must be called */
2872 /* ONLY AFTER p_tx_fw_statistics_pram */
2873 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2874 init_firmware_statistics_gathering_mode((ug_info
->
2876 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
),
2877 (ug_info
->statisticsMode
&
2878 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
),
2879 &ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
2880 ugeth
->tx_fw_statistics_pram_offset
,
2881 &ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
2882 ugeth
->rx_fw_statistics_pram_offset
,
2883 &ugeth
->p_tx_glbl_pram
->temoder
,
2884 &ugeth
->p_rx_glbl_pram
->remoder
);
2886 /* function code register */
2887 out_8(&ugeth
->p_rx_glbl_pram
->rstate
, function_code
);
2889 /* initialize extended filtering */
2890 if (ug_info
->rxExtendedFiltering
) {
2891 if (!ug_info
->extendedFilteringChainPointer
) {
2892 if (netif_msg_ifup(ugeth
))
2893 pr_err("Null Extended Filtering Chain Pointer\n");
2897 /* Allocate memory for extended filtering Mode Global
2899 ugeth
->exf_glbl_param_offset
=
2900 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram
),
2901 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT
);
2902 if (IS_ERR_VALUE(ugeth
->exf_glbl_param_offset
)) {
2903 if (netif_msg_ifup(ugeth
))
2904 pr_err("Can not allocate DPRAM memory for p_exf_glbl_param\n");
2908 ugeth
->p_exf_glbl_param
=
2909 (struct ucc_geth_exf_global_pram __iomem
*) qe_muram_addr(ugeth
->
2910 exf_glbl_param_offset
);
2911 out_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
2912 ugeth
->exf_glbl_param_offset
);
2913 out_be32(&ugeth
->p_exf_glbl_param
->l2pcdptr
,
2914 (u32
) ug_info
->extendedFilteringChainPointer
);
2916 } else { /* initialize 82xx style address filtering */
2918 /* Init individual address recognition registers to disabled */
2920 for (j
= 0; j
< NUM_OF_PADDRS
; j
++)
2921 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth
, (u8
) j
);
2924 (struct ucc_geth_82xx_address_filtering_pram __iomem
*) ugeth
->
2925 p_rx_glbl_pram
->addressfiltering
;
2927 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
2928 ENET_ADDR_TYPE_GROUP
);
2929 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
2930 ENET_ADDR_TYPE_INDIVIDUAL
);
2934 * Initialize UCC at QE level
2937 command
= QE_INIT_TX_RX
;
2939 /* Allocate shadow InitEnet command parameter structure.
2940 * This is needed because after the InitEnet command is executed,
2941 * the structure in DPRAM is released, because DPRAM is a premium
2943 * This shadow structure keeps a copy of what was done so that the
2944 * allocated resources can be released when the channel is freed.
2946 if (!(ugeth
->p_init_enet_param_shadow
=
2947 kmalloc(sizeof(struct ucc_geth_init_pram
), GFP_KERNEL
))) {
2948 if (netif_msg_ifup(ugeth
))
2949 pr_err("Can not allocate memory for p_UccInitEnetParamShadows\n");
2952 /* Zero out *p_init_enet_param_shadow */
2953 memset((char *)ugeth
->p_init_enet_param_shadow
,
2954 0, sizeof(struct ucc_geth_init_pram
));
2956 /* Fill shadow InitEnet command parameter structure */
2958 ugeth
->p_init_enet_param_shadow
->resinit1
=
2959 ENET_INIT_PARAM_MAGIC_RES_INIT1
;
2960 ugeth
->p_init_enet_param_shadow
->resinit2
=
2961 ENET_INIT_PARAM_MAGIC_RES_INIT2
;
2962 ugeth
->p_init_enet_param_shadow
->resinit3
=
2963 ENET_INIT_PARAM_MAGIC_RES_INIT3
;
2964 ugeth
->p_init_enet_param_shadow
->resinit4
=
2965 ENET_INIT_PARAM_MAGIC_RES_INIT4
;
2966 ugeth
->p_init_enet_param_shadow
->resinit5
=
2967 ENET_INIT_PARAM_MAGIC_RES_INIT5
;
2968 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2969 ((u32
) ug_info
->numThreadsRx
) << ENET_INIT_PARAM_RGF_SHIFT
;
2970 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2971 ((u32
) ug_info
->numThreadsTx
) << ENET_INIT_PARAM_TGF_SHIFT
;
2973 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
2974 ugeth
->rx_glbl_pram_offset
| ug_info
->riscRx
;
2975 if ((ug_info
->largestexternallookupkeysize
!=
2976 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
) &&
2977 (ug_info
->largestexternallookupkeysize
!=
2978 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
) &&
2979 (ug_info
->largestexternallookupkeysize
!=
2980 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)) {
2981 if (netif_msg_ifup(ugeth
))
2982 pr_err("Invalid largest External Lookup Key Size\n");
2985 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
=
2986 ug_info
->largestexternallookupkeysize
;
2987 size
= sizeof(struct ucc_geth_thread_rx_pram
);
2988 if (ug_info
->rxExtendedFiltering
) {
2989 size
+= THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
2990 if (ug_info
->largestexternallookupkeysize
==
2991 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
2993 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
2994 if (ug_info
->largestexternallookupkeysize
==
2995 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
2997 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
3000 if ((ret_val
= fill_init_enet_entries(ugeth
, &(ugeth
->
3001 p_init_enet_param_shadow
->rxthread
[0]),
3002 (u8
) (numThreadsRxNumerical
+ 1)
3003 /* Rx needs one extra for terminator */
3004 , size
, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT
,
3005 ug_info
->riscRx
, 1)) != 0) {
3006 if (netif_msg_ifup(ugeth
))
3007 pr_err("Can not fill p_init_enet_param_shadow\n");
3011 ugeth
->p_init_enet_param_shadow
->txglobal
=
3012 ugeth
->tx_glbl_pram_offset
| ug_info
->riscTx
;
3014 fill_init_enet_entries(ugeth
,
3015 &(ugeth
->p_init_enet_param_shadow
->
3016 txthread
[0]), numThreadsTxNumerical
,
3017 sizeof(struct ucc_geth_thread_tx_pram
),
3018 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT
,
3019 ug_info
->riscTx
, 0)) != 0) {
3020 if (netif_msg_ifup(ugeth
))
3021 pr_err("Can not fill p_init_enet_param_shadow\n");
3025 /* Load Rx bds with buffers */
3026 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3027 if ((ret_val
= rx_bd_buffer_set(ugeth
, (u8
) i
)) != 0) {
3028 if (netif_msg_ifup(ugeth
))
3029 pr_err("Can not fill Rx bds with buffers\n");
3034 /* Allocate InitEnet command parameter structure */
3035 init_enet_pram_offset
= qe_muram_alloc(sizeof(struct ucc_geth_init_pram
), 4);
3036 if (IS_ERR_VALUE(init_enet_pram_offset
)) {
3037 if (netif_msg_ifup(ugeth
))
3038 pr_err("Can not allocate DPRAM memory for p_init_enet_pram\n");
3042 (struct ucc_geth_init_pram __iomem
*) qe_muram_addr(init_enet_pram_offset
);
3044 /* Copy shadow InitEnet command parameter structure into PRAM */
3045 out_8(&p_init_enet_pram
->resinit1
,
3046 ugeth
->p_init_enet_param_shadow
->resinit1
);
3047 out_8(&p_init_enet_pram
->resinit2
,
3048 ugeth
->p_init_enet_param_shadow
->resinit2
);
3049 out_8(&p_init_enet_pram
->resinit3
,
3050 ugeth
->p_init_enet_param_shadow
->resinit3
);
3051 out_8(&p_init_enet_pram
->resinit4
,
3052 ugeth
->p_init_enet_param_shadow
->resinit4
);
3053 out_be16(&p_init_enet_pram
->resinit5
,
3054 ugeth
->p_init_enet_param_shadow
->resinit5
);
3055 out_8(&p_init_enet_pram
->largestexternallookupkeysize
,
3056 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
);
3057 out_be32(&p_init_enet_pram
->rgftgfrxglobal
,
3058 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
);
3059 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_RX
; i
++)
3060 out_be32(&p_init_enet_pram
->rxthread
[i
],
3061 ugeth
->p_init_enet_param_shadow
->rxthread
[i
]);
3062 out_be32(&p_init_enet_pram
->txglobal
,
3063 ugeth
->p_init_enet_param_shadow
->txglobal
);
3064 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_TX
; i
++)
3065 out_be32(&p_init_enet_pram
->txthread
[i
],
3066 ugeth
->p_init_enet_param_shadow
->txthread
[i
]);
3068 /* Issue QE command */
3070 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
3071 qe_issue_cmd(command
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
3072 init_enet_pram_offset
);
3074 /* Free InitEnet command parameter */
3075 qe_muram_free(init_enet_pram_offset
);
3080 /* This is called by the kernel when a frame is ready for transmission. */
3081 /* It is pointed to by the dev->hard_start_xmit function pointer */
3082 static int ucc_geth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3084 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3085 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3086 struct ucc_fast_private
*uccf
;
3088 u8 __iomem
*bd
; /* BD pointer */
3091 unsigned long flags
;
3093 ugeth_vdbg("%s: IN", __func__
);
3095 spin_lock_irqsave(&ugeth
->lock
, flags
);
3097 dev
->stats
.tx_bytes
+= skb
->len
;
3099 /* Start from the next BD that should be filled */
3100 bd
= ugeth
->txBd
[txQ
];
3101 bd_status
= in_be32((u32 __iomem
*)bd
);
3102 /* Save the skb pointer so we can free it later */
3103 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_curtx
[txQ
]] = skb
;
3105 /* Update the current skb pointer (wrapping if this was the last) */
3106 ugeth
->skb_curtx
[txQ
] =
3107 (ugeth
->skb_curtx
[txQ
] +
3108 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3110 /* set up the buffer descriptor */
3111 out_be32(&((struct qe_bd __iomem
*)bd
)->buf
,
3112 dma_map_single(ugeth
->dev
, skb
->data
,
3113 skb
->len
, DMA_TO_DEVICE
));
3115 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3117 bd_status
= (bd_status
& T_W
) | T_R
| T_I
| T_L
| skb
->len
;
3119 /* set bd status and length */
3120 out_be32((u32 __iomem
*)bd
, bd_status
);
3122 /* Move to next BD in the ring */
3123 if (!(bd_status
& T_W
))
3124 bd
+= sizeof(struct qe_bd
);
3126 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3128 /* If the next BD still needs to be cleaned up, then the bds
3129 are full. We need to tell the kernel to stop sending us stuff. */
3130 if (bd
== ugeth
->confBd
[txQ
]) {
3131 if (!netif_queue_stopped(dev
))
3132 netif_stop_queue(dev
);
3135 ugeth
->txBd
[txQ
] = bd
;
3137 skb_tx_timestamp(skb
);
3139 if (ugeth
->p_scheduler
) {
3140 ugeth
->cpucount
[txQ
]++;
3141 /* Indicate to QE that there are more Tx bds ready for
3143 /* This is done by writing a running counter of the bd
3144 count to the scheduler PRAM. */
3145 out_be16(ugeth
->p_cpucount
[txQ
], ugeth
->cpucount
[txQ
]);
3148 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3150 out_be16(uccf
->p_utodr
, UCC_FAST_TOD
);
3152 spin_unlock_irqrestore(&ugeth
->lock
, flags
);
3154 return NETDEV_TX_OK
;
3157 static int ucc_geth_rx(struct ucc_geth_private
*ugeth
, u8 rxQ
, int rx_work_limit
)
3159 struct sk_buff
*skb
;
3161 u16 length
, howmany
= 0;
3164 struct net_device
*dev
;
3166 ugeth_vdbg("%s: IN", __func__
);
3170 /* collect received buffers */
3171 bd
= ugeth
->rxBd
[rxQ
];
3173 bd_status
= in_be32((u32 __iomem
*)bd
);
3175 /* while there are received buffers and BD is full (~R_E) */
3176 while (!((bd_status
& (R_E
)) || (--rx_work_limit
< 0))) {
3177 bdBuffer
= (u8
*) in_be32(&((struct qe_bd __iomem
*)bd
)->buf
);
3178 length
= (u16
) ((bd_status
& BD_LENGTH_MASK
) - 4);
3179 skb
= ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]];
3181 /* determine whether buffer is first, last, first and last
3182 (single buffer frame) or middle (not first and not last) */
3184 (!(bd_status
& (R_F
| R_L
))) ||
3185 (bd_status
& R_ERRORS_FATAL
)) {
3186 if (netif_msg_rx_err(ugeth
))
3187 pr_err("%d: ERROR!!! skb - 0x%08x\n",
3188 __LINE__
, (u32
)skb
);
3191 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = NULL
;
3192 dev
->stats
.rx_dropped
++;
3194 dev
->stats
.rx_packets
++;
3197 /* Prep the skb for the packet */
3198 skb_put(skb
, length
);
3200 /* Tell the skb what kind of packet this is */
3201 skb
->protocol
= eth_type_trans(skb
, ugeth
->ndev
);
3203 dev
->stats
.rx_bytes
+= length
;
3204 /* Send the packet up the stack */
3205 netif_receive_skb(skb
);
3208 skb
= get_new_skb(ugeth
, bd
);
3210 if (netif_msg_rx_err(ugeth
))
3211 pr_warn("No Rx Data Buffer\n");
3212 dev
->stats
.rx_dropped
++;
3216 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = skb
;
3218 /* update to point at the next skb */
3219 ugeth
->skb_currx
[rxQ
] =
3220 (ugeth
->skb_currx
[rxQ
] +
3221 1) & RX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenRx
[rxQ
]);
3223 if (bd_status
& R_W
)
3224 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
3226 bd
+= sizeof(struct qe_bd
);
3228 bd_status
= in_be32((u32 __iomem
*)bd
);
3231 ugeth
->rxBd
[rxQ
] = bd
;
3235 static int ucc_geth_tx(struct net_device
*dev
, u8 txQ
)
3237 /* Start from the next BD that should be filled */
3238 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3239 u8 __iomem
*bd
; /* BD pointer */
3242 bd
= ugeth
->confBd
[txQ
];
3243 bd_status
= in_be32((u32 __iomem
*)bd
);
3245 /* Normal processing. */
3246 while ((bd_status
& T_R
) == 0) {
3247 struct sk_buff
*skb
;
3249 /* BD contains already transmitted buffer. */
3250 /* Handle the transmitted buffer and release */
3251 /* the BD to be used with the current frame */
3253 skb
= ugeth
->tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]];
3257 dev
->stats
.tx_packets
++;
3259 dev_consume_skb_any(skb
);
3261 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]] = NULL
;
3262 ugeth
->skb_dirtytx
[txQ
] =
3263 (ugeth
->skb_dirtytx
[txQ
] +
3264 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3266 /* We freed a buffer, so now we can restart transmission */
3267 if (netif_queue_stopped(dev
))
3268 netif_wake_queue(dev
);
3270 /* Advance the confirmation BD pointer */
3271 if (!(bd_status
& T_W
))
3272 bd
+= sizeof(struct qe_bd
);
3274 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3275 bd_status
= in_be32((u32 __iomem
*)bd
);
3277 ugeth
->confBd
[txQ
] = bd
;
3281 static int ucc_geth_poll(struct napi_struct
*napi
, int budget
)
3283 struct ucc_geth_private
*ugeth
= container_of(napi
, struct ucc_geth_private
, napi
);
3284 struct ucc_geth_info
*ug_info
;
3287 ug_info
= ugeth
->ug_info
;
3289 /* Tx event processing */
3290 spin_lock(&ugeth
->lock
);
3291 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++)
3292 ucc_geth_tx(ugeth
->ndev
, i
);
3293 spin_unlock(&ugeth
->lock
);
3296 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
3297 howmany
+= ucc_geth_rx(ugeth
, i
, budget
- howmany
);
3299 if (howmany
< budget
) {
3300 napi_complete(napi
);
3301 setbits32(ugeth
->uccf
->p_uccm
, UCCE_RX_EVENTS
| UCCE_TX_EVENTS
);
3307 static irqreturn_t
ucc_geth_irq_handler(int irq
, void *info
)
3309 struct net_device
*dev
= info
;
3310 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3311 struct ucc_fast_private
*uccf
;
3312 struct ucc_geth_info
*ug_info
;
3316 ugeth_vdbg("%s: IN", __func__
);
3319 ug_info
= ugeth
->ug_info
;
3321 /* read and clear events */
3322 ucce
= (u32
) in_be32(uccf
->p_ucce
);
3323 uccm
= (u32
) in_be32(uccf
->p_uccm
);
3325 out_be32(uccf
->p_ucce
, ucce
);
3327 /* check for receive events that require processing */
3328 if (ucce
& (UCCE_RX_EVENTS
| UCCE_TX_EVENTS
)) {
3329 if (napi_schedule_prep(&ugeth
->napi
)) {
3330 uccm
&= ~(UCCE_RX_EVENTS
| UCCE_TX_EVENTS
);
3331 out_be32(uccf
->p_uccm
, uccm
);
3332 __napi_schedule(&ugeth
->napi
);
3336 /* Errors and other events */
3337 if (ucce
& UCCE_OTHER
) {
3338 if (ucce
& UCC_GETH_UCCE_BSY
)
3339 dev
->stats
.rx_errors
++;
3340 if (ucce
& UCC_GETH_UCCE_TXE
)
3341 dev
->stats
.tx_errors
++;
3347 #ifdef CONFIG_NET_POLL_CONTROLLER
3349 * Polling 'interrupt' - used by things like netconsole to send skbs
3350 * without having to re-enable interrupts. It's not called while
3351 * the interrupt routine is executing.
3353 static void ucc_netpoll(struct net_device
*dev
)
3355 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3356 int irq
= ugeth
->ug_info
->uf_info
.irq
;
3359 ucc_geth_irq_handler(irq
, dev
);
3362 #endif /* CONFIG_NET_POLL_CONTROLLER */
3364 static int ucc_geth_set_mac_addr(struct net_device
*dev
, void *p
)
3366 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3367 struct sockaddr
*addr
= p
;
3369 if (!is_valid_ether_addr(addr
->sa_data
))
3370 return -EADDRNOTAVAIL
;
3372 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3375 * If device is not running, we will set mac addr register
3376 * when opening the device.
3378 if (!netif_running(dev
))
3381 spin_lock_irq(&ugeth
->lock
);
3382 init_mac_station_addr_regs(dev
->dev_addr
[0],
3388 &ugeth
->ug_regs
->macstnaddr1
,
3389 &ugeth
->ug_regs
->macstnaddr2
);
3390 spin_unlock_irq(&ugeth
->lock
);
3395 static int ucc_geth_init_mac(struct ucc_geth_private
*ugeth
)
3397 struct net_device
*dev
= ugeth
->ndev
;
3400 err
= ucc_struct_init(ugeth
);
3402 netif_err(ugeth
, ifup
, dev
, "Cannot configure internal struct, aborting\n");
3406 err
= ucc_geth_startup(ugeth
);
3408 netif_err(ugeth
, ifup
, dev
, "Cannot configure net device, aborting\n");
3412 err
= adjust_enet_interface(ugeth
);
3414 netif_err(ugeth
, ifup
, dev
, "Cannot configure net device, aborting\n");
3418 /* Set MACSTNADDR1, MACSTNADDR2 */
3419 /* For more details see the hardware spec. */
3420 init_mac_station_addr_regs(dev
->dev_addr
[0],
3426 &ugeth
->ug_regs
->macstnaddr1
,
3427 &ugeth
->ug_regs
->macstnaddr2
);
3429 err
= ugeth_enable(ugeth
, COMM_DIR_RX_AND_TX
);
3431 netif_err(ugeth
, ifup
, dev
, "Cannot enable net device, aborting\n");
3437 ucc_geth_stop(ugeth
);
3441 /* Called when something needs to use the ethernet device */
3442 /* Returns 0 for success. */
3443 static int ucc_geth_open(struct net_device
*dev
)
3445 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3448 ugeth_vdbg("%s: IN", __func__
);
3450 /* Test station address */
3451 if (dev
->dev_addr
[0] & ENET_GROUP_ADDR
) {
3452 netif_err(ugeth
, ifup
, dev
,
3453 "Multicast address used for station address - is this what you wanted?\n");
3457 err
= init_phy(dev
);
3459 netif_err(ugeth
, ifup
, dev
, "Cannot initialize PHY, aborting\n");
3463 err
= ucc_geth_init_mac(ugeth
);
3465 netif_err(ugeth
, ifup
, dev
, "Cannot initialize MAC, aborting\n");
3469 err
= request_irq(ugeth
->ug_info
->uf_info
.irq
, ucc_geth_irq_handler
,
3470 0, "UCC Geth", dev
);
3472 netif_err(ugeth
, ifup
, dev
, "Cannot get IRQ for net device, aborting\n");
3476 phy_start(ugeth
->phydev
);
3477 napi_enable(&ugeth
->napi
);
3478 netif_start_queue(dev
);
3480 device_set_wakeup_capable(&dev
->dev
,
3481 qe_alive_during_sleep() || ugeth
->phydev
->irq
);
3482 device_set_wakeup_enable(&dev
->dev
, ugeth
->wol_en
);
3487 ucc_geth_stop(ugeth
);
3491 /* Stops the kernel queue, and halts the controller */
3492 static int ucc_geth_close(struct net_device
*dev
)
3494 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3496 ugeth_vdbg("%s: IN", __func__
);
3498 napi_disable(&ugeth
->napi
);
3500 cancel_work_sync(&ugeth
->timeout_work
);
3501 ucc_geth_stop(ugeth
);
3502 phy_disconnect(ugeth
->phydev
);
3503 ugeth
->phydev
= NULL
;
3505 free_irq(ugeth
->ug_info
->uf_info
.irq
, ugeth
->ndev
);
3507 netif_stop_queue(dev
);
3512 /* Reopen device. This will reset the MAC and PHY. */
3513 static void ucc_geth_timeout_work(struct work_struct
*work
)
3515 struct ucc_geth_private
*ugeth
;
3516 struct net_device
*dev
;
3518 ugeth
= container_of(work
, struct ucc_geth_private
, timeout_work
);
3521 ugeth_vdbg("%s: IN", __func__
);
3523 dev
->stats
.tx_errors
++;
3525 ugeth_dump_regs(ugeth
);
3527 if (dev
->flags
& IFF_UP
) {
3529 * Must reset MAC *and* PHY. This is done by reopening
3532 netif_tx_stop_all_queues(dev
);
3533 ucc_geth_stop(ugeth
);
3534 ucc_geth_init_mac(ugeth
);
3535 /* Must start PHY here */
3536 phy_start(ugeth
->phydev
);
3537 netif_tx_start_all_queues(dev
);
3540 netif_tx_schedule_all(dev
);
3544 * ucc_geth_timeout gets called when a packet has not been
3545 * transmitted after a set amount of time.
3547 static void ucc_geth_timeout(struct net_device
*dev
)
3549 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3551 schedule_work(&ugeth
->timeout_work
);
3557 static int ucc_geth_suspend(struct platform_device
*ofdev
, pm_message_t state
)
3559 struct net_device
*ndev
= platform_get_drvdata(ofdev
);
3560 struct ucc_geth_private
*ugeth
= netdev_priv(ndev
);
3562 if (!netif_running(ndev
))
3565 netif_device_detach(ndev
);
3566 napi_disable(&ugeth
->napi
);
3569 * Disable the controller, otherwise we'll wakeup on any network
3572 ugeth_disable(ugeth
, COMM_DIR_RX_AND_TX
);
3574 if (ugeth
->wol_en
& WAKE_MAGIC
) {
3575 setbits32(ugeth
->uccf
->p_uccm
, UCC_GETH_UCCE_MPD
);
3576 setbits32(&ugeth
->ug_regs
->maccfg2
, MACCFG2_MPE
);
3577 ucc_fast_enable(ugeth
->uccf
, COMM_DIR_RX_AND_TX
);
3578 } else if (!(ugeth
->wol_en
& WAKE_PHY
)) {
3579 phy_stop(ugeth
->phydev
);
3585 static int ucc_geth_resume(struct platform_device
*ofdev
)
3587 struct net_device
*ndev
= platform_get_drvdata(ofdev
);
3588 struct ucc_geth_private
*ugeth
= netdev_priv(ndev
);
3591 if (!netif_running(ndev
))
3594 if (qe_alive_during_sleep()) {
3595 if (ugeth
->wol_en
& WAKE_MAGIC
) {
3596 ucc_fast_disable(ugeth
->uccf
, COMM_DIR_RX_AND_TX
);
3597 clrbits32(&ugeth
->ug_regs
->maccfg2
, MACCFG2_MPE
);
3598 clrbits32(ugeth
->uccf
->p_uccm
, UCC_GETH_UCCE_MPD
);
3600 ugeth_enable(ugeth
, COMM_DIR_RX_AND_TX
);
3603 * Full reinitialization is required if QE shuts down
3606 ucc_geth_memclean(ugeth
);
3608 err
= ucc_geth_init_mac(ugeth
);
3610 netdev_err(ndev
, "Cannot initialize MAC, aborting\n");
3616 ugeth
->oldspeed
= 0;
3617 ugeth
->oldduplex
= -1;
3619 phy_stop(ugeth
->phydev
);
3620 phy_start(ugeth
->phydev
);
3622 napi_enable(&ugeth
->napi
);
3623 netif_device_attach(ndev
);
3629 #define ucc_geth_suspend NULL
3630 #define ucc_geth_resume NULL
3633 static phy_interface_t
to_phy_interface(const char *phy_connection_type
)
3635 if (strcasecmp(phy_connection_type
, "mii") == 0)
3636 return PHY_INTERFACE_MODE_MII
;
3637 if (strcasecmp(phy_connection_type
, "gmii") == 0)
3638 return PHY_INTERFACE_MODE_GMII
;
3639 if (strcasecmp(phy_connection_type
, "tbi") == 0)
3640 return PHY_INTERFACE_MODE_TBI
;
3641 if (strcasecmp(phy_connection_type
, "rmii") == 0)
3642 return PHY_INTERFACE_MODE_RMII
;
3643 if (strcasecmp(phy_connection_type
, "rgmii") == 0)
3644 return PHY_INTERFACE_MODE_RGMII
;
3645 if (strcasecmp(phy_connection_type
, "rgmii-id") == 0)
3646 return PHY_INTERFACE_MODE_RGMII_ID
;
3647 if (strcasecmp(phy_connection_type
, "rgmii-txid") == 0)
3648 return PHY_INTERFACE_MODE_RGMII_TXID
;
3649 if (strcasecmp(phy_connection_type
, "rgmii-rxid") == 0)
3650 return PHY_INTERFACE_MODE_RGMII_RXID
;
3651 if (strcasecmp(phy_connection_type
, "rtbi") == 0)
3652 return PHY_INTERFACE_MODE_RTBI
;
3653 if (strcasecmp(phy_connection_type
, "sgmii") == 0)
3654 return PHY_INTERFACE_MODE_SGMII
;
3656 return PHY_INTERFACE_MODE_MII
;
3659 static int ucc_geth_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
3661 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3663 if (!netif_running(dev
))
3669 return phy_mii_ioctl(ugeth
->phydev
, rq
, cmd
);
3672 static const struct net_device_ops ucc_geth_netdev_ops
= {
3673 .ndo_open
= ucc_geth_open
,
3674 .ndo_stop
= ucc_geth_close
,
3675 .ndo_start_xmit
= ucc_geth_start_xmit
,
3676 .ndo_validate_addr
= eth_validate_addr
,
3677 .ndo_set_mac_address
= ucc_geth_set_mac_addr
,
3678 .ndo_change_mtu
= eth_change_mtu
,
3679 .ndo_set_rx_mode
= ucc_geth_set_multi
,
3680 .ndo_tx_timeout
= ucc_geth_timeout
,
3681 .ndo_do_ioctl
= ucc_geth_ioctl
,
3682 #ifdef CONFIG_NET_POLL_CONTROLLER
3683 .ndo_poll_controller
= ucc_netpoll
,
3687 static int ucc_geth_probe(struct platform_device
* ofdev
)
3689 struct device
*device
= &ofdev
->dev
;
3690 struct device_node
*np
= ofdev
->dev
.of_node
;
3691 struct net_device
*dev
= NULL
;
3692 struct ucc_geth_private
*ugeth
= NULL
;
3693 struct ucc_geth_info
*ug_info
;
3694 struct resource res
;
3695 int err
, ucc_num
, max_speed
= 0;
3696 const unsigned int *prop
;
3698 const void *mac_addr
;
3699 phy_interface_t phy_interface
;
3700 static const int enet_to_speed
[] = {
3701 SPEED_10
, SPEED_10
, SPEED_10
,
3702 SPEED_100
, SPEED_100
, SPEED_100
,
3703 SPEED_1000
, SPEED_1000
, SPEED_1000
, SPEED_1000
,
3705 static const phy_interface_t enet_to_phy_interface
[] = {
3706 PHY_INTERFACE_MODE_MII
, PHY_INTERFACE_MODE_RMII
,
3707 PHY_INTERFACE_MODE_RGMII
, PHY_INTERFACE_MODE_MII
,
3708 PHY_INTERFACE_MODE_RMII
, PHY_INTERFACE_MODE_RGMII
,
3709 PHY_INTERFACE_MODE_GMII
, PHY_INTERFACE_MODE_RGMII
,
3710 PHY_INTERFACE_MODE_TBI
, PHY_INTERFACE_MODE_RTBI
,
3711 PHY_INTERFACE_MODE_SGMII
,
3714 ugeth_vdbg("%s: IN", __func__
);
3716 prop
= of_get_property(np
, "cell-index", NULL
);
3718 prop
= of_get_property(np
, "device-id", NULL
);
3723 ucc_num
= *prop
- 1;
3724 if ((ucc_num
< 0) || (ucc_num
> 7))
3727 ug_info
= &ugeth_info
[ucc_num
];
3728 if (ug_info
== NULL
) {
3729 if (netif_msg_probe(&debug
))
3730 pr_err("[%d] Missing additional data!\n", ucc_num
);
3734 ug_info
->uf_info
.ucc_num
= ucc_num
;
3736 sprop
= of_get_property(np
, "rx-clock-name", NULL
);
3738 ug_info
->uf_info
.rx_clock
= qe_clock_source(sprop
);
3739 if ((ug_info
->uf_info
.rx_clock
< QE_CLK_NONE
) ||
3740 (ug_info
->uf_info
.rx_clock
> QE_CLK24
)) {
3741 pr_err("invalid rx-clock-name property\n");
3745 prop
= of_get_property(np
, "rx-clock", NULL
);
3747 /* If both rx-clock-name and rx-clock are missing,
3748 we want to tell people to use rx-clock-name. */
3749 pr_err("missing rx-clock-name property\n");
3752 if ((*prop
< QE_CLK_NONE
) || (*prop
> QE_CLK24
)) {
3753 pr_err("invalid rx-clock propperty\n");
3756 ug_info
->uf_info
.rx_clock
= *prop
;
3759 sprop
= of_get_property(np
, "tx-clock-name", NULL
);
3761 ug_info
->uf_info
.tx_clock
= qe_clock_source(sprop
);
3762 if ((ug_info
->uf_info
.tx_clock
< QE_CLK_NONE
) ||
3763 (ug_info
->uf_info
.tx_clock
> QE_CLK24
)) {
3764 pr_err("invalid tx-clock-name property\n");
3768 prop
= of_get_property(np
, "tx-clock", NULL
);
3770 pr_err("missing tx-clock-name property\n");
3773 if ((*prop
< QE_CLK_NONE
) || (*prop
> QE_CLK24
)) {
3774 pr_err("invalid tx-clock property\n");
3777 ug_info
->uf_info
.tx_clock
= *prop
;
3780 err
= of_address_to_resource(np
, 0, &res
);
3784 ug_info
->uf_info
.regs
= res
.start
;
3785 ug_info
->uf_info
.irq
= irq_of_parse_and_map(np
, 0);
3787 ug_info
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
3788 if (!ug_info
->phy_node
&& of_phy_is_fixed_link(np
)) {
3790 * In the case of a fixed PHY, the DT node associated
3791 * to the PHY is the Ethernet MAC DT node.
3793 err
= of_phy_register_fixed_link(np
);
3796 ug_info
->phy_node
= of_node_get(np
);
3799 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3800 ug_info
->tbi_node
= of_parse_phandle(np
, "tbi-handle", 0);
3802 /* get the phy interface type, or default to MII */
3803 prop
= of_get_property(np
, "phy-connection-type", NULL
);
3805 /* handle interface property present in old trees */
3806 prop
= of_get_property(ug_info
->phy_node
, "interface", NULL
);
3808 phy_interface
= enet_to_phy_interface
[*prop
];
3809 max_speed
= enet_to_speed
[*prop
];
3811 phy_interface
= PHY_INTERFACE_MODE_MII
;
3813 phy_interface
= to_phy_interface((const char *)prop
);
3816 /* get speed, or derive from PHY interface */
3818 switch (phy_interface
) {
3819 case PHY_INTERFACE_MODE_GMII
:
3820 case PHY_INTERFACE_MODE_RGMII
:
3821 case PHY_INTERFACE_MODE_RGMII_ID
:
3822 case PHY_INTERFACE_MODE_RGMII_RXID
:
3823 case PHY_INTERFACE_MODE_RGMII_TXID
:
3824 case PHY_INTERFACE_MODE_TBI
:
3825 case PHY_INTERFACE_MODE_RTBI
:
3826 case PHY_INTERFACE_MODE_SGMII
:
3827 max_speed
= SPEED_1000
;
3830 max_speed
= SPEED_100
;
3834 if (max_speed
== SPEED_1000
) {
3835 unsigned int snums
= qe_get_num_of_snums();
3837 /* configure muram FIFOs for gigabit operation */
3838 ug_info
->uf_info
.urfs
= UCC_GETH_URFS_GIGA_INIT
;
3839 ug_info
->uf_info
.urfet
= UCC_GETH_URFET_GIGA_INIT
;
3840 ug_info
->uf_info
.urfset
= UCC_GETH_URFSET_GIGA_INIT
;
3841 ug_info
->uf_info
.utfs
= UCC_GETH_UTFS_GIGA_INIT
;
3842 ug_info
->uf_info
.utfet
= UCC_GETH_UTFET_GIGA_INIT
;
3843 ug_info
->uf_info
.utftt
= UCC_GETH_UTFTT_GIGA_INIT
;
3844 ug_info
->numThreadsTx
= UCC_GETH_NUM_OF_THREADS_4
;
3846 /* If QE's snum number is 46/76 which means we need to support
3847 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3848 * more Threads to Rx.
3850 if ((snums
== 76) || (snums
== 46))
3851 ug_info
->numThreadsRx
= UCC_GETH_NUM_OF_THREADS_6
;
3853 ug_info
->numThreadsRx
= UCC_GETH_NUM_OF_THREADS_4
;
3856 if (netif_msg_probe(&debug
))
3857 pr_info("UCC%1d at 0x%8x (irq = %d)\n",
3858 ug_info
->uf_info
.ucc_num
+ 1, ug_info
->uf_info
.regs
,
3859 ug_info
->uf_info
.irq
);
3861 /* Create an ethernet device instance */
3862 dev
= alloc_etherdev(sizeof(*ugeth
));
3865 of_node_put(ug_info
->tbi_node
);
3866 of_node_put(ug_info
->phy_node
);
3870 ugeth
= netdev_priv(dev
);
3871 spin_lock_init(&ugeth
->lock
);
3873 /* Create CQs for hash tables */
3874 INIT_LIST_HEAD(&ugeth
->group_hash_q
);
3875 INIT_LIST_HEAD(&ugeth
->ind_hash_q
);
3877 dev_set_drvdata(device
, dev
);
3879 /* Set the dev->base_addr to the gfar reg region */
3880 dev
->base_addr
= (unsigned long)(ug_info
->uf_info
.regs
);
3882 SET_NETDEV_DEV(dev
, device
);
3884 /* Fill in the dev structure */
3885 uec_set_ethtool_ops(dev
);
3886 dev
->netdev_ops
= &ucc_geth_netdev_ops
;
3887 dev
->watchdog_timeo
= TX_TIMEOUT
;
3888 INIT_WORK(&ugeth
->timeout_work
, ucc_geth_timeout_work
);
3889 netif_napi_add(dev
, &ugeth
->napi
, ucc_geth_poll
, 64);
3892 ugeth
->msg_enable
= netif_msg_init(debug
.msg_enable
, UGETH_MSG_DEFAULT
);
3893 ugeth
->phy_interface
= phy_interface
;
3894 ugeth
->max_speed
= max_speed
;
3896 /* Carrier starts down, phylib will bring it up */
3897 netif_carrier_off(dev
);
3899 err
= register_netdev(dev
);
3901 if (netif_msg_probe(ugeth
))
3902 pr_err("%s: Cannot register net device, aborting\n",
3905 of_node_put(ug_info
->tbi_node
);
3906 of_node_put(ug_info
->phy_node
);
3910 mac_addr
= of_get_mac_address(np
);
3912 memcpy(dev
->dev_addr
, mac_addr
, ETH_ALEN
);
3914 ugeth
->ug_info
= ug_info
;
3915 ugeth
->dev
= device
;
3922 static int ucc_geth_remove(struct platform_device
* ofdev
)
3924 struct net_device
*dev
= platform_get_drvdata(ofdev
);
3925 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3927 unregister_netdev(dev
);
3929 ucc_geth_memclean(ugeth
);
3930 of_node_put(ugeth
->ug_info
->tbi_node
);
3931 of_node_put(ugeth
->ug_info
->phy_node
);
3936 static struct of_device_id ucc_geth_match
[] = {
3939 .compatible
= "ucc_geth",
3944 MODULE_DEVICE_TABLE(of
, ucc_geth_match
);
3946 static struct platform_driver ucc_geth_driver
= {
3949 .of_match_table
= ucc_geth_match
,
3951 .probe
= ucc_geth_probe
,
3952 .remove
= ucc_geth_remove
,
3953 .suspend
= ucc_geth_suspend
,
3954 .resume
= ucc_geth_resume
,
3957 static int __init
ucc_geth_init(void)
3961 if (netif_msg_drv(&debug
))
3962 pr_info(DRV_DESC
"\n");
3963 for (i
= 0; i
< 8; i
++)
3964 memcpy(&(ugeth_info
[i
]), &ugeth_primary_info
,
3965 sizeof(ugeth_primary_info
));
3967 ret
= platform_driver_register(&ucc_geth_driver
);
3972 static void __exit
ucc_geth_exit(void)
3974 platform_driver_unregister(&ucc_geth_driver
);
3977 module_init(ucc_geth_init
);
3978 module_exit(ucc_geth_exit
);
3980 MODULE_AUTHOR("Freescale Semiconductor, Inc");
3981 MODULE_DESCRIPTION(DRV_DESC
);
3982 MODULE_VERSION(DRV_VERSION
);
3983 MODULE_LICENSE("GPL");