1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
30 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
35 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
36 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
37 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
38 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
40 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
42 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
44 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
45 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
46 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
48 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
49 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
51 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
52 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
54 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
55 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
57 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
58 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
59 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
60 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
61 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
62 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
64 /* PHY Specific Control Register 2 (Page 0, Register 26) */
65 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
66 /* 1=Reverse Auto-Negotiation */
68 /* MAC Specific Control Register (Page 2, Register 21) */
69 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
70 #define GG82563_MSCR_TX_CLK_MASK 0x0007
71 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
72 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
73 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
75 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
77 /* DSP Distance Register (Page 5, Register 26) */
78 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
88 /* Max number of times Kumeran read/write should be validated */
89 #define GG82563_MAX_KMRN_RETRY 0x5
91 /* Power Management Control Register (Page 193, Register 20) */
92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
95 /* In-Band Control Register (Page 194, Register 18) */
96 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
98 /* A table for the GG82563 cable length where the range is defined
99 * with a lower bound at "index" and the upper bound at
102 static const u16 e1000_gg82563_cable_length_table
[] = {
103 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
104 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
105 ARRAY_SIZE(e1000_gg82563_cable_length_table)
107 static s32
e1000_setup_copper_link_80003es2lan(struct e1000_hw
*hw
);
108 static s32
e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw
*hw
, u16 mask
);
109 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw
*hw
, u16 mask
);
110 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw
*hw
);
111 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw
*hw
);
112 static s32
e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw
*hw
);
113 static s32
e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw
*hw
, u16 duplex
);
114 static s32
e1000_cfg_on_link_up_80003es2lan(struct e1000_hw
*hw
);
115 static s32
e1000_read_kmrn_reg_80003es2lan(struct e1000_hw
*hw
, u32 offset
,
117 static s32
e1000_write_kmrn_reg_80003es2lan(struct e1000_hw
*hw
, u32 offset
,
119 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw
*hw
);
122 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
123 * @hw: pointer to the HW structure
125 static s32
e1000_init_phy_params_80003es2lan(struct e1000_hw
*hw
)
127 struct e1000_phy_info
*phy
= &hw
->phy
;
130 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
131 phy
->type
= e1000_phy_none
;
134 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
135 phy
->ops
.power_down
= e1000_power_down_phy_copper_80003es2lan
;
139 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
140 phy
->reset_delay_us
= 100;
141 phy
->type
= e1000_phy_gg82563
;
143 /* This can only be done after all function pointers are setup. */
144 ret_val
= e1000e_get_phy_id(hw
);
147 if (phy
->id
!= GG82563_E_PHY_ID
)
148 return -E1000_ERR_PHY
;
154 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
155 * @hw: pointer to the HW structure
157 static s32
e1000_init_nvm_params_80003es2lan(struct e1000_hw
*hw
)
159 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
160 u32 eecd
= er32(EECD
);
163 nvm
->opcode_bits
= 8;
165 switch (nvm
->override
) {
166 case e1000_nvm_override_spi_large
:
168 nvm
->address_bits
= 16;
170 case e1000_nvm_override_spi_small
:
172 nvm
->address_bits
= 8;
175 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
176 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
180 nvm
->type
= e1000_nvm_eeprom_spi
;
182 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
183 E1000_EECD_SIZE_EX_SHIFT
);
185 /* Added to a constant, "size" becomes the left-shift value
186 * for setting word_size.
188 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
190 /* EEPROM access above 16k is unsupported */
193 nvm
->word_size
= 1 << size
;
199 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
200 * @hw: pointer to the HW structure
202 static s32
e1000_init_mac_params_80003es2lan(struct e1000_hw
*hw
)
204 struct e1000_mac_info
*mac
= &hw
->mac
;
206 /* Set media type and media-dependent function pointers */
207 switch (hw
->adapter
->pdev
->device
) {
208 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT
:
209 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
210 mac
->ops
.check_for_link
= e1000e_check_for_serdes_link
;
211 mac
->ops
.setup_physical_interface
=
212 e1000e_setup_fiber_serdes_link
;
215 hw
->phy
.media_type
= e1000_media_type_copper
;
216 mac
->ops
.check_for_link
= e1000e_check_for_copper_link
;
217 mac
->ops
.setup_physical_interface
=
218 e1000_setup_copper_link_80003es2lan
;
222 /* Set mta register count */
223 mac
->mta_reg_count
= 128;
224 /* Set rar entry count */
225 mac
->rar_entry_count
= E1000_RAR_ENTRIES
;
227 mac
->has_fwsm
= true;
228 /* ARC supported; valid only if manageability features are enabled. */
229 mac
->arc_subsystem_valid
= !!(er32(FWSM
) & E1000_FWSM_MODE_MASK
);
230 /* Adaptive IFS not supported */
231 mac
->adaptive_ifs
= false;
233 /* set lan id for port to determine which phy lock to use */
234 hw
->mac
.ops
.set_lan_id(hw
);
239 static s32
e1000_get_variants_80003es2lan(struct e1000_adapter
*adapter
)
241 struct e1000_hw
*hw
= &adapter
->hw
;
244 rc
= e1000_init_mac_params_80003es2lan(hw
);
248 rc
= e1000_init_nvm_params_80003es2lan(hw
);
252 rc
= e1000_init_phy_params_80003es2lan(hw
);
260 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
261 * @hw: pointer to the HW structure
263 * A wrapper to acquire access rights to the correct PHY.
265 static s32
e1000_acquire_phy_80003es2lan(struct e1000_hw
*hw
)
269 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
270 return e1000_acquire_swfw_sync_80003es2lan(hw
, mask
);
274 * e1000_release_phy_80003es2lan - Release rights to access PHY
275 * @hw: pointer to the HW structure
277 * A wrapper to release access rights to the correct PHY.
279 static void e1000_release_phy_80003es2lan(struct e1000_hw
*hw
)
283 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
284 e1000_release_swfw_sync_80003es2lan(hw
, mask
);
288 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
289 * @hw: pointer to the HW structure
291 * Acquire the semaphore to access the Kumeran interface.
294 static s32
e1000_acquire_mac_csr_80003es2lan(struct e1000_hw
*hw
)
298 mask
= E1000_SWFW_CSR_SM
;
300 return e1000_acquire_swfw_sync_80003es2lan(hw
, mask
);
304 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
305 * @hw: pointer to the HW structure
307 * Release the semaphore used to access the Kumeran interface
309 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw
*hw
)
313 mask
= E1000_SWFW_CSR_SM
;
315 e1000_release_swfw_sync_80003es2lan(hw
, mask
);
319 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
320 * @hw: pointer to the HW structure
322 * Acquire the semaphore to access the EEPROM.
324 static s32
e1000_acquire_nvm_80003es2lan(struct e1000_hw
*hw
)
328 ret_val
= e1000_acquire_swfw_sync_80003es2lan(hw
, E1000_SWFW_EEP_SM
);
332 ret_val
= e1000e_acquire_nvm(hw
);
335 e1000_release_swfw_sync_80003es2lan(hw
, E1000_SWFW_EEP_SM
);
341 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
342 * @hw: pointer to the HW structure
344 * Release the semaphore used to access the EEPROM.
346 static void e1000_release_nvm_80003es2lan(struct e1000_hw
*hw
)
348 e1000e_release_nvm(hw
);
349 e1000_release_swfw_sync_80003es2lan(hw
, E1000_SWFW_EEP_SM
);
353 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
354 * @hw: pointer to the HW structure
355 * @mask: specifies which semaphore to acquire
357 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
358 * will also specify which port we're acquiring the lock for.
360 static s32
e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw
*hw
, u16 mask
)
364 u32 fwmask
= mask
<< 16;
368 while (i
< timeout
) {
369 if (e1000e_get_hw_semaphore(hw
))
370 return -E1000_ERR_SWFW_SYNC
;
372 swfw_sync
= er32(SW_FW_SYNC
);
373 if (!(swfw_sync
& (fwmask
| swmask
)))
376 /* Firmware currently using resource (fwmask)
377 * or other software thread using resource (swmask)
379 e1000e_put_hw_semaphore(hw
);
385 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
386 return -E1000_ERR_SWFW_SYNC
;
390 ew32(SW_FW_SYNC
, swfw_sync
);
392 e1000e_put_hw_semaphore(hw
);
398 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
399 * @hw: pointer to the HW structure
400 * @mask: specifies which semaphore to acquire
402 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
403 * will also specify which port we're releasing the lock for.
405 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw
*hw
, u16 mask
)
409 while (e1000e_get_hw_semaphore(hw
) != 0)
412 swfw_sync
= er32(SW_FW_SYNC
);
414 ew32(SW_FW_SYNC
, swfw_sync
);
416 e1000e_put_hw_semaphore(hw
);
420 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
421 * @hw: pointer to the HW structure
422 * @offset: offset of the register to read
423 * @data: pointer to the data returned from the operation
425 * Read the GG82563 PHY register.
427 static s32
e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw
*hw
,
428 u32 offset
, u16
*data
)
434 ret_val
= e1000_acquire_phy_80003es2lan(hw
);
438 /* Select Configuration Page */
439 if ((offset
& MAX_PHY_REG_ADDRESS
) < GG82563_MIN_ALT_REG
) {
440 page_select
= GG82563_PHY_PAGE_SELECT
;
442 /* Use Alternative Page Select register to access
443 * registers 30 and 31
445 page_select
= GG82563_PHY_PAGE_SELECT_ALT
;
448 temp
= (u16
)((u16
)offset
>> GG82563_PAGE_SHIFT
);
449 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
, temp
);
451 e1000_release_phy_80003es2lan(hw
);
455 if (hw
->dev_spec
.e80003es2lan
.mdic_wa_enable
) {
456 /* The "ready" bit in the MDIC register may be incorrectly set
457 * before the device has completed the "Page Select" MDI
458 * transaction. So we wait 200us after each MDI command...
462 /* ...and verify the command was successful. */
463 ret_val
= e1000e_read_phy_reg_mdic(hw
, page_select
, &temp
);
465 if (((u16
)offset
>> GG82563_PAGE_SHIFT
) != temp
) {
466 e1000_release_phy_80003es2lan(hw
);
467 return -E1000_ERR_PHY
;
472 ret_val
= e1000e_read_phy_reg_mdic(hw
,
473 MAX_PHY_REG_ADDRESS
& offset
,
478 ret_val
= e1000e_read_phy_reg_mdic(hw
,
479 MAX_PHY_REG_ADDRESS
& offset
,
483 e1000_release_phy_80003es2lan(hw
);
489 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
490 * @hw: pointer to the HW structure
491 * @offset: offset of the register to read
492 * @data: value to write to the register
494 * Write to the GG82563 PHY register.
496 static s32
e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw
*hw
,
497 u32 offset
, u16 data
)
503 ret_val
= e1000_acquire_phy_80003es2lan(hw
);
507 /* Select Configuration Page */
508 if ((offset
& MAX_PHY_REG_ADDRESS
) < GG82563_MIN_ALT_REG
) {
509 page_select
= GG82563_PHY_PAGE_SELECT
;
511 /* Use Alternative Page Select register to access
512 * registers 30 and 31
514 page_select
= GG82563_PHY_PAGE_SELECT_ALT
;
517 temp
= (u16
)((u16
)offset
>> GG82563_PAGE_SHIFT
);
518 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
, temp
);
520 e1000_release_phy_80003es2lan(hw
);
524 if (hw
->dev_spec
.e80003es2lan
.mdic_wa_enable
) {
525 /* The "ready" bit in the MDIC register may be incorrectly set
526 * before the device has completed the "Page Select" MDI
527 * transaction. So we wait 200us after each MDI command...
531 /* ...and verify the command was successful. */
532 ret_val
= e1000e_read_phy_reg_mdic(hw
, page_select
, &temp
);
534 if (((u16
)offset
>> GG82563_PAGE_SHIFT
) != temp
) {
535 e1000_release_phy_80003es2lan(hw
);
536 return -E1000_ERR_PHY
;
541 ret_val
= e1000e_write_phy_reg_mdic(hw
,
542 MAX_PHY_REG_ADDRESS
& offset
,
547 ret_val
= e1000e_write_phy_reg_mdic(hw
,
548 MAX_PHY_REG_ADDRESS
& offset
,
552 e1000_release_phy_80003es2lan(hw
);
558 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
559 * @hw: pointer to the HW structure
560 * @offset: offset of the register to read
561 * @words: number of words to write
562 * @data: buffer of data to write to the NVM
564 * Write "words" of data to the ESB2 NVM.
566 static s32
e1000_write_nvm_80003es2lan(struct e1000_hw
*hw
, u16 offset
,
567 u16 words
, u16
*data
)
569 return e1000e_write_nvm_spi(hw
, offset
, words
, data
);
573 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
574 * @hw: pointer to the HW structure
576 * Wait a specific amount of time for manageability processes to complete.
577 * This is a function pointer entry point called by the phy module.
579 static s32
e1000_get_cfg_done_80003es2lan(struct e1000_hw
*hw
)
581 s32 timeout
= PHY_CFG_TIMEOUT
;
582 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
584 if (hw
->bus
.func
== 1)
585 mask
= E1000_NVM_CFG_DONE_PORT_1
;
588 if (er32(EEMNGCTL
) & mask
)
590 usleep_range(1000, 2000);
594 e_dbg("MNG configuration cycle has not completed.\n");
595 return -E1000_ERR_RESET
;
602 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
603 * @hw: pointer to the HW structure
605 * Force the speed and duplex settings onto the PHY. This is a
606 * function pointer entry point called by the phy module.
608 static s32
e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw
*hw
)
614 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
615 * forced whenever speed and duplex are forced.
617 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
621 phy_data
&= ~GG82563_PSCR_CROSSOVER_MODE_AUTO
;
622 ret_val
= e1e_wphy(hw
, GG82563_PHY_SPEC_CTRL
, phy_data
);
626 e_dbg("GG82563 PSCR: %X\n", phy_data
);
628 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
632 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
634 /* Reset the phy to commit changes. */
635 phy_data
|= MII_CR_RESET
;
637 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
643 if (hw
->phy
.autoneg_wait_to_complete
) {
644 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
646 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
652 /* We didn't get link.
653 * Reset the DSP and cross our fingers.
655 ret_val
= e1000e_phy_reset_dsp(hw
);
661 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
667 ret_val
= e1e_rphy(hw
, GG82563_PHY_MAC_SPEC_CTRL
, &phy_data
);
671 /* Resetting the phy means we need to verify the TX_CLK corresponds
672 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
674 phy_data
&= ~GG82563_MSCR_TX_CLK_MASK
;
675 if (hw
->mac
.forced_speed_duplex
& E1000_ALL_10_SPEED
)
676 phy_data
|= GG82563_MSCR_TX_CLK_10MBPS_2_5
;
678 phy_data
|= GG82563_MSCR_TX_CLK_100MBPS_25
;
680 /* In addition, we must re-enable CRS on Tx for both half and full
683 phy_data
|= GG82563_MSCR_ASSERT_CRS_ON_TX
;
684 ret_val
= e1e_wphy(hw
, GG82563_PHY_MAC_SPEC_CTRL
, phy_data
);
690 * e1000_get_cable_length_80003es2lan - Set approximate cable length
691 * @hw: pointer to the HW structure
693 * Find the approximate cable length as measured by the GG82563 PHY.
694 * This is a function pointer entry point called by the phy module.
696 static s32
e1000_get_cable_length_80003es2lan(struct e1000_hw
*hw
)
698 struct e1000_phy_info
*phy
= &hw
->phy
;
702 ret_val
= e1e_rphy(hw
, GG82563_PHY_DSP_DISTANCE
, &phy_data
);
706 index
= phy_data
& GG82563_DSPD_CABLE_LENGTH
;
708 if (index
>= GG82563_CABLE_LENGTH_TABLE_SIZE
- 5)
709 return -E1000_ERR_PHY
;
711 phy
->min_cable_length
= e1000_gg82563_cable_length_table
[index
];
712 phy
->max_cable_length
= e1000_gg82563_cable_length_table
[index
+ 5];
714 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
720 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
721 * @hw: pointer to the HW structure
722 * @speed: pointer to speed buffer
723 * @duplex: pointer to duplex buffer
725 * Retrieve the current speed and duplex configuration.
727 static s32
e1000_get_link_up_info_80003es2lan(struct e1000_hw
*hw
, u16
*speed
,
732 if (hw
->phy
.media_type
== e1000_media_type_copper
) {
733 ret_val
= e1000e_get_speed_and_duplex_copper(hw
,
736 hw
->phy
.ops
.cfg_on_link_up(hw
);
738 ret_val
= e1000e_get_speed_and_duplex_fiber_serdes(hw
,
747 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
748 * @hw: pointer to the HW structure
750 * Perform a global reset to the ESB2 controller.
752 static s32
e1000_reset_hw_80003es2lan(struct e1000_hw
*hw
)
758 /* Prevent the PCI-E bus from sticking if there is no TLP connection
759 * on the last TLP read/write transaction when MAC is reset.
761 ret_val
= e1000e_disable_pcie_master(hw
);
763 e_dbg("PCI-E Master disable polling has failed.\n");
765 e_dbg("Masking off all interrupts\n");
766 ew32(IMC
, 0xffffffff);
769 ew32(TCTL
, E1000_TCTL_PSP
);
772 usleep_range(10000, 20000);
776 ret_val
= e1000_acquire_phy_80003es2lan(hw
);
777 e_dbg("Issuing a global reset to MAC\n");
778 ew32(CTRL
, ctrl
| E1000_CTRL_RST
);
779 e1000_release_phy_80003es2lan(hw
);
781 /* Disable IBIST slave mode (far-end loopback) */
782 e1000_read_kmrn_reg_80003es2lan(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
784 kum_reg_data
|= E1000_KMRNCTRLSTA_IBIST_DISABLE
;
785 e1000_write_kmrn_reg_80003es2lan(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
788 ret_val
= e1000e_get_auto_rd_done(hw
);
790 /* We don't want to continue accessing MAC registers. */
793 /* Clear any pending interrupt events. */
794 ew32(IMC
, 0xffffffff);
797 return e1000_check_alt_mac_addr_generic(hw
);
801 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
802 * @hw: pointer to the HW structure
804 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
806 static s32
e1000_init_hw_80003es2lan(struct e1000_hw
*hw
)
808 struct e1000_mac_info
*mac
= &hw
->mac
;
814 e1000_initialize_hw_bits_80003es2lan(hw
);
816 /* Initialize identification LED */
817 ret_val
= mac
->ops
.id_led_init(hw
);
819 e_dbg("Error initializing identification LED\n");
820 /* This is not fatal and we should not stop init due to this */
822 /* Disabling VLAN filtering */
823 e_dbg("Initializing the IEEE VLAN\n");
824 mac
->ops
.clear_vfta(hw
);
826 /* Setup the receive address. */
827 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
829 /* Zero out the Multicast HASH table */
830 e_dbg("Zeroing the MTA\n");
831 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
832 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
834 /* Setup link and flow control */
835 ret_val
= mac
->ops
.setup_link(hw
);
837 /* Disable IBIST slave mode (far-end loopback) */
838 e1000_read_kmrn_reg_80003es2lan(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
840 kum_reg_data
|= E1000_KMRNCTRLSTA_IBIST_DISABLE
;
841 e1000_write_kmrn_reg_80003es2lan(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
844 /* Set the transmit descriptor write-back policy */
845 reg_data
= er32(TXDCTL(0));
846 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
847 E1000_TXDCTL_FULL_TX_DESC_WB
| E1000_TXDCTL_COUNT_DESC
;
848 ew32(TXDCTL(0), reg_data
);
850 /* ...for both queues. */
851 reg_data
= er32(TXDCTL(1));
852 reg_data
= (reg_data
& ~E1000_TXDCTL_WTHRESH
) |
853 E1000_TXDCTL_FULL_TX_DESC_WB
| E1000_TXDCTL_COUNT_DESC
;
854 ew32(TXDCTL(1), reg_data
);
856 /* Enable retransmit on late collisions */
857 reg_data
= er32(TCTL
);
858 reg_data
|= E1000_TCTL_RTLC
;
859 ew32(TCTL
, reg_data
);
861 /* Configure Gigabit Carry Extend Padding */
862 reg_data
= er32(TCTL_EXT
);
863 reg_data
&= ~E1000_TCTL_EXT_GCEX_MASK
;
864 reg_data
|= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN
;
865 ew32(TCTL_EXT
, reg_data
);
867 /* Configure Transmit Inter-Packet Gap */
868 reg_data
= er32(TIPG
);
869 reg_data
&= ~E1000_TIPG_IPGT_MASK
;
870 reg_data
|= DEFAULT_TIPG_IPGT_1000_80003ES2LAN
;
871 ew32(TIPG
, reg_data
);
873 reg_data
= E1000_READ_REG_ARRAY(hw
, E1000_FFLT
, 0x0001);
874 reg_data
&= ~0x00100000;
875 E1000_WRITE_REG_ARRAY(hw
, E1000_FFLT
, 0x0001, reg_data
);
877 /* default to true to enable the MDIC W/A */
878 hw
->dev_spec
.e80003es2lan
.mdic_wa_enable
= true;
880 ret_val
= e1000_read_kmrn_reg_80003es2lan(hw
,
881 E1000_KMRNCTRLSTA_OFFSET
>>
882 E1000_KMRNCTRLSTA_OFFSET_SHIFT
,
885 if ((i
& E1000_KMRNCTRLSTA_OPMODE_MASK
) ==
886 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO
)
887 hw
->dev_spec
.e80003es2lan
.mdic_wa_enable
= false;
890 /* Clear all of the statistics registers (clear on read). It is
891 * important that we do this after we have tried to establish link
892 * because the symbol error count will increment wildly if there
895 e1000_clear_hw_cntrs_80003es2lan(hw
);
901 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
902 * @hw: pointer to the HW structure
904 * Initializes required hardware-dependent bits needed for normal operation.
906 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw
*hw
)
910 /* Transmit Descriptor Control 0 */
911 reg
= er32(TXDCTL(0));
913 ew32(TXDCTL(0), reg
);
915 /* Transmit Descriptor Control 1 */
916 reg
= er32(TXDCTL(1));
918 ew32(TXDCTL(1), reg
);
920 /* Transmit Arbitration Control 0 */
922 reg
&= ~(0xF << 27); /* 30:27 */
923 if (hw
->phy
.media_type
!= e1000_media_type_copper
)
927 /* Transmit Arbitration Control 1 */
929 if (er32(TCTL
) & E1000_TCTL_MULR
)
935 /* Disable IPv6 extension header parsing because some malformed
936 * IPv6 headers can hang the Rx.
939 reg
|= (E1000_RFCTL_IPV6_EX_DIS
| E1000_RFCTL_NEW_IPV6_EXT_DIS
);
944 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
945 * @hw: pointer to the HW structure
947 * Setup some GG82563 PHY registers for obtaining link
949 static s32
e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw
*hw
)
951 struct e1000_phy_info
*phy
= &hw
->phy
;
956 ret_val
= e1e_rphy(hw
, GG82563_PHY_MAC_SPEC_CTRL
, &data
);
960 data
|= GG82563_MSCR_ASSERT_CRS_ON_TX
;
961 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
962 data
|= GG82563_MSCR_TX_CLK_1000MBPS_25
;
964 ret_val
= e1e_wphy(hw
, GG82563_PHY_MAC_SPEC_CTRL
, data
);
969 * MDI/MDI-X = 0 (default)
970 * 0 - Auto for all speeds
973 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
975 ret_val
= e1e_rphy(hw
, GG82563_PHY_SPEC_CTRL
, &data
);
979 data
&= ~GG82563_PSCR_CROSSOVER_MODE_MASK
;
983 data
|= GG82563_PSCR_CROSSOVER_MODE_MDI
;
986 data
|= GG82563_PSCR_CROSSOVER_MODE_MDIX
;
990 data
|= GG82563_PSCR_CROSSOVER_MODE_AUTO
;
995 * disable_polarity_correction = 0 (default)
996 * Automatic Correction for Reversed Cable Polarity
1000 data
&= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE
;
1001 if (phy
->disable_polarity_correction
)
1002 data
|= GG82563_PSCR_POLARITY_REVERSAL_DISABLE
;
1004 ret_val
= e1e_wphy(hw
, GG82563_PHY_SPEC_CTRL
, data
);
1008 /* SW Reset the PHY so all changes take effect */
1009 ret_val
= e1000e_commit_phy(hw
);
1011 e_dbg("Error Resetting the PHY\n");
1015 /* Bypass Rx and Tx FIFO's */
1016 ret_val
= e1000_write_kmrn_reg_80003es2lan(hw
,
1017 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL
,
1018 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS
|
1019 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS
);
1023 ret_val
= e1000_read_kmrn_reg_80003es2lan(hw
,
1024 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE
,
1028 data
|= E1000_KMRNCTRLSTA_OPMODE_E_IDLE
;
1029 ret_val
= e1000_write_kmrn_reg_80003es2lan(hw
,
1030 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE
,
1035 ret_val
= e1e_rphy(hw
, GG82563_PHY_SPEC_CTRL_2
, &data
);
1039 data
&= ~GG82563_PSCR2_REVERSE_AUTO_NEG
;
1040 ret_val
= e1e_wphy(hw
, GG82563_PHY_SPEC_CTRL_2
, data
);
1044 ctrl_ext
= er32(CTRL_EXT
);
1045 ctrl_ext
&= ~(E1000_CTRL_EXT_LINK_MODE_MASK
);
1046 ew32(CTRL_EXT
, ctrl_ext
);
1048 ret_val
= e1e_rphy(hw
, GG82563_PHY_PWR_MGMT_CTRL
, &data
);
1052 /* Do not init these registers when the HW is in IAMT mode, since the
1053 * firmware will have already initialized them. We only initialize
1054 * them if the HW is not in IAMT mode.
1056 if (!hw
->mac
.ops
.check_mng_mode(hw
)) {
1057 /* Enable Electrical Idle on the PHY */
1058 data
|= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE
;
1059 ret_val
= e1e_wphy(hw
, GG82563_PHY_PWR_MGMT_CTRL
, data
);
1063 ret_val
= e1e_rphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, &data
);
1067 data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
1068 ret_val
= e1e_wphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, data
);
1073 /* Workaround: Disable padding in Kumeran interface in the MAC
1074 * and in the PHY to avoid CRC errors.
1076 ret_val
= e1e_rphy(hw
, GG82563_PHY_INBAND_CTRL
, &data
);
1080 data
|= GG82563_ICR_DIS_PADDING
;
1081 ret_val
= e1e_wphy(hw
, GG82563_PHY_INBAND_CTRL
, data
);
1089 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1090 * @hw: pointer to the HW structure
1092 * Essentially a wrapper for setting up all things "copper" related.
1093 * This is a function pointer entry point called by the mac module.
1095 static s32
e1000_setup_copper_link_80003es2lan(struct e1000_hw
*hw
)
1102 ctrl
|= E1000_CTRL_SLU
;
1103 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1106 /* Set the mac to wait the maximum time between each
1107 * iteration and increase the max iterations when
1108 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1110 ret_val
= e1000_write_kmrn_reg_80003es2lan(hw
, GG82563_REG(0x34, 4),
1114 ret_val
= e1000_read_kmrn_reg_80003es2lan(hw
, GG82563_REG(0x34, 9),
1119 ret_val
= e1000_write_kmrn_reg_80003es2lan(hw
, GG82563_REG(0x34, 9),
1123 ret_val
= e1000_read_kmrn_reg_80003es2lan(hw
,
1124 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL
,
1128 reg_data
|= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING
;
1129 ret_val
= e1000_write_kmrn_reg_80003es2lan(hw
,
1130 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL
,
1135 ret_val
= e1000_copper_link_setup_gg82563_80003es2lan(hw
);
1139 return e1000e_setup_copper_link(hw
);
1143 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1144 * @hw: pointer to the HW structure
1145 * @duplex: current duplex setting
1147 * Configure the KMRN interface by applying last minute quirks for
1150 static s32
e1000_cfg_on_link_up_80003es2lan(struct e1000_hw
*hw
)
1156 if (hw
->phy
.media_type
== e1000_media_type_copper
) {
1157 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, &speed
,
1162 if (speed
== SPEED_1000
)
1163 ret_val
= e1000_cfg_kmrn_1000_80003es2lan(hw
);
1165 ret_val
= e1000_cfg_kmrn_10_100_80003es2lan(hw
, duplex
);
1172 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1173 * @hw: pointer to the HW structure
1174 * @duplex: current duplex setting
1176 * Configure the KMRN interface by applying last minute quirks for
1179 static s32
e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw
*hw
, u16 duplex
)
1184 u16 reg_data
, reg_data2
;
1186 reg_data
= E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT
;
1187 ret_val
= e1000_write_kmrn_reg_80003es2lan(hw
,
1188 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL
,
1193 /* Configure Transmit Inter-Packet Gap */
1195 tipg
&= ~E1000_TIPG_IPGT_MASK
;
1196 tipg
|= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN
;
1200 ret_val
= e1e_rphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, ®_data
);
1204 ret_val
= e1e_rphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, ®_data2
);
1208 } while ((reg_data
!= reg_data2
) && (i
< GG82563_MAX_KMRN_RETRY
));
1210 if (duplex
== HALF_DUPLEX
)
1211 reg_data
|= GG82563_KMCR_PASS_FALSE_CARRIER
;
1213 reg_data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
1215 return e1e_wphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, reg_data
);
1219 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1220 * @hw: pointer to the HW structure
1222 * Configure the KMRN interface by applying last minute quirks for
1223 * gigabit operation.
1225 static s32
e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw
*hw
)
1228 u16 reg_data
, reg_data2
;
1232 reg_data
= E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT
;
1233 ret_val
= e1000_write_kmrn_reg_80003es2lan(hw
,
1234 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL
,
1239 /* Configure Transmit Inter-Packet Gap */
1241 tipg
&= ~E1000_TIPG_IPGT_MASK
;
1242 tipg
|= DEFAULT_TIPG_IPGT_1000_80003ES2LAN
;
1246 ret_val
= e1e_rphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, ®_data
);
1250 ret_val
= e1e_rphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, ®_data2
);
1254 } while ((reg_data
!= reg_data2
) && (i
< GG82563_MAX_KMRN_RETRY
));
1256 reg_data
&= ~GG82563_KMCR_PASS_FALSE_CARRIER
;
1258 return e1e_wphy(hw
, GG82563_PHY_KMRN_MODE_CTRL
, reg_data
);
1262 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1263 * @hw: pointer to the HW structure
1264 * @offset: register offset to be read
1265 * @data: pointer to the read data
1267 * Acquire semaphore, then read the PHY register at offset
1268 * using the kumeran interface. The information retrieved is stored in data.
1269 * Release the semaphore before exiting.
1271 static s32
e1000_read_kmrn_reg_80003es2lan(struct e1000_hw
*hw
, u32 offset
,
1277 ret_val
= e1000_acquire_mac_csr_80003es2lan(hw
);
1281 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
1282 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
1283 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
1288 kmrnctrlsta
= er32(KMRNCTRLSTA
);
1289 *data
= (u16
)kmrnctrlsta
;
1291 e1000_release_mac_csr_80003es2lan(hw
);
1297 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1298 * @hw: pointer to the HW structure
1299 * @offset: register offset to write to
1300 * @data: data to write at register offset
1302 * Acquire semaphore, then write the data to PHY register
1303 * at the offset using the kumeran interface. Release semaphore
1306 static s32
e1000_write_kmrn_reg_80003es2lan(struct e1000_hw
*hw
, u32 offset
,
1312 ret_val
= e1000_acquire_mac_csr_80003es2lan(hw
);
1316 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
1317 E1000_KMRNCTRLSTA_OFFSET
) | data
;
1318 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
1323 e1000_release_mac_csr_80003es2lan(hw
);
1329 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1330 * @hw: pointer to the HW structure
1332 static s32
e1000_read_mac_addr_80003es2lan(struct e1000_hw
*hw
)
1336 /* If there's an alternate MAC address place it in RAR0
1337 * so that it will override the Si installed default perm
1340 ret_val
= e1000_check_alt_mac_addr_generic(hw
);
1344 return e1000_read_mac_addr_generic(hw
);
1348 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1349 * @hw: pointer to the HW structure
1351 * In the case of a PHY power down to save power, or to turn off link during a
1352 * driver unload, or wake on lan is not enabled, remove the link.
1354 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw
*hw
)
1356 /* If the management interface is not enabled, then power down */
1357 if (!(hw
->mac
.ops
.check_mng_mode(hw
) ||
1358 hw
->phy
.ops
.check_reset_block(hw
)))
1359 e1000_power_down_phy_copper(hw
);
1363 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1364 * @hw: pointer to the HW structure
1366 * Clears the hardware counters by reading the counter registers.
1368 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw
*hw
)
1370 e1000e_clear_hw_cntrs_base(hw
);
1408 static const struct e1000_mac_operations es2_mac_ops
= {
1409 .read_mac_addr
= e1000_read_mac_addr_80003es2lan
,
1410 .id_led_init
= e1000e_id_led_init_generic
,
1411 .blink_led
= e1000e_blink_led_generic
,
1412 .check_mng_mode
= e1000e_check_mng_mode_generic
,
1413 /* check_for_link dependent on media type */
1414 .cleanup_led
= e1000e_cleanup_led_generic
,
1415 .clear_hw_cntrs
= e1000_clear_hw_cntrs_80003es2lan
,
1416 .get_bus_info
= e1000e_get_bus_info_pcie
,
1417 .set_lan_id
= e1000_set_lan_id_multi_port_pcie
,
1418 .get_link_up_info
= e1000_get_link_up_info_80003es2lan
,
1419 .led_on
= e1000e_led_on_generic
,
1420 .led_off
= e1000e_led_off_generic
,
1421 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
1422 .write_vfta
= e1000_write_vfta_generic
,
1423 .clear_vfta
= e1000_clear_vfta_generic
,
1424 .reset_hw
= e1000_reset_hw_80003es2lan
,
1425 .init_hw
= e1000_init_hw_80003es2lan
,
1426 .setup_link
= e1000e_setup_link_generic
,
1427 /* setup_physical_interface dependent on media type */
1428 .setup_led
= e1000e_setup_led_generic
,
1429 .config_collision_dist
= e1000e_config_collision_dist_generic
,
1430 .rar_set
= e1000e_rar_set_generic
,
1433 static const struct e1000_phy_operations es2_phy_ops
= {
1434 .acquire
= e1000_acquire_phy_80003es2lan
,
1435 .check_polarity
= e1000_check_polarity_m88
,
1436 .check_reset_block
= e1000e_check_reset_block_generic
,
1437 .commit
= e1000e_phy_sw_reset
,
1438 .force_speed_duplex
= e1000_phy_force_speed_duplex_80003es2lan
,
1439 .get_cfg_done
= e1000_get_cfg_done_80003es2lan
,
1440 .get_cable_length
= e1000_get_cable_length_80003es2lan
,
1441 .get_info
= e1000e_get_phy_info_m88
,
1442 .read_reg
= e1000_read_phy_reg_gg82563_80003es2lan
,
1443 .release
= e1000_release_phy_80003es2lan
,
1444 .reset
= e1000e_phy_hw_reset_generic
,
1445 .set_d0_lplu_state
= NULL
,
1446 .set_d3_lplu_state
= e1000e_set_d3_lplu_state
,
1447 .write_reg
= e1000_write_phy_reg_gg82563_80003es2lan
,
1448 .cfg_on_link_up
= e1000_cfg_on_link_up_80003es2lan
,
1451 static const struct e1000_nvm_operations es2_nvm_ops
= {
1452 .acquire
= e1000_acquire_nvm_80003es2lan
,
1453 .read
= e1000e_read_nvm_eerd
,
1454 .release
= e1000_release_nvm_80003es2lan
,
1455 .reload
= e1000e_reload_nvm_generic
,
1456 .update
= e1000e_update_nvm_checksum_generic
,
1457 .valid_led_default
= e1000e_valid_led_default
,
1458 .validate
= e1000e_validate_nvm_checksum_generic
,
1459 .write
= e1000_write_nvm_80003es2lan
,
1462 const struct e1000_info e1000_es2_info
= {
1463 .mac
= e1000_80003es2lan
,
1464 .flags
= FLAG_HAS_HW_VLAN_FILTER
1465 | FLAG_HAS_JUMBO_FRAMES
1467 | FLAG_APME_IN_CTRL3
1468 | FLAG_HAS_CTRLEXT_ON_LOAD
1469 | FLAG_RX_NEEDS_RESTART
/* errata */
1470 | FLAG_TARC_SET_BIT_ZERO
/* errata */
1471 | FLAG_APME_CHECK_PORT_B
1472 | FLAG_DISABLE_FC_PAUSE_TIME
, /* errata */
1473 .flags2
= FLAG2_DMA_BURST
,
1475 .max_hw_frame_size
= DEFAULT_JUMBO
,
1476 .get_variants
= e1000_get_variants_80003es2lan
,
1477 .mac_ops
= &es2_mac_ops
,
1478 .phy_ops
= &es2_phy_ops
,
1479 .nvm_ops
= &es2_nvm_ops
,