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e1000e: cosmetic cleanup of comments
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / e1000.h
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* Linux PRO/1000 Ethernet Driver main header file */
30
31 #ifndef _E1000_H_
32 #define _E1000_H_
33
34 #include <linux/bitops.h>
35 #include <linux/types.h>
36 #include <linux/timer.h>
37 #include <linux/workqueue.h>
38 #include <linux/io.h>
39 #include <linux/netdevice.h>
40 #include <linux/pci.h>
41 #include <linux/pci-aspm.h>
42 #include <linux/crc32.h>
43 #include <linux/if_vlan.h>
44
45 #include "hw.h"
46
47 struct e1000_info;
48
49 #define e_dbg(format, arg...) \
50 netdev_dbg(hw->adapter->netdev, format, ## arg)
51 #define e_err(format, arg...) \
52 netdev_err(adapter->netdev, format, ## arg)
53 #define e_info(format, arg...) \
54 netdev_info(adapter->netdev, format, ## arg)
55 #define e_warn(format, arg...) \
56 netdev_warn(adapter->netdev, format, ## arg)
57 #define e_notice(format, arg...) \
58 netdev_notice(adapter->netdev, format, ## arg)
59
60
61 /* Interrupt modes, as used by the IntMode parameter */
62 #define E1000E_INT_MODE_LEGACY 0
63 #define E1000E_INT_MODE_MSI 1
64 #define E1000E_INT_MODE_MSIX 2
65
66 /* Tx/Rx descriptor defines */
67 #define E1000_DEFAULT_TXD 256
68 #define E1000_MAX_TXD 4096
69 #define E1000_MIN_TXD 64
70
71 #define E1000_DEFAULT_RXD 256
72 #define E1000_MAX_RXD 4096
73 #define E1000_MIN_RXD 64
74
75 #define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
76 #define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
77
78 /* Early Receive defines */
79 #define E1000_ERT_2048 0x100
80
81 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
82
83 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
84 /* How many Rx Buffers do we bundle into one write to the hardware ? */
85 #define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
86
87 #define AUTO_ALL_MODES 0
88 #define E1000_EEPROM_APME 0x0400
89
90 #define E1000_MNG_VLAN_NONE (-1)
91
92 /* Number of packet split data buffers (not including the header buffer) */
93 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
94
95 #define DEFAULT_JUMBO 9234
96
97 /* BM/HV Specific Registers */
98 #define BM_PORT_CTRL_PAGE 769
99
100 #define PHY_UPPER_SHIFT 21
101 #define BM_PHY_REG(page, reg) \
102 (((reg) & MAX_PHY_REG_ADDRESS) |\
103 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
104 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
105
106 /* PHY Wakeup Registers and defines */
107 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
108 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
109 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
110 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
111 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
112 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
113 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
114 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
115 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
116 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
117
118 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
119 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
120 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
121 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
122 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
123 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
124 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
125
126 #define HV_STATS_PAGE 778
127 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
128 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
129 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
130 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
131 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
132 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
133 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
134 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
135 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
136 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
137 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
138 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
139 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
140 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
141
142 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
143
144 /* BM PHY Copper Specific Status */
145 #define BM_CS_STATUS 17
146 #define BM_CS_STATUS_LINK_UP 0x0400
147 #define BM_CS_STATUS_RESOLVED 0x0800
148 #define BM_CS_STATUS_SPEED_MASK 0xC000
149 #define BM_CS_STATUS_SPEED_1000 0x8000
150
151 /* 82577 Mobile Phy Status Register */
152 #define HV_M_STATUS 26
153 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
154 #define HV_M_STATUS_SPEED_MASK 0x0300
155 #define HV_M_STATUS_SPEED_1000 0x0200
156 #define HV_M_STATUS_LINK_UP 0x0040
157
158 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
159 #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
160
161 /* Time to wait before putting the device into D3 if there's no link (in ms). */
162 #define LINK_TIMEOUT 100
163
164 /* Count for polling __E1000_RESET condition every 10-20msec.
165 * Experimentation has shown the reset can take approximately 210msec.
166 */
167 #define E1000_CHECK_RESET_COUNT 25
168
169 #define DEFAULT_RDTR 0
170 #define DEFAULT_RADV 8
171 #define BURST_RDTR 0x20
172 #define BURST_RADV 0x20
173
174 /* in the case of WTHRESH, it appears at least the 82571/2 hardware
175 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
176 * WTHRESH=4, so a setting of 5 gives the most efficient bus
177 * utilization but to avoid possible Tx stalls, set it to 1
178 */
179 #define E1000_TXDCTL_DMA_BURST_ENABLE \
180 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
181 E1000_TXDCTL_COUNT_DESC | \
182 (1 << 16) | /* wthresh must be +1 more than desired */\
183 (1 << 8) | /* hthresh */ \
184 0x1f) /* pthresh */
185
186 #define E1000_RXDCTL_DMA_BURST_ENABLE \
187 (0x01000000 | /* set descriptor granularity */ \
188 (4 << 16) | /* set writeback threshold */ \
189 (4 << 8) | /* set prefetch threshold */ \
190 0x20) /* set hthresh */
191
192 #define E1000_TIDV_FPD (1 << 31)
193 #define E1000_RDTR_FPD (1 << 31)
194
195 enum e1000_boards {
196 board_82571,
197 board_82572,
198 board_82573,
199 board_82574,
200 board_82583,
201 board_80003es2lan,
202 board_ich8lan,
203 board_ich9lan,
204 board_ich10lan,
205 board_pchlan,
206 board_pch2lan,
207 board_pch_lpt,
208 };
209
210 struct e1000_ps_page {
211 struct page *page;
212 u64 dma; /* must be u64 - written to hw */
213 };
214
215 /* wrappers around a pointer to a socket buffer,
216 * so a DMA handle can be stored along with the buffer
217 */
218 struct e1000_buffer {
219 dma_addr_t dma;
220 struct sk_buff *skb;
221 union {
222 /* Tx */
223 struct {
224 unsigned long time_stamp;
225 u16 length;
226 u16 next_to_watch;
227 unsigned int segs;
228 unsigned int bytecount;
229 u16 mapped_as_page;
230 };
231 /* Rx */
232 struct {
233 /* arrays of page information for packet split */
234 struct e1000_ps_page *ps_pages;
235 struct page *page;
236 };
237 };
238 };
239
240 struct e1000_ring {
241 struct e1000_adapter *adapter; /* back pointer to adapter */
242 void *desc; /* pointer to ring memory */
243 dma_addr_t dma; /* phys address of ring */
244 unsigned int size; /* length of ring in bytes */
245 unsigned int count; /* number of desc. in ring */
246
247 u16 next_to_use;
248 u16 next_to_clean;
249
250 void __iomem *head;
251 void __iomem *tail;
252
253 /* array of buffer information structs */
254 struct e1000_buffer *buffer_info;
255
256 char name[IFNAMSIZ + 5];
257 u32 ims_val;
258 u32 itr_val;
259 void __iomem *itr_register;
260 int set_itr;
261
262 struct sk_buff *rx_skb_top;
263 };
264
265 /* PHY register snapshot values */
266 struct e1000_phy_regs {
267 u16 bmcr; /* basic mode control register */
268 u16 bmsr; /* basic mode status register */
269 u16 advertise; /* auto-negotiation advertisement */
270 u16 lpa; /* link partner ability register */
271 u16 expansion; /* auto-negotiation expansion reg */
272 u16 ctrl1000; /* 1000BASE-T control register */
273 u16 stat1000; /* 1000BASE-T status register */
274 u16 estatus; /* extended status register */
275 };
276
277 /* board specific private data structure */
278 struct e1000_adapter {
279 struct timer_list watchdog_timer;
280 struct timer_list phy_info_timer;
281 struct timer_list blink_timer;
282
283 struct work_struct reset_task;
284 struct work_struct watchdog_task;
285
286 const struct e1000_info *ei;
287
288 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
289 u32 bd_number;
290 u32 rx_buffer_len;
291 u16 mng_vlan_id;
292 u16 link_speed;
293 u16 link_duplex;
294 u16 eeprom_vers;
295
296 /* track device up/down/testing state */
297 unsigned long state;
298
299 /* Interrupt Throttle Rate */
300 u32 itr;
301 u32 itr_setting;
302 u16 tx_itr;
303 u16 rx_itr;
304
305 /* Tx */
306 struct e1000_ring *tx_ring /* One per active queue */
307 ____cacheline_aligned_in_smp;
308 u32 tx_fifo_limit;
309
310 struct napi_struct napi;
311
312 unsigned int restart_queue;
313 u32 txd_cmd;
314
315 bool detect_tx_hung;
316 bool tx_hang_recheck;
317 u8 tx_timeout_factor;
318
319 u32 tx_int_delay;
320 u32 tx_abs_int_delay;
321
322 unsigned int total_tx_bytes;
323 unsigned int total_tx_packets;
324 unsigned int total_rx_bytes;
325 unsigned int total_rx_packets;
326
327 /* Tx stats */
328 u64 tpt_old;
329 u64 colc_old;
330 u32 gotc;
331 u64 gotc_old;
332 u32 tx_timeout_count;
333 u32 tx_fifo_head;
334 u32 tx_head_addr;
335 u32 tx_fifo_size;
336 u32 tx_dma_failed;
337
338 /* Rx */
339 bool (*clean_rx) (struct e1000_ring *ring, int *work_done,
340 int work_to_do) ____cacheline_aligned_in_smp;
341 void (*alloc_rx_buf) (struct e1000_ring *ring, int cleaned_count,
342 gfp_t gfp);
343 struct e1000_ring *rx_ring;
344
345 u32 rx_int_delay;
346 u32 rx_abs_int_delay;
347
348 /* Rx stats */
349 u64 hw_csum_err;
350 u64 hw_csum_good;
351 u64 rx_hdr_split;
352 u32 gorc;
353 u64 gorc_old;
354 u32 alloc_rx_buff_failed;
355 u32 rx_dma_failed;
356
357 unsigned int rx_ps_pages;
358 u16 rx_ps_bsize0;
359 u32 max_frame_size;
360 u32 min_frame_size;
361
362 /* OS defined structs */
363 struct net_device *netdev;
364 struct pci_dev *pdev;
365
366 /* structs defined in e1000_hw.h */
367 struct e1000_hw hw;
368
369 spinlock_t stats64_lock;
370 struct e1000_hw_stats stats;
371 struct e1000_phy_info phy_info;
372 struct e1000_phy_stats phy_stats;
373
374 /* Snapshot of PHY registers */
375 struct e1000_phy_regs phy_regs;
376
377 struct e1000_ring test_tx_ring;
378 struct e1000_ring test_rx_ring;
379 u32 test_icr;
380
381 u32 msg_enable;
382 unsigned int num_vectors;
383 struct msix_entry *msix_entries;
384 int int_mode;
385 u32 eiac_mask;
386
387 u32 eeprom_wol;
388 u32 wol;
389 u32 pba;
390 u32 max_hw_frame_size;
391
392 bool fc_autoneg;
393
394 unsigned int flags;
395 unsigned int flags2;
396 struct work_struct downshift_task;
397 struct work_struct update_phy_task;
398 struct work_struct print_hang_task;
399
400 bool idle_check;
401 int phy_hang_count;
402
403 u16 tx_ring_count;
404 u16 rx_ring_count;
405 };
406
407 struct e1000_info {
408 enum e1000_mac_type mac;
409 unsigned int flags;
410 unsigned int flags2;
411 u32 pba;
412 u32 max_hw_frame_size;
413 s32 (*get_variants)(struct e1000_adapter *);
414 const struct e1000_mac_operations *mac_ops;
415 const struct e1000_phy_operations *phy_ops;
416 const struct e1000_nvm_operations *nvm_ops;
417 };
418
419 /* hardware capability, feature, and workaround flags */
420 #define FLAG_HAS_AMT (1 << 0)
421 #define FLAG_HAS_FLASH (1 << 1)
422 #define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
423 #define FLAG_HAS_WOL (1 << 3)
424 /* reserved bit4 */
425 #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
426 #define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
427 #define FLAG_HAS_JUMBO_FRAMES (1 << 7)
428 #define FLAG_READ_ONLY_NVM (1 << 8)
429 #define FLAG_IS_ICH (1 << 9)
430 #define FLAG_HAS_MSIX (1 << 10)
431 #define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
432 #define FLAG_IS_QUAD_PORT_A (1 << 12)
433 #define FLAG_IS_QUAD_PORT (1 << 13)
434 /* reserved bit14 */
435 #define FLAG_APME_IN_WUC (1 << 15)
436 #define FLAG_APME_IN_CTRL3 (1 << 16)
437 #define FLAG_APME_CHECK_PORT_B (1 << 17)
438 #define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
439 #define FLAG_NO_WAKE_UCAST (1 << 19)
440 #define FLAG_MNG_PT_ENABLED (1 << 20)
441 #define FLAG_RESET_OVERWRITES_LAA (1 << 21)
442 #define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
443 #define FLAG_TARC_SET_BIT_ZERO (1 << 23)
444 #define FLAG_RX_NEEDS_RESTART (1 << 24)
445 #define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
446 #define FLAG_SMART_POWER_DOWN (1 << 26)
447 #define FLAG_MSI_ENABLED (1 << 27)
448 /* reserved (1 << 28) */
449 #define FLAG_TSO_FORCE (1 << 29)
450 #define FLAG_RX_RESTART_NOW (1 << 30)
451 #define FLAG_MSI_TEST_FAILED (1 << 31)
452
453 #define FLAG2_CRC_STRIPPING (1 << 0)
454 #define FLAG2_HAS_PHY_WAKEUP (1 << 1)
455 #define FLAG2_IS_DISCARDING (1 << 2)
456 #define FLAG2_DISABLE_ASPM_L1 (1 << 3)
457 #define FLAG2_HAS_PHY_STATS (1 << 4)
458 #define FLAG2_HAS_EEE (1 << 5)
459 #define FLAG2_DMA_BURST (1 << 6)
460 #define FLAG2_DISABLE_ASPM_L0S (1 << 7)
461 #define FLAG2_DISABLE_AIM (1 << 8)
462 #define FLAG2_CHECK_PHY_HANG (1 << 9)
463 #define FLAG2_NO_DISABLE_RX (1 << 10)
464 #define FLAG2_PCIM2PCI_ARBITER_WA (1 << 11)
465 #define FLAG2_DFLT_CRC_STRIPPING (1 << 12)
466
467 #define E1000_RX_DESC_PS(R, i) \
468 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
469 #define E1000_RX_DESC_EXT(R, i) \
470 (&(((union e1000_rx_desc_extended *)((R).desc))[i]))
471 #define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
472 #define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
473 #define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
474
475 enum e1000_state_t {
476 __E1000_TESTING,
477 __E1000_RESETTING,
478 __E1000_ACCESS_SHARED_RESOURCE,
479 __E1000_DOWN
480 };
481
482 enum latency_range {
483 lowest_latency = 0,
484 low_latency = 1,
485 bulk_latency = 2,
486 latency_invalid = 255
487 };
488
489 extern char e1000e_driver_name[];
490 extern const char e1000e_driver_version[];
491
492 extern void e1000e_check_options(struct e1000_adapter *adapter);
493 extern void e1000e_set_ethtool_ops(struct net_device *netdev);
494
495 extern int e1000e_up(struct e1000_adapter *adapter);
496 extern void e1000e_down(struct e1000_adapter *adapter);
497 extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
498 extern void e1000e_reset(struct e1000_adapter *adapter);
499 extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
500 extern int e1000e_setup_rx_resources(struct e1000_ring *ring);
501 extern int e1000e_setup_tx_resources(struct e1000_ring *ring);
502 extern void e1000e_free_rx_resources(struct e1000_ring *ring);
503 extern void e1000e_free_tx_resources(struct e1000_ring *ring);
504 extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
505 struct rtnl_link_stats64
506 *stats);
507 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
508 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
509 extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
510 extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
511 extern void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr);
512
513 extern unsigned int copybreak;
514
515 extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
516
517 extern const struct e1000_info e1000_82571_info;
518 extern const struct e1000_info e1000_82572_info;
519 extern const struct e1000_info e1000_82573_info;
520 extern const struct e1000_info e1000_82574_info;
521 extern const struct e1000_info e1000_82583_info;
522 extern const struct e1000_info e1000_ich8_info;
523 extern const struct e1000_info e1000_ich9_info;
524 extern const struct e1000_info e1000_ich10_info;
525 extern const struct e1000_info e1000_pch_info;
526 extern const struct e1000_info e1000_pch2_info;
527 extern const struct e1000_info e1000_pch_lpt_info;
528 extern const struct e1000_info e1000_es2_info;
529
530 extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
531 u32 pba_num_size);
532
533 extern s32 e1000e_commit_phy(struct e1000_hw *hw);
534
535 extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
536
537 extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
538 extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
539
540 extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
541 extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
542 bool state);
543 extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
544 extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
545 extern void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
546 extern void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
547 extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
548 extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
549 extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
550
551 extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
552 extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
553 extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
554 extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
555 extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
556 extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
557 extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
558 extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
559 extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
560 extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
561 extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
562 extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
563 extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
564 extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
565 extern s32 e1000e_id_led_init_generic(struct e1000_hw *hw);
566 extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
567 extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
568 extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
569 extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
570 extern s32 e1000e_setup_link_generic(struct e1000_hw *hw);
571 extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
572 extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
573 extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
574 u8 *mc_addr_list,
575 u32 mc_addr_count);
576 extern void e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
577 extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
578 extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
579 extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
580 extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
581 extern void e1000e_config_collision_dist_generic(struct e1000_hw *hw);
582 extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
583 extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
584 extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
585 extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
586 extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
587 extern void e1000e_reset_adaptive(struct e1000_hw *hw);
588 extern void e1000e_update_adaptive(struct e1000_hw *hw);
589
590 extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
591 extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
592 extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
593 extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
594 extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
595 extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
596 extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
597 extern s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page);
598 extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
599 extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
600 u16 *data);
601 extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
602 extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
603 extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
604 extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
605 u16 data);
606 extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
607 extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
608 extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
609 extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
610 extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
611 extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
612 extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
613 extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
614 extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
615 extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
616 extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
617 extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
618 extern s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
619 u16 *phy_reg);
620 extern s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw,
621 u16 *phy_reg);
622 extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
623 extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
624 extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
625 extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
626 extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
627 u16 data);
628 extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
629 extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
630 u16 *data);
631 extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
632 u32 usec_interval, bool *success);
633 extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
634 extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
635 extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
636 extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
637 extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
638 extern s32 e1000e_check_downshift(struct e1000_hw *hw);
639 extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
640 extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
641 u16 *data);
642 extern s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
643 u16 *data);
644 extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
645 extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
646 u16 data);
647 extern s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset,
648 u16 data);
649 extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
650 extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
651 extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
652 extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
653 extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
654 extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
655
656 extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
657 extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
658 extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
659 extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
660 extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
661 extern bool e1000_check_phy_82574(struct e1000_hw *hw);
662
663 static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
664 {
665 return hw->phy.ops.reset(hw);
666 }
667
668 static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
669 {
670 return hw->phy.ops.read_reg(hw, offset, data);
671 }
672
673 static inline s32 e1e_rphy_locked(struct e1000_hw *hw, u32 offset, u16 *data)
674 {
675 return hw->phy.ops.read_reg_locked(hw, offset, data);
676 }
677
678 static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
679 {
680 return hw->phy.ops.write_reg(hw, offset, data);
681 }
682
683 static inline s32 e1e_wphy_locked(struct e1000_hw *hw, u32 offset, u16 data)
684 {
685 return hw->phy.ops.write_reg_locked(hw, offset, data);
686 }
687
688 static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
689 {
690 return hw->phy.ops.get_cable_length(hw);
691 }
692
693 extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
694 extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
695 extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
696 extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
697 extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
698 extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
699 extern void e1000e_release_nvm(struct e1000_hw *hw);
700 extern void e1000e_reload_nvm_generic(struct e1000_hw *hw);
701 extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
702
703 static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
704 {
705 if (hw->mac.ops.read_mac_addr)
706 return hw->mac.ops.read_mac_addr(hw);
707
708 return e1000_read_mac_addr_generic(hw);
709 }
710
711 static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
712 {
713 return hw->nvm.ops.validate(hw);
714 }
715
716 static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
717 {
718 return hw->nvm.ops.update(hw);
719 }
720
721 static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
722 {
723 return hw->nvm.ops.read(hw, offset, words, data);
724 }
725
726 static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
727 {
728 return hw->nvm.ops.write(hw, offset, words, data);
729 }
730
731 static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
732 {
733 return hw->phy.ops.get_info(hw);
734 }
735
736 extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
737 extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
738 extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
739
740 static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
741 {
742 return readl(hw->hw_addr + reg);
743 }
744
745 #define er32(reg) __er32(hw, E1000_##reg)
746
747 /**
748 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
749 * @hw: pointer to the HW structure
750 *
751 * When updating the MAC CSR registers, the Manageability Engine (ME) could
752 * be accessing the registers at the same time. Normally, this is handled in
753 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
754 * accesses later than it should which could result in the register to have
755 * an incorrect value. Workaround this by checking the FWSM register which
756 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
757 * and try again a number of times.
758 **/
759 static inline s32 __ew32_prepare(struct e1000_hw *hw)
760 {
761 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
762
763 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
764 udelay(50);
765
766 return i;
767 }
768
769 static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
770 {
771 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
772 __ew32_prepare(hw);
773
774 writel(val, hw->hw_addr + reg);
775 }
776
777 #define ew32(reg, val) __ew32(hw, E1000_##reg, (val))
778
779 #define e1e_flush() er32(STATUS)
780
781 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
782 (__ew32((a), (reg + ((offset) << 2)), (value)))
783
784 #define E1000_READ_REG_ARRAY(a, reg, offset) \
785 (readl((a)->hw_addr + reg + ((offset) << 2)))
786
787 #endif /* _E1000_H_ */
Linux kernel - Deliverables
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