projects / deliverable / linux.git / blob
? search:


15d93141cc1119f1b5646f02f230d7cdd02be4c6
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /* 82562G 10/100 Network Connection
30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
41 * 82567LM Gigabit Network Connection
42 * 82567LF Gigabit Network Connection
43 * 82567V Gigabit Network Connection
44 * 82567LM-2 Gigabit Network Connection
45 * 82567LF-2 Gigabit Network Connection
46 * 82567V-2 Gigabit Network Connection
47 * 82567LF-3 Gigabit Network Connection
48 * 82567LM-3 Gigabit Network Connection
49 * 82567LM-4 Gigabit Network Connection
50 * 82577LM Gigabit Network Connection
51 * 82577LC Gigabit Network Connection
52 * 82578DM Gigabit Network Connection
53 * 82578DC Gigabit Network Connection
54 * 82579LM Gigabit Network Connection
55 * 82579V Gigabit Network Connection
56 */
57
58 #include "e1000.h"
59
60 #define ICH_FLASH_GFPREG 0x0000
61 #define ICH_FLASH_HSFSTS 0x0004
62 #define ICH_FLASH_HSFCTL 0x0006
63 #define ICH_FLASH_FADDR 0x0008
64 #define ICH_FLASH_FDATA0 0x0010
65 #define ICH_FLASH_PR0 0x0074
66
67 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
70 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
71 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
72
73 #define ICH_CYCLE_READ 0
74 #define ICH_CYCLE_WRITE 2
75 #define ICH_CYCLE_ERASE 3
76
77 #define FLASH_GFPREG_BASE_MASK 0x1FFF
78 #define FLASH_SECTOR_ADDR_SHIFT 12
79
80 #define ICH_FLASH_SEG_SIZE_256 256
81 #define ICH_FLASH_SEG_SIZE_4K 4096
82 #define ICH_FLASH_SEG_SIZE_8K 8192
83 #define ICH_FLASH_SEG_SIZE_64K 65536
84
85
86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87 /* FW established a valid mode */
88 #define E1000_ICH_FWSM_FW_VALID 0x00008000
89
90 #define E1000_ICH_MNG_IAMT_MODE 0x2
91
92 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
93 (ID_LED_DEF1_OFF2 << 8) | \
94 (ID_LED_DEF1_ON2 << 4) | \
95 (ID_LED_DEF1_DEF2))
96
97 #define E1000_ICH_NVM_SIG_WORD 0x13
98 #define E1000_ICH_NVM_SIG_MASK 0xC000
99 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
100 #define E1000_ICH_NVM_SIG_VALUE 0x80
101
102 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
103
104 #define E1000_FEXTNVM_SW_CONFIG 1
105 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
106
107 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
108 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
109
110 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
111 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
112 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
113
114 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
115
116 #define E1000_ICH_RAR_ENTRIES 7
117 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
118 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
119
120 #define PHY_PAGE_SHIFT 5
121 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
122 ((reg) & MAX_PHY_REG_ADDRESS))
123 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
124 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
125
126 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
127 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
128 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
129
130 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
131
132 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
133
134 /* SMBus Control Phy Register */
135 #define CV_SMB_CTRL PHY_REG(769, 23)
136 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
137
138 /* SMBus Address Phy Register */
139 #define HV_SMB_ADDR PHY_REG(768, 26)
140 #define HV_SMB_ADDR_MASK 0x007F
141 #define HV_SMB_ADDR_PEC_EN 0x0200
142 #define HV_SMB_ADDR_VALID 0x0080
143 #define HV_SMB_ADDR_FREQ_MASK 0x1100
144 #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
145 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
146
147 /* PHY Power Management Control */
148 #define HV_PM_CTRL PHY_REG(770, 17)
149 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
150
151 /* PHY Low Power Idle Control */
152 #define I82579_LPI_CTRL PHY_REG(772, 20)
153 #define I82579_LPI_CTRL_100_ENABLE 0x2000
154 #define I82579_LPI_CTRL_1000_ENABLE 0x4000
155 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
156 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80
157
158 /* Extended Management Interface (EMI) Registers */
159 #define I82579_EMI_ADDR 0x10
160 #define I82579_EMI_DATA 0x11
161 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
162 #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */
163 #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */
164 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */
165 #define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */
166 #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
167 #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */
168 #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE supported */
169 #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
170 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
171 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */
172
173 /* Intel Rapid Start Technology Support */
174 #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
175 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
176 #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
177 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
178 #define I217_CGFREG PHY_REG(772, 29)
179 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002
180 #define I217_MEMPWR PHY_REG(772, 26)
181 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
182
183 /* Strapping Option Register - RO */
184 #define E1000_STRAP 0x0000C
185 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
186 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
187 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000
188 #define E1000_STRAP_SMT_FREQ_SHIFT 12
189
190 /* OEM Bits Phy Register */
191 #define HV_OEM_BITS PHY_REG(768, 25)
192 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
193 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
194 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
195
196 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
197 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
198
199 /* KMRN Mode Control */
200 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
201 #define HV_KMRN_MDIO_SLOW 0x0400
202
203 /* KMRN FIFO Control and Status */
204 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
205 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
206 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
207
208 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
209 /* Offset 04h HSFSTS */
210 union ich8_hws_flash_status {
211 struct ich8_hsfsts {
212 u16 flcdone :1; /* bit 0 Flash Cycle Done */
213 u16 flcerr :1; /* bit 1 Flash Cycle Error */
214 u16 dael :1; /* bit 2 Direct Access error Log */
215 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
216 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
217 u16 reserved1 :2; /* bit 13:6 Reserved */
218 u16 reserved2 :6; /* bit 13:6 Reserved */
219 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
220 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
221 } hsf_status;
222 u16 regval;
223 };
224
225 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
226 /* Offset 06h FLCTL */
227 union ich8_hws_flash_ctrl {
228 struct ich8_hsflctl {
229 u16 flcgo :1; /* 0 Flash Cycle Go */
230 u16 flcycle :2; /* 2:1 Flash Cycle */
231 u16 reserved :5; /* 7:3 Reserved */
232 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
233 u16 flockdn :6; /* 15:10 Reserved */
234 } hsf_ctrl;
235 u16 regval;
236 };
237
238 /* ICH Flash Region Access Permissions */
239 union ich8_hws_flash_regacc {
240 struct ich8_flracc {
241 u32 grra :8; /* 0:7 GbE region Read Access */
242 u32 grwa :8; /* 8:15 GbE region Write Access */
243 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
244 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
245 } hsf_flregacc;
246 u16 regval;
247 };
248
249 /* ICH Flash Protected Region */
250 union ich8_flash_protected_range {
251 struct ich8_pr {
252 u32 base:13; /* 0:12 Protected Range Base */
253 u32 reserved1:2; /* 13:14 Reserved */
254 u32 rpe:1; /* 15 Read Protection Enable */
255 u32 limit:13; /* 16:28 Protected Range Limit */
256 u32 reserved2:2; /* 29:30 Reserved */
257 u32 wpe:1; /* 31 Write Protection Enable */
258 } range;
259 u32 regval;
260 };
261
262 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
263 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
264 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
265 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
266 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
267 u32 offset, u8 byte);
268 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
269 u8 *data);
270 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
271 u16 *data);
272 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
273 u8 size, u16 *data);
274 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
275 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
276 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
277 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
278 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
279 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
280 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
281 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
282 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
283 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
284 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
285 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
286 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
287 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
288 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
289 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
290 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
291 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
292 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
293 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
294 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
295 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
296
297 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
298 {
299 return readw(hw->flash_address + reg);
300 }
301
302 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
303 {
304 return readl(hw->flash_address + reg);
305 }
306
307 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
308 {
309 writew(val, hw->flash_address + reg);
310 }
311
312 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
313 {
314 writel(val, hw->flash_address + reg);
315 }
316
317 #define er16flash(reg) __er16flash(hw, (reg))
318 #define er32flash(reg) __er32flash(hw, (reg))
319 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
320 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
321
322 /**
323 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
324 * @hw: pointer to the HW structure
325 *
326 * Test access to the PHY registers by reading the PHY ID registers. If
327 * the PHY ID is already known (e.g. resume path) compare it with known ID,
328 * otherwise assume the read PHY ID is correct if it is valid.
329 *
330 * Assumes the sw/fw/hw semaphore is already acquired.
331 **/
332 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
333 {
334 u16 phy_reg = 0;
335 u32 phy_id = 0;
336 s32 ret_val;
337 u16 retry_count;
338
339 for (retry_count = 0; retry_count < 2; retry_count++) {
340 ret_val = e1e_rphy_locked(hw, PHY_ID1, &phy_reg);
341 if (ret_val || (phy_reg == 0xFFFF))
342 continue;
343 phy_id = (u32)(phy_reg << 16);
344
345 ret_val = e1e_rphy_locked(hw, PHY_ID2, &phy_reg);
346 if (ret_val || (phy_reg == 0xFFFF)) {
347 phy_id = 0;
348 continue;
349 }
350 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
351 break;
352 }
353
354 if (hw->phy.id) {
355 if (hw->phy.id == phy_id)
356 return true;
357 } else if (phy_id) {
358 hw->phy.id = phy_id;
359 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
360 return true;
361 }
362
363 /* In case the PHY needs to be in mdio slow mode,
364 * set slow mode and try to get the PHY id again.
365 */
366 hw->phy.ops.release(hw);
367 ret_val = e1000_set_mdio_slow_mode_hv(hw);
368 if (!ret_val)
369 ret_val = e1000e_get_phy_id(hw);
370 hw->phy.ops.acquire(hw);
371
372 return !ret_val;
373 }
374
375 /**
376 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
377 * @hw: pointer to the HW structure
378 *
379 * Workarounds/flow necessary for PHY initialization during driver load
380 * and resume paths.
381 **/
382 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
383 {
384 u32 mac_reg, fwsm = er32(FWSM);
385 s32 ret_val;
386 u16 phy_reg;
387
388 ret_val = hw->phy.ops.acquire(hw);
389 if (ret_val) {
390 e_dbg("Failed to initialize PHY flow\n");
391 return ret_val;
392 }
393
394 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
395 * inaccessible and resetting the PHY is not blocked, toggle the
396 * LANPHYPC Value bit to force the interconnect to PCIe mode.
397 */
398 switch (hw->mac.type) {
399 case e1000_pch_lpt:
400 if (e1000_phy_is_accessible_pchlan(hw))
401 break;
402
403 /* Before toggling LANPHYPC, see if PHY is accessible by
404 * forcing MAC to SMBus mode first.
405 */
406 mac_reg = er32(CTRL_EXT);
407 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
408 ew32(CTRL_EXT, mac_reg);
409
410 /* fall-through */
411 case e1000_pch2lan:
412 /* Gate automatic PHY configuration by hardware on
413 * non-managed 82579
414 */
415 if ((hw->mac.type == e1000_pch2lan) &&
416 !(fwsm & E1000_ICH_FWSM_FW_VALID))
417 e1000_gate_hw_phy_config_ich8lan(hw, true);
418
419 if (e1000_phy_is_accessible_pchlan(hw)) {
420 if (hw->mac.type == e1000_pch_lpt) {
421 /* Unforce SMBus mode in PHY */
422 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
423 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
424 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
425
426 /* Unforce SMBus mode in MAC */
427 mac_reg = er32(CTRL_EXT);
428 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
429 ew32(CTRL_EXT, mac_reg);
430 }
431 break;
432 }
433
434 /* fall-through */
435 case e1000_pchlan:
436 if ((hw->mac.type == e1000_pchlan) &&
437 (fwsm & E1000_ICH_FWSM_FW_VALID))
438 break;
439
440 if (hw->phy.ops.check_reset_block(hw)) {
441 e_dbg("Required LANPHYPC toggle blocked by ME\n");
442 break;
443 }
444
445 e_dbg("Toggling LANPHYPC\n");
446
447 /* Set Phy Config Counter to 50msec */
448 mac_reg = er32(FEXTNVM3);
449 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
450 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
451 ew32(FEXTNVM3, mac_reg);
452
453 /* Toggle LANPHYPC Value bit */
454 mac_reg = er32(CTRL);
455 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
456 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
457 ew32(CTRL, mac_reg);
458 e1e_flush();
459 udelay(10);
460 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
461 ew32(CTRL, mac_reg);
462 e1e_flush();
463 if (hw->mac.type < e1000_pch_lpt) {
464 msleep(50);
465 } else {
466 u16 count = 20;
467 do {
468 usleep_range(5000, 10000);
469 } while (!(er32(CTRL_EXT) &
470 E1000_CTRL_EXT_LPCD) && count--);
471 }
472 break;
473 default:
474 break;
475 }
476
477 hw->phy.ops.release(hw);
478
479 /* Reset the PHY before any access to it. Doing so, ensures
480 * that the PHY is in a known good state before we read/write
481 * PHY registers. The generic reset is sufficient here,
482 * because we haven't determined the PHY type yet.
483 */
484 ret_val = e1000e_phy_hw_reset_generic(hw);
485
486 /* Ungate automatic PHY configuration on non-managed 82579 */
487 if ((hw->mac.type == e1000_pch2lan) &&
488 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
489 usleep_range(10000, 20000);
490 e1000_gate_hw_phy_config_ich8lan(hw, false);
491 }
492
493 return ret_val;
494 }
495
496 /**
497 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
498 * @hw: pointer to the HW structure
499 *
500 * Initialize family-specific PHY parameters and function pointers.
501 **/
502 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
503 {
504 struct e1000_phy_info *phy = &hw->phy;
505 s32 ret_val = 0;
506
507 phy->addr = 1;
508 phy->reset_delay_us = 100;
509
510 phy->ops.set_page = e1000_set_page_igp;
511 phy->ops.read_reg = e1000_read_phy_reg_hv;
512 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
513 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
514 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
515 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
516 phy->ops.write_reg = e1000_write_phy_reg_hv;
517 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
518 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
519 phy->ops.power_up = e1000_power_up_phy_copper;
520 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
521 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
522
523 phy->id = e1000_phy_unknown;
524
525 ret_val = e1000_init_phy_workarounds_pchlan(hw);
526 if (ret_val)
527 return ret_val;
528
529 if (phy->id == e1000_phy_unknown)
530 switch (hw->mac.type) {
531 default:
532 ret_val = e1000e_get_phy_id(hw);
533 if (ret_val)
534 return ret_val;
535 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
536 break;
537 /* fall-through */
538 case e1000_pch2lan:
539 case e1000_pch_lpt:
540 /* In case the PHY needs to be in mdio slow mode,
541 * set slow mode and try to get the PHY id again.
542 */
543 ret_val = e1000_set_mdio_slow_mode_hv(hw);
544 if (ret_val)
545 return ret_val;
546 ret_val = e1000e_get_phy_id(hw);
547 if (ret_val)
548 return ret_val;
549 break;
550 }
551 phy->type = e1000e_get_phy_type_from_id(phy->id);
552
553 switch (phy->type) {
554 case e1000_phy_82577:
555 case e1000_phy_82579:
556 case e1000_phy_i217:
557 phy->ops.check_polarity = e1000_check_polarity_82577;
558 phy->ops.force_speed_duplex =
559 e1000_phy_force_speed_duplex_82577;
560 phy->ops.get_cable_length = e1000_get_cable_length_82577;
561 phy->ops.get_info = e1000_get_phy_info_82577;
562 phy->ops.commit = e1000e_phy_sw_reset;
563 break;
564 case e1000_phy_82578:
565 phy->ops.check_polarity = e1000_check_polarity_m88;
566 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
567 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
568 phy->ops.get_info = e1000e_get_phy_info_m88;
569 break;
570 default:
571 ret_val = -E1000_ERR_PHY;
572 break;
573 }
574
575 return ret_val;
576 }
577
578 /**
579 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
580 * @hw: pointer to the HW structure
581 *
582 * Initialize family-specific PHY parameters and function pointers.
583 **/
584 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
585 {
586 struct e1000_phy_info *phy = &hw->phy;
587 s32 ret_val;
588 u16 i = 0;
589
590 phy->addr = 1;
591 phy->reset_delay_us = 100;
592
593 phy->ops.power_up = e1000_power_up_phy_copper;
594 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
595
596 /* We may need to do this twice - once for IGP and if that fails,
597 * we'll set BM func pointers and try again
598 */
599 ret_val = e1000e_determine_phy_address(hw);
600 if (ret_val) {
601 phy->ops.write_reg = e1000e_write_phy_reg_bm;
602 phy->ops.read_reg = e1000e_read_phy_reg_bm;
603 ret_val = e1000e_determine_phy_address(hw);
604 if (ret_val) {
605 e_dbg("Cannot determine PHY addr. Erroring out\n");
606 return ret_val;
607 }
608 }
609
610 phy->id = 0;
611 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
612 (i++ < 100)) {
613 usleep_range(1000, 2000);
614 ret_val = e1000e_get_phy_id(hw);
615 if (ret_val)
616 return ret_val;
617 }
618
619 /* Verify phy id */
620 switch (phy->id) {
621 case IGP03E1000_E_PHY_ID:
622 phy->type = e1000_phy_igp_3;
623 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
624 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
625 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
626 phy->ops.get_info = e1000e_get_phy_info_igp;
627 phy->ops.check_polarity = e1000_check_polarity_igp;
628 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
629 break;
630 case IFE_E_PHY_ID:
631 case IFE_PLUS_E_PHY_ID:
632 case IFE_C_E_PHY_ID:
633 phy->type = e1000_phy_ife;
634 phy->autoneg_mask = E1000_ALL_NOT_GIG;
635 phy->ops.get_info = e1000_get_phy_info_ife;
636 phy->ops.check_polarity = e1000_check_polarity_ife;
637 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
638 break;
639 case BME1000_E_PHY_ID:
640 phy->type = e1000_phy_bm;
641 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
642 phy->ops.read_reg = e1000e_read_phy_reg_bm;
643 phy->ops.write_reg = e1000e_write_phy_reg_bm;
644 phy->ops.commit = e1000e_phy_sw_reset;
645 phy->ops.get_info = e1000e_get_phy_info_m88;
646 phy->ops.check_polarity = e1000_check_polarity_m88;
647 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
648 break;
649 default:
650 return -E1000_ERR_PHY;
651 break;
652 }
653
654 return 0;
655 }
656
657 /**
658 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
659 * @hw: pointer to the HW structure
660 *
661 * Initialize family-specific NVM parameters and function
662 * pointers.
663 **/
664 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
665 {
666 struct e1000_nvm_info *nvm = &hw->nvm;
667 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
668 u32 gfpreg, sector_base_addr, sector_end_addr;
669 u16 i;
670
671 /* Can't read flash registers if the register set isn't mapped. */
672 if (!hw->flash_address) {
673 e_dbg("ERROR: Flash registers not mapped\n");
674 return -E1000_ERR_CONFIG;
675 }
676
677 nvm->type = e1000_nvm_flash_sw;
678
679 gfpreg = er32flash(ICH_FLASH_GFPREG);
680
681 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
682 * Add 1 to sector_end_addr since this sector is included in
683 * the overall size.
684 */
685 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
686 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
687
688 /* flash_base_addr is byte-aligned */
689 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
690
691 /* find total size of the NVM, then cut in half since the total
692 * size represents two separate NVM banks.
693 */
694 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
695 << FLASH_SECTOR_ADDR_SHIFT;
696 nvm->flash_bank_size /= 2;
697 /* Adjust to word count */
698 nvm->flash_bank_size /= sizeof(u16);
699
700 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
701
702 /* Clear shadow ram */
703 for (i = 0; i < nvm->word_size; i++) {
704 dev_spec->shadow_ram[i].modified = false;
705 dev_spec->shadow_ram[i].value = 0xFFFF;
706 }
707
708 return 0;
709 }
710
711 /**
712 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
713 * @hw: pointer to the HW structure
714 *
715 * Initialize family-specific MAC parameters and function
716 * pointers.
717 **/
718 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
719 {
720 struct e1000_mac_info *mac = &hw->mac;
721
722 /* Set media type function pointer */
723 hw->phy.media_type = e1000_media_type_copper;
724
725 /* Set mta register count */
726 mac->mta_reg_count = 32;
727 /* Set rar entry count */
728 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
729 if (mac->type == e1000_ich8lan)
730 mac->rar_entry_count--;
731 /* FWSM register */
732 mac->has_fwsm = true;
733 /* ARC subsystem not supported */
734 mac->arc_subsystem_valid = false;
735 /* Adaptive IFS supported */
736 mac->adaptive_ifs = true;
737
738 /* LED and other operations */
739 switch (mac->type) {
740 case e1000_ich8lan:
741 case e1000_ich9lan:
742 case e1000_ich10lan:
743 /* check management mode */
744 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
745 /* ID LED init */
746 mac->ops.id_led_init = e1000e_id_led_init_generic;
747 /* blink LED */
748 mac->ops.blink_led = e1000e_blink_led_generic;
749 /* setup LED */
750 mac->ops.setup_led = e1000e_setup_led_generic;
751 /* cleanup LED */
752 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
753 /* turn on/off LED */
754 mac->ops.led_on = e1000_led_on_ich8lan;
755 mac->ops.led_off = e1000_led_off_ich8lan;
756 break;
757 case e1000_pch2lan:
758 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
759 mac->ops.rar_set = e1000_rar_set_pch2lan;
760 /* fall-through */
761 case e1000_pch_lpt:
762 case e1000_pchlan:
763 /* check management mode */
764 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
765 /* ID LED init */
766 mac->ops.id_led_init = e1000_id_led_init_pchlan;
767 /* setup LED */
768 mac->ops.setup_led = e1000_setup_led_pchlan;
769 /* cleanup LED */
770 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
771 /* turn on/off LED */
772 mac->ops.led_on = e1000_led_on_pchlan;
773 mac->ops.led_off = e1000_led_off_pchlan;
774 break;
775 default:
776 break;
777 }
778
779 if (mac->type == e1000_pch_lpt) {
780 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
781 mac->ops.rar_set = e1000_rar_set_pch_lpt;
782 }
783
784 /* Enable PCS Lock-loss workaround for ICH8 */
785 if (mac->type == e1000_ich8lan)
786 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
787
788 /* Gate automatic PHY configuration by hardware on managed
789 * 82579 and i217
790 */
791 if ((mac->type == e1000_pch2lan || mac->type == e1000_pch_lpt) &&
792 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
793 e1000_gate_hw_phy_config_ich8lan(hw, true);
794
795 return 0;
796 }
797
798 /**
799 * __e1000_access_emi_reg_locked - Read/write EMI register
800 * @hw: pointer to the HW structure
801 * @addr: EMI address to program
802 * @data: pointer to value to read/write from/to the EMI address
803 * @read: boolean flag to indicate read or write
804 *
805 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
806 **/
807 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
808 u16 *data, bool read)
809 {
810 s32 ret_val = 0;
811
812 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
813 if (ret_val)
814 return ret_val;
815
816 if (read)
817 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
818 else
819 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
820
821 return ret_val;
822 }
823
824 /**
825 * e1000_read_emi_reg_locked - Read Extended Management Interface register
826 * @hw: pointer to the HW structure
827 * @addr: EMI address to program
828 * @data: value to be read from the EMI address
829 *
830 * Assumes the SW/FW/HW Semaphore is already acquired.
831 **/
832 static s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
833 {
834 return __e1000_access_emi_reg_locked(hw, addr, data, true);
835 }
836
837 /**
838 * e1000_write_emi_reg_locked - Write Extended Management Interface register
839 * @hw: pointer to the HW structure
840 * @addr: EMI address to program
841 * @data: value to be written to the EMI address
842 *
843 * Assumes the SW/FW/HW Semaphore is already acquired.
844 **/
845 static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
846 {
847 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
848 }
849
850 /**
851 * e1000_set_eee_pchlan - Enable/disable EEE support
852 * @hw: pointer to the HW structure
853 *
854 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
855 * the link and the EEE capabilities of the link partner. The LPI Control
856 * register bits will remain set only if/when link is up.
857 **/
858 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
859 {
860 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
861 s32 ret_val;
862 u16 lpi_ctrl;
863
864 if ((hw->phy.type != e1000_phy_82579) &&
865 (hw->phy.type != e1000_phy_i217))
866 return 0;
867
868 ret_val = hw->phy.ops.acquire(hw);
869 if (ret_val)
870 return ret_val;
871
872 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
873 if (ret_val)
874 goto release;
875
876 /* Clear bits that enable EEE in various speeds */
877 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
878
879 /* Enable EEE if not disabled by user */
880 if (!dev_spec->eee_disable) {
881 u16 lpa, pcs_status, data;
882
883 /* Save off link partner's EEE ability */
884 switch (hw->phy.type) {
885 case e1000_phy_82579:
886 lpa = I82579_EEE_LP_ABILITY;
887 pcs_status = I82579_EEE_PCS_STATUS;
888 break;
889 case e1000_phy_i217:
890 lpa = I217_EEE_LP_ABILITY;
891 pcs_status = I217_EEE_PCS_STATUS;
892 break;
893 default:
894 ret_val = -E1000_ERR_PHY;
895 goto release;
896 }
897 ret_val = e1000_read_emi_reg_locked(hw, lpa,
898 &dev_spec->eee_lp_ability);
899 if (ret_val)
900 goto release;
901
902 /* Enable EEE only for speeds in which the link partner is
903 * EEE capable.
904 */
905 if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
906 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
907
908 if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
909 e1e_rphy_locked(hw, PHY_LP_ABILITY, &data);
910 if (data & NWAY_LPAR_100TX_FD_CAPS)
911 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
912 else
913 /* EEE is not supported in 100Half, so ignore
914 * partner's EEE in 100 ability if full-duplex
915 * is not advertised.
916 */
917 dev_spec->eee_lp_ability &=
918 ~I82579_EEE_100_SUPPORTED;
919 }
920
921 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
922 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
923 if (ret_val)
924 goto release;
925 }
926
927 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
928 release:
929 hw->phy.ops.release(hw);
930
931 return ret_val;
932 }
933
934 /**
935 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
936 * @hw: pointer to the HW structure
937 *
938 * Checks to see of the link status of the hardware has changed. If a
939 * change in link status has been detected, then we read the PHY registers
940 * to get the current speed/duplex if link exists.
941 **/
942 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
943 {
944 struct e1000_mac_info *mac = &hw->mac;
945 s32 ret_val;
946 bool link;
947 u16 phy_reg;
948
949 /* We only want to go out to the PHY registers to see if Auto-Neg
950 * has completed and/or if our link status has changed. The
951 * get_link_status flag is set upon receiving a Link Status
952 * Change or Rx Sequence Error interrupt.
953 */
954 if (!mac->get_link_status)
955 return 0;
956
957 /* First we want to see if the MII Status Register reports
958 * link. If so, then we want to get the current speed/duplex
959 * of the PHY.
960 */
961 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
962 if (ret_val)
963 return ret_val;
964
965 if (hw->mac.type == e1000_pchlan) {
966 ret_val = e1000_k1_gig_workaround_hv(hw, link);
967 if (ret_val)
968 return ret_val;
969 }
970
971 /* Clear link partner's EEE ability */
972 hw->dev_spec.ich8lan.eee_lp_ability = 0;
973
974 if (!link)
975 return 0; /* No link detected */
976
977 mac->get_link_status = false;
978
979 switch (hw->mac.type) {
980 case e1000_pch2lan:
981 ret_val = e1000_k1_workaround_lv(hw);
982 if (ret_val)
983 return ret_val;
984 /* fall-thru */
985 case e1000_pchlan:
986 if (hw->phy.type == e1000_phy_82578) {
987 ret_val = e1000_link_stall_workaround_hv(hw);
988 if (ret_val)
989 return ret_val;
990 }
991
992 /* Workaround for PCHx parts in half-duplex:
993 * Set the number of preambles removed from the packet
994 * when it is passed from the PHY to the MAC to prevent
995 * the MAC from misinterpreting the packet type.
996 */
997 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
998 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
999
1000 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1001 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1002
1003 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1004 break;
1005 default:
1006 break;
1007 }
1008
1009 /* Check if there was DownShift, must be checked
1010 * immediately after link-up
1011 */
1012 e1000e_check_downshift(hw);
1013
1014 /* Enable/Disable EEE after link up */
1015 ret_val = e1000_set_eee_pchlan(hw);
1016 if (ret_val)
1017 return ret_val;
1018
1019 /* If we are forcing speed/duplex, then we simply return since
1020 * we have already determined whether we have link or not.
1021 */
1022 if (!mac->autoneg)
1023 return -E1000_ERR_CONFIG;
1024
1025 /* Auto-Neg is enabled. Auto Speed Detection takes care
1026 * of MAC speed/duplex configuration. So we only need to
1027 * configure Collision Distance in the MAC.
1028 */
1029 mac->ops.config_collision_dist(hw);
1030
1031 /* Configure Flow Control now that Auto-Neg has completed.
1032 * First, we need to restore the desired flow control
1033 * settings because we may have had to re-autoneg with a
1034 * different link partner.
1035 */
1036 ret_val = e1000e_config_fc_after_link_up(hw);
1037 if (ret_val)
1038 e_dbg("Error configuring flow control\n");
1039
1040 return ret_val;
1041 }
1042
1043 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1044 {
1045 struct e1000_hw *hw = &adapter->hw;
1046 s32 rc;
1047
1048 rc = e1000_init_mac_params_ich8lan(hw);
1049 if (rc)
1050 return rc;
1051
1052 rc = e1000_init_nvm_params_ich8lan(hw);
1053 if (rc)
1054 return rc;
1055
1056 switch (hw->mac.type) {
1057 case e1000_ich8lan:
1058 case e1000_ich9lan:
1059 case e1000_ich10lan:
1060 rc = e1000_init_phy_params_ich8lan(hw);
1061 break;
1062 case e1000_pchlan:
1063 case e1000_pch2lan:
1064 case e1000_pch_lpt:
1065 rc = e1000_init_phy_params_pchlan(hw);
1066 break;
1067 default:
1068 break;
1069 }
1070 if (rc)
1071 return rc;
1072
1073 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1074 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1075 */
1076 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1077 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1078 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1079 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1080 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
1081
1082 hw->mac.ops.blink_led = NULL;
1083 }
1084
1085 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1086 (adapter->hw.phy.type != e1000_phy_ife))
1087 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1088
1089 /* Enable workaround for 82579 w/ ME enabled */
1090 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1091 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1092 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1093
1094 /* Disable EEE by default until IEEE802.3az spec is finalized */
1095 if (adapter->flags2 & FLAG2_HAS_EEE)
1096 adapter->hw.dev_spec.ich8lan.eee_disable = true;
1097
1098 return 0;
1099 }
1100
1101 static DEFINE_MUTEX(nvm_mutex);
1102
1103 /**
1104 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1105 * @hw: pointer to the HW structure
1106 *
1107 * Acquires the mutex for performing NVM operations.
1108 **/
1109 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
1110 {
1111 mutex_lock(&nvm_mutex);
1112
1113 return 0;
1114 }
1115
1116 /**
1117 * e1000_release_nvm_ich8lan - Release NVM mutex
1118 * @hw: pointer to the HW structure
1119 *
1120 * Releases the mutex used while performing NVM operations.
1121 **/
1122 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
1123 {
1124 mutex_unlock(&nvm_mutex);
1125 }
1126
1127 /**
1128 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1129 * @hw: pointer to the HW structure
1130 *
1131 * Acquires the software control flag for performing PHY and select
1132 * MAC CSR accesses.
1133 **/
1134 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1135 {
1136 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1137 s32 ret_val = 0;
1138
1139 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1140 &hw->adapter->state)) {
1141 e_dbg("contention for Phy access\n");
1142 return -E1000_ERR_PHY;
1143 }
1144
1145 while (timeout) {
1146 extcnf_ctrl = er32(EXTCNF_CTRL);
1147 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1148 break;
1149
1150 mdelay(1);
1151 timeout--;
1152 }
1153
1154 if (!timeout) {
1155 e_dbg("SW has already locked the resource.\n");
1156 ret_val = -E1000_ERR_CONFIG;
1157 goto out;
1158 }
1159
1160 timeout = SW_FLAG_TIMEOUT;
1161
1162 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1163 ew32(EXTCNF_CTRL, extcnf_ctrl);
1164
1165 while (timeout) {
1166 extcnf_ctrl = er32(EXTCNF_CTRL);
1167 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1168 break;
1169
1170 mdelay(1);
1171 timeout--;
1172 }
1173
1174 if (!timeout) {
1175 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1176 er32(FWSM), extcnf_ctrl);
1177 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1178 ew32(EXTCNF_CTRL, extcnf_ctrl);
1179 ret_val = -E1000_ERR_CONFIG;
1180 goto out;
1181 }
1182
1183 out:
1184 if (ret_val)
1185 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1186
1187 return ret_val;
1188 }
1189
1190 /**
1191 * e1000_release_swflag_ich8lan - Release software control flag
1192 * @hw: pointer to the HW structure
1193 *
1194 * Releases the software control flag for performing PHY and select
1195 * MAC CSR accesses.
1196 **/
1197 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1198 {
1199 u32 extcnf_ctrl;
1200
1201 extcnf_ctrl = er32(EXTCNF_CTRL);
1202
1203 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1204 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1205 ew32(EXTCNF_CTRL, extcnf_ctrl);
1206 } else {
1207 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1208 }
1209
1210 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1211 }
1212
1213 /**
1214 * e1000_check_mng_mode_ich8lan - Checks management mode
1215 * @hw: pointer to the HW structure
1216 *
1217 * This checks if the adapter has any manageability enabled.
1218 * This is a function pointer entry point only called by read/write
1219 * routines for the PHY and NVM parts.
1220 **/
1221 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1222 {
1223 u32 fwsm;
1224
1225 fwsm = er32(FWSM);
1226 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1227 ((fwsm & E1000_FWSM_MODE_MASK) ==
1228 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1229 }
1230
1231 /**
1232 * e1000_check_mng_mode_pchlan - Checks management mode
1233 * @hw: pointer to the HW structure
1234 *
1235 * This checks if the adapter has iAMT enabled.
1236 * This is a function pointer entry point only called by read/write
1237 * routines for the PHY and NVM parts.
1238 **/
1239 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1240 {
1241 u32 fwsm;
1242
1243 fwsm = er32(FWSM);
1244 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1245 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1246 }
1247
1248 /**
1249 * e1000_rar_set_pch2lan - Set receive address register
1250 * @hw: pointer to the HW structure
1251 * @addr: pointer to the receive address
1252 * @index: receive address array register
1253 *
1254 * Sets the receive address array register at index to the address passed
1255 * in by addr. For 82579, RAR[0] is the base address register that is to
1256 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1257 * Use SHRA[0-3] in place of those reserved for ME.
1258 **/
1259 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1260 {
1261 u32 rar_low, rar_high;
1262
1263 /* HW expects these in little endian so we reverse the byte order
1264 * from network order (big endian) to little endian
1265 */
1266 rar_low = ((u32)addr[0] |
1267 ((u32)addr[1] << 8) |
1268 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1269
1270 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1271
1272 /* If MAC address zero, no need to set the AV bit */
1273 if (rar_low || rar_high)
1274 rar_high |= E1000_RAH_AV;
1275
1276 if (index == 0) {
1277 ew32(RAL(index), rar_low);
1278 e1e_flush();
1279 ew32(RAH(index), rar_high);
1280 e1e_flush();
1281 return;
1282 }
1283
1284 if (index < hw->mac.rar_entry_count) {
1285 s32 ret_val;
1286
1287 ret_val = e1000_acquire_swflag_ich8lan(hw);
1288 if (ret_val)
1289 goto out;
1290
1291 ew32(SHRAL(index - 1), rar_low);
1292 e1e_flush();
1293 ew32(SHRAH(index - 1), rar_high);
1294 e1e_flush();
1295
1296 e1000_release_swflag_ich8lan(hw);
1297
1298 /* verify the register updates */
1299 if ((er32(SHRAL(index - 1)) == rar_low) &&
1300 (er32(SHRAH(index - 1)) == rar_high))
1301 return;
1302
1303 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1304 (index - 1), er32(FWSM));
1305 }
1306
1307 out:
1308 e_dbg("Failed to write receive address at index %d\n", index);
1309 }
1310
1311 /**
1312 * e1000_rar_set_pch_lpt - Set receive address registers
1313 * @hw: pointer to the HW structure
1314 * @addr: pointer to the receive address
1315 * @index: receive address array register
1316 *
1317 * Sets the receive address register array at index to the address passed
1318 * in by addr. For LPT, RAR[0] is the base address register that is to
1319 * contain the MAC address. SHRA[0-10] are the shared receive address
1320 * registers that are shared between the Host and manageability engine (ME).
1321 **/
1322 static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1323 {
1324 u32 rar_low, rar_high;
1325 u32 wlock_mac;
1326
1327 /* HW expects these in little endian so we reverse the byte order
1328 * from network order (big endian) to little endian
1329 */
1330 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1331 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1332
1333 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1334
1335 /* If MAC address zero, no need to set the AV bit */
1336 if (rar_low || rar_high)
1337 rar_high |= E1000_RAH_AV;
1338
1339 if (index == 0) {
1340 ew32(RAL(index), rar_low);
1341 e1e_flush();
1342 ew32(RAH(index), rar_high);
1343 e1e_flush();
1344 return;
1345 }
1346
1347 /* The manageability engine (ME) can lock certain SHRAR registers that
1348 * it is using - those registers are unavailable for use.
1349 */
1350 if (index < hw->mac.rar_entry_count) {
1351 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1352 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1353
1354 /* Check if all SHRAR registers are locked */
1355 if (wlock_mac == 1)
1356 goto out;
1357
1358 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1359 s32 ret_val;
1360
1361 ret_val = e1000_acquire_swflag_ich8lan(hw);
1362
1363 if (ret_val)
1364 goto out;
1365
1366 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1367 e1e_flush();
1368 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1369 e1e_flush();
1370
1371 e1000_release_swflag_ich8lan(hw);
1372
1373 /* verify the register updates */
1374 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1375 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1376 return;
1377 }
1378 }
1379
1380 out:
1381 e_dbg("Failed to write receive address at index %d\n", index);
1382 }
1383
1384 /**
1385 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1386 * @hw: pointer to the HW structure
1387 *
1388 * Checks if firmware is blocking the reset of the PHY.
1389 * This is a function pointer entry point only called by
1390 * reset routines.
1391 **/
1392 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
1393 {
1394 u32 fwsm;
1395
1396 fwsm = er32(FWSM);
1397
1398 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
1399 }
1400
1401 /**
1402 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1403 * @hw: pointer to the HW structure
1404 *
1405 * Assumes semaphore already acquired.
1406 *
1407 **/
1408 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1409 {
1410 u16 phy_data;
1411 u32 strap = er32(STRAP);
1412 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
1413 E1000_STRAP_SMT_FREQ_SHIFT;
1414 s32 ret_val = 0;
1415
1416 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1417
1418 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1419 if (ret_val)
1420 return ret_val;
1421
1422 phy_data &= ~HV_SMB_ADDR_MASK;
1423 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1424 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1425
1426 if (hw->phy.type == e1000_phy_i217) {
1427 /* Restore SMBus frequency */
1428 if (freq--) {
1429 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
1430 phy_data |= (freq & (1 << 0)) <<
1431 HV_SMB_ADDR_FREQ_LOW_SHIFT;
1432 phy_data |= (freq & (1 << 1)) <<
1433 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
1434 } else {
1435 e_dbg("Unsupported SMB frequency in PHY\n");
1436 }
1437 }
1438
1439 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1440 }
1441
1442 /**
1443 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1444 * @hw: pointer to the HW structure
1445 *
1446 * SW should configure the LCD from the NVM extended configuration region
1447 * as a workaround for certain parts.
1448 **/
1449 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1450 {
1451 struct e1000_phy_info *phy = &hw->phy;
1452 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1453 s32 ret_val = 0;
1454 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1455
1456 /* Initialize the PHY from the NVM on ICH platforms. This
1457 * is needed due to an issue where the NVM configuration is
1458 * not properly autoloaded after power transitions.
1459 * Therefore, after each PHY reset, we will load the
1460 * configuration data out of the NVM manually.
1461 */
1462 switch (hw->mac.type) {
1463 case e1000_ich8lan:
1464 if (phy->type != e1000_phy_igp_3)
1465 return ret_val;
1466
1467 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1468 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1469 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1470 break;
1471 }
1472 /* Fall-thru */
1473 case e1000_pchlan:
1474 case e1000_pch2lan:
1475 case e1000_pch_lpt:
1476 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1477 break;
1478 default:
1479 return ret_val;
1480 }
1481
1482 ret_val = hw->phy.ops.acquire(hw);
1483 if (ret_val)
1484 return ret_val;
1485
1486 data = er32(FEXTNVM);
1487 if (!(data & sw_cfg_mask))
1488 goto release;
1489
1490 /* Make sure HW does not configure LCD from PHY
1491 * extended configuration before SW configuration
1492 */
1493 data = er32(EXTCNF_CTRL);
1494 if ((hw->mac.type < e1000_pch2lan) &&
1495 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
1496 goto release;
1497
1498 cnf_size = er32(EXTCNF_SIZE);
1499 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1500 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1501 if (!cnf_size)
1502 goto release;
1503
1504 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1505 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1506
1507 if (((hw->mac.type == e1000_pchlan) &&
1508 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
1509 (hw->mac.type > e1000_pchlan)) {
1510 /* HW configures the SMBus address and LEDs when the
1511 * OEM and LCD Write Enable bits are set in the NVM.
1512 * When both NVM bits are cleared, SW will configure
1513 * them instead.
1514 */
1515 ret_val = e1000_write_smbus_addr(hw);
1516 if (ret_val)
1517 goto release;
1518
1519 data = er32(LEDCTL);
1520 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1521 (u16)data);
1522 if (ret_val)
1523 goto release;
1524 }
1525
1526 /* Configure LCD from extended configuration region. */
1527
1528 /* cnf_base_addr is in DWORD */
1529 word_addr = (u16)(cnf_base_addr << 1);
1530
1531 for (i = 0; i < cnf_size; i++) {
1532 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1533 &reg_data);
1534 if (ret_val)
1535 goto release;
1536
1537 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1538 1, &reg_addr);
1539 if (ret_val)
1540 goto release;
1541
1542 /* Save off the PHY page for future writes. */
1543 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1544 phy_page = reg_data;
1545 continue;
1546 }
1547
1548 reg_addr &= PHY_REG_MASK;
1549 reg_addr |= phy_page;
1550
1551 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
1552 if (ret_val)
1553 goto release;
1554 }
1555
1556 release:
1557 hw->phy.ops.release(hw);
1558 return ret_val;
1559 }
1560
1561 /**
1562 * e1000_k1_gig_workaround_hv - K1 Si workaround
1563 * @hw: pointer to the HW structure
1564 * @link: link up bool flag
1565 *
1566 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1567 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1568 * If link is down, the function will restore the default K1 setting located
1569 * in the NVM.
1570 **/
1571 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1572 {
1573 s32 ret_val = 0;
1574 u16 status_reg = 0;
1575 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1576
1577 if (hw->mac.type != e1000_pchlan)
1578 return 0;
1579
1580 /* Wrap the whole flow with the sw flag */
1581 ret_val = hw->phy.ops.acquire(hw);
1582 if (ret_val)
1583 return ret_val;
1584
1585 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1586 if (link) {
1587 if (hw->phy.type == e1000_phy_82578) {
1588 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
1589 &status_reg);
1590 if (ret_val)
1591 goto release;
1592
1593 status_reg &= BM_CS_STATUS_LINK_UP |
1594 BM_CS_STATUS_RESOLVED |
1595 BM_CS_STATUS_SPEED_MASK;
1596
1597 if (status_reg == (BM_CS_STATUS_LINK_UP |
1598 BM_CS_STATUS_RESOLVED |
1599 BM_CS_STATUS_SPEED_1000))
1600 k1_enable = false;
1601 }
1602
1603 if (hw->phy.type == e1000_phy_82577) {
1604 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
1605 if (ret_val)
1606 goto release;
1607
1608 status_reg &= HV_M_STATUS_LINK_UP |
1609 HV_M_STATUS_AUTONEG_COMPLETE |
1610 HV_M_STATUS_SPEED_MASK;
1611
1612 if (status_reg == (HV_M_STATUS_LINK_UP |
1613 HV_M_STATUS_AUTONEG_COMPLETE |
1614 HV_M_STATUS_SPEED_1000))
1615 k1_enable = false;
1616 }
1617
1618 /* Link stall fix for link up */
1619 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
1620 if (ret_val)
1621 goto release;
1622
1623 } else {
1624 /* Link stall fix for link down */
1625 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
1626 if (ret_val)
1627 goto release;
1628 }
1629
1630 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1631
1632 release:
1633 hw->phy.ops.release(hw);
1634
1635 return ret_val;
1636 }
1637
1638 /**
1639 * e1000_configure_k1_ich8lan - Configure K1 power state
1640 * @hw: pointer to the HW structure
1641 * @enable: K1 state to configure
1642 *
1643 * Configure the K1 power state based on the provided parameter.
1644 * Assumes semaphore already acquired.
1645 *
1646 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1647 **/
1648 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1649 {
1650 s32 ret_val = 0;
1651 u32 ctrl_reg = 0;
1652 u32 ctrl_ext = 0;
1653 u32 reg = 0;
1654 u16 kmrn_reg = 0;
1655
1656 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1657 &kmrn_reg);
1658 if (ret_val)
1659 return ret_val;
1660
1661 if (k1_enable)
1662 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1663 else
1664 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1665
1666 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
1667 kmrn_reg);
1668 if (ret_val)
1669 return ret_val;
1670
1671 udelay(20);
1672 ctrl_ext = er32(CTRL_EXT);
1673 ctrl_reg = er32(CTRL);
1674
1675 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1676 reg |= E1000_CTRL_FRCSPD;
1677 ew32(CTRL, reg);
1678
1679 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1680 e1e_flush();
1681 udelay(20);
1682 ew32(CTRL, ctrl_reg);
1683 ew32(CTRL_EXT, ctrl_ext);
1684 e1e_flush();
1685 udelay(20);
1686
1687 return 0;
1688 }
1689
1690 /**
1691 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1692 * @hw: pointer to the HW structure
1693 * @d0_state: boolean if entering d0 or d3 device state
1694 *
1695 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1696 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1697 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1698 **/
1699 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1700 {
1701 s32 ret_val = 0;
1702 u32 mac_reg;
1703 u16 oem_reg;
1704
1705 if (hw->mac.type < e1000_pchlan)
1706 return ret_val;
1707
1708 ret_val = hw->phy.ops.acquire(hw);
1709 if (ret_val)
1710 return ret_val;
1711
1712 if (hw->mac.type == e1000_pchlan) {
1713 mac_reg = er32(EXTCNF_CTRL);
1714 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1715 goto release;
1716 }
1717
1718 mac_reg = er32(FEXTNVM);
1719 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1720 goto release;
1721
1722 mac_reg = er32(PHY_CTRL);
1723
1724 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
1725 if (ret_val)
1726 goto release;
1727
1728 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1729
1730 if (d0_state) {
1731 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1732 oem_reg |= HV_OEM_BITS_GBE_DIS;
1733
1734 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1735 oem_reg |= HV_OEM_BITS_LPLU;
1736 } else {
1737 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1738 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1739 oem_reg |= HV_OEM_BITS_GBE_DIS;
1740
1741 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1742 E1000_PHY_CTRL_NOND0A_LPLU))
1743 oem_reg |= HV_OEM_BITS_LPLU;
1744 }
1745
1746 /* Set Restart auto-neg to activate the bits */
1747 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
1748 !hw->phy.ops.check_reset_block(hw))
1749 oem_reg |= HV_OEM_BITS_RESTART_AN;
1750
1751 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
1752
1753 release:
1754 hw->phy.ops.release(hw);
1755
1756 return ret_val;
1757 }
1758
1759
1760 /**
1761 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1762 * @hw: pointer to the HW structure
1763 **/
1764 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1765 {
1766 s32 ret_val;
1767 u16 data;
1768
1769 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1770 if (ret_val)
1771 return ret_val;
1772
1773 data |= HV_KMRN_MDIO_SLOW;
1774
1775 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1776
1777 return ret_val;
1778 }
1779
1780 /**
1781 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1782 * done after every PHY reset.
1783 **/
1784 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1785 {
1786 s32 ret_val = 0;
1787 u16 phy_data;
1788
1789 if (hw->mac.type != e1000_pchlan)
1790 return 0;
1791
1792 /* Set MDIO slow mode before any other MDIO access */
1793 if (hw->phy.type == e1000_phy_82577) {
1794 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1795 if (ret_val)
1796 return ret_val;
1797 }
1798
1799 if (((hw->phy.type == e1000_phy_82577) &&
1800 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1801 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1802 /* Disable generation of early preamble */
1803 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1804 if (ret_val)
1805 return ret_val;
1806
1807 /* Preamble tuning for SSC */
1808 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1809 if (ret_val)
1810 return ret_val;
1811 }
1812
1813 if (hw->phy.type == e1000_phy_82578) {
1814 /* Return registers to default by doing a soft reset then
1815 * writing 0x3140 to the control register.
1816 */
1817 if (hw->phy.revision < 2) {
1818 e1000e_phy_sw_reset(hw);
1819 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1820 }
1821 }
1822
1823 /* Select page 0 */
1824 ret_val = hw->phy.ops.acquire(hw);
1825 if (ret_val)
1826 return ret_val;
1827
1828 hw->phy.addr = 1;
1829 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1830 hw->phy.ops.release(hw);
1831 if (ret_val)
1832 return ret_val;
1833
1834 /* Configure the K1 Si workaround during phy reset assuming there is
1835 * link so that it disables K1 if link is in 1Gbps.
1836 */
1837 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1838 if (ret_val)
1839 return ret_val;
1840
1841 /* Workaround for link disconnects on a busy hub in half duplex */
1842 ret_val = hw->phy.ops.acquire(hw);
1843 if (ret_val)
1844 return ret_val;
1845 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1846 if (ret_val)
1847 goto release;
1848 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
1849 if (ret_val)
1850 goto release;
1851
1852 /* set MSE higher to enable link to stay up when noise is high */
1853 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
1854 release:
1855 hw->phy.ops.release(hw);
1856
1857 return ret_val;
1858 }
1859
1860 /**
1861 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1862 * @hw: pointer to the HW structure
1863 **/
1864 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1865 {
1866 u32 mac_reg;
1867 u16 i, phy_reg = 0;
1868 s32 ret_val;
1869
1870 ret_val = hw->phy.ops.acquire(hw);
1871 if (ret_val)
1872 return;
1873 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1874 if (ret_val)
1875 goto release;
1876
1877 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1878 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1879 mac_reg = er32(RAL(i));
1880 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1881 (u16)(mac_reg & 0xFFFF));
1882 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1883 (u16)((mac_reg >> 16) & 0xFFFF));
1884
1885 mac_reg = er32(RAH(i));
1886 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1887 (u16)(mac_reg & 0xFFFF));
1888 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1889 (u16)((mac_reg & E1000_RAH_AV)
1890 >> 16));
1891 }
1892
1893 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1894
1895 release:
1896 hw->phy.ops.release(hw);
1897 }
1898
1899 /**
1900 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1901 * with 82579 PHY
1902 * @hw: pointer to the HW structure
1903 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1904 **/
1905 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1906 {
1907 s32 ret_val = 0;
1908 u16 phy_reg, data;
1909 u32 mac_reg;
1910 u16 i;
1911
1912 if (hw->mac.type < e1000_pch2lan)
1913 return 0;
1914
1915 /* disable Rx path while enabling/disabling workaround */
1916 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1917 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1918 if (ret_val)
1919 return ret_val;
1920
1921 if (enable) {
1922 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
1923 * SHRAL/H) and initial CRC values to the MAC
1924 */
1925 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1926 u8 mac_addr[ETH_ALEN] = {0};
1927 u32 addr_high, addr_low;
1928
1929 addr_high = er32(RAH(i));
1930 if (!(addr_high & E1000_RAH_AV))
1931 continue;
1932 addr_low = er32(RAL(i));
1933 mac_addr[0] = (addr_low & 0xFF);
1934 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1935 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1936 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1937 mac_addr[4] = (addr_high & 0xFF);
1938 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1939
1940 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1941 }
1942
1943 /* Write Rx addresses to the PHY */
1944 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1945
1946 /* Enable jumbo frame workaround in the MAC */
1947 mac_reg = er32(FFLT_DBG);
1948 mac_reg &= ~(1 << 14);
1949 mac_reg |= (7 << 15);
1950 ew32(FFLT_DBG, mac_reg);
1951
1952 mac_reg = er32(RCTL);
1953 mac_reg |= E1000_RCTL_SECRC;
1954 ew32(RCTL, mac_reg);
1955
1956 ret_val = e1000e_read_kmrn_reg(hw,
1957 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1958 &data);
1959 if (ret_val)
1960 return ret_val;
1961 ret_val = e1000e_write_kmrn_reg(hw,
1962 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1963 data | (1 << 0));
1964 if (ret_val)
1965 return ret_val;
1966 ret_val = e1000e_read_kmrn_reg(hw,
1967 E1000_KMRNCTRLSTA_HD_CTRL,
1968 &data);
1969 if (ret_val)
1970 return ret_val;
1971 data &= ~(0xF << 8);
1972 data |= (0xB << 8);
1973 ret_val = e1000e_write_kmrn_reg(hw,
1974 E1000_KMRNCTRLSTA_HD_CTRL,
1975 data);
1976 if (ret_val)
1977 return ret_val;
1978
1979 /* Enable jumbo frame workaround in the PHY */
1980 e1e_rphy(hw, PHY_REG(769, 23), &data);
1981 data &= ~(0x7F << 5);
1982 data |= (0x37 << 5);
1983 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1984 if (ret_val)
1985 return ret_val;
1986 e1e_rphy(hw, PHY_REG(769, 16), &data);
1987 data &= ~(1 << 13);
1988 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1989 if (ret_val)
1990 return ret_val;
1991 e1e_rphy(hw, PHY_REG(776, 20), &data);
1992 data &= ~(0x3FF << 2);
1993 data |= (0x1A << 2);
1994 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1995 if (ret_val)
1996 return ret_val;
1997 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1998 if (ret_val)
1999 return ret_val;
2000 e1e_rphy(hw, HV_PM_CTRL, &data);
2001 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2002 if (ret_val)
2003 return ret_val;
2004 } else {
2005 /* Write MAC register values back to h/w defaults */
2006 mac_reg = er32(FFLT_DBG);
2007 mac_reg &= ~(0xF << 14);
2008 ew32(FFLT_DBG, mac_reg);
2009
2010 mac_reg = er32(RCTL);
2011 mac_reg &= ~E1000_RCTL_SECRC;
2012 ew32(RCTL, mac_reg);
2013
2014 ret_val = e1000e_read_kmrn_reg(hw,
2015 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2016 &data);
2017 if (ret_val)
2018 return ret_val;
2019 ret_val = e1000e_write_kmrn_reg(hw,
2020 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2021 data & ~(1 << 0));
2022 if (ret_val)
2023 return ret_val;
2024 ret_val = e1000e_read_kmrn_reg(hw,
2025 E1000_KMRNCTRLSTA_HD_CTRL,
2026 &data);
2027 if (ret_val)
2028 return ret_val;
2029 data &= ~(0xF << 8);
2030 data |= (0xB << 8);
2031 ret_val = e1000e_write_kmrn_reg(hw,
2032 E1000_KMRNCTRLSTA_HD_CTRL,
2033 data);
2034 if (ret_val)
2035 return ret_val;
2036
2037 /* Write PHY register values back to h/w defaults */
2038 e1e_rphy(hw, PHY_REG(769, 23), &data);
2039 data &= ~(0x7F << 5);
2040 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2041 if (ret_val)
2042 return ret_val;
2043 e1e_rphy(hw, PHY_REG(769, 16), &data);
2044 data |= (1 << 13);
2045 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2046 if (ret_val)
2047 return ret_val;
2048 e1e_rphy(hw, PHY_REG(776, 20), &data);
2049 data &= ~(0x3FF << 2);
2050 data |= (0x8 << 2);
2051 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2052 if (ret_val)
2053 return ret_val;
2054 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2055 if (ret_val)
2056 return ret_val;
2057 e1e_rphy(hw, HV_PM_CTRL, &data);
2058 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2059 if (ret_val)
2060 return ret_val;
2061 }
2062
2063 /* re-enable Rx path after enabling/disabling workaround */
2064 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2065 }
2066
2067 /**
2068 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2069 * done after every PHY reset.
2070 **/
2071 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2072 {
2073 s32 ret_val = 0;
2074
2075 if (hw->mac.type != e1000_pch2lan)
2076 return 0;
2077
2078 /* Set MDIO slow mode before any other MDIO access */
2079 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2080
2081 ret_val = hw->phy.ops.acquire(hw);
2082 if (ret_val)
2083 return ret_val;
2084 /* set MSE higher to enable link to stay up when noise is high */
2085 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2086 if (ret_val)
2087 goto release;
2088 /* drop link after 5 times MSE threshold was reached */
2089 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2090 release:
2091 hw->phy.ops.release(hw);
2092
2093 return ret_val;
2094 }
2095
2096 /**
2097 * e1000_k1_gig_workaround_lv - K1 Si workaround
2098 * @hw: pointer to the HW structure
2099 *
2100 * Workaround to set the K1 beacon duration for 82579 parts
2101 **/
2102 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2103 {
2104 s32 ret_val = 0;
2105 u16 status_reg = 0;
2106 u32 mac_reg;
2107 u16 phy_reg;
2108
2109 if (hw->mac.type != e1000_pch2lan)
2110 return 0;
2111
2112 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2113 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2114 if (ret_val)
2115 return ret_val;
2116
2117 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2118 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2119 mac_reg = er32(FEXTNVM4);
2120 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2121
2122 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
2123 if (ret_val)
2124 return ret_val;
2125
2126 if (status_reg & HV_M_STATUS_SPEED_1000) {
2127 u16 pm_phy_reg;
2128
2129 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
2130 phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2131 /* LV 1G Packet drop issue wa */
2132 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2133 if (ret_val)
2134 return ret_val;
2135 pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA;
2136 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2137 if (ret_val)
2138 return ret_val;
2139 } else {
2140 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2141 phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
2142 }
2143 ew32(FEXTNVM4, mac_reg);
2144 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
2145 }
2146
2147 return ret_val;
2148 }
2149
2150 /**
2151 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2152 * @hw: pointer to the HW structure
2153 * @gate: boolean set to true to gate, false to ungate
2154 *
2155 * Gate/ungate the automatic PHY configuration via hardware; perform
2156 * the configuration via software instead.
2157 **/
2158 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2159 {
2160 u32 extcnf_ctrl;
2161
2162 if (hw->mac.type < e1000_pch2lan)
2163 return;
2164
2165 extcnf_ctrl = er32(EXTCNF_CTRL);
2166
2167 if (gate)
2168 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2169 else
2170 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2171
2172 ew32(EXTCNF_CTRL, extcnf_ctrl);
2173 }
2174
2175 /**
2176 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2177 * @hw: pointer to the HW structure
2178 *
2179 * Check the appropriate indication the MAC has finished configuring the
2180 * PHY after a software reset.
2181 **/
2182 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2183 {
2184 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2185
2186 /* Wait for basic configuration completes before proceeding */
2187 do {
2188 data = er32(STATUS);
2189 data &= E1000_STATUS_LAN_INIT_DONE;
2190 udelay(100);
2191 } while ((!data) && --loop);
2192
2193 /* If basic configuration is incomplete before the above loop
2194 * count reaches 0, loading the configuration from NVM will
2195 * leave the PHY in a bad state possibly resulting in no link.
2196 */
2197 if (loop == 0)
2198 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2199
2200 /* Clear the Init Done bit for the next init event */
2201 data = er32(STATUS);
2202 data &= ~E1000_STATUS_LAN_INIT_DONE;
2203 ew32(STATUS, data);
2204 }
2205
2206 /**
2207 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2208 * @hw: pointer to the HW structure
2209 **/
2210 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2211 {
2212 s32 ret_val = 0;
2213 u16 reg;
2214
2215 if (hw->phy.ops.check_reset_block(hw))
2216 return 0;
2217
2218 /* Allow time for h/w to get to quiescent state after reset */
2219 usleep_range(10000, 20000);
2220
2221 /* Perform any necessary post-reset workarounds */
2222 switch (hw->mac.type) {
2223 case e1000_pchlan:
2224 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2225 if (ret_val)
2226 return ret_val;
2227 break;
2228 case e1000_pch2lan:
2229 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2230 if (ret_val)
2231 return ret_val;
2232 break;
2233 default:
2234 break;
2235 }
2236
2237 /* Clear the host wakeup bit after lcd reset */
2238 if (hw->mac.type >= e1000_pchlan) {
2239 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2240 reg &= ~BM_WUC_HOST_WU_BIT;
2241 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2242 }
2243
2244 /* Configure the LCD with the extended configuration region in NVM */
2245 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2246 if (ret_val)
2247 return ret_val;
2248
2249 /* Configure the LCD with the OEM bits in NVM */
2250 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2251
2252 if (hw->mac.type == e1000_pch2lan) {
2253 /* Ungate automatic PHY configuration on non-managed 82579 */
2254 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2255 usleep_range(10000, 20000);
2256 e1000_gate_hw_phy_config_ich8lan(hw, false);
2257 }
2258
2259 /* Set EEE LPI Update Timer to 200usec */
2260 ret_val = hw->phy.ops.acquire(hw);
2261 if (ret_val)
2262 return ret_val;
2263 ret_val = e1000_write_emi_reg_locked(hw,
2264 I82579_LPI_UPDATE_TIMER,
2265 0x1387);
2266 hw->phy.ops.release(hw);
2267 }
2268
2269 return ret_val;
2270 }
2271
2272 /**
2273 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2274 * @hw: pointer to the HW structure
2275 *
2276 * Resets the PHY
2277 * This is a function pointer entry point called by drivers
2278 * or other shared routines.
2279 **/
2280 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2281 {
2282 s32 ret_val = 0;
2283
2284 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2285 if ((hw->mac.type == e1000_pch2lan) &&
2286 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2287 e1000_gate_hw_phy_config_ich8lan(hw, true);
2288
2289 ret_val = e1000e_phy_hw_reset_generic(hw);
2290 if (ret_val)
2291 return ret_val;
2292
2293 return e1000_post_phy_reset_ich8lan(hw);
2294 }
2295
2296 /**
2297 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2298 * @hw: pointer to the HW structure
2299 * @active: true to enable LPLU, false to disable
2300 *
2301 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2302 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2303 * the phy speed. This function will manually set the LPLU bit and restart
2304 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2305 * since it configures the same bit.
2306 **/
2307 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2308 {
2309 s32 ret_val = 0;
2310 u16 oem_reg;
2311
2312 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2313 if (ret_val)
2314 return ret_val;
2315
2316 if (active)
2317 oem_reg |= HV_OEM_BITS_LPLU;
2318 else
2319 oem_reg &= ~HV_OEM_BITS_LPLU;
2320
2321 if (!hw->phy.ops.check_reset_block(hw))
2322 oem_reg |= HV_OEM_BITS_RESTART_AN;
2323
2324 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2325 }
2326
2327 /**
2328 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2329 * @hw: pointer to the HW structure
2330 * @active: true to enable LPLU, false to disable
2331 *
2332 * Sets the LPLU D0 state according to the active flag. When
2333 * activating LPLU this function also disables smart speed
2334 * and vice versa. LPLU will not be activated unless the
2335 * device autonegotiation advertisement meets standards of
2336 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2337 * This is a function pointer entry point only called by
2338 * PHY setup routines.
2339 **/
2340 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2341 {
2342 struct e1000_phy_info *phy = &hw->phy;
2343 u32 phy_ctrl;
2344 s32 ret_val = 0;
2345 u16 data;
2346
2347 if (phy->type == e1000_phy_ife)
2348 return 0;
2349
2350 phy_ctrl = er32(PHY_CTRL);
2351
2352 if (active) {
2353 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2354 ew32(PHY_CTRL, phy_ctrl);
2355
2356 if (phy->type != e1000_phy_igp_3)
2357 return 0;
2358
2359 /* Call gig speed drop workaround on LPLU before accessing
2360 * any PHY registers
2361 */
2362 if (hw->mac.type == e1000_ich8lan)
2363 e1000e_gig_downshift_workaround_ich8lan(hw);
2364
2365 /* When LPLU is enabled, we should disable SmartSpeed */
2366 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2367 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2368 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2369 if (ret_val)
2370 return ret_val;
2371 } else {
2372 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2373 ew32(PHY_CTRL, phy_ctrl);
2374
2375 if (phy->type != e1000_phy_igp_3)
2376 return 0;
2377
2378 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2379 * during Dx states where the power conservation is most
2380 * important. During driver activity we should enable
2381 * SmartSpeed, so performance is maintained.
2382 */
2383 if (phy->smart_speed == e1000_smart_speed_on) {
2384 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2385 &data);
2386 if (ret_val)
2387 return ret_val;
2388
2389 data |= IGP01E1000_PSCFR_SMART_SPEED;
2390 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2391 data);
2392 if (ret_val)
2393 return ret_val;
2394 } else if (phy->smart_speed == e1000_smart_speed_off) {
2395 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2396 &data);
2397 if (ret_val)
2398 return ret_val;
2399
2400 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2401 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2402 data);
2403 if (ret_val)
2404 return ret_val;
2405 }
2406 }
2407
2408 return 0;
2409 }
2410
2411 /**
2412 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2413 * @hw: pointer to the HW structure
2414 * @active: true to enable LPLU, false to disable
2415 *
2416 * Sets the LPLU D3 state according to the active flag. When
2417 * activating LPLU this function also disables smart speed
2418 * and vice versa. LPLU will not be activated unless the
2419 * device autonegotiation advertisement meets standards of
2420 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2421 * This is a function pointer entry point only called by
2422 * PHY setup routines.
2423 **/
2424 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2425 {
2426 struct e1000_phy_info *phy = &hw->phy;
2427 u32 phy_ctrl;
2428 s32 ret_val = 0;
2429 u16 data;
2430
2431 phy_ctrl = er32(PHY_CTRL);
2432
2433 if (!active) {
2434 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2435 ew32(PHY_CTRL, phy_ctrl);
2436
2437 if (phy->type != e1000_phy_igp_3)
2438 return 0;
2439
2440 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2441 * during Dx states where the power conservation is most
2442 * important. During driver activity we should enable
2443 * SmartSpeed, so performance is maintained.
2444 */
2445 if (phy->smart_speed == e1000_smart_speed_on) {
2446 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2447 &data);
2448 if (ret_val)
2449 return ret_val;
2450
2451 data |= IGP01E1000_PSCFR_SMART_SPEED;
2452 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2453 data);
2454 if (ret_val)
2455 return ret_val;
2456 } else if (phy->smart_speed == e1000_smart_speed_off) {
2457 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2458 &data);
2459 if (ret_val)
2460 return ret_val;
2461
2462 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2463 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2464 data);
2465 if (ret_val)
2466 return ret_val;
2467 }
2468 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2469 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2470 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2471 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2472 ew32(PHY_CTRL, phy_ctrl);
2473
2474 if (phy->type != e1000_phy_igp_3)
2475 return 0;
2476
2477 /* Call gig speed drop workaround on LPLU before accessing
2478 * any PHY registers
2479 */
2480 if (hw->mac.type == e1000_ich8lan)
2481 e1000e_gig_downshift_workaround_ich8lan(hw);
2482
2483 /* When LPLU is enabled, we should disable SmartSpeed */
2484 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2485 if (ret_val)
2486 return ret_val;
2487
2488 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2489 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2490 }
2491
2492 return ret_val;
2493 }
2494
2495 /**
2496 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2497 * @hw: pointer to the HW structure
2498 * @bank: pointer to the variable that returns the active bank
2499 *
2500 * Reads signature byte from the NVM using the flash access registers.
2501 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2502 **/
2503 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2504 {
2505 u32 eecd;
2506 struct e1000_nvm_info *nvm = &hw->nvm;
2507 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2508 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2509 u8 sig_byte = 0;
2510 s32 ret_val;
2511
2512 switch (hw->mac.type) {
2513 case e1000_ich8lan:
2514 case e1000_ich9lan:
2515 eecd = er32(EECD);
2516 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2517 E1000_EECD_SEC1VAL_VALID_MASK) {
2518 if (eecd & E1000_EECD_SEC1VAL)
2519 *bank = 1;
2520 else
2521 *bank = 0;
2522
2523 return 0;
2524 }
2525 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2526 /* fall-thru */
2527 default:
2528 /* set bank to 0 in case flash read fails */
2529 *bank = 0;
2530
2531 /* Check bank 0 */
2532 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2533 &sig_byte);
2534 if (ret_val)
2535 return ret_val;
2536 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2537 E1000_ICH_NVM_SIG_VALUE) {
2538 *bank = 0;
2539 return 0;
2540 }
2541
2542 /* Check bank 1 */
2543 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2544 bank1_offset,
2545 &sig_byte);
2546 if (ret_val)
2547 return ret_val;
2548 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2549 E1000_ICH_NVM_SIG_VALUE) {
2550 *bank = 1;
2551 return 0;
2552 }
2553
2554 e_dbg("ERROR: No valid NVM bank present\n");
2555 return -E1000_ERR_NVM;
2556 }
2557 }
2558
2559 /**
2560 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2561 * @hw: pointer to the HW structure
2562 * @offset: The offset (in bytes) of the word(s) to read.
2563 * @words: Size of data to read in words
2564 * @data: Pointer to the word(s) to read at offset.
2565 *
2566 * Reads a word(s) from the NVM using the flash access registers.
2567 **/
2568 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2569 u16 *data)
2570 {
2571 struct e1000_nvm_info *nvm = &hw->nvm;
2572 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2573 u32 act_offset;
2574 s32 ret_val = 0;
2575 u32 bank = 0;
2576 u16 i, word;
2577
2578 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2579 (words == 0)) {
2580 e_dbg("nvm parameter(s) out of bounds\n");
2581 ret_val = -E1000_ERR_NVM;
2582 goto out;
2583 }
2584
2585 nvm->ops.acquire(hw);
2586
2587 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2588 if (ret_val) {
2589 e_dbg("Could not detect valid bank, assuming bank 0\n");
2590 bank = 0;
2591 }
2592
2593 act_offset = (bank) ? nvm->flash_bank_size : 0;
2594 act_offset += offset;
2595
2596 ret_val = 0;
2597 for (i = 0; i < words; i++) {
2598 if (dev_spec->shadow_ram[offset+i].modified) {
2599 data[i] = dev_spec->shadow_ram[offset+i].value;
2600 } else {
2601 ret_val = e1000_read_flash_word_ich8lan(hw,
2602 act_offset + i,
2603 &word);
2604 if (ret_val)
2605 break;
2606 data[i] = word;
2607 }
2608 }
2609
2610 nvm->ops.release(hw);
2611
2612 out:
2613 if (ret_val)
2614 e_dbg("NVM read error: %d\n", ret_val);
2615
2616 return ret_val;
2617 }
2618
2619 /**
2620 * e1000_flash_cycle_init_ich8lan - Initialize flash
2621 * @hw: pointer to the HW structure
2622 *
2623 * This function does initial flash setup so that a new read/write/erase cycle
2624 * can be started.
2625 **/
2626 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2627 {
2628 union ich8_hws_flash_status hsfsts;
2629 s32 ret_val = -E1000_ERR_NVM;
2630
2631 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2632
2633 /* Check if the flash descriptor is valid */
2634 if (!hsfsts.hsf_status.fldesvalid) {
2635 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
2636 return -E1000_ERR_NVM;
2637 }
2638
2639 /* Clear FCERR and DAEL in hw status by writing 1 */
2640 hsfsts.hsf_status.flcerr = 1;
2641 hsfsts.hsf_status.dael = 1;
2642
2643 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2644
2645 /* Either we should have a hardware SPI cycle in progress
2646 * bit to check against, in order to start a new cycle or
2647 * FDONE bit should be changed in the hardware so that it
2648 * is 1 after hardware reset, which can then be used as an
2649 * indication whether a cycle is in progress or has been
2650 * completed.
2651 */
2652
2653 if (!hsfsts.hsf_status.flcinprog) {
2654 /* There is no cycle running at present,
2655 * so we can start a cycle.
2656 * Begin by setting Flash Cycle Done.
2657 */
2658 hsfsts.hsf_status.flcdone = 1;
2659 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2660 ret_val = 0;
2661 } else {
2662 s32 i;
2663
2664 /* Otherwise poll for sometime so the current
2665 * cycle has a chance to end before giving up.
2666 */
2667 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2668 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2669 if (!hsfsts.hsf_status.flcinprog) {
2670 ret_val = 0;
2671 break;
2672 }
2673 udelay(1);
2674 }
2675 if (!ret_val) {
2676 /* Successful in waiting for previous cycle to timeout,
2677 * now set the Flash Cycle Done.
2678 */
2679 hsfsts.hsf_status.flcdone = 1;
2680 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2681 } else {
2682 e_dbg("Flash controller busy, cannot get access\n");
2683 }
2684 }
2685
2686 return ret_val;
2687 }
2688
2689 /**
2690 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2691 * @hw: pointer to the HW structure
2692 * @timeout: maximum time to wait for completion
2693 *
2694 * This function starts a flash cycle and waits for its completion.
2695 **/
2696 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2697 {
2698 union ich8_hws_flash_ctrl hsflctl;
2699 union ich8_hws_flash_status hsfsts;
2700 u32 i = 0;
2701
2702 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2703 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2704 hsflctl.hsf_ctrl.flcgo = 1;
2705 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2706
2707 /* wait till FDONE bit is set to 1 */
2708 do {
2709 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2710 if (hsfsts.hsf_status.flcdone)
2711 break;
2712 udelay(1);
2713 } while (i++ < timeout);
2714
2715 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
2716 return 0;
2717
2718 return -E1000_ERR_NVM;
2719 }
2720
2721 /**
2722 * e1000_read_flash_word_ich8lan - Read word from flash
2723 * @hw: pointer to the HW structure
2724 * @offset: offset to data location
2725 * @data: pointer to the location for storing the data
2726 *
2727 * Reads the flash word at offset into data. Offset is converted
2728 * to bytes before read.
2729 **/
2730 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2731 u16 *data)
2732 {
2733 /* Must convert offset into bytes. */
2734 offset <<= 1;
2735
2736 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2737 }
2738
2739 /**
2740 * e1000_read_flash_byte_ich8lan - Read byte from flash
2741 * @hw: pointer to the HW structure
2742 * @offset: The offset of the byte to read.
2743 * @data: Pointer to a byte to store the value read.
2744 *
2745 * Reads a single byte from the NVM using the flash access registers.
2746 **/
2747 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2748 u8 *data)
2749 {
2750 s32 ret_val;
2751 u16 word = 0;
2752
2753 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2754 if (ret_val)
2755 return ret_val;
2756
2757 *data = (u8)word;
2758
2759 return 0;
2760 }
2761
2762 /**
2763 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2764 * @hw: pointer to the HW structure
2765 * @offset: The offset (in bytes) of the byte or word to read.
2766 * @size: Size of data to read, 1=byte 2=word
2767 * @data: Pointer to the word to store the value read.
2768 *
2769 * Reads a byte or word from the NVM using the flash access registers.
2770 **/
2771 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2772 u8 size, u16 *data)
2773 {
2774 union ich8_hws_flash_status hsfsts;
2775 union ich8_hws_flash_ctrl hsflctl;
2776 u32 flash_linear_addr;
2777 u32 flash_data = 0;
2778 s32 ret_val = -E1000_ERR_NVM;
2779 u8 count = 0;
2780
2781 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2782 return -E1000_ERR_NVM;
2783
2784 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2785 hw->nvm.flash_base_addr;
2786
2787 do {
2788 udelay(1);
2789 /* Steps */
2790 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2791 if (ret_val)
2792 break;
2793
2794 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2795 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2796 hsflctl.hsf_ctrl.fldbcount = size - 1;
2797 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2798 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2799
2800 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2801
2802 ret_val = e1000_flash_cycle_ich8lan(hw,
2803 ICH_FLASH_READ_COMMAND_TIMEOUT);
2804
2805 /* Check if FCERR is set to 1, if set to 1, clear it
2806 * and try the whole sequence a few more times, else
2807 * read in (shift in) the Flash Data0, the order is
2808 * least significant byte first msb to lsb
2809 */
2810 if (!ret_val) {
2811 flash_data = er32flash(ICH_FLASH_FDATA0);
2812 if (size == 1)
2813 *data = (u8)(flash_data & 0x000000FF);
2814 else if (size == 2)
2815 *data = (u16)(flash_data & 0x0000FFFF);
2816 break;
2817 } else {
2818 /* If we've gotten here, then things are probably
2819 * completely hosed, but if the error condition is
2820 * detected, it won't hurt to give it another try...
2821 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2822 */
2823 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2824 if (hsfsts.hsf_status.flcerr) {
2825 /* Repeat for some time before giving up. */
2826 continue;
2827 } else if (!hsfsts.hsf_status.flcdone) {
2828 e_dbg("Timeout error - flash cycle did not complete.\n");
2829 break;
2830 }
2831 }
2832 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2833
2834 return ret_val;
2835 }
2836
2837 /**
2838 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2839 * @hw: pointer to the HW structure
2840 * @offset: The offset (in bytes) of the word(s) to write.
2841 * @words: Size of data to write in words
2842 * @data: Pointer to the word(s) to write at offset.
2843 *
2844 * Writes a byte or word to the NVM using the flash access registers.
2845 **/
2846 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2847 u16 *data)
2848 {
2849 struct e1000_nvm_info *nvm = &hw->nvm;
2850 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2851 u16 i;
2852
2853 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2854 (words == 0)) {
2855 e_dbg("nvm parameter(s) out of bounds\n");
2856 return -E1000_ERR_NVM;
2857 }
2858
2859 nvm->ops.acquire(hw);
2860
2861 for (i = 0; i < words; i++) {
2862 dev_spec->shadow_ram[offset+i].modified = true;
2863 dev_spec->shadow_ram[offset+i].value = data[i];
2864 }
2865
2866 nvm->ops.release(hw);
2867
2868 return 0;
2869 }
2870
2871 /**
2872 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2873 * @hw: pointer to the HW structure
2874 *
2875 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2876 * which writes the checksum to the shadow ram. The changes in the shadow
2877 * ram are then committed to the EEPROM by processing each bank at a time
2878 * checking for the modified bit and writing only the pending changes.
2879 * After a successful commit, the shadow ram is cleared and is ready for
2880 * future writes.
2881 **/
2882 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2883 {
2884 struct e1000_nvm_info *nvm = &hw->nvm;
2885 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2886 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2887 s32 ret_val;
2888 u16 data;
2889
2890 ret_val = e1000e_update_nvm_checksum_generic(hw);
2891 if (ret_val)
2892 goto out;
2893
2894 if (nvm->type != e1000_nvm_flash_sw)
2895 goto out;
2896
2897 nvm->ops.acquire(hw);
2898
2899 /* We're writing to the opposite bank so if we're on bank 1,
2900 * write to bank 0 etc. We also need to erase the segment that
2901 * is going to be written
2902 */
2903 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2904 if (ret_val) {
2905 e_dbg("Could not detect valid bank, assuming bank 0\n");
2906 bank = 0;
2907 }
2908
2909 if (bank == 0) {
2910 new_bank_offset = nvm->flash_bank_size;
2911 old_bank_offset = 0;
2912 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2913 if (ret_val)
2914 goto release;
2915 } else {
2916 old_bank_offset = nvm->flash_bank_size;
2917 new_bank_offset = 0;
2918 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2919 if (ret_val)
2920 goto release;
2921 }
2922
2923 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2924 /* Determine whether to write the value stored
2925 * in the other NVM bank or a modified value stored
2926 * in the shadow RAM
2927 */
2928 if (dev_spec->shadow_ram[i].modified) {
2929 data = dev_spec->shadow_ram[i].value;
2930 } else {
2931 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2932 old_bank_offset,
2933 &data);
2934 if (ret_val)
2935 break;
2936 }
2937
2938 /* If the word is 0x13, then make sure the signature bits
2939 * (15:14) are 11b until the commit has completed.
2940 * This will allow us to write 10b which indicates the
2941 * signature is valid. We want to do this after the write
2942 * has completed so that we don't mark the segment valid
2943 * while the write is still in progress
2944 */
2945 if (i == E1000_ICH_NVM_SIG_WORD)
2946 data |= E1000_ICH_NVM_SIG_MASK;
2947
2948 /* Convert offset to bytes. */
2949 act_offset = (i + new_bank_offset) << 1;
2950
2951 udelay(100);
2952 /* Write the bytes to the new bank. */
2953 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2954 act_offset,
2955 (u8)data);
2956 if (ret_val)
2957 break;
2958
2959 udelay(100);
2960 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2961 act_offset + 1,
2962 (u8)(data >> 8));
2963 if (ret_val)
2964 break;
2965 }
2966
2967 /* Don't bother writing the segment valid bits if sector
2968 * programming failed.
2969 */
2970 if (ret_val) {
2971 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2972 e_dbg("Flash commit failed.\n");
2973 goto release;
2974 }
2975
2976 /* Finally validate the new segment by setting bit 15:14
2977 * to 10b in word 0x13 , this can be done without an
2978 * erase as well since these bits are 11 to start with
2979 * and we need to change bit 14 to 0b
2980 */
2981 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2982 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2983 if (ret_val)
2984 goto release;
2985
2986 data &= 0xBFFF;
2987 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2988 act_offset * 2 + 1,
2989 (u8)(data >> 8));
2990 if (ret_val)
2991 goto release;
2992
2993 /* And invalidate the previously valid segment by setting
2994 * its signature word (0x13) high_byte to 0b. This can be
2995 * done without an erase because flash erase sets all bits
2996 * to 1's. We can write 1's to 0's without an erase
2997 */
2998 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2999 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
3000 if (ret_val)
3001 goto release;
3002
3003 /* Great! Everything worked, we can now clear the cached entries. */
3004 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3005 dev_spec->shadow_ram[i].modified = false;
3006 dev_spec->shadow_ram[i].value = 0xFFFF;
3007 }
3008
3009 release:
3010 nvm->ops.release(hw);
3011
3012 /* Reload the EEPROM, or else modifications will not appear
3013 * until after the next adapter reset.
3014 */
3015 if (!ret_val) {
3016 nvm->ops.reload(hw);
3017 usleep_range(10000, 20000);
3018 }
3019
3020 out:
3021 if (ret_val)
3022 e_dbg("NVM update error: %d\n", ret_val);
3023
3024 return ret_val;
3025 }
3026
3027 /**
3028 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3029 * @hw: pointer to the HW structure
3030 *
3031 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3032 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3033 * calculated, in which case we need to calculate the checksum and set bit 6.
3034 **/
3035 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
3036 {
3037 s32 ret_val;
3038 u16 data;
3039 u16 word;
3040 u16 valid_csum_mask;
3041
3042 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3043 * the checksum needs to be fixed. This bit is an indication that
3044 * the NVM was prepared by OEM software and did not calculate
3045 * the checksum...a likely scenario.
3046 */
3047 switch (hw->mac.type) {
3048 case e1000_pch_lpt:
3049 word = NVM_COMPAT;
3050 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
3051 break;
3052 default:
3053 word = NVM_FUTURE_INIT_WORD1;
3054 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
3055 break;
3056 }
3057
3058 ret_val = e1000_read_nvm(hw, word, 1, &data);
3059 if (ret_val)
3060 return ret_val;
3061
3062 if (!(data & valid_csum_mask)) {
3063 data |= valid_csum_mask;
3064 ret_val = e1000_write_nvm(hw, word, 1, &data);
3065 if (ret_val)
3066 return ret_val;
3067 ret_val = e1000e_update_nvm_checksum(hw);
3068 if (ret_val)
3069 return ret_val;
3070 }
3071
3072 return e1000e_validate_nvm_checksum_generic(hw);
3073 }
3074
3075 /**
3076 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3077 * @hw: pointer to the HW structure
3078 *
3079 * To prevent malicious write/erase of the NVM, set it to be read-only
3080 * so that the hardware ignores all write/erase cycles of the NVM via
3081 * the flash control registers. The shadow-ram copy of the NVM will
3082 * still be updated, however any updates to this copy will not stick
3083 * across driver reloads.
3084 **/
3085 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
3086 {
3087 struct e1000_nvm_info *nvm = &hw->nvm;
3088 union ich8_flash_protected_range pr0;
3089 union ich8_hws_flash_status hsfsts;
3090 u32 gfpreg;
3091
3092 nvm->ops.acquire(hw);
3093
3094 gfpreg = er32flash(ICH_FLASH_GFPREG);
3095
3096 /* Write-protect GbE Sector of NVM */
3097 pr0.regval = er32flash(ICH_FLASH_PR0);
3098 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
3099 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
3100 pr0.range.wpe = true;
3101 ew32flash(ICH_FLASH_PR0, pr0.regval);
3102
3103 /* Lock down a subset of GbE Flash Control Registers, e.g.
3104 * PR0 to prevent the write-protection from being lifted.
3105 * Once FLOCKDN is set, the registers protected by it cannot
3106 * be written until FLOCKDN is cleared by a hardware reset.
3107 */
3108 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3109 hsfsts.hsf_status.flockdn = true;
3110 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3111
3112 nvm->ops.release(hw);
3113 }
3114
3115 /**
3116 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3117 * @hw: pointer to the HW structure
3118 * @offset: The offset (in bytes) of the byte/word to read.
3119 * @size: Size of data to read, 1=byte 2=word
3120 * @data: The byte(s) to write to the NVM.
3121 *
3122 * Writes one/two bytes to the NVM using the flash access registers.
3123 **/
3124 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3125 u8 size, u16 data)
3126 {
3127 union ich8_hws_flash_status hsfsts;
3128 union ich8_hws_flash_ctrl hsflctl;
3129 u32 flash_linear_addr;
3130 u32 flash_data = 0;
3131 s32 ret_val;
3132 u8 count = 0;
3133
3134 if (size < 1 || size > 2 || data > size * 0xff ||
3135 offset > ICH_FLASH_LINEAR_ADDR_MASK)
3136 return -E1000_ERR_NVM;
3137
3138 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3139 hw->nvm.flash_base_addr;
3140
3141 do {
3142 udelay(1);
3143 /* Steps */
3144 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3145 if (ret_val)
3146 break;
3147
3148 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3149 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3150 hsflctl.hsf_ctrl.fldbcount = size -1;
3151 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
3152 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3153
3154 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3155
3156 if (size == 1)
3157 flash_data = (u32)data & 0x00FF;
3158 else
3159 flash_data = (u32)data;
3160
3161 ew32flash(ICH_FLASH_FDATA0, flash_data);
3162
3163 /* check if FCERR is set to 1 , if set to 1, clear it
3164 * and try the whole sequence a few more times else done
3165 */
3166 ret_val = e1000_flash_cycle_ich8lan(hw,
3167 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
3168 if (!ret_val)
3169 break;
3170
3171 /* If we're here, then things are most likely
3172 * completely hosed, but if the error condition
3173 * is detected, it won't hurt to give it another
3174 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3175 */
3176 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3177 if (hsfsts.hsf_status.flcerr)
3178 /* Repeat for some time before giving up. */
3179 continue;
3180 if (!hsfsts.hsf_status.flcdone) {
3181 e_dbg("Timeout error - flash cycle did not complete.\n");
3182 break;
3183 }
3184 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3185
3186 return ret_val;
3187 }
3188
3189 /**
3190 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3191 * @hw: pointer to the HW structure
3192 * @offset: The index of the byte to read.
3193 * @data: The byte to write to the NVM.
3194 *
3195 * Writes a single byte to the NVM using the flash access registers.
3196 **/
3197 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3198 u8 data)
3199 {
3200 u16 word = (u16)data;
3201
3202 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
3203 }
3204
3205 /**
3206 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3207 * @hw: pointer to the HW structure
3208 * @offset: The offset of the byte to write.
3209 * @byte: The byte to write to the NVM.
3210 *
3211 * Writes a single byte to the NVM using the flash access registers.
3212 * Goes through a retry algorithm before giving up.
3213 **/
3214 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
3215 u32 offset, u8 byte)
3216 {
3217 s32 ret_val;
3218 u16 program_retries;
3219
3220 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3221 if (!ret_val)
3222 return ret_val;
3223
3224 for (program_retries = 0; program_retries < 100; program_retries++) {
3225 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
3226 udelay(100);
3227 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
3228 if (!ret_val)
3229 break;
3230 }
3231 if (program_retries == 100)
3232 return -E1000_ERR_NVM;
3233
3234 return 0;
3235 }
3236
3237 /**
3238 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3239 * @hw: pointer to the HW structure
3240 * @bank: 0 for first bank, 1 for second bank, etc.
3241 *
3242 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3243 * bank N is 4096 * N + flash_reg_addr.
3244 **/
3245 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
3246 {
3247 struct e1000_nvm_info *nvm = &hw->nvm;
3248 union ich8_hws_flash_status hsfsts;
3249 union ich8_hws_flash_ctrl hsflctl;
3250 u32 flash_linear_addr;
3251 /* bank size is in 16bit words - adjust to bytes */
3252 u32 flash_bank_size = nvm->flash_bank_size * 2;
3253 s32 ret_val;
3254 s32 count = 0;
3255 s32 j, iteration, sector_size;
3256
3257 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3258
3259 /* Determine HW Sector size: Read BERASE bits of hw flash status
3260 * register
3261 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3262 * consecutive sectors. The start index for the nth Hw sector
3263 * can be calculated as = bank * 4096 + n * 256
3264 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3265 * The start index for the nth Hw sector can be calculated
3266 * as = bank * 4096
3267 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3268 * (ich9 only, otherwise error condition)
3269 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3270 */
3271 switch (hsfsts.hsf_status.berasesz) {
3272 case 0:
3273 /* Hw sector size 256 */
3274 sector_size = ICH_FLASH_SEG_SIZE_256;
3275 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
3276 break;
3277 case 1:
3278 sector_size = ICH_FLASH_SEG_SIZE_4K;
3279 iteration = 1;
3280 break;
3281 case 2:
3282 sector_size = ICH_FLASH_SEG_SIZE_8K;
3283 iteration = 1;
3284 break;
3285 case 3:
3286 sector_size = ICH_FLASH_SEG_SIZE_64K;
3287 iteration = 1;
3288 break;
3289 default:
3290 return -E1000_ERR_NVM;
3291 }
3292
3293 /* Start with the base address, then add the sector offset. */
3294 flash_linear_addr = hw->nvm.flash_base_addr;
3295 flash_linear_addr += (bank) ? flash_bank_size : 0;
3296
3297 for (j = 0; j < iteration ; j++) {
3298 do {
3299 /* Steps */
3300 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3301 if (ret_val)
3302 return ret_val;
3303
3304 /* Write a value 11 (block Erase) in Flash
3305 * Cycle field in hw flash control
3306 */
3307 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3308 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
3309 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3310
3311 /* Write the last 24 bits of an index within the
3312 * block into Flash Linear address field in Flash
3313 * Address.
3314 */
3315 flash_linear_addr += (j * sector_size);
3316 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3317
3318 ret_val = e1000_flash_cycle_ich8lan(hw,
3319 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
3320 if (!ret_val)
3321 break;
3322
3323 /* Check if FCERR is set to 1. If 1,
3324 * clear it and try the whole sequence
3325 * a few more times else Done
3326 */
3327 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3328 if (hsfsts.hsf_status.flcerr)
3329 /* repeat for some time before giving up */
3330 continue;
3331 else if (!hsfsts.hsf_status.flcdone)
3332 return ret_val;
3333 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
3334 }
3335
3336 return 0;
3337 }
3338
3339 /**
3340 * e1000_valid_led_default_ich8lan - Set the default LED settings
3341 * @hw: pointer to the HW structure
3342 * @data: Pointer to the LED settings
3343 *
3344 * Reads the LED default settings from the NVM to data. If the NVM LED
3345 * settings is all 0's or F's, set the LED default to a valid LED default
3346 * setting.
3347 **/
3348 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
3349 {
3350 s32 ret_val;
3351
3352 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
3353 if (ret_val) {
3354 e_dbg("NVM Read Error\n");
3355 return ret_val;
3356 }
3357
3358 if (*data == ID_LED_RESERVED_0000 ||
3359 *data == ID_LED_RESERVED_FFFF)
3360 *data = ID_LED_DEFAULT_ICH8LAN;
3361
3362 return 0;
3363 }
3364
3365 /**
3366 * e1000_id_led_init_pchlan - store LED configurations
3367 * @hw: pointer to the HW structure
3368 *
3369 * PCH does not control LEDs via the LEDCTL register, rather it uses
3370 * the PHY LED configuration register.
3371 *
3372 * PCH also does not have an "always on" or "always off" mode which
3373 * complicates the ID feature. Instead of using the "on" mode to indicate
3374 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3375 * use "link_up" mode. The LEDs will still ID on request if there is no
3376 * link based on logic in e1000_led_[on|off]_pchlan().
3377 **/
3378 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
3379 {
3380 struct e1000_mac_info *mac = &hw->mac;
3381 s32 ret_val;
3382 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3383 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3384 u16 data, i, temp, shift;
3385
3386 /* Get default ID LED modes */
3387 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3388 if (ret_val)
3389 return ret_val;
3390
3391 mac->ledctl_default = er32(LEDCTL);
3392 mac->ledctl_mode1 = mac->ledctl_default;
3393 mac->ledctl_mode2 = mac->ledctl_default;
3394
3395 for (i = 0; i < 4; i++) {
3396 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3397 shift = (i * 5);
3398 switch (temp) {
3399 case ID_LED_ON1_DEF2:
3400 case ID_LED_ON1_ON2:
3401 case ID_LED_ON1_OFF2:
3402 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3403 mac->ledctl_mode1 |= (ledctl_on << shift);
3404 break;
3405 case ID_LED_OFF1_DEF2:
3406 case ID_LED_OFF1_ON2:
3407 case ID_LED_OFF1_OFF2:
3408 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3409 mac->ledctl_mode1 |= (ledctl_off << shift);
3410 break;
3411 default:
3412 /* Do nothing */
3413 break;
3414 }
3415 switch (temp) {
3416 case ID_LED_DEF1_ON2:
3417 case ID_LED_ON1_ON2:
3418 case ID_LED_OFF1_ON2:
3419 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3420 mac->ledctl_mode2 |= (ledctl_on << shift);
3421 break;
3422 case ID_LED_DEF1_OFF2:
3423 case ID_LED_ON1_OFF2:
3424 case ID_LED_OFF1_OFF2:
3425 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3426 mac->ledctl_mode2 |= (ledctl_off << shift);
3427 break;
3428 default:
3429 /* Do nothing */
3430 break;
3431 }
3432 }
3433
3434 return 0;
3435 }
3436
3437 /**
3438 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3439 * @hw: pointer to the HW structure
3440 *
3441 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3442 * register, so the the bus width is hard coded.
3443 **/
3444 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3445 {
3446 struct e1000_bus_info *bus = &hw->bus;
3447 s32 ret_val;
3448
3449 ret_val = e1000e_get_bus_info_pcie(hw);
3450
3451 /* ICH devices are "PCI Express"-ish. They have
3452 * a configuration space, but do not contain
3453 * PCI Express Capability registers, so bus width
3454 * must be hardcoded.
3455 */
3456 if (bus->width == e1000_bus_width_unknown)
3457 bus->width = e1000_bus_width_pcie_x1;
3458
3459 return ret_val;
3460 }
3461
3462 /**
3463 * e1000_reset_hw_ich8lan - Reset the hardware
3464 * @hw: pointer to the HW structure
3465 *
3466 * Does a full reset of the hardware which includes a reset of the PHY and
3467 * MAC.
3468 **/
3469 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3470 {
3471 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3472 u16 kum_cfg;
3473 u32 ctrl, reg;
3474 s32 ret_val;
3475
3476 /* Prevent the PCI-E bus from sticking if there is no TLP connection
3477 * on the last TLP read/write transaction when MAC is reset.
3478 */
3479 ret_val = e1000e_disable_pcie_master(hw);
3480 if (ret_val)
3481 e_dbg("PCI-E Master disable polling has failed.\n");
3482
3483 e_dbg("Masking off all interrupts\n");
3484 ew32(IMC, 0xffffffff);
3485
3486 /* Disable the Transmit and Receive units. Then delay to allow
3487 * any pending transactions to complete before we hit the MAC
3488 * with the global reset.
3489 */
3490 ew32(RCTL, 0);
3491 ew32(TCTL, E1000_TCTL_PSP);
3492 e1e_flush();
3493
3494 usleep_range(10000, 20000);
3495
3496 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3497 if (hw->mac.type == e1000_ich8lan) {
3498 /* Set Tx and Rx buffer allocation to 8k apiece. */
3499 ew32(PBA, E1000_PBA_8K);
3500 /* Set Packet Buffer Size to 16k. */
3501 ew32(PBS, E1000_PBS_16K);
3502 }
3503
3504 if (hw->mac.type == e1000_pchlan) {
3505 /* Save the NVM K1 bit setting */
3506 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
3507 if (ret_val)
3508 return ret_val;
3509
3510 if (kum_cfg & E1000_NVM_K1_ENABLE)
3511 dev_spec->nvm_k1_enabled = true;
3512 else
3513 dev_spec->nvm_k1_enabled = false;
3514 }
3515
3516 ctrl = er32(CTRL);
3517
3518 if (!hw->phy.ops.check_reset_block(hw)) {
3519 /* Full-chip reset requires MAC and PHY reset at the same
3520 * time to make sure the interface between MAC and the
3521 * external PHY is reset.
3522 */
3523 ctrl |= E1000_CTRL_PHY_RST;
3524
3525 /* Gate automatic PHY configuration by hardware on
3526 * non-managed 82579
3527 */
3528 if ((hw->mac.type == e1000_pch2lan) &&
3529 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3530 e1000_gate_hw_phy_config_ich8lan(hw, true);
3531 }
3532 ret_val = e1000_acquire_swflag_ich8lan(hw);
3533 e_dbg("Issuing a global reset to ich8lan\n");
3534 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3535 /* cannot issue a flush here because it hangs the hardware */
3536 msleep(20);
3537
3538 /* Set Phy Config Counter to 50msec */
3539 if (hw->mac.type == e1000_pch2lan) {
3540 reg = er32(FEXTNVM3);
3541 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
3542 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
3543 ew32(FEXTNVM3, reg);
3544 }
3545
3546 if (!ret_val)
3547 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3548
3549 if (ctrl & E1000_CTRL_PHY_RST) {
3550 ret_val = hw->phy.ops.get_cfg_done(hw);
3551 if (ret_val)
3552 return ret_val;
3553
3554 ret_val = e1000_post_phy_reset_ich8lan(hw);
3555 if (ret_val)
3556 return ret_val;
3557 }
3558
3559 /* For PCH, this write will make sure that any noise
3560 * will be detected as a CRC error and be dropped rather than show up
3561 * as a bad packet to the DMA engine.
3562 */
3563 if (hw->mac.type == e1000_pchlan)
3564 ew32(CRC_OFFSET, 0x65656565);
3565
3566 ew32(IMC, 0xffffffff);
3567 er32(ICR);
3568
3569 reg = er32(KABGTXD);
3570 reg |= E1000_KABGTXD_BGSQLBIAS;
3571 ew32(KABGTXD, reg);
3572
3573 return 0;
3574 }
3575
3576 /**
3577 * e1000_init_hw_ich8lan - Initialize the hardware
3578 * @hw: pointer to the HW structure
3579 *
3580 * Prepares the hardware for transmit and receive by doing the following:
3581 * - initialize hardware bits
3582 * - initialize LED identification
3583 * - setup receive address registers
3584 * - setup flow control
3585 * - setup transmit descriptors
3586 * - clear statistics
3587 **/
3588 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3589 {
3590 struct e1000_mac_info *mac = &hw->mac;
3591 u32 ctrl_ext, txdctl, snoop;
3592 s32 ret_val;
3593 u16 i;
3594
3595 e1000_initialize_hw_bits_ich8lan(hw);
3596
3597 /* Initialize identification LED */
3598 ret_val = mac->ops.id_led_init(hw);
3599 if (ret_val)
3600 e_dbg("Error initializing identification LED\n");
3601 /* This is not fatal and we should not stop init due to this */
3602
3603 /* Setup the receive address. */
3604 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3605
3606 /* Zero out the Multicast HASH table */
3607 e_dbg("Zeroing the MTA\n");
3608 for (i = 0; i < mac->mta_reg_count; i++)
3609 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3610
3611 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3612 * the ME. Disable wakeup by clearing the host wakeup bit.
3613 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3614 */
3615 if (hw->phy.type == e1000_phy_82578) {
3616 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3617 i &= ~BM_WUC_HOST_WU_BIT;
3618 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3619 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3620 if (ret_val)
3621 return ret_val;
3622 }
3623
3624 /* Setup link and flow control */
3625 ret_val = mac->ops.setup_link(hw);
3626
3627 /* Set the transmit descriptor write-back policy for both queues */
3628 txdctl = er32(TXDCTL(0));
3629 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3630 E1000_TXDCTL_FULL_TX_DESC_WB;
3631 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3632 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3633 ew32(TXDCTL(0), txdctl);
3634 txdctl = er32(TXDCTL(1));
3635 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3636 E1000_TXDCTL_FULL_TX_DESC_WB;
3637 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3638 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3639 ew32(TXDCTL(1), txdctl);
3640
3641 /* ICH8 has opposite polarity of no_snoop bits.
3642 * By default, we should use snoop behavior.
3643 */
3644 if (mac->type == e1000_ich8lan)
3645 snoop = PCIE_ICH8_SNOOP_ALL;
3646 else
3647 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3648 e1000e_set_pcie_no_snoop(hw, snoop);
3649
3650 ctrl_ext = er32(CTRL_EXT);
3651 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3652 ew32(CTRL_EXT, ctrl_ext);
3653
3654 /* Clear all of the statistics registers (clear on read). It is
3655 * important that we do this after we have tried to establish link
3656 * because the symbol error count will increment wildly if there
3657 * is no link.
3658 */
3659 e1000_clear_hw_cntrs_ich8lan(hw);
3660
3661 return ret_val;
3662 }
3663 /**
3664 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3665 * @hw: pointer to the HW structure
3666 *
3667 * Sets/Clears required hardware bits necessary for correctly setting up the
3668 * hardware for transmit and receive.
3669 **/
3670 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3671 {
3672 u32 reg;
3673
3674 /* Extended Device Control */
3675 reg = er32(CTRL_EXT);
3676 reg |= (1 << 22);
3677 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3678 if (hw->mac.type >= e1000_pchlan)
3679 reg |= E1000_CTRL_EXT_PHYPDEN;
3680 ew32(CTRL_EXT, reg);
3681
3682 /* Transmit Descriptor Control 0 */
3683 reg = er32(TXDCTL(0));
3684 reg |= (1 << 22);
3685 ew32(TXDCTL(0), reg);
3686
3687 /* Transmit Descriptor Control 1 */
3688 reg = er32(TXDCTL(1));
3689 reg |= (1 << 22);
3690 ew32(TXDCTL(1), reg);
3691
3692 /* Transmit Arbitration Control 0 */
3693 reg = er32(TARC(0));
3694 if (hw->mac.type == e1000_ich8lan)
3695 reg |= (1 << 28) | (1 << 29);
3696 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3697 ew32(TARC(0), reg);
3698
3699 /* Transmit Arbitration Control 1 */
3700 reg = er32(TARC(1));
3701 if (er32(TCTL) & E1000_TCTL_MULR)
3702 reg &= ~(1 << 28);
3703 else
3704 reg |= (1 << 28);
3705 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3706 ew32(TARC(1), reg);
3707
3708 /* Device Status */
3709 if (hw->mac.type == e1000_ich8lan) {
3710 reg = er32(STATUS);
3711 reg &= ~(1 << 31);
3712 ew32(STATUS, reg);
3713 }
3714
3715 /* work-around descriptor data corruption issue during nfs v2 udp
3716 * traffic, just disable the nfs filtering capability
3717 */
3718 reg = er32(RFCTL);
3719 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3720
3721 /* Disable IPv6 extension header parsing because some malformed
3722 * IPv6 headers can hang the Rx.
3723 */
3724 if (hw->mac.type == e1000_ich8lan)
3725 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
3726 ew32(RFCTL, reg);
3727 }
3728
3729 /**
3730 * e1000_setup_link_ich8lan - Setup flow control and link settings
3731 * @hw: pointer to the HW structure
3732 *
3733 * Determines which flow control settings to use, then configures flow
3734 * control. Calls the appropriate media-specific link configuration
3735 * function. Assuming the adapter has a valid link partner, a valid link
3736 * should be established. Assumes the hardware has previously been reset
3737 * and the transmitter and receiver are not enabled.
3738 **/
3739 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3740 {
3741 s32 ret_val;
3742
3743 if (hw->phy.ops.check_reset_block(hw))
3744 return 0;
3745
3746 /* ICH parts do not have a word in the NVM to determine
3747 * the default flow control setting, so we explicitly
3748 * set it to full.
3749 */
3750 if (hw->fc.requested_mode == e1000_fc_default) {
3751 /* Workaround h/w hang when Tx flow control enabled */
3752 if (hw->mac.type == e1000_pchlan)
3753 hw->fc.requested_mode = e1000_fc_rx_pause;
3754 else
3755 hw->fc.requested_mode = e1000_fc_full;
3756 }
3757
3758 /* Save off the requested flow control mode for use later. Depending
3759 * on the link partner's capabilities, we may or may not use this mode.
3760 */
3761 hw->fc.current_mode = hw->fc.requested_mode;
3762
3763 e_dbg("After fix-ups FlowControl is now = %x\n",
3764 hw->fc.current_mode);
3765
3766 /* Continue to configure the copper link. */
3767 ret_val = hw->mac.ops.setup_physical_interface(hw);
3768 if (ret_val)
3769 return ret_val;
3770
3771 ew32(FCTTV, hw->fc.pause_time);
3772 if ((hw->phy.type == e1000_phy_82578) ||
3773 (hw->phy.type == e1000_phy_82579) ||
3774 (hw->phy.type == e1000_phy_i217) ||
3775 (hw->phy.type == e1000_phy_82577)) {
3776 ew32(FCRTV_PCH, hw->fc.refresh_time);
3777
3778 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3779 hw->fc.pause_time);
3780 if (ret_val)
3781 return ret_val;
3782 }
3783
3784 return e1000e_set_fc_watermarks(hw);
3785 }
3786
3787 /**
3788 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3789 * @hw: pointer to the HW structure
3790 *
3791 * Configures the kumeran interface to the PHY to wait the appropriate time
3792 * when polling the PHY, then call the generic setup_copper_link to finish
3793 * configuring the copper link.
3794 **/
3795 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3796 {
3797 u32 ctrl;
3798 s32 ret_val;
3799 u16 reg_data;
3800
3801 ctrl = er32(CTRL);
3802 ctrl |= E1000_CTRL_SLU;
3803 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3804 ew32(CTRL, ctrl);
3805
3806 /* Set the mac to wait the maximum time between each iteration
3807 * and increase the max iterations when polling the phy;
3808 * this fixes erroneous timeouts at 10Mbps.
3809 */
3810 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3811 if (ret_val)
3812 return ret_val;
3813 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3814 &reg_data);
3815 if (ret_val)
3816 return ret_val;
3817 reg_data |= 0x3F;
3818 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3819 reg_data);
3820 if (ret_val)
3821 return ret_val;
3822
3823 switch (hw->phy.type) {
3824 case e1000_phy_igp_3:
3825 ret_val = e1000e_copper_link_setup_igp(hw);
3826 if (ret_val)
3827 return ret_val;
3828 break;
3829 case e1000_phy_bm:
3830 case e1000_phy_82578:
3831 ret_val = e1000e_copper_link_setup_m88(hw);
3832 if (ret_val)
3833 return ret_val;
3834 break;
3835 case e1000_phy_82577:
3836 case e1000_phy_82579:
3837 case e1000_phy_i217:
3838 ret_val = e1000_copper_link_setup_82577(hw);
3839 if (ret_val)
3840 return ret_val;
3841 break;
3842 case e1000_phy_ife:
3843 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3844 if (ret_val)
3845 return ret_val;
3846
3847 reg_data &= ~IFE_PMC_AUTO_MDIX;
3848
3849 switch (hw->phy.mdix) {
3850 case 1:
3851 reg_data &= ~IFE_PMC_FORCE_MDIX;
3852 break;
3853 case 2:
3854 reg_data |= IFE_PMC_FORCE_MDIX;
3855 break;
3856 case 0:
3857 default:
3858 reg_data |= IFE_PMC_AUTO_MDIX;
3859 break;
3860 }
3861 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3862 if (ret_val)
3863 return ret_val;
3864 break;
3865 default:
3866 break;
3867 }
3868
3869 return e1000e_setup_copper_link(hw);
3870 }
3871
3872 /**
3873 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3874 * @hw: pointer to the HW structure
3875 * @speed: pointer to store current link speed
3876 * @duplex: pointer to store the current link duplex
3877 *
3878 * Calls the generic get_speed_and_duplex to retrieve the current link
3879 * information and then calls the Kumeran lock loss workaround for links at
3880 * gigabit speeds.
3881 **/
3882 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3883 u16 *duplex)
3884 {
3885 s32 ret_val;
3886
3887 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3888 if (ret_val)
3889 return ret_val;
3890
3891 if ((hw->mac.type == e1000_ich8lan) &&
3892 (hw->phy.type == e1000_phy_igp_3) &&
3893 (*speed == SPEED_1000)) {
3894 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3895 }
3896
3897 return ret_val;
3898 }
3899
3900 /**
3901 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3902 * @hw: pointer to the HW structure
3903 *
3904 * Work-around for 82566 Kumeran PCS lock loss:
3905 * On link status change (i.e. PCI reset, speed change) and link is up and
3906 * speed is gigabit-
3907 * 0) if workaround is optionally disabled do nothing
3908 * 1) wait 1ms for Kumeran link to come up
3909 * 2) check Kumeran Diagnostic register PCS lock loss bit
3910 * 3) if not set the link is locked (all is good), otherwise...
3911 * 4) reset the PHY
3912 * 5) repeat up to 10 times
3913 * Note: this is only called for IGP3 copper when speed is 1gb.
3914 **/
3915 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3916 {
3917 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3918 u32 phy_ctrl;
3919 s32 ret_val;
3920 u16 i, data;
3921 bool link;
3922
3923 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3924 return 0;
3925
3926 /* Make sure link is up before proceeding. If not just return.
3927 * Attempting this while link is negotiating fouled up link
3928 * stability
3929 */
3930 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3931 if (!link)
3932 return 0;
3933
3934 for (i = 0; i < 10; i++) {
3935 /* read once to clear */
3936 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3937 if (ret_val)
3938 return ret_val;
3939 /* and again to get new status */
3940 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3941 if (ret_val)
3942 return ret_val;
3943
3944 /* check for PCS lock */
3945 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3946 return 0;
3947
3948 /* Issue PHY reset */
3949 e1000_phy_hw_reset(hw);
3950 mdelay(5);
3951 }
3952 /* Disable GigE link negotiation */
3953 phy_ctrl = er32(PHY_CTRL);
3954 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3955 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3956 ew32(PHY_CTRL, phy_ctrl);
3957
3958 /* Call gig speed drop workaround on Gig disable before accessing
3959 * any PHY registers
3960 */
3961 e1000e_gig_downshift_workaround_ich8lan(hw);
3962
3963 /* unable to acquire PCS lock */
3964 return -E1000_ERR_PHY;
3965 }
3966
3967 /**
3968 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3969 * @hw: pointer to the HW structure
3970 * @state: boolean value used to set the current Kumeran workaround state
3971 *
3972 * If ICH8, set the current Kumeran workaround state (enabled - true
3973 * /disabled - false).
3974 **/
3975 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3976 bool state)
3977 {
3978 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3979
3980 if (hw->mac.type != e1000_ich8lan) {
3981 e_dbg("Workaround applies to ICH8 only.\n");
3982 return;
3983 }
3984
3985 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3986 }
3987
3988 /**
3989 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3990 * @hw: pointer to the HW structure
3991 *
3992 * Workaround for 82566 power-down on D3 entry:
3993 * 1) disable gigabit link
3994 * 2) write VR power-down enable
3995 * 3) read it back
3996 * Continue if successful, else issue LCD reset and repeat
3997 **/
3998 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3999 {
4000 u32 reg;
4001 u16 data;
4002 u8 retry = 0;
4003
4004 if (hw->phy.type != e1000_phy_igp_3)
4005 return;
4006
4007 /* Try the workaround twice (if needed) */
4008 do {
4009 /* Disable link */
4010 reg = er32(PHY_CTRL);
4011 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
4012 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4013 ew32(PHY_CTRL, reg);
4014
4015 /* Call gig speed drop workaround on Gig disable before
4016 * accessing any PHY registers
4017 */
4018 if (hw->mac.type == e1000_ich8lan)
4019 e1000e_gig_downshift_workaround_ich8lan(hw);
4020
4021 /* Write VR power-down enable */
4022 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4023 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4024 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
4025
4026 /* Read it back and test */
4027 e1e_rphy(hw, IGP3_VR_CTRL, &data);
4028 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
4029 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
4030 break;
4031
4032 /* Issue PHY reset and repeat at most one more time */
4033 reg = er32(CTRL);
4034 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
4035 retry++;
4036 } while (retry);
4037 }
4038
4039 /**
4040 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4041 * @hw: pointer to the HW structure
4042 *
4043 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4044 * LPLU, Gig disable, MDIC PHY reset):
4045 * 1) Set Kumeran Near-end loopback
4046 * 2) Clear Kumeran Near-end loopback
4047 * Should only be called for ICH8[m] devices with any 1G Phy.
4048 **/
4049 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
4050 {
4051 s32 ret_val;
4052 u16 reg_data;
4053
4054 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
4055 return;
4056
4057 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4058 &reg_data);
4059 if (ret_val)
4060 return;
4061 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
4062 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4063 reg_data);
4064 if (ret_val)
4065 return;
4066 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
4067 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
4068 reg_data);
4069 }
4070
4071 /**
4072 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4073 * @hw: pointer to the HW structure
4074 *
4075 * During S0 to Sx transition, it is possible the link remains at gig
4076 * instead of negotiating to a lower speed. Before going to Sx, set
4077 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4078 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4079 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4080 * needs to be written.
4081 * Parts that support (and are linked to a partner which support) EEE in
4082 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4083 * than 10Mbps w/o EEE.
4084 **/
4085 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
4086 {
4087 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4088 u32 phy_ctrl;
4089 s32 ret_val;
4090
4091 phy_ctrl = er32(PHY_CTRL);
4092 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
4093 if (hw->phy.type == e1000_phy_i217) {
4094 u16 phy_reg;
4095
4096 ret_val = hw->phy.ops.acquire(hw);
4097 if (ret_val)
4098 goto out;
4099
4100 if (!dev_spec->eee_disable) {
4101 u16 eee_advert;
4102
4103 ret_val =
4104 e1000_read_emi_reg_locked(hw,
4105 I217_EEE_ADVERTISEMENT,
4106 &eee_advert);
4107 if (ret_val)
4108 goto release;
4109
4110 /* Disable LPLU if both link partners support 100BaseT
4111 * EEE and 100Full is advertised on both ends of the
4112 * link.
4113 */
4114 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
4115 (dev_spec->eee_lp_ability &
4116 I82579_EEE_100_SUPPORTED) &&
4117 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL))
4118 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
4119 E1000_PHY_CTRL_NOND0A_LPLU);
4120 }
4121
4122 /* For i217 Intel Rapid Start Technology support,
4123 * when the system is going into Sx and no manageability engine
4124 * is present, the driver must configure proxy to reset only on
4125 * power good. LPI (Low Power Idle) state must also reset only
4126 * on power good, as well as the MTA (Multicast table array).
4127 * The SMBus release must also be disabled on LCD reset.
4128 */
4129 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4130
4131 /* Enable proxy to reset only on power good. */
4132 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
4133 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
4134 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
4135
4136 /* Set bit enable LPI (EEE) to reset only on
4137 * power good.
4138 */
4139 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
4140 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
4141 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
4142
4143 /* Disable the SMB release on LCD reset. */
4144 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4145 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
4146 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4147 }
4148
4149 /* Enable MTA to reset for Intel Rapid Start Technology
4150 * Support
4151 */
4152 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4153 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
4154 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4155
4156 release:
4157 hw->phy.ops.release(hw);
4158 }
4159 out:
4160 ew32(PHY_CTRL, phy_ctrl);
4161
4162 if (hw->mac.type == e1000_ich8lan)
4163 e1000e_gig_downshift_workaround_ich8lan(hw);
4164
4165 if (hw->mac.type >= e1000_pchlan) {
4166 e1000_oem_bits_config_ich8lan(hw, false);
4167
4168 /* Reset PHY to activate OEM bits on 82577/8 */
4169 if (hw->mac.type == e1000_pchlan)
4170 e1000e_phy_hw_reset_generic(hw);
4171
4172 ret_val = hw->phy.ops.acquire(hw);
4173 if (ret_val)
4174 return;
4175 e1000_write_smbus_addr(hw);
4176 hw->phy.ops.release(hw);
4177 }
4178 }
4179
4180 /**
4181 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4182 * @hw: pointer to the HW structure
4183 *
4184 * During Sx to S0 transitions on non-managed devices or managed devices
4185 * on which PHY resets are not blocked, if the PHY registers cannot be
4186 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4187 * the PHY.
4188 * On i217, setup Intel Rapid Start Technology.
4189 **/
4190 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
4191 {
4192 s32 ret_val;
4193
4194 if (hw->mac.type < e1000_pch2lan)
4195 return;
4196
4197 ret_val = e1000_init_phy_workarounds_pchlan(hw);
4198 if (ret_val) {
4199 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
4200 return;
4201 }
4202
4203 /* For i217 Intel Rapid Start Technology support when the system
4204 * is transitioning from Sx and no manageability engine is present
4205 * configure SMBus to restore on reset, disable proxy, and enable
4206 * the reset on MTA (Multicast table array).
4207 */
4208 if (hw->phy.type == e1000_phy_i217) {
4209 u16 phy_reg;
4210
4211 ret_val = hw->phy.ops.acquire(hw);
4212 if (ret_val) {
4213 e_dbg("Failed to setup iRST\n");
4214 return;
4215 }
4216
4217 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
4218 /* Restore clear on SMB if no manageability engine
4219 * is present
4220 */
4221 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
4222 if (ret_val)
4223 goto release;
4224 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
4225 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
4226
4227 /* Disable Proxy */
4228 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
4229 }
4230 /* Enable reset on MTA */
4231 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
4232 if (ret_val)
4233 goto release;
4234 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
4235 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
4236 release:
4237 if (ret_val)
4238 e_dbg("Error %d in resume workarounds\n", ret_val);
4239 hw->phy.ops.release(hw);
4240 }
4241 }
4242
4243 /**
4244 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4245 * @hw: pointer to the HW structure
4246 *
4247 * Return the LED back to the default configuration.
4248 **/
4249 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
4250 {
4251 if (hw->phy.type == e1000_phy_ife)
4252 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
4253
4254 ew32(LEDCTL, hw->mac.ledctl_default);
4255 return 0;
4256 }
4257
4258 /**
4259 * e1000_led_on_ich8lan - Turn LEDs on
4260 * @hw: pointer to the HW structure
4261 *
4262 * Turn on the LEDs.
4263 **/
4264 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
4265 {
4266 if (hw->phy.type == e1000_phy_ife)
4267 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4268 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
4269
4270 ew32(LEDCTL, hw->mac.ledctl_mode2);
4271 return 0;
4272 }
4273
4274 /**
4275 * e1000_led_off_ich8lan - Turn LEDs off
4276 * @hw: pointer to the HW structure
4277 *
4278 * Turn off the LEDs.
4279 **/
4280 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
4281 {
4282 if (hw->phy.type == e1000_phy_ife)
4283 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
4284 (IFE_PSCL_PROBE_MODE |
4285 IFE_PSCL_PROBE_LEDS_OFF));
4286
4287 ew32(LEDCTL, hw->mac.ledctl_mode1);
4288 return 0;
4289 }
4290
4291 /**
4292 * e1000_setup_led_pchlan - Configures SW controllable LED
4293 * @hw: pointer to the HW structure
4294 *
4295 * This prepares the SW controllable LED for use.
4296 **/
4297 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
4298 {
4299 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
4300 }
4301
4302 /**
4303 * e1000_cleanup_led_pchlan - Restore the default LED operation
4304 * @hw: pointer to the HW structure
4305 *
4306 * Return the LED back to the default configuration.
4307 **/
4308 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
4309 {
4310 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
4311 }
4312
4313 /**
4314 * e1000_led_on_pchlan - Turn LEDs on
4315 * @hw: pointer to the HW structure
4316 *
4317 * Turn on the LEDs.
4318 **/
4319 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
4320 {
4321 u16 data = (u16)hw->mac.ledctl_mode2;
4322 u32 i, led;
4323
4324 /* If no link, then turn LED on by setting the invert bit
4325 * for each LED that's mode is "link_up" in ledctl_mode2.
4326 */
4327 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4328 for (i = 0; i < 3; i++) {
4329 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4330 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4331 E1000_LEDCTL_MODE_LINK_UP)
4332 continue;
4333 if (led & E1000_PHY_LED0_IVRT)
4334 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4335 else
4336 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4337 }
4338 }
4339
4340 return e1e_wphy(hw, HV_LED_CONFIG, data);
4341 }
4342
4343 /**
4344 * e1000_led_off_pchlan - Turn LEDs off
4345 * @hw: pointer to the HW structure
4346 *
4347 * Turn off the LEDs.
4348 **/
4349 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
4350 {
4351 u16 data = (u16)hw->mac.ledctl_mode1;
4352 u32 i, led;
4353
4354 /* If no link, then turn LED off by clearing the invert bit
4355 * for each LED that's mode is "link_up" in ledctl_mode1.
4356 */
4357 if (!(er32(STATUS) & E1000_STATUS_LU)) {
4358 for (i = 0; i < 3; i++) {
4359 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
4360 if ((led & E1000_PHY_LED0_MODE_MASK) !=
4361 E1000_LEDCTL_MODE_LINK_UP)
4362 continue;
4363 if (led & E1000_PHY_LED0_IVRT)
4364 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
4365 else
4366 data |= (E1000_PHY_LED0_IVRT << (i * 5));
4367 }
4368 }
4369
4370 return e1e_wphy(hw, HV_LED_CONFIG, data);
4371 }
4372
4373 /**
4374 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4375 * @hw: pointer to the HW structure
4376 *
4377 * Read appropriate register for the config done bit for completion status
4378 * and configure the PHY through s/w for EEPROM-less parts.
4379 *
4380 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4381 * config done bit, so only an error is logged and continues. If we were
4382 * to return with error, EEPROM-less silicon would not be able to be reset
4383 * or change link.
4384 **/
4385 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
4386 {
4387 s32 ret_val = 0;
4388 u32 bank = 0;
4389 u32 status;
4390
4391 e1000e_get_cfg_done(hw);
4392
4393 /* Wait for indication from h/w that it has completed basic config */
4394 if (hw->mac.type >= e1000_ich10lan) {
4395 e1000_lan_init_done_ich8lan(hw);
4396 } else {
4397 ret_val = e1000e_get_auto_rd_done(hw);
4398 if (ret_val) {
4399 /* When auto config read does not complete, do not
4400 * return with an error. This can happen in situations
4401 * where there is no eeprom and prevents getting link.
4402 */
4403 e_dbg("Auto Read Done did not complete\n");
4404 ret_val = 0;
4405 }
4406 }
4407
4408 /* Clear PHY Reset Asserted bit */
4409 status = er32(STATUS);
4410 if (status & E1000_STATUS_PHYRA)
4411 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
4412 else
4413 e_dbg("PHY Reset Asserted not set - needs delay\n");
4414
4415 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4416 if (hw->mac.type <= e1000_ich9lan) {
4417 if (!(er32(EECD) & E1000_EECD_PRES) &&
4418 (hw->phy.type == e1000_phy_igp_3)) {
4419 e1000e_phy_init_script_igp3(hw);
4420 }
4421 } else {
4422 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
4423 /* Maybe we should do a basic PHY config */
4424 e_dbg("EEPROM not present\n");
4425 ret_val = -E1000_ERR_CONFIG;
4426 }
4427 }
4428
4429 return ret_val;
4430 }
4431
4432 /**
4433 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4434 * @hw: pointer to the HW structure
4435 *
4436 * In the case of a PHY power down to save power, or to turn off link during a
4437 * driver unload, or wake on lan is not enabled, remove the link.
4438 **/
4439 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
4440 {
4441 /* If the management interface is not enabled, then power down */
4442 if (!(hw->mac.ops.check_mng_mode(hw) ||
4443 hw->phy.ops.check_reset_block(hw)))
4444 e1000_power_down_phy_copper(hw);
4445 }
4446
4447 /**
4448 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4449 * @hw: pointer to the HW structure
4450 *
4451 * Clears hardware counters specific to the silicon family and calls
4452 * clear_hw_cntrs_generic to clear all general purpose counters.
4453 **/
4454 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
4455 {
4456 u16 phy_data;
4457 s32 ret_val;
4458
4459 e1000e_clear_hw_cntrs_base(hw);
4460
4461 er32(ALGNERRC);
4462 er32(RXERRC);
4463 er32(TNCRS);
4464 er32(CEXTERR);
4465 er32(TSCTC);
4466 er32(TSCTFC);
4467
4468 er32(MGTPRC);
4469 er32(MGTPDC);
4470 er32(MGTPTC);
4471
4472 er32(IAC);
4473 er32(ICRXOC);
4474
4475 /* Clear PHY statistics registers */
4476 if ((hw->phy.type == e1000_phy_82578) ||
4477 (hw->phy.type == e1000_phy_82579) ||
4478 (hw->phy.type == e1000_phy_i217) ||
4479 (hw->phy.type == e1000_phy_82577)) {
4480 ret_val = hw->phy.ops.acquire(hw);
4481 if (ret_val)
4482 return;
4483 ret_val = hw->phy.ops.set_page(hw,
4484 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4485 if (ret_val)
4486 goto release;
4487 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4488 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4489 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4490 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4491 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4492 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4493 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4494 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4495 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4496 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4497 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4498 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4499 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4500 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4501 release:
4502 hw->phy.ops.release(hw);
4503 }
4504 }
4505
4506 static const struct e1000_mac_operations ich8_mac_ops = {
4507 /* check_mng_mode dependent on mac type */
4508 .check_for_link = e1000_check_for_copper_link_ich8lan,
4509 /* cleanup_led dependent on mac type */
4510 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
4511 .get_bus_info = e1000_get_bus_info_ich8lan,
4512 .set_lan_id = e1000_set_lan_id_single_port,
4513 .get_link_up_info = e1000_get_link_up_info_ich8lan,
4514 /* led_on dependent on mac type */
4515 /* led_off dependent on mac type */
4516 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
4517 .reset_hw = e1000_reset_hw_ich8lan,
4518 .init_hw = e1000_init_hw_ich8lan,
4519 .setup_link = e1000_setup_link_ich8lan,
4520 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4521 /* id_led_init dependent on mac type */
4522 .config_collision_dist = e1000e_config_collision_dist_generic,
4523 .rar_set = e1000e_rar_set_generic,
4524 };
4525
4526 static const struct e1000_phy_operations ich8_phy_ops = {
4527 .acquire = e1000_acquire_swflag_ich8lan,
4528 .check_reset_block = e1000_check_reset_block_ich8lan,
4529 .commit = NULL,
4530 .get_cfg_done = e1000_get_cfg_done_ich8lan,
4531 .get_cable_length = e1000e_get_cable_length_igp_2,
4532 .read_reg = e1000e_read_phy_reg_igp,
4533 .release = e1000_release_swflag_ich8lan,
4534 .reset = e1000_phy_hw_reset_ich8lan,
4535 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4536 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
4537 .write_reg = e1000e_write_phy_reg_igp,
4538 };
4539
4540 static const struct e1000_nvm_operations ich8_nvm_ops = {
4541 .acquire = e1000_acquire_nvm_ich8lan,
4542 .read = e1000_read_nvm_ich8lan,
4543 .release = e1000_release_nvm_ich8lan,
4544 .reload = e1000e_reload_nvm_generic,
4545 .update = e1000_update_nvm_checksum_ich8lan,
4546 .valid_led_default = e1000_valid_led_default_ich8lan,
4547 .validate = e1000_validate_nvm_checksum_ich8lan,
4548 .write = e1000_write_nvm_ich8lan,
4549 };
4550
4551 const struct e1000_info e1000_ich8_info = {
4552 .mac = e1000_ich8lan,
4553 .flags = FLAG_HAS_WOL
4554 | FLAG_IS_ICH
4555 | FLAG_HAS_CTRLEXT_ON_LOAD
4556 | FLAG_HAS_AMT
4557 | FLAG_HAS_FLASH
4558 | FLAG_APME_IN_WUC,
4559 .pba = 8,
4560 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
4561 .get_variants = e1000_get_variants_ich8lan,
4562 .mac_ops = &ich8_mac_ops,
4563 .phy_ops = &ich8_phy_ops,
4564 .nvm_ops = &ich8_nvm_ops,
4565 };
4566
4567 const struct e1000_info e1000_ich9_info = {
4568 .mac = e1000_ich9lan,
4569 .flags = FLAG_HAS_JUMBO_FRAMES
4570 | FLAG_IS_ICH
4571 | FLAG_HAS_WOL
4572 | FLAG_HAS_CTRLEXT_ON_LOAD
4573 | FLAG_HAS_AMT
4574 | FLAG_HAS_FLASH
4575 | FLAG_APME_IN_WUC,
4576 .pba = 18,
4577 .max_hw_frame_size = DEFAULT_JUMBO,
4578 .get_variants = e1000_get_variants_ich8lan,
4579 .mac_ops = &ich8_mac_ops,
4580 .phy_ops = &ich8_phy_ops,
4581 .nvm_ops = &ich8_nvm_ops,
4582 };
4583
4584 const struct e1000_info e1000_ich10_info = {
4585 .mac = e1000_ich10lan,
4586 .flags = FLAG_HAS_JUMBO_FRAMES
4587 | FLAG_IS_ICH
4588 | FLAG_HAS_WOL
4589 | FLAG_HAS_CTRLEXT_ON_LOAD
4590 | FLAG_HAS_AMT
4591 | FLAG_HAS_FLASH
4592 | FLAG_APME_IN_WUC,
4593 .pba = 18,
4594 .max_hw_frame_size = DEFAULT_JUMBO,
4595 .get_variants = e1000_get_variants_ich8lan,
4596 .mac_ops = &ich8_mac_ops,
4597 .phy_ops = &ich8_phy_ops,
4598 .nvm_ops = &ich8_nvm_ops,
4599 };
4600
4601 const struct e1000_info e1000_pch_info = {
4602 .mac = e1000_pchlan,
4603 .flags = FLAG_IS_ICH
4604 | FLAG_HAS_WOL
4605 | FLAG_HAS_CTRLEXT_ON_LOAD
4606 | FLAG_HAS_AMT
4607 | FLAG_HAS_FLASH
4608 | FLAG_HAS_JUMBO_FRAMES
4609 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4610 | FLAG_APME_IN_WUC,
4611 .flags2 = FLAG2_HAS_PHY_STATS,
4612 .pba = 26,
4613 .max_hw_frame_size = 4096,
4614 .get_variants = e1000_get_variants_ich8lan,
4615 .mac_ops = &ich8_mac_ops,
4616 .phy_ops = &ich8_phy_ops,
4617 .nvm_ops = &ich8_nvm_ops,
4618 };
4619
4620 const struct e1000_info e1000_pch2_info = {
4621 .mac = e1000_pch2lan,
4622 .flags = FLAG_IS_ICH
4623 | FLAG_HAS_WOL
4624 | FLAG_HAS_CTRLEXT_ON_LOAD
4625 | FLAG_HAS_AMT
4626 | FLAG_HAS_FLASH
4627 | FLAG_HAS_JUMBO_FRAMES
4628 | FLAG_APME_IN_WUC,
4629 .flags2 = FLAG2_HAS_PHY_STATS
4630 | FLAG2_HAS_EEE,
4631 .pba = 26,
4632 .max_hw_frame_size = DEFAULT_JUMBO,
4633 .get_variants = e1000_get_variants_ich8lan,
4634 .mac_ops = &ich8_mac_ops,
4635 .phy_ops = &ich8_phy_ops,
4636 .nvm_ops = &ich8_nvm_ops,
4637 };
4638
4639 const struct e1000_info e1000_pch_lpt_info = {
4640 .mac = e1000_pch_lpt,
4641 .flags = FLAG_IS_ICH
4642 | FLAG_HAS_WOL
4643 | FLAG_HAS_CTRLEXT_ON_LOAD
4644 | FLAG_HAS_AMT
4645 | FLAG_HAS_FLASH
4646 | FLAG_HAS_JUMBO_FRAMES
4647 | FLAG_APME_IN_WUC,
4648 .flags2 = FLAG2_HAS_PHY_STATS
4649 | FLAG2_HAS_EEE,
4650 .pba = 26,
4651 .max_hw_frame_size = DEFAULT_JUMBO,
4652 .get_variants = e1000_get_variants_ich8lan,
4653 .mac_ops = &ich8_mac_ops,
4654 .phy_ops = &ich8_phy_ops,
4655 .nvm_ops = &ich8_nvm_ops,
4656 };
Linux kernel - Deliverables
This page took 0.249957 seconds and 4 git commands to generate.