1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 /* 82562G 10/100 Network Connection
30 * 82562G-2 10/100 Network Connection
31 * 82562GT 10/100 Network Connection
32 * 82562GT-2 10/100 Network Connection
33 * 82562V 10/100 Network Connection
34 * 82562V-2 10/100 Network Connection
35 * 82566DC-2 Gigabit Network Connection
36 * 82566DC Gigabit Network Connection
37 * 82566DM-2 Gigabit Network Connection
38 * 82566DM Gigabit Network Connection
39 * 82566MC Gigabit Network Connection
40 * 82566MM Gigabit Network Connection
41 * 82567LM Gigabit Network Connection
42 * 82567LF Gigabit Network Connection
43 * 82567V Gigabit Network Connection
44 * 82567LM-2 Gigabit Network Connection
45 * 82567LF-2 Gigabit Network Connection
46 * 82567V-2 Gigabit Network Connection
47 * 82567LF-3 Gigabit Network Connection
48 * 82567LM-3 Gigabit Network Connection
49 * 82567LM-4 Gigabit Network Connection
50 * 82577LM Gigabit Network Connection
51 * 82577LC Gigabit Network Connection
52 * 82578DM Gigabit Network Connection
53 * 82578DC Gigabit Network Connection
54 * 82579LM Gigabit Network Connection
55 * 82579V Gigabit Network Connection
60 #define ICH_FLASH_GFPREG 0x0000
61 #define ICH_FLASH_HSFSTS 0x0004
62 #define ICH_FLASH_HSFCTL 0x0006
63 #define ICH_FLASH_FADDR 0x0008
64 #define ICH_FLASH_FDATA0 0x0010
65 #define ICH_FLASH_PR0 0x0074
67 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
70 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
71 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73 #define ICH_CYCLE_READ 0
74 #define ICH_CYCLE_WRITE 2
75 #define ICH_CYCLE_ERASE 3
77 #define FLASH_GFPREG_BASE_MASK 0x1FFF
78 #define FLASH_SECTOR_ADDR_SHIFT 12
80 #define ICH_FLASH_SEG_SIZE_256 256
81 #define ICH_FLASH_SEG_SIZE_4K 4096
82 #define ICH_FLASH_SEG_SIZE_8K 8192
83 #define ICH_FLASH_SEG_SIZE_64K 65536
86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87 /* FW established a valid mode */
88 #define E1000_ICH_FWSM_FW_VALID 0x00008000
90 #define E1000_ICH_MNG_IAMT_MODE 0x2
92 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
93 (ID_LED_DEF1_OFF2 << 8) | \
94 (ID_LED_DEF1_ON2 << 4) | \
97 #define E1000_ICH_NVM_SIG_WORD 0x13
98 #define E1000_ICH_NVM_SIG_MASK 0xC000
99 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
100 #define E1000_ICH_NVM_SIG_VALUE 0x80
102 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104 #define E1000_FEXTNVM_SW_CONFIG 1
105 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
108 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000
110 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
111 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
112 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
114 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
116 #define E1000_ICH_RAR_ENTRIES 7
117 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */
118 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */
120 #define PHY_PAGE_SHIFT 5
121 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
122 ((reg) & MAX_PHY_REG_ADDRESS))
123 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
124 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
126 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
127 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
128 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
130 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
132 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
134 /* SMBus Control Phy Register */
135 #define CV_SMB_CTRL PHY_REG(769, 23)
136 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
138 /* SMBus Address Phy Register */
139 #define HV_SMB_ADDR PHY_REG(768, 26)
140 #define HV_SMB_ADDR_MASK 0x007F
141 #define HV_SMB_ADDR_PEC_EN 0x0200
142 #define HV_SMB_ADDR_VALID 0x0080
143 #define HV_SMB_ADDR_FREQ_MASK 0x1100
144 #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8
145 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12
147 /* PHY Power Management Control */
148 #define HV_PM_CTRL PHY_REG(770, 17)
149 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
151 /* Intel Rapid Start Technology Support */
152 #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70)
153 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080
154 #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28)
155 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000
156 #define I217_CGFREG PHY_REG(772, 29)
157 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002
158 #define I217_MEMPWR PHY_REG(772, 26)
159 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
161 /* Strapping Option Register - RO */
162 #define E1000_STRAP 0x0000C
163 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
164 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
165 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000
166 #define E1000_STRAP_SMT_FREQ_SHIFT 12
168 /* OEM Bits Phy Register */
169 #define HV_OEM_BITS PHY_REG(768, 25)
170 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
171 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
172 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
174 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
175 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
177 /* KMRN Mode Control */
178 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
179 #define HV_KMRN_MDIO_SLOW 0x0400
181 /* KMRN FIFO Control and Status */
182 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16)
183 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000
184 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12
186 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
187 /* Offset 04h HSFSTS */
188 union ich8_hws_flash_status
{
190 u16 flcdone
:1; /* bit 0 Flash Cycle Done */
191 u16 flcerr
:1; /* bit 1 Flash Cycle Error */
192 u16 dael
:1; /* bit 2 Direct Access error Log */
193 u16 berasesz
:2; /* bit 4:3 Sector Erase Size */
194 u16 flcinprog
:1; /* bit 5 flash cycle in Progress */
195 u16 reserved1
:2; /* bit 13:6 Reserved */
196 u16 reserved2
:6; /* bit 13:6 Reserved */
197 u16 fldesvalid
:1; /* bit 14 Flash Descriptor Valid */
198 u16 flockdn
:1; /* bit 15 Flash Config Lock-Down */
203 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
204 /* Offset 06h FLCTL */
205 union ich8_hws_flash_ctrl
{
206 struct ich8_hsflctl
{
207 u16 flcgo
:1; /* 0 Flash Cycle Go */
208 u16 flcycle
:2; /* 2:1 Flash Cycle */
209 u16 reserved
:5; /* 7:3 Reserved */
210 u16 fldbcount
:2; /* 9:8 Flash Data Byte Count */
211 u16 flockdn
:6; /* 15:10 Reserved */
216 /* ICH Flash Region Access Permissions */
217 union ich8_hws_flash_regacc
{
219 u32 grra
:8; /* 0:7 GbE region Read Access */
220 u32 grwa
:8; /* 8:15 GbE region Write Access */
221 u32 gmrag
:8; /* 23:16 GbE Master Read Access Grant */
222 u32 gmwag
:8; /* 31:24 GbE Master Write Access Grant */
227 /* ICH Flash Protected Region */
228 union ich8_flash_protected_range
{
230 u32 base
:13; /* 0:12 Protected Range Base */
231 u32 reserved1
:2; /* 13:14 Reserved */
232 u32 rpe
:1; /* 15 Read Protection Enable */
233 u32 limit
:13; /* 16:28 Protected Range Limit */
234 u32 reserved2
:2; /* 29:30 Reserved */
235 u32 wpe
:1; /* 31 Write Protection Enable */
240 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
);
241 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
);
242 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
);
243 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
);
244 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
245 u32 offset
, u8 byte
);
246 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
248 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
250 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
252 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
);
253 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
);
254 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
);
255 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
);
256 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
);
257 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
);
258 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
);
259 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
);
260 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
);
261 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
);
262 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
);
263 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
);
264 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
);
265 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
);
266 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
);
267 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
);
268 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
);
269 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
);
270 static void e1000_rar_set_pch2lan(struct e1000_hw
*hw
, u8
*addr
, u32 index
);
271 static void e1000_rar_set_pch_lpt(struct e1000_hw
*hw
, u8
*addr
, u32 index
);
272 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
);
273 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
);
275 static inline u16
__er16flash(struct e1000_hw
*hw
, unsigned long reg
)
277 return readw(hw
->flash_address
+ reg
);
280 static inline u32
__er32flash(struct e1000_hw
*hw
, unsigned long reg
)
282 return readl(hw
->flash_address
+ reg
);
285 static inline void __ew16flash(struct e1000_hw
*hw
, unsigned long reg
, u16 val
)
287 writew(val
, hw
->flash_address
+ reg
);
290 static inline void __ew32flash(struct e1000_hw
*hw
, unsigned long reg
, u32 val
)
292 writel(val
, hw
->flash_address
+ reg
);
295 #define er16flash(reg) __er16flash(hw, (reg))
296 #define er32flash(reg) __er32flash(hw, (reg))
297 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
298 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
301 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
302 * @hw: pointer to the HW structure
304 * Test access to the PHY registers by reading the PHY ID registers. If
305 * the PHY ID is already known (e.g. resume path) compare it with known ID,
306 * otherwise assume the read PHY ID is correct if it is valid.
308 * Assumes the sw/fw/hw semaphore is already acquired.
310 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw
*hw
)
317 for (retry_count
= 0; retry_count
< 2; retry_count
++) {
318 ret_val
= e1e_rphy_locked(hw
, PHY_ID1
, &phy_reg
);
319 if (ret_val
|| (phy_reg
== 0xFFFF))
321 phy_id
= (u32
)(phy_reg
<< 16);
323 ret_val
= e1e_rphy_locked(hw
, PHY_ID2
, &phy_reg
);
324 if (ret_val
|| (phy_reg
== 0xFFFF)) {
328 phy_id
|= (u32
)(phy_reg
& PHY_REVISION_MASK
);
333 if (hw
->phy
.id
== phy_id
)
337 hw
->phy
.revision
= (u32
)(phy_reg
& ~PHY_REVISION_MASK
);
341 /* In case the PHY needs to be in mdio slow mode,
342 * set slow mode and try to get the PHY id again.
344 hw
->phy
.ops
.release(hw
);
345 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
347 ret_val
= e1000e_get_phy_id(hw
);
348 hw
->phy
.ops
.acquire(hw
);
354 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
355 * @hw: pointer to the HW structure
357 * Workarounds/flow necessary for PHY initialization during driver load
360 static s32
e1000_init_phy_workarounds_pchlan(struct e1000_hw
*hw
)
362 u32 mac_reg
, fwsm
= er32(FWSM
);
366 ret_val
= hw
->phy
.ops
.acquire(hw
);
368 e_dbg("Failed to initialize PHY flow\n");
372 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
373 * inaccessible and resetting the PHY is not blocked, toggle the
374 * LANPHYPC Value bit to force the interconnect to PCIe mode.
376 switch (hw
->mac
.type
) {
378 if (e1000_phy_is_accessible_pchlan(hw
))
381 /* Before toggling LANPHYPC, see if PHY is accessible by
382 * forcing MAC to SMBus mode first.
384 mac_reg
= er32(CTRL_EXT
);
385 mac_reg
|= E1000_CTRL_EXT_FORCE_SMBUS
;
386 ew32(CTRL_EXT
, mac_reg
);
390 /* Gate automatic PHY configuration by hardware on
393 if ((hw
->mac
.type
== e1000_pch2lan
) &&
394 !(fwsm
& E1000_ICH_FWSM_FW_VALID
))
395 e1000_gate_hw_phy_config_ich8lan(hw
, true);
397 if (e1000_phy_is_accessible_pchlan(hw
)) {
398 if (hw
->mac
.type
== e1000_pch_lpt
) {
399 /* Unforce SMBus mode in PHY */
400 e1e_rphy_locked(hw
, CV_SMB_CTRL
, &phy_reg
);
401 phy_reg
&= ~CV_SMB_CTRL_FORCE_SMBUS
;
402 e1e_wphy_locked(hw
, CV_SMB_CTRL
, phy_reg
);
404 /* Unforce SMBus mode in MAC */
405 mac_reg
= er32(CTRL_EXT
);
406 mac_reg
&= ~E1000_CTRL_EXT_FORCE_SMBUS
;
407 ew32(CTRL_EXT
, mac_reg
);
414 if ((hw
->mac
.type
== e1000_pchlan
) &&
415 (fwsm
& E1000_ICH_FWSM_FW_VALID
))
418 if (hw
->phy
.ops
.check_reset_block(hw
)) {
419 e_dbg("Required LANPHYPC toggle blocked by ME\n");
423 e_dbg("Toggling LANPHYPC\n");
425 /* Set Phy Config Counter to 50msec */
426 mac_reg
= er32(FEXTNVM3
);
427 mac_reg
&= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK
;
428 mac_reg
|= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
;
429 ew32(FEXTNVM3
, mac_reg
);
431 /* Toggle LANPHYPC Value bit */
432 mac_reg
= er32(CTRL
);
433 mac_reg
|= E1000_CTRL_LANPHYPC_OVERRIDE
;
434 mac_reg
&= ~E1000_CTRL_LANPHYPC_VALUE
;
438 mac_reg
&= ~E1000_CTRL_LANPHYPC_OVERRIDE
;
441 if (hw
->mac
.type
< e1000_pch_lpt
) {
446 usleep_range(5000, 10000);
447 } while (!(er32(CTRL_EXT
) &
448 E1000_CTRL_EXT_LPCD
) && count
--);
455 hw
->phy
.ops
.release(hw
);
457 /* Reset the PHY before any access to it. Doing so, ensures
458 * that the PHY is in a known good state before we read/write
459 * PHY registers. The generic reset is sufficient here,
460 * because we haven't determined the PHY type yet.
462 ret_val
= e1000e_phy_hw_reset_generic(hw
);
464 /* Ungate automatic PHY configuration on non-managed 82579 */
465 if ((hw
->mac
.type
== e1000_pch2lan
) &&
466 !(fwsm
& E1000_ICH_FWSM_FW_VALID
)) {
467 usleep_range(10000, 20000);
468 e1000_gate_hw_phy_config_ich8lan(hw
, false);
475 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
476 * @hw: pointer to the HW structure
478 * Initialize family-specific PHY parameters and function pointers.
480 static s32
e1000_init_phy_params_pchlan(struct e1000_hw
*hw
)
482 struct e1000_phy_info
*phy
= &hw
->phy
;
486 phy
->reset_delay_us
= 100;
488 phy
->ops
.set_page
= e1000_set_page_igp
;
489 phy
->ops
.read_reg
= e1000_read_phy_reg_hv
;
490 phy
->ops
.read_reg_locked
= e1000_read_phy_reg_hv_locked
;
491 phy
->ops
.read_reg_page
= e1000_read_phy_reg_page_hv
;
492 phy
->ops
.set_d0_lplu_state
= e1000_set_lplu_state_pchlan
;
493 phy
->ops
.set_d3_lplu_state
= e1000_set_lplu_state_pchlan
;
494 phy
->ops
.write_reg
= e1000_write_phy_reg_hv
;
495 phy
->ops
.write_reg_locked
= e1000_write_phy_reg_hv_locked
;
496 phy
->ops
.write_reg_page
= e1000_write_phy_reg_page_hv
;
497 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
498 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
499 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
501 phy
->id
= e1000_phy_unknown
;
503 ret_val
= e1000_init_phy_workarounds_pchlan(hw
);
507 if (phy
->id
== e1000_phy_unknown
)
508 switch (hw
->mac
.type
) {
510 ret_val
= e1000e_get_phy_id(hw
);
513 if ((phy
->id
!= 0) && (phy
->id
!= PHY_REVISION_MASK
))
518 /* In case the PHY needs to be in mdio slow mode,
519 * set slow mode and try to get the PHY id again.
521 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
524 ret_val
= e1000e_get_phy_id(hw
);
529 phy
->type
= e1000e_get_phy_type_from_id(phy
->id
);
532 case e1000_phy_82577
:
533 case e1000_phy_82579
:
535 phy
->ops
.check_polarity
= e1000_check_polarity_82577
;
536 phy
->ops
.force_speed_duplex
=
537 e1000_phy_force_speed_duplex_82577
;
538 phy
->ops
.get_cable_length
= e1000_get_cable_length_82577
;
539 phy
->ops
.get_info
= e1000_get_phy_info_82577
;
540 phy
->ops
.commit
= e1000e_phy_sw_reset
;
542 case e1000_phy_82578
:
543 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
544 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
545 phy
->ops
.get_cable_length
= e1000e_get_cable_length_m88
;
546 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
549 ret_val
= -E1000_ERR_PHY
;
557 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
558 * @hw: pointer to the HW structure
560 * Initialize family-specific PHY parameters and function pointers.
562 static s32
e1000_init_phy_params_ich8lan(struct e1000_hw
*hw
)
564 struct e1000_phy_info
*phy
= &hw
->phy
;
569 phy
->reset_delay_us
= 100;
571 phy
->ops
.power_up
= e1000_power_up_phy_copper
;
572 phy
->ops
.power_down
= e1000_power_down_phy_copper_ich8lan
;
574 /* We may need to do this twice - once for IGP and if that fails,
575 * we'll set BM func pointers and try again
577 ret_val
= e1000e_determine_phy_address(hw
);
579 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
580 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
581 ret_val
= e1000e_determine_phy_address(hw
);
583 e_dbg("Cannot determine PHY addr. Erroring out\n");
589 while ((e1000_phy_unknown
== e1000e_get_phy_type_from_id(phy
->id
)) &&
591 usleep_range(1000, 2000);
592 ret_val
= e1000e_get_phy_id(hw
);
599 case IGP03E1000_E_PHY_ID
:
600 phy
->type
= e1000_phy_igp_3
;
601 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
602 phy
->ops
.read_reg_locked
= e1000e_read_phy_reg_igp_locked
;
603 phy
->ops
.write_reg_locked
= e1000e_write_phy_reg_igp_locked
;
604 phy
->ops
.get_info
= e1000e_get_phy_info_igp
;
605 phy
->ops
.check_polarity
= e1000_check_polarity_igp
;
606 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_igp
;
609 case IFE_PLUS_E_PHY_ID
:
611 phy
->type
= e1000_phy_ife
;
612 phy
->autoneg_mask
= E1000_ALL_NOT_GIG
;
613 phy
->ops
.get_info
= e1000_get_phy_info_ife
;
614 phy
->ops
.check_polarity
= e1000_check_polarity_ife
;
615 phy
->ops
.force_speed_duplex
= e1000_phy_force_speed_duplex_ife
;
617 case BME1000_E_PHY_ID
:
618 phy
->type
= e1000_phy_bm
;
619 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
620 phy
->ops
.read_reg
= e1000e_read_phy_reg_bm
;
621 phy
->ops
.write_reg
= e1000e_write_phy_reg_bm
;
622 phy
->ops
.commit
= e1000e_phy_sw_reset
;
623 phy
->ops
.get_info
= e1000e_get_phy_info_m88
;
624 phy
->ops
.check_polarity
= e1000_check_polarity_m88
;
625 phy
->ops
.force_speed_duplex
= e1000e_phy_force_speed_duplex_m88
;
628 return -E1000_ERR_PHY
;
636 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
637 * @hw: pointer to the HW structure
639 * Initialize family-specific NVM parameters and function
642 static s32
e1000_init_nvm_params_ich8lan(struct e1000_hw
*hw
)
644 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
645 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
646 u32 gfpreg
, sector_base_addr
, sector_end_addr
;
649 /* Can't read flash registers if the register set isn't mapped. */
650 if (!hw
->flash_address
) {
651 e_dbg("ERROR: Flash registers not mapped\n");
652 return -E1000_ERR_CONFIG
;
655 nvm
->type
= e1000_nvm_flash_sw
;
657 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
659 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
660 * Add 1 to sector_end_addr since this sector is included in
663 sector_base_addr
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
664 sector_end_addr
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
) + 1;
666 /* flash_base_addr is byte-aligned */
667 nvm
->flash_base_addr
= sector_base_addr
<< FLASH_SECTOR_ADDR_SHIFT
;
669 /* find total size of the NVM, then cut in half since the total
670 * size represents two separate NVM banks.
672 nvm
->flash_bank_size
= (sector_end_addr
- sector_base_addr
)
673 << FLASH_SECTOR_ADDR_SHIFT
;
674 nvm
->flash_bank_size
/= 2;
675 /* Adjust to word count */
676 nvm
->flash_bank_size
/= sizeof(u16
);
678 nvm
->word_size
= E1000_ICH8_SHADOW_RAM_WORDS
;
680 /* Clear shadow ram */
681 for (i
= 0; i
< nvm
->word_size
; i
++) {
682 dev_spec
->shadow_ram
[i
].modified
= false;
683 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
690 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
691 * @hw: pointer to the HW structure
693 * Initialize family-specific MAC parameters and function
696 static s32
e1000_init_mac_params_ich8lan(struct e1000_hw
*hw
)
698 struct e1000_mac_info
*mac
= &hw
->mac
;
700 /* Set media type function pointer */
701 hw
->phy
.media_type
= e1000_media_type_copper
;
703 /* Set mta register count */
704 mac
->mta_reg_count
= 32;
705 /* Set rar entry count */
706 mac
->rar_entry_count
= E1000_ICH_RAR_ENTRIES
;
707 if (mac
->type
== e1000_ich8lan
)
708 mac
->rar_entry_count
--;
710 mac
->has_fwsm
= true;
711 /* ARC subsystem not supported */
712 mac
->arc_subsystem_valid
= false;
713 /* Adaptive IFS supported */
714 mac
->adaptive_ifs
= true;
716 /* LED and other operations */
721 /* check management mode */
722 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_ich8lan
;
724 mac
->ops
.id_led_init
= e1000e_id_led_init_generic
;
726 mac
->ops
.blink_led
= e1000e_blink_led_generic
;
728 mac
->ops
.setup_led
= e1000e_setup_led_generic
;
730 mac
->ops
.cleanup_led
= e1000_cleanup_led_ich8lan
;
731 /* turn on/off LED */
732 mac
->ops
.led_on
= e1000_led_on_ich8lan
;
733 mac
->ops
.led_off
= e1000_led_off_ich8lan
;
736 mac
->rar_entry_count
= E1000_PCH2_RAR_ENTRIES
;
737 mac
->ops
.rar_set
= e1000_rar_set_pch2lan
;
741 /* check management mode */
742 mac
->ops
.check_mng_mode
= e1000_check_mng_mode_pchlan
;
744 mac
->ops
.id_led_init
= e1000_id_led_init_pchlan
;
746 mac
->ops
.setup_led
= e1000_setup_led_pchlan
;
748 mac
->ops
.cleanup_led
= e1000_cleanup_led_pchlan
;
749 /* turn on/off LED */
750 mac
->ops
.led_on
= e1000_led_on_pchlan
;
751 mac
->ops
.led_off
= e1000_led_off_pchlan
;
757 if (mac
->type
== e1000_pch_lpt
) {
758 mac
->rar_entry_count
= E1000_PCH_LPT_RAR_ENTRIES
;
759 mac
->ops
.rar_set
= e1000_rar_set_pch_lpt
;
762 /* Enable PCS Lock-loss workaround for ICH8 */
763 if (mac
->type
== e1000_ich8lan
)
764 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw
, true);
766 /* Gate automatic PHY configuration by hardware on managed
769 if ((mac
->type
== e1000_pch2lan
|| mac
->type
== e1000_pch_lpt
) &&
770 (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
771 e1000_gate_hw_phy_config_ich8lan(hw
, true);
777 * __e1000_access_emi_reg_locked - Read/write EMI register
778 * @hw: pointer to the HW structure
779 * @addr: EMI address to program
780 * @data: pointer to value to read/write from/to the EMI address
781 * @read: boolean flag to indicate read or write
783 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
785 static s32
__e1000_access_emi_reg_locked(struct e1000_hw
*hw
, u16 address
,
786 u16
*data
, bool read
)
790 ret_val
= e1e_wphy_locked(hw
, I82579_EMI_ADDR
, address
);
795 ret_val
= e1e_rphy_locked(hw
, I82579_EMI_DATA
, data
);
797 ret_val
= e1e_wphy_locked(hw
, I82579_EMI_DATA
, *data
);
803 * e1000_read_emi_reg_locked - Read Extended Management Interface register
804 * @hw: pointer to the HW structure
805 * @addr: EMI address to program
806 * @data: value to be read from the EMI address
808 * Assumes the SW/FW/HW Semaphore is already acquired.
810 s32
e1000_read_emi_reg_locked(struct e1000_hw
*hw
, u16 addr
, u16
*data
)
812 return __e1000_access_emi_reg_locked(hw
, addr
, data
, true);
816 * e1000_write_emi_reg_locked - Write Extended Management Interface register
817 * @hw: pointer to the HW structure
818 * @addr: EMI address to program
819 * @data: value to be written to the EMI address
821 * Assumes the SW/FW/HW Semaphore is already acquired.
823 static s32
e1000_write_emi_reg_locked(struct e1000_hw
*hw
, u16 addr
, u16 data
)
825 return __e1000_access_emi_reg_locked(hw
, addr
, &data
, false);
829 * e1000_set_eee_pchlan - Enable/disable EEE support
830 * @hw: pointer to the HW structure
832 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
833 * the link and the EEE capabilities of the link partner. The LPI Control
834 * register bits will remain set only if/when link is up.
836 static s32
e1000_set_eee_pchlan(struct e1000_hw
*hw
)
838 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
842 if ((hw
->phy
.type
!= e1000_phy_82579
) &&
843 (hw
->phy
.type
!= e1000_phy_i217
))
846 ret_val
= hw
->phy
.ops
.acquire(hw
);
850 ret_val
= e1e_rphy_locked(hw
, I82579_LPI_CTRL
, &lpi_ctrl
);
854 /* Clear bits that enable EEE in various speeds */
855 lpi_ctrl
&= ~I82579_LPI_CTRL_ENABLE_MASK
;
857 /* Enable EEE if not disabled by user */
858 if (!dev_spec
->eee_disable
) {
859 u16 lpa
, pcs_status
, data
;
861 /* Save off link partner's EEE ability */
862 switch (hw
->phy
.type
) {
863 case e1000_phy_82579
:
864 lpa
= I82579_EEE_LP_ABILITY
;
865 pcs_status
= I82579_EEE_PCS_STATUS
;
868 lpa
= I217_EEE_LP_ABILITY
;
869 pcs_status
= I217_EEE_PCS_STATUS
;
872 ret_val
= -E1000_ERR_PHY
;
875 ret_val
= e1000_read_emi_reg_locked(hw
, lpa
,
876 &dev_spec
->eee_lp_ability
);
880 /* Enable EEE only for speeds in which the link partner is
883 if (dev_spec
->eee_lp_ability
& I82579_EEE_1000_SUPPORTED
)
884 lpi_ctrl
|= I82579_LPI_CTRL_1000_ENABLE
;
886 if (dev_spec
->eee_lp_ability
& I82579_EEE_100_SUPPORTED
) {
887 e1e_rphy_locked(hw
, PHY_LP_ABILITY
, &data
);
888 if (data
& NWAY_LPAR_100TX_FD_CAPS
)
889 lpi_ctrl
|= I82579_LPI_CTRL_100_ENABLE
;
891 /* EEE is not supported in 100Half, so ignore
892 * partner's EEE in 100 ability if full-duplex
895 dev_spec
->eee_lp_ability
&=
896 ~I82579_EEE_100_SUPPORTED
;
899 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
900 ret_val
= e1000_read_emi_reg_locked(hw
, pcs_status
, &data
);
905 ret_val
= e1e_wphy_locked(hw
, I82579_LPI_CTRL
, lpi_ctrl
);
907 hw
->phy
.ops
.release(hw
);
913 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
914 * @hw: pointer to the HW structure
916 * Checks to see of the link status of the hardware has changed. If a
917 * change in link status has been detected, then we read the PHY registers
918 * to get the current speed/duplex if link exists.
920 static s32
e1000_check_for_copper_link_ich8lan(struct e1000_hw
*hw
)
922 struct e1000_mac_info
*mac
= &hw
->mac
;
927 /* We only want to go out to the PHY registers to see if Auto-Neg
928 * has completed and/or if our link status has changed. The
929 * get_link_status flag is set upon receiving a Link Status
930 * Change or Rx Sequence Error interrupt.
932 if (!mac
->get_link_status
)
935 /* First we want to see if the MII Status Register reports
936 * link. If so, then we want to get the current speed/duplex
939 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
943 if (hw
->mac
.type
== e1000_pchlan
) {
944 ret_val
= e1000_k1_gig_workaround_hv(hw
, link
);
949 /* Clear link partner's EEE ability */
950 hw
->dev_spec
.ich8lan
.eee_lp_ability
= 0;
953 return 0; /* No link detected */
955 mac
->get_link_status
= false;
957 switch (hw
->mac
.type
) {
959 ret_val
= e1000_k1_workaround_lv(hw
);
964 if (hw
->phy
.type
== e1000_phy_82578
) {
965 ret_val
= e1000_link_stall_workaround_hv(hw
);
970 /* Workaround for PCHx parts in half-duplex:
971 * Set the number of preambles removed from the packet
972 * when it is passed from the PHY to the MAC to prevent
973 * the MAC from misinterpreting the packet type.
975 e1e_rphy(hw
, HV_KMRN_FIFO_CTRLSTA
, &phy_reg
);
976 phy_reg
&= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK
;
978 if ((er32(STATUS
) & E1000_STATUS_FD
) != E1000_STATUS_FD
)
979 phy_reg
|= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT
);
981 e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, phy_reg
);
987 /* Check if there was DownShift, must be checked
988 * immediately after link-up
990 e1000e_check_downshift(hw
);
992 /* Enable/Disable EEE after link up */
993 ret_val
= e1000_set_eee_pchlan(hw
);
997 /* If we are forcing speed/duplex, then we simply return since
998 * we have already determined whether we have link or not.
1001 return -E1000_ERR_CONFIG
;
1003 /* Auto-Neg is enabled. Auto Speed Detection takes care
1004 * of MAC speed/duplex configuration. So we only need to
1005 * configure Collision Distance in the MAC.
1007 mac
->ops
.config_collision_dist(hw
);
1009 /* Configure Flow Control now that Auto-Neg has completed.
1010 * First, we need to restore the desired flow control
1011 * settings because we may have had to re-autoneg with a
1012 * different link partner.
1014 ret_val
= e1000e_config_fc_after_link_up(hw
);
1016 e_dbg("Error configuring flow control\n");
1021 static s32
e1000_get_variants_ich8lan(struct e1000_adapter
*adapter
)
1023 struct e1000_hw
*hw
= &adapter
->hw
;
1026 rc
= e1000_init_mac_params_ich8lan(hw
);
1030 rc
= e1000_init_nvm_params_ich8lan(hw
);
1034 switch (hw
->mac
.type
) {
1037 case e1000_ich10lan
:
1038 rc
= e1000_init_phy_params_ich8lan(hw
);
1043 rc
= e1000_init_phy_params_pchlan(hw
);
1051 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1052 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1054 if ((adapter
->hw
.phy
.type
== e1000_phy_ife
) ||
1055 ((adapter
->hw
.mac
.type
>= e1000_pch2lan
) &&
1056 (!(er32(CTRL_EXT
) & E1000_CTRL_EXT_LSECCK
)))) {
1057 adapter
->flags
&= ~FLAG_HAS_JUMBO_FRAMES
;
1058 adapter
->max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
;
1060 hw
->mac
.ops
.blink_led
= NULL
;
1063 if ((adapter
->hw
.mac
.type
== e1000_ich8lan
) &&
1064 (adapter
->hw
.phy
.type
!= e1000_phy_ife
))
1065 adapter
->flags
|= FLAG_LSC_GIG_SPEED_DROP
;
1067 /* Enable workaround for 82579 w/ ME enabled */
1068 if ((adapter
->hw
.mac
.type
== e1000_pch2lan
) &&
1069 (er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
1070 adapter
->flags2
|= FLAG2_PCIM2PCI_ARBITER_WA
;
1072 /* Disable EEE by default until IEEE802.3az spec is finalized */
1073 if (adapter
->flags2
& FLAG2_HAS_EEE
)
1074 adapter
->hw
.dev_spec
.ich8lan
.eee_disable
= true;
1079 static DEFINE_MUTEX(nvm_mutex
);
1082 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1083 * @hw: pointer to the HW structure
1085 * Acquires the mutex for performing NVM operations.
1087 static s32
e1000_acquire_nvm_ich8lan(struct e1000_hw
*hw
)
1089 mutex_lock(&nvm_mutex
);
1095 * e1000_release_nvm_ich8lan - Release NVM mutex
1096 * @hw: pointer to the HW structure
1098 * Releases the mutex used while performing NVM operations.
1100 static void e1000_release_nvm_ich8lan(struct e1000_hw
*hw
)
1102 mutex_unlock(&nvm_mutex
);
1106 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1107 * @hw: pointer to the HW structure
1109 * Acquires the software control flag for performing PHY and select
1112 static s32
e1000_acquire_swflag_ich8lan(struct e1000_hw
*hw
)
1114 u32 extcnf_ctrl
, timeout
= PHY_CFG_TIMEOUT
;
1117 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE
,
1118 &hw
->adapter
->state
)) {
1119 e_dbg("contention for Phy access\n");
1120 return -E1000_ERR_PHY
;
1124 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1125 if (!(extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
))
1133 e_dbg("SW has already locked the resource.\n");
1134 ret_val
= -E1000_ERR_CONFIG
;
1138 timeout
= SW_FLAG_TIMEOUT
;
1140 extcnf_ctrl
|= E1000_EXTCNF_CTRL_SWFLAG
;
1141 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1144 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1145 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
)
1153 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1154 er32(FWSM
), extcnf_ctrl
);
1155 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
1156 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1157 ret_val
= -E1000_ERR_CONFIG
;
1163 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
1169 * e1000_release_swflag_ich8lan - Release software control flag
1170 * @hw: pointer to the HW structure
1172 * Releases the software control flag for performing PHY and select
1175 static void e1000_release_swflag_ich8lan(struct e1000_hw
*hw
)
1179 extcnf_ctrl
= er32(EXTCNF_CTRL
);
1181 if (extcnf_ctrl
& E1000_EXTCNF_CTRL_SWFLAG
) {
1182 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_SWFLAG
;
1183 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
1185 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1188 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
1192 * e1000_check_mng_mode_ich8lan - Checks management mode
1193 * @hw: pointer to the HW structure
1195 * This checks if the adapter has any manageability enabled.
1196 * This is a function pointer entry point only called by read/write
1197 * routines for the PHY and NVM parts.
1199 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw
*hw
)
1204 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
1205 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1206 (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
1210 * e1000_check_mng_mode_pchlan - Checks management mode
1211 * @hw: pointer to the HW structure
1213 * This checks if the adapter has iAMT enabled.
1214 * This is a function pointer entry point only called by read/write
1215 * routines for the PHY and NVM parts.
1217 static bool e1000_check_mng_mode_pchlan(struct e1000_hw
*hw
)
1222 return (fwsm
& E1000_ICH_FWSM_FW_VALID
) &&
1223 (fwsm
& (E1000_ICH_MNG_IAMT_MODE
<< E1000_FWSM_MODE_SHIFT
));
1227 * e1000_rar_set_pch2lan - Set receive address register
1228 * @hw: pointer to the HW structure
1229 * @addr: pointer to the receive address
1230 * @index: receive address array register
1232 * Sets the receive address array register at index to the address passed
1233 * in by addr. For 82579, RAR[0] is the base address register that is to
1234 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1235 * Use SHRA[0-3] in place of those reserved for ME.
1237 static void e1000_rar_set_pch2lan(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
1239 u32 rar_low
, rar_high
;
1241 /* HW expects these in little endian so we reverse the byte order
1242 * from network order (big endian) to little endian
1244 rar_low
= ((u32
)addr
[0] |
1245 ((u32
)addr
[1] << 8) |
1246 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
1248 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1250 /* If MAC address zero, no need to set the AV bit */
1251 if (rar_low
|| rar_high
)
1252 rar_high
|= E1000_RAH_AV
;
1255 ew32(RAL(index
), rar_low
);
1257 ew32(RAH(index
), rar_high
);
1262 if (index
< hw
->mac
.rar_entry_count
) {
1265 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1269 ew32(SHRAL(index
- 1), rar_low
);
1271 ew32(SHRAH(index
- 1), rar_high
);
1274 e1000_release_swflag_ich8lan(hw
);
1276 /* verify the register updates */
1277 if ((er32(SHRAL(index
- 1)) == rar_low
) &&
1278 (er32(SHRAH(index
- 1)) == rar_high
))
1281 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1282 (index
- 1), er32(FWSM
));
1286 e_dbg("Failed to write receive address at index %d\n", index
);
1290 * e1000_rar_set_pch_lpt - Set receive address registers
1291 * @hw: pointer to the HW structure
1292 * @addr: pointer to the receive address
1293 * @index: receive address array register
1295 * Sets the receive address register array at index to the address passed
1296 * in by addr. For LPT, RAR[0] is the base address register that is to
1297 * contain the MAC address. SHRA[0-10] are the shared receive address
1298 * registers that are shared between the Host and manageability engine (ME).
1300 static void e1000_rar_set_pch_lpt(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
1302 u32 rar_low
, rar_high
;
1305 /* HW expects these in little endian so we reverse the byte order
1306 * from network order (big endian) to little endian
1308 rar_low
= ((u32
)addr
[0] | ((u32
)addr
[1] << 8) |
1309 ((u32
)addr
[2] << 16) | ((u32
)addr
[3] << 24));
1311 rar_high
= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1313 /* If MAC address zero, no need to set the AV bit */
1314 if (rar_low
|| rar_high
)
1315 rar_high
|= E1000_RAH_AV
;
1318 ew32(RAL(index
), rar_low
);
1320 ew32(RAH(index
), rar_high
);
1325 /* The manageability engine (ME) can lock certain SHRAR registers that
1326 * it is using - those registers are unavailable for use.
1328 if (index
< hw
->mac
.rar_entry_count
) {
1329 wlock_mac
= er32(FWSM
) & E1000_FWSM_WLOCK_MAC_MASK
;
1330 wlock_mac
>>= E1000_FWSM_WLOCK_MAC_SHIFT
;
1332 /* Check if all SHRAR registers are locked */
1336 if ((wlock_mac
== 0) || (index
<= wlock_mac
)) {
1339 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
1344 ew32(SHRAL_PCH_LPT(index
- 1), rar_low
);
1346 ew32(SHRAH_PCH_LPT(index
- 1), rar_high
);
1349 e1000_release_swflag_ich8lan(hw
);
1351 /* verify the register updates */
1352 if ((er32(SHRAL_PCH_LPT(index
- 1)) == rar_low
) &&
1353 (er32(SHRAH_PCH_LPT(index
- 1)) == rar_high
))
1359 e_dbg("Failed to write receive address at index %d\n", index
);
1363 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1364 * @hw: pointer to the HW structure
1366 * Checks if firmware is blocking the reset of the PHY.
1367 * This is a function pointer entry point only called by
1370 static s32
e1000_check_reset_block_ich8lan(struct e1000_hw
*hw
)
1376 return (fwsm
& E1000_ICH_FWSM_RSPCIPHY
) ? 0 : E1000_BLK_PHY_RESET
;
1380 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
1381 * @hw: pointer to the HW structure
1383 * Assumes semaphore already acquired.
1386 static s32
e1000_write_smbus_addr(struct e1000_hw
*hw
)
1389 u32 strap
= er32(STRAP
);
1390 u32 freq
= (strap
& E1000_STRAP_SMT_FREQ_MASK
) >>
1391 E1000_STRAP_SMT_FREQ_SHIFT
;
1394 strap
&= E1000_STRAP_SMBUS_ADDRESS_MASK
;
1396 ret_val
= e1000_read_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, &phy_data
);
1400 phy_data
&= ~HV_SMB_ADDR_MASK
;
1401 phy_data
|= (strap
>> E1000_STRAP_SMBUS_ADDRESS_SHIFT
);
1402 phy_data
|= HV_SMB_ADDR_PEC_EN
| HV_SMB_ADDR_VALID
;
1404 if (hw
->phy
.type
== e1000_phy_i217
) {
1405 /* Restore SMBus frequency */
1407 phy_data
&= ~HV_SMB_ADDR_FREQ_MASK
;
1408 phy_data
|= (freq
& (1 << 0)) <<
1409 HV_SMB_ADDR_FREQ_LOW_SHIFT
;
1410 phy_data
|= (freq
& (1 << 1)) <<
1411 (HV_SMB_ADDR_FREQ_HIGH_SHIFT
- 1);
1413 e_dbg("Unsupported SMB frequency in PHY\n");
1417 return e1000_write_phy_reg_hv_locked(hw
, HV_SMB_ADDR
, phy_data
);
1421 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1422 * @hw: pointer to the HW structure
1424 * SW should configure the LCD from the NVM extended configuration region
1425 * as a workaround for certain parts.
1427 static s32
e1000_sw_lcd_config_ich8lan(struct e1000_hw
*hw
)
1429 struct e1000_phy_info
*phy
= &hw
->phy
;
1430 u32 i
, data
, cnf_size
, cnf_base_addr
, sw_cfg_mask
;
1432 u16 word_addr
, reg_data
, reg_addr
, phy_page
= 0;
1434 /* Initialize the PHY from the NVM on ICH platforms. This
1435 * is needed due to an issue where the NVM configuration is
1436 * not properly autoloaded after power transitions.
1437 * Therefore, after each PHY reset, we will load the
1438 * configuration data out of the NVM manually.
1440 switch (hw
->mac
.type
) {
1442 if (phy
->type
!= e1000_phy_igp_3
)
1445 if ((hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_AMT
) ||
1446 (hw
->adapter
->pdev
->device
== E1000_DEV_ID_ICH8_IGP_C
)) {
1447 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG
;
1454 sw_cfg_mask
= E1000_FEXTNVM_SW_CONFIG_ICH8M
;
1460 ret_val
= hw
->phy
.ops
.acquire(hw
);
1464 data
= er32(FEXTNVM
);
1465 if (!(data
& sw_cfg_mask
))
1468 /* Make sure HW does not configure LCD from PHY
1469 * extended configuration before SW configuration
1471 data
= er32(EXTCNF_CTRL
);
1472 if ((hw
->mac
.type
< e1000_pch2lan
) &&
1473 (data
& E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE
))
1476 cnf_size
= er32(EXTCNF_SIZE
);
1477 cnf_size
&= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK
;
1478 cnf_size
>>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT
;
1482 cnf_base_addr
= data
& E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK
;
1483 cnf_base_addr
>>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT
;
1485 if (((hw
->mac
.type
== e1000_pchlan
) &&
1486 !(data
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)) ||
1487 (hw
->mac
.type
> e1000_pchlan
)) {
1488 /* HW configures the SMBus address and LEDs when the
1489 * OEM and LCD Write Enable bits are set in the NVM.
1490 * When both NVM bits are cleared, SW will configure
1493 ret_val
= e1000_write_smbus_addr(hw
);
1497 data
= er32(LEDCTL
);
1498 ret_val
= e1000_write_phy_reg_hv_locked(hw
, HV_LED_CONFIG
,
1504 /* Configure LCD from extended configuration region. */
1506 /* cnf_base_addr is in DWORD */
1507 word_addr
= (u16
)(cnf_base_addr
<< 1);
1509 for (i
= 0; i
< cnf_size
; i
++) {
1510 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2), 1,
1515 ret_val
= e1000_read_nvm(hw
, (word_addr
+ i
* 2 + 1),
1520 /* Save off the PHY page for future writes. */
1521 if (reg_addr
== IGP01E1000_PHY_PAGE_SELECT
) {
1522 phy_page
= reg_data
;
1526 reg_addr
&= PHY_REG_MASK
;
1527 reg_addr
|= phy_page
;
1529 ret_val
= e1e_wphy_locked(hw
, (u32
)reg_addr
, reg_data
);
1535 hw
->phy
.ops
.release(hw
);
1540 * e1000_k1_gig_workaround_hv - K1 Si workaround
1541 * @hw: pointer to the HW structure
1542 * @link: link up bool flag
1544 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1545 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1546 * If link is down, the function will restore the default K1 setting located
1549 static s32
e1000_k1_gig_workaround_hv(struct e1000_hw
*hw
, bool link
)
1553 bool k1_enable
= hw
->dev_spec
.ich8lan
.nvm_k1_enabled
;
1555 if (hw
->mac
.type
!= e1000_pchlan
)
1558 /* Wrap the whole flow with the sw flag */
1559 ret_val
= hw
->phy
.ops
.acquire(hw
);
1563 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1565 if (hw
->phy
.type
== e1000_phy_82578
) {
1566 ret_val
= e1e_rphy_locked(hw
, BM_CS_STATUS
,
1571 status_reg
&= BM_CS_STATUS_LINK_UP
|
1572 BM_CS_STATUS_RESOLVED
|
1573 BM_CS_STATUS_SPEED_MASK
;
1575 if (status_reg
== (BM_CS_STATUS_LINK_UP
|
1576 BM_CS_STATUS_RESOLVED
|
1577 BM_CS_STATUS_SPEED_1000
))
1581 if (hw
->phy
.type
== e1000_phy_82577
) {
1582 ret_val
= e1e_rphy_locked(hw
, HV_M_STATUS
, &status_reg
);
1586 status_reg
&= HV_M_STATUS_LINK_UP
|
1587 HV_M_STATUS_AUTONEG_COMPLETE
|
1588 HV_M_STATUS_SPEED_MASK
;
1590 if (status_reg
== (HV_M_STATUS_LINK_UP
|
1591 HV_M_STATUS_AUTONEG_COMPLETE
|
1592 HV_M_STATUS_SPEED_1000
))
1596 /* Link stall fix for link up */
1597 ret_val
= e1e_wphy_locked(hw
, PHY_REG(770, 19), 0x0100);
1602 /* Link stall fix for link down */
1603 ret_val
= e1e_wphy_locked(hw
, PHY_REG(770, 19), 0x4100);
1608 ret_val
= e1000_configure_k1_ich8lan(hw
, k1_enable
);
1611 hw
->phy
.ops
.release(hw
);
1617 * e1000_configure_k1_ich8lan - Configure K1 power state
1618 * @hw: pointer to the HW structure
1619 * @enable: K1 state to configure
1621 * Configure the K1 power state based on the provided parameter.
1622 * Assumes semaphore already acquired.
1624 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1626 s32
e1000_configure_k1_ich8lan(struct e1000_hw
*hw
, bool k1_enable
)
1634 ret_val
= e1000e_read_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
1640 kmrn_reg
|= E1000_KMRNCTRLSTA_K1_ENABLE
;
1642 kmrn_reg
&= ~E1000_KMRNCTRLSTA_K1_ENABLE
;
1644 ret_val
= e1000e_write_kmrn_reg_locked(hw
, E1000_KMRNCTRLSTA_K1_CONFIG
,
1650 ctrl_ext
= er32(CTRL_EXT
);
1651 ctrl_reg
= er32(CTRL
);
1653 reg
= ctrl_reg
& ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1654 reg
|= E1000_CTRL_FRCSPD
;
1657 ew32(CTRL_EXT
, ctrl_ext
| E1000_CTRL_EXT_SPD_BYPS
);
1660 ew32(CTRL
, ctrl_reg
);
1661 ew32(CTRL_EXT
, ctrl_ext
);
1669 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1670 * @hw: pointer to the HW structure
1671 * @d0_state: boolean if entering d0 or d3 device state
1673 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1674 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1675 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1677 static s32
e1000_oem_bits_config_ich8lan(struct e1000_hw
*hw
, bool d0_state
)
1683 if (hw
->mac
.type
< e1000_pchlan
)
1686 ret_val
= hw
->phy
.ops
.acquire(hw
);
1690 if (hw
->mac
.type
== e1000_pchlan
) {
1691 mac_reg
= er32(EXTCNF_CTRL
);
1692 if (mac_reg
& E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
)
1696 mac_reg
= er32(FEXTNVM
);
1697 if (!(mac_reg
& E1000_FEXTNVM_SW_CONFIG_ICH8M
))
1700 mac_reg
= er32(PHY_CTRL
);
1702 ret_val
= e1e_rphy_locked(hw
, HV_OEM_BITS
, &oem_reg
);
1706 oem_reg
&= ~(HV_OEM_BITS_GBE_DIS
| HV_OEM_BITS_LPLU
);
1709 if (mac_reg
& E1000_PHY_CTRL_GBE_DISABLE
)
1710 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1712 if (mac_reg
& E1000_PHY_CTRL_D0A_LPLU
)
1713 oem_reg
|= HV_OEM_BITS_LPLU
;
1715 if (mac_reg
& (E1000_PHY_CTRL_GBE_DISABLE
|
1716 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
))
1717 oem_reg
|= HV_OEM_BITS_GBE_DIS
;
1719 if (mac_reg
& (E1000_PHY_CTRL_D0A_LPLU
|
1720 E1000_PHY_CTRL_NOND0A_LPLU
))
1721 oem_reg
|= HV_OEM_BITS_LPLU
;
1724 /* Set Restart auto-neg to activate the bits */
1725 if ((d0_state
|| (hw
->mac
.type
!= e1000_pchlan
)) &&
1726 !hw
->phy
.ops
.check_reset_block(hw
))
1727 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
1729 ret_val
= e1e_wphy_locked(hw
, HV_OEM_BITS
, oem_reg
);
1732 hw
->phy
.ops
.release(hw
);
1739 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1740 * @hw: pointer to the HW structure
1742 static s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
)
1747 ret_val
= e1e_rphy(hw
, HV_KMRN_MODE_CTRL
, &data
);
1751 data
|= HV_KMRN_MDIO_SLOW
;
1753 ret_val
= e1e_wphy(hw
, HV_KMRN_MODE_CTRL
, data
);
1759 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1760 * done after every PHY reset.
1762 static s32
e1000_hv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
1767 if (hw
->mac
.type
!= e1000_pchlan
)
1770 /* Set MDIO slow mode before any other MDIO access */
1771 if (hw
->phy
.type
== e1000_phy_82577
) {
1772 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
1777 if (((hw
->phy
.type
== e1000_phy_82577
) &&
1778 ((hw
->phy
.revision
== 1) || (hw
->phy
.revision
== 2))) ||
1779 ((hw
->phy
.type
== e1000_phy_82578
) && (hw
->phy
.revision
== 1))) {
1780 /* Disable generation of early preamble */
1781 ret_val
= e1e_wphy(hw
, PHY_REG(769, 25), 0x4431);
1785 /* Preamble tuning for SSC */
1786 ret_val
= e1e_wphy(hw
, HV_KMRN_FIFO_CTRLSTA
, 0xA204);
1791 if (hw
->phy
.type
== e1000_phy_82578
) {
1792 /* Return registers to default by doing a soft reset then
1793 * writing 0x3140 to the control register.
1795 if (hw
->phy
.revision
< 2) {
1796 e1000e_phy_sw_reset(hw
);
1797 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, 0x3140);
1802 ret_val
= hw
->phy
.ops
.acquire(hw
);
1807 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, 0);
1808 hw
->phy
.ops
.release(hw
);
1812 /* Configure the K1 Si workaround during phy reset assuming there is
1813 * link so that it disables K1 if link is in 1Gbps.
1815 ret_val
= e1000_k1_gig_workaround_hv(hw
, true);
1819 /* Workaround for link disconnects on a busy hub in half duplex */
1820 ret_val
= hw
->phy
.ops
.acquire(hw
);
1823 ret_val
= e1e_rphy_locked(hw
, BM_PORT_GEN_CFG
, &phy_data
);
1826 ret_val
= e1e_wphy_locked(hw
, BM_PORT_GEN_CFG
, phy_data
& 0x00FF);
1830 /* set MSE higher to enable link to stay up when noise is high */
1831 ret_val
= e1000_write_emi_reg_locked(hw
, I82577_MSE_THRESHOLD
, 0x0034);
1833 hw
->phy
.ops
.release(hw
);
1839 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1840 * @hw: pointer to the HW structure
1842 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw
*hw
)
1848 ret_val
= hw
->phy
.ops
.acquire(hw
);
1851 ret_val
= e1000_enable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
1855 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1856 for (i
= 0; i
< (hw
->mac
.rar_entry_count
+ 4); i
++) {
1857 mac_reg
= er32(RAL(i
));
1858 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_L(i
),
1859 (u16
)(mac_reg
& 0xFFFF));
1860 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_M(i
),
1861 (u16
)((mac_reg
>> 16) & 0xFFFF));
1863 mac_reg
= er32(RAH(i
));
1864 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_H(i
),
1865 (u16
)(mac_reg
& 0xFFFF));
1866 hw
->phy
.ops
.write_reg_page(hw
, BM_RAR_CTRL(i
),
1867 (u16
)((mac_reg
& E1000_RAH_AV
)
1871 e1000_disable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
1874 hw
->phy
.ops
.release(hw
);
1878 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1880 * @hw: pointer to the HW structure
1881 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1883 s32
e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw
*hw
, bool enable
)
1890 if (hw
->mac
.type
< e1000_pch2lan
)
1893 /* disable Rx path while enabling/disabling workaround */
1894 e1e_rphy(hw
, PHY_REG(769, 20), &phy_reg
);
1895 ret_val
= e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
| (1 << 14));
1900 /* Write Rx addresses (rar_entry_count for RAL/H, +4 for
1901 * SHRAL/H) and initial CRC values to the MAC
1903 for (i
= 0; i
< (hw
->mac
.rar_entry_count
+ 4); i
++) {
1904 u8 mac_addr
[ETH_ALEN
] = {0};
1905 u32 addr_high
, addr_low
;
1907 addr_high
= er32(RAH(i
));
1908 if (!(addr_high
& E1000_RAH_AV
))
1910 addr_low
= er32(RAL(i
));
1911 mac_addr
[0] = (addr_low
& 0xFF);
1912 mac_addr
[1] = ((addr_low
>> 8) & 0xFF);
1913 mac_addr
[2] = ((addr_low
>> 16) & 0xFF);
1914 mac_addr
[3] = ((addr_low
>> 24) & 0xFF);
1915 mac_addr
[4] = (addr_high
& 0xFF);
1916 mac_addr
[5] = ((addr_high
>> 8) & 0xFF);
1918 ew32(PCH_RAICC(i
), ~ether_crc_le(ETH_ALEN
, mac_addr
));
1921 /* Write Rx addresses to the PHY */
1922 e1000_copy_rx_addrs_to_phy_ich8lan(hw
);
1924 /* Enable jumbo frame workaround in the MAC */
1925 mac_reg
= er32(FFLT_DBG
);
1926 mac_reg
&= ~(1 << 14);
1927 mac_reg
|= (7 << 15);
1928 ew32(FFLT_DBG
, mac_reg
);
1930 mac_reg
= er32(RCTL
);
1931 mac_reg
|= E1000_RCTL_SECRC
;
1932 ew32(RCTL
, mac_reg
);
1934 ret_val
= e1000e_read_kmrn_reg(hw
,
1935 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1939 ret_val
= e1000e_write_kmrn_reg(hw
,
1940 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1944 ret_val
= e1000e_read_kmrn_reg(hw
,
1945 E1000_KMRNCTRLSTA_HD_CTRL
,
1949 data
&= ~(0xF << 8);
1951 ret_val
= e1000e_write_kmrn_reg(hw
,
1952 E1000_KMRNCTRLSTA_HD_CTRL
,
1957 /* Enable jumbo frame workaround in the PHY */
1958 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
1959 data
&= ~(0x7F << 5);
1960 data
|= (0x37 << 5);
1961 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
1964 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
1966 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
1969 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
1970 data
&= ~(0x3FF << 2);
1971 data
|= (0x1A << 2);
1972 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
1975 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0xF100);
1978 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
1979 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
| (1 << 10));
1983 /* Write MAC register values back to h/w defaults */
1984 mac_reg
= er32(FFLT_DBG
);
1985 mac_reg
&= ~(0xF << 14);
1986 ew32(FFLT_DBG
, mac_reg
);
1988 mac_reg
= er32(RCTL
);
1989 mac_reg
&= ~E1000_RCTL_SECRC
;
1990 ew32(RCTL
, mac_reg
);
1992 ret_val
= e1000e_read_kmrn_reg(hw
,
1993 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
1997 ret_val
= e1000e_write_kmrn_reg(hw
,
1998 E1000_KMRNCTRLSTA_CTRL_OFFSET
,
2002 ret_val
= e1000e_read_kmrn_reg(hw
,
2003 E1000_KMRNCTRLSTA_HD_CTRL
,
2007 data
&= ~(0xF << 8);
2009 ret_val
= e1000e_write_kmrn_reg(hw
,
2010 E1000_KMRNCTRLSTA_HD_CTRL
,
2015 /* Write PHY register values back to h/w defaults */
2016 e1e_rphy(hw
, PHY_REG(769, 23), &data
);
2017 data
&= ~(0x7F << 5);
2018 ret_val
= e1e_wphy(hw
, PHY_REG(769, 23), data
);
2021 e1e_rphy(hw
, PHY_REG(769, 16), &data
);
2023 ret_val
= e1e_wphy(hw
, PHY_REG(769, 16), data
);
2026 e1e_rphy(hw
, PHY_REG(776, 20), &data
);
2027 data
&= ~(0x3FF << 2);
2029 ret_val
= e1e_wphy(hw
, PHY_REG(776, 20), data
);
2032 ret_val
= e1e_wphy(hw
, PHY_REG(776, 23), 0x7E00);
2035 e1e_rphy(hw
, HV_PM_CTRL
, &data
);
2036 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, data
& ~(1 << 10));
2041 /* re-enable Rx path after enabling/disabling workaround */
2042 return e1e_wphy(hw
, PHY_REG(769, 20), phy_reg
& ~(1 << 14));
2046 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2047 * done after every PHY reset.
2049 static s32
e1000_lv_phy_workarounds_ich8lan(struct e1000_hw
*hw
)
2053 if (hw
->mac
.type
!= e1000_pch2lan
)
2056 /* Set MDIO slow mode before any other MDIO access */
2057 ret_val
= e1000_set_mdio_slow_mode_hv(hw
);
2061 ret_val
= hw
->phy
.ops
.acquire(hw
);
2064 /* set MSE higher to enable link to stay up when noise is high */
2065 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_MSE_THRESHOLD
, 0x0034);
2068 /* drop link after 5 times MSE threshold was reached */
2069 ret_val
= e1000_write_emi_reg_locked(hw
, I82579_MSE_LINK_DOWN
, 0x0005);
2071 hw
->phy
.ops
.release(hw
);
2077 * e1000_k1_gig_workaround_lv - K1 Si workaround
2078 * @hw: pointer to the HW structure
2080 * Workaround to set the K1 beacon duration for 82579 parts
2082 static s32
e1000_k1_workaround_lv(struct e1000_hw
*hw
)
2089 if (hw
->mac
.type
!= e1000_pch2lan
)
2092 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
2093 ret_val
= e1e_rphy(hw
, HV_M_STATUS
, &status_reg
);
2097 if ((status_reg
& (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
))
2098 == (HV_M_STATUS_LINK_UP
| HV_M_STATUS_AUTONEG_COMPLETE
)) {
2099 mac_reg
= er32(FEXTNVM4
);
2100 mac_reg
&= ~E1000_FEXTNVM4_BEACON_DURATION_MASK
;
2102 ret_val
= e1e_rphy(hw
, I82579_LPI_CTRL
, &phy_reg
);
2106 if (status_reg
& HV_M_STATUS_SPEED_1000
) {
2109 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_8USEC
;
2110 phy_reg
&= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT
;
2111 /* LV 1G Packet drop issue wa */
2112 ret_val
= e1e_rphy(hw
, HV_PM_CTRL
, &pm_phy_reg
);
2115 pm_phy_reg
&= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA
;
2116 ret_val
= e1e_wphy(hw
, HV_PM_CTRL
, pm_phy_reg
);
2120 mac_reg
|= E1000_FEXTNVM4_BEACON_DURATION_16USEC
;
2121 phy_reg
|= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT
;
2123 ew32(FEXTNVM4
, mac_reg
);
2124 ret_val
= e1e_wphy(hw
, I82579_LPI_CTRL
, phy_reg
);
2131 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2132 * @hw: pointer to the HW structure
2133 * @gate: boolean set to true to gate, false to ungate
2135 * Gate/ungate the automatic PHY configuration via hardware; perform
2136 * the configuration via software instead.
2138 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw
*hw
, bool gate
)
2142 if (hw
->mac
.type
< e1000_pch2lan
)
2145 extcnf_ctrl
= er32(EXTCNF_CTRL
);
2148 extcnf_ctrl
|= E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
2150 extcnf_ctrl
&= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG
;
2152 ew32(EXTCNF_CTRL
, extcnf_ctrl
);
2156 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2157 * @hw: pointer to the HW structure
2159 * Check the appropriate indication the MAC has finished configuring the
2160 * PHY after a software reset.
2162 static void e1000_lan_init_done_ich8lan(struct e1000_hw
*hw
)
2164 u32 data
, loop
= E1000_ICH8_LAN_INIT_TIMEOUT
;
2166 /* Wait for basic configuration completes before proceeding */
2168 data
= er32(STATUS
);
2169 data
&= E1000_STATUS_LAN_INIT_DONE
;
2171 } while ((!data
) && --loop
);
2173 /* If basic configuration is incomplete before the above loop
2174 * count reaches 0, loading the configuration from NVM will
2175 * leave the PHY in a bad state possibly resulting in no link.
2178 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2180 /* Clear the Init Done bit for the next init event */
2181 data
= er32(STATUS
);
2182 data
&= ~E1000_STATUS_LAN_INIT_DONE
;
2187 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2188 * @hw: pointer to the HW structure
2190 static s32
e1000_post_phy_reset_ich8lan(struct e1000_hw
*hw
)
2195 if (hw
->phy
.ops
.check_reset_block(hw
))
2198 /* Allow time for h/w to get to quiescent state after reset */
2199 usleep_range(10000, 20000);
2201 /* Perform any necessary post-reset workarounds */
2202 switch (hw
->mac
.type
) {
2204 ret_val
= e1000_hv_phy_workarounds_ich8lan(hw
);
2209 ret_val
= e1000_lv_phy_workarounds_ich8lan(hw
);
2217 /* Clear the host wakeup bit after lcd reset */
2218 if (hw
->mac
.type
>= e1000_pchlan
) {
2219 e1e_rphy(hw
, BM_PORT_GEN_CFG
, ®
);
2220 reg
&= ~BM_WUC_HOST_WU_BIT
;
2221 e1e_wphy(hw
, BM_PORT_GEN_CFG
, reg
);
2224 /* Configure the LCD with the extended configuration region in NVM */
2225 ret_val
= e1000_sw_lcd_config_ich8lan(hw
);
2229 /* Configure the LCD with the OEM bits in NVM */
2230 ret_val
= e1000_oem_bits_config_ich8lan(hw
, true);
2232 if (hw
->mac
.type
== e1000_pch2lan
) {
2233 /* Ungate automatic PHY configuration on non-managed 82579 */
2234 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
2235 usleep_range(10000, 20000);
2236 e1000_gate_hw_phy_config_ich8lan(hw
, false);
2239 /* Set EEE LPI Update Timer to 200usec */
2240 ret_val
= hw
->phy
.ops
.acquire(hw
);
2243 ret_val
= e1000_write_emi_reg_locked(hw
,
2244 I82579_LPI_UPDATE_TIMER
,
2246 hw
->phy
.ops
.release(hw
);
2253 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2254 * @hw: pointer to the HW structure
2257 * This is a function pointer entry point called by drivers
2258 * or other shared routines.
2260 static s32
e1000_phy_hw_reset_ich8lan(struct e1000_hw
*hw
)
2264 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2265 if ((hw
->mac
.type
== e1000_pch2lan
) &&
2266 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
2267 e1000_gate_hw_phy_config_ich8lan(hw
, true);
2269 ret_val
= e1000e_phy_hw_reset_generic(hw
);
2273 return e1000_post_phy_reset_ich8lan(hw
);
2277 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2278 * @hw: pointer to the HW structure
2279 * @active: true to enable LPLU, false to disable
2281 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2282 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2283 * the phy speed. This function will manually set the LPLU bit and restart
2284 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2285 * since it configures the same bit.
2287 static s32
e1000_set_lplu_state_pchlan(struct e1000_hw
*hw
, bool active
)
2292 ret_val
= e1e_rphy(hw
, HV_OEM_BITS
, &oem_reg
);
2297 oem_reg
|= HV_OEM_BITS_LPLU
;
2299 oem_reg
&= ~HV_OEM_BITS_LPLU
;
2301 if (!hw
->phy
.ops
.check_reset_block(hw
))
2302 oem_reg
|= HV_OEM_BITS_RESTART_AN
;
2304 return e1e_wphy(hw
, HV_OEM_BITS
, oem_reg
);
2308 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2309 * @hw: pointer to the HW structure
2310 * @active: true to enable LPLU, false to disable
2312 * Sets the LPLU D0 state according to the active flag. When
2313 * activating LPLU this function also disables smart speed
2314 * and vice versa. LPLU will not be activated unless the
2315 * device autonegotiation advertisement meets standards of
2316 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2317 * This is a function pointer entry point only called by
2318 * PHY setup routines.
2320 static s32
e1000_set_d0_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
2322 struct e1000_phy_info
*phy
= &hw
->phy
;
2327 if (phy
->type
== e1000_phy_ife
)
2330 phy_ctrl
= er32(PHY_CTRL
);
2333 phy_ctrl
|= E1000_PHY_CTRL_D0A_LPLU
;
2334 ew32(PHY_CTRL
, phy_ctrl
);
2336 if (phy
->type
!= e1000_phy_igp_3
)
2339 /* Call gig speed drop workaround on LPLU before accessing
2342 if (hw
->mac
.type
== e1000_ich8lan
)
2343 e1000e_gig_downshift_workaround_ich8lan(hw
);
2345 /* When LPLU is enabled, we should disable SmartSpeed */
2346 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
2347 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2348 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
2352 phy_ctrl
&= ~E1000_PHY_CTRL_D0A_LPLU
;
2353 ew32(PHY_CTRL
, phy_ctrl
);
2355 if (phy
->type
!= e1000_phy_igp_3
)
2358 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2359 * during Dx states where the power conservation is most
2360 * important. During driver activity we should enable
2361 * SmartSpeed, so performance is maintained.
2363 if (phy
->smart_speed
== e1000_smart_speed_on
) {
2364 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2369 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
2370 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2374 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
2375 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2380 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2381 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2392 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2393 * @hw: pointer to the HW structure
2394 * @active: true to enable LPLU, false to disable
2396 * Sets the LPLU D3 state according to the active flag. When
2397 * activating LPLU this function also disables smart speed
2398 * and vice versa. LPLU will not be activated unless the
2399 * device autonegotiation advertisement meets standards of
2400 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2401 * This is a function pointer entry point only called by
2402 * PHY setup routines.
2404 static s32
e1000_set_d3_lplu_state_ich8lan(struct e1000_hw
*hw
, bool active
)
2406 struct e1000_phy_info
*phy
= &hw
->phy
;
2411 phy_ctrl
= er32(PHY_CTRL
);
2414 phy_ctrl
&= ~E1000_PHY_CTRL_NOND0A_LPLU
;
2415 ew32(PHY_CTRL
, phy_ctrl
);
2417 if (phy
->type
!= e1000_phy_igp_3
)
2420 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2421 * during Dx states where the power conservation is most
2422 * important. During driver activity we should enable
2423 * SmartSpeed, so performance is maintained.
2425 if (phy
->smart_speed
== e1000_smart_speed_on
) {
2426 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2431 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
2432 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2436 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
2437 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2442 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2443 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
2448 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
2449 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
2450 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
2451 phy_ctrl
|= E1000_PHY_CTRL_NOND0A_LPLU
;
2452 ew32(PHY_CTRL
, phy_ctrl
);
2454 if (phy
->type
!= e1000_phy_igp_3
)
2457 /* Call gig speed drop workaround on LPLU before accessing
2460 if (hw
->mac
.type
== e1000_ich8lan
)
2461 e1000e_gig_downshift_workaround_ich8lan(hw
);
2463 /* When LPLU is enabled, we should disable SmartSpeed */
2464 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
2468 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
2469 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
2476 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2477 * @hw: pointer to the HW structure
2478 * @bank: pointer to the variable that returns the active bank
2480 * Reads signature byte from the NVM using the flash access registers.
2481 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2483 static s32
e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw
*hw
, u32
*bank
)
2486 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2487 u32 bank1_offset
= nvm
->flash_bank_size
* sizeof(u16
);
2488 u32 act_offset
= E1000_ICH_NVM_SIG_WORD
* 2 + 1;
2492 switch (hw
->mac
.type
) {
2496 if ((eecd
& E1000_EECD_SEC1VAL_VALID_MASK
) ==
2497 E1000_EECD_SEC1VAL_VALID_MASK
) {
2498 if (eecd
& E1000_EECD_SEC1VAL
)
2505 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2508 /* set bank to 0 in case flash read fails */
2512 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
,
2516 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
2517 E1000_ICH_NVM_SIG_VALUE
) {
2523 ret_val
= e1000_read_flash_byte_ich8lan(hw
, act_offset
+
2528 if ((sig_byte
& E1000_ICH_NVM_VALID_SIG_MASK
) ==
2529 E1000_ICH_NVM_SIG_VALUE
) {
2534 e_dbg("ERROR: No valid NVM bank present\n");
2535 return -E1000_ERR_NVM
;
2540 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2541 * @hw: pointer to the HW structure
2542 * @offset: The offset (in bytes) of the word(s) to read.
2543 * @words: Size of data to read in words
2544 * @data: Pointer to the word(s) to read at offset.
2546 * Reads a word(s) from the NVM using the flash access registers.
2548 static s32
e1000_read_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
2551 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2552 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2558 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
2560 e_dbg("nvm parameter(s) out of bounds\n");
2561 ret_val
= -E1000_ERR_NVM
;
2565 nvm
->ops
.acquire(hw
);
2567 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
2569 e_dbg("Could not detect valid bank, assuming bank 0\n");
2573 act_offset
= (bank
) ? nvm
->flash_bank_size
: 0;
2574 act_offset
+= offset
;
2577 for (i
= 0; i
< words
; i
++) {
2578 if (dev_spec
->shadow_ram
[offset
+i
].modified
) {
2579 data
[i
] = dev_spec
->shadow_ram
[offset
+i
].value
;
2581 ret_val
= e1000_read_flash_word_ich8lan(hw
,
2590 nvm
->ops
.release(hw
);
2594 e_dbg("NVM read error: %d\n", ret_val
);
2600 * e1000_flash_cycle_init_ich8lan - Initialize flash
2601 * @hw: pointer to the HW structure
2603 * This function does initial flash setup so that a new read/write/erase cycle
2606 static s32
e1000_flash_cycle_init_ich8lan(struct e1000_hw
*hw
)
2608 union ich8_hws_flash_status hsfsts
;
2609 s32 ret_val
= -E1000_ERR_NVM
;
2611 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2613 /* Check if the flash descriptor is valid */
2614 if (!hsfsts
.hsf_status
.fldesvalid
) {
2615 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
2616 return -E1000_ERR_NVM
;
2619 /* Clear FCERR and DAEL in hw status by writing 1 */
2620 hsfsts
.hsf_status
.flcerr
= 1;
2621 hsfsts
.hsf_status
.dael
= 1;
2623 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2625 /* Either we should have a hardware SPI cycle in progress
2626 * bit to check against, in order to start a new cycle or
2627 * FDONE bit should be changed in the hardware so that it
2628 * is 1 after hardware reset, which can then be used as an
2629 * indication whether a cycle is in progress or has been
2633 if (!hsfsts
.hsf_status
.flcinprog
) {
2634 /* There is no cycle running at present,
2635 * so we can start a cycle.
2636 * Begin by setting Flash Cycle Done.
2638 hsfsts
.hsf_status
.flcdone
= 1;
2639 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2644 /* Otherwise poll for sometime so the current
2645 * cycle has a chance to end before giving up.
2647 for (i
= 0; i
< ICH_FLASH_READ_COMMAND_TIMEOUT
; i
++) {
2648 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2649 if (!hsfsts
.hsf_status
.flcinprog
) {
2656 /* Successful in waiting for previous cycle to timeout,
2657 * now set the Flash Cycle Done.
2659 hsfsts
.hsf_status
.flcdone
= 1;
2660 ew16flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
2662 e_dbg("Flash controller busy, cannot get access\n");
2670 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2671 * @hw: pointer to the HW structure
2672 * @timeout: maximum time to wait for completion
2674 * This function starts a flash cycle and waits for its completion.
2676 static s32
e1000_flash_cycle_ich8lan(struct e1000_hw
*hw
, u32 timeout
)
2678 union ich8_hws_flash_ctrl hsflctl
;
2679 union ich8_hws_flash_status hsfsts
;
2682 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2683 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2684 hsflctl
.hsf_ctrl
.flcgo
= 1;
2685 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2687 /* wait till FDONE bit is set to 1 */
2689 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2690 if (hsfsts
.hsf_status
.flcdone
)
2693 } while (i
++ < timeout
);
2695 if (hsfsts
.hsf_status
.flcdone
&& !hsfsts
.hsf_status
.flcerr
)
2698 return -E1000_ERR_NVM
;
2702 * e1000_read_flash_word_ich8lan - Read word from flash
2703 * @hw: pointer to the HW structure
2704 * @offset: offset to data location
2705 * @data: pointer to the location for storing the data
2707 * Reads the flash word at offset into data. Offset is converted
2708 * to bytes before read.
2710 static s32
e1000_read_flash_word_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2713 /* Must convert offset into bytes. */
2716 return e1000_read_flash_data_ich8lan(hw
, offset
, 2, data
);
2720 * e1000_read_flash_byte_ich8lan - Read byte from flash
2721 * @hw: pointer to the HW structure
2722 * @offset: The offset of the byte to read.
2723 * @data: Pointer to a byte to store the value read.
2725 * Reads a single byte from the NVM using the flash access registers.
2727 static s32
e1000_read_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2733 ret_val
= e1000_read_flash_data_ich8lan(hw
, offset
, 1, &word
);
2743 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2744 * @hw: pointer to the HW structure
2745 * @offset: The offset (in bytes) of the byte or word to read.
2746 * @size: Size of data to read, 1=byte 2=word
2747 * @data: Pointer to the word to store the value read.
2749 * Reads a byte or word from the NVM using the flash access registers.
2751 static s32
e1000_read_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
2754 union ich8_hws_flash_status hsfsts
;
2755 union ich8_hws_flash_ctrl hsflctl
;
2756 u32 flash_linear_addr
;
2758 s32 ret_val
= -E1000_ERR_NVM
;
2761 if (size
< 1 || size
> 2 || offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
2762 return -E1000_ERR_NVM
;
2764 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
2765 hw
->nvm
.flash_base_addr
;
2770 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
2774 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
2775 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2776 hsflctl
.hsf_ctrl
.fldbcount
= size
- 1;
2777 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_READ
;
2778 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
2780 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
2782 ret_val
= e1000_flash_cycle_ich8lan(hw
,
2783 ICH_FLASH_READ_COMMAND_TIMEOUT
);
2785 /* Check if FCERR is set to 1, if set to 1, clear it
2786 * and try the whole sequence a few more times, else
2787 * read in (shift in) the Flash Data0, the order is
2788 * least significant byte first msb to lsb
2791 flash_data
= er32flash(ICH_FLASH_FDATA0
);
2793 *data
= (u8
)(flash_data
& 0x000000FF);
2795 *data
= (u16
)(flash_data
& 0x0000FFFF);
2798 /* If we've gotten here, then things are probably
2799 * completely hosed, but if the error condition is
2800 * detected, it won't hurt to give it another try...
2801 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2803 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
2804 if (hsfsts
.hsf_status
.flcerr
) {
2805 /* Repeat for some time before giving up. */
2807 } else if (!hsfsts
.hsf_status
.flcdone
) {
2808 e_dbg("Timeout error - flash cycle did not complete.\n");
2812 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
2818 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2819 * @hw: pointer to the HW structure
2820 * @offset: The offset (in bytes) of the word(s) to write.
2821 * @words: Size of data to write in words
2822 * @data: Pointer to the word(s) to write at offset.
2824 * Writes a byte or word to the NVM using the flash access registers.
2826 static s32
e1000_write_nvm_ich8lan(struct e1000_hw
*hw
, u16 offset
, u16 words
,
2829 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2830 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2833 if ((offset
>= nvm
->word_size
) || (words
> nvm
->word_size
- offset
) ||
2835 e_dbg("nvm parameter(s) out of bounds\n");
2836 return -E1000_ERR_NVM
;
2839 nvm
->ops
.acquire(hw
);
2841 for (i
= 0; i
< words
; i
++) {
2842 dev_spec
->shadow_ram
[offset
+i
].modified
= true;
2843 dev_spec
->shadow_ram
[offset
+i
].value
= data
[i
];
2846 nvm
->ops
.release(hw
);
2852 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2853 * @hw: pointer to the HW structure
2855 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2856 * which writes the checksum to the shadow ram. The changes in the shadow
2857 * ram are then committed to the EEPROM by processing each bank at a time
2858 * checking for the modified bit and writing only the pending changes.
2859 * After a successful commit, the shadow ram is cleared and is ready for
2862 static s32
e1000_update_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
2864 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
2865 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
2866 u32 i
, act_offset
, new_bank_offset
, old_bank_offset
, bank
;
2870 ret_val
= e1000e_update_nvm_checksum_generic(hw
);
2874 if (nvm
->type
!= e1000_nvm_flash_sw
)
2877 nvm
->ops
.acquire(hw
);
2879 /* We're writing to the opposite bank so if we're on bank 1,
2880 * write to bank 0 etc. We also need to erase the segment that
2881 * is going to be written
2883 ret_val
= e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
);
2885 e_dbg("Could not detect valid bank, assuming bank 0\n");
2890 new_bank_offset
= nvm
->flash_bank_size
;
2891 old_bank_offset
= 0;
2892 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 1);
2896 old_bank_offset
= nvm
->flash_bank_size
;
2897 new_bank_offset
= 0;
2898 ret_val
= e1000_erase_flash_bank_ich8lan(hw
, 0);
2903 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
2904 /* Determine whether to write the value stored
2905 * in the other NVM bank or a modified value stored
2908 if (dev_spec
->shadow_ram
[i
].modified
) {
2909 data
= dev_spec
->shadow_ram
[i
].value
;
2911 ret_val
= e1000_read_flash_word_ich8lan(hw
, i
+
2918 /* If the word is 0x13, then make sure the signature bits
2919 * (15:14) are 11b until the commit has completed.
2920 * This will allow us to write 10b which indicates the
2921 * signature is valid. We want to do this after the write
2922 * has completed so that we don't mark the segment valid
2923 * while the write is still in progress
2925 if (i
== E1000_ICH_NVM_SIG_WORD
)
2926 data
|= E1000_ICH_NVM_SIG_MASK
;
2928 /* Convert offset to bytes. */
2929 act_offset
= (i
+ new_bank_offset
) << 1;
2932 /* Write the bytes to the new bank. */
2933 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2940 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2947 /* Don't bother writing the segment valid bits if sector
2948 * programming failed.
2951 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2952 e_dbg("Flash commit failed.\n");
2956 /* Finally validate the new segment by setting bit 15:14
2957 * to 10b in word 0x13 , this can be done without an
2958 * erase as well since these bits are 11 to start with
2959 * and we need to change bit 14 to 0b
2961 act_offset
= new_bank_offset
+ E1000_ICH_NVM_SIG_WORD
;
2962 ret_val
= e1000_read_flash_word_ich8lan(hw
, act_offset
, &data
);
2967 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
,
2973 /* And invalidate the previously valid segment by setting
2974 * its signature word (0x13) high_byte to 0b. This can be
2975 * done without an erase because flash erase sets all bits
2976 * to 1's. We can write 1's to 0's without an erase
2978 act_offset
= (old_bank_offset
+ E1000_ICH_NVM_SIG_WORD
) * 2 + 1;
2979 ret_val
= e1000_retry_write_flash_byte_ich8lan(hw
, act_offset
, 0);
2983 /* Great! Everything worked, we can now clear the cached entries. */
2984 for (i
= 0; i
< E1000_ICH8_SHADOW_RAM_WORDS
; i
++) {
2985 dev_spec
->shadow_ram
[i
].modified
= false;
2986 dev_spec
->shadow_ram
[i
].value
= 0xFFFF;
2990 nvm
->ops
.release(hw
);
2992 /* Reload the EEPROM, or else modifications will not appear
2993 * until after the next adapter reset.
2996 nvm
->ops
.reload(hw
);
2997 usleep_range(10000, 20000);
3002 e_dbg("NVM update error: %d\n", ret_val
);
3008 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
3009 * @hw: pointer to the HW structure
3011 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
3012 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
3013 * calculated, in which case we need to calculate the checksum and set bit 6.
3015 static s32
e1000_validate_nvm_checksum_ich8lan(struct e1000_hw
*hw
)
3020 u16 valid_csum_mask
;
3022 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
3023 * the checksum needs to be fixed. This bit is an indication that
3024 * the NVM was prepared by OEM software and did not calculate
3025 * the checksum...a likely scenario.
3027 switch (hw
->mac
.type
) {
3030 valid_csum_mask
= NVM_COMPAT_VALID_CSUM
;
3033 word
= NVM_FUTURE_INIT_WORD1
;
3034 valid_csum_mask
= NVM_FUTURE_INIT_WORD1_VALID_CSUM
;
3038 ret_val
= e1000_read_nvm(hw
, word
, 1, &data
);
3042 if (!(data
& valid_csum_mask
)) {
3043 data
|= valid_csum_mask
;
3044 ret_val
= e1000_write_nvm(hw
, word
, 1, &data
);
3047 ret_val
= e1000e_update_nvm_checksum(hw
);
3052 return e1000e_validate_nvm_checksum_generic(hw
);
3056 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
3057 * @hw: pointer to the HW structure
3059 * To prevent malicious write/erase of the NVM, set it to be read-only
3060 * so that the hardware ignores all write/erase cycles of the NVM via
3061 * the flash control registers. The shadow-ram copy of the NVM will
3062 * still be updated, however any updates to this copy will not stick
3063 * across driver reloads.
3065 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw
*hw
)
3067 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3068 union ich8_flash_protected_range pr0
;
3069 union ich8_hws_flash_status hsfsts
;
3072 nvm
->ops
.acquire(hw
);
3074 gfpreg
= er32flash(ICH_FLASH_GFPREG
);
3076 /* Write-protect GbE Sector of NVM */
3077 pr0
.regval
= er32flash(ICH_FLASH_PR0
);
3078 pr0
.range
.base
= gfpreg
& FLASH_GFPREG_BASE_MASK
;
3079 pr0
.range
.limit
= ((gfpreg
>> 16) & FLASH_GFPREG_BASE_MASK
);
3080 pr0
.range
.wpe
= true;
3081 ew32flash(ICH_FLASH_PR0
, pr0
.regval
);
3083 /* Lock down a subset of GbE Flash Control Registers, e.g.
3084 * PR0 to prevent the write-protection from being lifted.
3085 * Once FLOCKDN is set, the registers protected by it cannot
3086 * be written until FLOCKDN is cleared by a hardware reset.
3088 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3089 hsfsts
.hsf_status
.flockdn
= true;
3090 ew32flash(ICH_FLASH_HSFSTS
, hsfsts
.regval
);
3092 nvm
->ops
.release(hw
);
3096 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
3097 * @hw: pointer to the HW structure
3098 * @offset: The offset (in bytes) of the byte/word to read.
3099 * @size: Size of data to read, 1=byte 2=word
3100 * @data: The byte(s) to write to the NVM.
3102 * Writes one/two bytes to the NVM using the flash access registers.
3104 static s32
e1000_write_flash_data_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3107 union ich8_hws_flash_status hsfsts
;
3108 union ich8_hws_flash_ctrl hsflctl
;
3109 u32 flash_linear_addr
;
3114 if (size
< 1 || size
> 2 || data
> size
* 0xff ||
3115 offset
> ICH_FLASH_LINEAR_ADDR_MASK
)
3116 return -E1000_ERR_NVM
;
3118 flash_linear_addr
= (ICH_FLASH_LINEAR_ADDR_MASK
& offset
) +
3119 hw
->nvm
.flash_base_addr
;
3124 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
3128 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
3129 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3130 hsflctl
.hsf_ctrl
.fldbcount
= size
-1;
3131 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_WRITE
;
3132 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
3134 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
3137 flash_data
= (u32
)data
& 0x00FF;
3139 flash_data
= (u32
)data
;
3141 ew32flash(ICH_FLASH_FDATA0
, flash_data
);
3143 /* check if FCERR is set to 1 , if set to 1, clear it
3144 * and try the whole sequence a few more times else done
3146 ret_val
= e1000_flash_cycle_ich8lan(hw
,
3147 ICH_FLASH_WRITE_COMMAND_TIMEOUT
);
3151 /* If we're here, then things are most likely
3152 * completely hosed, but if the error condition
3153 * is detected, it won't hurt to give it another
3154 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
3156 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3157 if (hsfsts
.hsf_status
.flcerr
)
3158 /* Repeat for some time before giving up. */
3160 if (!hsfsts
.hsf_status
.flcdone
) {
3161 e_dbg("Timeout error - flash cycle did not complete.\n");
3164 } while (count
++ < ICH_FLASH_CYCLE_REPEAT_COUNT
);
3170 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
3171 * @hw: pointer to the HW structure
3172 * @offset: The index of the byte to read.
3173 * @data: The byte to write to the NVM.
3175 * Writes a single byte to the NVM using the flash access registers.
3177 static s32
e1000_write_flash_byte_ich8lan(struct e1000_hw
*hw
, u32 offset
,
3180 u16 word
= (u16
)data
;
3182 return e1000_write_flash_data_ich8lan(hw
, offset
, 1, word
);
3186 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
3187 * @hw: pointer to the HW structure
3188 * @offset: The offset of the byte to write.
3189 * @byte: The byte to write to the NVM.
3191 * Writes a single byte to the NVM using the flash access registers.
3192 * Goes through a retry algorithm before giving up.
3194 static s32
e1000_retry_write_flash_byte_ich8lan(struct e1000_hw
*hw
,
3195 u32 offset
, u8 byte
)
3198 u16 program_retries
;
3200 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
3204 for (program_retries
= 0; program_retries
< 100; program_retries
++) {
3205 e_dbg("Retrying Byte %2.2X at offset %u\n", byte
, offset
);
3207 ret_val
= e1000_write_flash_byte_ich8lan(hw
, offset
, byte
);
3211 if (program_retries
== 100)
3212 return -E1000_ERR_NVM
;
3218 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
3219 * @hw: pointer to the HW structure
3220 * @bank: 0 for first bank, 1 for second bank, etc.
3222 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
3223 * bank N is 4096 * N + flash_reg_addr.
3225 static s32
e1000_erase_flash_bank_ich8lan(struct e1000_hw
*hw
, u32 bank
)
3227 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
3228 union ich8_hws_flash_status hsfsts
;
3229 union ich8_hws_flash_ctrl hsflctl
;
3230 u32 flash_linear_addr
;
3231 /* bank size is in 16bit words - adjust to bytes */
3232 u32 flash_bank_size
= nvm
->flash_bank_size
* 2;
3235 s32 j
, iteration
, sector_size
;
3237 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3239 /* Determine HW Sector size: Read BERASE bits of hw flash status
3241 * 00: The Hw sector is 256 bytes, hence we need to erase 16
3242 * consecutive sectors. The start index for the nth Hw sector
3243 * can be calculated as = bank * 4096 + n * 256
3244 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
3245 * The start index for the nth Hw sector can be calculated
3247 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
3248 * (ich9 only, otherwise error condition)
3249 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
3251 switch (hsfsts
.hsf_status
.berasesz
) {
3253 /* Hw sector size 256 */
3254 sector_size
= ICH_FLASH_SEG_SIZE_256
;
3255 iteration
= flash_bank_size
/ ICH_FLASH_SEG_SIZE_256
;
3258 sector_size
= ICH_FLASH_SEG_SIZE_4K
;
3262 sector_size
= ICH_FLASH_SEG_SIZE_8K
;
3266 sector_size
= ICH_FLASH_SEG_SIZE_64K
;
3270 return -E1000_ERR_NVM
;
3273 /* Start with the base address, then add the sector offset. */
3274 flash_linear_addr
= hw
->nvm
.flash_base_addr
;
3275 flash_linear_addr
+= (bank
) ? flash_bank_size
: 0;
3277 for (j
= 0; j
< iteration
; j
++) {
3280 ret_val
= e1000_flash_cycle_init_ich8lan(hw
);
3284 /* Write a value 11 (block Erase) in Flash
3285 * Cycle field in hw flash control
3287 hsflctl
.regval
= er16flash(ICH_FLASH_HSFCTL
);
3288 hsflctl
.hsf_ctrl
.flcycle
= ICH_CYCLE_ERASE
;
3289 ew16flash(ICH_FLASH_HSFCTL
, hsflctl
.regval
);
3291 /* Write the last 24 bits of an index within the
3292 * block into Flash Linear address field in Flash
3295 flash_linear_addr
+= (j
* sector_size
);
3296 ew32flash(ICH_FLASH_FADDR
, flash_linear_addr
);
3298 ret_val
= e1000_flash_cycle_ich8lan(hw
,
3299 ICH_FLASH_ERASE_COMMAND_TIMEOUT
);
3303 /* Check if FCERR is set to 1. If 1,
3304 * clear it and try the whole sequence
3305 * a few more times else Done
3307 hsfsts
.regval
= er16flash(ICH_FLASH_HSFSTS
);
3308 if (hsfsts
.hsf_status
.flcerr
)
3309 /* repeat for some time before giving up */
3311 else if (!hsfsts
.hsf_status
.flcdone
)
3313 } while (++count
< ICH_FLASH_CYCLE_REPEAT_COUNT
);
3320 * e1000_valid_led_default_ich8lan - Set the default LED settings
3321 * @hw: pointer to the HW structure
3322 * @data: Pointer to the LED settings
3324 * Reads the LED default settings from the NVM to data. If the NVM LED
3325 * settings is all 0's or F's, set the LED default to a valid LED default
3328 static s32
e1000_valid_led_default_ich8lan(struct e1000_hw
*hw
, u16
*data
)
3332 ret_val
= e1000_read_nvm(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
3334 e_dbg("NVM Read Error\n");
3338 if (*data
== ID_LED_RESERVED_0000
||
3339 *data
== ID_LED_RESERVED_FFFF
)
3340 *data
= ID_LED_DEFAULT_ICH8LAN
;
3346 * e1000_id_led_init_pchlan - store LED configurations
3347 * @hw: pointer to the HW structure
3349 * PCH does not control LEDs via the LEDCTL register, rather it uses
3350 * the PHY LED configuration register.
3352 * PCH also does not have an "always on" or "always off" mode which
3353 * complicates the ID feature. Instead of using the "on" mode to indicate
3354 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
3355 * use "link_up" mode. The LEDs will still ID on request if there is no
3356 * link based on logic in e1000_led_[on|off]_pchlan().
3358 static s32
e1000_id_led_init_pchlan(struct e1000_hw
*hw
)
3360 struct e1000_mac_info
*mac
= &hw
->mac
;
3362 const u32 ledctl_on
= E1000_LEDCTL_MODE_LINK_UP
;
3363 const u32 ledctl_off
= E1000_LEDCTL_MODE_LINK_UP
| E1000_PHY_LED0_IVRT
;
3364 u16 data
, i
, temp
, shift
;
3366 /* Get default ID LED modes */
3367 ret_val
= hw
->nvm
.ops
.valid_led_default(hw
, &data
);
3371 mac
->ledctl_default
= er32(LEDCTL
);
3372 mac
->ledctl_mode1
= mac
->ledctl_default
;
3373 mac
->ledctl_mode2
= mac
->ledctl_default
;
3375 for (i
= 0; i
< 4; i
++) {
3376 temp
= (data
>> (i
<< 2)) & E1000_LEDCTL_LED0_MODE_MASK
;
3379 case ID_LED_ON1_DEF2
:
3380 case ID_LED_ON1_ON2
:
3381 case ID_LED_ON1_OFF2
:
3382 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3383 mac
->ledctl_mode1
|= (ledctl_on
<< shift
);
3385 case ID_LED_OFF1_DEF2
:
3386 case ID_LED_OFF1_ON2
:
3387 case ID_LED_OFF1_OFF2
:
3388 mac
->ledctl_mode1
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3389 mac
->ledctl_mode1
|= (ledctl_off
<< shift
);
3396 case ID_LED_DEF1_ON2
:
3397 case ID_LED_ON1_ON2
:
3398 case ID_LED_OFF1_ON2
:
3399 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3400 mac
->ledctl_mode2
|= (ledctl_on
<< shift
);
3402 case ID_LED_DEF1_OFF2
:
3403 case ID_LED_ON1_OFF2
:
3404 case ID_LED_OFF1_OFF2
:
3405 mac
->ledctl_mode2
&= ~(E1000_PHY_LED0_MASK
<< shift
);
3406 mac
->ledctl_mode2
|= (ledctl_off
<< shift
);
3418 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3419 * @hw: pointer to the HW structure
3421 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3422 * register, so the the bus width is hard coded.
3424 static s32
e1000_get_bus_info_ich8lan(struct e1000_hw
*hw
)
3426 struct e1000_bus_info
*bus
= &hw
->bus
;
3429 ret_val
= e1000e_get_bus_info_pcie(hw
);
3431 /* ICH devices are "PCI Express"-ish. They have
3432 * a configuration space, but do not contain
3433 * PCI Express Capability registers, so bus width
3434 * must be hardcoded.
3436 if (bus
->width
== e1000_bus_width_unknown
)
3437 bus
->width
= e1000_bus_width_pcie_x1
;
3443 * e1000_reset_hw_ich8lan - Reset the hardware
3444 * @hw: pointer to the HW structure
3446 * Does a full reset of the hardware which includes a reset of the PHY and
3449 static s32
e1000_reset_hw_ich8lan(struct e1000_hw
*hw
)
3451 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3456 /* Prevent the PCI-E bus from sticking if there is no TLP connection
3457 * on the last TLP read/write transaction when MAC is reset.
3459 ret_val
= e1000e_disable_pcie_master(hw
);
3461 e_dbg("PCI-E Master disable polling has failed.\n");
3463 e_dbg("Masking off all interrupts\n");
3464 ew32(IMC
, 0xffffffff);
3466 /* Disable the Transmit and Receive units. Then delay to allow
3467 * any pending transactions to complete before we hit the MAC
3468 * with the global reset.
3471 ew32(TCTL
, E1000_TCTL_PSP
);
3474 usleep_range(10000, 20000);
3476 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3477 if (hw
->mac
.type
== e1000_ich8lan
) {
3478 /* Set Tx and Rx buffer allocation to 8k apiece. */
3479 ew32(PBA
, E1000_PBA_8K
);
3480 /* Set Packet Buffer Size to 16k. */
3481 ew32(PBS
, E1000_PBS_16K
);
3484 if (hw
->mac
.type
== e1000_pchlan
) {
3485 /* Save the NVM K1 bit setting */
3486 ret_val
= e1000_read_nvm(hw
, E1000_NVM_K1_CONFIG
, 1, &kum_cfg
);
3490 if (kum_cfg
& E1000_NVM_K1_ENABLE
)
3491 dev_spec
->nvm_k1_enabled
= true;
3493 dev_spec
->nvm_k1_enabled
= false;
3498 if (!hw
->phy
.ops
.check_reset_block(hw
)) {
3499 /* Full-chip reset requires MAC and PHY reset at the same
3500 * time to make sure the interface between MAC and the
3501 * external PHY is reset.
3503 ctrl
|= E1000_CTRL_PHY_RST
;
3505 /* Gate automatic PHY configuration by hardware on
3508 if ((hw
->mac
.type
== e1000_pch2lan
) &&
3509 !(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
))
3510 e1000_gate_hw_phy_config_ich8lan(hw
, true);
3512 ret_val
= e1000_acquire_swflag_ich8lan(hw
);
3513 e_dbg("Issuing a global reset to ich8lan\n");
3514 ew32(CTRL
, (ctrl
| E1000_CTRL_RST
));
3515 /* cannot issue a flush here because it hangs the hardware */
3518 /* Set Phy Config Counter to 50msec */
3519 if (hw
->mac
.type
== e1000_pch2lan
) {
3520 reg
= er32(FEXTNVM3
);
3521 reg
&= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK
;
3522 reg
|= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC
;
3523 ew32(FEXTNVM3
, reg
);
3527 clear_bit(__E1000_ACCESS_SHARED_RESOURCE
, &hw
->adapter
->state
);
3529 if (ctrl
& E1000_CTRL_PHY_RST
) {
3530 ret_val
= hw
->phy
.ops
.get_cfg_done(hw
);
3534 ret_val
= e1000_post_phy_reset_ich8lan(hw
);
3539 /* For PCH, this write will make sure that any noise
3540 * will be detected as a CRC error and be dropped rather than show up
3541 * as a bad packet to the DMA engine.
3543 if (hw
->mac
.type
== e1000_pchlan
)
3544 ew32(CRC_OFFSET
, 0x65656565);
3546 ew32(IMC
, 0xffffffff);
3549 reg
= er32(KABGTXD
);
3550 reg
|= E1000_KABGTXD_BGSQLBIAS
;
3557 * e1000_init_hw_ich8lan - Initialize the hardware
3558 * @hw: pointer to the HW structure
3560 * Prepares the hardware for transmit and receive by doing the following:
3561 * - initialize hardware bits
3562 * - initialize LED identification
3563 * - setup receive address registers
3564 * - setup flow control
3565 * - setup transmit descriptors
3566 * - clear statistics
3568 static s32
e1000_init_hw_ich8lan(struct e1000_hw
*hw
)
3570 struct e1000_mac_info
*mac
= &hw
->mac
;
3571 u32 ctrl_ext
, txdctl
, snoop
;
3575 e1000_initialize_hw_bits_ich8lan(hw
);
3577 /* Initialize identification LED */
3578 ret_val
= mac
->ops
.id_led_init(hw
);
3580 e_dbg("Error initializing identification LED\n");
3581 /* This is not fatal and we should not stop init due to this */
3583 /* Setup the receive address. */
3584 e1000e_init_rx_addrs(hw
, mac
->rar_entry_count
);
3586 /* Zero out the Multicast HASH table */
3587 e_dbg("Zeroing the MTA\n");
3588 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
3589 E1000_WRITE_REG_ARRAY(hw
, E1000_MTA
, i
, 0);
3591 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
3592 * the ME. Disable wakeup by clearing the host wakeup bit.
3593 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3595 if (hw
->phy
.type
== e1000_phy_82578
) {
3596 e1e_rphy(hw
, BM_PORT_GEN_CFG
, &i
);
3597 i
&= ~BM_WUC_HOST_WU_BIT
;
3598 e1e_wphy(hw
, BM_PORT_GEN_CFG
, i
);
3599 ret_val
= e1000_phy_hw_reset_ich8lan(hw
);
3604 /* Setup link and flow control */
3605 ret_val
= mac
->ops
.setup_link(hw
);
3607 /* Set the transmit descriptor write-back policy for both queues */
3608 txdctl
= er32(TXDCTL(0));
3609 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
3610 E1000_TXDCTL_FULL_TX_DESC_WB
;
3611 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
3612 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
3613 ew32(TXDCTL(0), txdctl
);
3614 txdctl
= er32(TXDCTL(1));
3615 txdctl
= (txdctl
& ~E1000_TXDCTL_WTHRESH
) |
3616 E1000_TXDCTL_FULL_TX_DESC_WB
;
3617 txdctl
= (txdctl
& ~E1000_TXDCTL_PTHRESH
) |
3618 E1000_TXDCTL_MAX_TX_DESC_PREFETCH
;
3619 ew32(TXDCTL(1), txdctl
);
3621 /* ICH8 has opposite polarity of no_snoop bits.
3622 * By default, we should use snoop behavior.
3624 if (mac
->type
== e1000_ich8lan
)
3625 snoop
= PCIE_ICH8_SNOOP_ALL
;
3627 snoop
= (u32
) ~(PCIE_NO_SNOOP_ALL
);
3628 e1000e_set_pcie_no_snoop(hw
, snoop
);
3630 ctrl_ext
= er32(CTRL_EXT
);
3631 ctrl_ext
|= E1000_CTRL_EXT_RO_DIS
;
3632 ew32(CTRL_EXT
, ctrl_ext
);
3634 /* Clear all of the statistics registers (clear on read). It is
3635 * important that we do this after we have tried to establish link
3636 * because the symbol error count will increment wildly if there
3639 e1000_clear_hw_cntrs_ich8lan(hw
);
3644 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3645 * @hw: pointer to the HW structure
3647 * Sets/Clears required hardware bits necessary for correctly setting up the
3648 * hardware for transmit and receive.
3650 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw
*hw
)
3654 /* Extended Device Control */
3655 reg
= er32(CTRL_EXT
);
3657 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3658 if (hw
->mac
.type
>= e1000_pchlan
)
3659 reg
|= E1000_CTRL_EXT_PHYPDEN
;
3660 ew32(CTRL_EXT
, reg
);
3662 /* Transmit Descriptor Control 0 */
3663 reg
= er32(TXDCTL(0));
3665 ew32(TXDCTL(0), reg
);
3667 /* Transmit Descriptor Control 1 */
3668 reg
= er32(TXDCTL(1));
3670 ew32(TXDCTL(1), reg
);
3672 /* Transmit Arbitration Control 0 */
3673 reg
= er32(TARC(0));
3674 if (hw
->mac
.type
== e1000_ich8lan
)
3675 reg
|= (1 << 28) | (1 << 29);
3676 reg
|= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3679 /* Transmit Arbitration Control 1 */
3680 reg
= er32(TARC(1));
3681 if (er32(TCTL
) & E1000_TCTL_MULR
)
3685 reg
|= (1 << 24) | (1 << 26) | (1 << 30);
3689 if (hw
->mac
.type
== e1000_ich8lan
) {
3695 /* work-around descriptor data corruption issue during nfs v2 udp
3696 * traffic, just disable the nfs filtering capability
3699 reg
|= (E1000_RFCTL_NFSW_DIS
| E1000_RFCTL_NFSR_DIS
);
3701 /* Disable IPv6 extension header parsing because some malformed
3702 * IPv6 headers can hang the Rx.
3704 if (hw
->mac
.type
== e1000_ich8lan
)
3705 reg
|= (E1000_RFCTL_IPV6_EX_DIS
| E1000_RFCTL_NEW_IPV6_EXT_DIS
);
3710 * e1000_setup_link_ich8lan - Setup flow control and link settings
3711 * @hw: pointer to the HW structure
3713 * Determines which flow control settings to use, then configures flow
3714 * control. Calls the appropriate media-specific link configuration
3715 * function. Assuming the adapter has a valid link partner, a valid link
3716 * should be established. Assumes the hardware has previously been reset
3717 * and the transmitter and receiver are not enabled.
3719 static s32
e1000_setup_link_ich8lan(struct e1000_hw
*hw
)
3723 if (hw
->phy
.ops
.check_reset_block(hw
))
3726 /* ICH parts do not have a word in the NVM to determine
3727 * the default flow control setting, so we explicitly
3730 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
3731 /* Workaround h/w hang when Tx flow control enabled */
3732 if (hw
->mac
.type
== e1000_pchlan
)
3733 hw
->fc
.requested_mode
= e1000_fc_rx_pause
;
3735 hw
->fc
.requested_mode
= e1000_fc_full
;
3738 /* Save off the requested flow control mode for use later. Depending
3739 * on the link partner's capabilities, we may or may not use this mode.
3741 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
3743 e_dbg("After fix-ups FlowControl is now = %x\n",
3744 hw
->fc
.current_mode
);
3746 /* Continue to configure the copper link. */
3747 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
3751 ew32(FCTTV
, hw
->fc
.pause_time
);
3752 if ((hw
->phy
.type
== e1000_phy_82578
) ||
3753 (hw
->phy
.type
== e1000_phy_82579
) ||
3754 (hw
->phy
.type
== e1000_phy_i217
) ||
3755 (hw
->phy
.type
== e1000_phy_82577
)) {
3756 ew32(FCRTV_PCH
, hw
->fc
.refresh_time
);
3758 ret_val
= e1e_wphy(hw
, PHY_REG(BM_PORT_CTRL_PAGE
, 27),
3764 return e1000e_set_fc_watermarks(hw
);
3768 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3769 * @hw: pointer to the HW structure
3771 * Configures the kumeran interface to the PHY to wait the appropriate time
3772 * when polling the PHY, then call the generic setup_copper_link to finish
3773 * configuring the copper link.
3775 static s32
e1000_setup_copper_link_ich8lan(struct e1000_hw
*hw
)
3782 ctrl
|= E1000_CTRL_SLU
;
3783 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
3786 /* Set the mac to wait the maximum time between each iteration
3787 * and increase the max iterations when polling the phy;
3788 * this fixes erroneous timeouts at 10Mbps.
3790 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_TIMEOUTS
, 0xFFFF);
3793 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
3798 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_INBAND_PARAM
,
3803 switch (hw
->phy
.type
) {
3804 case e1000_phy_igp_3
:
3805 ret_val
= e1000e_copper_link_setup_igp(hw
);
3810 case e1000_phy_82578
:
3811 ret_val
= e1000e_copper_link_setup_m88(hw
);
3815 case e1000_phy_82577
:
3816 case e1000_phy_82579
:
3817 case e1000_phy_i217
:
3818 ret_val
= e1000_copper_link_setup_82577(hw
);
3823 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, ®_data
);
3827 reg_data
&= ~IFE_PMC_AUTO_MDIX
;
3829 switch (hw
->phy
.mdix
) {
3831 reg_data
&= ~IFE_PMC_FORCE_MDIX
;
3834 reg_data
|= IFE_PMC_FORCE_MDIX
;
3838 reg_data
|= IFE_PMC_AUTO_MDIX
;
3841 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, reg_data
);
3849 return e1000e_setup_copper_link(hw
);
3853 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3854 * @hw: pointer to the HW structure
3855 * @speed: pointer to store current link speed
3856 * @duplex: pointer to store the current link duplex
3858 * Calls the generic get_speed_and_duplex to retrieve the current link
3859 * information and then calls the Kumeran lock loss workaround for links at
3862 static s32
e1000_get_link_up_info_ich8lan(struct e1000_hw
*hw
, u16
*speed
,
3867 ret_val
= e1000e_get_speed_and_duplex_copper(hw
, speed
, duplex
);
3871 if ((hw
->mac
.type
== e1000_ich8lan
) &&
3872 (hw
->phy
.type
== e1000_phy_igp_3
) &&
3873 (*speed
== SPEED_1000
)) {
3874 ret_val
= e1000_kmrn_lock_loss_workaround_ich8lan(hw
);
3881 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3882 * @hw: pointer to the HW structure
3884 * Work-around for 82566 Kumeran PCS lock loss:
3885 * On link status change (i.e. PCI reset, speed change) and link is up and
3887 * 0) if workaround is optionally disabled do nothing
3888 * 1) wait 1ms for Kumeran link to come up
3889 * 2) check Kumeran Diagnostic register PCS lock loss bit
3890 * 3) if not set the link is locked (all is good), otherwise...
3892 * 5) repeat up to 10 times
3893 * Note: this is only called for IGP3 copper when speed is 1gb.
3895 static s32
e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
)
3897 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3903 if (!dev_spec
->kmrn_lock_loss_workaround_enabled
)
3906 /* Make sure link is up before proceeding. If not just return.
3907 * Attempting this while link is negotiating fouled up link
3910 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
3914 for (i
= 0; i
< 10; i
++) {
3915 /* read once to clear */
3916 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
3919 /* and again to get new status */
3920 ret_val
= e1e_rphy(hw
, IGP3_KMRN_DIAG
, &data
);
3924 /* check for PCS lock */
3925 if (!(data
& IGP3_KMRN_DIAG_PCS_LOCK_LOSS
))
3928 /* Issue PHY reset */
3929 e1000_phy_hw_reset(hw
);
3932 /* Disable GigE link negotiation */
3933 phy_ctrl
= er32(PHY_CTRL
);
3934 phy_ctrl
|= (E1000_PHY_CTRL_GBE_DISABLE
|
3935 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
3936 ew32(PHY_CTRL
, phy_ctrl
);
3938 /* Call gig speed drop workaround on Gig disable before accessing
3941 e1000e_gig_downshift_workaround_ich8lan(hw
);
3943 /* unable to acquire PCS lock */
3944 return -E1000_ERR_PHY
;
3948 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3949 * @hw: pointer to the HW structure
3950 * @state: boolean value used to set the current Kumeran workaround state
3952 * If ICH8, set the current Kumeran workaround state (enabled - true
3953 * /disabled - false).
3955 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw
*hw
,
3958 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
3960 if (hw
->mac
.type
!= e1000_ich8lan
) {
3961 e_dbg("Workaround applies to ICH8 only.\n");
3965 dev_spec
->kmrn_lock_loss_workaround_enabled
= state
;
3969 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3970 * @hw: pointer to the HW structure
3972 * Workaround for 82566 power-down on D3 entry:
3973 * 1) disable gigabit link
3974 * 2) write VR power-down enable
3976 * Continue if successful, else issue LCD reset and repeat
3978 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw
*hw
)
3984 if (hw
->phy
.type
!= e1000_phy_igp_3
)
3987 /* Try the workaround twice (if needed) */
3990 reg
= er32(PHY_CTRL
);
3991 reg
|= (E1000_PHY_CTRL_GBE_DISABLE
|
3992 E1000_PHY_CTRL_NOND0A_GBE_DISABLE
);
3993 ew32(PHY_CTRL
, reg
);
3995 /* Call gig speed drop workaround on Gig disable before
3996 * accessing any PHY registers
3998 if (hw
->mac
.type
== e1000_ich8lan
)
3999 e1000e_gig_downshift_workaround_ich8lan(hw
);
4001 /* Write VR power-down enable */
4002 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
4003 data
&= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
4004 e1e_wphy(hw
, IGP3_VR_CTRL
, data
| IGP3_VR_CTRL_MODE_SHUTDOWN
);
4006 /* Read it back and test */
4007 e1e_rphy(hw
, IGP3_VR_CTRL
, &data
);
4008 data
&= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK
;
4009 if ((data
== IGP3_VR_CTRL_MODE_SHUTDOWN
) || retry
)
4012 /* Issue PHY reset and repeat at most one more time */
4014 ew32(CTRL
, reg
| E1000_CTRL_PHY_RST
);
4020 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
4021 * @hw: pointer to the HW structure
4023 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
4024 * LPLU, Gig disable, MDIC PHY reset):
4025 * 1) Set Kumeran Near-end loopback
4026 * 2) Clear Kumeran Near-end loopback
4027 * Should only be called for ICH8[m] devices with any 1G Phy.
4029 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw
*hw
)
4034 if ((hw
->mac
.type
!= e1000_ich8lan
) || (hw
->phy
.type
== e1000_phy_ife
))
4037 ret_val
= e1000e_read_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
4041 reg_data
|= E1000_KMRNCTRLSTA_DIAG_NELPBK
;
4042 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
4046 reg_data
&= ~E1000_KMRNCTRLSTA_DIAG_NELPBK
;
4047 ret_val
= e1000e_write_kmrn_reg(hw
, E1000_KMRNCTRLSTA_DIAG_OFFSET
,
4052 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
4053 * @hw: pointer to the HW structure
4055 * During S0 to Sx transition, it is possible the link remains at gig
4056 * instead of negotiating to a lower speed. Before going to Sx, set
4057 * 'Gig Disable' to force link speed negotiation to a lower speed based on
4058 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
4059 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
4060 * needs to be written.
4061 * Parts that support (and are linked to a partner which support) EEE in
4062 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
4063 * than 10Mbps w/o EEE.
4065 void e1000_suspend_workarounds_ich8lan(struct e1000_hw
*hw
)
4067 struct e1000_dev_spec_ich8lan
*dev_spec
= &hw
->dev_spec
.ich8lan
;
4071 phy_ctrl
= er32(PHY_CTRL
);
4072 phy_ctrl
|= E1000_PHY_CTRL_GBE_DISABLE
;
4073 if (hw
->phy
.type
== e1000_phy_i217
) {
4076 ret_val
= hw
->phy
.ops
.acquire(hw
);
4080 if (!dev_spec
->eee_disable
) {
4084 e1000_read_emi_reg_locked(hw
,
4085 I217_EEE_ADVERTISEMENT
,
4090 /* Disable LPLU if both link partners support 100BaseT
4091 * EEE and 100Full is advertised on both ends of the
4094 if ((eee_advert
& I82579_EEE_100_SUPPORTED
) &&
4095 (dev_spec
->eee_lp_ability
&
4096 I82579_EEE_100_SUPPORTED
) &&
4097 (hw
->phy
.autoneg_advertised
& ADVERTISE_100_FULL
))
4098 phy_ctrl
&= ~(E1000_PHY_CTRL_D0A_LPLU
|
4099 E1000_PHY_CTRL_NOND0A_LPLU
);
4102 /* For i217 Intel Rapid Start Technology support,
4103 * when the system is going into Sx and no manageability engine
4104 * is present, the driver must configure proxy to reset only on
4105 * power good. LPI (Low Power Idle) state must also reset only
4106 * on power good, as well as the MTA (Multicast table array).
4107 * The SMBus release must also be disabled on LCD reset.
4109 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
4111 /* Enable proxy to reset only on power good. */
4112 e1e_rphy_locked(hw
, I217_PROXY_CTRL
, &phy_reg
);
4113 phy_reg
|= I217_PROXY_CTRL_AUTO_DISABLE
;
4114 e1e_wphy_locked(hw
, I217_PROXY_CTRL
, phy_reg
);
4116 /* Set bit enable LPI (EEE) to reset only on
4119 e1e_rphy_locked(hw
, I217_SxCTRL
, &phy_reg
);
4120 phy_reg
|= I217_SxCTRL_ENABLE_LPI_RESET
;
4121 e1e_wphy_locked(hw
, I217_SxCTRL
, phy_reg
);
4123 /* Disable the SMB release on LCD reset. */
4124 e1e_rphy_locked(hw
, I217_MEMPWR
, &phy_reg
);
4125 phy_reg
&= ~I217_MEMPWR_DISABLE_SMB_RELEASE
;
4126 e1e_wphy_locked(hw
, I217_MEMPWR
, phy_reg
);
4129 /* Enable MTA to reset for Intel Rapid Start Technology
4132 e1e_rphy_locked(hw
, I217_CGFREG
, &phy_reg
);
4133 phy_reg
|= I217_CGFREG_ENABLE_MTA_RESET
;
4134 e1e_wphy_locked(hw
, I217_CGFREG
, phy_reg
);
4137 hw
->phy
.ops
.release(hw
);
4140 ew32(PHY_CTRL
, phy_ctrl
);
4142 if (hw
->mac
.type
== e1000_ich8lan
)
4143 e1000e_gig_downshift_workaround_ich8lan(hw
);
4145 if (hw
->mac
.type
>= e1000_pchlan
) {
4146 e1000_oem_bits_config_ich8lan(hw
, false);
4148 /* Reset PHY to activate OEM bits on 82577/8 */
4149 if (hw
->mac
.type
== e1000_pchlan
)
4150 e1000e_phy_hw_reset_generic(hw
);
4152 ret_val
= hw
->phy
.ops
.acquire(hw
);
4155 e1000_write_smbus_addr(hw
);
4156 hw
->phy
.ops
.release(hw
);
4161 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
4162 * @hw: pointer to the HW structure
4164 * During Sx to S0 transitions on non-managed devices or managed devices
4165 * on which PHY resets are not blocked, if the PHY registers cannot be
4166 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
4168 * On i217, setup Intel Rapid Start Technology.
4170 void e1000_resume_workarounds_pchlan(struct e1000_hw
*hw
)
4174 if (hw
->mac
.type
< e1000_pch2lan
)
4177 ret_val
= e1000_init_phy_workarounds_pchlan(hw
);
4179 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val
);
4183 /* For i217 Intel Rapid Start Technology support when the system
4184 * is transitioning from Sx and no manageability engine is present
4185 * configure SMBus to restore on reset, disable proxy, and enable
4186 * the reset on MTA (Multicast table array).
4188 if (hw
->phy
.type
== e1000_phy_i217
) {
4191 ret_val
= hw
->phy
.ops
.acquire(hw
);
4193 e_dbg("Failed to setup iRST\n");
4197 if (!(er32(FWSM
) & E1000_ICH_FWSM_FW_VALID
)) {
4198 /* Restore clear on SMB if no manageability engine
4201 ret_val
= e1e_rphy_locked(hw
, I217_MEMPWR
, &phy_reg
);
4204 phy_reg
|= I217_MEMPWR_DISABLE_SMB_RELEASE
;
4205 e1e_wphy_locked(hw
, I217_MEMPWR
, phy_reg
);
4208 e1e_wphy_locked(hw
, I217_PROXY_CTRL
, 0);
4210 /* Enable reset on MTA */
4211 ret_val
= e1e_rphy_locked(hw
, I217_CGFREG
, &phy_reg
);
4214 phy_reg
&= ~I217_CGFREG_ENABLE_MTA_RESET
;
4215 e1e_wphy_locked(hw
, I217_CGFREG
, phy_reg
);
4218 e_dbg("Error %d in resume workarounds\n", ret_val
);
4219 hw
->phy
.ops
.release(hw
);
4224 * e1000_cleanup_led_ich8lan - Restore the default LED operation
4225 * @hw: pointer to the HW structure
4227 * Return the LED back to the default configuration.
4229 static s32
e1000_cleanup_led_ich8lan(struct e1000_hw
*hw
)
4231 if (hw
->phy
.type
== e1000_phy_ife
)
4232 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
, 0);
4234 ew32(LEDCTL
, hw
->mac
.ledctl_default
);
4239 * e1000_led_on_ich8lan - Turn LEDs on
4240 * @hw: pointer to the HW structure
4244 static s32
e1000_led_on_ich8lan(struct e1000_hw
*hw
)
4246 if (hw
->phy
.type
== e1000_phy_ife
)
4247 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
4248 (IFE_PSCL_PROBE_MODE
| IFE_PSCL_PROBE_LEDS_ON
));
4250 ew32(LEDCTL
, hw
->mac
.ledctl_mode2
);
4255 * e1000_led_off_ich8lan - Turn LEDs off
4256 * @hw: pointer to the HW structure
4258 * Turn off the LEDs.
4260 static s32
e1000_led_off_ich8lan(struct e1000_hw
*hw
)
4262 if (hw
->phy
.type
== e1000_phy_ife
)
4263 return e1e_wphy(hw
, IFE_PHY_SPECIAL_CONTROL_LED
,
4264 (IFE_PSCL_PROBE_MODE
|
4265 IFE_PSCL_PROBE_LEDS_OFF
));
4267 ew32(LEDCTL
, hw
->mac
.ledctl_mode1
);
4272 * e1000_setup_led_pchlan - Configures SW controllable LED
4273 * @hw: pointer to the HW structure
4275 * This prepares the SW controllable LED for use.
4277 static s32
e1000_setup_led_pchlan(struct e1000_hw
*hw
)
4279 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_mode1
);
4283 * e1000_cleanup_led_pchlan - Restore the default LED operation
4284 * @hw: pointer to the HW structure
4286 * Return the LED back to the default configuration.
4288 static s32
e1000_cleanup_led_pchlan(struct e1000_hw
*hw
)
4290 return e1e_wphy(hw
, HV_LED_CONFIG
, (u16
)hw
->mac
.ledctl_default
);
4294 * e1000_led_on_pchlan - Turn LEDs on
4295 * @hw: pointer to the HW structure
4299 static s32
e1000_led_on_pchlan(struct e1000_hw
*hw
)
4301 u16 data
= (u16
)hw
->mac
.ledctl_mode2
;
4304 /* If no link, then turn LED on by setting the invert bit
4305 * for each LED that's mode is "link_up" in ledctl_mode2.
4307 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
4308 for (i
= 0; i
< 3; i
++) {
4309 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
4310 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
4311 E1000_LEDCTL_MODE_LINK_UP
)
4313 if (led
& E1000_PHY_LED0_IVRT
)
4314 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
4316 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
4320 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
4324 * e1000_led_off_pchlan - Turn LEDs off
4325 * @hw: pointer to the HW structure
4327 * Turn off the LEDs.
4329 static s32
e1000_led_off_pchlan(struct e1000_hw
*hw
)
4331 u16 data
= (u16
)hw
->mac
.ledctl_mode1
;
4334 /* If no link, then turn LED off by clearing the invert bit
4335 * for each LED that's mode is "link_up" in ledctl_mode1.
4337 if (!(er32(STATUS
) & E1000_STATUS_LU
)) {
4338 for (i
= 0; i
< 3; i
++) {
4339 led
= (data
>> (i
* 5)) & E1000_PHY_LED0_MASK
;
4340 if ((led
& E1000_PHY_LED0_MODE_MASK
) !=
4341 E1000_LEDCTL_MODE_LINK_UP
)
4343 if (led
& E1000_PHY_LED0_IVRT
)
4344 data
&= ~(E1000_PHY_LED0_IVRT
<< (i
* 5));
4346 data
|= (E1000_PHY_LED0_IVRT
<< (i
* 5));
4350 return e1e_wphy(hw
, HV_LED_CONFIG
, data
);
4354 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
4355 * @hw: pointer to the HW structure
4357 * Read appropriate register for the config done bit for completion status
4358 * and configure the PHY through s/w for EEPROM-less parts.
4360 * NOTE: some silicon which is EEPROM-less will fail trying to read the
4361 * config done bit, so only an error is logged and continues. If we were
4362 * to return with error, EEPROM-less silicon would not be able to be reset
4365 static s32
e1000_get_cfg_done_ich8lan(struct e1000_hw
*hw
)
4371 e1000e_get_cfg_done(hw
);
4373 /* Wait for indication from h/w that it has completed basic config */
4374 if (hw
->mac
.type
>= e1000_ich10lan
) {
4375 e1000_lan_init_done_ich8lan(hw
);
4377 ret_val
= e1000e_get_auto_rd_done(hw
);
4379 /* When auto config read does not complete, do not
4380 * return with an error. This can happen in situations
4381 * where there is no eeprom and prevents getting link.
4383 e_dbg("Auto Read Done did not complete\n");
4388 /* Clear PHY Reset Asserted bit */
4389 status
= er32(STATUS
);
4390 if (status
& E1000_STATUS_PHYRA
)
4391 ew32(STATUS
, status
& ~E1000_STATUS_PHYRA
);
4393 e_dbg("PHY Reset Asserted not set - needs delay\n");
4395 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
4396 if (hw
->mac
.type
<= e1000_ich9lan
) {
4397 if (!(er32(EECD
) & E1000_EECD_PRES
) &&
4398 (hw
->phy
.type
== e1000_phy_igp_3
)) {
4399 e1000e_phy_init_script_igp3(hw
);
4402 if (e1000_valid_nvm_bank_detect_ich8lan(hw
, &bank
)) {
4403 /* Maybe we should do a basic PHY config */
4404 e_dbg("EEPROM not present\n");
4405 ret_val
= -E1000_ERR_CONFIG
;
4413 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
4414 * @hw: pointer to the HW structure
4416 * In the case of a PHY power down to save power, or to turn off link during a
4417 * driver unload, or wake on lan is not enabled, remove the link.
4419 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw
*hw
)
4421 /* If the management interface is not enabled, then power down */
4422 if (!(hw
->mac
.ops
.check_mng_mode(hw
) ||
4423 hw
->phy
.ops
.check_reset_block(hw
)))
4424 e1000_power_down_phy_copper(hw
);
4428 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
4429 * @hw: pointer to the HW structure
4431 * Clears hardware counters specific to the silicon family and calls
4432 * clear_hw_cntrs_generic to clear all general purpose counters.
4434 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw
*hw
)
4439 e1000e_clear_hw_cntrs_base(hw
);
4455 /* Clear PHY statistics registers */
4456 if ((hw
->phy
.type
== e1000_phy_82578
) ||
4457 (hw
->phy
.type
== e1000_phy_82579
) ||
4458 (hw
->phy
.type
== e1000_phy_i217
) ||
4459 (hw
->phy
.type
== e1000_phy_82577
)) {
4460 ret_val
= hw
->phy
.ops
.acquire(hw
);
4463 ret_val
= hw
->phy
.ops
.set_page(hw
,
4464 HV_STATS_PAGE
<< IGP_PAGE_SHIFT
);
4467 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_UPPER
, &phy_data
);
4468 hw
->phy
.ops
.read_reg_page(hw
, HV_SCC_LOWER
, &phy_data
);
4469 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_UPPER
, &phy_data
);
4470 hw
->phy
.ops
.read_reg_page(hw
, HV_ECOL_LOWER
, &phy_data
);
4471 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_UPPER
, &phy_data
);
4472 hw
->phy
.ops
.read_reg_page(hw
, HV_MCC_LOWER
, &phy_data
);
4473 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_UPPER
, &phy_data
);
4474 hw
->phy
.ops
.read_reg_page(hw
, HV_LATECOL_LOWER
, &phy_data
);
4475 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_UPPER
, &phy_data
);
4476 hw
->phy
.ops
.read_reg_page(hw
, HV_COLC_LOWER
, &phy_data
);
4477 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_UPPER
, &phy_data
);
4478 hw
->phy
.ops
.read_reg_page(hw
, HV_DC_LOWER
, &phy_data
);
4479 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_UPPER
, &phy_data
);
4480 hw
->phy
.ops
.read_reg_page(hw
, HV_TNCRS_LOWER
, &phy_data
);
4482 hw
->phy
.ops
.release(hw
);
4486 static const struct e1000_mac_operations ich8_mac_ops
= {
4487 /* check_mng_mode dependent on mac type */
4488 .check_for_link
= e1000_check_for_copper_link_ich8lan
,
4489 /* cleanup_led dependent on mac type */
4490 .clear_hw_cntrs
= e1000_clear_hw_cntrs_ich8lan
,
4491 .get_bus_info
= e1000_get_bus_info_ich8lan
,
4492 .set_lan_id
= e1000_set_lan_id_single_port
,
4493 .get_link_up_info
= e1000_get_link_up_info_ich8lan
,
4494 /* led_on dependent on mac type */
4495 /* led_off dependent on mac type */
4496 .update_mc_addr_list
= e1000e_update_mc_addr_list_generic
,
4497 .reset_hw
= e1000_reset_hw_ich8lan
,
4498 .init_hw
= e1000_init_hw_ich8lan
,
4499 .setup_link
= e1000_setup_link_ich8lan
,
4500 .setup_physical_interface
= e1000_setup_copper_link_ich8lan
,
4501 /* id_led_init dependent on mac type */
4502 .config_collision_dist
= e1000e_config_collision_dist_generic
,
4503 .rar_set
= e1000e_rar_set_generic
,
4506 static const struct e1000_phy_operations ich8_phy_ops
= {
4507 .acquire
= e1000_acquire_swflag_ich8lan
,
4508 .check_reset_block
= e1000_check_reset_block_ich8lan
,
4510 .get_cfg_done
= e1000_get_cfg_done_ich8lan
,
4511 .get_cable_length
= e1000e_get_cable_length_igp_2
,
4512 .read_reg
= e1000e_read_phy_reg_igp
,
4513 .release
= e1000_release_swflag_ich8lan
,
4514 .reset
= e1000_phy_hw_reset_ich8lan
,
4515 .set_d0_lplu_state
= e1000_set_d0_lplu_state_ich8lan
,
4516 .set_d3_lplu_state
= e1000_set_d3_lplu_state_ich8lan
,
4517 .write_reg
= e1000e_write_phy_reg_igp
,
4520 static const struct e1000_nvm_operations ich8_nvm_ops
= {
4521 .acquire
= e1000_acquire_nvm_ich8lan
,
4522 .read
= e1000_read_nvm_ich8lan
,
4523 .release
= e1000_release_nvm_ich8lan
,
4524 .reload
= e1000e_reload_nvm_generic
,
4525 .update
= e1000_update_nvm_checksum_ich8lan
,
4526 .valid_led_default
= e1000_valid_led_default_ich8lan
,
4527 .validate
= e1000_validate_nvm_checksum_ich8lan
,
4528 .write
= e1000_write_nvm_ich8lan
,
4531 const struct e1000_info e1000_ich8_info
= {
4532 .mac
= e1000_ich8lan
,
4533 .flags
= FLAG_HAS_WOL
4535 | FLAG_HAS_CTRLEXT_ON_LOAD
4540 .max_hw_frame_size
= ETH_FRAME_LEN
+ ETH_FCS_LEN
,
4541 .get_variants
= e1000_get_variants_ich8lan
,
4542 .mac_ops
= &ich8_mac_ops
,
4543 .phy_ops
= &ich8_phy_ops
,
4544 .nvm_ops
= &ich8_nvm_ops
,
4547 const struct e1000_info e1000_ich9_info
= {
4548 .mac
= e1000_ich9lan
,
4549 .flags
= FLAG_HAS_JUMBO_FRAMES
4552 | FLAG_HAS_CTRLEXT_ON_LOAD
4557 .max_hw_frame_size
= DEFAULT_JUMBO
,
4558 .get_variants
= e1000_get_variants_ich8lan
,
4559 .mac_ops
= &ich8_mac_ops
,
4560 .phy_ops
= &ich8_phy_ops
,
4561 .nvm_ops
= &ich8_nvm_ops
,
4564 const struct e1000_info e1000_ich10_info
= {
4565 .mac
= e1000_ich10lan
,
4566 .flags
= FLAG_HAS_JUMBO_FRAMES
4569 | FLAG_HAS_CTRLEXT_ON_LOAD
4574 .max_hw_frame_size
= DEFAULT_JUMBO
,
4575 .get_variants
= e1000_get_variants_ich8lan
,
4576 .mac_ops
= &ich8_mac_ops
,
4577 .phy_ops
= &ich8_phy_ops
,
4578 .nvm_ops
= &ich8_nvm_ops
,
4581 const struct e1000_info e1000_pch_info
= {
4582 .mac
= e1000_pchlan
,
4583 .flags
= FLAG_IS_ICH
4585 | FLAG_HAS_CTRLEXT_ON_LOAD
4588 | FLAG_HAS_JUMBO_FRAMES
4589 | FLAG_DISABLE_FC_PAUSE_TIME
/* errata */
4591 .flags2
= FLAG2_HAS_PHY_STATS
,
4593 .max_hw_frame_size
= 4096,
4594 .get_variants
= e1000_get_variants_ich8lan
,
4595 .mac_ops
= &ich8_mac_ops
,
4596 .phy_ops
= &ich8_phy_ops
,
4597 .nvm_ops
= &ich8_nvm_ops
,
4600 const struct e1000_info e1000_pch2_info
= {
4601 .mac
= e1000_pch2lan
,
4602 .flags
= FLAG_IS_ICH
4604 | FLAG_HAS_CTRLEXT_ON_LOAD
4607 | FLAG_HAS_JUMBO_FRAMES
4609 .flags2
= FLAG2_HAS_PHY_STATS
4612 .max_hw_frame_size
= DEFAULT_JUMBO
,
4613 .get_variants
= e1000_get_variants_ich8lan
,
4614 .mac_ops
= &ich8_mac_ops
,
4615 .phy_ops
= &ich8_phy_ops
,
4616 .nvm_ops
= &ich8_nvm_ops
,
4619 const struct e1000_info e1000_pch_lpt_info
= {
4620 .mac
= e1000_pch_lpt
,
4621 .flags
= FLAG_IS_ICH
4623 | FLAG_HAS_CTRLEXT_ON_LOAD
4626 | FLAG_HAS_JUMBO_FRAMES
4628 .flags2
= FLAG2_HAS_PHY_STATS
4631 .max_hw_frame_size
= DEFAULT_JUMBO
,
4632 .get_variants
= e1000_get_variants_ich8lan
,
4633 .mac_ops
= &ich8_mac_ops
,
4634 .phy_ops
= &ich8_phy_ops
,
4635 .nvm_ops
= &ich8_nvm_ops
,