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e1000e: Set HW FIFO minimum pointer gap for non-gig speeds
[deliverable/linux.git] / drivers / net / ethernet / intel / e1000e / ich8lan.c
1 /* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2015 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
21
22 /* 82562G 10/100 Network Connection
23 * 82562G-2 10/100 Network Connection
24 * 82562GT 10/100 Network Connection
25 * 82562GT-2 10/100 Network Connection
26 * 82562V 10/100 Network Connection
27 * 82562V-2 10/100 Network Connection
28 * 82566DC-2 Gigabit Network Connection
29 * 82566DC Gigabit Network Connection
30 * 82566DM-2 Gigabit Network Connection
31 * 82566DM Gigabit Network Connection
32 * 82566MC Gigabit Network Connection
33 * 82566MM Gigabit Network Connection
34 * 82567LM Gigabit Network Connection
35 * 82567LF Gigabit Network Connection
36 * 82567V Gigabit Network Connection
37 * 82567LM-2 Gigabit Network Connection
38 * 82567LF-2 Gigabit Network Connection
39 * 82567V-2 Gigabit Network Connection
40 * 82567LF-3 Gigabit Network Connection
41 * 82567LM-3 Gigabit Network Connection
42 * 82567LM-4 Gigabit Network Connection
43 * 82577LM Gigabit Network Connection
44 * 82577LC Gigabit Network Connection
45 * 82578DM Gigabit Network Connection
46 * 82578DC Gigabit Network Connection
47 * 82579LM Gigabit Network Connection
48 * 82579V Gigabit Network Connection
49 * Ethernet Connection I217-LM
50 * Ethernet Connection I217-V
51 * Ethernet Connection I218-V
52 * Ethernet Connection I218-LM
53 * Ethernet Connection (2) I218-LM
54 * Ethernet Connection (2) I218-V
55 * Ethernet Connection (3) I218-LM
56 * Ethernet Connection (3) I218-V
57 */
58
59 #include "e1000.h"
60
61 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
62 /* Offset 04h HSFSTS */
63 union ich8_hws_flash_status {
64 struct ich8_hsfsts {
65 u16 flcdone:1; /* bit 0 Flash Cycle Done */
66 u16 flcerr:1; /* bit 1 Flash Cycle Error */
67 u16 dael:1; /* bit 2 Direct Access error Log */
68 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
69 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
70 u16 reserved1:2; /* bit 13:6 Reserved */
71 u16 reserved2:6; /* bit 13:6 Reserved */
72 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
73 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
74 } hsf_status;
75 u16 regval;
76 };
77
78 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
79 /* Offset 06h FLCTL */
80 union ich8_hws_flash_ctrl {
81 struct ich8_hsflctl {
82 u16 flcgo:1; /* 0 Flash Cycle Go */
83 u16 flcycle:2; /* 2:1 Flash Cycle */
84 u16 reserved:5; /* 7:3 Reserved */
85 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
86 u16 flockdn:6; /* 15:10 Reserved */
87 } hsf_ctrl;
88 u16 regval;
89 };
90
91 /* ICH Flash Region Access Permissions */
92 union ich8_hws_flash_regacc {
93 struct ich8_flracc {
94 u32 grra:8; /* 0:7 GbE region Read Access */
95 u32 grwa:8; /* 8:15 GbE region Write Access */
96 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
97 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
98 } hsf_flregacc;
99 u16 regval;
100 };
101
102 /* ICH Flash Protected Region */
103 union ich8_flash_protected_range {
104 struct ich8_pr {
105 u32 base:13; /* 0:12 Protected Range Base */
106 u32 reserved1:2; /* 13:14 Reserved */
107 u32 rpe:1; /* 15 Read Protection Enable */
108 u32 limit:13; /* 16:28 Protected Range Limit */
109 u32 reserved2:2; /* 29:30 Reserved */
110 u32 wpe:1; /* 31 Write Protection Enable */
111 } range;
112 u32 regval;
113 };
114
115 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
116 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
117 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
118 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
119 u32 offset, u8 byte);
120 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
121 u8 *data);
122 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
123 u16 *data);
124 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
125 u8 size, u16 *data);
126 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
127 u32 *data);
128 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
129 u32 offset, u32 *data);
130 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
131 u32 offset, u32 data);
132 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
133 u32 offset, u32 dword);
134 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
135 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
136 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
137 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
138 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
139 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
140 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
141 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
142 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
143 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
144 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
145 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
146 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
147 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
148 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
149 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
150 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
151 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
152 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
153 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
155 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
156 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
157 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
158
159 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
160 {
161 return readw(hw->flash_address + reg);
162 }
163
164 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
165 {
166 return readl(hw->flash_address + reg);
167 }
168
169 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
170 {
171 writew(val, hw->flash_address + reg);
172 }
173
174 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
175 {
176 writel(val, hw->flash_address + reg);
177 }
178
179 #define er16flash(reg) __er16flash(hw, (reg))
180 #define er32flash(reg) __er32flash(hw, (reg))
181 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
182 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
183
184 /**
185 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
186 * @hw: pointer to the HW structure
187 *
188 * Test access to the PHY registers by reading the PHY ID registers. If
189 * the PHY ID is already known (e.g. resume path) compare it with known ID,
190 * otherwise assume the read PHY ID is correct if it is valid.
191 *
192 * Assumes the sw/fw/hw semaphore is already acquired.
193 **/
194 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
195 {
196 u16 phy_reg = 0;
197 u32 phy_id = 0;
198 s32 ret_val = 0;
199 u16 retry_count;
200 u32 mac_reg = 0;
201
202 for (retry_count = 0; retry_count < 2; retry_count++) {
203 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
204 if (ret_val || (phy_reg == 0xFFFF))
205 continue;
206 phy_id = (u32)(phy_reg << 16);
207
208 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
209 if (ret_val || (phy_reg == 0xFFFF)) {
210 phy_id = 0;
211 continue;
212 }
213 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
214 break;
215 }
216
217 if (hw->phy.id) {
218 if (hw->phy.id == phy_id)
219 goto out;
220 } else if (phy_id) {
221 hw->phy.id = phy_id;
222 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
223 goto out;
224 }
225
226 /* In case the PHY needs to be in mdio slow mode,
227 * set slow mode and try to get the PHY id again.
228 */
229 if (hw->mac.type < e1000_pch_lpt) {
230 hw->phy.ops.release(hw);
231 ret_val = e1000_set_mdio_slow_mode_hv(hw);
232 if (!ret_val)
233 ret_val = e1000e_get_phy_id(hw);
234 hw->phy.ops.acquire(hw);
235 }
236
237 if (ret_val)
238 return false;
239 out:
240 if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
241 /* Only unforce SMBus if ME is not active */
242 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
243 /* Unforce SMBus mode in PHY */
244 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
245 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
246 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
247
248 /* Unforce SMBus mode in MAC */
249 mac_reg = er32(CTRL_EXT);
250 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
251 ew32(CTRL_EXT, mac_reg);
252 }
253 }
254
255 return true;
256 }
257
258 /**
259 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
260 * @hw: pointer to the HW structure
261 *
262 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
263 * used to reset the PHY to a quiescent state when necessary.
264 **/
265 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
266 {
267 u32 mac_reg;
268
269 /* Set Phy Config Counter to 50msec */
270 mac_reg = er32(FEXTNVM3);
271 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
272 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
273 ew32(FEXTNVM3, mac_reg);
274
275 /* Toggle LANPHYPC Value bit */
276 mac_reg = er32(CTRL);
277 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
278 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
279 ew32(CTRL, mac_reg);
280 e1e_flush();
281 usleep_range(10, 20);
282 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
283 ew32(CTRL, mac_reg);
284 e1e_flush();
285
286 if (hw->mac.type < e1000_pch_lpt) {
287 msleep(50);
288 } else {
289 u16 count = 20;
290
291 do {
292 usleep_range(5000, 10000);
293 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
294
295 msleep(30);
296 }
297 }
298
299 /**
300 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
301 * @hw: pointer to the HW structure
302 *
303 * Workarounds/flow necessary for PHY initialization during driver load
304 * and resume paths.
305 **/
306 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
307 {
308 struct e1000_adapter *adapter = hw->adapter;
309 u32 mac_reg, fwsm = er32(FWSM);
310 s32 ret_val;
311
312 /* Gate automatic PHY configuration by hardware on managed and
313 * non-managed 82579 and newer adapters.
314 */
315 e1000_gate_hw_phy_config_ich8lan(hw, true);
316
317 /* It is not possible to be certain of the current state of ULP
318 * so forcibly disable it.
319 */
320 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
321 e1000_disable_ulp_lpt_lp(hw, true);
322
323 ret_val = hw->phy.ops.acquire(hw);
324 if (ret_val) {
325 e_dbg("Failed to initialize PHY flow\n");
326 goto out;
327 }
328
329 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
330 * inaccessible and resetting the PHY is not blocked, toggle the
331 * LANPHYPC Value bit to force the interconnect to PCIe mode.
332 */
333 switch (hw->mac.type) {
334 case e1000_pch_lpt:
335 case e1000_pch_spt:
336 if (e1000_phy_is_accessible_pchlan(hw))
337 break;
338
339 /* Before toggling LANPHYPC, see if PHY is accessible by
340 * forcing MAC to SMBus mode first.
341 */
342 mac_reg = er32(CTRL_EXT);
343 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
344 ew32(CTRL_EXT, mac_reg);
345
346 /* Wait 50 milliseconds for MAC to finish any retries
347 * that it might be trying to perform from previous
348 * attempts to acknowledge any phy read requests.
349 */
350 msleep(50);
351
352 /* fall-through */
353 case e1000_pch2lan:
354 if (e1000_phy_is_accessible_pchlan(hw))
355 break;
356
357 /* fall-through */
358 case e1000_pchlan:
359 if ((hw->mac.type == e1000_pchlan) &&
360 (fwsm & E1000_ICH_FWSM_FW_VALID))
361 break;
362
363 if (hw->phy.ops.check_reset_block(hw)) {
364 e_dbg("Required LANPHYPC toggle blocked by ME\n");
365 ret_val = -E1000_ERR_PHY;
366 break;
367 }
368
369 /* Toggle LANPHYPC Value bit */
370 e1000_toggle_lanphypc_pch_lpt(hw);
371 if (hw->mac.type >= e1000_pch_lpt) {
372 if (e1000_phy_is_accessible_pchlan(hw))
373 break;
374
375 /* Toggling LANPHYPC brings the PHY out of SMBus mode
376 * so ensure that the MAC is also out of SMBus mode
377 */
378 mac_reg = er32(CTRL_EXT);
379 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
380 ew32(CTRL_EXT, mac_reg);
381
382 if (e1000_phy_is_accessible_pchlan(hw))
383 break;
384
385 ret_val = -E1000_ERR_PHY;
386 }
387 break;
388 default:
389 break;
390 }
391
392 hw->phy.ops.release(hw);
393 if (!ret_val) {
394
395 /* Check to see if able to reset PHY. Print error if not */
396 if (hw->phy.ops.check_reset_block(hw)) {
397 e_err("Reset blocked by ME\n");
398 goto out;
399 }
400
401 /* Reset the PHY before any access to it. Doing so, ensures
402 * that the PHY is in a known good state before we read/write
403 * PHY registers. The generic reset is sufficient here,
404 * because we haven't determined the PHY type yet.
405 */
406 ret_val = e1000e_phy_hw_reset_generic(hw);
407 if (ret_val)
408 goto out;
409
410 /* On a successful reset, possibly need to wait for the PHY
411 * to quiesce to an accessible state before returning control
412 * to the calling function. If the PHY does not quiesce, then
413 * return E1000E_BLK_PHY_RESET, as this is the condition that
414 * the PHY is in.
415 */
416 ret_val = hw->phy.ops.check_reset_block(hw);
417 if (ret_val)
418 e_err("ME blocked access to PHY after reset\n");
419 }
420
421 out:
422 /* Ungate automatic PHY configuration on non-managed 82579 */
423 if ((hw->mac.type == e1000_pch2lan) &&
424 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
425 usleep_range(10000, 20000);
426 e1000_gate_hw_phy_config_ich8lan(hw, false);
427 }
428
429 return ret_val;
430 }
431
432 /**
433 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
434 * @hw: pointer to the HW structure
435 *
436 * Initialize family-specific PHY parameters and function pointers.
437 **/
438 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
439 {
440 struct e1000_phy_info *phy = &hw->phy;
441 s32 ret_val;
442
443 phy->addr = 1;
444 phy->reset_delay_us = 100;
445
446 phy->ops.set_page = e1000_set_page_igp;
447 phy->ops.read_reg = e1000_read_phy_reg_hv;
448 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
449 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
450 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
451 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
452 phy->ops.write_reg = e1000_write_phy_reg_hv;
453 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
454 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
455 phy->ops.power_up = e1000_power_up_phy_copper;
456 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
457 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
458
459 phy->id = e1000_phy_unknown;
460
461 ret_val = e1000_init_phy_workarounds_pchlan(hw);
462 if (ret_val)
463 return ret_val;
464
465 if (phy->id == e1000_phy_unknown)
466 switch (hw->mac.type) {
467 default:
468 ret_val = e1000e_get_phy_id(hw);
469 if (ret_val)
470 return ret_val;
471 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
472 break;
473 /* fall-through */
474 case e1000_pch2lan:
475 case e1000_pch_lpt:
476 case e1000_pch_spt:
477 /* In case the PHY needs to be in mdio slow mode,
478 * set slow mode and try to get the PHY id again.
479 */
480 ret_val = e1000_set_mdio_slow_mode_hv(hw);
481 if (ret_val)
482 return ret_val;
483 ret_val = e1000e_get_phy_id(hw);
484 if (ret_val)
485 return ret_val;
486 break;
487 }
488 phy->type = e1000e_get_phy_type_from_id(phy->id);
489
490 switch (phy->type) {
491 case e1000_phy_82577:
492 case e1000_phy_82579:
493 case e1000_phy_i217:
494 phy->ops.check_polarity = e1000_check_polarity_82577;
495 phy->ops.force_speed_duplex =
496 e1000_phy_force_speed_duplex_82577;
497 phy->ops.get_cable_length = e1000_get_cable_length_82577;
498 phy->ops.get_info = e1000_get_phy_info_82577;
499 phy->ops.commit = e1000e_phy_sw_reset;
500 break;
501 case e1000_phy_82578:
502 phy->ops.check_polarity = e1000_check_polarity_m88;
503 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
504 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
505 phy->ops.get_info = e1000e_get_phy_info_m88;
506 break;
507 default:
508 ret_val = -E1000_ERR_PHY;
509 break;
510 }
511
512 return ret_val;
513 }
514
515 /**
516 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
517 * @hw: pointer to the HW structure
518 *
519 * Initialize family-specific PHY parameters and function pointers.
520 **/
521 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
522 {
523 struct e1000_phy_info *phy = &hw->phy;
524 s32 ret_val;
525 u16 i = 0;
526
527 phy->addr = 1;
528 phy->reset_delay_us = 100;
529
530 phy->ops.power_up = e1000_power_up_phy_copper;
531 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
532
533 /* We may need to do this twice - once for IGP and if that fails,
534 * we'll set BM func pointers and try again
535 */
536 ret_val = e1000e_determine_phy_address(hw);
537 if (ret_val) {
538 phy->ops.write_reg = e1000e_write_phy_reg_bm;
539 phy->ops.read_reg = e1000e_read_phy_reg_bm;
540 ret_val = e1000e_determine_phy_address(hw);
541 if (ret_val) {
542 e_dbg("Cannot determine PHY addr. Erroring out\n");
543 return ret_val;
544 }
545 }
546
547 phy->id = 0;
548 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
549 (i++ < 100)) {
550 usleep_range(1000, 2000);
551 ret_val = e1000e_get_phy_id(hw);
552 if (ret_val)
553 return ret_val;
554 }
555
556 /* Verify phy id */
557 switch (phy->id) {
558 case IGP03E1000_E_PHY_ID:
559 phy->type = e1000_phy_igp_3;
560 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
561 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
562 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
563 phy->ops.get_info = e1000e_get_phy_info_igp;
564 phy->ops.check_polarity = e1000_check_polarity_igp;
565 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
566 break;
567 case IFE_E_PHY_ID:
568 case IFE_PLUS_E_PHY_ID:
569 case IFE_C_E_PHY_ID:
570 phy->type = e1000_phy_ife;
571 phy->autoneg_mask = E1000_ALL_NOT_GIG;
572 phy->ops.get_info = e1000_get_phy_info_ife;
573 phy->ops.check_polarity = e1000_check_polarity_ife;
574 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
575 break;
576 case BME1000_E_PHY_ID:
577 phy->type = e1000_phy_bm;
578 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
579 phy->ops.read_reg = e1000e_read_phy_reg_bm;
580 phy->ops.write_reg = e1000e_write_phy_reg_bm;
581 phy->ops.commit = e1000e_phy_sw_reset;
582 phy->ops.get_info = e1000e_get_phy_info_m88;
583 phy->ops.check_polarity = e1000_check_polarity_m88;
584 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
585 break;
586 default:
587 return -E1000_ERR_PHY;
588 }
589
590 return 0;
591 }
592
593 /**
594 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
595 * @hw: pointer to the HW structure
596 *
597 * Initialize family-specific NVM parameters and function
598 * pointers.
599 **/
600 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
601 {
602 struct e1000_nvm_info *nvm = &hw->nvm;
603 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
604 u32 gfpreg, sector_base_addr, sector_end_addr;
605 u16 i;
606 u32 nvm_size;
607
608 nvm->type = e1000_nvm_flash_sw;
609
610 if (hw->mac.type == e1000_pch_spt) {
611 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
612 * STRAP register. This is because in SPT the GbE Flash region
613 * is no longer accessed through the flash registers. Instead,
614 * the mechanism has changed, and the Flash region access
615 * registers are now implemented in GbE memory space.
616 */
617 nvm->flash_base_addr = 0;
618 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
619 * NVM_SIZE_MULTIPLIER;
620 nvm->flash_bank_size = nvm_size / 2;
621 /* Adjust to word count */
622 nvm->flash_bank_size /= sizeof(u16);
623 /* Set the base address for flash register access */
624 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
625 } else {
626 /* Can't read flash registers if register set isn't mapped. */
627 if (!hw->flash_address) {
628 e_dbg("ERROR: Flash registers not mapped\n");
629 return -E1000_ERR_CONFIG;
630 }
631
632 gfpreg = er32flash(ICH_FLASH_GFPREG);
633
634 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
635 * Add 1 to sector_end_addr since this sector is included in
636 * the overall size.
637 */
638 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
639 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
640
641 /* flash_base_addr is byte-aligned */
642 nvm->flash_base_addr = sector_base_addr
643 << FLASH_SECTOR_ADDR_SHIFT;
644
645 /* find total size of the NVM, then cut in half since the total
646 * size represents two separate NVM banks.
647 */
648 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
649 << FLASH_SECTOR_ADDR_SHIFT);
650 nvm->flash_bank_size /= 2;
651 /* Adjust to word count */
652 nvm->flash_bank_size /= sizeof(u16);
653 }
654
655 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
656
657 /* Clear shadow ram */
658 for (i = 0; i < nvm->word_size; i++) {
659 dev_spec->shadow_ram[i].modified = false;
660 dev_spec->shadow_ram[i].value = 0xFFFF;
661 }
662
663 return 0;
664 }
665
666 /**
667 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
668 * @hw: pointer to the HW structure
669 *
670 * Initialize family-specific MAC parameters and function
671 * pointers.
672 **/
673 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
674 {
675 struct e1000_mac_info *mac = &hw->mac;
676
677 /* Set media type function pointer */
678 hw->phy.media_type = e1000_media_type_copper;
679
680 /* Set mta register count */
681 mac->mta_reg_count = 32;
682 /* Set rar entry count */
683 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
684 if (mac->type == e1000_ich8lan)
685 mac->rar_entry_count--;
686 /* FWSM register */
687 mac->has_fwsm = true;
688 /* ARC subsystem not supported */
689 mac->arc_subsystem_valid = false;
690 /* Adaptive IFS supported */
691 mac->adaptive_ifs = true;
692
693 /* LED and other operations */
694 switch (mac->type) {
695 case e1000_ich8lan:
696 case e1000_ich9lan:
697 case e1000_ich10lan:
698 /* check management mode */
699 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
700 /* ID LED init */
701 mac->ops.id_led_init = e1000e_id_led_init_generic;
702 /* blink LED */
703 mac->ops.blink_led = e1000e_blink_led_generic;
704 /* setup LED */
705 mac->ops.setup_led = e1000e_setup_led_generic;
706 /* cleanup LED */
707 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
708 /* turn on/off LED */
709 mac->ops.led_on = e1000_led_on_ich8lan;
710 mac->ops.led_off = e1000_led_off_ich8lan;
711 break;
712 case e1000_pch2lan:
713 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
714 mac->ops.rar_set = e1000_rar_set_pch2lan;
715 /* fall-through */
716 case e1000_pch_lpt:
717 case e1000_pch_spt:
718 case e1000_pchlan:
719 /* check management mode */
720 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
721 /* ID LED init */
722 mac->ops.id_led_init = e1000_id_led_init_pchlan;
723 /* setup LED */
724 mac->ops.setup_led = e1000_setup_led_pchlan;
725 /* cleanup LED */
726 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
727 /* turn on/off LED */
728 mac->ops.led_on = e1000_led_on_pchlan;
729 mac->ops.led_off = e1000_led_off_pchlan;
730 break;
731 default:
732 break;
733 }
734
735 if ((mac->type == e1000_pch_lpt) || (mac->type == e1000_pch_spt)) {
736 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
737 mac->ops.rar_set = e1000_rar_set_pch_lpt;
738 mac->ops.setup_physical_interface =
739 e1000_setup_copper_link_pch_lpt;
740 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
741 }
742
743 /* Enable PCS Lock-loss workaround for ICH8 */
744 if (mac->type == e1000_ich8lan)
745 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
746
747 return 0;
748 }
749
750 /**
751 * __e1000_access_emi_reg_locked - Read/write EMI register
752 * @hw: pointer to the HW structure
753 * @addr: EMI address to program
754 * @data: pointer to value to read/write from/to the EMI address
755 * @read: boolean flag to indicate read or write
756 *
757 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
758 **/
759 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
760 u16 *data, bool read)
761 {
762 s32 ret_val;
763
764 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
765 if (ret_val)
766 return ret_val;
767
768 if (read)
769 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
770 else
771 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
772
773 return ret_val;
774 }
775
776 /**
777 * e1000_read_emi_reg_locked - Read Extended Management Interface register
778 * @hw: pointer to the HW structure
779 * @addr: EMI address to program
780 * @data: value to be read from the EMI address
781 *
782 * Assumes the SW/FW/HW Semaphore is already acquired.
783 **/
784 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
785 {
786 return __e1000_access_emi_reg_locked(hw, addr, data, true);
787 }
788
789 /**
790 * e1000_write_emi_reg_locked - Write Extended Management Interface register
791 * @hw: pointer to the HW structure
792 * @addr: EMI address to program
793 * @data: value to be written to the EMI address
794 *
795 * Assumes the SW/FW/HW Semaphore is already acquired.
796 **/
797 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
798 {
799 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
800 }
801
802 /**
803 * e1000_set_eee_pchlan - Enable/disable EEE support
804 * @hw: pointer to the HW structure
805 *
806 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
807 * the link and the EEE capabilities of the link partner. The LPI Control
808 * register bits will remain set only if/when link is up.
809 *
810 * EEE LPI must not be asserted earlier than one second after link is up.
811 * On 82579, EEE LPI should not be enabled until such time otherwise there
812 * can be link issues with some switches. Other devices can have EEE LPI
813 * enabled immediately upon link up since they have a timer in hardware which
814 * prevents LPI from being asserted too early.
815 **/
816 s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
817 {
818 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
819 s32 ret_val;
820 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
821
822 switch (hw->phy.type) {
823 case e1000_phy_82579:
824 lpa = I82579_EEE_LP_ABILITY;
825 pcs_status = I82579_EEE_PCS_STATUS;
826 adv_addr = I82579_EEE_ADVERTISEMENT;
827 break;
828 case e1000_phy_i217:
829 lpa = I217_EEE_LP_ABILITY;
830 pcs_status = I217_EEE_PCS_STATUS;
831 adv_addr = I217_EEE_ADVERTISEMENT;
832 break;
833 default:
834 return 0;
835 }
836
837 ret_val = hw->phy.ops.acquire(hw);
838 if (ret_val)
839 return ret_val;
840
841 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
842 if (ret_val)
843 goto release;
844
845 /* Clear bits that enable EEE in various speeds */
846 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
847
848 /* Enable EEE if not disabled by user */
849 if (!dev_spec->eee_disable) {
850 /* Save off link partner's EEE ability */
851 ret_val = e1000_read_emi_reg_locked(hw, lpa,
852 &dev_spec->eee_lp_ability);
853 if (ret_val)
854 goto release;
855
856 /* Read EEE advertisement */
857 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
858 if (ret_val)
859 goto release;
860
861 /* Enable EEE only for speeds in which the link partner is
862 * EEE capable and for which we advertise EEE.
863 */
864 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
865 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
866
867 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
868 e1e_rphy_locked(hw, MII_LPA, &data);
869 if (data & LPA_100FULL)
870 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
871 else
872 /* EEE is not supported in 100Half, so ignore
873 * partner's EEE in 100 ability if full-duplex
874 * is not advertised.
875 */
876 dev_spec->eee_lp_ability &=
877 ~I82579_EEE_100_SUPPORTED;
878 }
879 }
880
881 if (hw->phy.type == e1000_phy_82579) {
882 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
883 &data);
884 if (ret_val)
885 goto release;
886
887 data &= ~I82579_LPI_100_PLL_SHUT;
888 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
889 data);
890 }
891
892 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
893 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
894 if (ret_val)
895 goto release;
896
897 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
898 release:
899 hw->phy.ops.release(hw);
900
901 return ret_val;
902 }
903
904 /**
905 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
906 * @hw: pointer to the HW structure
907 * @link: link up bool flag
908 *
909 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
910 * preventing further DMA write requests. Workaround the issue by disabling
911 * the de-assertion of the clock request when in 1Gpbs mode.
912 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
913 * speeds in order to avoid Tx hangs.
914 **/
915 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
916 {
917 u32 fextnvm6 = er32(FEXTNVM6);
918 u32 status = er32(STATUS);
919 s32 ret_val = 0;
920 u16 reg;
921
922 if (link && (status & E1000_STATUS_SPEED_1000)) {
923 ret_val = hw->phy.ops.acquire(hw);
924 if (ret_val)
925 return ret_val;
926
927 ret_val =
928 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
929 &reg);
930 if (ret_val)
931 goto release;
932
933 ret_val =
934 e1000e_write_kmrn_reg_locked(hw,
935 E1000_KMRNCTRLSTA_K1_CONFIG,
936 reg &
937 ~E1000_KMRNCTRLSTA_K1_ENABLE);
938 if (ret_val)
939 goto release;
940
941 usleep_range(10, 20);
942
943 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
944
945 ret_val =
946 e1000e_write_kmrn_reg_locked(hw,
947 E1000_KMRNCTRLSTA_K1_CONFIG,
948 reg);
949 release:
950 hw->phy.ops.release(hw);
951 } else {
952 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
953 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
954
955 if ((hw->phy.revision > 5) || !link ||
956 ((status & E1000_STATUS_SPEED_100) &&
957 (status & E1000_STATUS_FD)))
958 goto update_fextnvm6;
959
960 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, &reg);
961 if (ret_val)
962 return ret_val;
963
964 /* Clear link status transmit timeout */
965 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
966
967 if (status & E1000_STATUS_SPEED_100) {
968 /* Set inband Tx timeout to 5x10us for 100Half */
969 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
970
971 /* Do not extend the K1 entry latency for 100Half */
972 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
973 } else {
974 /* Set inband Tx timeout to 50x10us for 10Full/Half */
975 reg |= 50 <<
976 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
977
978 /* Extend the K1 entry latency for 10 Mbps */
979 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
980 }
981
982 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
983 if (ret_val)
984 return ret_val;
985
986 update_fextnvm6:
987 ew32(FEXTNVM6, fextnvm6);
988 }
989
990 return ret_val;
991 }
992
993 /**
994 * e1000_platform_pm_pch_lpt - Set platform power management values
995 * @hw: pointer to the HW structure
996 * @link: bool indicating link status
997 *
998 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
999 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1000 * when link is up (which must not exceed the maximum latency supported
1001 * by the platform), otherwise specify there is no LTR requirement.
1002 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1003 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1004 * Capability register set, on this device LTR is set by writing the
1005 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1006 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1007 * message to the PMC.
1008 **/
1009 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1010 {
1011 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1012 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1013 u16 lat_enc = 0; /* latency encoded */
1014
1015 if (link) {
1016 u16 speed, duplex, scale = 0;
1017 u16 max_snoop, max_nosnoop;
1018 u16 max_ltr_enc; /* max LTR latency encoded */
1019 u64 value;
1020 u32 rxa;
1021
1022 if (!hw->adapter->max_frame_size) {
1023 e_dbg("max_frame_size not set.\n");
1024 return -E1000_ERR_CONFIG;
1025 }
1026
1027 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1028 if (!speed) {
1029 e_dbg("Speed not set.\n");
1030 return -E1000_ERR_CONFIG;
1031 }
1032
1033 /* Rx Packet Buffer Allocation size (KB) */
1034 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1035
1036 /* Determine the maximum latency tolerated by the device.
1037 *
1038 * Per the PCIe spec, the tolerated latencies are encoded as
1039 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1040 * a 10-bit value (0-1023) to provide a range from 1 ns to
1041 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1042 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1043 */
1044 rxa *= 512;
1045 value = (rxa > hw->adapter->max_frame_size) ?
1046 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1047 0;
1048
1049 while (value > PCI_LTR_VALUE_MASK) {
1050 scale++;
1051 value = DIV_ROUND_UP(value, (1 << 5));
1052 }
1053 if (scale > E1000_LTRV_SCALE_MAX) {
1054 e_dbg("Invalid LTR latency scale %d\n", scale);
1055 return -E1000_ERR_CONFIG;
1056 }
1057 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1058
1059 /* Determine the maximum latency tolerated by the platform */
1060 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1061 &max_snoop);
1062 pci_read_config_word(hw->adapter->pdev,
1063 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1064 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1065
1066 if (lat_enc > max_ltr_enc)
1067 lat_enc = max_ltr_enc;
1068 }
1069
1070 /* Set Snoop and No-Snoop latencies the same */
1071 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1072 ew32(LTRV, reg);
1073
1074 return 0;
1075 }
1076
1077 /**
1078 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1079 * @hw: pointer to the HW structure
1080 * @to_sx: boolean indicating a system power state transition to Sx
1081 *
1082 * When link is down, configure ULP mode to significantly reduce the power
1083 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1084 * ME firmware to start the ULP configuration. If not on an ME enabled
1085 * system, configure the ULP mode by software.
1086 */
1087 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1088 {
1089 u32 mac_reg;
1090 s32 ret_val = 0;
1091 u16 phy_reg;
1092 u16 oem_reg = 0;
1093
1094 if ((hw->mac.type < e1000_pch_lpt) ||
1095 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1096 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1097 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1098 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1099 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1100 return 0;
1101
1102 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1103 /* Request ME configure ULP mode in the PHY */
1104 mac_reg = er32(H2ME);
1105 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1106 ew32(H2ME, mac_reg);
1107
1108 goto out;
1109 }
1110
1111 if (!to_sx) {
1112 int i = 0;
1113
1114 /* Poll up to 5 seconds for Cable Disconnected indication */
1115 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1116 /* Bail if link is re-acquired */
1117 if (er32(STATUS) & E1000_STATUS_LU)
1118 return -E1000_ERR_PHY;
1119
1120 if (i++ == 100)
1121 break;
1122
1123 msleep(50);
1124 }
1125 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1126 (er32(FEXT) &
1127 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1128 }
1129
1130 ret_val = hw->phy.ops.acquire(hw);
1131 if (ret_val)
1132 goto out;
1133
1134 /* Force SMBus mode in PHY */
1135 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1136 if (ret_val)
1137 goto release;
1138 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1139 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1140
1141 /* Force SMBus mode in MAC */
1142 mac_reg = er32(CTRL_EXT);
1143 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1144 ew32(CTRL_EXT, mac_reg);
1145
1146 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1147 * LPLU and disable Gig speed when entering ULP
1148 */
1149 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1150 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1151 &oem_reg);
1152 if (ret_val)
1153 goto release;
1154
1155 phy_reg = oem_reg;
1156 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1157
1158 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1159 phy_reg);
1160
1161 if (ret_val)
1162 goto release;
1163 }
1164
1165 /* Set Inband ULP Exit, Reset to SMBus mode and
1166 * Disable SMBus Release on PERST# in PHY
1167 */
1168 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1169 if (ret_val)
1170 goto release;
1171 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1172 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1173 if (to_sx) {
1174 if (er32(WUFC) & E1000_WUFC_LNKC)
1175 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1176 else
1177 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1178
1179 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1180 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1181 } else {
1182 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1183 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1184 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1185 }
1186 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1187
1188 /* Set Disable SMBus Release on PERST# in MAC */
1189 mac_reg = er32(FEXTNVM7);
1190 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1191 ew32(FEXTNVM7, mac_reg);
1192
1193 /* Commit ULP changes in PHY by starting auto ULP configuration */
1194 phy_reg |= I218_ULP_CONFIG1_START;
1195 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1196
1197 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1198 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1199 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1200 oem_reg);
1201 if (ret_val)
1202 goto release;
1203 }
1204
1205 release:
1206 hw->phy.ops.release(hw);
1207 out:
1208 if (ret_val)
1209 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1210 else
1211 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1212
1213 return ret_val;
1214 }
1215
1216 /**
1217 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1218 * @hw: pointer to the HW structure
1219 * @force: boolean indicating whether or not to force disabling ULP
1220 *
1221 * Un-configure ULP mode when link is up, the system is transitioned from
1222 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1223 * system, poll for an indication from ME that ULP has been un-configured.
1224 * If not on an ME enabled system, un-configure the ULP mode by software.
1225 *
1226 * During nominal operation, this function is called when link is acquired
1227 * to disable ULP mode (force=false); otherwise, for example when unloading
1228 * the driver or during Sx->S0 transitions, this is called with force=true
1229 * to forcibly disable ULP.
1230 */
1231 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1232 {
1233 s32 ret_val = 0;
1234 u32 mac_reg;
1235 u16 phy_reg;
1236 int i = 0;
1237
1238 if ((hw->mac.type < e1000_pch_lpt) ||
1239 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1240 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1241 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1242 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1243 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1244 return 0;
1245
1246 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1247 if (force) {
1248 /* Request ME un-configure ULP mode in the PHY */
1249 mac_reg = er32(H2ME);
1250 mac_reg &= ~E1000_H2ME_ULP;
1251 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1252 ew32(H2ME, mac_reg);
1253 }
1254
1255 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1256 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1257 if (i++ == 30) {
1258 ret_val = -E1000_ERR_PHY;
1259 goto out;
1260 }
1261
1262 usleep_range(10000, 20000);
1263 }
1264 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1265
1266 if (force) {
1267 mac_reg = er32(H2ME);
1268 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1269 ew32(H2ME, mac_reg);
1270 } else {
1271 /* Clear H2ME.ULP after ME ULP configuration */
1272 mac_reg = er32(H2ME);
1273 mac_reg &= ~E1000_H2ME_ULP;
1274 ew32(H2ME, mac_reg);
1275 }
1276
1277 goto out;
1278 }
1279
1280 ret_val = hw->phy.ops.acquire(hw);
1281 if (ret_val)
1282 goto out;
1283
1284 if (force)
1285 /* Toggle LANPHYPC Value bit */
1286 e1000_toggle_lanphypc_pch_lpt(hw);
1287
1288 /* Unforce SMBus mode in PHY */
1289 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1290 if (ret_val) {
1291 /* The MAC might be in PCIe mode, so temporarily force to
1292 * SMBus mode in order to access the PHY.
1293 */
1294 mac_reg = er32(CTRL_EXT);
1295 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1296 ew32(CTRL_EXT, mac_reg);
1297
1298 msleep(50);
1299
1300 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1301 &phy_reg);
1302 if (ret_val)
1303 goto release;
1304 }
1305 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1306 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1307
1308 /* Unforce SMBus mode in MAC */
1309 mac_reg = er32(CTRL_EXT);
1310 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1311 ew32(CTRL_EXT, mac_reg);
1312
1313 /* When ULP mode was previously entered, K1 was disabled by the
1314 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1315 */
1316 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1317 if (ret_val)
1318 goto release;
1319 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1320 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1321
1322 /* Clear ULP enabled configuration */
1323 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1324 if (ret_val)
1325 goto release;
1326 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1327 I218_ULP_CONFIG1_STICKY_ULP |
1328 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1329 I218_ULP_CONFIG1_WOL_HOST |
1330 I218_ULP_CONFIG1_INBAND_EXIT |
1331 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1332 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1333
1334 /* Commit ULP changes by starting auto ULP configuration */
1335 phy_reg |= I218_ULP_CONFIG1_START;
1336 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1337
1338 /* Clear Disable SMBus Release on PERST# in MAC */
1339 mac_reg = er32(FEXTNVM7);
1340 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1341 ew32(FEXTNVM7, mac_reg);
1342
1343 release:
1344 hw->phy.ops.release(hw);
1345 if (force) {
1346 e1000_phy_hw_reset(hw);
1347 msleep(50);
1348 }
1349 out:
1350 if (ret_val)
1351 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1352 else
1353 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1354
1355 return ret_val;
1356 }
1357
1358 /**
1359 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1360 * @hw: pointer to the HW structure
1361 *
1362 * Checks to see of the link status of the hardware has changed. If a
1363 * change in link status has been detected, then we read the PHY registers
1364 * to get the current speed/duplex if link exists.
1365 **/
1366 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1367 {
1368 struct e1000_mac_info *mac = &hw->mac;
1369 s32 ret_val, tipg_reg = 0;
1370 u16 emi_addr, emi_val = 0;
1371 bool link;
1372 u16 phy_reg;
1373
1374 /* We only want to go out to the PHY registers to see if Auto-Neg
1375 * has completed and/or if our link status has changed. The
1376 * get_link_status flag is set upon receiving a Link Status
1377 * Change or Rx Sequence Error interrupt.
1378 */
1379 if (!mac->get_link_status)
1380 return 0;
1381
1382 /* First we want to see if the MII Status Register reports
1383 * link. If so, then we want to get the current speed/duplex
1384 * of the PHY.
1385 */
1386 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1387 if (ret_val)
1388 return ret_val;
1389
1390 if (hw->mac.type == e1000_pchlan) {
1391 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1392 if (ret_val)
1393 return ret_val;
1394 }
1395
1396 /* When connected at 10Mbps half-duplex, some parts are excessively
1397 * aggressive resulting in many collisions. To avoid this, increase
1398 * the IPG and reduce Rx latency in the PHY.
1399 */
1400 if (((hw->mac.type == e1000_pch2lan) ||
1401 (hw->mac.type == e1000_pch_lpt) ||
1402 (hw->mac.type == e1000_pch_spt)) && link) {
1403 u16 speed, duplex;
1404
1405 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1406 tipg_reg = er32(TIPG);
1407 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1408
1409 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1410 tipg_reg |= 0xFF;
1411 /* Reduce Rx latency in analog PHY */
1412 emi_val = 0;
1413 } else if (hw->mac.type == e1000_pch_spt &&
1414 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1415 tipg_reg |= 0xC;
1416 emi_val = 1;
1417 } else {
1418
1419 /* Roll back the default values */
1420 tipg_reg |= 0x08;
1421 emi_val = 1;
1422 }
1423
1424 ew32(TIPG, tipg_reg);
1425
1426 ret_val = hw->phy.ops.acquire(hw);
1427 if (ret_val)
1428 return ret_val;
1429
1430 if (hw->mac.type == e1000_pch2lan)
1431 emi_addr = I82579_RX_CONFIG;
1432 else
1433 emi_addr = I217_RX_CONFIG;
1434 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1435
1436 if (hw->mac.type == e1000_pch_lpt ||
1437 hw->mac.type == e1000_pch_spt) {
1438 u16 phy_reg;
1439
1440 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1441 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1442 if (speed == SPEED_100 || speed == SPEED_10)
1443 phy_reg |= 0x3E8;
1444 else
1445 phy_reg |= 0xFA;
1446 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1447 }
1448 hw->phy.ops.release(hw);
1449
1450 if (ret_val)
1451 return ret_val;
1452
1453 if (hw->mac.type == e1000_pch_spt) {
1454 u16 data;
1455 u16 ptr_gap;
1456
1457 if (speed == SPEED_1000) {
1458 ret_val = hw->phy.ops.acquire(hw);
1459 if (ret_val)
1460 return ret_val;
1461
1462 ret_val = e1e_rphy_locked(hw,
1463 PHY_REG(776, 20),
1464 &data);
1465 if (ret_val) {
1466 hw->phy.ops.release(hw);
1467 return ret_val;
1468 }
1469
1470 ptr_gap = (data & (0x3FF << 2)) >> 2;
1471 if (ptr_gap < 0x18) {
1472 data &= ~(0x3FF << 2);
1473 data |= (0x18 << 2);
1474 ret_val =
1475 e1e_wphy_locked(hw,
1476 PHY_REG(776, 20),
1477 data);
1478 }
1479 hw->phy.ops.release(hw);
1480 if (ret_val)
1481 return ret_val;
1482 } else {
1483 ret_val = hw->phy.ops.acquire(hw);
1484 if (ret_val)
1485 return ret_val;
1486
1487 ret_val = e1e_wphy_locked(hw,
1488 PHY_REG(776, 20),
1489 0xC023);
1490 hw->phy.ops.release(hw);
1491 if (ret_val)
1492 return ret_val;
1493
1494 }
1495 }
1496 }
1497
1498 /* I217 Packet Loss issue:
1499 * ensure that FEXTNVM4 Beacon Duration is set correctly
1500 * on power up.
1501 * Set the Beacon Duration for I217 to 8 usec
1502 */
1503 if ((hw->mac.type == e1000_pch_lpt) || (hw->mac.type == e1000_pch_spt)) {
1504 u32 mac_reg;
1505
1506 mac_reg = er32(FEXTNVM4);
1507 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1508 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1509 ew32(FEXTNVM4, mac_reg);
1510 }
1511
1512 /* Work-around I218 hang issue */
1513 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1514 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1515 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1516 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1517 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1518 if (ret_val)
1519 return ret_val;
1520 }
1521 if ((hw->mac.type == e1000_pch_lpt) ||
1522 (hw->mac.type == e1000_pch_spt)) {
1523 /* Set platform power management values for
1524 * Latency Tolerance Reporting (LTR)
1525 */
1526 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1527 if (ret_val)
1528 return ret_val;
1529 }
1530
1531 /* Clear link partner's EEE ability */
1532 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1533
1534 /* FEXTNVM6 K1-off workaround */
1535 if (hw->mac.type == e1000_pch_spt) {
1536 u32 pcieanacfg = er32(PCIEANACFG);
1537 u32 fextnvm6 = er32(FEXTNVM6);
1538
1539 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1540 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1541 else
1542 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1543
1544 ew32(FEXTNVM6, fextnvm6);
1545 }
1546
1547 if (!link)
1548 return 0; /* No link detected */
1549
1550 mac->get_link_status = false;
1551
1552 switch (hw->mac.type) {
1553 case e1000_pch2lan:
1554 ret_val = e1000_k1_workaround_lv(hw);
1555 if (ret_val)
1556 return ret_val;
1557 /* fall-thru */
1558 case e1000_pchlan:
1559 if (hw->phy.type == e1000_phy_82578) {
1560 ret_val = e1000_link_stall_workaround_hv(hw);
1561 if (ret_val)
1562 return ret_val;
1563 }
1564
1565 /* Workaround for PCHx parts in half-duplex:
1566 * Set the number of preambles removed from the packet
1567 * when it is passed from the PHY to the MAC to prevent
1568 * the MAC from misinterpreting the packet type.
1569 */
1570 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1571 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1572
1573 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1574 phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1575
1576 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1577 break;
1578 default:
1579 break;
1580 }
1581
1582 /* Check if there was DownShift, must be checked
1583 * immediately after link-up
1584 */
1585 e1000e_check_downshift(hw);
1586
1587 /* Enable/Disable EEE after link up */
1588 if (hw->phy.type > e1000_phy_82579) {
1589 ret_val = e1000_set_eee_pchlan(hw);
1590 if (ret_val)
1591 return ret_val;
1592 }
1593
1594 /* If we are forcing speed/duplex, then we simply return since
1595 * we have already determined whether we have link or not.
1596 */
1597 if (!mac->autoneg)
1598 return -E1000_ERR_CONFIG;
1599
1600 /* Auto-Neg is enabled. Auto Speed Detection takes care
1601 * of MAC speed/duplex configuration. So we only need to
1602 * configure Collision Distance in the MAC.
1603 */
1604 mac->ops.config_collision_dist(hw);
1605
1606 /* Configure Flow Control now that Auto-Neg has completed.
1607 * First, we need to restore the desired flow control
1608 * settings because we may have had to re-autoneg with a
1609 * different link partner.
1610 */
1611 ret_val = e1000e_config_fc_after_link_up(hw);
1612 if (ret_val)
1613 e_dbg("Error configuring flow control\n");
1614
1615 return ret_val;
1616 }
1617
1618 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1619 {
1620 struct e1000_hw *hw = &adapter->hw;
1621 s32 rc;
1622
1623 rc = e1000_init_mac_params_ich8lan(hw);
1624 if (rc)
1625 return rc;
1626
1627 rc = e1000_init_nvm_params_ich8lan(hw);
1628 if (rc)
1629 return rc;
1630
1631 switch (hw->mac.type) {
1632 case e1000_ich8lan:
1633 case e1000_ich9lan:
1634 case e1000_ich10lan:
1635 rc = e1000_init_phy_params_ich8lan(hw);
1636 break;
1637 case e1000_pchlan:
1638 case e1000_pch2lan:
1639 case e1000_pch_lpt:
1640 case e1000_pch_spt:
1641 rc = e1000_init_phy_params_pchlan(hw);
1642 break;
1643 default:
1644 break;
1645 }
1646 if (rc)
1647 return rc;
1648
1649 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1650 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1651 */
1652 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1653 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1654 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1655 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1656 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1657
1658 hw->mac.ops.blink_led = NULL;
1659 }
1660
1661 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1662 (adapter->hw.phy.type != e1000_phy_ife))
1663 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1664
1665 /* Enable workaround for 82579 w/ ME enabled */
1666 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1667 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1668 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1669
1670 return 0;
1671 }
1672
1673 static DEFINE_MUTEX(nvm_mutex);
1674
1675 /**
1676 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1677 * @hw: pointer to the HW structure
1678 *
1679 * Acquires the mutex for performing NVM operations.
1680 **/
1681 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1682 {
1683 mutex_lock(&nvm_mutex);
1684
1685 return 0;
1686 }
1687
1688 /**
1689 * e1000_release_nvm_ich8lan - Release NVM mutex
1690 * @hw: pointer to the HW structure
1691 *
1692 * Releases the mutex used while performing NVM operations.
1693 **/
1694 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1695 {
1696 mutex_unlock(&nvm_mutex);
1697 }
1698
1699 /**
1700 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1701 * @hw: pointer to the HW structure
1702 *
1703 * Acquires the software control flag for performing PHY and select
1704 * MAC CSR accesses.
1705 **/
1706 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1707 {
1708 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1709 s32 ret_val = 0;
1710
1711 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1712 &hw->adapter->state)) {
1713 e_dbg("contention for Phy access\n");
1714 return -E1000_ERR_PHY;
1715 }
1716
1717 while (timeout) {
1718 extcnf_ctrl = er32(EXTCNF_CTRL);
1719 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1720 break;
1721
1722 mdelay(1);
1723 timeout--;
1724 }
1725
1726 if (!timeout) {
1727 e_dbg("SW has already locked the resource.\n");
1728 ret_val = -E1000_ERR_CONFIG;
1729 goto out;
1730 }
1731
1732 timeout = SW_FLAG_TIMEOUT;
1733
1734 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1735 ew32(EXTCNF_CTRL, extcnf_ctrl);
1736
1737 while (timeout) {
1738 extcnf_ctrl = er32(EXTCNF_CTRL);
1739 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1740 break;
1741
1742 mdelay(1);
1743 timeout--;
1744 }
1745
1746 if (!timeout) {
1747 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1748 er32(FWSM), extcnf_ctrl);
1749 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1750 ew32(EXTCNF_CTRL, extcnf_ctrl);
1751 ret_val = -E1000_ERR_CONFIG;
1752 goto out;
1753 }
1754
1755 out:
1756 if (ret_val)
1757 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1758
1759 return ret_val;
1760 }
1761
1762 /**
1763 * e1000_release_swflag_ich8lan - Release software control flag
1764 * @hw: pointer to the HW structure
1765 *
1766 * Releases the software control flag for performing PHY and select
1767 * MAC CSR accesses.
1768 **/
1769 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1770 {
1771 u32 extcnf_ctrl;
1772
1773 extcnf_ctrl = er32(EXTCNF_CTRL);
1774
1775 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1776 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1777 ew32(EXTCNF_CTRL, extcnf_ctrl);
1778 } else {
1779 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1780 }
1781
1782 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1783 }
1784
1785 /**
1786 * e1000_check_mng_mode_ich8lan - Checks management mode
1787 * @hw: pointer to the HW structure
1788 *
1789 * This checks if the adapter has any manageability enabled.
1790 * This is a function pointer entry point only called by read/write
1791 * routines for the PHY and NVM parts.
1792 **/
1793 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1794 {
1795 u32 fwsm;
1796
1797 fwsm = er32(FWSM);
1798 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1799 ((fwsm & E1000_FWSM_MODE_MASK) ==
1800 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1801 }
1802
1803 /**
1804 * e1000_check_mng_mode_pchlan - Checks management mode
1805 * @hw: pointer to the HW structure
1806 *
1807 * This checks if the adapter has iAMT enabled.
1808 * This is a function pointer entry point only called by read/write
1809 * routines for the PHY and NVM parts.
1810 **/
1811 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1812 {
1813 u32 fwsm;
1814
1815 fwsm = er32(FWSM);
1816 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1817 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1818 }
1819
1820 /**
1821 * e1000_rar_set_pch2lan - Set receive address register
1822 * @hw: pointer to the HW structure
1823 * @addr: pointer to the receive address
1824 * @index: receive address array register
1825 *
1826 * Sets the receive address array register at index to the address passed
1827 * in by addr. For 82579, RAR[0] is the base address register that is to
1828 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1829 * Use SHRA[0-3] in place of those reserved for ME.
1830 **/
1831 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1832 {
1833 u32 rar_low, rar_high;
1834
1835 /* HW expects these in little endian so we reverse the byte order
1836 * from network order (big endian) to little endian
1837 */
1838 rar_low = ((u32)addr[0] |
1839 ((u32)addr[1] << 8) |
1840 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1841
1842 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1843
1844 /* If MAC address zero, no need to set the AV bit */
1845 if (rar_low || rar_high)
1846 rar_high |= E1000_RAH_AV;
1847
1848 if (index == 0) {
1849 ew32(RAL(index), rar_low);
1850 e1e_flush();
1851 ew32(RAH(index), rar_high);
1852 e1e_flush();
1853 return 0;
1854 }
1855
1856 /* RAR[1-6] are owned by manageability. Skip those and program the
1857 * next address into the SHRA register array.
1858 */
1859 if (index < (u32)(hw->mac.rar_entry_count)) {
1860 s32 ret_val;
1861
1862 ret_val = e1000_acquire_swflag_ich8lan(hw);
1863 if (ret_val)
1864 goto out;
1865
1866 ew32(SHRAL(index - 1), rar_low);
1867 e1e_flush();
1868 ew32(SHRAH(index - 1), rar_high);
1869 e1e_flush();
1870
1871 e1000_release_swflag_ich8lan(hw);
1872
1873 /* verify the register updates */
1874 if ((er32(SHRAL(index - 1)) == rar_low) &&
1875 (er32(SHRAH(index - 1)) == rar_high))
1876 return 0;
1877
1878 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1879 (index - 1), er32(FWSM));
1880 }
1881
1882 out:
1883 e_dbg("Failed to write receive address at index %d\n", index);
1884 return -E1000_ERR_CONFIG;
1885 }
1886
1887 /**
1888 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1889 * @hw: pointer to the HW structure
1890 *
1891 * Get the number of available receive registers that the Host can
1892 * program. SHRA[0-10] are the shared receive address registers
1893 * that are shared between the Host and manageability engine (ME).
1894 * ME can reserve any number of addresses and the host needs to be
1895 * able to tell how many available registers it has access to.
1896 **/
1897 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1898 {
1899 u32 wlock_mac;
1900 u32 num_entries;
1901
1902 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1903 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1904
1905 switch (wlock_mac) {
1906 case 0:
1907 /* All SHRA[0..10] and RAR[0] available */
1908 num_entries = hw->mac.rar_entry_count;
1909 break;
1910 case 1:
1911 /* Only RAR[0] available */
1912 num_entries = 1;
1913 break;
1914 default:
1915 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1916 num_entries = wlock_mac + 1;
1917 break;
1918 }
1919
1920 return num_entries;
1921 }
1922
1923 /**
1924 * e1000_rar_set_pch_lpt - Set receive address registers
1925 * @hw: pointer to the HW structure
1926 * @addr: pointer to the receive address
1927 * @index: receive address array register
1928 *
1929 * Sets the receive address register array at index to the address passed
1930 * in by addr. For LPT, RAR[0] is the base address register that is to
1931 * contain the MAC address. SHRA[0-10] are the shared receive address
1932 * registers that are shared between the Host and manageability engine (ME).
1933 **/
1934 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1935 {
1936 u32 rar_low, rar_high;
1937 u32 wlock_mac;
1938
1939 /* HW expects these in little endian so we reverse the byte order
1940 * from network order (big endian) to little endian
1941 */
1942 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1943 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1944
1945 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1946
1947 /* If MAC address zero, no need to set the AV bit */
1948 if (rar_low || rar_high)
1949 rar_high |= E1000_RAH_AV;
1950
1951 if (index == 0) {
1952 ew32(RAL(index), rar_low);
1953 e1e_flush();
1954 ew32(RAH(index), rar_high);
1955 e1e_flush();
1956 return 0;
1957 }
1958
1959 /* The manageability engine (ME) can lock certain SHRAR registers that
1960 * it is using - those registers are unavailable for use.
1961 */
1962 if (index < hw->mac.rar_entry_count) {
1963 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1964 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1965
1966 /* Check if all SHRAR registers are locked */
1967 if (wlock_mac == 1)
1968 goto out;
1969
1970 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1971 s32 ret_val;
1972
1973 ret_val = e1000_acquire_swflag_ich8lan(hw);
1974
1975 if (ret_val)
1976 goto out;
1977
1978 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1979 e1e_flush();
1980 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1981 e1e_flush();
1982
1983 e1000_release_swflag_ich8lan(hw);
1984
1985 /* verify the register updates */
1986 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1987 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1988 return 0;
1989 }
1990 }
1991
1992 out:
1993 e_dbg("Failed to write receive address at index %d\n", index);
1994 return -E1000_ERR_CONFIG;
1995 }
1996
1997 /**
1998 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
1999 * @hw: pointer to the HW structure
2000 *
2001 * Checks if firmware is blocking the reset of the PHY.
2002 * This is a function pointer entry point only called by
2003 * reset routines.
2004 **/
2005 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2006 {
2007 bool blocked = false;
2008 int i = 0;
2009
2010 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2011 (i++ < 30))
2012 usleep_range(10000, 20000);
2013 return blocked ? E1000_BLK_PHY_RESET : 0;
2014 }
2015
2016 /**
2017 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2018 * @hw: pointer to the HW structure
2019 *
2020 * Assumes semaphore already acquired.
2021 *
2022 **/
2023 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2024 {
2025 u16 phy_data;
2026 u32 strap = er32(STRAP);
2027 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2028 E1000_STRAP_SMT_FREQ_SHIFT;
2029 s32 ret_val;
2030
2031 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2032
2033 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2034 if (ret_val)
2035 return ret_val;
2036
2037 phy_data &= ~HV_SMB_ADDR_MASK;
2038 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2039 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2040
2041 if (hw->phy.type == e1000_phy_i217) {
2042 /* Restore SMBus frequency */
2043 if (freq--) {
2044 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2045 phy_data |= (freq & (1 << 0)) <<
2046 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2047 phy_data |= (freq & (1 << 1)) <<
2048 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2049 } else {
2050 e_dbg("Unsupported SMB frequency in PHY\n");
2051 }
2052 }
2053
2054 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2055 }
2056
2057 /**
2058 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2059 * @hw: pointer to the HW structure
2060 *
2061 * SW should configure the LCD from the NVM extended configuration region
2062 * as a workaround for certain parts.
2063 **/
2064 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2065 {
2066 struct e1000_phy_info *phy = &hw->phy;
2067 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2068 s32 ret_val = 0;
2069 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2070
2071 /* Initialize the PHY from the NVM on ICH platforms. This
2072 * is needed due to an issue where the NVM configuration is
2073 * not properly autoloaded after power transitions.
2074 * Therefore, after each PHY reset, we will load the
2075 * configuration data out of the NVM manually.
2076 */
2077 switch (hw->mac.type) {
2078 case e1000_ich8lan:
2079 if (phy->type != e1000_phy_igp_3)
2080 return ret_val;
2081
2082 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2083 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2084 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2085 break;
2086 }
2087 /* Fall-thru */
2088 case e1000_pchlan:
2089 case e1000_pch2lan:
2090 case e1000_pch_lpt:
2091 case e1000_pch_spt:
2092 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2093 break;
2094 default:
2095 return ret_val;
2096 }
2097
2098 ret_val = hw->phy.ops.acquire(hw);
2099 if (ret_val)
2100 return ret_val;
2101
2102 data = er32(FEXTNVM);
2103 if (!(data & sw_cfg_mask))
2104 goto release;
2105
2106 /* Make sure HW does not configure LCD from PHY
2107 * extended configuration before SW configuration
2108 */
2109 data = er32(EXTCNF_CTRL);
2110 if ((hw->mac.type < e1000_pch2lan) &&
2111 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2112 goto release;
2113
2114 cnf_size = er32(EXTCNF_SIZE);
2115 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2116 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2117 if (!cnf_size)
2118 goto release;
2119
2120 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2121 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2122
2123 if (((hw->mac.type == e1000_pchlan) &&
2124 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2125 (hw->mac.type > e1000_pchlan)) {
2126 /* HW configures the SMBus address and LEDs when the
2127 * OEM and LCD Write Enable bits are set in the NVM.
2128 * When both NVM bits are cleared, SW will configure
2129 * them instead.
2130 */
2131 ret_val = e1000_write_smbus_addr(hw);
2132 if (ret_val)
2133 goto release;
2134
2135 data = er32(LEDCTL);
2136 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2137 (u16)data);
2138 if (ret_val)
2139 goto release;
2140 }
2141
2142 /* Configure LCD from extended configuration region. */
2143
2144 /* cnf_base_addr is in DWORD */
2145 word_addr = (u16)(cnf_base_addr << 1);
2146
2147 for (i = 0; i < cnf_size; i++) {
2148 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, &reg_data);
2149 if (ret_val)
2150 goto release;
2151
2152 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2153 1, &reg_addr);
2154 if (ret_val)
2155 goto release;
2156
2157 /* Save off the PHY page for future writes. */
2158 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2159 phy_page = reg_data;
2160 continue;
2161 }
2162
2163 reg_addr &= PHY_REG_MASK;
2164 reg_addr |= phy_page;
2165
2166 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2167 if (ret_val)
2168 goto release;
2169 }
2170
2171 release:
2172 hw->phy.ops.release(hw);
2173 return ret_val;
2174 }
2175
2176 /**
2177 * e1000_k1_gig_workaround_hv - K1 Si workaround
2178 * @hw: pointer to the HW structure
2179 * @link: link up bool flag
2180 *
2181 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2182 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2183 * If link is down, the function will restore the default K1 setting located
2184 * in the NVM.
2185 **/
2186 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2187 {
2188 s32 ret_val = 0;
2189 u16 status_reg = 0;
2190 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2191
2192 if (hw->mac.type != e1000_pchlan)
2193 return 0;
2194
2195 /* Wrap the whole flow with the sw flag */
2196 ret_val = hw->phy.ops.acquire(hw);
2197 if (ret_val)
2198 return ret_val;
2199
2200 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2201 if (link) {
2202 if (hw->phy.type == e1000_phy_82578) {
2203 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2204 &status_reg);
2205 if (ret_val)
2206 goto release;
2207
2208 status_reg &= (BM_CS_STATUS_LINK_UP |
2209 BM_CS_STATUS_RESOLVED |
2210 BM_CS_STATUS_SPEED_MASK);
2211
2212 if (status_reg == (BM_CS_STATUS_LINK_UP |
2213 BM_CS_STATUS_RESOLVED |
2214 BM_CS_STATUS_SPEED_1000))
2215 k1_enable = false;
2216 }
2217
2218 if (hw->phy.type == e1000_phy_82577) {
2219 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2220 if (ret_val)
2221 goto release;
2222
2223 status_reg &= (HV_M_STATUS_LINK_UP |
2224 HV_M_STATUS_AUTONEG_COMPLETE |
2225 HV_M_STATUS_SPEED_MASK);
2226
2227 if (status_reg == (HV_M_STATUS_LINK_UP |
2228 HV_M_STATUS_AUTONEG_COMPLETE |
2229 HV_M_STATUS_SPEED_1000))
2230 k1_enable = false;
2231 }
2232
2233 /* Link stall fix for link up */
2234 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2235 if (ret_val)
2236 goto release;
2237
2238 } else {
2239 /* Link stall fix for link down */
2240 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2241 if (ret_val)
2242 goto release;
2243 }
2244
2245 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2246
2247 release:
2248 hw->phy.ops.release(hw);
2249
2250 return ret_val;
2251 }
2252
2253 /**
2254 * e1000_configure_k1_ich8lan - Configure K1 power state
2255 * @hw: pointer to the HW structure
2256 * @enable: K1 state to configure
2257 *
2258 * Configure the K1 power state based on the provided parameter.
2259 * Assumes semaphore already acquired.
2260 *
2261 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2262 **/
2263 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2264 {
2265 s32 ret_val;
2266 u32 ctrl_reg = 0;
2267 u32 ctrl_ext = 0;
2268 u32 reg = 0;
2269 u16 kmrn_reg = 0;
2270
2271 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2272 &kmrn_reg);
2273 if (ret_val)
2274 return ret_val;
2275
2276 if (k1_enable)
2277 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2278 else
2279 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2280
2281 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2282 kmrn_reg);
2283 if (ret_val)
2284 return ret_val;
2285
2286 usleep_range(20, 40);
2287 ctrl_ext = er32(CTRL_EXT);
2288 ctrl_reg = er32(CTRL);
2289
2290 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2291 reg |= E1000_CTRL_FRCSPD;
2292 ew32(CTRL, reg);
2293
2294 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2295 e1e_flush();
2296 usleep_range(20, 40);
2297 ew32(CTRL, ctrl_reg);
2298 ew32(CTRL_EXT, ctrl_ext);
2299 e1e_flush();
2300 usleep_range(20, 40);
2301
2302 return 0;
2303 }
2304
2305 /**
2306 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2307 * @hw: pointer to the HW structure
2308 * @d0_state: boolean if entering d0 or d3 device state
2309 *
2310 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2311 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2312 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2313 **/
2314 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2315 {
2316 s32 ret_val = 0;
2317 u32 mac_reg;
2318 u16 oem_reg;
2319
2320 if (hw->mac.type < e1000_pchlan)
2321 return ret_val;
2322
2323 ret_val = hw->phy.ops.acquire(hw);
2324 if (ret_val)
2325 return ret_val;
2326
2327 if (hw->mac.type == e1000_pchlan) {
2328 mac_reg = er32(EXTCNF_CTRL);
2329 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2330 goto release;
2331 }
2332
2333 mac_reg = er32(FEXTNVM);
2334 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2335 goto release;
2336
2337 mac_reg = er32(PHY_CTRL);
2338
2339 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2340 if (ret_val)
2341 goto release;
2342
2343 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2344
2345 if (d0_state) {
2346 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2347 oem_reg |= HV_OEM_BITS_GBE_DIS;
2348
2349 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2350 oem_reg |= HV_OEM_BITS_LPLU;
2351 } else {
2352 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2353 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2354 oem_reg |= HV_OEM_BITS_GBE_DIS;
2355
2356 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2357 E1000_PHY_CTRL_NOND0A_LPLU))
2358 oem_reg |= HV_OEM_BITS_LPLU;
2359 }
2360
2361 /* Set Restart auto-neg to activate the bits */
2362 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2363 !hw->phy.ops.check_reset_block(hw))
2364 oem_reg |= HV_OEM_BITS_RESTART_AN;
2365
2366 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2367
2368 release:
2369 hw->phy.ops.release(hw);
2370
2371 return ret_val;
2372 }
2373
2374 /**
2375 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2376 * @hw: pointer to the HW structure
2377 **/
2378 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2379 {
2380 s32 ret_val;
2381 u16 data;
2382
2383 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2384 if (ret_val)
2385 return ret_val;
2386
2387 data |= HV_KMRN_MDIO_SLOW;
2388
2389 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2390
2391 return ret_val;
2392 }
2393
2394 /**
2395 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2396 * done after every PHY reset.
2397 **/
2398 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2399 {
2400 s32 ret_val = 0;
2401 u16 phy_data;
2402
2403 if (hw->mac.type != e1000_pchlan)
2404 return 0;
2405
2406 /* Set MDIO slow mode before any other MDIO access */
2407 if (hw->phy.type == e1000_phy_82577) {
2408 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2409 if (ret_val)
2410 return ret_val;
2411 }
2412
2413 if (((hw->phy.type == e1000_phy_82577) &&
2414 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2415 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2416 /* Disable generation of early preamble */
2417 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2418 if (ret_val)
2419 return ret_val;
2420
2421 /* Preamble tuning for SSC */
2422 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2423 if (ret_val)
2424 return ret_val;
2425 }
2426
2427 if (hw->phy.type == e1000_phy_82578) {
2428 /* Return registers to default by doing a soft reset then
2429 * writing 0x3140 to the control register.
2430 */
2431 if (hw->phy.revision < 2) {
2432 e1000e_phy_sw_reset(hw);
2433 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2434 }
2435 }
2436
2437 /* Select page 0 */
2438 ret_val = hw->phy.ops.acquire(hw);
2439 if (ret_val)
2440 return ret_val;
2441
2442 hw->phy.addr = 1;
2443 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2444 hw->phy.ops.release(hw);
2445 if (ret_val)
2446 return ret_val;
2447
2448 /* Configure the K1 Si workaround during phy reset assuming there is
2449 * link so that it disables K1 if link is in 1Gbps.
2450 */
2451 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2452 if (ret_val)
2453 return ret_val;
2454
2455 /* Workaround for link disconnects on a busy hub in half duplex */
2456 ret_val = hw->phy.ops.acquire(hw);
2457 if (ret_val)
2458 return ret_val;
2459 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2460 if (ret_val)
2461 goto release;
2462 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2463 if (ret_val)
2464 goto release;
2465
2466 /* set MSE higher to enable link to stay up when noise is high */
2467 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2468 release:
2469 hw->phy.ops.release(hw);
2470
2471 return ret_val;
2472 }
2473
2474 /**
2475 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2476 * @hw: pointer to the HW structure
2477 **/
2478 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2479 {
2480 u32 mac_reg;
2481 u16 i, phy_reg = 0;
2482 s32 ret_val;
2483
2484 ret_val = hw->phy.ops.acquire(hw);
2485 if (ret_val)
2486 return;
2487 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2488 if (ret_val)
2489 goto release;
2490
2491 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2492 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2493 mac_reg = er32(RAL(i));
2494 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2495 (u16)(mac_reg & 0xFFFF));
2496 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2497 (u16)((mac_reg >> 16) & 0xFFFF));
2498
2499 mac_reg = er32(RAH(i));
2500 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2501 (u16)(mac_reg & 0xFFFF));
2502 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2503 (u16)((mac_reg & E1000_RAH_AV)
2504 >> 16));
2505 }
2506
2507 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2508
2509 release:
2510 hw->phy.ops.release(hw);
2511 }
2512
2513 /**
2514 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2515 * with 82579 PHY
2516 * @hw: pointer to the HW structure
2517 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2518 **/
2519 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2520 {
2521 s32 ret_val = 0;
2522 u16 phy_reg, data;
2523 u32 mac_reg;
2524 u16 i;
2525
2526 if (hw->mac.type < e1000_pch2lan)
2527 return 0;
2528
2529 /* disable Rx path while enabling/disabling workaround */
2530 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2531 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
2532 if (ret_val)
2533 return ret_val;
2534
2535 if (enable) {
2536 /* Write Rx addresses (rar_entry_count for RAL/H, and
2537 * SHRAL/H) and initial CRC values to the MAC
2538 */
2539 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2540 u8 mac_addr[ETH_ALEN] = { 0 };
2541 u32 addr_high, addr_low;
2542
2543 addr_high = er32(RAH(i));
2544 if (!(addr_high & E1000_RAH_AV))
2545 continue;
2546 addr_low = er32(RAL(i));
2547 mac_addr[0] = (addr_low & 0xFF);
2548 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2549 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2550 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2551 mac_addr[4] = (addr_high & 0xFF);
2552 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2553
2554 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2555 }
2556
2557 /* Write Rx addresses to the PHY */
2558 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2559
2560 /* Enable jumbo frame workaround in the MAC */
2561 mac_reg = er32(FFLT_DBG);
2562 mac_reg &= ~(1 << 14);
2563 mac_reg |= (7 << 15);
2564 ew32(FFLT_DBG, mac_reg);
2565
2566 mac_reg = er32(RCTL);
2567 mac_reg |= E1000_RCTL_SECRC;
2568 ew32(RCTL, mac_reg);
2569
2570 ret_val = e1000e_read_kmrn_reg(hw,
2571 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2572 &data);
2573 if (ret_val)
2574 return ret_val;
2575 ret_val = e1000e_write_kmrn_reg(hw,
2576 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2577 data | (1 << 0));
2578 if (ret_val)
2579 return ret_val;
2580 ret_val = e1000e_read_kmrn_reg(hw,
2581 E1000_KMRNCTRLSTA_HD_CTRL,
2582 &data);
2583 if (ret_val)
2584 return ret_val;
2585 data &= ~(0xF << 8);
2586 data |= (0xB << 8);
2587 ret_val = e1000e_write_kmrn_reg(hw,
2588 E1000_KMRNCTRLSTA_HD_CTRL,
2589 data);
2590 if (ret_val)
2591 return ret_val;
2592
2593 /* Enable jumbo frame workaround in the PHY */
2594 e1e_rphy(hw, PHY_REG(769, 23), &data);
2595 data &= ~(0x7F << 5);
2596 data |= (0x37 << 5);
2597 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2598 if (ret_val)
2599 return ret_val;
2600 e1e_rphy(hw, PHY_REG(769, 16), &data);
2601 data &= ~(1 << 13);
2602 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2603 if (ret_val)
2604 return ret_val;
2605 e1e_rphy(hw, PHY_REG(776, 20), &data);
2606 data &= ~(0x3FF << 2);
2607 data |= (E1000_TX_PTR_GAP << 2);
2608 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2609 if (ret_val)
2610 return ret_val;
2611 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2612 if (ret_val)
2613 return ret_val;
2614 e1e_rphy(hw, HV_PM_CTRL, &data);
2615 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
2616 if (ret_val)
2617 return ret_val;
2618 } else {
2619 /* Write MAC register values back to h/w defaults */
2620 mac_reg = er32(FFLT_DBG);
2621 mac_reg &= ~(0xF << 14);
2622 ew32(FFLT_DBG, mac_reg);
2623
2624 mac_reg = er32(RCTL);
2625 mac_reg &= ~E1000_RCTL_SECRC;
2626 ew32(RCTL, mac_reg);
2627
2628 ret_val = e1000e_read_kmrn_reg(hw,
2629 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2630 &data);
2631 if (ret_val)
2632 return ret_val;
2633 ret_val = e1000e_write_kmrn_reg(hw,
2634 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2635 data & ~(1 << 0));
2636 if (ret_val)
2637 return ret_val;
2638 ret_val = e1000e_read_kmrn_reg(hw,
2639 E1000_KMRNCTRLSTA_HD_CTRL,
2640 &data);
2641 if (ret_val)
2642 return ret_val;
2643 data &= ~(0xF << 8);
2644 data |= (0xB << 8);
2645 ret_val = e1000e_write_kmrn_reg(hw,
2646 E1000_KMRNCTRLSTA_HD_CTRL,
2647 data);
2648 if (ret_val)
2649 return ret_val;
2650
2651 /* Write PHY register values back to h/w defaults */
2652 e1e_rphy(hw, PHY_REG(769, 23), &data);
2653 data &= ~(0x7F << 5);
2654 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2655 if (ret_val)
2656 return ret_val;
2657 e1e_rphy(hw, PHY_REG(769, 16), &data);
2658 data |= (1 << 13);
2659 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2660 if (ret_val)
2661 return ret_val;
2662 e1e_rphy(hw, PHY_REG(776, 20), &data);
2663 data &= ~(0x3FF << 2);
2664 data |= (0x8 << 2);
2665 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2666 if (ret_val)
2667 return ret_val;
2668 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2669 if (ret_val)
2670 return ret_val;
2671 e1e_rphy(hw, HV_PM_CTRL, &data);
2672 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
2673 if (ret_val)
2674 return ret_val;
2675 }
2676
2677 /* re-enable Rx path after enabling/disabling workaround */
2678 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
2679 }
2680
2681 /**
2682 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2683 * done after every PHY reset.
2684 **/
2685 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2686 {
2687 s32 ret_val = 0;
2688
2689 if (hw->mac.type != e1000_pch2lan)
2690 return 0;
2691
2692 /* Set MDIO slow mode before any other MDIO access */
2693 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2694 if (ret_val)
2695 return ret_val;
2696
2697 ret_val = hw->phy.ops.acquire(hw);
2698 if (ret_val)
2699 return ret_val;
2700 /* set MSE higher to enable link to stay up when noise is high */
2701 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2702 if (ret_val)
2703 goto release;
2704 /* drop link after 5 times MSE threshold was reached */
2705 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2706 release:
2707 hw->phy.ops.release(hw);
2708
2709 return ret_val;
2710 }
2711
2712 /**
2713 * e1000_k1_gig_workaround_lv - K1 Si workaround
2714 * @hw: pointer to the HW structure
2715 *
2716 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2717 * Disable K1 in 1000Mbps and 100Mbps
2718 **/
2719 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2720 {
2721 s32 ret_val = 0;
2722 u16 status_reg = 0;
2723
2724 if (hw->mac.type != e1000_pch2lan)
2725 return 0;
2726
2727 /* Set K1 beacon duration based on 10Mbs speed */
2728 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2729 if (ret_val)
2730 return ret_val;
2731
2732 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2733 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2734 if (status_reg &
2735 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2736 u16 pm_phy_reg;
2737
2738 /* LV 1G/100 Packet drop issue wa */
2739 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2740 if (ret_val)
2741 return ret_val;
2742 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2743 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2744 if (ret_val)
2745 return ret_val;
2746 } else {
2747 u32 mac_reg;
2748
2749 mac_reg = er32(FEXTNVM4);
2750 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2751 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2752 ew32(FEXTNVM4, mac_reg);
2753 }
2754 }
2755
2756 return ret_val;
2757 }
2758
2759 /**
2760 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2761 * @hw: pointer to the HW structure
2762 * @gate: boolean set to true to gate, false to ungate
2763 *
2764 * Gate/ungate the automatic PHY configuration via hardware; perform
2765 * the configuration via software instead.
2766 **/
2767 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2768 {
2769 u32 extcnf_ctrl;
2770
2771 if (hw->mac.type < e1000_pch2lan)
2772 return;
2773
2774 extcnf_ctrl = er32(EXTCNF_CTRL);
2775
2776 if (gate)
2777 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2778 else
2779 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2780
2781 ew32(EXTCNF_CTRL, extcnf_ctrl);
2782 }
2783
2784 /**
2785 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2786 * @hw: pointer to the HW structure
2787 *
2788 * Check the appropriate indication the MAC has finished configuring the
2789 * PHY after a software reset.
2790 **/
2791 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2792 {
2793 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2794
2795 /* Wait for basic configuration completes before proceeding */
2796 do {
2797 data = er32(STATUS);
2798 data &= E1000_STATUS_LAN_INIT_DONE;
2799 usleep_range(100, 200);
2800 } while ((!data) && --loop);
2801
2802 /* If basic configuration is incomplete before the above loop
2803 * count reaches 0, loading the configuration from NVM will
2804 * leave the PHY in a bad state possibly resulting in no link.
2805 */
2806 if (loop == 0)
2807 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2808
2809 /* Clear the Init Done bit for the next init event */
2810 data = er32(STATUS);
2811 data &= ~E1000_STATUS_LAN_INIT_DONE;
2812 ew32(STATUS, data);
2813 }
2814
2815 /**
2816 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2817 * @hw: pointer to the HW structure
2818 **/
2819 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2820 {
2821 s32 ret_val = 0;
2822 u16 reg;
2823
2824 if (hw->phy.ops.check_reset_block(hw))
2825 return 0;
2826
2827 /* Allow time for h/w to get to quiescent state after reset */
2828 usleep_range(10000, 20000);
2829
2830 /* Perform any necessary post-reset workarounds */
2831 switch (hw->mac.type) {
2832 case e1000_pchlan:
2833 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2834 if (ret_val)
2835 return ret_val;
2836 break;
2837 case e1000_pch2lan:
2838 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2839 if (ret_val)
2840 return ret_val;
2841 break;
2842 default:
2843 break;
2844 }
2845
2846 /* Clear the host wakeup bit after lcd reset */
2847 if (hw->mac.type >= e1000_pchlan) {
2848 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
2849 reg &= ~BM_WUC_HOST_WU_BIT;
2850 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2851 }
2852
2853 /* Configure the LCD with the extended configuration region in NVM */
2854 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2855 if (ret_val)
2856 return ret_val;
2857
2858 /* Configure the LCD with the OEM bits in NVM */
2859 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2860
2861 if (hw->mac.type == e1000_pch2lan) {
2862 /* Ungate automatic PHY configuration on non-managed 82579 */
2863 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2864 usleep_range(10000, 20000);
2865 e1000_gate_hw_phy_config_ich8lan(hw, false);
2866 }
2867
2868 /* Set EEE LPI Update Timer to 200usec */
2869 ret_val = hw->phy.ops.acquire(hw);
2870 if (ret_val)
2871 return ret_val;
2872 ret_val = e1000_write_emi_reg_locked(hw,
2873 I82579_LPI_UPDATE_TIMER,
2874 0x1387);
2875 hw->phy.ops.release(hw);
2876 }
2877
2878 return ret_val;
2879 }
2880
2881 /**
2882 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2883 * @hw: pointer to the HW structure
2884 *
2885 * Resets the PHY
2886 * This is a function pointer entry point called by drivers
2887 * or other shared routines.
2888 **/
2889 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2890 {
2891 s32 ret_val = 0;
2892
2893 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2894 if ((hw->mac.type == e1000_pch2lan) &&
2895 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2896 e1000_gate_hw_phy_config_ich8lan(hw, true);
2897
2898 ret_val = e1000e_phy_hw_reset_generic(hw);
2899 if (ret_val)
2900 return ret_val;
2901
2902 return e1000_post_phy_reset_ich8lan(hw);
2903 }
2904
2905 /**
2906 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2907 * @hw: pointer to the HW structure
2908 * @active: true to enable LPLU, false to disable
2909 *
2910 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2911 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2912 * the phy speed. This function will manually set the LPLU bit and restart
2913 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2914 * since it configures the same bit.
2915 **/
2916 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2917 {
2918 s32 ret_val;
2919 u16 oem_reg;
2920
2921 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2922 if (ret_val)
2923 return ret_val;
2924
2925 if (active)
2926 oem_reg |= HV_OEM_BITS_LPLU;
2927 else
2928 oem_reg &= ~HV_OEM_BITS_LPLU;
2929
2930 if (!hw->phy.ops.check_reset_block(hw))
2931 oem_reg |= HV_OEM_BITS_RESTART_AN;
2932
2933 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2934 }
2935
2936 /**
2937 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2938 * @hw: pointer to the HW structure
2939 * @active: true to enable LPLU, false to disable
2940 *
2941 * Sets the LPLU D0 state according to the active flag. When
2942 * activating LPLU this function also disables smart speed
2943 * and vice versa. LPLU will not be activated unless the
2944 * device autonegotiation advertisement meets standards of
2945 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2946 * This is a function pointer entry point only called by
2947 * PHY setup routines.
2948 **/
2949 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2950 {
2951 struct e1000_phy_info *phy = &hw->phy;
2952 u32 phy_ctrl;
2953 s32 ret_val = 0;
2954 u16 data;
2955
2956 if (phy->type == e1000_phy_ife)
2957 return 0;
2958
2959 phy_ctrl = er32(PHY_CTRL);
2960
2961 if (active) {
2962 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2963 ew32(PHY_CTRL, phy_ctrl);
2964
2965 if (phy->type != e1000_phy_igp_3)
2966 return 0;
2967
2968 /* Call gig speed drop workaround on LPLU before accessing
2969 * any PHY registers
2970 */
2971 if (hw->mac.type == e1000_ich8lan)
2972 e1000e_gig_downshift_workaround_ich8lan(hw);
2973
2974 /* When LPLU is enabled, we should disable SmartSpeed */
2975 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2976 if (ret_val)
2977 return ret_val;
2978 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2979 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2980 if (ret_val)
2981 return ret_val;
2982 } else {
2983 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2984 ew32(PHY_CTRL, phy_ctrl);
2985
2986 if (phy->type != e1000_phy_igp_3)
2987 return 0;
2988
2989 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2990 * during Dx states where the power conservation is most
2991 * important. During driver activity we should enable
2992 * SmartSpeed, so performance is maintained.
2993 */
2994 if (phy->smart_speed == e1000_smart_speed_on) {
2995 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2996 &data);
2997 if (ret_val)
2998 return ret_val;
2999
3000 data |= IGP01E1000_PSCFR_SMART_SPEED;
3001 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3002 data);
3003 if (ret_val)
3004 return ret_val;
3005 } else if (phy->smart_speed == e1000_smart_speed_off) {
3006 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3007 &data);
3008 if (ret_val)
3009 return ret_val;
3010
3011 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3012 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3013 data);
3014 if (ret_val)
3015 return ret_val;
3016 }
3017 }
3018
3019 return 0;
3020 }
3021
3022 /**
3023 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3024 * @hw: pointer to the HW structure
3025 * @active: true to enable LPLU, false to disable
3026 *
3027 * Sets the LPLU D3 state according to the active flag. When
3028 * activating LPLU this function also disables smart speed
3029 * and vice versa. LPLU will not be activated unless the
3030 * device autonegotiation advertisement meets standards of
3031 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3032 * This is a function pointer entry point only called by
3033 * PHY setup routines.
3034 **/
3035 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3036 {
3037 struct e1000_phy_info *phy = &hw->phy;
3038 u32 phy_ctrl;
3039 s32 ret_val = 0;
3040 u16 data;
3041
3042 phy_ctrl = er32(PHY_CTRL);
3043
3044 if (!active) {
3045 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3046 ew32(PHY_CTRL, phy_ctrl);
3047
3048 if (phy->type != e1000_phy_igp_3)
3049 return 0;
3050
3051 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3052 * during Dx states where the power conservation is most
3053 * important. During driver activity we should enable
3054 * SmartSpeed, so performance is maintained.
3055 */
3056 if (phy->smart_speed == e1000_smart_speed_on) {
3057 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3058 &data);
3059 if (ret_val)
3060 return ret_val;
3061
3062 data |= IGP01E1000_PSCFR_SMART_SPEED;
3063 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3064 data);
3065 if (ret_val)
3066 return ret_val;
3067 } else if (phy->smart_speed == e1000_smart_speed_off) {
3068 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3069 &data);
3070 if (ret_val)
3071 return ret_val;
3072
3073 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3074 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3075 data);
3076 if (ret_val)
3077 return ret_val;
3078 }
3079 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3080 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3081 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3082 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3083 ew32(PHY_CTRL, phy_ctrl);
3084
3085 if (phy->type != e1000_phy_igp_3)
3086 return 0;
3087
3088 /* Call gig speed drop workaround on LPLU before accessing
3089 * any PHY registers
3090 */
3091 if (hw->mac.type == e1000_ich8lan)
3092 e1000e_gig_downshift_workaround_ich8lan(hw);
3093
3094 /* When LPLU is enabled, we should disable SmartSpeed */
3095 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3096 if (ret_val)
3097 return ret_val;
3098
3099 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3100 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3101 }
3102
3103 return ret_val;
3104 }
3105
3106 /**
3107 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3108 * @hw: pointer to the HW structure
3109 * @bank: pointer to the variable that returns the active bank
3110 *
3111 * Reads signature byte from the NVM using the flash access registers.
3112 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3113 **/
3114 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3115 {
3116 u32 eecd;
3117 struct e1000_nvm_info *nvm = &hw->nvm;
3118 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3119 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3120 u32 nvm_dword = 0;
3121 u8 sig_byte = 0;
3122 s32 ret_val;
3123
3124 switch (hw->mac.type) {
3125 case e1000_pch_spt:
3126 bank1_offset = nvm->flash_bank_size;
3127 act_offset = E1000_ICH_NVM_SIG_WORD;
3128
3129 /* set bank to 0 in case flash read fails */
3130 *bank = 0;
3131
3132 /* Check bank 0 */
3133 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3134 &nvm_dword);
3135 if (ret_val)
3136 return ret_val;
3137 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3138 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3139 E1000_ICH_NVM_SIG_VALUE) {
3140 *bank = 0;
3141 return 0;
3142 }
3143
3144 /* Check bank 1 */
3145 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3146 bank1_offset,
3147 &nvm_dword);
3148 if (ret_val)
3149 return ret_val;
3150 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3151 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3152 E1000_ICH_NVM_SIG_VALUE) {
3153 *bank = 1;
3154 return 0;
3155 }
3156
3157 e_dbg("ERROR: No valid NVM bank present\n");
3158 return -E1000_ERR_NVM;
3159 case e1000_ich8lan:
3160 case e1000_ich9lan:
3161 eecd = er32(EECD);
3162 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3163 E1000_EECD_SEC1VAL_VALID_MASK) {
3164 if (eecd & E1000_EECD_SEC1VAL)
3165 *bank = 1;
3166 else
3167 *bank = 0;
3168
3169 return 0;
3170 }
3171 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3172 /* fall-thru */
3173 default:
3174 /* set bank to 0 in case flash read fails */
3175 *bank = 0;
3176
3177 /* Check bank 0 */
3178 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3179 &sig_byte);
3180 if (ret_val)
3181 return ret_val;
3182 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3183 E1000_ICH_NVM_SIG_VALUE) {
3184 *bank = 0;
3185 return 0;
3186 }
3187
3188 /* Check bank 1 */
3189 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3190 bank1_offset,
3191 &sig_byte);
3192 if (ret_val)
3193 return ret_val;
3194 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3195 E1000_ICH_NVM_SIG_VALUE) {
3196 *bank = 1;
3197 return 0;
3198 }
3199
3200 e_dbg("ERROR: No valid NVM bank present\n");
3201 return -E1000_ERR_NVM;
3202 }
3203 }
3204
3205 /**
3206 * e1000_read_nvm_spt - NVM access for SPT
3207 * @hw: pointer to the HW structure
3208 * @offset: The offset (in bytes) of the word(s) to read.
3209 * @words: Size of data to read in words.
3210 * @data: pointer to the word(s) to read at offset.
3211 *
3212 * Reads a word(s) from the NVM
3213 **/
3214 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3215 u16 *data)
3216 {
3217 struct e1000_nvm_info *nvm = &hw->nvm;
3218 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3219 u32 act_offset;
3220 s32 ret_val = 0;
3221 u32 bank = 0;
3222 u32 dword = 0;
3223 u16 offset_to_read;
3224 u16 i;
3225
3226 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3227 (words == 0)) {
3228 e_dbg("nvm parameter(s) out of bounds\n");
3229 ret_val = -E1000_ERR_NVM;
3230 goto out;
3231 }
3232
3233 nvm->ops.acquire(hw);
3234
3235 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3236 if (ret_val) {
3237 e_dbg("Could not detect valid bank, assuming bank 0\n");
3238 bank = 0;
3239 }
3240
3241 act_offset = (bank) ? nvm->flash_bank_size : 0;
3242 act_offset += offset;
3243
3244 ret_val = 0;
3245
3246 for (i = 0; i < words; i += 2) {
3247 if (words - i == 1) {
3248 if (dev_spec->shadow_ram[offset + i].modified) {
3249 data[i] =
3250 dev_spec->shadow_ram[offset + i].value;
3251 } else {
3252 offset_to_read = act_offset + i -
3253 ((act_offset + i) % 2);
3254 ret_val =
3255 e1000_read_flash_dword_ich8lan(hw,
3256 offset_to_read,
3257 &dword);
3258 if (ret_val)
3259 break;
3260 if ((act_offset + i) % 2 == 0)
3261 data[i] = (u16)(dword & 0xFFFF);
3262 else
3263 data[i] = (u16)((dword >> 16) & 0xFFFF);
3264 }
3265 } else {
3266 offset_to_read = act_offset + i;
3267 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3268 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3269 ret_val =
3270 e1000_read_flash_dword_ich8lan(hw,
3271 offset_to_read,
3272 &dword);
3273 if (ret_val)
3274 break;
3275 }
3276 if (dev_spec->shadow_ram[offset + i].modified)
3277 data[i] =
3278 dev_spec->shadow_ram[offset + i].value;
3279 else
3280 data[i] = (u16)(dword & 0xFFFF);
3281 if (dev_spec->shadow_ram[offset + i].modified)
3282 data[i + 1] =
3283 dev_spec->shadow_ram[offset + i + 1].value;
3284 else
3285 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3286 }
3287 }
3288
3289 nvm->ops.release(hw);
3290
3291 out:
3292 if (ret_val)
3293 e_dbg("NVM read error: %d\n", ret_val);
3294
3295 return ret_val;
3296 }
3297
3298 /**
3299 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3300 * @hw: pointer to the HW structure
3301 * @offset: The offset (in bytes) of the word(s) to read.
3302 * @words: Size of data to read in words
3303 * @data: Pointer to the word(s) to read at offset.
3304 *
3305 * Reads a word(s) from the NVM using the flash access registers.
3306 **/
3307 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3308 u16 *data)
3309 {
3310 struct e1000_nvm_info *nvm = &hw->nvm;
3311 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3312 u32 act_offset;
3313 s32 ret_val = 0;
3314 u32 bank = 0;
3315 u16 i, word;
3316
3317 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3318 (words == 0)) {
3319 e_dbg("nvm parameter(s) out of bounds\n");
3320 ret_val = -E1000_ERR_NVM;
3321 goto out;
3322 }
3323
3324 nvm->ops.acquire(hw);
3325
3326 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3327 if (ret_val) {
3328 e_dbg("Could not detect valid bank, assuming bank 0\n");
3329 bank = 0;
3330 }
3331
3332 act_offset = (bank) ? nvm->flash_bank_size : 0;
3333 act_offset += offset;
3334
3335 ret_val = 0;
3336 for (i = 0; i < words; i++) {
3337 if (dev_spec->shadow_ram[offset + i].modified) {
3338 data[i] = dev_spec->shadow_ram[offset + i].value;
3339 } else {
3340 ret_val = e1000_read_flash_word_ich8lan(hw,
3341 act_offset + i,
3342 &word);
3343 if (ret_val)
3344 break;
3345 data[i] = word;
3346 }
3347 }
3348
3349 nvm->ops.release(hw);
3350
3351 out:
3352 if (ret_val)
3353 e_dbg("NVM read error: %d\n", ret_val);
3354
3355 return ret_val;
3356 }
3357
3358 /**
3359 * e1000_flash_cycle_init_ich8lan - Initialize flash
3360 * @hw: pointer to the HW structure
3361 *
3362 * This function does initial flash setup so that a new read/write/erase cycle
3363 * can be started.
3364 **/
3365 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3366 {
3367 union ich8_hws_flash_status hsfsts;
3368 s32 ret_val = -E1000_ERR_NVM;
3369
3370 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3371
3372 /* Check if the flash descriptor is valid */
3373 if (!hsfsts.hsf_status.fldesvalid) {
3374 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3375 return -E1000_ERR_NVM;
3376 }
3377
3378 /* Clear FCERR and DAEL in hw status by writing 1 */
3379 hsfsts.hsf_status.flcerr = 1;
3380 hsfsts.hsf_status.dael = 1;
3381 if (hw->mac.type == e1000_pch_spt)
3382 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3383 else
3384 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3385
3386 /* Either we should have a hardware SPI cycle in progress
3387 * bit to check against, in order to start a new cycle or
3388 * FDONE bit should be changed in the hardware so that it
3389 * is 1 after hardware reset, which can then be used as an
3390 * indication whether a cycle is in progress or has been
3391 * completed.
3392 */
3393
3394 if (!hsfsts.hsf_status.flcinprog) {
3395 /* There is no cycle running at present,
3396 * so we can start a cycle.
3397 * Begin by setting Flash Cycle Done.
3398 */
3399 hsfsts.hsf_status.flcdone = 1;
3400 if (hw->mac.type == e1000_pch_spt)
3401 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3402 else
3403 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3404 ret_val = 0;
3405 } else {
3406 s32 i;
3407
3408 /* Otherwise poll for sometime so the current
3409 * cycle has a chance to end before giving up.
3410 */
3411 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3412 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3413 if (!hsfsts.hsf_status.flcinprog) {
3414 ret_val = 0;
3415 break;
3416 }
3417 udelay(1);
3418 }
3419 if (!ret_val) {
3420 /* Successful in waiting for previous cycle to timeout,
3421 * now set the Flash Cycle Done.
3422 */
3423 hsfsts.hsf_status.flcdone = 1;
3424 if (hw->mac.type == e1000_pch_spt)
3425 ew32flash(ICH_FLASH_HSFSTS,
3426 hsfsts.regval & 0xFFFF);
3427 else
3428 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3429 } else {
3430 e_dbg("Flash controller busy, cannot get access\n");
3431 }
3432 }
3433
3434 return ret_val;
3435 }
3436
3437 /**
3438 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3439 * @hw: pointer to the HW structure
3440 * @timeout: maximum time to wait for completion
3441 *
3442 * This function starts a flash cycle and waits for its completion.
3443 **/
3444 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3445 {
3446 union ich8_hws_flash_ctrl hsflctl;
3447 union ich8_hws_flash_status hsfsts;
3448 u32 i = 0;
3449
3450 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3451 if (hw->mac.type == e1000_pch_spt)
3452 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3453 else
3454 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3455 hsflctl.hsf_ctrl.flcgo = 1;
3456
3457 if (hw->mac.type == e1000_pch_spt)
3458 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3459 else
3460 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3461
3462 /* wait till FDONE bit is set to 1 */
3463 do {
3464 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3465 if (hsfsts.hsf_status.flcdone)
3466 break;
3467 udelay(1);
3468 } while (i++ < timeout);
3469
3470 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3471 return 0;
3472
3473 return -E1000_ERR_NVM;
3474 }
3475
3476 /**
3477 * e1000_read_flash_dword_ich8lan - Read dword from flash
3478 * @hw: pointer to the HW structure
3479 * @offset: offset to data location
3480 * @data: pointer to the location for storing the data
3481 *
3482 * Reads the flash dword at offset into data. Offset is converted
3483 * to bytes before read.
3484 **/
3485 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3486 u32 *data)
3487 {
3488 /* Must convert word offset into bytes. */
3489 offset <<= 1;
3490 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3491 }
3492
3493 /**
3494 * e1000_read_flash_word_ich8lan - Read word from flash
3495 * @hw: pointer to the HW structure
3496 * @offset: offset to data location
3497 * @data: pointer to the location for storing the data
3498 *
3499 * Reads the flash word at offset into data. Offset is converted
3500 * to bytes before read.
3501 **/
3502 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3503 u16 *data)
3504 {
3505 /* Must convert offset into bytes. */
3506 offset <<= 1;
3507
3508 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3509 }
3510
3511 /**
3512 * e1000_read_flash_byte_ich8lan - Read byte from flash
3513 * @hw: pointer to the HW structure
3514 * @offset: The offset of the byte to read.
3515 * @data: Pointer to a byte to store the value read.
3516 *
3517 * Reads a single byte from the NVM using the flash access registers.
3518 **/
3519 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3520 u8 *data)
3521 {
3522 s32 ret_val;
3523 u16 word = 0;
3524
3525 /* In SPT, only 32 bits access is supported,
3526 * so this function should not be called.
3527 */
3528 if (hw->mac.type == e1000_pch_spt)
3529 return -E1000_ERR_NVM;
3530 else
3531 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3532
3533 if (ret_val)
3534 return ret_val;
3535
3536 *data = (u8)word;
3537
3538 return 0;
3539 }
3540
3541 /**
3542 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3543 * @hw: pointer to the HW structure
3544 * @offset: The offset (in bytes) of the byte or word to read.
3545 * @size: Size of data to read, 1=byte 2=word
3546 * @data: Pointer to the word to store the value read.
3547 *
3548 * Reads a byte or word from the NVM using the flash access registers.
3549 **/
3550 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3551 u8 size, u16 *data)
3552 {
3553 union ich8_hws_flash_status hsfsts;
3554 union ich8_hws_flash_ctrl hsflctl;
3555 u32 flash_linear_addr;
3556 u32 flash_data = 0;
3557 s32 ret_val = -E1000_ERR_NVM;
3558 u8 count = 0;
3559
3560 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3561 return -E1000_ERR_NVM;
3562
3563 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3564 hw->nvm.flash_base_addr);
3565
3566 do {
3567 udelay(1);
3568 /* Steps */
3569 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3570 if (ret_val)
3571 break;
3572
3573 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3574 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3575 hsflctl.hsf_ctrl.fldbcount = size - 1;
3576 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3577 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3578
3579 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3580
3581 ret_val =
3582 e1000_flash_cycle_ich8lan(hw,
3583 ICH_FLASH_READ_COMMAND_TIMEOUT);
3584
3585 /* Check if FCERR is set to 1, if set to 1, clear it
3586 * and try the whole sequence a few more times, else
3587 * read in (shift in) the Flash Data0, the order is
3588 * least significant byte first msb to lsb
3589 */
3590 if (!ret_val) {
3591 flash_data = er32flash(ICH_FLASH_FDATA0);
3592 if (size == 1)
3593 *data = (u8)(flash_data & 0x000000FF);
3594 else if (size == 2)
3595 *data = (u16)(flash_data & 0x0000FFFF);
3596 break;
3597 } else {
3598 /* If we've gotten here, then things are probably
3599 * completely hosed, but if the error condition is
3600 * detected, it won't hurt to give it another try...
3601 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3602 */
3603 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3604 if (hsfsts.hsf_status.flcerr) {
3605 /* Repeat for some time before giving up. */
3606 continue;
3607 } else if (!hsfsts.hsf_status.flcdone) {
3608 e_dbg("Timeout error - flash cycle did not complete.\n");
3609 break;
3610 }
3611 }
3612 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3613
3614 return ret_val;
3615 }
3616
3617 /**
3618 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3619 * @hw: pointer to the HW structure
3620 * @offset: The offset (in bytes) of the dword to read.
3621 * @data: Pointer to the dword to store the value read.
3622 *
3623 * Reads a byte or word from the NVM using the flash access registers.
3624 **/
3625
3626 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3627 u32 *data)
3628 {
3629 union ich8_hws_flash_status hsfsts;
3630 union ich8_hws_flash_ctrl hsflctl;
3631 u32 flash_linear_addr;
3632 s32 ret_val = -E1000_ERR_NVM;
3633 u8 count = 0;
3634
3635 if (offset > ICH_FLASH_LINEAR_ADDR_MASK ||
3636 hw->mac.type != e1000_pch_spt)
3637 return -E1000_ERR_NVM;
3638 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3639 hw->nvm.flash_base_addr);
3640
3641 do {
3642 udelay(1);
3643 /* Steps */
3644 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3645 if (ret_val)
3646 break;
3647 /* In SPT, This register is in Lan memory space, not flash.
3648 * Therefore, only 32 bit access is supported
3649 */
3650 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3651
3652 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3653 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3654 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3655 /* In SPT, This register is in Lan memory space, not flash.
3656 * Therefore, only 32 bit access is supported
3657 */
3658 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3659 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3660
3661 ret_val =
3662 e1000_flash_cycle_ich8lan(hw,
3663 ICH_FLASH_READ_COMMAND_TIMEOUT);
3664
3665 /* Check if FCERR is set to 1, if set to 1, clear it
3666 * and try the whole sequence a few more times, else
3667 * read in (shift in) the Flash Data0, the order is
3668 * least significant byte first msb to lsb
3669 */
3670 if (!ret_val) {
3671 *data = er32flash(ICH_FLASH_FDATA0);
3672 break;
3673 } else {
3674 /* If we've gotten here, then things are probably
3675 * completely hosed, but if the error condition is
3676 * detected, it won't hurt to give it another try...
3677 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3678 */
3679 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3680 if (hsfsts.hsf_status.flcerr) {
3681 /* Repeat for some time before giving up. */
3682 continue;
3683 } else if (!hsfsts.hsf_status.flcdone) {
3684 e_dbg("Timeout error - flash cycle did not complete.\n");
3685 break;
3686 }
3687 }
3688 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3689
3690 return ret_val;
3691 }
3692
3693 /**
3694 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3695 * @hw: pointer to the HW structure
3696 * @offset: The offset (in bytes) of the word(s) to write.
3697 * @words: Size of data to write in words
3698 * @data: Pointer to the word(s) to write at offset.
3699 *
3700 * Writes a byte or word to the NVM using the flash access registers.
3701 **/
3702 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3703 u16 *data)
3704 {
3705 struct e1000_nvm_info *nvm = &hw->nvm;
3706 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3707 u16 i;
3708
3709 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3710 (words == 0)) {
3711 e_dbg("nvm parameter(s) out of bounds\n");
3712 return -E1000_ERR_NVM;
3713 }
3714
3715 nvm->ops.acquire(hw);
3716
3717 for (i = 0; i < words; i++) {
3718 dev_spec->shadow_ram[offset + i].modified = true;
3719 dev_spec->shadow_ram[offset + i].value = data[i];
3720 }
3721
3722 nvm->ops.release(hw);
3723
3724 return 0;
3725 }
3726
3727 /**
3728 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3729 * @hw: pointer to the HW structure
3730 *
3731 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3732 * which writes the checksum to the shadow ram. The changes in the shadow
3733 * ram are then committed to the EEPROM by processing each bank at a time
3734 * checking for the modified bit and writing only the pending changes.
3735 * After a successful commit, the shadow ram is cleared and is ready for
3736 * future writes.
3737 **/
3738 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3739 {
3740 struct e1000_nvm_info *nvm = &hw->nvm;
3741 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3742 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3743 s32 ret_val;
3744 u32 dword = 0;
3745
3746 ret_val = e1000e_update_nvm_checksum_generic(hw);
3747 if (ret_val)
3748 goto out;
3749
3750 if (nvm->type != e1000_nvm_flash_sw)
3751 goto out;
3752
3753 nvm->ops.acquire(hw);
3754
3755 /* We're writing to the opposite bank so if we're on bank 1,
3756 * write to bank 0 etc. We also need to erase the segment that
3757 * is going to be written
3758 */
3759 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3760 if (ret_val) {
3761 e_dbg("Could not detect valid bank, assuming bank 0\n");
3762 bank = 0;
3763 }
3764
3765 if (bank == 0) {
3766 new_bank_offset = nvm->flash_bank_size;
3767 old_bank_offset = 0;
3768 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3769 if (ret_val)
3770 goto release;
3771 } else {
3772 old_bank_offset = nvm->flash_bank_size;
3773 new_bank_offset = 0;
3774 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3775 if (ret_val)
3776 goto release;
3777 }
3778 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3779 /* Determine whether to write the value stored
3780 * in the other NVM bank or a modified value stored
3781 * in the shadow RAM
3782 */
3783 ret_val = e1000_read_flash_dword_ich8lan(hw,
3784 i + old_bank_offset,
3785 &dword);
3786
3787 if (dev_spec->shadow_ram[i].modified) {
3788 dword &= 0xffff0000;
3789 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3790 }
3791 if (dev_spec->shadow_ram[i + 1].modified) {
3792 dword &= 0x0000ffff;
3793 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3794 << 16);
3795 }
3796 if (ret_val)
3797 break;
3798
3799 /* If the word is 0x13, then make sure the signature bits
3800 * (15:14) are 11b until the commit has completed.
3801 * This will allow us to write 10b which indicates the
3802 * signature is valid. We want to do this after the write
3803 * has completed so that we don't mark the segment valid
3804 * while the write is still in progress
3805 */
3806 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3807 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3808
3809 /* Convert offset to bytes. */
3810 act_offset = (i + new_bank_offset) << 1;
3811
3812 usleep_range(100, 200);
3813
3814 /* Write the data to the new bank. Offset in words */
3815 act_offset = i + new_bank_offset;
3816 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3817 dword);
3818 if (ret_val)
3819 break;
3820 }
3821
3822 /* Don't bother writing the segment valid bits if sector
3823 * programming failed.
3824 */
3825 if (ret_val) {
3826 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3827 e_dbg("Flash commit failed.\n");
3828 goto release;
3829 }
3830
3831 /* Finally validate the new segment by setting bit 15:14
3832 * to 10b in word 0x13 , this can be done without an
3833 * erase as well since these bits are 11 to start with
3834 * and we need to change bit 14 to 0b
3835 */
3836 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3837
3838 /*offset in words but we read dword */
3839 --act_offset;
3840 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3841
3842 if (ret_val)
3843 goto release;
3844
3845 dword &= 0xBFFFFFFF;
3846 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3847
3848 if (ret_val)
3849 goto release;
3850
3851 /* And invalidate the previously valid segment by setting
3852 * its signature word (0x13) high_byte to 0b. This can be
3853 * done without an erase because flash erase sets all bits
3854 * to 1's. We can write 1's to 0's without an erase
3855 */
3856 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3857
3858 /* offset in words but we read dword */
3859 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3860 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3861
3862 if (ret_val)
3863 goto release;
3864
3865 dword &= 0x00FFFFFF;
3866 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3867
3868 if (ret_val)
3869 goto release;
3870
3871 /* Great! Everything worked, we can now clear the cached entries. */
3872 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3873 dev_spec->shadow_ram[i].modified = false;
3874 dev_spec->shadow_ram[i].value = 0xFFFF;
3875 }
3876
3877 release:
3878 nvm->ops.release(hw);
3879
3880 /* Reload the EEPROM, or else modifications will not appear
3881 * until after the next adapter reset.
3882 */
3883 if (!ret_val) {
3884 nvm->ops.reload(hw);
3885 usleep_range(10000, 20000);
3886 }
3887
3888 out:
3889 if (ret_val)
3890 e_dbg("NVM update error: %d\n", ret_val);
3891
3892 return ret_val;
3893 }
3894
3895 /**
3896 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3897 * @hw: pointer to the HW structure
3898 *
3899 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3900 * which writes the checksum to the shadow ram. The changes in the shadow
3901 * ram are then committed to the EEPROM by processing each bank at a time
3902 * checking for the modified bit and writing only the pending changes.
3903 * After a successful commit, the shadow ram is cleared and is ready for
3904 * future writes.
3905 **/
3906 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3907 {
3908 struct e1000_nvm_info *nvm = &hw->nvm;
3909 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3910 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3911 s32 ret_val;
3912 u16 data = 0;
3913
3914 ret_val = e1000e_update_nvm_checksum_generic(hw);
3915 if (ret_val)
3916 goto out;
3917
3918 if (nvm->type != e1000_nvm_flash_sw)
3919 goto out;
3920
3921 nvm->ops.acquire(hw);
3922
3923 /* We're writing to the opposite bank so if we're on bank 1,
3924 * write to bank 0 etc. We also need to erase the segment that
3925 * is going to be written
3926 */
3927 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3928 if (ret_val) {
3929 e_dbg("Could not detect valid bank, assuming bank 0\n");
3930 bank = 0;
3931 }
3932
3933 if (bank == 0) {
3934 new_bank_offset = nvm->flash_bank_size;
3935 old_bank_offset = 0;
3936 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3937 if (ret_val)
3938 goto release;
3939 } else {
3940 old_bank_offset = nvm->flash_bank_size;
3941 new_bank_offset = 0;
3942 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3943 if (ret_val)
3944 goto release;
3945 }
3946 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3947 if (dev_spec->shadow_ram[i].modified) {
3948 data = dev_spec->shadow_ram[i].value;
3949 } else {
3950 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3951 old_bank_offset,
3952 &data);
3953 if (ret_val)
3954 break;
3955 }
3956
3957 /* If the word is 0x13, then make sure the signature bits
3958 * (15:14) are 11b until the commit has completed.
3959 * This will allow us to write 10b which indicates the
3960 * signature is valid. We want to do this after the write
3961 * has completed so that we don't mark the segment valid
3962 * while the write is still in progress
3963 */
3964 if (i == E1000_ICH_NVM_SIG_WORD)
3965 data |= E1000_ICH_NVM_SIG_MASK;
3966
3967 /* Convert offset to bytes. */
3968 act_offset = (i + new_bank_offset) << 1;
3969
3970 usleep_range(100, 200);
3971 /* Write the bytes to the new bank. */
3972 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3973 act_offset,
3974 (u8)data);
3975 if (ret_val)
3976 break;
3977
3978 usleep_range(100, 200);
3979 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3980 act_offset + 1,
3981 (u8)(data >> 8));
3982 if (ret_val)
3983 break;
3984 }
3985
3986 /* Don't bother writing the segment valid bits if sector
3987 * programming failed.
3988 */
3989 if (ret_val) {
3990 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3991 e_dbg("Flash commit failed.\n");
3992 goto release;
3993 }
3994
3995 /* Finally validate the new segment by setting bit 15:14
3996 * to 10b in word 0x13 , this can be done without an
3997 * erase as well since these bits are 11 to start with
3998 * and we need to change bit 14 to 0b
3999 */
4000 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4001 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4002 if (ret_val)
4003 goto release;
4004
4005 data &= 0xBFFF;
4006 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4007 act_offset * 2 + 1,
4008 (u8)(data >> 8));
4009 if (ret_val)
4010 goto release;
4011
4012 /* And invalidate the previously valid segment by setting
4013 * its signature word (0x13) high_byte to 0b. This can be
4014 * done without an erase because flash erase sets all bits
4015 * to 1's. We can write 1's to 0's without an erase
4016 */
4017 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4018 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4019 if (ret_val)
4020 goto release;
4021
4022 /* Great! Everything worked, we can now clear the cached entries. */
4023 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4024 dev_spec->shadow_ram[i].modified = false;
4025 dev_spec->shadow_ram[i].value = 0xFFFF;
4026 }
4027
4028 release:
4029 nvm->ops.release(hw);
4030
4031 /* Reload the EEPROM, or else modifications will not appear
4032 * until after the next adapter reset.
4033 */
4034 if (!ret_val) {
4035 nvm->ops.reload(hw);
4036 usleep_range(10000, 20000);
4037 }
4038
4039 out:
4040 if (ret_val)
4041 e_dbg("NVM update error: %d\n", ret_val);
4042
4043 return ret_val;
4044 }
4045
4046 /**
4047 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4048 * @hw: pointer to the HW structure
4049 *
4050 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4051 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4052 * calculated, in which case we need to calculate the checksum and set bit 6.
4053 **/
4054 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4055 {
4056 s32 ret_val;
4057 u16 data;
4058 u16 word;
4059 u16 valid_csum_mask;
4060
4061 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4062 * the checksum needs to be fixed. This bit is an indication that
4063 * the NVM was prepared by OEM software and did not calculate
4064 * the checksum...a likely scenario.
4065 */
4066 switch (hw->mac.type) {
4067 case e1000_pch_lpt:
4068 case e1000_pch_spt:
4069 word = NVM_COMPAT;
4070 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4071 break;
4072 default:
4073 word = NVM_FUTURE_INIT_WORD1;
4074 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4075 break;
4076 }
4077
4078 ret_val = e1000_read_nvm(hw, word, 1, &data);
4079 if (ret_val)
4080 return ret_val;
4081
4082 if (!(data & valid_csum_mask)) {
4083 data |= valid_csum_mask;
4084 ret_val = e1000_write_nvm(hw, word, 1, &data);
4085 if (ret_val)
4086 return ret_val;
4087 ret_val = e1000e_update_nvm_checksum(hw);
4088 if (ret_val)
4089 return ret_val;
4090 }
4091
4092 return e1000e_validate_nvm_checksum_generic(hw);
4093 }
4094
4095 /**
4096 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4097 * @hw: pointer to the HW structure
4098 *
4099 * To prevent malicious write/erase of the NVM, set it to be read-only
4100 * so that the hardware ignores all write/erase cycles of the NVM via
4101 * the flash control registers. The shadow-ram copy of the NVM will
4102 * still be updated, however any updates to this copy will not stick
4103 * across driver reloads.
4104 **/
4105 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4106 {
4107 struct e1000_nvm_info *nvm = &hw->nvm;
4108 union ich8_flash_protected_range pr0;
4109 union ich8_hws_flash_status hsfsts;
4110 u32 gfpreg;
4111
4112 nvm->ops.acquire(hw);
4113
4114 gfpreg = er32flash(ICH_FLASH_GFPREG);
4115
4116 /* Write-protect GbE Sector of NVM */
4117 pr0.regval = er32flash(ICH_FLASH_PR0);
4118 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4119 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4120 pr0.range.wpe = true;
4121 ew32flash(ICH_FLASH_PR0, pr0.regval);
4122
4123 /* Lock down a subset of GbE Flash Control Registers, e.g.
4124 * PR0 to prevent the write-protection from being lifted.
4125 * Once FLOCKDN is set, the registers protected by it cannot
4126 * be written until FLOCKDN is cleared by a hardware reset.
4127 */
4128 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4129 hsfsts.hsf_status.flockdn = true;
4130 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4131
4132 nvm->ops.release(hw);
4133 }
4134
4135 /**
4136 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4137 * @hw: pointer to the HW structure
4138 * @offset: The offset (in bytes) of the byte/word to read.
4139 * @size: Size of data to read, 1=byte 2=word
4140 * @data: The byte(s) to write to the NVM.
4141 *
4142 * Writes one/two bytes to the NVM using the flash access registers.
4143 **/
4144 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4145 u8 size, u16 data)
4146 {
4147 union ich8_hws_flash_status hsfsts;
4148 union ich8_hws_flash_ctrl hsflctl;
4149 u32 flash_linear_addr;
4150 u32 flash_data = 0;
4151 s32 ret_val;
4152 u8 count = 0;
4153
4154 if (hw->mac.type == e1000_pch_spt) {
4155 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4156 return -E1000_ERR_NVM;
4157 } else {
4158 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4159 return -E1000_ERR_NVM;
4160 }
4161
4162 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4163 hw->nvm.flash_base_addr);
4164
4165 do {
4166 udelay(1);
4167 /* Steps */
4168 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4169 if (ret_val)
4170 break;
4171 /* In SPT, This register is in Lan memory space, not
4172 * flash. Therefore, only 32 bit access is supported
4173 */
4174 if (hw->mac.type == e1000_pch_spt)
4175 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4176 else
4177 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4178
4179 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4180 hsflctl.hsf_ctrl.fldbcount = size - 1;
4181 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4182 /* In SPT, This register is in Lan memory space,
4183 * not flash. Therefore, only 32 bit access is
4184 * supported
4185 */
4186 if (hw->mac.type == e1000_pch_spt)
4187 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4188 else
4189 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4190
4191 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4192
4193 if (size == 1)
4194 flash_data = (u32)data & 0x00FF;
4195 else
4196 flash_data = (u32)data;
4197
4198 ew32flash(ICH_FLASH_FDATA0, flash_data);
4199
4200 /* check if FCERR is set to 1 , if set to 1, clear it
4201 * and try the whole sequence a few more times else done
4202 */
4203 ret_val =
4204 e1000_flash_cycle_ich8lan(hw,
4205 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4206 if (!ret_val)
4207 break;
4208
4209 /* If we're here, then things are most likely
4210 * completely hosed, but if the error condition
4211 * is detected, it won't hurt to give it another
4212 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4213 */
4214 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4215 if (hsfsts.hsf_status.flcerr)
4216 /* Repeat for some time before giving up. */
4217 continue;
4218 if (!hsfsts.hsf_status.flcdone) {
4219 e_dbg("Timeout error - flash cycle did not complete.\n");
4220 break;
4221 }
4222 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4223
4224 return ret_val;
4225 }
4226
4227 /**
4228 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4229 * @hw: pointer to the HW structure
4230 * @offset: The offset (in bytes) of the dwords to read.
4231 * @data: The 4 bytes to write to the NVM.
4232 *
4233 * Writes one/two/four bytes to the NVM using the flash access registers.
4234 **/
4235 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4236 u32 data)
4237 {
4238 union ich8_hws_flash_status hsfsts;
4239 union ich8_hws_flash_ctrl hsflctl;
4240 u32 flash_linear_addr;
4241 s32 ret_val;
4242 u8 count = 0;
4243
4244 if (hw->mac.type == e1000_pch_spt) {
4245 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4246 return -E1000_ERR_NVM;
4247 }
4248 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4249 hw->nvm.flash_base_addr);
4250 do {
4251 udelay(1);
4252 /* Steps */
4253 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4254 if (ret_val)
4255 break;
4256
4257 /* In SPT, This register is in Lan memory space, not
4258 * flash. Therefore, only 32 bit access is supported
4259 */
4260 if (hw->mac.type == e1000_pch_spt)
4261 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4262 >> 16;
4263 else
4264 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4265
4266 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4267 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4268
4269 /* In SPT, This register is in Lan memory space,
4270 * not flash. Therefore, only 32 bit access is
4271 * supported
4272 */
4273 if (hw->mac.type == e1000_pch_spt)
4274 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4275 else
4276 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4277
4278 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4279
4280 ew32flash(ICH_FLASH_FDATA0, data);
4281
4282 /* check if FCERR is set to 1 , if set to 1, clear it
4283 * and try the whole sequence a few more times else done
4284 */
4285 ret_val =
4286 e1000_flash_cycle_ich8lan(hw,
4287 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4288
4289 if (!ret_val)
4290 break;
4291
4292 /* If we're here, then things are most likely
4293 * completely hosed, but if the error condition
4294 * is detected, it won't hurt to give it another
4295 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4296 */
4297 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4298
4299 if (hsfsts.hsf_status.flcerr)
4300 /* Repeat for some time before giving up. */
4301 continue;
4302 if (!hsfsts.hsf_status.flcdone) {
4303 e_dbg("Timeout error - flash cycle did not complete.\n");
4304 break;
4305 }
4306 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4307
4308 return ret_val;
4309 }
4310
4311 /**
4312 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4313 * @hw: pointer to the HW structure
4314 * @offset: The index of the byte to read.
4315 * @data: The byte to write to the NVM.
4316 *
4317 * Writes a single byte to the NVM using the flash access registers.
4318 **/
4319 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4320 u8 data)
4321 {
4322 u16 word = (u16)data;
4323
4324 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4325 }
4326
4327 /**
4328 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4329 * @hw: pointer to the HW structure
4330 * @offset: The offset of the word to write.
4331 * @dword: The dword to write to the NVM.
4332 *
4333 * Writes a single dword to the NVM using the flash access registers.
4334 * Goes through a retry algorithm before giving up.
4335 **/
4336 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4337 u32 offset, u32 dword)
4338 {
4339 s32 ret_val;
4340 u16 program_retries;
4341
4342 /* Must convert word offset into bytes. */
4343 offset <<= 1;
4344 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4345
4346 if (!ret_val)
4347 return ret_val;
4348 for (program_retries = 0; program_retries < 100; program_retries++) {
4349 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4350 usleep_range(100, 200);
4351 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4352 if (!ret_val)
4353 break;
4354 }
4355 if (program_retries == 100)
4356 return -E1000_ERR_NVM;
4357
4358 return 0;
4359 }
4360
4361 /**
4362 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4363 * @hw: pointer to the HW structure
4364 * @offset: The offset of the byte to write.
4365 * @byte: The byte to write to the NVM.
4366 *
4367 * Writes a single byte to the NVM using the flash access registers.
4368 * Goes through a retry algorithm before giving up.
4369 **/
4370 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4371 u32 offset, u8 byte)
4372 {
4373 s32 ret_val;
4374 u16 program_retries;
4375
4376 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4377 if (!ret_val)
4378 return ret_val;
4379
4380 for (program_retries = 0; program_retries < 100; program_retries++) {
4381 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4382 usleep_range(100, 200);
4383 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4384 if (!ret_val)
4385 break;
4386 }
4387 if (program_retries == 100)
4388 return -E1000_ERR_NVM;
4389
4390 return 0;
4391 }
4392
4393 /**
4394 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4395 * @hw: pointer to the HW structure
4396 * @bank: 0 for first bank, 1 for second bank, etc.
4397 *
4398 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4399 * bank N is 4096 * N + flash_reg_addr.
4400 **/
4401 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4402 {
4403 struct e1000_nvm_info *nvm = &hw->nvm;
4404 union ich8_hws_flash_status hsfsts;
4405 union ich8_hws_flash_ctrl hsflctl;
4406 u32 flash_linear_addr;
4407 /* bank size is in 16bit words - adjust to bytes */
4408 u32 flash_bank_size = nvm->flash_bank_size * 2;
4409 s32 ret_val;
4410 s32 count = 0;
4411 s32 j, iteration, sector_size;
4412
4413 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4414
4415 /* Determine HW Sector size: Read BERASE bits of hw flash status
4416 * register
4417 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4418 * consecutive sectors. The start index for the nth Hw sector
4419 * can be calculated as = bank * 4096 + n * 256
4420 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4421 * The start index for the nth Hw sector can be calculated
4422 * as = bank * 4096
4423 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4424 * (ich9 only, otherwise error condition)
4425 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4426 */
4427 switch (hsfsts.hsf_status.berasesz) {
4428 case 0:
4429 /* Hw sector size 256 */
4430 sector_size = ICH_FLASH_SEG_SIZE_256;
4431 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4432 break;
4433 case 1:
4434 sector_size = ICH_FLASH_SEG_SIZE_4K;
4435 iteration = 1;
4436 break;
4437 case 2:
4438 sector_size = ICH_FLASH_SEG_SIZE_8K;
4439 iteration = 1;
4440 break;
4441 case 3:
4442 sector_size = ICH_FLASH_SEG_SIZE_64K;
4443 iteration = 1;
4444 break;
4445 default:
4446 return -E1000_ERR_NVM;
4447 }
4448
4449 /* Start with the base address, then add the sector offset. */
4450 flash_linear_addr = hw->nvm.flash_base_addr;
4451 flash_linear_addr += (bank) ? flash_bank_size : 0;
4452
4453 for (j = 0; j < iteration; j++) {
4454 do {
4455 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4456
4457 /* Steps */
4458 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4459 if (ret_val)
4460 return ret_val;
4461
4462 /* Write a value 11 (block Erase) in Flash
4463 * Cycle field in hw flash control
4464 */
4465 if (hw->mac.type == e1000_pch_spt)
4466 hsflctl.regval =
4467 er32flash(ICH_FLASH_HSFSTS) >> 16;
4468 else
4469 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4470
4471 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4472 if (hw->mac.type == e1000_pch_spt)
4473 ew32flash(ICH_FLASH_HSFSTS,
4474 hsflctl.regval << 16);
4475 else
4476 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4477
4478 /* Write the last 24 bits of an index within the
4479 * block into Flash Linear address field in Flash
4480 * Address.
4481 */
4482 flash_linear_addr += (j * sector_size);
4483 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4484
4485 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4486 if (!ret_val)
4487 break;
4488
4489 /* Check if FCERR is set to 1. If 1,
4490 * clear it and try the whole sequence
4491 * a few more times else Done
4492 */
4493 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4494 if (hsfsts.hsf_status.flcerr)
4495 /* repeat for some time before giving up */
4496 continue;
4497 else if (!hsfsts.hsf_status.flcdone)
4498 return ret_val;
4499 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4500 }
4501
4502 return 0;
4503 }
4504
4505 /**
4506 * e1000_valid_led_default_ich8lan - Set the default LED settings
4507 * @hw: pointer to the HW structure
4508 * @data: Pointer to the LED settings
4509 *
4510 * Reads the LED default settings from the NVM to data. If the NVM LED
4511 * settings is all 0's or F's, set the LED default to a valid LED default
4512 * setting.
4513 **/
4514 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4515 {
4516 s32 ret_val;
4517
4518 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4519 if (ret_val) {
4520 e_dbg("NVM Read Error\n");
4521 return ret_val;
4522 }
4523
4524 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4525 *data = ID_LED_DEFAULT_ICH8LAN;
4526
4527 return 0;
4528 }
4529
4530 /**
4531 * e1000_id_led_init_pchlan - store LED configurations
4532 * @hw: pointer to the HW structure
4533 *
4534 * PCH does not control LEDs via the LEDCTL register, rather it uses
4535 * the PHY LED configuration register.
4536 *
4537 * PCH also does not have an "always on" or "always off" mode which
4538 * complicates the ID feature. Instead of using the "on" mode to indicate
4539 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4540 * use "link_up" mode. The LEDs will still ID on request if there is no
4541 * link based on logic in e1000_led_[on|off]_pchlan().
4542 **/
4543 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4544 {
4545 struct e1000_mac_info *mac = &hw->mac;
4546 s32 ret_val;
4547 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4548 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4549 u16 data, i, temp, shift;
4550
4551 /* Get default ID LED modes */
4552 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4553 if (ret_val)
4554 return ret_val;
4555
4556 mac->ledctl_default = er32(LEDCTL);
4557 mac->ledctl_mode1 = mac->ledctl_default;
4558 mac->ledctl_mode2 = mac->ledctl_default;
4559
4560 for (i = 0; i < 4; i++) {
4561 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4562 shift = (i * 5);
4563 switch (temp) {
4564 case ID_LED_ON1_DEF2:
4565 case ID_LED_ON1_ON2:
4566 case ID_LED_ON1_OFF2:
4567 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4568 mac->ledctl_mode1 |= (ledctl_on << shift);
4569 break;
4570 case ID_LED_OFF1_DEF2:
4571 case ID_LED_OFF1_ON2:
4572 case ID_LED_OFF1_OFF2:
4573 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4574 mac->ledctl_mode1 |= (ledctl_off << shift);
4575 break;
4576 default:
4577 /* Do nothing */
4578 break;
4579 }
4580 switch (temp) {
4581 case ID_LED_DEF1_ON2:
4582 case ID_LED_ON1_ON2:
4583 case ID_LED_OFF1_ON2:
4584 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4585 mac->ledctl_mode2 |= (ledctl_on << shift);
4586 break;
4587 case ID_LED_DEF1_OFF2:
4588 case ID_LED_ON1_OFF2:
4589 case ID_LED_OFF1_OFF2:
4590 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4591 mac->ledctl_mode2 |= (ledctl_off << shift);
4592 break;
4593 default:
4594 /* Do nothing */
4595 break;
4596 }
4597 }
4598
4599 return 0;
4600 }
4601
4602 /**
4603 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4604 * @hw: pointer to the HW structure
4605 *
4606 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4607 * register, so the the bus width is hard coded.
4608 **/
4609 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4610 {
4611 struct e1000_bus_info *bus = &hw->bus;
4612 s32 ret_val;
4613
4614 ret_val = e1000e_get_bus_info_pcie(hw);
4615
4616 /* ICH devices are "PCI Express"-ish. They have
4617 * a configuration space, but do not contain
4618 * PCI Express Capability registers, so bus width
4619 * must be hardcoded.
4620 */
4621 if (bus->width == e1000_bus_width_unknown)
4622 bus->width = e1000_bus_width_pcie_x1;
4623
4624 return ret_val;
4625 }
4626
4627 /**
4628 * e1000_reset_hw_ich8lan - Reset the hardware
4629 * @hw: pointer to the HW structure
4630 *
4631 * Does a full reset of the hardware which includes a reset of the PHY and
4632 * MAC.
4633 **/
4634 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4635 {
4636 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4637 u16 kum_cfg;
4638 u32 ctrl, reg;
4639 s32 ret_val;
4640
4641 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4642 * on the last TLP read/write transaction when MAC is reset.
4643 */
4644 ret_val = e1000e_disable_pcie_master(hw);
4645 if (ret_val)
4646 e_dbg("PCI-E Master disable polling has failed.\n");
4647
4648 e_dbg("Masking off all interrupts\n");
4649 ew32(IMC, 0xffffffff);
4650
4651 /* Disable the Transmit and Receive units. Then delay to allow
4652 * any pending transactions to complete before we hit the MAC
4653 * with the global reset.
4654 */
4655 ew32(RCTL, 0);
4656 ew32(TCTL, E1000_TCTL_PSP);
4657 e1e_flush();
4658
4659 usleep_range(10000, 20000);
4660
4661 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4662 if (hw->mac.type == e1000_ich8lan) {
4663 /* Set Tx and Rx buffer allocation to 8k apiece. */
4664 ew32(PBA, E1000_PBA_8K);
4665 /* Set Packet Buffer Size to 16k. */
4666 ew32(PBS, E1000_PBS_16K);
4667 }
4668
4669 if (hw->mac.type == e1000_pchlan) {
4670 /* Save the NVM K1 bit setting */
4671 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4672 if (ret_val)
4673 return ret_val;
4674
4675 if (kum_cfg & E1000_NVM_K1_ENABLE)
4676 dev_spec->nvm_k1_enabled = true;
4677 else
4678 dev_spec->nvm_k1_enabled = false;
4679 }
4680
4681 ctrl = er32(CTRL);
4682
4683 if (!hw->phy.ops.check_reset_block(hw)) {
4684 /* Full-chip reset requires MAC and PHY reset at the same
4685 * time to make sure the interface between MAC and the
4686 * external PHY is reset.
4687 */
4688 ctrl |= E1000_CTRL_PHY_RST;
4689
4690 /* Gate automatic PHY configuration by hardware on
4691 * non-managed 82579
4692 */
4693 if ((hw->mac.type == e1000_pch2lan) &&
4694 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4695 e1000_gate_hw_phy_config_ich8lan(hw, true);
4696 }
4697 ret_val = e1000_acquire_swflag_ich8lan(hw);
4698 e_dbg("Issuing a global reset to ich8lan\n");
4699 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4700 /* cannot issue a flush here because it hangs the hardware */
4701 msleep(20);
4702
4703 /* Set Phy Config Counter to 50msec */
4704 if (hw->mac.type == e1000_pch2lan) {
4705 reg = er32(FEXTNVM3);
4706 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4707 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4708 ew32(FEXTNVM3, reg);
4709 }
4710
4711 if (!ret_val)
4712 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4713
4714 if (ctrl & E1000_CTRL_PHY_RST) {
4715 ret_val = hw->phy.ops.get_cfg_done(hw);
4716 if (ret_val)
4717 return ret_val;
4718
4719 ret_val = e1000_post_phy_reset_ich8lan(hw);
4720 if (ret_val)
4721 return ret_val;
4722 }
4723
4724 /* For PCH, this write will make sure that any noise
4725 * will be detected as a CRC error and be dropped rather than show up
4726 * as a bad packet to the DMA engine.
4727 */
4728 if (hw->mac.type == e1000_pchlan)
4729 ew32(CRC_OFFSET, 0x65656565);
4730
4731 ew32(IMC, 0xffffffff);
4732 er32(ICR);
4733
4734 reg = er32(KABGTXD);
4735 reg |= E1000_KABGTXD_BGSQLBIAS;
4736 ew32(KABGTXD, reg);
4737
4738 return 0;
4739 }
4740
4741 /**
4742 * e1000_init_hw_ich8lan - Initialize the hardware
4743 * @hw: pointer to the HW structure
4744 *
4745 * Prepares the hardware for transmit and receive by doing the following:
4746 * - initialize hardware bits
4747 * - initialize LED identification
4748 * - setup receive address registers
4749 * - setup flow control
4750 * - setup transmit descriptors
4751 * - clear statistics
4752 **/
4753 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4754 {
4755 struct e1000_mac_info *mac = &hw->mac;
4756 u32 ctrl_ext, txdctl, snoop;
4757 s32 ret_val;
4758 u16 i;
4759
4760 e1000_initialize_hw_bits_ich8lan(hw);
4761
4762 /* Initialize identification LED */
4763 ret_val = mac->ops.id_led_init(hw);
4764 /* An error is not fatal and we should not stop init due to this */
4765 if (ret_val)
4766 e_dbg("Error initializing identification LED\n");
4767
4768 /* Setup the receive address. */
4769 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4770
4771 /* Zero out the Multicast HASH table */
4772 e_dbg("Zeroing the MTA\n");
4773 for (i = 0; i < mac->mta_reg_count; i++)
4774 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4775
4776 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4777 * the ME. Disable wakeup by clearing the host wakeup bit.
4778 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4779 */
4780 if (hw->phy.type == e1000_phy_82578) {
4781 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4782 i &= ~BM_WUC_HOST_WU_BIT;
4783 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4784 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4785 if (ret_val)
4786 return ret_val;
4787 }
4788
4789 /* Setup link and flow control */
4790 ret_val = mac->ops.setup_link(hw);
4791
4792 /* Set the transmit descriptor write-back policy for both queues */
4793 txdctl = er32(TXDCTL(0));
4794 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4795 E1000_TXDCTL_FULL_TX_DESC_WB);
4796 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4797 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4798 ew32(TXDCTL(0), txdctl);
4799 txdctl = er32(TXDCTL(1));
4800 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4801 E1000_TXDCTL_FULL_TX_DESC_WB);
4802 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4803 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4804 ew32(TXDCTL(1), txdctl);
4805
4806 /* ICH8 has opposite polarity of no_snoop bits.
4807 * By default, we should use snoop behavior.
4808 */
4809 if (mac->type == e1000_ich8lan)
4810 snoop = PCIE_ICH8_SNOOP_ALL;
4811 else
4812 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4813 e1000e_set_pcie_no_snoop(hw, snoop);
4814
4815 ctrl_ext = er32(CTRL_EXT);
4816 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4817 ew32(CTRL_EXT, ctrl_ext);
4818
4819 /* Clear all of the statistics registers (clear on read). It is
4820 * important that we do this after we have tried to establish link
4821 * because the symbol error count will increment wildly if there
4822 * is no link.
4823 */
4824 e1000_clear_hw_cntrs_ich8lan(hw);
4825
4826 return ret_val;
4827 }
4828
4829 /**
4830 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4831 * @hw: pointer to the HW structure
4832 *
4833 * Sets/Clears required hardware bits necessary for correctly setting up the
4834 * hardware for transmit and receive.
4835 **/
4836 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4837 {
4838 u32 reg;
4839
4840 /* Extended Device Control */
4841 reg = er32(CTRL_EXT);
4842 reg |= (1 << 22);
4843 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4844 if (hw->mac.type >= e1000_pchlan)
4845 reg |= E1000_CTRL_EXT_PHYPDEN;
4846 ew32(CTRL_EXT, reg);
4847
4848 /* Transmit Descriptor Control 0 */
4849 reg = er32(TXDCTL(0));
4850 reg |= (1 << 22);
4851 ew32(TXDCTL(0), reg);
4852
4853 /* Transmit Descriptor Control 1 */
4854 reg = er32(TXDCTL(1));
4855 reg |= (1 << 22);
4856 ew32(TXDCTL(1), reg);
4857
4858 /* Transmit Arbitration Control 0 */
4859 reg = er32(TARC(0));
4860 if (hw->mac.type == e1000_ich8lan)
4861 reg |= (1 << 28) | (1 << 29);
4862 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
4863 ew32(TARC(0), reg);
4864
4865 /* Transmit Arbitration Control 1 */
4866 reg = er32(TARC(1));
4867 if (er32(TCTL) & E1000_TCTL_MULR)
4868 reg &= ~(1 << 28);
4869 else
4870 reg |= (1 << 28);
4871 reg |= (1 << 24) | (1 << 26) | (1 << 30);
4872 ew32(TARC(1), reg);
4873
4874 /* Device Status */
4875 if (hw->mac.type == e1000_ich8lan) {
4876 reg = er32(STATUS);
4877 reg &= ~(1 << 31);
4878 ew32(STATUS, reg);
4879 }
4880
4881 /* work-around descriptor data corruption issue during nfs v2 udp
4882 * traffic, just disable the nfs filtering capability
4883 */
4884 reg = er32(RFCTL);
4885 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4886
4887 /* Disable IPv6 extension header parsing because some malformed
4888 * IPv6 headers can hang the Rx.
4889 */
4890 if (hw->mac.type == e1000_ich8lan)
4891 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4892 ew32(RFCTL, reg);
4893
4894 /* Enable ECC on Lynxpoint */
4895 if ((hw->mac.type == e1000_pch_lpt) ||
4896 (hw->mac.type == e1000_pch_spt)) {
4897 reg = er32(PBECCSTS);
4898 reg |= E1000_PBECCSTS_ECC_ENABLE;
4899 ew32(PBECCSTS, reg);
4900
4901 reg = er32(CTRL);
4902 reg |= E1000_CTRL_MEHE;
4903 ew32(CTRL, reg);
4904 }
4905 }
4906
4907 /**
4908 * e1000_setup_link_ich8lan - Setup flow control and link settings
4909 * @hw: pointer to the HW structure
4910 *
4911 * Determines which flow control settings to use, then configures flow
4912 * control. Calls the appropriate media-specific link configuration
4913 * function. Assuming the adapter has a valid link partner, a valid link
4914 * should be established. Assumes the hardware has previously been reset
4915 * and the transmitter and receiver are not enabled.
4916 **/
4917 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4918 {
4919 s32 ret_val;
4920
4921 if (hw->phy.ops.check_reset_block(hw))
4922 return 0;
4923
4924 /* ICH parts do not have a word in the NVM to determine
4925 * the default flow control setting, so we explicitly
4926 * set it to full.
4927 */
4928 if (hw->fc.requested_mode == e1000_fc_default) {
4929 /* Workaround h/w hang when Tx flow control enabled */
4930 if (hw->mac.type == e1000_pchlan)
4931 hw->fc.requested_mode = e1000_fc_rx_pause;
4932 else
4933 hw->fc.requested_mode = e1000_fc_full;
4934 }
4935
4936 /* Save off the requested flow control mode for use later. Depending
4937 * on the link partner's capabilities, we may or may not use this mode.
4938 */
4939 hw->fc.current_mode = hw->fc.requested_mode;
4940
4941 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4942
4943 /* Continue to configure the copper link. */
4944 ret_val = hw->mac.ops.setup_physical_interface(hw);
4945 if (ret_val)
4946 return ret_val;
4947
4948 ew32(FCTTV, hw->fc.pause_time);
4949 if ((hw->phy.type == e1000_phy_82578) ||
4950 (hw->phy.type == e1000_phy_82579) ||
4951 (hw->phy.type == e1000_phy_i217) ||
4952 (hw->phy.type == e1000_phy_82577)) {
4953 ew32(FCRTV_PCH, hw->fc.refresh_time);
4954
4955 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4956 hw->fc.pause_time);
4957 if (ret_val)
4958 return ret_val;
4959 }
4960
4961 return e1000e_set_fc_watermarks(hw);
4962 }
4963
4964 /**
4965 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4966 * @hw: pointer to the HW structure
4967 *
4968 * Configures the kumeran interface to the PHY to wait the appropriate time
4969 * when polling the PHY, then call the generic setup_copper_link to finish
4970 * configuring the copper link.
4971 **/
4972 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4973 {
4974 u32 ctrl;
4975 s32 ret_val;
4976 u16 reg_data;
4977
4978 ctrl = er32(CTRL);
4979 ctrl |= E1000_CTRL_SLU;
4980 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
4981 ew32(CTRL, ctrl);
4982
4983 /* Set the mac to wait the maximum time between each iteration
4984 * and increase the max iterations when polling the phy;
4985 * this fixes erroneous timeouts at 10Mbps.
4986 */
4987 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
4988 if (ret_val)
4989 return ret_val;
4990 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4991 &reg_data);
4992 if (ret_val)
4993 return ret_val;
4994 reg_data |= 0x3F;
4995 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
4996 reg_data);
4997 if (ret_val)
4998 return ret_val;
4999
5000 switch (hw->phy.type) {
5001 case e1000_phy_igp_3:
5002 ret_val = e1000e_copper_link_setup_igp(hw);
5003 if (ret_val)
5004 return ret_val;
5005 break;
5006 case e1000_phy_bm:
5007 case e1000_phy_82578:
5008 ret_val = e1000e_copper_link_setup_m88(hw);
5009 if (ret_val)
5010 return ret_val;
5011 break;
5012 case e1000_phy_82577:
5013 case e1000_phy_82579:
5014 ret_val = e1000_copper_link_setup_82577(hw);
5015 if (ret_val)
5016 return ret_val;
5017 break;
5018 case e1000_phy_ife:
5019 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
5020 if (ret_val)
5021 return ret_val;
5022
5023 reg_data &= ~IFE_PMC_AUTO_MDIX;
5024
5025 switch (hw->phy.mdix) {
5026 case 1:
5027 reg_data &= ~IFE_PMC_FORCE_MDIX;
5028 break;
5029 case 2:
5030 reg_data |= IFE_PMC_FORCE_MDIX;
5031 break;
5032 case 0:
5033 default:
5034 reg_data |= IFE_PMC_AUTO_MDIX;
5035 break;
5036 }
5037 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5038 if (ret_val)
5039 return ret_val;
5040 break;
5041 default:
5042 break;
5043 }
5044
5045 return e1000e_setup_copper_link(hw);
5046 }
5047
5048 /**
5049 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5050 * @hw: pointer to the HW structure
5051 *
5052 * Calls the PHY specific link setup function and then calls the
5053 * generic setup_copper_link to finish configuring the link for
5054 * Lynxpoint PCH devices
5055 **/
5056 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5057 {
5058 u32 ctrl;
5059 s32 ret_val;
5060
5061 ctrl = er32(CTRL);
5062 ctrl |= E1000_CTRL_SLU;
5063 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5064 ew32(CTRL, ctrl);
5065
5066 ret_val = e1000_copper_link_setup_82577(hw);
5067 if (ret_val)
5068 return ret_val;
5069
5070 return e1000e_setup_copper_link(hw);
5071 }
5072
5073 /**
5074 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5075 * @hw: pointer to the HW structure
5076 * @speed: pointer to store current link speed
5077 * @duplex: pointer to store the current link duplex
5078 *
5079 * Calls the generic get_speed_and_duplex to retrieve the current link
5080 * information and then calls the Kumeran lock loss workaround for links at
5081 * gigabit speeds.
5082 **/
5083 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5084 u16 *duplex)
5085 {
5086 s32 ret_val;
5087
5088 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5089 if (ret_val)
5090 return ret_val;
5091
5092 if ((hw->mac.type == e1000_ich8lan) &&
5093 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5094 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5095 }
5096
5097 return ret_val;
5098 }
5099
5100 /**
5101 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5102 * @hw: pointer to the HW structure
5103 *
5104 * Work-around for 82566 Kumeran PCS lock loss:
5105 * On link status change (i.e. PCI reset, speed change) and link is up and
5106 * speed is gigabit-
5107 * 0) if workaround is optionally disabled do nothing
5108 * 1) wait 1ms for Kumeran link to come up
5109 * 2) check Kumeran Diagnostic register PCS lock loss bit
5110 * 3) if not set the link is locked (all is good), otherwise...
5111 * 4) reset the PHY
5112 * 5) repeat up to 10 times
5113 * Note: this is only called for IGP3 copper when speed is 1gb.
5114 **/
5115 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5116 {
5117 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5118 u32 phy_ctrl;
5119 s32 ret_val;
5120 u16 i, data;
5121 bool link;
5122
5123 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5124 return 0;
5125
5126 /* Make sure link is up before proceeding. If not just return.
5127 * Attempting this while link is negotiating fouled up link
5128 * stability
5129 */
5130 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5131 if (!link)
5132 return 0;
5133
5134 for (i = 0; i < 10; i++) {
5135 /* read once to clear */
5136 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5137 if (ret_val)
5138 return ret_val;
5139 /* and again to get new status */
5140 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5141 if (ret_val)
5142 return ret_val;
5143
5144 /* check for PCS lock */
5145 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5146 return 0;
5147
5148 /* Issue PHY reset */
5149 e1000_phy_hw_reset(hw);
5150 mdelay(5);
5151 }
5152 /* Disable GigE link negotiation */
5153 phy_ctrl = er32(PHY_CTRL);
5154 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5155 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5156 ew32(PHY_CTRL, phy_ctrl);
5157
5158 /* Call gig speed drop workaround on Gig disable before accessing
5159 * any PHY registers
5160 */
5161 e1000e_gig_downshift_workaround_ich8lan(hw);
5162
5163 /* unable to acquire PCS lock */
5164 return -E1000_ERR_PHY;
5165 }
5166
5167 /**
5168 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5169 * @hw: pointer to the HW structure
5170 * @state: boolean value used to set the current Kumeran workaround state
5171 *
5172 * If ICH8, set the current Kumeran workaround state (enabled - true
5173 * /disabled - false).
5174 **/
5175 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5176 bool state)
5177 {
5178 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5179
5180 if (hw->mac.type != e1000_ich8lan) {
5181 e_dbg("Workaround applies to ICH8 only.\n");
5182 return;
5183 }
5184
5185 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5186 }
5187
5188 /**
5189 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5190 * @hw: pointer to the HW structure
5191 *
5192 * Workaround for 82566 power-down on D3 entry:
5193 * 1) disable gigabit link
5194 * 2) write VR power-down enable
5195 * 3) read it back
5196 * Continue if successful, else issue LCD reset and repeat
5197 **/
5198 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5199 {
5200 u32 reg;
5201 u16 data;
5202 u8 retry = 0;
5203
5204 if (hw->phy.type != e1000_phy_igp_3)
5205 return;
5206
5207 /* Try the workaround twice (if needed) */
5208 do {
5209 /* Disable link */
5210 reg = er32(PHY_CTRL);
5211 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5212 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5213 ew32(PHY_CTRL, reg);
5214
5215 /* Call gig speed drop workaround on Gig disable before
5216 * accessing any PHY registers
5217 */
5218 if (hw->mac.type == e1000_ich8lan)
5219 e1000e_gig_downshift_workaround_ich8lan(hw);
5220
5221 /* Write VR power-down enable */
5222 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5223 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5224 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5225
5226 /* Read it back and test */
5227 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5228 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5229 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5230 break;
5231
5232 /* Issue PHY reset and repeat at most one more time */
5233 reg = er32(CTRL);
5234 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5235 retry++;
5236 } while (retry);
5237 }
5238
5239 /**
5240 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5241 * @hw: pointer to the HW structure
5242 *
5243 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5244 * LPLU, Gig disable, MDIC PHY reset):
5245 * 1) Set Kumeran Near-end loopback
5246 * 2) Clear Kumeran Near-end loopback
5247 * Should only be called for ICH8[m] devices with any 1G Phy.
5248 **/
5249 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5250 {
5251 s32 ret_val;
5252 u16 reg_data;
5253
5254 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5255 return;
5256
5257 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5258 &reg_data);
5259 if (ret_val)
5260 return;
5261 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5262 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5263 reg_data);
5264 if (ret_val)
5265 return;
5266 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5267 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5268 }
5269
5270 /**
5271 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5272 * @hw: pointer to the HW structure
5273 *
5274 * During S0 to Sx transition, it is possible the link remains at gig
5275 * instead of negotiating to a lower speed. Before going to Sx, set
5276 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5277 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5278 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5279 * needs to be written.
5280 * Parts that support (and are linked to a partner which support) EEE in
5281 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5282 * than 10Mbps w/o EEE.
5283 **/
5284 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5285 {
5286 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5287 u32 phy_ctrl;
5288 s32 ret_val;
5289
5290 phy_ctrl = er32(PHY_CTRL);
5291 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5292
5293 if (hw->phy.type == e1000_phy_i217) {
5294 u16 phy_reg, device_id = hw->adapter->pdev->device;
5295
5296 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5297 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5298 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5299 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5300 (hw->mac.type == e1000_pch_spt)) {
5301 u32 fextnvm6 = er32(FEXTNVM6);
5302
5303 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5304 }
5305
5306 ret_val = hw->phy.ops.acquire(hw);
5307 if (ret_val)
5308 goto out;
5309
5310 if (!dev_spec->eee_disable) {
5311 u16 eee_advert;
5312
5313 ret_val =
5314 e1000_read_emi_reg_locked(hw,
5315 I217_EEE_ADVERTISEMENT,
5316 &eee_advert);
5317 if (ret_val)
5318 goto release;
5319
5320 /* Disable LPLU if both link partners support 100BaseT
5321 * EEE and 100Full is advertised on both ends of the
5322 * link, and enable Auto Enable LPI since there will
5323 * be no driver to enable LPI while in Sx.
5324 */
5325 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5326 (dev_spec->eee_lp_ability &
5327 I82579_EEE_100_SUPPORTED) &&
5328 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5329 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5330 E1000_PHY_CTRL_NOND0A_LPLU);
5331
5332 /* Set Auto Enable LPI after link up */
5333 e1e_rphy_locked(hw,
5334 I217_LPI_GPIO_CTRL, &phy_reg);
5335 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5336 e1e_wphy_locked(hw,
5337 I217_LPI_GPIO_CTRL, phy_reg);
5338 }
5339 }
5340
5341 /* For i217 Intel Rapid Start Technology support,
5342 * when the system is going into Sx and no manageability engine
5343 * is present, the driver must configure proxy to reset only on
5344 * power good. LPI (Low Power Idle) state must also reset only
5345 * on power good, as well as the MTA (Multicast table array).
5346 * The SMBus release must also be disabled on LCD reset.
5347 */
5348 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5349 /* Enable proxy to reset only on power good. */
5350 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5351 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5352 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5353
5354 /* Set bit enable LPI (EEE) to reset only on
5355 * power good.
5356 */
5357 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5358 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5359 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5360
5361 /* Disable the SMB release on LCD reset. */
5362 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5363 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5364 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5365 }
5366
5367 /* Enable MTA to reset for Intel Rapid Start Technology
5368 * Support
5369 */
5370 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5371 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5372 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5373
5374 release:
5375 hw->phy.ops.release(hw);
5376 }
5377 out:
5378 ew32(PHY_CTRL, phy_ctrl);
5379
5380 if (hw->mac.type == e1000_ich8lan)
5381 e1000e_gig_downshift_workaround_ich8lan(hw);
5382
5383 if (hw->mac.type >= e1000_pchlan) {
5384 e1000_oem_bits_config_ich8lan(hw, false);
5385
5386 /* Reset PHY to activate OEM bits on 82577/8 */
5387 if (hw->mac.type == e1000_pchlan)
5388 e1000e_phy_hw_reset_generic(hw);
5389
5390 ret_val = hw->phy.ops.acquire(hw);
5391 if (ret_val)
5392 return;
5393 e1000_write_smbus_addr(hw);
5394 hw->phy.ops.release(hw);
5395 }
5396 }
5397
5398 /**
5399 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5400 * @hw: pointer to the HW structure
5401 *
5402 * During Sx to S0 transitions on non-managed devices or managed devices
5403 * on which PHY resets are not blocked, if the PHY registers cannot be
5404 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5405 * the PHY.
5406 * On i217, setup Intel Rapid Start Technology.
5407 **/
5408 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5409 {
5410 s32 ret_val;
5411
5412 if (hw->mac.type < e1000_pch2lan)
5413 return;
5414
5415 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5416 if (ret_val) {
5417 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5418 return;
5419 }
5420
5421 /* For i217 Intel Rapid Start Technology support when the system
5422 * is transitioning from Sx and no manageability engine is present
5423 * configure SMBus to restore on reset, disable proxy, and enable
5424 * the reset on MTA (Multicast table array).
5425 */
5426 if (hw->phy.type == e1000_phy_i217) {
5427 u16 phy_reg;
5428
5429 ret_val = hw->phy.ops.acquire(hw);
5430 if (ret_val) {
5431 e_dbg("Failed to setup iRST\n");
5432 return;
5433 }
5434
5435 /* Clear Auto Enable LPI after link up */
5436 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5437 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5438 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5439
5440 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5441 /* Restore clear on SMB if no manageability engine
5442 * is present
5443 */
5444 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5445 if (ret_val)
5446 goto release;
5447 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5448 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5449
5450 /* Disable Proxy */
5451 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5452 }
5453 /* Enable reset on MTA */
5454 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5455 if (ret_val)
5456 goto release;
5457 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5458 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5459 release:
5460 if (ret_val)
5461 e_dbg("Error %d in resume workarounds\n", ret_val);
5462 hw->phy.ops.release(hw);
5463 }
5464 }
5465
5466 /**
5467 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5468 * @hw: pointer to the HW structure
5469 *
5470 * Return the LED back to the default configuration.
5471 **/
5472 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5473 {
5474 if (hw->phy.type == e1000_phy_ife)
5475 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5476
5477 ew32(LEDCTL, hw->mac.ledctl_default);
5478 return 0;
5479 }
5480
5481 /**
5482 * e1000_led_on_ich8lan - Turn LEDs on
5483 * @hw: pointer to the HW structure
5484 *
5485 * Turn on the LEDs.
5486 **/
5487 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5488 {
5489 if (hw->phy.type == e1000_phy_ife)
5490 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5491 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5492
5493 ew32(LEDCTL, hw->mac.ledctl_mode2);
5494 return 0;
5495 }
5496
5497 /**
5498 * e1000_led_off_ich8lan - Turn LEDs off
5499 * @hw: pointer to the HW structure
5500 *
5501 * Turn off the LEDs.
5502 **/
5503 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5504 {
5505 if (hw->phy.type == e1000_phy_ife)
5506 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5507 (IFE_PSCL_PROBE_MODE |
5508 IFE_PSCL_PROBE_LEDS_OFF));
5509
5510 ew32(LEDCTL, hw->mac.ledctl_mode1);
5511 return 0;
5512 }
5513
5514 /**
5515 * e1000_setup_led_pchlan - Configures SW controllable LED
5516 * @hw: pointer to the HW structure
5517 *
5518 * This prepares the SW controllable LED for use.
5519 **/
5520 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5521 {
5522 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5523 }
5524
5525 /**
5526 * e1000_cleanup_led_pchlan - Restore the default LED operation
5527 * @hw: pointer to the HW structure
5528 *
5529 * Return the LED back to the default configuration.
5530 **/
5531 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5532 {
5533 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5534 }
5535
5536 /**
5537 * e1000_led_on_pchlan - Turn LEDs on
5538 * @hw: pointer to the HW structure
5539 *
5540 * Turn on the LEDs.
5541 **/
5542 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5543 {
5544 u16 data = (u16)hw->mac.ledctl_mode2;
5545 u32 i, led;
5546
5547 /* If no link, then turn LED on by setting the invert bit
5548 * for each LED that's mode is "link_up" in ledctl_mode2.
5549 */
5550 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5551 for (i = 0; i < 3; i++) {
5552 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5553 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5554 E1000_LEDCTL_MODE_LINK_UP)
5555 continue;
5556 if (led & E1000_PHY_LED0_IVRT)
5557 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5558 else
5559 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5560 }
5561 }
5562
5563 return e1e_wphy(hw, HV_LED_CONFIG, data);
5564 }
5565
5566 /**
5567 * e1000_led_off_pchlan - Turn LEDs off
5568 * @hw: pointer to the HW structure
5569 *
5570 * Turn off the LEDs.
5571 **/
5572 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5573 {
5574 u16 data = (u16)hw->mac.ledctl_mode1;
5575 u32 i, led;
5576
5577 /* If no link, then turn LED off by clearing the invert bit
5578 * for each LED that's mode is "link_up" in ledctl_mode1.
5579 */
5580 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5581 for (i = 0; i < 3; i++) {
5582 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5583 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5584 E1000_LEDCTL_MODE_LINK_UP)
5585 continue;
5586 if (led & E1000_PHY_LED0_IVRT)
5587 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5588 else
5589 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5590 }
5591 }
5592
5593 return e1e_wphy(hw, HV_LED_CONFIG, data);
5594 }
5595
5596 /**
5597 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5598 * @hw: pointer to the HW structure
5599 *
5600 * Read appropriate register for the config done bit for completion status
5601 * and configure the PHY through s/w for EEPROM-less parts.
5602 *
5603 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5604 * config done bit, so only an error is logged and continues. If we were
5605 * to return with error, EEPROM-less silicon would not be able to be reset
5606 * or change link.
5607 **/
5608 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5609 {
5610 s32 ret_val = 0;
5611 u32 bank = 0;
5612 u32 status;
5613
5614 e1000e_get_cfg_done_generic(hw);
5615
5616 /* Wait for indication from h/w that it has completed basic config */
5617 if (hw->mac.type >= e1000_ich10lan) {
5618 e1000_lan_init_done_ich8lan(hw);
5619 } else {
5620 ret_val = e1000e_get_auto_rd_done(hw);
5621 if (ret_val) {
5622 /* When auto config read does not complete, do not
5623 * return with an error. This can happen in situations
5624 * where there is no eeprom and prevents getting link.
5625 */
5626 e_dbg("Auto Read Done did not complete\n");
5627 ret_val = 0;
5628 }
5629 }
5630
5631 /* Clear PHY Reset Asserted bit */
5632 status = er32(STATUS);
5633 if (status & E1000_STATUS_PHYRA)
5634 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5635 else
5636 e_dbg("PHY Reset Asserted not set - needs delay\n");
5637
5638 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5639 if (hw->mac.type <= e1000_ich9lan) {
5640 if (!(er32(EECD) & E1000_EECD_PRES) &&
5641 (hw->phy.type == e1000_phy_igp_3)) {
5642 e1000e_phy_init_script_igp3(hw);
5643 }
5644 } else {
5645 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5646 /* Maybe we should do a basic PHY config */
5647 e_dbg("EEPROM not present\n");
5648 ret_val = -E1000_ERR_CONFIG;
5649 }
5650 }
5651
5652 return ret_val;
5653 }
5654
5655 /**
5656 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5657 * @hw: pointer to the HW structure
5658 *
5659 * In the case of a PHY power down to save power, or to turn off link during a
5660 * driver unload, or wake on lan is not enabled, remove the link.
5661 **/
5662 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5663 {
5664 /* If the management interface is not enabled, then power down */
5665 if (!(hw->mac.ops.check_mng_mode(hw) ||
5666 hw->phy.ops.check_reset_block(hw)))
5667 e1000_power_down_phy_copper(hw);
5668 }
5669
5670 /**
5671 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5672 * @hw: pointer to the HW structure
5673 *
5674 * Clears hardware counters specific to the silicon family and calls
5675 * clear_hw_cntrs_generic to clear all general purpose counters.
5676 **/
5677 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5678 {
5679 u16 phy_data;
5680 s32 ret_val;
5681
5682 e1000e_clear_hw_cntrs_base(hw);
5683
5684 er32(ALGNERRC);
5685 er32(RXERRC);
5686 er32(TNCRS);
5687 er32(CEXTERR);
5688 er32(TSCTC);
5689 er32(TSCTFC);
5690
5691 er32(MGTPRC);
5692 er32(MGTPDC);
5693 er32(MGTPTC);
5694
5695 er32(IAC);
5696 er32(ICRXOC);
5697
5698 /* Clear PHY statistics registers */
5699 if ((hw->phy.type == e1000_phy_82578) ||
5700 (hw->phy.type == e1000_phy_82579) ||
5701 (hw->phy.type == e1000_phy_i217) ||
5702 (hw->phy.type == e1000_phy_82577)) {
5703 ret_val = hw->phy.ops.acquire(hw);
5704 if (ret_val)
5705 return;
5706 ret_val = hw->phy.ops.set_page(hw,
5707 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5708 if (ret_val)
5709 goto release;
5710 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5711 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5712 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5713 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5714 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5715 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5716 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5717 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5718 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5719 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5720 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5721 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5722 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5723 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5724 release:
5725 hw->phy.ops.release(hw);
5726 }
5727 }
5728
5729 static const struct e1000_mac_operations ich8_mac_ops = {
5730 /* check_mng_mode dependent on mac type */
5731 .check_for_link = e1000_check_for_copper_link_ich8lan,
5732 /* cleanup_led dependent on mac type */
5733 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5734 .get_bus_info = e1000_get_bus_info_ich8lan,
5735 .set_lan_id = e1000_set_lan_id_single_port,
5736 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5737 /* led_on dependent on mac type */
5738 /* led_off dependent on mac type */
5739 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5740 .reset_hw = e1000_reset_hw_ich8lan,
5741 .init_hw = e1000_init_hw_ich8lan,
5742 .setup_link = e1000_setup_link_ich8lan,
5743 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5744 /* id_led_init dependent on mac type */
5745 .config_collision_dist = e1000e_config_collision_dist_generic,
5746 .rar_set = e1000e_rar_set_generic,
5747 .rar_get_count = e1000e_rar_get_count_generic,
5748 };
5749
5750 static const struct e1000_phy_operations ich8_phy_ops = {
5751 .acquire = e1000_acquire_swflag_ich8lan,
5752 .check_reset_block = e1000_check_reset_block_ich8lan,
5753 .commit = NULL,
5754 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5755 .get_cable_length = e1000e_get_cable_length_igp_2,
5756 .read_reg = e1000e_read_phy_reg_igp,
5757 .release = e1000_release_swflag_ich8lan,
5758 .reset = e1000_phy_hw_reset_ich8lan,
5759 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5760 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5761 .write_reg = e1000e_write_phy_reg_igp,
5762 };
5763
5764 static const struct e1000_nvm_operations ich8_nvm_ops = {
5765 .acquire = e1000_acquire_nvm_ich8lan,
5766 .read = e1000_read_nvm_ich8lan,
5767 .release = e1000_release_nvm_ich8lan,
5768 .reload = e1000e_reload_nvm_generic,
5769 .update = e1000_update_nvm_checksum_ich8lan,
5770 .valid_led_default = e1000_valid_led_default_ich8lan,
5771 .validate = e1000_validate_nvm_checksum_ich8lan,
5772 .write = e1000_write_nvm_ich8lan,
5773 };
5774
5775 static const struct e1000_nvm_operations spt_nvm_ops = {
5776 .acquire = e1000_acquire_nvm_ich8lan,
5777 .release = e1000_release_nvm_ich8lan,
5778 .read = e1000_read_nvm_spt,
5779 .update = e1000_update_nvm_checksum_spt,
5780 .reload = e1000e_reload_nvm_generic,
5781 .valid_led_default = e1000_valid_led_default_ich8lan,
5782 .validate = e1000_validate_nvm_checksum_ich8lan,
5783 .write = e1000_write_nvm_ich8lan,
5784 };
5785
5786 const struct e1000_info e1000_ich8_info = {
5787 .mac = e1000_ich8lan,
5788 .flags = FLAG_HAS_WOL
5789 | FLAG_IS_ICH
5790 | FLAG_HAS_CTRLEXT_ON_LOAD
5791 | FLAG_HAS_AMT
5792 | FLAG_HAS_FLASH
5793 | FLAG_APME_IN_WUC,
5794 .pba = 8,
5795 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5796 .get_variants = e1000_get_variants_ich8lan,
5797 .mac_ops = &ich8_mac_ops,
5798 .phy_ops = &ich8_phy_ops,
5799 .nvm_ops = &ich8_nvm_ops,
5800 };
5801
5802 const struct e1000_info e1000_ich9_info = {
5803 .mac = e1000_ich9lan,
5804 .flags = FLAG_HAS_JUMBO_FRAMES
5805 | FLAG_IS_ICH
5806 | FLAG_HAS_WOL
5807 | FLAG_HAS_CTRLEXT_ON_LOAD
5808 | FLAG_HAS_AMT
5809 | FLAG_HAS_FLASH
5810 | FLAG_APME_IN_WUC,
5811 .pba = 18,
5812 .max_hw_frame_size = DEFAULT_JUMBO,
5813 .get_variants = e1000_get_variants_ich8lan,
5814 .mac_ops = &ich8_mac_ops,
5815 .phy_ops = &ich8_phy_ops,
5816 .nvm_ops = &ich8_nvm_ops,
5817 };
5818
5819 const struct e1000_info e1000_ich10_info = {
5820 .mac = e1000_ich10lan,
5821 .flags = FLAG_HAS_JUMBO_FRAMES
5822 | FLAG_IS_ICH
5823 | FLAG_HAS_WOL
5824 | FLAG_HAS_CTRLEXT_ON_LOAD
5825 | FLAG_HAS_AMT
5826 | FLAG_HAS_FLASH
5827 | FLAG_APME_IN_WUC,
5828 .pba = 18,
5829 .max_hw_frame_size = DEFAULT_JUMBO,
5830 .get_variants = e1000_get_variants_ich8lan,
5831 .mac_ops = &ich8_mac_ops,
5832 .phy_ops = &ich8_phy_ops,
5833 .nvm_ops = &ich8_nvm_ops,
5834 };
5835
5836 const struct e1000_info e1000_pch_info = {
5837 .mac = e1000_pchlan,
5838 .flags = FLAG_IS_ICH
5839 | FLAG_HAS_WOL
5840 | FLAG_HAS_CTRLEXT_ON_LOAD
5841 | FLAG_HAS_AMT
5842 | FLAG_HAS_FLASH
5843 | FLAG_HAS_JUMBO_FRAMES
5844 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5845 | FLAG_APME_IN_WUC,
5846 .flags2 = FLAG2_HAS_PHY_STATS,
5847 .pba = 26,
5848 .max_hw_frame_size = 4096,
5849 .get_variants = e1000_get_variants_ich8lan,
5850 .mac_ops = &ich8_mac_ops,
5851 .phy_ops = &ich8_phy_ops,
5852 .nvm_ops = &ich8_nvm_ops,
5853 };
5854
5855 const struct e1000_info e1000_pch2_info = {
5856 .mac = e1000_pch2lan,
5857 .flags = FLAG_IS_ICH
5858 | FLAG_HAS_WOL
5859 | FLAG_HAS_HW_TIMESTAMP
5860 | FLAG_HAS_CTRLEXT_ON_LOAD
5861 | FLAG_HAS_AMT
5862 | FLAG_HAS_FLASH
5863 | FLAG_HAS_JUMBO_FRAMES
5864 | FLAG_APME_IN_WUC,
5865 .flags2 = FLAG2_HAS_PHY_STATS
5866 | FLAG2_HAS_EEE,
5867 .pba = 26,
5868 .max_hw_frame_size = 9022,
5869 .get_variants = e1000_get_variants_ich8lan,
5870 .mac_ops = &ich8_mac_ops,
5871 .phy_ops = &ich8_phy_ops,
5872 .nvm_ops = &ich8_nvm_ops,
5873 };
5874
5875 const struct e1000_info e1000_pch_lpt_info = {
5876 .mac = e1000_pch_lpt,
5877 .flags = FLAG_IS_ICH
5878 | FLAG_HAS_WOL
5879 | FLAG_HAS_HW_TIMESTAMP
5880 | FLAG_HAS_CTRLEXT_ON_LOAD
5881 | FLAG_HAS_AMT
5882 | FLAG_HAS_FLASH
5883 | FLAG_HAS_JUMBO_FRAMES
5884 | FLAG_APME_IN_WUC,
5885 .flags2 = FLAG2_HAS_PHY_STATS
5886 | FLAG2_HAS_EEE,
5887 .pba = 26,
5888 .max_hw_frame_size = 9022,
5889 .get_variants = e1000_get_variants_ich8lan,
5890 .mac_ops = &ich8_mac_ops,
5891 .phy_ops = &ich8_phy_ops,
5892 .nvm_ops = &ich8_nvm_ops,
5893 };
5894
5895 const struct e1000_info e1000_pch_spt_info = {
5896 .mac = e1000_pch_spt,
5897 .flags = FLAG_IS_ICH
5898 | FLAG_HAS_WOL
5899 | FLAG_HAS_HW_TIMESTAMP
5900 | FLAG_HAS_CTRLEXT_ON_LOAD
5901 | FLAG_HAS_AMT
5902 | FLAG_HAS_FLASH
5903 | FLAG_HAS_JUMBO_FRAMES
5904 | FLAG_APME_IN_WUC,
5905 .flags2 = FLAG2_HAS_PHY_STATS
5906 | FLAG2_HAS_EEE,
5907 .pba = 26,
5908 .max_hw_frame_size = 9022,
5909 .get_variants = e1000_get_variants_ich8lan,
5910 .mac_ops = &ich8_mac_ops,
5911 .phy_ops = &ich8_phy_ops,
5912 .nvm_ops = &spt_nvm_ops,
5913 };
Linux kernel - Deliverables
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