drivers/net/ethernet/intel/e1000e/ich8lan.h

   1 /* Intel PRO/1000 Linux driver
   2  * Copyright(c) 1999 - 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  *
  16  * Contact Information:
  17  * Linux NICS <linux.nics@intel.com>
  18  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  19  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  20  */
  21
  22 #ifndef _E1000E_ICH8LAN_H_
  23 #define _E1000E_ICH8LAN_H_
  24
  25 #define ICH_FLASH_GFPREG                0x0000
  26 #define ICH_FLASH_HSFSTS                0x0004
  27 #define ICH_FLASH_HSFCTL                0x0006
  28 #define ICH_FLASH_FADDR                 0x0008
  29 #define ICH_FLASH_FDATA0                0x0010
  30 #define ICH_FLASH_PR0                   0x0074
  31
  32 /* Requires up to 10 seconds when MNG might be accessing part. */
  33 #define ICH_FLASH_READ_COMMAND_TIMEOUT  10000000
  34 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
  35 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
  36 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  37 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  38
  39 #define ICH_CYCLE_READ                  0
  40 #define ICH_CYCLE_WRITE                 2
  41 #define ICH_CYCLE_ERASE                 3
  42
  43 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  44 #define FLASH_SECTOR_ADDR_SHIFT         12
  45
  46 #define ICH_FLASH_SEG_SIZE_256          256
  47 #define ICH_FLASH_SEG_SIZE_4K           4096
  48 #define ICH_FLASH_SEG_SIZE_8K           8192
  49 #define ICH_FLASH_SEG_SIZE_64K          65536
  50
  51 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040      /* Reset PHY on PCI Reset */
  52 /* FW established a valid mode */
  53 #define E1000_ICH_FWSM_FW_VALID 0x00008000
  54 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000      /* ME PCIm-to-PCI active */
  55 #define E1000_ICH_FWSM_PCIM2PCI_COUNT   2000
  56
  57 #define E1000_ICH_MNG_IAMT_MODE         0x2
  58
  59 #define E1000_FWSM_WLOCK_MAC_MASK       0x0380
  60 #define E1000_FWSM_WLOCK_MAC_SHIFT      7
  61 #define E1000_FWSM_ULP_CFG_DONE         0x00000400      /* Low power cfg done */
  62
  63 /* Shared Receive Address Registers */
  64 #define E1000_SHRAL_PCH_LPT(_i)         (0x05408 + ((_i) * 8))
  65 #define E1000_SHRAH_PCH_LPT(_i)         (0x0540C + ((_i) * 8))
  66
  67 #define E1000_H2ME              0x05B50 /* Host to ME */
  68 #define E1000_H2ME_ULP          0x00000800      /* ULP Indication Bit */
  69 #define E1000_H2ME_ENFORCE_SETTINGS     0x00001000      /* Enforce Settings */
  70
  71 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  72                                  (ID_LED_OFF1_OFF2 <<  8) | \
  73                                  (ID_LED_OFF1_ON2  <<  4) | \
  74                                  (ID_LED_DEF1_DEF2))
  75
  76 #define E1000_ICH_NVM_SIG_WORD          0x13
  77 #define E1000_ICH_NVM_SIG_MASK          0xC000
  78 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
  79 #define E1000_ICH_NVM_SIG_VALUE         0x80
  80
  81 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
  82
  83 /* FEXT register bit definition */
  84 #define E1000_FEXT_PHY_CABLE_DISCONNECTED       0x00000004
  85
  86 #define E1000_FEXTNVM_SW_CONFIG         1
  87 #define E1000_FEXTNVM_SW_CONFIG_ICH8M   (1 << 27)       /* different on ICH8M */
  88
  89 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK     0x0C000000
  90 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC   0x08000000
  91
  92 #define E1000_FEXTNVM4_BEACON_DURATION_MASK     0x7
  93 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC    0x7
  94 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC   0x3
  95
  96 #define E1000_FEXTNVM6_REQ_PLL_CLK      0x00000100
  97 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION        0x00000200
  98 #define E1000_FEXTNVM6_K1_OFF_ENABLE    0x80000000
  99 /* bit for disabling packet buffer read */
 100 #define E1000_FEXTNVM7_DISABLE_PB_READ  0x00040000
 101 #define E1000_FEXTNVM7_SIDE_CLK_UNGATE  0x00000004
 102 #define E1000_FEXTNVM7_DISABLE_SMB_PERST        0x00000020
 103 #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS       0x00000800
 104 #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS        0x00001000
 105 #define E1000_FEXTNVM11_DISABLE_PB_READ         0x00000200
 106 #define E1000_FEXTNVM11_DISABLE_MULR_FIX        0x00002000
 107
 108 /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
 109 #define E1000_RXDCTL_THRESH_UNIT_DESC   0x01000000
 110
 111 #define K1_ENTRY_LATENCY        0
 112 #define K1_MIN_TIME             1
 113 #define NVM_SIZE_MULTIPLIER 4096        /*multiplier for NVMS field */
 114 #define E1000_FLASH_BASE_ADDR 0xE000    /*offset of NVM access regs */
 115 #define E1000_CTRL_EXT_NVMVS 0x3        /*NVM valid sector */
 116 #define E1000_TARC0_CB_MULTIQ_3_REQ     (1 << 28 | 1 << 29)
 117 #define PCIE_ICH8_SNOOP_ALL     PCIE_NO_SNOOP_ALL
 118
 119 #define E1000_ICH_RAR_ENTRIES   7
 120 #define E1000_PCH2_RAR_ENTRIES  5       /* RAR[0], SHRA[0-3] */
 121 #define E1000_PCH_LPT_RAR_ENTRIES       12      /* RAR[0], SHRA[0-10] */
 122
 123 #define PHY_PAGE_SHIFT          5
 124 #define PHY_REG(page, reg)      (((page) << PHY_PAGE_SHIFT) | \
 125                                  ((reg) & MAX_PHY_REG_ADDRESS))
 126 #define IGP3_KMRN_DIAG  PHY_REG(770, 19)        /* KMRN Diagnostic */
 127 #define IGP3_VR_CTRL    PHY_REG(776, 18)        /* Voltage Regulator Control */
 128
 129 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS            0x0002
 130 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK    0x0300
 131 #define IGP3_VR_CTRL_MODE_SHUTDOWN              0x0200
 132
 133 /* PHY Wakeup Registers and defines */
 134 #define BM_PORT_GEN_CFG         PHY_REG(BM_PORT_CTRL_PAGE, 17)
 135 #define BM_RCTL                 PHY_REG(BM_WUC_PAGE, 0)
 136 #define BM_WUC                  PHY_REG(BM_WUC_PAGE, 1)
 137 #define BM_WUFC                 PHY_REG(BM_WUC_PAGE, 2)
 138 #define BM_WUS                  PHY_REG(BM_WUC_PAGE, 3)
 139 #define BM_RAR_L(_i)            (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
 140 #define BM_RAR_M(_i)            (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
 141 #define BM_RAR_H(_i)            (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
 142 #define BM_RAR_CTRL(_i)         (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
 143 #define BM_MTA(_i)              (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
 144
 145 #define BM_RCTL_UPE             0x0001  /* Unicast Promiscuous Mode */
 146 #define BM_RCTL_MPE             0x0002  /* Multicast Promiscuous Mode */
 147 #define BM_RCTL_MO_SHIFT        3       /* Multicast Offset Shift */
 148 #define BM_RCTL_MO_MASK         (3 << 3)        /* Multicast Offset Mask */
 149 #define BM_RCTL_BAM             0x0020  /* Broadcast Accept Mode */
 150 #define BM_RCTL_PMCF            0x0040  /* Pass MAC Control Frames */
 151 #define BM_RCTL_RFCE            0x0080  /* Rx Flow Control Enable */
 152
 153 #define HV_LED_CONFIG           PHY_REG(768, 30)        /* LED Configuration */
 154 #define HV_MUX_DATA_CTRL        PHY_REG(776, 16)
 155 #define HV_MUX_DATA_CTRL_GEN_TO_MAC     0x0400
 156 #define HV_MUX_DATA_CTRL_FORCE_SPEED    0x0004
 157 #define HV_STATS_PAGE   778
 158 /* Half-duplex collision counts */
 159 #define HV_SCC_UPPER    PHY_REG(HV_STATS_PAGE, 16)      /* Single Collision */
 160 #define HV_SCC_LOWER    PHY_REG(HV_STATS_PAGE, 17)
 161 #define HV_ECOL_UPPER   PHY_REG(HV_STATS_PAGE, 18)      /* Excessive Coll. */
 162 #define HV_ECOL_LOWER   PHY_REG(HV_STATS_PAGE, 19)
 163 #define HV_MCC_UPPER    PHY_REG(HV_STATS_PAGE, 20)      /* Multiple Collision */
 164 #define HV_MCC_LOWER    PHY_REG(HV_STATS_PAGE, 21)
 165 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23)     /* Late Collision */
 166 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
 167 #define HV_COLC_UPPER   PHY_REG(HV_STATS_PAGE, 25)      /* Collision */
 168 #define HV_COLC_LOWER   PHY_REG(HV_STATS_PAGE, 26)
 169 #define HV_DC_UPPER     PHY_REG(HV_STATS_PAGE, 27)      /* Defer Count */
 170 #define HV_DC_LOWER     PHY_REG(HV_STATS_PAGE, 28)
 171 #define HV_TNCRS_UPPER  PHY_REG(HV_STATS_PAGE, 29)      /* Tx with no CRS */
 172 #define HV_TNCRS_LOWER  PHY_REG(HV_STATS_PAGE, 30)
 173
 174 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
 175
 176 #define E1000_NVM_K1_CONFIG     0x1B    /* NVM K1 Config Word */
 177 #define E1000_NVM_K1_ENABLE     0x1     /* NVM Enable K1 bit */
 178
 179 /* SMBus Control Phy Register */
 180 #define CV_SMB_CTRL             PHY_REG(769, 23)
 181 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001
 182
 183 /* I218 Ultra Low Power Configuration 1 Register */
 184 #define I218_ULP_CONFIG1                PHY_REG(779, 16)
 185 #define I218_ULP_CONFIG1_START          0x0001  /* Start auto ULP config */
 186 #define I218_ULP_CONFIG1_IND            0x0004  /* Pwr up from ULP indication */
 187 #define I218_ULP_CONFIG1_STICKY_ULP     0x0010  /* Set sticky ULP mode */
 188 #define I218_ULP_CONFIG1_INBAND_EXIT    0x0020  /* Inband on ULP exit */
 189 #define I218_ULP_CONFIG1_WOL_HOST       0x0040  /* WoL Host on ULP exit */
 190 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100  /* Reset to SMBus mode */
 191 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST      0x1000  /* Disable on PERST# */
 192
 193 /* SMBus Address Phy Register */
 194 #define HV_SMB_ADDR             PHY_REG(768, 26)
 195 #define HV_SMB_ADDR_MASK        0x007F
 196 #define HV_SMB_ADDR_PEC_EN      0x0200
 197 #define HV_SMB_ADDR_VALID       0x0080
 198 #define HV_SMB_ADDR_FREQ_MASK           0x1100
 199 #define HV_SMB_ADDR_FREQ_LOW_SHIFT      8
 200 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT     12
 201
 202 /* Strapping Option Register - RO */
 203 #define E1000_STRAP                     0x0000C
 204 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 205 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 206 #define E1000_STRAP_SMT_FREQ_MASK       0x00003000
 207 #define E1000_STRAP_SMT_FREQ_SHIFT      12
 208
 209 /* OEM Bits Phy Register */
 210 #define HV_OEM_BITS             PHY_REG(768, 25)
 211 #define HV_OEM_BITS_LPLU        0x0004  /* Low Power Link Up */
 212 #define HV_OEM_BITS_GBE_DIS     0x0040  /* Gigabit Disable */
 213 #define HV_OEM_BITS_RESTART_AN  0x0400  /* Restart Auto-negotiation */
 214
 215 /* KMRN Mode Control */
 216 #define HV_KMRN_MODE_CTRL       PHY_REG(769, 16)
 217 #define HV_KMRN_MDIO_SLOW       0x0400
 218
 219 /* KMRN FIFO Control and Status */
 220 #define HV_KMRN_FIFO_CTRLSTA                    PHY_REG(770, 16)
 221 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK      0x7000
 222 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT     12
 223
 224 /* PHY Power Management Control */
 225 #define HV_PM_CTRL              PHY_REG(770, 17)
 226 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA  0x100
 227 #define HV_PM_CTRL_K1_ENABLE            0x4000
 228
 229 #define SW_FLAG_TIMEOUT         1000    /* SW Semaphore flag timeout in ms */
 230
 231 /* Inband Control */
 232 #define I217_INBAND_CTRL                                PHY_REG(770, 18)
 233 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK      0x3F00
 234 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT     8
 235
 236 /* Low Power Idle GPIO Control */
 237 #define I217_LPI_GPIO_CTRL                      PHY_REG(772, 18)
 238 #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI          0x0800
 239
 240 /* PHY Low Power Idle Control */
 241 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 242 #define I82579_LPI_CTRL_100_ENABLE              0x2000
 243 #define I82579_LPI_CTRL_1000_ENABLE             0x4000
 244 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 245 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
 246
 247 /* Extended Management Interface (EMI) Registers */
 248 #define I82579_EMI_ADDR         0x10
 249 #define I82579_EMI_DATA         0x11
 250 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 251 #define I82579_MSE_THRESHOLD    0x084F  /* 82579 Mean Square Error Threshold */
 252 #define I82577_MSE_THRESHOLD    0x0887  /* 82577 Mean Square Error Threshold */
 253 #define I82579_MSE_LINK_DOWN    0x2411  /* MSE count before dropping link */
 254 #define I82579_RX_CONFIG                0x3412  /* Receive configuration */
 255 #define I82579_LPI_PLL_SHUT             0x4412  /* LPI PLL Shut Enable */
 256 #define I82579_EEE_PCS_STATUS           0x182E  /* IEEE MMD Register 3.1 >> 8 */
 257 #define I82579_EEE_CAPABILITY           0x0410  /* IEEE MMD Register 3.20 */
 258 #define I82579_EEE_ADVERTISEMENT        0x040E  /* IEEE MMD Register 7.60 */
 259 #define I82579_EEE_LP_ABILITY           0x040F  /* IEEE MMD Register 7.61 */
 260 #define I82579_EEE_100_SUPPORTED        (1 << 1)        /* 100BaseTx EEE */
 261 #define I82579_EEE_1000_SUPPORTED       (1 << 2)        /* 1000BaseTx EEE */
 262 #define I82579_LPI_100_PLL_SHUT (1 << 2)        /* 100M LPI PLL Shut Enabled */
 263 #define I217_EEE_PCS_STATUS     0x9401  /* IEEE MMD Register 3.1 */
 264 #define I217_EEE_CAPABILITY     0x8000  /* IEEE MMD Register 3.20 */
 265 #define I217_EEE_ADVERTISEMENT  0x8001  /* IEEE MMD Register 7.60 */
 266 #define I217_EEE_LP_ABILITY     0x8002  /* IEEE MMD Register 7.61 */
 267 #define I217_RX_CONFIG          0xB20C  /* Receive configuration */
 268
 269 #define E1000_EEE_RX_LPI_RCVD   0x0400  /* Tx LP idle received */
 270 #define E1000_EEE_TX_LPI_RCVD   0x0800  /* Rx LP idle received */
 271
 272 /* Intel Rapid Start Technology Support */
 273 #define I217_PROXY_CTRL         BM_PHY_REG(BM_WUC_PAGE, 70)
 274 #define I217_PROXY_CTRL_AUTO_DISABLE    0x0080
 275 #define I217_SxCTRL                     PHY_REG(BM_PORT_CTRL_PAGE, 28)
 276 #define I217_SxCTRL_ENABLE_LPI_RESET    0x1000
 277 #define I217_CGFREG                     PHY_REG(772, 29)
 278 #define I217_CGFREG_ENABLE_MTA_RESET    0x0002
 279 #define I217_MEMPWR                     PHY_REG(772, 26)
 280 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010
 281
 282 /* Receive Address Initial CRC Calculation */
 283 #define E1000_PCH_RAICC(_n)     (0x05F50 + ((_n) * 4))
 284
 285 /* Latency Tolerance Reporting */
 286 #define E1000_LTRV                      0x000F8
 287 #define E1000_LTRV_SCALE_MAX            5
 288 #define E1000_LTRV_SCALE_FACTOR         5
 289 #define E1000_LTRV_REQ_SHIFT            15
 290 #define E1000_LTRV_NOSNOOP_SHIFT        16
 291 #define E1000_LTRV_SEND                 (1 << 30)
 292
 293 /* Proprietary Latency Tolerance Reporting PCI Capability */
 294 #define E1000_PCI_LTR_CAP_LPT           0xA8
 295
 296 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
 297 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
 298                                                   bool state);
 299 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 300 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
 301 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
 302 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
 303 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
 304 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
 305 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
 306 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data);
 307 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data);
 308 s32 e1000_set_eee_pchlan(struct e1000_hw *hw);
 309 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx);
 310 #endif /* _E1000E_ICH8LAN_H_ */