1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
);
32 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
33 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
);
34 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
);
35 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
);
36 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
37 u16
*data
, bool read
, bool page_set
);
38 static u32
e1000_get_phy_addr_for_hv_page(u32 page
);
39 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
40 u16
*data
, bool read
);
42 /* Cable length tables */
43 static const u16 e1000_m88_cable_length_table
[] = {
44 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
46 ARRAY_SIZE(e1000_m88_cable_length_table)
48 static const u16 e1000_igp_2_cable_length_table
[] = {
49 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
60 #define BM_PHY_REG_PAGE(offset) \
61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62 #define BM_PHY_REG_NUM(offset) \
63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65 ~MAX_PHY_REG_ADDRESS)))
67 #define HV_INTC_FC_PAGE_START 768
68 #define I82578_ADDR_REG 29
69 #define I82577_ADDR_REG 16
70 #define I82577_CFG_REG 22
71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73 #define I82577_CTRL_REG 23
75 /* 82577 specific PHY registers */
76 #define I82577_PHY_CTRL_2 18
77 #define I82577_PHY_STATUS_2 26
78 #define I82577_PHY_DIAG_STATUS 31
80 /* I82577 PHY Status 2 */
81 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
82 #define I82577_PHY_STATUS2_MDIX 0x0800
83 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
84 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
86 /* I82577 PHY Control 2 */
87 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
88 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
90 /* I82577 PHY Diagnostics Status */
91 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
92 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
94 /* BM PHY Copper Specific Control 1 */
95 #define BM_CS_CTRL1 16
97 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
98 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
99 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
102 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
103 * @hw: pointer to the HW structure
105 * Read the PHY management control register and check whether a PHY reset
106 * is blocked. If a reset is not blocked return 0, otherwise
107 * return E1000_BLK_PHY_RESET (12).
109 s32
e1000e_check_reset_block_generic(struct e1000_hw
*hw
)
115 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
116 E1000_BLK_PHY_RESET
: 0;
120 * e1000e_get_phy_id - Retrieve the PHY ID and revision
121 * @hw: pointer to the HW structure
123 * Reads the PHY registers and stores the PHY ID and possibly the PHY
124 * revision in the hardware structure.
126 s32
e1000e_get_phy_id(struct e1000_hw
*hw
)
128 struct e1000_phy_info
*phy
= &hw
->phy
;
133 if (!phy
->ops
.read_reg
)
136 while (retry_count
< 2) {
137 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
141 phy
->id
= (u32
)(phy_id
<< 16);
143 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
147 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
148 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
150 if (phy
->id
!= 0 && phy
->id
!= PHY_REVISION_MASK
)
160 * e1000e_phy_reset_dsp - Reset PHY DSP
161 * @hw: pointer to the HW structure
163 * Reset the digital signal processor.
165 s32
e1000e_phy_reset_dsp(struct e1000_hw
*hw
)
169 ret_val
= e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
173 return e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
177 * e1000e_read_phy_reg_mdic - Read MDI control register
178 * @hw: pointer to the HW structure
179 * @offset: register offset to be read
180 * @data: pointer to the read data
182 * Reads the MDI control register in the PHY at offset and stores the
183 * information read to data.
185 s32
e1000e_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
187 struct e1000_phy_info
*phy
= &hw
->phy
;
190 if (offset
> MAX_PHY_REG_ADDRESS
) {
191 e_dbg("PHY Address %d is out of range\n", offset
);
192 return -E1000_ERR_PARAM
;
196 * Set up Op-code, Phy Address, and register offset in the MDI
197 * Control register. The MAC will take care of interfacing with the
198 * PHY to retrieve the desired data.
200 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
201 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
202 (E1000_MDIC_OP_READ
));
207 * Poll the ready bit to see if the MDI read completed
208 * Increasing the time out as testing showed failures with
211 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
214 if (mdic
& E1000_MDIC_READY
)
217 if (!(mdic
& E1000_MDIC_READY
)) {
218 e_dbg("MDI Read did not complete\n");
219 return -E1000_ERR_PHY
;
221 if (mdic
& E1000_MDIC_ERROR
) {
222 e_dbg("MDI Error\n");
223 return -E1000_ERR_PHY
;
228 * Allow some time after each MDIC transaction to avoid
229 * reading duplicate data in the next MDIC transaction.
231 if (hw
->mac
.type
== e1000_pch2lan
)
238 * e1000e_write_phy_reg_mdic - Write MDI control register
239 * @hw: pointer to the HW structure
240 * @offset: register offset to write to
241 * @data: data to write to register at offset
243 * Writes data to MDI control register in the PHY at offset.
245 s32
e1000e_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
247 struct e1000_phy_info
*phy
= &hw
->phy
;
250 if (offset
> MAX_PHY_REG_ADDRESS
) {
251 e_dbg("PHY Address %d is out of range\n", offset
);
252 return -E1000_ERR_PARAM
;
256 * Set up Op-code, Phy Address, and register offset in the MDI
257 * Control register. The MAC will take care of interfacing with the
258 * PHY to retrieve the desired data.
260 mdic
= (((u32
)data
) |
261 (offset
<< E1000_MDIC_REG_SHIFT
) |
262 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
263 (E1000_MDIC_OP_WRITE
));
268 * Poll the ready bit to see if the MDI read completed
269 * Increasing the time out as testing showed failures with
272 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
275 if (mdic
& E1000_MDIC_READY
)
278 if (!(mdic
& E1000_MDIC_READY
)) {
279 e_dbg("MDI Write did not complete\n");
280 return -E1000_ERR_PHY
;
282 if (mdic
& E1000_MDIC_ERROR
) {
283 e_dbg("MDI Error\n");
284 return -E1000_ERR_PHY
;
288 * Allow some time after each MDIC transaction to avoid
289 * reading duplicate data in the next MDIC transaction.
291 if (hw
->mac
.type
== e1000_pch2lan
)
298 * e1000e_read_phy_reg_m88 - Read m88 PHY register
299 * @hw: pointer to the HW structure
300 * @offset: register offset to be read
301 * @data: pointer to the read data
303 * Acquires semaphore, if necessary, then reads the PHY register at offset
304 * and storing the retrieved information in data. Release any acquired
305 * semaphores before exiting.
307 s32
e1000e_read_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
311 ret_val
= hw
->phy
.ops
.acquire(hw
);
315 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
318 hw
->phy
.ops
.release(hw
);
324 * e1000e_write_phy_reg_m88 - Write m88 PHY register
325 * @hw: pointer to the HW structure
326 * @offset: register offset to write to
327 * @data: data to write at register offset
329 * Acquires semaphore, if necessary, then writes the data to PHY register
330 * at the offset. Release any acquired semaphores before exiting.
332 s32
e1000e_write_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16 data
)
336 ret_val
= hw
->phy
.ops
.acquire(hw
);
340 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
343 hw
->phy
.ops
.release(hw
);
349 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
350 * @hw: pointer to the HW structure
351 * @page: page to set (shifted left when necessary)
353 * Sets PHY page required for PHY register access. Assumes semaphore is
354 * already acquired. Note, this function sets phy.addr to 1 so the caller
355 * must set it appropriately (if necessary) after this function returns.
357 s32
e1000_set_page_igp(struct e1000_hw
*hw
, u16 page
)
359 e_dbg("Setting page 0x%x\n", page
);
363 return e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
, page
);
367 * __e1000e_read_phy_reg_igp - Read igp PHY register
368 * @hw: pointer to the HW structure
369 * @offset: register offset to be read
370 * @data: pointer to the read data
371 * @locked: semaphore has already been acquired or not
373 * Acquires semaphore, if necessary, then reads the PHY register at offset
374 * and stores the retrieved information in data. Release any acquired
375 * semaphores before exiting.
377 static s32
__e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
383 if (!hw
->phy
.ops
.acquire
)
386 ret_val
= hw
->phy
.ops
.acquire(hw
);
391 if (offset
> MAX_PHY_MULTI_PAGE_REG
)
392 ret_val
= e1000e_write_phy_reg_mdic(hw
,
393 IGP01E1000_PHY_PAGE_SELECT
,
396 ret_val
= e1000e_read_phy_reg_mdic(hw
,
397 MAX_PHY_REG_ADDRESS
& offset
,
400 hw
->phy
.ops
.release(hw
);
406 * e1000e_read_phy_reg_igp - Read igp PHY register
407 * @hw: pointer to the HW structure
408 * @offset: register offset to be read
409 * @data: pointer to the read data
411 * Acquires semaphore then reads the PHY register at offset and stores the
412 * retrieved information in data.
413 * Release the acquired semaphore before exiting.
415 s32
e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
417 return __e1000e_read_phy_reg_igp(hw
, offset
, data
, false);
421 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
422 * @hw: pointer to the HW structure
423 * @offset: register offset to be read
424 * @data: pointer to the read data
426 * Reads the PHY register at offset and stores the retrieved information
427 * in data. Assumes semaphore already acquired.
429 s32
e1000e_read_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
431 return __e1000e_read_phy_reg_igp(hw
, offset
, data
, true);
435 * e1000e_write_phy_reg_igp - Write igp PHY register
436 * @hw: pointer to the HW structure
437 * @offset: register offset to write to
438 * @data: data to write at register offset
439 * @locked: semaphore has already been acquired or not
441 * Acquires semaphore, if necessary, then writes the data to PHY register
442 * at the offset. Release any acquired semaphores before exiting.
444 static s32
__e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
,
450 if (!hw
->phy
.ops
.acquire
)
453 ret_val
= hw
->phy
.ops
.acquire(hw
);
458 if (offset
> MAX_PHY_MULTI_PAGE_REG
)
459 ret_val
= e1000e_write_phy_reg_mdic(hw
,
460 IGP01E1000_PHY_PAGE_SELECT
,
463 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
&
467 hw
->phy
.ops
.release(hw
);
473 * e1000e_write_phy_reg_igp - Write igp PHY register
474 * @hw: pointer to the HW structure
475 * @offset: register offset to write to
476 * @data: data to write at register offset
478 * Acquires semaphore then writes the data to PHY register
479 * at the offset. Release any acquired semaphores before exiting.
481 s32
e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
483 return __e1000e_write_phy_reg_igp(hw
, offset
, data
, false);
487 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
488 * @hw: pointer to the HW structure
489 * @offset: register offset to write to
490 * @data: data to write at register offset
492 * Writes the data to PHY register at the offset.
493 * Assumes semaphore already acquired.
495 s32
e1000e_write_phy_reg_igp_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
497 return __e1000e_write_phy_reg_igp(hw
, offset
, data
, true);
501 * __e1000_read_kmrn_reg - Read kumeran register
502 * @hw: pointer to the HW structure
503 * @offset: register offset to be read
504 * @data: pointer to the read data
505 * @locked: semaphore has already been acquired or not
507 * Acquires semaphore, if necessary. Then reads the PHY register at offset
508 * using the kumeran interface. The information retrieved is stored in data.
509 * Release any acquired semaphores before exiting.
511 static s32
__e1000_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
519 if (!hw
->phy
.ops
.acquire
)
522 ret_val
= hw
->phy
.ops
.acquire(hw
);
527 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
528 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
529 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
534 kmrnctrlsta
= er32(KMRNCTRLSTA
);
535 *data
= (u16
)kmrnctrlsta
;
538 hw
->phy
.ops
.release(hw
);
544 * e1000e_read_kmrn_reg - Read kumeran register
545 * @hw: pointer to the HW structure
546 * @offset: register offset to be read
547 * @data: pointer to the read data
549 * Acquires semaphore then reads the PHY register at offset using the
550 * kumeran interface. The information retrieved is stored in data.
551 * Release the acquired semaphore before exiting.
553 s32
e1000e_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
555 return __e1000_read_kmrn_reg(hw
, offset
, data
, false);
559 * e1000e_read_kmrn_reg_locked - Read kumeran register
560 * @hw: pointer to the HW structure
561 * @offset: register offset to be read
562 * @data: pointer to the read data
564 * Reads the PHY register at offset using the kumeran interface. The
565 * information retrieved is stored in data.
566 * Assumes semaphore already acquired.
568 s32
e1000e_read_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
570 return __e1000_read_kmrn_reg(hw
, offset
, data
, true);
574 * __e1000_write_kmrn_reg - Write kumeran register
575 * @hw: pointer to the HW structure
576 * @offset: register offset to write to
577 * @data: data to write at register offset
578 * @locked: semaphore has already been acquired or not
580 * Acquires semaphore, if necessary. Then write the data to PHY register
581 * at the offset using the kumeran interface. Release any acquired semaphores
584 static s32
__e1000_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
,
592 if (!hw
->phy
.ops
.acquire
)
595 ret_val
= hw
->phy
.ops
.acquire(hw
);
600 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
601 E1000_KMRNCTRLSTA_OFFSET
) | data
;
602 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
608 hw
->phy
.ops
.release(hw
);
614 * e1000e_write_kmrn_reg - Write kumeran register
615 * @hw: pointer to the HW structure
616 * @offset: register offset to write to
617 * @data: data to write at register offset
619 * Acquires semaphore then writes the data to the PHY register at the offset
620 * using the kumeran interface. Release the acquired semaphore before exiting.
622 s32
e1000e_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
624 return __e1000_write_kmrn_reg(hw
, offset
, data
, false);
628 * e1000e_write_kmrn_reg_locked - Write kumeran register
629 * @hw: pointer to the HW structure
630 * @offset: register offset to write to
631 * @data: data to write at register offset
633 * Write the data to PHY register at the offset using the kumeran interface.
634 * Assumes semaphore already acquired.
636 s32
e1000e_write_kmrn_reg_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
638 return __e1000_write_kmrn_reg(hw
, offset
, data
, true);
642 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
643 * @hw: pointer to the HW structure
645 * Sets up Carrier-sense on Transmit and downshift values.
647 s32
e1000_copper_link_setup_82577(struct e1000_hw
*hw
)
652 /* Enable CRS on Tx. This must be set for half-duplex operation. */
653 ret_val
= e1e_rphy(hw
, I82577_CFG_REG
, &phy_data
);
657 phy_data
|= I82577_CFG_ASSERT_CRS_ON_TX
;
659 /* Enable downshift */
660 phy_data
|= I82577_CFG_ENABLE_DOWNSHIFT
;
662 return e1e_wphy(hw
, I82577_CFG_REG
, phy_data
);
666 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
667 * @hw: pointer to the HW structure
669 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
670 * and downshift values are set also.
672 s32
e1000e_copper_link_setup_m88(struct e1000_hw
*hw
)
674 struct e1000_phy_info
*phy
= &hw
->phy
;
678 /* Enable CRS on Tx. This must be set for half-duplex operation. */
679 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
683 /* For BM PHY this bit is downshift enable */
684 if (phy
->type
!= e1000_phy_bm
)
685 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
689 * MDI/MDI-X = 0 (default)
690 * 0 - Auto for all speeds
693 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
695 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
699 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
702 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
705 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
709 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
715 * disable_polarity_correction = 0 (default)
716 * Automatic Correction for Reversed Cable Polarity
720 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
721 if (phy
->disable_polarity_correction
)
722 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
724 /* Enable downshift on BM (disabled by default) */
725 if (phy
->type
== e1000_phy_bm
)
726 phy_data
|= BME1000_PSCR_ENABLE_DOWNSHIFT
;
728 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
732 if ((phy
->type
== e1000_phy_m88
) &&
733 (phy
->revision
< E1000_REVISION_4
) &&
734 (phy
->id
!= BME1000_E_PHY_ID_R2
)) {
736 * Force TX_CLK in the Extended PHY Specific Control Register
739 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
743 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
745 if ((phy
->revision
== 2) &&
746 (phy
->id
== M88E1111_I_PHY_ID
)) {
747 /* 82573L PHY - set the downshift counter to 5x. */
748 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
749 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
751 /* Configure Master and Slave downshift values */
752 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
753 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
754 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
755 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
757 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
762 if ((phy
->type
== e1000_phy_bm
) && (phy
->id
== BME1000_E_PHY_ID_R2
)) {
763 /* Set PHY page 0, register 29 to 0x0003 */
764 ret_val
= e1e_wphy(hw
, 29, 0x0003);
768 /* Set PHY page 0, register 30 to 0x0000 */
769 ret_val
= e1e_wphy(hw
, 30, 0x0000);
774 /* Commit the changes. */
775 ret_val
= e1000e_commit_phy(hw
);
777 e_dbg("Error committing the PHY changes\n");
781 if (phy
->type
== e1000_phy_82578
) {
782 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
786 /* 82578 PHY - set the downshift count to 1x. */
787 phy_data
|= I82578_EPSCR_DOWNSHIFT_ENABLE
;
788 phy_data
&= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK
;
789 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
798 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
799 * @hw: pointer to the HW structure
801 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
804 s32
e1000e_copper_link_setup_igp(struct e1000_hw
*hw
)
806 struct e1000_phy_info
*phy
= &hw
->phy
;
810 ret_val
= e1000_phy_hw_reset(hw
);
812 e_dbg("Error resetting the PHY.\n");
817 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
818 * timeout issues when LFS is enabled.
822 /* disable lplu d0 during driver init */
823 ret_val
= e1000_set_d0_lplu_state(hw
, false);
825 e_dbg("Error Disabling LPLU D0\n");
828 /* Configure mdi-mdix settings */
829 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
833 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
837 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
840 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
844 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
847 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
851 /* set auto-master slave resolution settings */
852 if (hw
->mac
.autoneg
) {
854 * when autonegotiation advertisement is only 1000Mbps then we
855 * should disable SmartSpeed and enable Auto MasterSlave
856 * resolution as hardware default.
858 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
859 /* Disable SmartSpeed */
860 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
865 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
866 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
871 /* Set auto Master/Slave resolution process */
872 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
876 data
&= ~CR_1000T_MS_ENABLE
;
877 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
882 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
886 /* load defaults for future use */
887 phy
->original_ms_type
= (data
& CR_1000T_MS_ENABLE
) ?
888 ((data
& CR_1000T_MS_VALUE
) ?
889 e1000_ms_force_master
:
890 e1000_ms_force_slave
) :
893 switch (phy
->ms_type
) {
894 case e1000_ms_force_master
:
895 data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
897 case e1000_ms_force_slave
:
898 data
|= CR_1000T_MS_ENABLE
;
899 data
&= ~(CR_1000T_MS_VALUE
);
902 data
&= ~CR_1000T_MS_ENABLE
;
906 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
913 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
914 * @hw: pointer to the HW structure
916 * Reads the MII auto-neg advertisement register and/or the 1000T control
917 * register and if the PHY is already setup for auto-negotiation, then
918 * return successful. Otherwise, setup advertisement and flow control to
919 * the appropriate values for the wanted auto-negotiation.
921 static s32
e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
923 struct e1000_phy_info
*phy
= &hw
->phy
;
925 u16 mii_autoneg_adv_reg
;
926 u16 mii_1000t_ctrl_reg
= 0;
928 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
930 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
931 ret_val
= e1e_rphy(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
935 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
936 /* Read the MII 1000Base-T Control Register (Address 9). */
937 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
943 * Need to parse both autoneg_advertised and fc and set up
944 * the appropriate PHY registers. First we will parse for
945 * autoneg_advertised software override. Since we can advertise
946 * a plethora of combinations, we need to check each bit
951 * First we clear all the 10/100 mb speed bits in the Auto-Neg
952 * Advertisement Register (Address 4) and the 1000 mb speed bits in
953 * the 1000Base-T Control Register (Address 9).
955 mii_autoneg_adv_reg
&= ~(NWAY_AR_100TX_FD_CAPS
|
956 NWAY_AR_100TX_HD_CAPS
|
957 NWAY_AR_10T_FD_CAPS
|
958 NWAY_AR_10T_HD_CAPS
);
959 mii_1000t_ctrl_reg
&= ~(CR_1000T_HD_CAPS
| CR_1000T_FD_CAPS
);
961 e_dbg("autoneg_advertised %x\n", phy
->autoneg_advertised
);
963 /* Do we want to advertise 10 Mb Half Duplex? */
964 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
965 e_dbg("Advertise 10mb Half duplex\n");
966 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
969 /* Do we want to advertise 10 Mb Full Duplex? */
970 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
971 e_dbg("Advertise 10mb Full duplex\n");
972 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
975 /* Do we want to advertise 100 Mb Half Duplex? */
976 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
977 e_dbg("Advertise 100mb Half duplex\n");
978 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
981 /* Do we want to advertise 100 Mb Full Duplex? */
982 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
983 e_dbg("Advertise 100mb Full duplex\n");
984 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
987 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
988 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
)
989 e_dbg("Advertise 1000mb Half duplex request denied!\n");
991 /* Do we want to advertise 1000 Mb Full Duplex? */
992 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
993 e_dbg("Advertise 1000mb Full duplex\n");
994 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
998 * Check for a software override of the flow control settings, and
999 * setup the PHY advertisement registers accordingly. If
1000 * auto-negotiation is enabled, then software will have to set the
1001 * "PAUSE" bits to the correct value in the Auto-Negotiation
1002 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1005 * The possible values of the "fc" parameter are:
1006 * 0: Flow control is completely disabled
1007 * 1: Rx flow control is enabled (we can receive pause frames
1008 * but not send pause frames).
1009 * 2: Tx flow control is enabled (we can send pause frames
1010 * but we do not support receiving pause frames).
1011 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1012 * other: No software override. The flow control configuration
1013 * in the EEPROM is used.
1015 switch (hw
->fc
.current_mode
) {
1018 * Flow control (Rx & Tx) is completely disabled by a
1019 * software over-ride.
1021 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1023 case e1000_fc_rx_pause
:
1025 * Rx Flow control is enabled, and Tx Flow control is
1026 * disabled, by a software over-ride.
1028 * Since there really isn't a way to advertise that we are
1029 * capable of Rx Pause ONLY, we will advertise that we
1030 * support both symmetric and asymmetric Rx PAUSE. Later
1031 * (in e1000e_config_fc_after_link_up) we will disable the
1032 * hw's ability to send PAUSE frames.
1034 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1036 case e1000_fc_tx_pause
:
1038 * Tx Flow control is enabled, and Rx Flow control is
1039 * disabled, by a software over-ride.
1041 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
1042 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
1046 * Flow control (both Rx and Tx) is enabled by a software
1049 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
1052 e_dbg("Flow control param set incorrectly\n");
1053 return -E1000_ERR_CONFIG
;
1056 ret_val
= e1e_wphy(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
1060 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
1062 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
)
1063 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
1069 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1070 * @hw: pointer to the HW structure
1072 * Performs initial bounds checking on autoneg advertisement parameter, then
1073 * configure to advertise the full capability. Setup the PHY to autoneg
1074 * and restart the negotiation process between the link partner. If
1075 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1077 static s32
e1000_copper_link_autoneg(struct e1000_hw
*hw
)
1079 struct e1000_phy_info
*phy
= &hw
->phy
;
1084 * Perform some bounds checking on the autoneg advertisement
1087 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
1090 * If autoneg_advertised is zero, we assume it was not defaulted
1091 * by the calling code so we set to advertise full capability.
1093 if (!phy
->autoneg_advertised
)
1094 phy
->autoneg_advertised
= phy
->autoneg_mask
;
1096 e_dbg("Reconfiguring auto-neg advertisement params\n");
1097 ret_val
= e1000_phy_setup_autoneg(hw
);
1099 e_dbg("Error Setting up Auto-Negotiation\n");
1102 e_dbg("Restarting Auto-Neg\n");
1105 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1106 * the Auto Neg Restart bit in the PHY control register.
1108 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
1112 phy_ctrl
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
1113 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
1118 * Does the user want to wait for Auto-Neg to complete here, or
1119 * check at a later time (for example, callback routine).
1121 if (phy
->autoneg_wait_to_complete
) {
1122 ret_val
= e1000_wait_autoneg(hw
);
1124 e_dbg("Error while waiting for autoneg to complete\n");
1129 hw
->mac
.get_link_status
= true;
1135 * e1000e_setup_copper_link - Configure copper link settings
1136 * @hw: pointer to the HW structure
1138 * Calls the appropriate function to configure the link for auto-neg or forced
1139 * speed and duplex. Then we check for link, once link is established calls
1140 * to configure collision distance and flow control are called. If link is
1141 * not established, we return -E1000_ERR_PHY (-2).
1143 s32
e1000e_setup_copper_link(struct e1000_hw
*hw
)
1148 if (hw
->mac
.autoneg
) {
1150 * Setup autoneg and flow control advertisement and perform
1153 ret_val
= e1000_copper_link_autoneg(hw
);
1158 * PHY will be set to 10H, 10F, 100H or 100F
1159 * depending on user settings.
1161 e_dbg("Forcing Speed and Duplex\n");
1162 ret_val
= e1000_phy_force_speed_duplex(hw
);
1164 e_dbg("Error Forcing Speed and Duplex\n");
1170 * Check link status. Wait up to 100 microseconds for link to become
1173 ret_val
= e1000e_phy_has_link_generic(hw
, COPPER_LINK_UP_LIMIT
, 10,
1179 e_dbg("Valid link established!!!\n");
1180 hw
->mac
.ops
.config_collision_dist(hw
);
1181 ret_val
= e1000e_config_fc_after_link_up(hw
);
1183 e_dbg("Unable to establish link!!!\n");
1190 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1191 * @hw: pointer to the HW structure
1193 * Calls the PHY setup function to force speed and duplex. Clears the
1194 * auto-crossover to force MDI manually. Waits for link and returns
1195 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1197 s32
e1000e_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
1199 struct e1000_phy_info
*phy
= &hw
->phy
;
1204 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
1208 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1210 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
1215 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1216 * forced whenever speed and duplex are forced.
1218 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1222 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1223 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1225 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1229 e_dbg("IGP PSCR: %X\n", phy_data
);
1233 if (phy
->autoneg_wait_to_complete
) {
1234 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1236 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1242 e_dbg("Link taking longer than expected.\n");
1245 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1253 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1254 * @hw: pointer to the HW structure
1256 * Calls the PHY setup function to force speed and duplex. Clears the
1257 * auto-crossover to force MDI manually. Resets the PHY to commit the
1258 * changes. If time expires while waiting for link up, we reset the DSP.
1259 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1260 * successful completion, else return corresponding error code.
1262 s32
e1000e_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
1264 struct e1000_phy_info
*phy
= &hw
->phy
;
1270 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1271 * forced whenever speed and duplex are forced.
1273 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1277 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1278 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1282 e_dbg("M88E1000 PSCR: %X\n", phy_data
);
1284 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
1288 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1290 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
1294 /* Reset the phy to commit changes. */
1295 ret_val
= e1000e_commit_phy(hw
);
1299 if (phy
->autoneg_wait_to_complete
) {
1300 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1302 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1308 if (hw
->phy
.type
!= e1000_phy_m88
) {
1309 e_dbg("Link taking longer than expected.\n");
1312 * We didn't get link.
1313 * Reset the DSP and cross our fingers.
1315 ret_val
= e1e_wphy(hw
, M88E1000_PHY_PAGE_SELECT
,
1319 ret_val
= e1000e_phy_reset_dsp(hw
);
1326 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1332 if (hw
->phy
.type
!= e1000_phy_m88
)
1335 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1340 * Resetting the phy means we need to re-force TX_CLK in the
1341 * Extended PHY Specific Control Register to 25MHz clock from
1342 * the reset value of 2.5MHz.
1344 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1345 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1350 * In addition, we must re-enable CRS on Tx for both half and full
1353 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1357 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1358 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1364 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1365 * @hw: pointer to the HW structure
1367 * Forces the speed and duplex settings of the PHY.
1368 * This is a function pointer entry point only called by
1369 * PHY setup routines.
1371 s32
e1000_phy_force_speed_duplex_ife(struct e1000_hw
*hw
)
1373 struct e1000_phy_info
*phy
= &hw
->phy
;
1378 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &data
);
1382 e1000e_phy_force_speed_duplex_setup(hw
, &data
);
1384 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, data
);
1388 /* Disable MDI-X support for 10/100 */
1389 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
1393 data
&= ~IFE_PMC_AUTO_MDIX
;
1394 data
&= ~IFE_PMC_FORCE_MDIX
;
1396 ret_val
= e1e_wphy(hw
, IFE_PHY_MDIX_CONTROL
, data
);
1400 e_dbg("IFE PMC: %X\n", data
);
1404 if (phy
->autoneg_wait_to_complete
) {
1405 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1407 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1413 e_dbg("Link taking longer than expected.\n");
1416 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1426 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1427 * @hw: pointer to the HW structure
1428 * @phy_ctrl: pointer to current value of PHY_CONTROL
1430 * Forces speed and duplex on the PHY by doing the following: disable flow
1431 * control, force speed/duplex on the MAC, disable auto speed detection,
1432 * disable auto-negotiation, configure duplex, configure speed, configure
1433 * the collision distance, write configuration to CTRL register. The
1434 * caller must write to the PHY_CONTROL register for these settings to
1437 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw
*hw
, u16
*phy_ctrl
)
1439 struct e1000_mac_info
*mac
= &hw
->mac
;
1442 /* Turn off flow control when forcing speed/duplex */
1443 hw
->fc
.current_mode
= e1000_fc_none
;
1445 /* Force speed/duplex on the mac */
1447 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1448 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1450 /* Disable Auto Speed Detection */
1451 ctrl
&= ~E1000_CTRL_ASDE
;
1453 /* Disable autoneg on the phy */
1454 *phy_ctrl
&= ~MII_CR_AUTO_NEG_EN
;
1456 /* Forcing Full or Half Duplex? */
1457 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1458 ctrl
&= ~E1000_CTRL_FD
;
1459 *phy_ctrl
&= ~MII_CR_FULL_DUPLEX
;
1460 e_dbg("Half Duplex\n");
1462 ctrl
|= E1000_CTRL_FD
;
1463 *phy_ctrl
|= MII_CR_FULL_DUPLEX
;
1464 e_dbg("Full Duplex\n");
1467 /* Forcing 10mb or 100mb? */
1468 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1469 ctrl
|= E1000_CTRL_SPD_100
;
1470 *phy_ctrl
|= MII_CR_SPEED_100
;
1471 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1472 e_dbg("Forcing 100mb\n");
1474 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1475 *phy_ctrl
|= MII_CR_SPEED_10
;
1476 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1477 e_dbg("Forcing 10mb\n");
1480 hw
->mac
.ops
.config_collision_dist(hw
);
1486 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1487 * @hw: pointer to the HW structure
1488 * @active: boolean used to enable/disable lplu
1490 * Success returns 0, Failure returns 1
1492 * The low power link up (lplu) state is set to the power management level D3
1493 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1494 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1495 * is used during Dx states where the power conservation is most important.
1496 * During driver activity, SmartSpeed should be enabled so performance is
1499 s32
e1000e_set_d3_lplu_state(struct e1000_hw
*hw
, bool active
)
1501 struct e1000_phy_info
*phy
= &hw
->phy
;
1505 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
1510 data
&= ~IGP02E1000_PM_D3_LPLU
;
1511 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1515 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1516 * during Dx states where the power conservation is most
1517 * important. During driver activity we should enable
1518 * SmartSpeed, so performance is maintained.
1520 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1521 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1526 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1527 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1531 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1532 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1537 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1538 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1543 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1544 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1545 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1546 data
|= IGP02E1000_PM_D3_LPLU
;
1547 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1551 /* When LPLU is enabled, we should disable SmartSpeed */
1552 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1556 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1557 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1564 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1565 * @hw: pointer to the HW structure
1567 * Success returns 0, Failure returns 1
1569 * A downshift is detected by querying the PHY link health.
1571 s32
e1000e_check_downshift(struct e1000_hw
*hw
)
1573 struct e1000_phy_info
*phy
= &hw
->phy
;
1575 u16 phy_data
, offset
, mask
;
1577 switch (phy
->type
) {
1579 case e1000_phy_gg82563
:
1581 case e1000_phy_82578
:
1582 offset
= M88E1000_PHY_SPEC_STATUS
;
1583 mask
= M88E1000_PSSR_DOWNSHIFT
;
1585 case e1000_phy_igp_2
:
1586 case e1000_phy_igp_3
:
1587 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1588 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1591 /* speed downshift not supported */
1592 phy
->speed_downgraded
= false;
1596 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1599 phy
->speed_downgraded
= !!(phy_data
& mask
);
1605 * e1000_check_polarity_m88 - Checks the polarity.
1606 * @hw: pointer to the HW structure
1608 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1610 * Polarity is determined based on the PHY specific status register.
1612 s32
e1000_check_polarity_m88(struct e1000_hw
*hw
)
1614 struct e1000_phy_info
*phy
= &hw
->phy
;
1618 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1621 phy
->cable_polarity
= (data
& M88E1000_PSSR_REV_POLARITY
)
1622 ? e1000_rev_polarity_reversed
1623 : e1000_rev_polarity_normal
;
1629 * e1000_check_polarity_igp - Checks the polarity.
1630 * @hw: pointer to the HW structure
1632 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1634 * Polarity is determined based on the PHY port status register, and the
1635 * current speed (since there is no polarity at 100Mbps).
1637 s32
e1000_check_polarity_igp(struct e1000_hw
*hw
)
1639 struct e1000_phy_info
*phy
= &hw
->phy
;
1641 u16 data
, offset
, mask
;
1644 * Polarity is determined based on the speed of
1647 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1651 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1652 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1653 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1654 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1657 * This really only applies to 10Mbps since
1658 * there is no polarity for 100Mbps (always 0).
1660 offset
= IGP01E1000_PHY_PORT_STATUS
;
1661 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1664 ret_val
= e1e_rphy(hw
, offset
, &data
);
1667 phy
->cable_polarity
= (data
& mask
)
1668 ? e1000_rev_polarity_reversed
1669 : e1000_rev_polarity_normal
;
1675 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1676 * @hw: pointer to the HW structure
1678 * Polarity is determined on the polarity reversal feature being enabled.
1680 s32
e1000_check_polarity_ife(struct e1000_hw
*hw
)
1682 struct e1000_phy_info
*phy
= &hw
->phy
;
1684 u16 phy_data
, offset
, mask
;
1687 * Polarity is determined based on the reversal feature being enabled.
1689 if (phy
->polarity_correction
) {
1690 offset
= IFE_PHY_EXTENDED_STATUS_CONTROL
;
1691 mask
= IFE_PESC_POLARITY_REVERSED
;
1693 offset
= IFE_PHY_SPECIAL_CONTROL
;
1694 mask
= IFE_PSC_FORCE_POLARITY
;
1697 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1700 phy
->cable_polarity
= (phy_data
& mask
)
1701 ? e1000_rev_polarity_reversed
1702 : e1000_rev_polarity_normal
;
1708 * e1000_wait_autoneg - Wait for auto-neg completion
1709 * @hw: pointer to the HW structure
1711 * Waits for auto-negotiation to complete or for the auto-negotiation time
1712 * limit to expire, which ever happens first.
1714 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
)
1719 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1720 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1721 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1724 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1727 if (phy_status
& MII_SR_AUTONEG_COMPLETE
)
1733 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1740 * e1000e_phy_has_link_generic - Polls PHY for link
1741 * @hw: pointer to the HW structure
1742 * @iterations: number of times to poll for link
1743 * @usec_interval: delay between polling attempts
1744 * @success: pointer to whether polling was successful or not
1746 * Polls the PHY status register for link, 'iterations' number of times.
1748 s32
e1000e_phy_has_link_generic(struct e1000_hw
*hw
, u32 iterations
,
1749 u32 usec_interval
, bool *success
)
1754 for (i
= 0; i
< iterations
; i
++) {
1756 * Some PHYs require the PHY_STATUS register to be read
1757 * twice due to the link bit being sticky. No harm doing
1758 * it across the board.
1760 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1763 * If the first read fails, another entity may have
1764 * ownership of the resources, wait and try again to
1765 * see if they have relinquished the resources yet.
1767 udelay(usec_interval
);
1768 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1771 if (phy_status
& MII_SR_LINK_STATUS
)
1773 if (usec_interval
>= 1000)
1774 mdelay(usec_interval
/1000);
1776 udelay(usec_interval
);
1779 *success
= (i
< iterations
);
1785 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1786 * @hw: pointer to the HW structure
1788 * Reads the PHY specific status register to retrieve the cable length
1789 * information. The cable length is determined by averaging the minimum and
1790 * maximum values to get the "average" cable length. The m88 PHY has four
1791 * possible cable length values, which are:
1792 * Register Value Cable Length
1796 * 3 110 - 140 meters
1799 s32
e1000e_get_cable_length_m88(struct e1000_hw
*hw
)
1801 struct e1000_phy_info
*phy
= &hw
->phy
;
1803 u16 phy_data
, index
;
1805 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1809 index
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
1810 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
1812 if (index
>= M88E1000_CABLE_LENGTH_TABLE_SIZE
- 1)
1813 return -E1000_ERR_PHY
;
1815 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
1816 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+ 1];
1818 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1824 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1825 * @hw: pointer to the HW structure
1827 * The automatic gain control (agc) normalizes the amplitude of the
1828 * received signal, adjusting for the attenuation produced by the
1829 * cable. By reading the AGC registers, which represent the
1830 * combination of coarse and fine gain value, the value can be put
1831 * into a lookup table to obtain the approximate cable length
1834 s32
e1000e_get_cable_length_igp_2(struct e1000_hw
*hw
)
1836 struct e1000_phy_info
*phy
= &hw
->phy
;
1838 u16 phy_data
, i
, agc_value
= 0;
1839 u16 cur_agc_index
, max_agc_index
= 0;
1840 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
1841 static const u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] = {
1842 IGP02E1000_PHY_AGC_A
,
1843 IGP02E1000_PHY_AGC_B
,
1844 IGP02E1000_PHY_AGC_C
,
1845 IGP02E1000_PHY_AGC_D
1848 /* Read the AGC registers for all channels */
1849 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
1850 ret_val
= e1e_rphy(hw
, agc_reg_array
[i
], &phy_data
);
1855 * Getting bits 15:9, which represent the combination of
1856 * coarse and fine gain values. The result is a number
1857 * that can be put into the lookup table to obtain the
1858 * approximate cable length.
1860 cur_agc_index
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
1861 IGP02E1000_AGC_LENGTH_MASK
;
1863 /* Array index bound check. */
1864 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
1865 (cur_agc_index
== 0))
1866 return -E1000_ERR_PHY
;
1868 /* Remove min & max AGC values from calculation. */
1869 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
1870 e1000_igp_2_cable_length_table
[cur_agc_index
])
1871 min_agc_index
= cur_agc_index
;
1872 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
1873 e1000_igp_2_cable_length_table
[cur_agc_index
])
1874 max_agc_index
= cur_agc_index
;
1876 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
1879 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
1880 e1000_igp_2_cable_length_table
[max_agc_index
]);
1881 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
1883 /* Calculate cable length with the error range of +/- 10 meters. */
1884 phy
->min_cable_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
1885 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
1886 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
1888 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1894 * e1000e_get_phy_info_m88 - Retrieve PHY information
1895 * @hw: pointer to the HW structure
1897 * Valid for only copper links. Read the PHY status register (sticky read)
1898 * to verify that link is up. Read the PHY special control register to
1899 * determine the polarity and 10base-T extended distance. Read the PHY
1900 * special status register to determine MDI/MDIx and current speed. If
1901 * speed is 1000, then determine cable length, local and remote receiver.
1903 s32
e1000e_get_phy_info_m88(struct e1000_hw
*hw
)
1905 struct e1000_phy_info
*phy
= &hw
->phy
;
1910 if (phy
->media_type
!= e1000_media_type_copper
) {
1911 e_dbg("Phy info is only valid for copper media\n");
1912 return -E1000_ERR_CONFIG
;
1915 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1920 e_dbg("Phy info is only valid if link is up\n");
1921 return -E1000_ERR_CONFIG
;
1924 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1928 phy
->polarity_correction
= !!(phy_data
&
1929 M88E1000_PSCR_POLARITY_REVERSAL
);
1931 ret_val
= e1000_check_polarity_m88(hw
);
1935 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1939 phy
->is_mdix
= !!(phy_data
& M88E1000_PSSR_MDIX
);
1941 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
1942 ret_val
= e1000_get_cable_length(hw
);
1946 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &phy_data
);
1950 phy
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
)
1951 ? e1000_1000t_rx_status_ok
1952 : e1000_1000t_rx_status_not_ok
;
1954 phy
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
)
1955 ? e1000_1000t_rx_status_ok
1956 : e1000_1000t_rx_status_not_ok
;
1958 /* Set values to "undefined" */
1959 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1960 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1961 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1968 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1969 * @hw: pointer to the HW structure
1971 * Read PHY status to determine if link is up. If link is up, then
1972 * set/determine 10base-T extended distance and polarity correction. Read
1973 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1974 * determine on the cable length, local and remote receiver.
1976 s32
e1000e_get_phy_info_igp(struct e1000_hw
*hw
)
1978 struct e1000_phy_info
*phy
= &hw
->phy
;
1983 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1988 e_dbg("Phy info is only valid if link is up\n");
1989 return -E1000_ERR_CONFIG
;
1992 phy
->polarity_correction
= true;
1994 ret_val
= e1000_check_polarity_igp(hw
);
1998 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
2002 phy
->is_mdix
= !!(data
& IGP01E1000_PSSR_MDIX
);
2004 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
2005 IGP01E1000_PSSR_SPEED_1000MBPS
) {
2006 ret_val
= e1000_get_cable_length(hw
);
2010 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &data
);
2014 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
2015 ? e1000_1000t_rx_status_ok
2016 : e1000_1000t_rx_status_not_ok
;
2018 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
2019 ? e1000_1000t_rx_status_ok
2020 : e1000_1000t_rx_status_not_ok
;
2022 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2023 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2024 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2031 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2032 * @hw: pointer to the HW structure
2034 * Populates "phy" structure with various feature states.
2036 s32
e1000_get_phy_info_ife(struct e1000_hw
*hw
)
2038 struct e1000_phy_info
*phy
= &hw
->phy
;
2043 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2048 e_dbg("Phy info is only valid if link is up\n");
2049 return -E1000_ERR_CONFIG
;
2052 ret_val
= e1e_rphy(hw
, IFE_PHY_SPECIAL_CONTROL
, &data
);
2055 phy
->polarity_correction
= !(data
& IFE_PSC_AUTO_POLARITY_DISABLE
);
2057 if (phy
->polarity_correction
) {
2058 ret_val
= e1000_check_polarity_ife(hw
);
2062 /* Polarity is forced */
2063 phy
->cable_polarity
= (data
& IFE_PSC_FORCE_POLARITY
)
2064 ? e1000_rev_polarity_reversed
2065 : e1000_rev_polarity_normal
;
2068 ret_val
= e1e_rphy(hw
, IFE_PHY_MDIX_CONTROL
, &data
);
2072 phy
->is_mdix
= !!(data
& IFE_PMC_MDIX_STATUS
);
2074 /* The following parameters are undefined for 10/100 operation. */
2075 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2076 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2077 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2083 * e1000e_phy_sw_reset - PHY software reset
2084 * @hw: pointer to the HW structure
2086 * Does a software reset of the PHY by reading the PHY control register and
2087 * setting/write the control register reset bit to the PHY.
2089 s32
e1000e_phy_sw_reset(struct e1000_hw
*hw
)
2094 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
2098 phy_ctrl
|= MII_CR_RESET
;
2099 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
2109 * e1000e_phy_hw_reset_generic - PHY hardware reset
2110 * @hw: pointer to the HW structure
2112 * Verify the reset block is not blocking us from resetting. Acquire
2113 * semaphore (if necessary) and read/set/write the device control reset
2114 * bit in the PHY. Wait the appropriate delay time for the device to
2115 * reset and release the semaphore (if necessary).
2117 s32
e1000e_phy_hw_reset_generic(struct e1000_hw
*hw
)
2119 struct e1000_phy_info
*phy
= &hw
->phy
;
2123 ret_val
= phy
->ops
.check_reset_block(hw
);
2127 ret_val
= phy
->ops
.acquire(hw
);
2132 ew32(CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
2135 udelay(phy
->reset_delay_us
);
2142 phy
->ops
.release(hw
);
2144 return e1000_get_phy_cfg_done(hw
);
2148 * e1000e_get_cfg_done - Generic configuration done
2149 * @hw: pointer to the HW structure
2151 * Generic function to wait 10 milli-seconds for configuration to complete
2152 * and return success.
2154 s32
e1000e_get_cfg_done(struct e1000_hw
*hw
)
2162 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2163 * @hw: pointer to the HW structure
2165 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2167 s32
e1000e_phy_init_script_igp3(struct e1000_hw
*hw
)
2169 e_dbg("Running IGP 3 PHY init script\n");
2171 /* PHY init IGP 3 */
2172 /* Enable rise/fall, 10-mode work in class-A */
2173 e1e_wphy(hw
, 0x2F5B, 0x9018);
2174 /* Remove all caps from Replica path filter */
2175 e1e_wphy(hw
, 0x2F52, 0x0000);
2176 /* Bias trimming for ADC, AFE and Driver (Default) */
2177 e1e_wphy(hw
, 0x2FB1, 0x8B24);
2178 /* Increase Hybrid poly bias */
2179 e1e_wphy(hw
, 0x2FB2, 0xF8F0);
2180 /* Add 4% to Tx amplitude in Gig mode */
2181 e1e_wphy(hw
, 0x2010, 0x10B0);
2182 /* Disable trimming (TTT) */
2183 e1e_wphy(hw
, 0x2011, 0x0000);
2184 /* Poly DC correction to 94.6% + 2% for all channels */
2185 e1e_wphy(hw
, 0x20DD, 0x249A);
2186 /* ABS DC correction to 95.9% */
2187 e1e_wphy(hw
, 0x20DE, 0x00D3);
2188 /* BG temp curve trim */
2189 e1e_wphy(hw
, 0x28B4, 0x04CE);
2190 /* Increasing ADC OPAMP stage 1 currents to max */
2191 e1e_wphy(hw
, 0x2F70, 0x29E4);
2192 /* Force 1000 ( required for enabling PHY regs configuration) */
2193 e1e_wphy(hw
, 0x0000, 0x0140);
2194 /* Set upd_freq to 6 */
2195 e1e_wphy(hw
, 0x1F30, 0x1606);
2197 e1e_wphy(hw
, 0x1F31, 0xB814);
2198 /* Disable adaptive fixed FFE (Default) */
2199 e1e_wphy(hw
, 0x1F35, 0x002A);
2200 /* Enable FFE hysteresis */
2201 e1e_wphy(hw
, 0x1F3E, 0x0067);
2202 /* Fixed FFE for short cable lengths */
2203 e1e_wphy(hw
, 0x1F54, 0x0065);
2204 /* Fixed FFE for medium cable lengths */
2205 e1e_wphy(hw
, 0x1F55, 0x002A);
2206 /* Fixed FFE for long cable lengths */
2207 e1e_wphy(hw
, 0x1F56, 0x002A);
2208 /* Enable Adaptive Clip Threshold */
2209 e1e_wphy(hw
, 0x1F72, 0x3FB0);
2210 /* AHT reset limit to 1 */
2211 e1e_wphy(hw
, 0x1F76, 0xC0FF);
2212 /* Set AHT master delay to 127 msec */
2213 e1e_wphy(hw
, 0x1F77, 0x1DEC);
2214 /* Set scan bits for AHT */
2215 e1e_wphy(hw
, 0x1F78, 0xF9EF);
2216 /* Set AHT Preset bits */
2217 e1e_wphy(hw
, 0x1F79, 0x0210);
2218 /* Change integ_factor of channel A to 3 */
2219 e1e_wphy(hw
, 0x1895, 0x0003);
2220 /* Change prop_factor of channels BCD to 8 */
2221 e1e_wphy(hw
, 0x1796, 0x0008);
2222 /* Change cg_icount + enable integbp for channels BCD */
2223 e1e_wphy(hw
, 0x1798, 0xD008);
2225 * Change cg_icount + enable integbp + change prop_factor_master
2226 * to 8 for channel A
2228 e1e_wphy(hw
, 0x1898, 0xD918);
2229 /* Disable AHT in Slave mode on channel A */
2230 e1e_wphy(hw
, 0x187A, 0x0800);
2232 * Enable LPLU and disable AN to 1000 in non-D0a states,
2235 e1e_wphy(hw
, 0x0019, 0x008D);
2236 /* Enable restart AN on an1000_dis change */
2237 e1e_wphy(hw
, 0x001B, 0x2080);
2238 /* Enable wh_fifo read clock in 10/100 modes */
2239 e1e_wphy(hw
, 0x0014, 0x0045);
2240 /* Restart AN, Speed selection is 1000 */
2241 e1e_wphy(hw
, 0x0000, 0x1340);
2246 /* Internal function pointers */
2249 * e1000_get_phy_cfg_done - Generic PHY configuration done
2250 * @hw: pointer to the HW structure
2252 * Return success if silicon family did not implement a family specific
2253 * get_cfg_done function.
2255 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
2257 if (hw
->phy
.ops
.get_cfg_done
)
2258 return hw
->phy
.ops
.get_cfg_done(hw
);
2264 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2265 * @hw: pointer to the HW structure
2267 * When the silicon family has not implemented a forced speed/duplex
2268 * function for the PHY, simply return 0.
2270 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
2272 if (hw
->phy
.ops
.force_speed_duplex
)
2273 return hw
->phy
.ops
.force_speed_duplex(hw
);
2279 * e1000e_get_phy_type_from_id - Get PHY type from id
2280 * @phy_id: phy_id read from the phy
2282 * Returns the phy type from the id.
2284 enum e1000_phy_type
e1000e_get_phy_type_from_id(u32 phy_id
)
2286 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2289 case M88E1000_I_PHY_ID
:
2290 case M88E1000_E_PHY_ID
:
2291 case M88E1111_I_PHY_ID
:
2292 case M88E1011_I_PHY_ID
:
2293 phy_type
= e1000_phy_m88
;
2295 case IGP01E1000_I_PHY_ID
: /* IGP 1 & 2 share this */
2296 phy_type
= e1000_phy_igp_2
;
2298 case GG82563_E_PHY_ID
:
2299 phy_type
= e1000_phy_gg82563
;
2301 case IGP03E1000_E_PHY_ID
:
2302 phy_type
= e1000_phy_igp_3
;
2305 case IFE_PLUS_E_PHY_ID
:
2306 case IFE_C_E_PHY_ID
:
2307 phy_type
= e1000_phy_ife
;
2309 case BME1000_E_PHY_ID
:
2310 case BME1000_E_PHY_ID_R2
:
2311 phy_type
= e1000_phy_bm
;
2313 case I82578_E_PHY_ID
:
2314 phy_type
= e1000_phy_82578
;
2316 case I82577_E_PHY_ID
:
2317 phy_type
= e1000_phy_82577
;
2319 case I82579_E_PHY_ID
:
2320 phy_type
= e1000_phy_82579
;
2323 phy_type
= e1000_phy_unknown
;
2330 * e1000e_determine_phy_address - Determines PHY address.
2331 * @hw: pointer to the HW structure
2333 * This uses a trial and error method to loop through possible PHY
2334 * addresses. It tests each by reading the PHY ID registers and
2335 * checking for a match.
2337 s32
e1000e_determine_phy_address(struct e1000_hw
*hw
)
2341 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2343 hw
->phy
.id
= phy_type
;
2345 for (phy_addr
= 0; phy_addr
< E1000_MAX_PHY_ADDR
; phy_addr
++) {
2346 hw
->phy
.addr
= phy_addr
;
2350 e1000e_get_phy_id(hw
);
2351 phy_type
= e1000e_get_phy_type_from_id(hw
->phy
.id
);
2354 * If phy_type is valid, break - we found our
2357 if (phy_type
!= e1000_phy_unknown
)
2360 usleep_range(1000, 2000);
2365 return -E1000_ERR_PHY_TYPE
;
2369 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2370 * @page: page to access
2372 * Returns the phy address for the page requested.
2374 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
)
2378 if ((page
>= 768) || (page
== 0 && reg
== 25) || (reg
== 31))
2385 * e1000e_write_phy_reg_bm - Write BM PHY register
2386 * @hw: pointer to the HW structure
2387 * @offset: register offset to write to
2388 * @data: data to write at register offset
2390 * Acquires semaphore, if necessary, then writes the data to PHY register
2391 * at the offset. Release any acquired semaphores before exiting.
2393 s32
e1000e_write_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2396 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2398 ret_val
= hw
->phy
.ops
.acquire(hw
);
2402 /* Page 800 works differently than the rest so it has its own func */
2403 if (page
== BM_WUC_PAGE
) {
2404 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2409 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2411 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2412 u32 page_shift
, page_select
;
2415 * Page select is register 31 for phy address 1 and 22 for
2416 * phy address 2 and 3. Page select is shifted only for
2419 if (hw
->phy
.addr
== 1) {
2420 page_shift
= IGP_PAGE_SHIFT
;
2421 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2424 page_select
= BM_PHY_PAGE_SELECT
;
2427 /* Page is shifted left, PHY expects (page x 32) */
2428 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2429 (page
<< page_shift
));
2434 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2438 hw
->phy
.ops
.release(hw
);
2443 * e1000e_read_phy_reg_bm - Read BM PHY register
2444 * @hw: pointer to the HW structure
2445 * @offset: register offset to be read
2446 * @data: pointer to the read data
2448 * Acquires semaphore, if necessary, then reads the PHY register at offset
2449 * and storing the retrieved information in data. Release any acquired
2450 * semaphores before exiting.
2452 s32
e1000e_read_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2455 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2457 ret_val
= hw
->phy
.ops
.acquire(hw
);
2461 /* Page 800 works differently than the rest so it has its own func */
2462 if (page
== BM_WUC_PAGE
) {
2463 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2468 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2470 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2471 u32 page_shift
, page_select
;
2474 * Page select is register 31 for phy address 1 and 22 for
2475 * phy address 2 and 3. Page select is shifted only for
2478 if (hw
->phy
.addr
== 1) {
2479 page_shift
= IGP_PAGE_SHIFT
;
2480 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2483 page_select
= BM_PHY_PAGE_SELECT
;
2486 /* Page is shifted left, PHY expects (page x 32) */
2487 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2488 (page
<< page_shift
));
2493 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2496 hw
->phy
.ops
.release(hw
);
2501 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2502 * @hw: pointer to the HW structure
2503 * @offset: register offset to be read
2504 * @data: pointer to the read data
2506 * Acquires semaphore, if necessary, then reads the PHY register at offset
2507 * and storing the retrieved information in data. Release any acquired
2508 * semaphores before exiting.
2510 s32
e1000e_read_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2513 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2515 ret_val
= hw
->phy
.ops
.acquire(hw
);
2519 /* Page 800 works differently than the rest so it has its own func */
2520 if (page
== BM_WUC_PAGE
) {
2521 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2528 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2530 /* Page is shifted left, PHY expects (page x 32) */
2531 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2538 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2541 hw
->phy
.ops
.release(hw
);
2546 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2547 * @hw: pointer to the HW structure
2548 * @offset: register offset to write to
2549 * @data: data to write at register offset
2551 * Acquires semaphore, if necessary, then writes the data to PHY register
2552 * at the offset. Release any acquired semaphores before exiting.
2554 s32
e1000e_write_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2557 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2559 ret_val
= hw
->phy
.ops
.acquire(hw
);
2563 /* Page 800 works differently than the rest so it has its own func */
2564 if (page
== BM_WUC_PAGE
) {
2565 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2572 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2573 /* Page is shifted left, PHY expects (page x 32) */
2574 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2581 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2585 hw
->phy
.ops
.release(hw
);
2590 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2591 * @hw: pointer to the HW structure
2592 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2594 * Assumes semaphore already acquired and phy_reg points to a valid memory
2595 * address to store contents of the BM_WUC_ENABLE_REG register.
2597 s32
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw
*hw
, u16
*phy_reg
)
2602 /* All page select, port ctrl and wakeup registers use phy address 1 */
2605 /* Select Port Control Registers page */
2606 ret_val
= e1000_set_page_igp(hw
, (BM_PORT_CTRL_PAGE
<< IGP_PAGE_SHIFT
));
2608 e_dbg("Could not set Port Control page\n");
2612 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2614 e_dbg("Could not read PHY register %d.%d\n",
2615 BM_PORT_CTRL_PAGE
, BM_WUC_ENABLE_REG
);
2620 * Enable both PHY wakeup mode and Wakeup register page writes.
2621 * Prevent a power state change by disabling ME and Host PHY wakeup.
2624 temp
|= BM_WUC_ENABLE_BIT
;
2625 temp
&= ~(BM_WUC_ME_WU_BIT
| BM_WUC_HOST_WU_BIT
);
2627 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, temp
);
2629 e_dbg("Could not write PHY register %d.%d\n",
2630 BM_PORT_CTRL_PAGE
, BM_WUC_ENABLE_REG
);
2635 * Select Host Wakeup Registers page - caller now able to write
2636 * registers on the Wakeup registers page
2638 return e1000_set_page_igp(hw
, (BM_WUC_PAGE
<< IGP_PAGE_SHIFT
));
2642 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2643 * @hw: pointer to the HW structure
2644 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2646 * Restore BM_WUC_ENABLE_REG to its original value.
2648 * Assumes semaphore already acquired and *phy_reg is the contents of the
2649 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2652 s32
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw
*hw
, u16
*phy_reg
)
2656 /* Select Port Control Registers page */
2657 ret_val
= e1000_set_page_igp(hw
, (BM_PORT_CTRL_PAGE
<< IGP_PAGE_SHIFT
));
2659 e_dbg("Could not set Port Control page\n");
2663 /* Restore 769.17 to its original value */
2664 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, *phy_reg
);
2666 e_dbg("Could not restore PHY register %d.%d\n",
2667 BM_PORT_CTRL_PAGE
, BM_WUC_ENABLE_REG
);
2673 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2674 * @hw: pointer to the HW structure
2675 * @offset: register offset to be read or written
2676 * @data: pointer to the data to read or write
2677 * @read: determines if operation is read or write
2678 * @page_set: BM_WUC_PAGE already set and access enabled
2680 * Read the PHY register at offset and store the retrieved information in
2681 * data, or write data to PHY register at offset. Note the procedure to
2682 * access the PHY wakeup registers is different than reading the other PHY
2683 * registers. It works as such:
2684 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2685 * 2) Set page to 800 for host (801 if we were manageability)
2686 * 3) Write the address using the address opcode (0x11)
2687 * 4) Read or write the data using the data opcode (0x12)
2688 * 5) Restore 769.17.2 to its original value
2690 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2691 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2693 * Assumes semaphore is already acquired. When page_set==true, assumes
2694 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2695 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2697 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
2698 u16
*data
, bool read
, bool page_set
)
2701 u16 reg
= BM_PHY_REG_NUM(offset
);
2702 u16 page
= BM_PHY_REG_PAGE(offset
);
2705 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2706 if ((hw
->mac
.type
== e1000_pchlan
) &&
2707 (!(er32(PHY_CTRL
) & E1000_PHY_CTRL_GBE_DISABLE
)))
2708 e_dbg("Attempting to access page %d while gig enabled.\n",
2712 /* Enable access to PHY wakeup registers */
2713 ret_val
= e1000_enable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
2715 e_dbg("Could not enable PHY wakeup reg access\n");
2720 e_dbg("Accessing PHY page %d reg 0x%x\n", page
, reg
);
2722 /* Write the Wakeup register page offset value using opcode 0x11 */
2723 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ADDRESS_OPCODE
, reg
);
2725 e_dbg("Could not write address opcode to page %d\n", page
);
2730 /* Read the Wakeup register page value using opcode 0x12 */
2731 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2734 /* Write the Wakeup register page value using opcode 0x12 */
2735 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2740 e_dbg("Could not access PHY reg %d.%d\n", page
, reg
);
2745 ret_val
= e1000_disable_phy_wakeup_reg_access_bm(hw
, &phy_reg
);
2751 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2752 * @hw: pointer to the HW structure
2754 * In the case of a PHY power down to save power, or to turn off link during a
2755 * driver unload, or wake on lan is not enabled, restore the link to previous
2758 void e1000_power_up_phy_copper(struct e1000_hw
*hw
)
2762 /* The PHY will retain its settings across a power down/up cycle */
2763 e1e_rphy(hw
, PHY_CONTROL
, &mii_reg
);
2764 mii_reg
&= ~MII_CR_POWER_DOWN
;
2765 e1e_wphy(hw
, PHY_CONTROL
, mii_reg
);
2769 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2770 * @hw: pointer to the HW structure
2772 * In the case of a PHY power down to save power, or to turn off link during a
2773 * driver unload, or wake on lan is not enabled, restore the link to previous
2776 void e1000_power_down_phy_copper(struct e1000_hw
*hw
)
2780 /* The PHY will retain its settings across a power down/up cycle */
2781 e1e_rphy(hw
, PHY_CONTROL
, &mii_reg
);
2782 mii_reg
|= MII_CR_POWER_DOWN
;
2783 e1e_wphy(hw
, PHY_CONTROL
, mii_reg
);
2784 usleep_range(1000, 2000);
2788 * e1000e_commit_phy - Soft PHY reset
2789 * @hw: pointer to the HW structure
2791 * Performs a soft PHY reset on those that apply. This is a function pointer
2792 * entry point called by drivers.
2794 s32
e1000e_commit_phy(struct e1000_hw
*hw
)
2796 if (hw
->phy
.ops
.commit
)
2797 return hw
->phy
.ops
.commit(hw
);
2803 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2804 * @hw: pointer to the HW structure
2805 * @active: boolean used to enable/disable lplu
2807 * Success returns 0, Failure returns 1
2809 * The low power link up (lplu) state is set to the power management level D0
2810 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2811 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2812 * is used during Dx states where the power conservation is most important.
2813 * During driver activity, SmartSpeed should be enabled so performance is
2814 * maintained. This is a function pointer entry point called by drivers.
2816 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
)
2818 if (hw
->phy
.ops
.set_d0_lplu_state
)
2819 return hw
->phy
.ops
.set_d0_lplu_state(hw
, active
);
2825 * __e1000_read_phy_reg_hv - Read HV PHY register
2826 * @hw: pointer to the HW structure
2827 * @offset: register offset to be read
2828 * @data: pointer to the read data
2829 * @locked: semaphore has already been acquired or not
2831 * Acquires semaphore, if necessary, then reads the PHY register at offset
2832 * and stores the retrieved information in data. Release any acquired
2833 * semaphore before exiting.
2835 static s32
__e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
,
2836 bool locked
, bool page_set
)
2839 u16 page
= BM_PHY_REG_PAGE(offset
);
2840 u16 reg
= BM_PHY_REG_NUM(offset
);
2841 u32 phy_addr
= hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2844 ret_val
= hw
->phy
.ops
.acquire(hw
);
2849 /* Page 800 works differently than the rest so it has its own func */
2850 if (page
== BM_WUC_PAGE
) {
2851 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2856 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2857 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2863 if (page
== HV_INTC_FC_PAGE_START
)
2866 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2867 /* Page is shifted left, PHY expects (page x 32) */
2868 ret_val
= e1000_set_page_igp(hw
,
2869 (page
<< IGP_PAGE_SHIFT
));
2871 hw
->phy
.addr
= phy_addr
;
2878 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page
,
2879 page
<< IGP_PAGE_SHIFT
, reg
);
2881 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
2885 hw
->phy
.ops
.release(hw
);
2891 * e1000_read_phy_reg_hv - Read HV PHY register
2892 * @hw: pointer to the HW structure
2893 * @offset: register offset to be read
2894 * @data: pointer to the read data
2896 * Acquires semaphore then reads the PHY register at offset and stores
2897 * the retrieved information in data. Release the acquired semaphore
2900 s32
e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2902 return __e1000_read_phy_reg_hv(hw
, offset
, data
, false, false);
2906 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2907 * @hw: pointer to the HW structure
2908 * @offset: register offset to be read
2909 * @data: pointer to the read data
2911 * Reads the PHY register at offset and stores the retrieved information
2912 * in data. Assumes semaphore already acquired.
2914 s32
e1000_read_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2916 return __e1000_read_phy_reg_hv(hw
, offset
, data
, true, false);
2920 * e1000_read_phy_reg_page_hv - Read HV PHY register
2921 * @hw: pointer to the HW structure
2922 * @offset: register offset to write to
2923 * @data: data to write at register offset
2925 * Reads the PHY register at offset and stores the retrieved information
2926 * in data. Assumes semaphore already acquired and page already set.
2928 s32
e1000_read_phy_reg_page_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2930 return __e1000_read_phy_reg_hv(hw
, offset
, data
, true, true);
2934 * __e1000_write_phy_reg_hv - Write HV PHY register
2935 * @hw: pointer to the HW structure
2936 * @offset: register offset to write to
2937 * @data: data to write at register offset
2938 * @locked: semaphore has already been acquired or not
2940 * Acquires semaphore, if necessary, then writes the data to PHY register
2941 * at the offset. Release any acquired semaphores before exiting.
2943 static s32
__e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
,
2944 bool locked
, bool page_set
)
2947 u16 page
= BM_PHY_REG_PAGE(offset
);
2948 u16 reg
= BM_PHY_REG_NUM(offset
);
2949 u32 phy_addr
= hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2952 ret_val
= hw
->phy
.ops
.acquire(hw
);
2957 /* Page 800 works differently than the rest so it has its own func */
2958 if (page
== BM_WUC_PAGE
) {
2959 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2964 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2965 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2971 if (page
== HV_INTC_FC_PAGE_START
)
2975 * Workaround MDIO accesses being disabled after entering IEEE
2976 * Power Down (when bit 11 of the PHY Control register is set)
2978 if ((hw
->phy
.type
== e1000_phy_82578
) &&
2979 (hw
->phy
.revision
>= 1) &&
2980 (hw
->phy
.addr
== 2) &&
2981 !(MAX_PHY_REG_ADDRESS
& reg
) && (data
& (1 << 11))) {
2983 ret_val
= e1000_access_phy_debug_regs_hv(hw
,
2990 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2991 /* Page is shifted left, PHY expects (page x 32) */
2992 ret_val
= e1000_set_page_igp(hw
,
2993 (page
<< IGP_PAGE_SHIFT
));
2995 hw
->phy
.addr
= phy_addr
;
3002 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page
,
3003 page
<< IGP_PAGE_SHIFT
, reg
);
3005 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
3010 hw
->phy
.ops
.release(hw
);
3016 * e1000_write_phy_reg_hv - Write HV PHY register
3017 * @hw: pointer to the HW structure
3018 * @offset: register offset to write to
3019 * @data: data to write at register offset
3021 * Acquires semaphore then writes the data to PHY register at the offset.
3022 * Release the acquired semaphores before exiting.
3024 s32
e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
)
3026 return __e1000_write_phy_reg_hv(hw
, offset
, data
, false, false);
3030 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3031 * @hw: pointer to the HW structure
3032 * @offset: register offset to write to
3033 * @data: data to write at register offset
3035 * Writes the data to PHY register at the offset. Assumes semaphore
3038 s32
e1000_write_phy_reg_hv_locked(struct e1000_hw
*hw
, u32 offset
, u16 data
)
3040 return __e1000_write_phy_reg_hv(hw
, offset
, data
, true, false);
3044 * e1000_write_phy_reg_page_hv - Write HV PHY register
3045 * @hw: pointer to the HW structure
3046 * @offset: register offset to write to
3047 * @data: data to write at register offset
3049 * Writes the data to PHY register at the offset. Assumes semaphore
3050 * already acquired and page already set.
3052 s32
e1000_write_phy_reg_page_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
)
3054 return __e1000_write_phy_reg_hv(hw
, offset
, data
, true, true);
3058 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3059 * @page: page to be accessed
3061 static u32
e1000_get_phy_addr_for_hv_page(u32 page
)
3065 if (page
>= HV_INTC_FC_PAGE_START
)
3072 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3073 * @hw: pointer to the HW structure
3074 * @offset: register offset to be read or written
3075 * @data: pointer to the data to be read or written
3076 * @read: determines if operation is read or write
3078 * Reads the PHY register at offset and stores the retreived information
3079 * in data. Assumes semaphore already acquired. Note that the procedure
3080 * to access these regs uses the address port and data port to read/write.
3081 * These accesses done with PHY address 2 and without using pages.
3083 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
3084 u16
*data
, bool read
)
3090 /* This takes care of the difference with desktop vs mobile phy */
3091 addr_reg
= (hw
->phy
.type
== e1000_phy_82578
) ?
3092 I82578_ADDR_REG
: I82577_ADDR_REG
;
3093 data_reg
= addr_reg
+ 1;
3095 /* All operations in this function are phy address 2 */
3098 /* masking with 0x3F to remove the page from offset */
3099 ret_val
= e1000e_write_phy_reg_mdic(hw
, addr_reg
, (u16
)offset
& 0x3F);
3101 e_dbg("Could not write the Address Offset port register\n");
3105 /* Read or write the data value next */
3107 ret_val
= e1000e_read_phy_reg_mdic(hw
, data_reg
, data
);
3109 ret_val
= e1000e_write_phy_reg_mdic(hw
, data_reg
, *data
);
3112 e_dbg("Could not access the Data port register\n");
3118 * e1000_link_stall_workaround_hv - Si workaround
3119 * @hw: pointer to the HW structure
3121 * This function works around a Si bug where the link partner can get
3122 * a link up indication before the PHY does. If small packets are sent
3123 * by the link partner they can be placed in the packet buffer without
3124 * being properly accounted for by the PHY and will stall preventing
3125 * further packets from being received. The workaround is to clear the
3126 * packet buffer after the PHY detects link up.
3128 s32
e1000_link_stall_workaround_hv(struct e1000_hw
*hw
)
3133 if (hw
->phy
.type
!= e1000_phy_82578
)
3136 /* Do not apply workaround if in PHY loopback bit 14 set */
3137 e1e_rphy(hw
, PHY_CONTROL
, &data
);
3138 if (data
& PHY_CONTROL_LB
)
3141 /* check if link is up and at 1Gbps */
3142 ret_val
= e1e_rphy(hw
, BM_CS_STATUS
, &data
);
3146 data
&= BM_CS_STATUS_LINK_UP
| BM_CS_STATUS_RESOLVED
|
3147 BM_CS_STATUS_SPEED_MASK
;
3149 if (data
!= (BM_CS_STATUS_LINK_UP
| BM_CS_STATUS_RESOLVED
|
3150 BM_CS_STATUS_SPEED_1000
))
3155 /* flush the packets in the fifo buffer */
3156 ret_val
= e1e_wphy(hw
, HV_MUX_DATA_CTRL
, HV_MUX_DATA_CTRL_GEN_TO_MAC
|
3157 HV_MUX_DATA_CTRL_FORCE_SPEED
);
3161 return e1e_wphy(hw
, HV_MUX_DATA_CTRL
, HV_MUX_DATA_CTRL_GEN_TO_MAC
);
3165 * e1000_check_polarity_82577 - Checks the polarity.
3166 * @hw: pointer to the HW structure
3168 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3170 * Polarity is determined based on the PHY specific status register.
3172 s32
e1000_check_polarity_82577(struct e1000_hw
*hw
)
3174 struct e1000_phy_info
*phy
= &hw
->phy
;
3178 ret_val
= e1e_rphy(hw
, I82577_PHY_STATUS_2
, &data
);
3181 phy
->cable_polarity
= (data
& I82577_PHY_STATUS2_REV_POLARITY
)
3182 ? e1000_rev_polarity_reversed
3183 : e1000_rev_polarity_normal
;
3189 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3190 * @hw: pointer to the HW structure
3192 * Calls the PHY setup function to force speed and duplex.
3194 s32
e1000_phy_force_speed_duplex_82577(struct e1000_hw
*hw
)
3196 struct e1000_phy_info
*phy
= &hw
->phy
;
3201 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
3205 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
3207 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
3213 if (phy
->autoneg_wait_to_complete
) {
3214 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3216 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
3222 e_dbg("Link taking longer than expected.\n");
3225 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
3233 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3234 * @hw: pointer to the HW structure
3236 * Read PHY status to determine if link is up. If link is up, then
3237 * set/determine 10base-T extended distance and polarity correction. Read
3238 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3239 * determine on the cable length, local and remote receiver.
3241 s32
e1000_get_phy_info_82577(struct e1000_hw
*hw
)
3243 struct e1000_phy_info
*phy
= &hw
->phy
;
3248 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
3253 e_dbg("Phy info is only valid if link is up\n");
3254 return -E1000_ERR_CONFIG
;
3257 phy
->polarity_correction
= true;
3259 ret_val
= e1000_check_polarity_82577(hw
);
3263 ret_val
= e1e_rphy(hw
, I82577_PHY_STATUS_2
, &data
);
3267 phy
->is_mdix
= !!(data
& I82577_PHY_STATUS2_MDIX
);
3269 if ((data
& I82577_PHY_STATUS2_SPEED_MASK
) ==
3270 I82577_PHY_STATUS2_SPEED_1000MBPS
) {
3271 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
3275 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &data
);
3279 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
3280 ? e1000_1000t_rx_status_ok
3281 : e1000_1000t_rx_status_not_ok
;
3283 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
3284 ? e1000_1000t_rx_status_ok
3285 : e1000_1000t_rx_status_not_ok
;
3287 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
3288 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
3289 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
3296 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3297 * @hw: pointer to the HW structure
3299 * Reads the diagnostic status register and verifies result is valid before
3300 * placing it in the phy_cable_length field.
3302 s32
e1000_get_cable_length_82577(struct e1000_hw
*hw
)
3304 struct e1000_phy_info
*phy
= &hw
->phy
;
3306 u16 phy_data
, length
;
3308 ret_val
= e1e_rphy(hw
, I82577_PHY_DIAG_STATUS
, &phy_data
);
3312 length
= (phy_data
& I82577_DSTATUS_CABLE_LENGTH
) >>
3313 I82577_DSTATUS_CABLE_LENGTH_SHIFT
;
3315 if (length
== E1000_CABLE_LENGTH_UNDEFINED
)
3316 ret_val
= -E1000_ERR_PHY
;
3318 phy
->cable_length
= length
;