1 /* Intel Ethernet Switch Host Interface Driver
2 * Copyright(c) 2013 - 2015 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
16 * Contact Information:
17 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
18 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 * fm10k_reset_hw_pf - PF hardware reset
26 * @hw: pointer to hardware structure
28 * This function should return the hardware to a state similar to the
29 * one it is in after being powered on.
31 static s32
fm10k_reset_hw_pf(struct fm10k_hw
*hw
)
37 /* Disable interrupts */
38 fm10k_write_reg(hw
, FM10K_EIMR
, FM10K_EIMR_DISABLE(ALL
));
40 /* Lock ITR2 reg 0 into itself and disable interrupt moderation */
41 fm10k_write_reg(hw
, FM10K_ITR2(0), 0);
42 fm10k_write_reg(hw
, FM10K_INT_CTRL
, 0);
44 /* We assume here Tx and Rx queue 0 are owned by the PF */
46 /* Shut off VF access to their queues forcing them to queue 0 */
47 for (i
= 0; i
< FM10K_TQMAP_TABLE_SIZE
; i
++) {
48 fm10k_write_reg(hw
, FM10K_TQMAP(i
), 0);
49 fm10k_write_reg(hw
, FM10K_RQMAP(i
), 0);
52 /* shut down all rings */
53 err
= fm10k_disable_queues_generic(hw
, FM10K_MAX_QUEUES
);
57 /* Verify that DMA is no longer active */
58 reg
= fm10k_read_reg(hw
, FM10K_DMA_CTRL
);
59 if (reg
& (FM10K_DMA_CTRL_TX_ACTIVE
| FM10K_DMA_CTRL_RX_ACTIVE
))
60 return FM10K_ERR_DMA_PENDING
;
62 /* verify the switch is ready for reset */
63 reg
= fm10k_read_reg(hw
, FM10K_DMA_CTRL2
);
64 if (!(reg
& FM10K_DMA_CTRL2_SWITCH_READY
))
67 /* Inititate data path reset */
68 reg
|= FM10K_DMA_CTRL_DATAPATH_RESET
;
69 fm10k_write_reg(hw
, FM10K_DMA_CTRL
, reg
);
71 /* Flush write and allow 100us for reset to complete */
72 fm10k_write_flush(hw
);
73 udelay(FM10K_RESET_TIMEOUT
);
75 /* Verify we made it out of reset */
76 reg
= fm10k_read_reg(hw
, FM10K_IP
);
77 if (!(reg
& FM10K_IP_NOTINRESET
))
78 err
= FM10K_ERR_RESET_FAILED
;
85 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
86 * @hw: pointer to hardware structure
88 * Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
90 static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw
*hw
)
92 u16 sriov_ctrl
= fm10k_read_pci_cfg_word(hw
, FM10K_PCIE_SRIOV_CTRL
);
94 return !!(sriov_ctrl
& FM10K_PCIE_SRIOV_CTRL_VFARI
);
98 * fm10k_init_hw_pf - PF hardware initialization
99 * @hw: pointer to hardware structure
102 static s32
fm10k_init_hw_pf(struct fm10k_hw
*hw
)
104 u32 dma_ctrl
, txqctl
;
107 /* Establish default VSI as valid */
108 fm10k_write_reg(hw
, FM10K_DGLORTDEC(fm10k_dglort_default
), 0);
109 fm10k_write_reg(hw
, FM10K_DGLORTMAP(fm10k_dglort_default
),
110 FM10K_DGLORTMAP_ANY
);
112 /* Invalidate all other GLORT entries */
113 for (i
= 1; i
< FM10K_DGLORT_COUNT
; i
++)
114 fm10k_write_reg(hw
, FM10K_DGLORTMAP(i
), FM10K_DGLORTMAP_NONE
);
116 /* reset ITR2(0) to point to itself */
117 fm10k_write_reg(hw
, FM10K_ITR2(0), 0);
119 /* reset VF ITR2(0) to point to 0 avoid PF registers */
120 fm10k_write_reg(hw
, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF
), 0);
122 /* loop through all PF ITR2 registers pointing them to the previous */
123 for (i
= 1; i
< FM10K_ITR_REG_COUNT_PF
; i
++)
124 fm10k_write_reg(hw
, FM10K_ITR2(i
), i
- 1);
126 /* Enable interrupt moderator if not already enabled */
127 fm10k_write_reg(hw
, FM10K_INT_CTRL
, FM10K_INT_CTRL_ENABLEMODERATOR
);
129 /* compute the default txqctl configuration */
130 txqctl
= FM10K_TXQCTL_PF
| FM10K_TXQCTL_UNLIMITED_BW
|
131 (hw
->mac
.default_vid
<< FM10K_TXQCTL_VID_SHIFT
);
133 for (i
= 0; i
< FM10K_MAX_QUEUES
; i
++) {
134 /* configure rings for 256 Queue / 32 Descriptor cache mode */
135 fm10k_write_reg(hw
, FM10K_TQDLOC(i
),
136 (i
* FM10K_TQDLOC_BASE_32_DESC
) |
137 FM10K_TQDLOC_SIZE_32_DESC
);
138 fm10k_write_reg(hw
, FM10K_TXQCTL(i
), txqctl
);
140 /* configure rings to provide TPH processing hints */
141 fm10k_write_reg(hw
, FM10K_TPH_TXCTRL(i
),
142 FM10K_TPH_TXCTRL_DESC_TPHEN
|
143 FM10K_TPH_TXCTRL_DESC_RROEN
|
144 FM10K_TPH_TXCTRL_DESC_WROEN
|
145 FM10K_TPH_TXCTRL_DATA_RROEN
);
146 fm10k_write_reg(hw
, FM10K_TPH_RXCTRL(i
),
147 FM10K_TPH_RXCTRL_DESC_TPHEN
|
148 FM10K_TPH_RXCTRL_DESC_RROEN
|
149 FM10K_TPH_RXCTRL_DATA_WROEN
|
150 FM10K_TPH_RXCTRL_HDR_WROEN
);
153 /* set max hold interval to align with 1.024 usec in all modes and
156 switch (hw
->bus
.speed
) {
157 case fm10k_bus_speed_2500
:
158 dma_ctrl
= FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1
;
159 hw
->mac
.itr_scale
= FM10K_TDLEN_ITR_SCALE_GEN1
;
161 case fm10k_bus_speed_5000
:
162 dma_ctrl
= FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2
;
163 hw
->mac
.itr_scale
= FM10K_TDLEN_ITR_SCALE_GEN2
;
165 case fm10k_bus_speed_8000
:
166 dma_ctrl
= FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3
;
167 hw
->mac
.itr_scale
= FM10K_TDLEN_ITR_SCALE_GEN3
;
171 /* just in case, assume Gen3 ITR scale */
172 hw
->mac
.itr_scale
= FM10K_TDLEN_ITR_SCALE_GEN3
;
176 /* Configure TSO flags */
177 fm10k_write_reg(hw
, FM10K_DTXTCPFLGL
, FM10K_TSO_FLAGS_LOW
);
178 fm10k_write_reg(hw
, FM10K_DTXTCPFLGH
, FM10K_TSO_FLAGS_HI
);
181 * Set Rx Descriptor size to 32
182 * Set Minimum MSS to 64
183 * Set Maximum number of Rx queues to 256 / 32 Descriptor
185 dma_ctrl
|= FM10K_DMA_CTRL_TX_ENABLE
| FM10K_DMA_CTRL_RX_ENABLE
|
186 FM10K_DMA_CTRL_RX_DESC_SIZE
| FM10K_DMA_CTRL_MINMSS_64
|
187 FM10K_DMA_CTRL_32_DESC
;
189 fm10k_write_reg(hw
, FM10K_DMA_CTRL
, dma_ctrl
);
191 /* record maximum queue count, we limit ourselves to 128 */
192 hw
->mac
.max_queues
= FM10K_MAX_QUEUES_PF
;
194 /* We support either 64 VFs or 7 VFs depending on if we have ARI */
195 hw
->iov
.total_vfs
= fm10k_is_ari_hierarchy_pf(hw
) ? 64 : 7;
201 * fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
202 * @hw: pointer to hardware structure
203 * @vid: VLAN ID to add to table
204 * @vsi: Index indicating VF ID or PF ID in table
205 * @set: Indicates if this is a set or clear operation
207 * This function adds or removes the corresponding VLAN ID from the VLAN
208 * filter table for the corresponding function. In addition to the
209 * standard set/clear that supports one bit a multi-bit write is
210 * supported to set 64 bits at a time.
212 static s32
fm10k_update_vlan_pf(struct fm10k_hw
*hw
, u32 vid
, u8 vsi
, bool set
)
214 u32 vlan_table
, reg
, mask
, bit
, len
;
216 /* verify the VSI index is valid */
217 if (vsi
> FM10K_VLAN_TABLE_VSI_MAX
)
218 return FM10K_ERR_PARAM
;
220 /* VLAN multi-bit write:
221 * The multi-bit write has several parts to it.
223 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
225 * | RSVD0 | Length |C|RSVD0| VLAN ID |
226 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
228 * VLAN ID: Vlan Starting value
229 * RSVD0: Reserved section, must be 0
230 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
231 * Length: Number of times to repeat the bit being set
234 vid
= (vid
<< 17) >> 17;
236 /* verify the reserved 0 fields are 0 */
237 if (len
>= FM10K_VLAN_TABLE_VID_MAX
|| vid
>= FM10K_VLAN_TABLE_VID_MAX
)
238 return FM10K_ERR_PARAM
;
240 /* Loop through the table updating all required VLANs */
241 for (reg
= FM10K_VLAN_TABLE(vsi
, vid
/ 32), bit
= vid
% 32;
242 len
< FM10K_VLAN_TABLE_VID_MAX
;
243 len
-= 32 - bit
, reg
++, bit
= 0) {
244 /* record the initial state of the register */
245 vlan_table
= fm10k_read_reg(hw
, reg
);
247 /* truncate mask if we are at the start or end of the run */
248 mask
= (~(u32
)0 >> ((len
< 31) ? 31 - len
: 0)) << bit
;
250 /* make necessary modifications to the register */
251 mask
&= set
? ~vlan_table
: vlan_table
;
253 fm10k_write_reg(hw
, reg
, vlan_table
^ mask
);
260 * fm10k_read_mac_addr_pf - Read device MAC address
261 * @hw: pointer to the HW structure
263 * Reads the device MAC address from the SM_AREA and stores the value.
265 static s32
fm10k_read_mac_addr_pf(struct fm10k_hw
*hw
)
267 u8 perm_addr
[ETH_ALEN
];
270 serial_num
= fm10k_read_reg(hw
, FM10K_SM_AREA(1));
272 /* last byte should be all 1's */
273 if ((~serial_num
) << 24)
274 return FM10K_ERR_INVALID_MAC_ADDR
;
276 perm_addr
[0] = (u8
)(serial_num
>> 24);
277 perm_addr
[1] = (u8
)(serial_num
>> 16);
278 perm_addr
[2] = (u8
)(serial_num
>> 8);
280 serial_num
= fm10k_read_reg(hw
, FM10K_SM_AREA(0));
282 /* first byte should be all 1's */
283 if ((~serial_num
) >> 24)
284 return FM10K_ERR_INVALID_MAC_ADDR
;
286 perm_addr
[3] = (u8
)(serial_num
>> 16);
287 perm_addr
[4] = (u8
)(serial_num
>> 8);
288 perm_addr
[5] = (u8
)(serial_num
);
290 ether_addr_copy(hw
->mac
.perm_addr
, perm_addr
);
291 ether_addr_copy(hw
->mac
.addr
, perm_addr
);
297 * fm10k_glort_valid_pf - Validate that the provided glort is valid
298 * @hw: pointer to the HW structure
299 * @glort: base glort to be validated
301 * This function will return an error if the provided glort is invalid
303 bool fm10k_glort_valid_pf(struct fm10k_hw
*hw
, u16 glort
)
305 glort
&= hw
->mac
.dglort_map
>> FM10K_DGLORTMAP_MASK_SHIFT
;
307 return glort
== (hw
->mac
.dglort_map
& FM10K_DGLORTMAP_NONE
);
311 * fm10k_update_xc_addr_pf - Update device addresses
312 * @hw: pointer to the HW structure
313 * @glort: base resource tag for this request
314 * @mac: MAC address to add/remove from table
315 * @vid: VLAN ID to add/remove from table
316 * @add: Indicates if this is an add or remove operation
317 * @flags: flags field to indicate add and secure
319 * This function generates a message to the Switch API requesting
320 * that the given logical port add/remove the given L2 MAC/VLAN address.
322 static s32
fm10k_update_xc_addr_pf(struct fm10k_hw
*hw
, u16 glort
,
323 const u8
*mac
, u16 vid
, bool add
, u8 flags
)
325 struct fm10k_mbx_info
*mbx
= &hw
->mbx
;
326 struct fm10k_mac_update mac_update
;
329 /* clear set bit from VLAN ID */
330 vid
&= ~FM10K_VLAN_CLEAR
;
332 /* if glort or VLAN are not valid return error */
333 if (!fm10k_glort_valid_pf(hw
, glort
) || vid
>= FM10K_VLAN_TABLE_VID_MAX
)
334 return FM10K_ERR_PARAM
;
337 mac_update
.mac_lower
= cpu_to_le32(((u32
)mac
[2] << 24) |
338 ((u32
)mac
[3] << 16) |
341 mac_update
.mac_upper
= cpu_to_le16(((u16
)mac
[0] << 8) |
343 mac_update
.vlan
= cpu_to_le16(vid
);
344 mac_update
.glort
= cpu_to_le16(glort
);
345 mac_update
.action
= add
? 0 : 1;
346 mac_update
.flags
= flags
;
348 /* populate mac_update fields */
349 fm10k_tlv_msg_init(msg
, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE
);
350 fm10k_tlv_attr_put_le_struct(msg
, FM10K_PF_ATTR_ID_MAC_UPDATE
,
351 &mac_update
, sizeof(mac_update
));
353 /* load onto outgoing mailbox */
354 return mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
358 * fm10k_update_uc_addr_pf - Update device unicast addresses
359 * @hw: pointer to the HW structure
360 * @glort: base resource tag for this request
361 * @mac: MAC address to add/remove from table
362 * @vid: VLAN ID to add/remove from table
363 * @add: Indicates if this is an add or remove operation
364 * @flags: flags field to indicate add and secure
366 * This function is used to add or remove unicast addresses for
369 static s32
fm10k_update_uc_addr_pf(struct fm10k_hw
*hw
, u16 glort
,
370 const u8
*mac
, u16 vid
, bool add
, u8 flags
)
372 /* verify MAC address is valid */
373 if (!is_valid_ether_addr(mac
))
374 return FM10K_ERR_PARAM
;
376 return fm10k_update_xc_addr_pf(hw
, glort
, mac
, vid
, add
, flags
);
380 * fm10k_update_mc_addr_pf - Update device multicast addresses
381 * @hw: pointer to the HW structure
382 * @glort: base resource tag for this request
383 * @mac: MAC address to add/remove from table
384 * @vid: VLAN ID to add/remove from table
385 * @add: Indicates if this is an add or remove operation
387 * This function is used to add or remove multicast MAC addresses for
390 static s32
fm10k_update_mc_addr_pf(struct fm10k_hw
*hw
, u16 glort
,
391 const u8
*mac
, u16 vid
, bool add
)
393 /* verify multicast address is valid */
394 if (!is_multicast_ether_addr(mac
))
395 return FM10K_ERR_PARAM
;
397 return fm10k_update_xc_addr_pf(hw
, glort
, mac
, vid
, add
, 0);
401 * fm10k_update_xcast_mode_pf - Request update of multicast mode
402 * @hw: pointer to hardware structure
403 * @glort: base resource tag for this request
404 * @mode: integer value indicating mode being requested
406 * This function will attempt to request a higher mode for the port
407 * so that it can enable either multicast, multicast promiscuous, or
408 * promiscuous mode of operation.
410 static s32
fm10k_update_xcast_mode_pf(struct fm10k_hw
*hw
, u16 glort
, u8 mode
)
412 struct fm10k_mbx_info
*mbx
= &hw
->mbx
;
413 u32 msg
[3], xcast_mode
;
415 if (mode
> FM10K_XCAST_MODE_NONE
)
416 return FM10K_ERR_PARAM
;
418 /* if glort is not valid return error */
419 if (!fm10k_glort_valid_pf(hw
, glort
))
420 return FM10K_ERR_PARAM
;
422 /* write xcast mode as a single u32 value,
423 * lower 16 bits: glort
424 * upper 16 bits: mode
426 xcast_mode
= ((u32
)mode
<< 16) | glort
;
428 /* generate message requesting to change xcast mode */
429 fm10k_tlv_msg_init(msg
, FM10K_PF_MSG_ID_XCAST_MODES
);
430 fm10k_tlv_attr_put_u32(msg
, FM10K_PF_ATTR_ID_XCAST_MODE
, xcast_mode
);
432 /* load onto outgoing mailbox */
433 return mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
437 * fm10k_update_int_moderator_pf - Update interrupt moderator linked list
438 * @hw: pointer to hardware structure
440 * This function walks through the MSI-X vector table to determine the
441 * number of active interrupts and based on that information updates the
442 * interrupt moderator linked list.
444 static void fm10k_update_int_moderator_pf(struct fm10k_hw
*hw
)
448 /* Disable interrupt moderator */
449 fm10k_write_reg(hw
, FM10K_INT_CTRL
, 0);
451 /* loop through PF from last to first looking enabled vectors */
452 for (i
= FM10K_ITR_REG_COUNT_PF
- 1; i
; i
--) {
453 if (!fm10k_read_reg(hw
, FM10K_MSIX_VECTOR_MASK(i
)))
457 /* always reset VFITR2[0] to point to last enabled PF vector */
458 fm10k_write_reg(hw
, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF
), i
);
460 /* reset ITR2[0] to point to last enabled PF vector */
461 if (!hw
->iov
.num_vfs
)
462 fm10k_write_reg(hw
, FM10K_ITR2(0), i
);
464 /* Enable interrupt moderator */
465 fm10k_write_reg(hw
, FM10K_INT_CTRL
, FM10K_INT_CTRL_ENABLEMODERATOR
);
469 * fm10k_update_lport_state_pf - Notify the switch of a change in port state
470 * @hw: pointer to the HW structure
471 * @glort: base resource tag for this request
472 * @count: number of logical ports being updated
473 * @enable: boolean value indicating enable or disable
475 * This function is used to add/remove a logical port from the switch.
477 static s32
fm10k_update_lport_state_pf(struct fm10k_hw
*hw
, u16 glort
,
478 u16 count
, bool enable
)
480 struct fm10k_mbx_info
*mbx
= &hw
->mbx
;
481 u32 msg
[3], lport_msg
;
483 /* do nothing if we are being asked to create or destroy 0 ports */
487 /* if glort is not valid return error */
488 if (!fm10k_glort_valid_pf(hw
, glort
))
489 return FM10K_ERR_PARAM
;
491 /* construct the lport message from the 2 pieces of data we have */
492 lport_msg
= ((u32
)count
<< 16) | glort
;
494 /* generate lport create/delete message */
495 fm10k_tlv_msg_init(msg
, enable
? FM10K_PF_MSG_ID_LPORT_CREATE
:
496 FM10K_PF_MSG_ID_LPORT_DELETE
);
497 fm10k_tlv_attr_put_u32(msg
, FM10K_PF_ATTR_ID_PORT
, lport_msg
);
499 /* load onto outgoing mailbox */
500 return mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
504 * fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
505 * @hw: pointer to hardware structure
506 * @dglort: pointer to dglort configuration structure
508 * Reads the configuration structure contained in dglort_cfg and uses
509 * that information to then populate a DGLORTMAP/DEC entry and the queues
510 * to which it has been assigned.
512 static s32
fm10k_configure_dglort_map_pf(struct fm10k_hw
*hw
,
513 struct fm10k_dglort_cfg
*dglort
)
515 u16 glort
, queue_count
, vsi_count
, pc_count
;
516 u16 vsi
, queue
, pc
, q_idx
;
517 u32 txqctl
, dglortdec
, dglortmap
;
519 /* verify the dglort pointer */
521 return FM10K_ERR_PARAM
;
523 /* verify the dglort values */
524 if ((dglort
->idx
> 7) || (dglort
->rss_l
> 7) || (dglort
->pc_l
> 3) ||
525 (dglort
->vsi_l
> 6) || (dglort
->vsi_b
> 64) ||
526 (dglort
->queue_l
> 8) || (dglort
->queue_b
>= 256))
527 return FM10K_ERR_PARAM
;
529 /* determine count of VSIs and queues */
530 queue_count
= 1 << (dglort
->rss_l
+ dglort
->pc_l
);
531 vsi_count
= 1 << (dglort
->vsi_l
+ dglort
->queue_l
);
532 glort
= dglort
->glort
;
533 q_idx
= dglort
->queue_b
;
535 /* configure SGLORT for queues */
536 for (vsi
= 0; vsi
< vsi_count
; vsi
++, glort
++) {
537 for (queue
= 0; queue
< queue_count
; queue
++, q_idx
++) {
538 if (q_idx
>= FM10K_MAX_QUEUES
)
541 fm10k_write_reg(hw
, FM10K_TX_SGLORT(q_idx
), glort
);
542 fm10k_write_reg(hw
, FM10K_RX_SGLORT(q_idx
), glort
);
546 /* determine count of PCs and queues */
547 queue_count
= 1 << (dglort
->queue_l
+ dglort
->rss_l
+ dglort
->vsi_l
);
548 pc_count
= 1 << dglort
->pc_l
;
550 /* configure PC for Tx queues */
551 for (pc
= 0; pc
< pc_count
; pc
++) {
552 q_idx
= pc
+ dglort
->queue_b
;
553 for (queue
= 0; queue
< queue_count
; queue
++) {
554 if (q_idx
>= FM10K_MAX_QUEUES
)
557 txqctl
= fm10k_read_reg(hw
, FM10K_TXQCTL(q_idx
));
558 txqctl
&= ~FM10K_TXQCTL_PC_MASK
;
559 txqctl
|= pc
<< FM10K_TXQCTL_PC_SHIFT
;
560 fm10k_write_reg(hw
, FM10K_TXQCTL(q_idx
), txqctl
);
566 /* configure DGLORTDEC */
567 dglortdec
= ((u32
)(dglort
->rss_l
) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT
) |
568 ((u32
)(dglort
->queue_b
) << FM10K_DGLORTDEC_QBASE_SHIFT
) |
569 ((u32
)(dglort
->pc_l
) << FM10K_DGLORTDEC_PCLENGTH_SHIFT
) |
570 ((u32
)(dglort
->vsi_b
) << FM10K_DGLORTDEC_VSIBASE_SHIFT
) |
571 ((u32
)(dglort
->vsi_l
) << FM10K_DGLORTDEC_VSILENGTH_SHIFT
) |
572 ((u32
)(dglort
->queue_l
));
573 if (dglort
->inner_rss
)
574 dglortdec
|= FM10K_DGLORTDEC_INNERRSS_ENABLE
;
576 /* configure DGLORTMAP */
577 dglortmap
= (dglort
->idx
== fm10k_dglort_default
) ?
578 FM10K_DGLORTMAP_ANY
: FM10K_DGLORTMAP_ZERO
;
579 dglortmap
<<= dglort
->vsi_l
+ dglort
->queue_l
+ dglort
->shared_l
;
580 dglortmap
|= dglort
->glort
;
582 /* write values to hardware */
583 fm10k_write_reg(hw
, FM10K_DGLORTDEC(dglort
->idx
), dglortdec
);
584 fm10k_write_reg(hw
, FM10K_DGLORTMAP(dglort
->idx
), dglortmap
);
589 u16
fm10k_queues_per_pool(struct fm10k_hw
*hw
)
591 u16 num_pools
= hw
->iov
.num_pools
;
593 return (num_pools
> 32) ? 2 : (num_pools
> 16) ? 4 : (num_pools
> 8) ?
594 8 : FM10K_MAX_QUEUES_POOL
;
597 u16
fm10k_vf_queue_index(struct fm10k_hw
*hw
, u16 vf_idx
)
599 u16 num_vfs
= hw
->iov
.num_vfs
;
600 u16 vf_q_idx
= FM10K_MAX_QUEUES
;
602 vf_q_idx
-= fm10k_queues_per_pool(hw
) * (num_vfs
- vf_idx
);
607 static u16
fm10k_vectors_per_pool(struct fm10k_hw
*hw
)
609 u16 num_pools
= hw
->iov
.num_pools
;
611 return (num_pools
> 32) ? 8 : (num_pools
> 16) ? 16 :
612 FM10K_MAX_VECTORS_POOL
;
615 static u16
fm10k_vf_vector_index(struct fm10k_hw
*hw
, u16 vf_idx
)
617 u16 vf_v_idx
= FM10K_MAX_VECTORS_PF
;
619 vf_v_idx
+= fm10k_vectors_per_pool(hw
) * vf_idx
;
625 * fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
626 * @hw: pointer to the HW structure
627 * @num_vfs: number of VFs to be allocated
628 * @num_pools: number of virtualization pools to be allocated
630 * Allocates queues and traffic classes to virtualization entities to prepare
631 * the PF for SR-IOV and VMDq
633 static s32
fm10k_iov_assign_resources_pf(struct fm10k_hw
*hw
, u16 num_vfs
,
636 u16 qmap_stride
, qpp
, vpp
, vf_q_idx
, vf_q_idx0
, qmap_idx
;
637 u32 vid
= hw
->mac
.default_vid
<< FM10K_TXQCTL_VID_SHIFT
;
640 /* hardware only supports up to 64 pools */
642 return FM10K_ERR_PARAM
;
644 /* the number of VFs cannot exceed the number of pools */
645 if ((num_vfs
> num_pools
) || (num_vfs
> hw
->iov
.total_vfs
))
646 return FM10K_ERR_PARAM
;
648 /* record number of virtualization entities */
649 hw
->iov
.num_vfs
= num_vfs
;
650 hw
->iov
.num_pools
= num_pools
;
652 /* determine qmap offsets and counts */
653 qmap_stride
= (num_vfs
> 8) ? 32 : 256;
654 qpp
= fm10k_queues_per_pool(hw
);
655 vpp
= fm10k_vectors_per_pool(hw
);
657 /* calculate starting index for queues */
658 vf_q_idx
= fm10k_vf_queue_index(hw
, 0);
661 /* establish TCs with -1 credits and no quanta to prevent transmit */
662 for (i
= 0; i
< num_vfs
; i
++) {
663 fm10k_write_reg(hw
, FM10K_TC_MAXCREDIT(i
), 0);
664 fm10k_write_reg(hw
, FM10K_TC_RATE(i
), 0);
665 fm10k_write_reg(hw
, FM10K_TC_CREDIT(i
),
666 FM10K_TC_CREDIT_CREDIT_MASK
);
669 /* zero out all mbmem registers */
670 for (i
= FM10K_VFMBMEM_LEN
* num_vfs
; i
--;)
671 fm10k_write_reg(hw
, FM10K_MBMEM(i
), 0);
673 /* clear event notification of VF FLR */
674 fm10k_write_reg(hw
, FM10K_PFVFLREC(0), ~0);
675 fm10k_write_reg(hw
, FM10K_PFVFLREC(1), ~0);
677 /* loop through unallocated rings assigning them back to PF */
678 for (i
= FM10K_MAX_QUEUES_PF
; i
< vf_q_idx
; i
++) {
679 fm10k_write_reg(hw
, FM10K_TXDCTL(i
), 0);
680 fm10k_write_reg(hw
, FM10K_TXQCTL(i
), FM10K_TXQCTL_PF
|
681 FM10K_TXQCTL_UNLIMITED_BW
| vid
);
682 fm10k_write_reg(hw
, FM10K_RXQCTL(i
), FM10K_RXQCTL_PF
);
685 /* PF should have already updated VFITR2[0] */
687 /* update all ITR registers to flow to VFITR2[0] */
688 for (i
= FM10K_ITR_REG_COUNT_PF
+ 1; i
< FM10K_ITR_REG_COUNT
; i
++) {
689 if (!(i
& (vpp
- 1)))
690 fm10k_write_reg(hw
, FM10K_ITR2(i
), i
- vpp
);
692 fm10k_write_reg(hw
, FM10K_ITR2(i
), i
- 1);
695 /* update PF ITR2[0] to reference the last vector */
696 fm10k_write_reg(hw
, FM10K_ITR2(0),
697 fm10k_vf_vector_index(hw
, num_vfs
- 1));
699 /* loop through rings populating rings and TCs */
700 for (i
= 0; i
< num_vfs
; i
++) {
701 /* record index for VF queue 0 for use in end of loop */
702 vf_q_idx0
= vf_q_idx
;
704 for (j
= 0; j
< qpp
; j
++, qmap_idx
++, vf_q_idx
++) {
705 /* assign VF and locked TC to queues */
706 fm10k_write_reg(hw
, FM10K_TXDCTL(vf_q_idx
), 0);
707 fm10k_write_reg(hw
, FM10K_TXQCTL(vf_q_idx
),
708 (i
<< FM10K_TXQCTL_TC_SHIFT
) | i
|
709 FM10K_TXQCTL_VF
| vid
);
710 fm10k_write_reg(hw
, FM10K_RXDCTL(vf_q_idx
),
711 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY
|
712 FM10K_RXDCTL_DROP_ON_EMPTY
);
713 fm10k_write_reg(hw
, FM10K_RXQCTL(vf_q_idx
),
715 (i
<< FM10K_RXQCTL_VF_SHIFT
));
717 /* map queue pair to VF */
718 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), vf_q_idx
);
719 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
), vf_q_idx
);
722 /* repeat the first ring for all of the remaining VF rings */
723 for (; j
< qmap_stride
; j
++, qmap_idx
++) {
724 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), vf_q_idx0
);
725 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
), vf_q_idx0
);
729 /* loop through remaining indexes assigning all to queue 0 */
730 while (qmap_idx
< FM10K_TQMAP_TABLE_SIZE
) {
731 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), 0);
732 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
), 0);
740 * fm10k_iov_configure_tc_pf - Configure the shaping group for VF
741 * @hw: pointer to the HW structure
742 * @vf_idx: index of VF receiving GLORT
743 * @rate: Rate indicated in Mb/s
745 * Configured the TC for a given VF to allow only up to a given number
746 * of Mb/s of outgoing Tx throughput.
748 static s32
fm10k_iov_configure_tc_pf(struct fm10k_hw
*hw
, u16 vf_idx
, int rate
)
750 /* configure defaults */
751 u32 interval
= FM10K_TC_RATE_INTERVAL_4US_GEN3
;
752 u32 tc_rate
= FM10K_TC_RATE_QUANTA_MASK
;
754 /* verify vf is in range */
755 if (vf_idx
>= hw
->iov
.num_vfs
)
756 return FM10K_ERR_PARAM
;
758 /* set interval to align with 4.096 usec in all modes */
759 switch (hw
->bus
.speed
) {
760 case fm10k_bus_speed_2500
:
761 interval
= FM10K_TC_RATE_INTERVAL_4US_GEN1
;
763 case fm10k_bus_speed_5000
:
764 interval
= FM10K_TC_RATE_INTERVAL_4US_GEN2
;
771 if (rate
> FM10K_VF_TC_MAX
|| rate
< FM10K_VF_TC_MIN
)
772 return FM10K_ERR_PARAM
;
774 /* The quanta is measured in Bytes per 4.096 or 8.192 usec
775 * The rate is provided in Mbits per second
776 * To tralslate from rate to quanta we need to multiply the
777 * rate by 8.192 usec and divide by 8 bits/byte. To avoid
778 * dealing with floating point we can round the values up
779 * to the nearest whole number ratio which gives us 128 / 125.
781 tc_rate
= (rate
* 128) / 125;
783 /* try to keep the rate limiting accurate by increasing
784 * the number of credits and interval for rates less than 4Gb/s
792 /* update rate limiter with new values */
793 fm10k_write_reg(hw
, FM10K_TC_RATE(vf_idx
), tc_rate
| interval
);
794 fm10k_write_reg(hw
, FM10K_TC_MAXCREDIT(vf_idx
), FM10K_TC_MAXCREDIT_64K
);
795 fm10k_write_reg(hw
, FM10K_TC_CREDIT(vf_idx
), FM10K_TC_MAXCREDIT_64K
);
801 * fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
802 * @hw: pointer to the HW structure
803 * @vf_idx: index of VF receiving GLORT
805 * Update the interrupt moderator linked list to include any MSI-X
806 * interrupts which the VF has enabled in the MSI-X vector table.
808 static s32
fm10k_iov_assign_int_moderator_pf(struct fm10k_hw
*hw
, u16 vf_idx
)
810 u16 vf_v_idx
, vf_v_limit
, i
;
812 /* verify vf is in range */
813 if (vf_idx
>= hw
->iov
.num_vfs
)
814 return FM10K_ERR_PARAM
;
816 /* determine vector offset and count */
817 vf_v_idx
= fm10k_vf_vector_index(hw
, vf_idx
);
818 vf_v_limit
= vf_v_idx
+ fm10k_vectors_per_pool(hw
);
820 /* search for first vector that is not masked */
821 for (i
= vf_v_limit
- 1; i
> vf_v_idx
; i
--) {
822 if (!fm10k_read_reg(hw
, FM10K_MSIX_VECTOR_MASK(i
)))
826 /* reset linked list so it now includes our active vectors */
827 if (vf_idx
== (hw
->iov
.num_vfs
- 1))
828 fm10k_write_reg(hw
, FM10K_ITR2(0), i
);
830 fm10k_write_reg(hw
, FM10K_ITR2(vf_v_limit
), i
);
836 * fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
837 * @hw: pointer to the HW structure
838 * @vf_info: pointer to VF information structure
840 * Assign a MAC address and default VLAN to a VF and notify it of the update
842 static s32
fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw
*hw
,
843 struct fm10k_vf_info
*vf_info
)
845 u16 qmap_stride
, queues_per_pool
, vf_q_idx
, timeout
, qmap_idx
, i
;
846 u32 msg
[4], txdctl
, txqctl
, tdbal
= 0, tdbah
= 0;
850 /* verify vf is in range */
851 if (!vf_info
|| vf_info
->vf_idx
>= hw
->iov
.num_vfs
)
852 return FM10K_ERR_PARAM
;
854 /* determine qmap offsets and counts */
855 qmap_stride
= (hw
->iov
.num_vfs
> 8) ? 32 : 256;
856 queues_per_pool
= fm10k_queues_per_pool(hw
);
858 /* calculate starting index for queues */
859 vf_idx
= vf_info
->vf_idx
;
860 vf_q_idx
= fm10k_vf_queue_index(hw
, vf_idx
);
861 qmap_idx
= qmap_stride
* vf_idx
;
863 /* MAP Tx queue back to 0 temporarily, and disable it */
864 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), 0);
865 fm10k_write_reg(hw
, FM10K_TXDCTL(vf_q_idx
), 0);
867 /* determine correct default VLAN ID */
869 vf_vid
= vf_info
->pf_vid
| FM10K_VLAN_CLEAR
;
871 vf_vid
= vf_info
->sw_vid
;
873 /* generate MAC_ADDR request */
874 fm10k_tlv_msg_init(msg
, FM10K_VF_MSG_ID_MAC_VLAN
);
875 fm10k_tlv_attr_put_mac_vlan(msg
, FM10K_MAC_VLAN_MSG_DEFAULT_MAC
,
876 vf_info
->mac
, vf_vid
);
878 /* load onto outgoing mailbox, ignore any errors on enqueue */
879 if (vf_info
->mbx
.ops
.enqueue_tx
)
880 vf_info
->mbx
.ops
.enqueue_tx(hw
, &vf_info
->mbx
, msg
);
882 /* verify ring has disabled before modifying base address registers */
883 txdctl
= fm10k_read_reg(hw
, FM10K_TXDCTL(vf_q_idx
));
884 for (timeout
= 0; txdctl
& FM10K_TXDCTL_ENABLE
; timeout
++) {
885 /* limit ourselves to a 1ms timeout */
887 err
= FM10K_ERR_DMA_PENDING
;
891 usleep_range(100, 200);
892 txdctl
= fm10k_read_reg(hw
, FM10K_TXDCTL(vf_q_idx
));
895 /* Update base address registers to contain MAC address */
896 if (is_valid_ether_addr(vf_info
->mac
)) {
897 tdbal
= (((u32
)vf_info
->mac
[3]) << 24) |
898 (((u32
)vf_info
->mac
[4]) << 16) |
899 (((u32
)vf_info
->mac
[5]) << 8);
901 tdbah
= (((u32
)0xFF) << 24) |
902 (((u32
)vf_info
->mac
[0]) << 16) |
903 (((u32
)vf_info
->mac
[1]) << 8) |
904 ((u32
)vf_info
->mac
[2]);
907 /* Record the base address into queue 0 */
908 fm10k_write_reg(hw
, FM10K_TDBAL(vf_q_idx
), tdbal
);
909 fm10k_write_reg(hw
, FM10K_TDBAH(vf_q_idx
), tdbah
);
911 /* Provide the VF the ITR scale, using software-defined fields in TDLEN
912 * to pass the information during VF initialization. See definition of
913 * FM10K_TDLEN_ITR_SCALE_SHIFT for more details.
915 fm10k_write_reg(hw
, FM10K_TDLEN(vf_q_idx
), hw
->mac
.itr_scale
<<
916 FM10K_TDLEN_ITR_SCALE_SHIFT
);
919 /* configure Queue control register */
920 txqctl
= ((u32
)vf_vid
<< FM10K_TXQCTL_VID_SHIFT
) &
921 FM10K_TXQCTL_VID_MASK
;
922 txqctl
|= (vf_idx
<< FM10K_TXQCTL_TC_SHIFT
) |
923 FM10K_TXQCTL_VF
| vf_idx
;
926 for (i
= 0; i
< queues_per_pool
; i
++)
927 fm10k_write_reg(hw
, FM10K_TXQCTL(vf_q_idx
+ i
), txqctl
);
929 /* restore the queue back to VF ownership */
930 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
), vf_q_idx
);
935 * fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
936 * @hw: pointer to the HW structure
937 * @vf_info: pointer to VF information structure
939 * Reassign the interrupts and queues to a VF following an FLR
941 static s32
fm10k_iov_reset_resources_pf(struct fm10k_hw
*hw
,
942 struct fm10k_vf_info
*vf_info
)
944 u16 qmap_stride
, queues_per_pool
, vf_q_idx
, qmap_idx
;
945 u32 tdbal
= 0, tdbah
= 0, txqctl
, rxqctl
;
946 u16 vf_v_idx
, vf_v_limit
, vf_vid
;
947 u8 vf_idx
= vf_info
->vf_idx
;
950 /* verify vf is in range */
951 if (vf_idx
>= hw
->iov
.num_vfs
)
952 return FM10K_ERR_PARAM
;
954 /* clear event notification of VF FLR */
955 fm10k_write_reg(hw
, FM10K_PFVFLREC(vf_idx
/ 32), 1 << (vf_idx
% 32));
957 /* force timeout and then disconnect the mailbox */
958 vf_info
->mbx
.timeout
= 0;
959 if (vf_info
->mbx
.ops
.disconnect
)
960 vf_info
->mbx
.ops
.disconnect(hw
, &vf_info
->mbx
);
962 /* determine vector offset and count */
963 vf_v_idx
= fm10k_vf_vector_index(hw
, vf_idx
);
964 vf_v_limit
= vf_v_idx
+ fm10k_vectors_per_pool(hw
);
966 /* determine qmap offsets and counts */
967 qmap_stride
= (hw
->iov
.num_vfs
> 8) ? 32 : 256;
968 queues_per_pool
= fm10k_queues_per_pool(hw
);
969 qmap_idx
= qmap_stride
* vf_idx
;
971 /* make all the queues inaccessible to the VF */
972 for (i
= qmap_idx
; i
< (qmap_idx
+ qmap_stride
); i
++) {
973 fm10k_write_reg(hw
, FM10K_TQMAP(i
), 0);
974 fm10k_write_reg(hw
, FM10K_RQMAP(i
), 0);
977 /* calculate starting index for queues */
978 vf_q_idx
= fm10k_vf_queue_index(hw
, vf_idx
);
980 /* determine correct default VLAN ID */
982 vf_vid
= vf_info
->pf_vid
;
984 vf_vid
= vf_info
->sw_vid
;
986 /* configure Queue control register */
987 txqctl
= ((u32
)vf_vid
<< FM10K_TXQCTL_VID_SHIFT
) |
988 (vf_idx
<< FM10K_TXQCTL_TC_SHIFT
) |
989 FM10K_TXQCTL_VF
| vf_idx
;
990 rxqctl
= FM10K_RXQCTL_VF
| (vf_idx
<< FM10K_RXQCTL_VF_SHIFT
);
992 /* stop further DMA and reset queue ownership back to VF */
993 for (i
= vf_q_idx
; i
< (queues_per_pool
+ vf_q_idx
); i
++) {
994 fm10k_write_reg(hw
, FM10K_TXDCTL(i
), 0);
995 fm10k_write_reg(hw
, FM10K_TXQCTL(i
), txqctl
);
996 fm10k_write_reg(hw
, FM10K_RXDCTL(i
),
997 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY
|
998 FM10K_RXDCTL_DROP_ON_EMPTY
);
999 fm10k_write_reg(hw
, FM10K_RXQCTL(i
), rxqctl
);
1002 /* reset TC with -1 credits and no quanta to prevent transmit */
1003 fm10k_write_reg(hw
, FM10K_TC_MAXCREDIT(vf_idx
), 0);
1004 fm10k_write_reg(hw
, FM10K_TC_RATE(vf_idx
), 0);
1005 fm10k_write_reg(hw
, FM10K_TC_CREDIT(vf_idx
),
1006 FM10K_TC_CREDIT_CREDIT_MASK
);
1008 /* update our first entry in the table based on previous VF */
1010 hw
->mac
.ops
.update_int_moderator(hw
);
1012 hw
->iov
.ops
.assign_int_moderator(hw
, vf_idx
- 1);
1014 /* reset linked list so it now includes our active vectors */
1015 if (vf_idx
== (hw
->iov
.num_vfs
- 1))
1016 fm10k_write_reg(hw
, FM10K_ITR2(0), vf_v_idx
);
1018 fm10k_write_reg(hw
, FM10K_ITR2(vf_v_limit
), vf_v_idx
);
1020 /* link remaining vectors so that next points to previous */
1021 for (vf_v_idx
++; vf_v_idx
< vf_v_limit
; vf_v_idx
++)
1022 fm10k_write_reg(hw
, FM10K_ITR2(vf_v_idx
), vf_v_idx
- 1);
1024 /* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1025 for (i
= FM10K_VFMBMEM_LEN
; i
--;)
1026 fm10k_write_reg(hw
, FM10K_MBMEM_VF(vf_idx
, i
), 0);
1027 for (i
= FM10K_VLAN_TABLE_SIZE
; i
--;)
1028 fm10k_write_reg(hw
, FM10K_VLAN_TABLE(vf_info
->vsi
, i
), 0);
1029 for (i
= FM10K_RETA_SIZE
; i
--;)
1030 fm10k_write_reg(hw
, FM10K_RETA(vf_info
->vsi
, i
), 0);
1031 for (i
= FM10K_RSSRK_SIZE
; i
--;)
1032 fm10k_write_reg(hw
, FM10K_RSSRK(vf_info
->vsi
, i
), 0);
1033 fm10k_write_reg(hw
, FM10K_MRQC(vf_info
->vsi
), 0);
1035 /* Update base address registers to contain MAC address */
1036 if (is_valid_ether_addr(vf_info
->mac
)) {
1037 tdbal
= (((u32
)vf_info
->mac
[3]) << 24) |
1038 (((u32
)vf_info
->mac
[4]) << 16) |
1039 (((u32
)vf_info
->mac
[5]) << 8);
1040 tdbah
= (((u32
)0xFF) << 24) |
1041 (((u32
)vf_info
->mac
[0]) << 16) |
1042 (((u32
)vf_info
->mac
[1]) << 8) |
1043 ((u32
)vf_info
->mac
[2]);
1046 /* map queue pairs back to VF from last to first */
1047 for (i
= queues_per_pool
; i
--;) {
1048 fm10k_write_reg(hw
, FM10K_TDBAL(vf_q_idx
+ i
), tdbal
);
1049 fm10k_write_reg(hw
, FM10K_TDBAH(vf_q_idx
+ i
), tdbah
);
1050 /* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an
1051 * explanation of how TDLEN is used.
1053 fm10k_write_reg(hw
, FM10K_TDLEN(vf_q_idx
+ i
),
1054 hw
->mac
.itr_scale
<<
1055 FM10K_TDLEN_ITR_SCALE_SHIFT
);
1056 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
+ i
), vf_q_idx
+ i
);
1057 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
+ i
), vf_q_idx
+ i
);
1060 /* repeat the first ring for all the remaining VF rings */
1061 for (i
= queues_per_pool
; i
< qmap_stride
; i
++) {
1062 fm10k_write_reg(hw
, FM10K_TQMAP(qmap_idx
+ i
), vf_q_idx
);
1063 fm10k_write_reg(hw
, FM10K_RQMAP(qmap_idx
+ i
), vf_q_idx
);
1070 * fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1071 * @hw: pointer to hardware structure
1072 * @vf_info: pointer to VF information structure
1073 * @lport_idx: Logical port offset from the hardware glort
1074 * @flags: Set of capability flags to extend port beyond basic functionality
1076 * This function allows enabling a VF port by assigning it a GLORT and
1077 * setting the flags so that it can enable an Rx mode.
1079 static s32
fm10k_iov_set_lport_pf(struct fm10k_hw
*hw
,
1080 struct fm10k_vf_info
*vf_info
,
1081 u16 lport_idx
, u8 flags
)
1083 u16 glort
= (hw
->mac
.dglort_map
+ lport_idx
) & FM10K_DGLORTMAP_NONE
;
1085 /* if glort is not valid return error */
1086 if (!fm10k_glort_valid_pf(hw
, glort
))
1087 return FM10K_ERR_PARAM
;
1089 vf_info
->vf_flags
= flags
| FM10K_VF_FLAG_NONE_CAPABLE
;
1090 vf_info
->glort
= glort
;
1096 * fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1097 * @hw: pointer to hardware structure
1098 * @vf_info: pointer to VF information structure
1100 * This function disables a VF port by stripping it of a GLORT and
1101 * setting the flags so that it cannot enable any Rx mode.
1103 static void fm10k_iov_reset_lport_pf(struct fm10k_hw
*hw
,
1104 struct fm10k_vf_info
*vf_info
)
1108 /* need to disable the port if it is already enabled */
1109 if (FM10K_VF_FLAG_ENABLED(vf_info
)) {
1110 /* notify switch that this port has been disabled */
1111 fm10k_update_lport_state_pf(hw
, vf_info
->glort
, 1, false);
1113 /* generate port state response to notify VF it is not ready */
1114 fm10k_tlv_msg_init(msg
, FM10K_VF_MSG_ID_LPORT_STATE
);
1115 vf_info
->mbx
.ops
.enqueue_tx(hw
, &vf_info
->mbx
, msg
);
1118 /* clear flags and glort if it exists */
1119 vf_info
->vf_flags
= 0;
1124 * fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1125 * @hw: pointer to hardware structure
1126 * @q: stats for all queues of a VF
1127 * @vf_idx: index of VF
1129 * This function collects queue stats for VFs.
1131 static void fm10k_iov_update_stats_pf(struct fm10k_hw
*hw
,
1132 struct fm10k_hw_stats_q
*q
,
1137 /* get stats for all of the queues */
1138 qpp
= fm10k_queues_per_pool(hw
);
1139 idx
= fm10k_vf_queue_index(hw
, vf_idx
);
1140 fm10k_update_hw_stats_q(hw
, q
, idx
, qpp
);
1143 static s32
fm10k_iov_report_timestamp_pf(struct fm10k_hw
*hw
,
1144 struct fm10k_vf_info
*vf_info
,
1149 /* generate port state response to notify VF it is not ready */
1150 fm10k_tlv_msg_init(msg
, FM10K_VF_MSG_ID_1588
);
1151 fm10k_tlv_attr_put_u64(msg
, FM10K_1588_MSG_TIMESTAMP
, timestamp
);
1153 return vf_info
->mbx
.ops
.enqueue_tx(hw
, &vf_info
->mbx
, msg
);
1157 * fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1158 * @hw: Pointer to hardware structure
1159 * @results: Pointer array to message, results[0] is pointer to message
1160 * @mbx: Pointer to mailbox information structure
1162 * This function is a default handler for MSI-X requests from the VF. The
1163 * assumption is that in this case it is acceptable to just directly
1164 * hand off the message from the VF to the underlying shared code.
1166 s32
fm10k_iov_msg_msix_pf(struct fm10k_hw
*hw
, u32
**results
,
1167 struct fm10k_mbx_info
*mbx
)
1169 struct fm10k_vf_info
*vf_info
= (struct fm10k_vf_info
*)mbx
;
1170 u8 vf_idx
= vf_info
->vf_idx
;
1172 return hw
->iov
.ops
.assign_int_moderator(hw
, vf_idx
);
1176 * fm10k_iov_select_vid - Select correct default VLAN ID
1177 * @hw: Pointer to hardware structure
1178 * @vid: VLAN ID to correct
1180 * Will report an error if the VLAN ID is out of range. For VID = 0, it will
1181 * return either the pf_vid or sw_vid depending on which one is set.
1183 static s32
fm10k_iov_select_vid(struct fm10k_vf_info
*vf_info
, u16 vid
)
1186 return vf_info
->pf_vid
? vf_info
->pf_vid
: vf_info
->sw_vid
;
1187 else if (vf_info
->pf_vid
&& vid
!= vf_info
->pf_vid
)
1188 return FM10K_ERR_PARAM
;
1194 * fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1195 * @hw: Pointer to hardware structure
1196 * @results: Pointer array to message, results[0] is pointer to message
1197 * @mbx: Pointer to mailbox information structure
1199 * This function is a default handler for MAC/VLAN requests from the VF.
1200 * The assumption is that in this case it is acceptable to just directly
1201 * hand off the message from the VF to the underlying shared code.
1203 s32
fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw
*hw
, u32
**results
,
1204 struct fm10k_mbx_info
*mbx
)
1206 struct fm10k_vf_info
*vf_info
= (struct fm10k_vf_info
*)mbx
;
1214 /* we shouldn't be updating rules on a disabled interface */
1215 if (!FM10K_VF_FLAG_ENABLED(vf_info
))
1216 err
= FM10K_ERR_PARAM
;
1218 if (!err
&& !!results
[FM10K_MAC_VLAN_MSG_VLAN
]) {
1219 result
= results
[FM10K_MAC_VLAN_MSG_VLAN
];
1221 /* record VLAN id requested */
1222 err
= fm10k_tlv_attr_get_u32(result
, &vid
);
1226 /* verify upper 16 bits are zero */
1228 return FM10K_ERR_PARAM
;
1230 set
= !(vid
& FM10K_VLAN_CLEAR
);
1231 vid
&= ~FM10K_VLAN_CLEAR
;
1233 err
= fm10k_iov_select_vid(vf_info
, (u16
)vid
);
1239 /* update VSI info for VF in regards to VLAN table */
1240 err
= hw
->mac
.ops
.update_vlan(hw
, vid
, vf_info
->vsi
, set
);
1243 if (!err
&& !!results
[FM10K_MAC_VLAN_MSG_MAC
]) {
1244 result
= results
[FM10K_MAC_VLAN_MSG_MAC
];
1246 /* record unicast MAC address requested */
1247 err
= fm10k_tlv_attr_get_mac_vlan(result
, mac
, &vlan
);
1251 /* block attempts to set MAC for a locked device */
1252 if (is_valid_ether_addr(vf_info
->mac
) &&
1253 !ether_addr_equal(mac
, vf_info
->mac
))
1254 return FM10K_ERR_PARAM
;
1256 set
= !(vlan
& FM10K_VLAN_CLEAR
);
1257 vlan
&= ~FM10K_VLAN_CLEAR
;
1259 err
= fm10k_iov_select_vid(vf_info
, vlan
);
1265 /* notify switch of request for new unicast address */
1266 err
= hw
->mac
.ops
.update_uc_addr(hw
, vf_info
->glort
,
1270 if (!err
&& !!results
[FM10K_MAC_VLAN_MSG_MULTICAST
]) {
1271 result
= results
[FM10K_MAC_VLAN_MSG_MULTICAST
];
1273 /* record multicast MAC address requested */
1274 err
= fm10k_tlv_attr_get_mac_vlan(result
, mac
, &vlan
);
1278 /* verify that the VF is allowed to request multicast */
1279 if (!(vf_info
->vf_flags
& FM10K_VF_FLAG_MULTI_ENABLED
))
1280 return FM10K_ERR_PARAM
;
1282 set
= !(vlan
& FM10K_VLAN_CLEAR
);
1283 vlan
&= ~FM10K_VLAN_CLEAR
;
1285 err
= fm10k_iov_select_vid(vf_info
, vlan
);
1291 /* notify switch of request for new multicast address */
1292 err
= hw
->mac
.ops
.update_mc_addr(hw
, vf_info
->glort
,
1300 * fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1301 * @vf_info: VF info structure containing capability flags
1302 * @mode: Requested xcast mode
1304 * This function outputs the mode that most closely matches the requested
1305 * mode. If not modes match it will request we disable the port
1307 static u8
fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info
*vf_info
,
1310 u8 vf_flags
= vf_info
->vf_flags
;
1312 /* match up mode to capabilities as best as possible */
1314 case FM10K_XCAST_MODE_PROMISC
:
1315 if (vf_flags
& FM10K_VF_FLAG_PROMISC_CAPABLE
)
1316 return FM10K_XCAST_MODE_PROMISC
;
1318 case FM10K_XCAST_MODE_ALLMULTI
:
1319 if (vf_flags
& FM10K_VF_FLAG_ALLMULTI_CAPABLE
)
1320 return FM10K_XCAST_MODE_ALLMULTI
;
1322 case FM10K_XCAST_MODE_MULTI
:
1323 if (vf_flags
& FM10K_VF_FLAG_MULTI_CAPABLE
)
1324 return FM10K_XCAST_MODE_MULTI
;
1326 case FM10K_XCAST_MODE_NONE
:
1327 if (vf_flags
& FM10K_VF_FLAG_NONE_CAPABLE
)
1328 return FM10K_XCAST_MODE_NONE
;
1334 /* disable interface as it should not be able to request any */
1335 return FM10K_XCAST_MODE_DISABLE
;
1339 * fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1340 * @hw: Pointer to hardware structure
1341 * @results: Pointer array to message, results[0] is pointer to message
1342 * @mbx: Pointer to mailbox information structure
1344 * This function is a default handler for port state requests. The port
1345 * state requests for now are basic and consist of enabling or disabling
1348 s32
fm10k_iov_msg_lport_state_pf(struct fm10k_hw
*hw
, u32
**results
,
1349 struct fm10k_mbx_info
*mbx
)
1351 struct fm10k_vf_info
*vf_info
= (struct fm10k_vf_info
*)mbx
;
1357 /* verify VF is allowed to enable even minimal mode */
1358 if (!(vf_info
->vf_flags
& FM10K_VF_FLAG_NONE_CAPABLE
))
1359 return FM10K_ERR_PARAM
;
1361 if (!!results
[FM10K_LPORT_STATE_MSG_XCAST_MODE
]) {
1362 result
= results
[FM10K_LPORT_STATE_MSG_XCAST_MODE
];
1364 /* XCAST mode update requested */
1365 err
= fm10k_tlv_attr_get_u8(result
, &mode
);
1367 return FM10K_ERR_PARAM
;
1369 /* prep for possible demotion depending on capabilities */
1370 mode
= fm10k_iov_supported_xcast_mode_pf(vf_info
, mode
);
1372 /* if mode is not currently enabled, enable it */
1373 if (!(FM10K_VF_FLAG_ENABLED(vf_info
) & (1 << mode
)))
1374 fm10k_update_xcast_mode_pf(hw
, vf_info
->glort
, mode
);
1376 /* swap mode back to a bit flag */
1377 mode
= FM10K_VF_FLAG_SET_MODE(mode
);
1378 } else if (!results
[FM10K_LPORT_STATE_MSG_DISABLE
]) {
1379 /* need to disable the port if it is already enabled */
1380 if (FM10K_VF_FLAG_ENABLED(vf_info
))
1381 err
= fm10k_update_lport_state_pf(hw
, vf_info
->glort
,
1384 /* we need to clear VF_FLAG_ENABLED flags in order to ensure
1385 * that we actually re-enable the LPORT state below. Note that
1386 * this has no impact if the VF is already disabled, as the
1387 * flags are already cleared.
1390 vf_info
->vf_flags
= FM10K_VF_FLAG_CAPABLE(vf_info
);
1392 /* when enabling the port we should reset the rate limiters */
1393 hw
->iov
.ops
.configure_tc(hw
, vf_info
->vf_idx
, vf_info
->rate
);
1395 /* set mode for minimal functionality */
1396 mode
= FM10K_VF_FLAG_SET_MODE_NONE
;
1398 /* generate port state response to notify VF it is ready */
1399 fm10k_tlv_msg_init(msg
, FM10K_VF_MSG_ID_LPORT_STATE
);
1400 fm10k_tlv_attr_put_bool(msg
, FM10K_LPORT_STATE_MSG_READY
);
1401 mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
1404 /* if enable state toggled note the update */
1405 if (!err
&& (!FM10K_VF_FLAG_ENABLED(vf_info
) != !mode
))
1406 err
= fm10k_update_lport_state_pf(hw
, vf_info
->glort
, 1,
1409 /* if state change succeeded, then update our stored state */
1410 mode
|= FM10K_VF_FLAG_CAPABLE(vf_info
);
1412 vf_info
->vf_flags
= mode
;
1418 * fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1419 * @hw: pointer to hardware structure
1420 * @stats: pointer to the stats structure to update
1422 * This function collects and aggregates global and per queue hardware
1425 static void fm10k_update_hw_stats_pf(struct fm10k_hw
*hw
,
1426 struct fm10k_hw_stats
*stats
)
1428 u32 timeout
, ur
, ca
, um
, xec
, vlan_drop
, loopback_drop
, nodesc_drop
;
1431 /* Use Tx queue 0 as a canary to detect a reset */
1432 id
= fm10k_read_reg(hw
, FM10K_TXQCTL(0));
1434 /* Read Global Statistics */
1436 timeout
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_TIMEOUT
,
1438 ur
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_UR
, &stats
->ur
);
1439 ca
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_CA
, &stats
->ca
);
1440 um
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_UM
, &stats
->um
);
1441 xec
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_XEC
, &stats
->xec
);
1442 vlan_drop
= fm10k_read_hw_stats_32b(hw
, FM10K_STATS_VLAN_DROP
,
1445 fm10k_read_hw_stats_32b(hw
,
1446 FM10K_STATS_LOOPBACK_DROP
,
1447 &stats
->loopback_drop
);
1448 nodesc_drop
= fm10k_read_hw_stats_32b(hw
,
1449 FM10K_STATS_NODESC_DROP
,
1450 &stats
->nodesc_drop
);
1452 /* if value has not changed then we have consistent data */
1454 id
= fm10k_read_reg(hw
, FM10K_TXQCTL(0));
1455 } while ((id
^ id_prev
) & FM10K_TXQCTL_ID_MASK
);
1457 /* drop non-ID bits and set VALID ID bit */
1458 id
&= FM10K_TXQCTL_ID_MASK
;
1459 id
|= FM10K_STAT_VALID
;
1461 /* Update Global Statistics */
1462 if (stats
->stats_idx
== id
) {
1463 stats
->timeout
.count
+= timeout
;
1464 stats
->ur
.count
+= ur
;
1465 stats
->ca
.count
+= ca
;
1466 stats
->um
.count
+= um
;
1467 stats
->xec
.count
+= xec
;
1468 stats
->vlan_drop
.count
+= vlan_drop
;
1469 stats
->loopback_drop
.count
+= loopback_drop
;
1470 stats
->nodesc_drop
.count
+= nodesc_drop
;
1473 /* Update bases and record current PF id */
1474 fm10k_update_hw_base_32b(&stats
->timeout
, timeout
);
1475 fm10k_update_hw_base_32b(&stats
->ur
, ur
);
1476 fm10k_update_hw_base_32b(&stats
->ca
, ca
);
1477 fm10k_update_hw_base_32b(&stats
->um
, um
);
1478 fm10k_update_hw_base_32b(&stats
->xec
, xec
);
1479 fm10k_update_hw_base_32b(&stats
->vlan_drop
, vlan_drop
);
1480 fm10k_update_hw_base_32b(&stats
->loopback_drop
, loopback_drop
);
1481 fm10k_update_hw_base_32b(&stats
->nodesc_drop
, nodesc_drop
);
1482 stats
->stats_idx
= id
;
1484 /* Update Queue Statistics */
1485 fm10k_update_hw_stats_q(hw
, stats
->q
, 0, hw
->mac
.max_queues
);
1489 * fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1490 * @hw: pointer to hardware structure
1491 * @stats: pointer to the stats structure to update
1493 * This function resets the base for global and per queue hardware
1496 static void fm10k_rebind_hw_stats_pf(struct fm10k_hw
*hw
,
1497 struct fm10k_hw_stats
*stats
)
1499 /* Unbind Global Statistics */
1500 fm10k_unbind_hw_stats_32b(&stats
->timeout
);
1501 fm10k_unbind_hw_stats_32b(&stats
->ur
);
1502 fm10k_unbind_hw_stats_32b(&stats
->ca
);
1503 fm10k_unbind_hw_stats_32b(&stats
->um
);
1504 fm10k_unbind_hw_stats_32b(&stats
->xec
);
1505 fm10k_unbind_hw_stats_32b(&stats
->vlan_drop
);
1506 fm10k_unbind_hw_stats_32b(&stats
->loopback_drop
);
1507 fm10k_unbind_hw_stats_32b(&stats
->nodesc_drop
);
1509 /* Unbind Queue Statistics */
1510 fm10k_unbind_hw_stats_q(stats
->q
, 0, hw
->mac
.max_queues
);
1512 /* Reinitialize bases for all stats */
1513 fm10k_update_hw_stats_pf(hw
, stats
);
1517 * fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1518 * @hw: pointer to hardware structure
1519 * @dma_mask: 64 bit DMA mask required for platform
1521 * This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1522 * to limit the access to memory beyond what is physically in the system.
1524 static void fm10k_set_dma_mask_pf(struct fm10k_hw
*hw
, u64 dma_mask
)
1526 /* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1527 u32 phyaddr
= (u32
)(dma_mask
>> 32);
1529 fm10k_write_reg(hw
, FM10K_PHYADDR
, phyaddr
);
1533 * fm10k_get_fault_pf - Record a fault in one of the interface units
1534 * @hw: pointer to hardware structure
1535 * @type: pointer to fault type register offset
1536 * @fault: pointer to memory location to record the fault
1538 * Record the fault register contents to the fault data structure and
1539 * clear the entry from the register.
1541 * Returns ERR_PARAM if invalid register is specified or no error is present.
1543 static s32
fm10k_get_fault_pf(struct fm10k_hw
*hw
, int type
,
1544 struct fm10k_fault
*fault
)
1548 /* verify the fault register is in range and is aligned */
1550 case FM10K_PCA_FAULT
:
1551 case FM10K_THI_FAULT
:
1552 case FM10K_FUM_FAULT
:
1555 return FM10K_ERR_PARAM
;
1558 /* only service faults that are valid */
1559 func
= fm10k_read_reg(hw
, type
+ FM10K_FAULT_FUNC
);
1560 if (!(func
& FM10K_FAULT_FUNC_VALID
))
1561 return FM10K_ERR_PARAM
;
1563 /* read remaining fields */
1564 fault
->address
= fm10k_read_reg(hw
, type
+ FM10K_FAULT_ADDR_HI
);
1565 fault
->address
<<= 32;
1566 fault
->address
= fm10k_read_reg(hw
, type
+ FM10K_FAULT_ADDR_LO
);
1567 fault
->specinfo
= fm10k_read_reg(hw
, type
+ FM10K_FAULT_SPECINFO
);
1569 /* clear valid bit to allow for next error */
1570 fm10k_write_reg(hw
, type
+ FM10K_FAULT_FUNC
, FM10K_FAULT_FUNC_VALID
);
1572 /* Record which function triggered the error */
1573 if (func
& FM10K_FAULT_FUNC_PF
)
1576 fault
->func
= 1 + ((func
& FM10K_FAULT_FUNC_VF_MASK
) >>
1577 FM10K_FAULT_FUNC_VF_SHIFT
);
1579 /* record fault type */
1580 fault
->type
= func
& FM10K_FAULT_FUNC_TYPE_MASK
;
1586 * fm10k_request_lport_map_pf - Request LPORT map from the switch API
1587 * @hw: pointer to hardware structure
1590 static s32
fm10k_request_lport_map_pf(struct fm10k_hw
*hw
)
1592 struct fm10k_mbx_info
*mbx
= &hw
->mbx
;
1595 /* issue request asking for LPORT map */
1596 fm10k_tlv_msg_init(msg
, FM10K_PF_MSG_ID_LPORT_MAP
);
1598 /* load onto outgoing mailbox */
1599 return mbx
->ops
.enqueue_tx(hw
, mbx
, msg
);
1603 * fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1604 * @hw: pointer to hardware structure
1605 * @switch_ready: pointer to boolean value that will record switch state
1607 * This funciton will check the DMA_CTRL2 register and mailbox in order
1608 * to determine if the switch is ready for the PF to begin requesting
1609 * addresses and mapping traffic to the local interface.
1611 static s32
fm10k_get_host_state_pf(struct fm10k_hw
*hw
, bool *switch_ready
)
1616 /* verify the switch is ready for interaction */
1617 dma_ctrl2
= fm10k_read_reg(hw
, FM10K_DMA_CTRL2
);
1618 if (!(dma_ctrl2
& FM10K_DMA_CTRL2_SWITCH_READY
))
1621 /* retrieve generic host state info */
1622 ret_val
= fm10k_get_host_state_generic(hw
, switch_ready
);
1626 /* interface cannot receive traffic without logical ports */
1627 if (hw
->mac
.dglort_map
== FM10K_DGLORTMAP_NONE
)
1628 ret_val
= fm10k_request_lport_map_pf(hw
);
1634 /* This structure defines the attibutes to be parsed below */
1635 const struct fm10k_tlv_attr fm10k_lport_map_msg_attr
[] = {
1636 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP
),
1641 * fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1642 * @hw: Pointer to hardware structure
1643 * @results: pointer array containing parsed data
1644 * @mbx: Pointer to mailbox information structure
1646 * This handler configures the lport mapping based on the reply from the
1649 s32
fm10k_msg_lport_map_pf(struct fm10k_hw
*hw
, u32
**results
,
1650 struct fm10k_mbx_info
*mbx
)
1656 err
= fm10k_tlv_attr_get_u32(results
[FM10K_PF_ATTR_ID_LPORT_MAP
],
1661 /* extract values out of the header */
1662 glort
= FM10K_MSG_HDR_FIELD_GET(dglort_map
, LPORT_MAP_GLORT
);
1663 mask
= FM10K_MSG_HDR_FIELD_GET(dglort_map
, LPORT_MAP_MASK
);
1665 /* verify mask is set and none of the masked bits in glort are set */
1666 if (!mask
|| (glort
& ~mask
))
1667 return FM10K_ERR_PARAM
;
1669 /* verify the mask is contiguous, and that it is 1's followed by 0's */
1670 if (((~(mask
- 1) & mask
) + mask
) & FM10K_DGLORTMAP_NONE
)
1671 return FM10K_ERR_PARAM
;
1673 /* record the glort, mask, and port count */
1674 hw
->mac
.dglort_map
= dglort_map
;
1679 const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr
[] = {
1680 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID
),
1685 * fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1686 * @hw: Pointer to hardware structure
1687 * @results: pointer array containing parsed data
1688 * @mbx: Pointer to mailbox information structure
1690 * This handler configures the default VLAN for the PF
1692 static s32
fm10k_msg_update_pvid_pf(struct fm10k_hw
*hw
, u32
**results
,
1693 struct fm10k_mbx_info
*mbx
)
1699 err
= fm10k_tlv_attr_get_u32(results
[FM10K_PF_ATTR_ID_UPDATE_PVID
],
1704 /* extract values from the pvid update */
1705 glort
= FM10K_MSG_HDR_FIELD_GET(pvid_update
, UPDATE_PVID_GLORT
);
1706 pvid
= FM10K_MSG_HDR_FIELD_GET(pvid_update
, UPDATE_PVID_PVID
);
1708 /* if glort is not valid return error */
1709 if (!fm10k_glort_valid_pf(hw
, glort
))
1710 return FM10K_ERR_PARAM
;
1712 /* verify VLAN ID is valid */
1713 if (pvid
>= FM10K_VLAN_TABLE_VID_MAX
)
1714 return FM10K_ERR_PARAM
;
1716 /* record the port VLAN ID value */
1717 hw
->mac
.default_vid
= pvid
;
1723 * fm10k_record_global_table_data - Move global table data to swapi table info
1724 * @from: pointer to source table data structure
1725 * @to: pointer to destination table info structure
1727 * This function is will copy table_data to the table_info contained in
1730 static void fm10k_record_global_table_data(struct fm10k_global_table_data
*from
,
1731 struct fm10k_swapi_table_info
*to
)
1733 /* convert from le32 struct to CPU byte ordered values */
1734 to
->used
= le32_to_cpu(from
->used
);
1735 to
->avail
= le32_to_cpu(from
->avail
);
1738 const struct fm10k_tlv_attr fm10k_err_msg_attr
[] = {
1739 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR
,
1740 sizeof(struct fm10k_swapi_error
)),
1745 * fm10k_msg_err_pf - Message handler for error reply
1746 * @hw: Pointer to hardware structure
1747 * @results: pointer array containing parsed data
1748 * @mbx: Pointer to mailbox information structure
1750 * This handler will capture the data for any error replies to previous
1751 * messages that the PF has sent.
1753 s32
fm10k_msg_err_pf(struct fm10k_hw
*hw
, u32
**results
,
1754 struct fm10k_mbx_info
*mbx
)
1756 struct fm10k_swapi_error err_msg
;
1759 /* extract structure from message */
1760 err
= fm10k_tlv_attr_get_le_struct(results
[FM10K_PF_ATTR_ID_ERR
],
1761 &err_msg
, sizeof(err_msg
));
1765 /* record table status */
1766 fm10k_record_global_table_data(&err_msg
.mac
, &hw
->swapi
.mac
);
1767 fm10k_record_global_table_data(&err_msg
.nexthop
, &hw
->swapi
.nexthop
);
1768 fm10k_record_global_table_data(&err_msg
.ffu
, &hw
->swapi
.ffu
);
1770 /* record SW API status value */
1771 hw
->swapi
.status
= le32_to_cpu(err_msg
.status
);
1776 const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr
[] = {
1777 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP
,
1778 sizeof(struct fm10k_swapi_1588_timestamp
)),
1782 /* currently there is no shared 1588 timestamp handler */
1785 * fm10k_adjust_systime_pf - Adjust systime frequency
1786 * @hw: pointer to hardware structure
1787 * @ppb: adjustment rate in parts per billion
1789 * This function will adjust the SYSTIME_CFG register contained in BAR 4
1790 * if this function is supported for BAR 4 access. The adjustment amount
1791 * is based on the parts per billion value provided and adjusted to a
1792 * value based on parts per 2^48 clock cycles.
1794 * If adjustment is not supported or the requested value is too large
1795 * we will return an error.
1797 static s32
fm10k_adjust_systime_pf(struct fm10k_hw
*hw
, s32 ppb
)
1801 /* if sw_addr is not set we don't have switch register access */
1803 return ppb
? FM10K_ERR_PARAM
: 0;
1805 /* we must convert the value from parts per billion to parts per
1806 * 2^48 cycles. In addition I have opted to only use the 30 most
1807 * significant bits of the adjustment value as the 8 least
1808 * significant bits are located in another register and represent
1809 * a value significantly less than a part per billion, the result
1810 * of dropping the 8 least significant bits is that the adjustment
1811 * value is effectively multiplied by 2^8 when we write it.
1813 * As a result of all this the math for this breaks down as follows:
1814 * ppb / 10^9 == adjust * 2^8 / 2^48
1815 * If we solve this for adjust, and simplify it comes out as:
1816 * ppb * 2^31 / 5^9 == adjust
1818 systime_adjust
= (ppb
< 0) ? -ppb
: ppb
;
1819 systime_adjust
<<= 31;
1820 do_div(systime_adjust
, 1953125);
1822 /* verify the requested adjustment value is in range */
1823 if (systime_adjust
> FM10K_SW_SYSTIME_ADJUST_MASK
)
1824 return FM10K_ERR_PARAM
;
1827 systime_adjust
|= FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE
;
1829 fm10k_write_sw_reg(hw
, FM10K_SW_SYSTIME_ADJUST
, (u32
)systime_adjust
);
1835 * fm10k_read_systime_pf - Reads value of systime registers
1836 * @hw: pointer to the hardware structure
1838 * Function reads the content of 2 registers, combined to represent a 64 bit
1839 * value measured in nanosecods. In order to guarantee the value is accurate
1840 * we check the 32 most significant bits both before and after reading the
1841 * 32 least significant bits to verify they didn't change as we were reading
1844 static u64
fm10k_read_systime_pf(struct fm10k_hw
*hw
)
1846 u32 systime_l
, systime_h
, systime_tmp
;
1848 systime_h
= fm10k_read_reg(hw
, FM10K_SYSTIME
+ 1);
1851 systime_tmp
= systime_h
;
1852 systime_l
= fm10k_read_reg(hw
, FM10K_SYSTIME
);
1853 systime_h
= fm10k_read_reg(hw
, FM10K_SYSTIME
+ 1);
1854 } while (systime_tmp
!= systime_h
);
1856 return ((u64
)systime_h
<< 32) | systime_l
;
1859 static const struct fm10k_msg_data fm10k_msg_data_pf
[] = {
1860 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES
, fm10k_msg_err_pf
),
1861 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE
, fm10k_msg_err_pf
),
1862 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf
),
1863 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE
, fm10k_msg_err_pf
),
1864 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE
, fm10k_msg_err_pf
),
1865 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf
),
1866 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error
),
1869 static const struct fm10k_mac_ops mac_ops_pf
= {
1870 .get_bus_info
= fm10k_get_bus_info_generic
,
1871 .reset_hw
= fm10k_reset_hw_pf
,
1872 .init_hw
= fm10k_init_hw_pf
,
1873 .start_hw
= fm10k_start_hw_generic
,
1874 .stop_hw
= fm10k_stop_hw_generic
,
1875 .update_vlan
= fm10k_update_vlan_pf
,
1876 .read_mac_addr
= fm10k_read_mac_addr_pf
,
1877 .update_uc_addr
= fm10k_update_uc_addr_pf
,
1878 .update_mc_addr
= fm10k_update_mc_addr_pf
,
1879 .update_xcast_mode
= fm10k_update_xcast_mode_pf
,
1880 .update_int_moderator
= fm10k_update_int_moderator_pf
,
1881 .update_lport_state
= fm10k_update_lport_state_pf
,
1882 .update_hw_stats
= fm10k_update_hw_stats_pf
,
1883 .rebind_hw_stats
= fm10k_rebind_hw_stats_pf
,
1884 .configure_dglort_map
= fm10k_configure_dglort_map_pf
,
1885 .set_dma_mask
= fm10k_set_dma_mask_pf
,
1886 .get_fault
= fm10k_get_fault_pf
,
1887 .get_host_state
= fm10k_get_host_state_pf
,
1888 .adjust_systime
= fm10k_adjust_systime_pf
,
1889 .read_systime
= fm10k_read_systime_pf
,
1892 static const struct fm10k_iov_ops iov_ops_pf
= {
1893 .assign_resources
= fm10k_iov_assign_resources_pf
,
1894 .configure_tc
= fm10k_iov_configure_tc_pf
,
1895 .assign_int_moderator
= fm10k_iov_assign_int_moderator_pf
,
1896 .assign_default_mac_vlan
= fm10k_iov_assign_default_mac_vlan_pf
,
1897 .reset_resources
= fm10k_iov_reset_resources_pf
,
1898 .set_lport
= fm10k_iov_set_lport_pf
,
1899 .reset_lport
= fm10k_iov_reset_lport_pf
,
1900 .update_stats
= fm10k_iov_update_stats_pf
,
1901 .report_timestamp
= fm10k_iov_report_timestamp_pf
,
1904 static s32
fm10k_get_invariants_pf(struct fm10k_hw
*hw
)
1906 fm10k_get_invariants_generic(hw
);
1908 return fm10k_sm_mbx_init(hw
, &hw
->mbx
, fm10k_msg_data_pf
);
1911 const struct fm10k_info fm10k_pf_info
= {
1912 .mac
= fm10k_mac_pf
,
1913 .get_invariants
= fm10k_get_invariants_pf
,
1914 .mac_ops
= &mac_ops_pf
,
1915 .iov_ops
= &iov_ops_pf
,