1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
33 * This file needs to comply with the Linux Kernel coding style.
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0004
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
94 enum i40e_admin_queue_err
{
95 I40E_AQ_RC_OK
= 0, /* success */
96 I40E_AQ_RC_EPERM
= 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT
= 2, /* No such element */
98 I40E_AQ_RC_ESRCH
= 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR
= 4, /* operation interrupted */
100 I40E_AQ_RC_EIO
= 5, /* I/O error */
101 I40E_AQ_RC_ENXIO
= 6, /* No such resource */
102 I40E_AQ_RC_E2BIG
= 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN
= 8, /* Try again */
104 I40E_AQ_RC_ENOMEM
= 9, /* Out of memory */
105 I40E_AQ_RC_EACCES
= 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT
= 11, /* Bad address */
107 I40E_AQ_RC_EBUSY
= 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST
= 13, /* object already exists */
109 I40E_AQ_RC_EINVAL
= 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY
= 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC
= 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS
= 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE
= 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED
= 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR
= 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE
= 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG
= 22, /* File too large */
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc
{
123 i40e_aqc_opc_get_version
= 0x0001,
124 i40e_aqc_opc_driver_version
= 0x0002,
125 i40e_aqc_opc_queue_shutdown
= 0x0003,
126 i40e_aqc_opc_set_pf_context
= 0x0004,
128 /* resource ownership */
129 i40e_aqc_opc_request_resource
= 0x0008,
130 i40e_aqc_opc_release_resource
= 0x0009,
132 i40e_aqc_opc_list_func_capabilities
= 0x000A,
133 i40e_aqc_opc_list_dev_capabilities
= 0x000B,
136 i40e_aqc_opc_mac_address_read
= 0x0107,
137 i40e_aqc_opc_mac_address_write
= 0x0108,
140 i40e_aqc_opc_clear_pxe_mode
= 0x0110,
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config
= 0x0200,
144 i40e_aqc_opc_add_statistics
= 0x0201,
145 i40e_aqc_opc_remove_statistics
= 0x0202,
146 i40e_aqc_opc_set_port_parameters
= 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc
= 0x0204,
148 i40e_aqc_opc_set_switch_config
= 0x0205,
150 i40e_aqc_opc_add_vsi
= 0x0210,
151 i40e_aqc_opc_update_vsi_parameters
= 0x0211,
152 i40e_aqc_opc_get_vsi_parameters
= 0x0212,
154 i40e_aqc_opc_add_pv
= 0x0220,
155 i40e_aqc_opc_update_pv_parameters
= 0x0221,
156 i40e_aqc_opc_get_pv_parameters
= 0x0222,
158 i40e_aqc_opc_add_veb
= 0x0230,
159 i40e_aqc_opc_update_veb_parameters
= 0x0231,
160 i40e_aqc_opc_get_veb_parameters
= 0x0232,
162 i40e_aqc_opc_delete_element
= 0x0243,
164 i40e_aqc_opc_add_macvlan
= 0x0250,
165 i40e_aqc_opc_remove_macvlan
= 0x0251,
166 i40e_aqc_opc_add_vlan
= 0x0252,
167 i40e_aqc_opc_remove_vlan
= 0x0253,
168 i40e_aqc_opc_set_vsi_promiscuous_modes
= 0x0254,
169 i40e_aqc_opc_add_tag
= 0x0255,
170 i40e_aqc_opc_remove_tag
= 0x0256,
171 i40e_aqc_opc_add_multicast_etag
= 0x0257,
172 i40e_aqc_opc_remove_multicast_etag
= 0x0258,
173 i40e_aqc_opc_update_tag
= 0x0259,
174 i40e_aqc_opc_add_control_packet_filter
= 0x025A,
175 i40e_aqc_opc_remove_control_packet_filter
= 0x025B,
176 i40e_aqc_opc_add_cloud_filters
= 0x025C,
177 i40e_aqc_opc_remove_cloud_filters
= 0x025D,
179 i40e_aqc_opc_add_mirror_rule
= 0x0260,
180 i40e_aqc_opc_delete_mirror_rule
= 0x0261,
183 i40e_aqc_opc_dcb_ignore_pfc
= 0x0301,
184 i40e_aqc_opc_dcb_updated
= 0x0302,
187 i40e_aqc_opc_configure_vsi_bw_limit
= 0x0400,
188 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit
= 0x0406,
189 i40e_aqc_opc_configure_vsi_tc_bw
= 0x0407,
190 i40e_aqc_opc_query_vsi_bw_config
= 0x0408,
191 i40e_aqc_opc_query_vsi_ets_sla_config
= 0x040A,
192 i40e_aqc_opc_configure_switching_comp_bw_limit
= 0x0410,
194 i40e_aqc_opc_enable_switching_comp_ets
= 0x0413,
195 i40e_aqc_opc_modify_switching_comp_ets
= 0x0414,
196 i40e_aqc_opc_disable_switching_comp_ets
= 0x0415,
197 i40e_aqc_opc_configure_switching_comp_ets_bw_limit
= 0x0416,
198 i40e_aqc_opc_configure_switching_comp_bw_config
= 0x0417,
199 i40e_aqc_opc_query_switching_comp_ets_config
= 0x0418,
200 i40e_aqc_opc_query_port_ets_config
= 0x0419,
201 i40e_aqc_opc_query_switching_comp_bw_config
= 0x041A,
202 i40e_aqc_opc_suspend_port_tx
= 0x041B,
203 i40e_aqc_opc_resume_port_tx
= 0x041C,
204 i40e_aqc_opc_configure_partition_bw
= 0x041D,
207 i40e_aqc_opc_query_hmc_resource_profile
= 0x0500,
208 i40e_aqc_opc_set_hmc_resource_profile
= 0x0501,
211 i40e_aqc_opc_get_phy_abilities
= 0x0600,
212 i40e_aqc_opc_set_phy_config
= 0x0601,
213 i40e_aqc_opc_set_mac_config
= 0x0603,
214 i40e_aqc_opc_set_link_restart_an
= 0x0605,
215 i40e_aqc_opc_get_link_status
= 0x0607,
216 i40e_aqc_opc_set_phy_int_mask
= 0x0613,
217 i40e_aqc_opc_get_local_advt_reg
= 0x0614,
218 i40e_aqc_opc_set_local_advt_reg
= 0x0615,
219 i40e_aqc_opc_get_partner_advt
= 0x0616,
220 i40e_aqc_opc_set_lb_modes
= 0x0618,
221 i40e_aqc_opc_get_phy_wol_caps
= 0x0621,
222 i40e_aqc_opc_set_phy_debug
= 0x0622,
223 i40e_aqc_opc_upload_ext_phy_fm
= 0x0625,
224 i40e_aqc_opc_run_phy_activity
= 0x0626,
227 i40e_aqc_opc_nvm_read
= 0x0701,
228 i40e_aqc_opc_nvm_erase
= 0x0702,
229 i40e_aqc_opc_nvm_update
= 0x0703,
230 i40e_aqc_opc_nvm_config_read
= 0x0704,
231 i40e_aqc_opc_nvm_config_write
= 0x0705,
232 i40e_aqc_opc_oem_post_update
= 0x0720,
234 /* virtualization commands */
235 i40e_aqc_opc_send_msg_to_pf
= 0x0801,
236 i40e_aqc_opc_send_msg_to_vf
= 0x0802,
237 i40e_aqc_opc_send_msg_to_peer
= 0x0803,
239 /* alternate structure */
240 i40e_aqc_opc_alternate_write
= 0x0900,
241 i40e_aqc_opc_alternate_write_indirect
= 0x0901,
242 i40e_aqc_opc_alternate_read
= 0x0902,
243 i40e_aqc_opc_alternate_read_indirect
= 0x0903,
244 i40e_aqc_opc_alternate_write_done
= 0x0904,
245 i40e_aqc_opc_alternate_set_mode
= 0x0905,
246 i40e_aqc_opc_alternate_clear_port
= 0x0906,
249 i40e_aqc_opc_lldp_get_mib
= 0x0A00,
250 i40e_aqc_opc_lldp_update_mib
= 0x0A01,
251 i40e_aqc_opc_lldp_add_tlv
= 0x0A02,
252 i40e_aqc_opc_lldp_update_tlv
= 0x0A03,
253 i40e_aqc_opc_lldp_delete_tlv
= 0x0A04,
254 i40e_aqc_opc_lldp_stop
= 0x0A05,
255 i40e_aqc_opc_lldp_start
= 0x0A06,
256 i40e_aqc_opc_get_cee_dcb_cfg
= 0x0A07,
257 i40e_aqc_opc_lldp_set_local_mib
= 0x0A08,
258 i40e_aqc_opc_lldp_stop_start_spec_agent
= 0x0A09,
260 /* Tunnel commands */
261 i40e_aqc_opc_add_udp_tunnel
= 0x0B00,
262 i40e_aqc_opc_del_udp_tunnel
= 0x0B01,
263 i40e_aqc_opc_set_rss_key
= 0x0B02,
264 i40e_aqc_opc_set_rss_lut
= 0x0B03,
265 i40e_aqc_opc_get_rss_key
= 0x0B04,
266 i40e_aqc_opc_get_rss_lut
= 0x0B05,
269 i40e_aqc_opc_event_lan_overflow
= 0x1001,
272 i40e_aqc_opc_oem_parameter_change
= 0xFE00,
273 i40e_aqc_opc_oem_device_status_change
= 0xFE01,
274 i40e_aqc_opc_oem_ocsd_initialize
= 0xFE02,
275 i40e_aqc_opc_oem_ocbb_initialize
= 0xFE03,
278 i40e_aqc_opc_debug_read_reg
= 0xFF03,
279 i40e_aqc_opc_debug_write_reg
= 0xFF04,
280 i40e_aqc_opc_debug_modify_reg
= 0xFF07,
281 i40e_aqc_opc_debug_dump_internals
= 0xFF08,
284 /* command structures and indirect data structures */
286 /* Structure naming conventions:
287 * - no suffix for direct command descriptor structures
288 * - _data for indirect sent data
289 * - _resp for indirect return data (data which is both will use _data)
290 * - _completion for direct return data
291 * - _element_ for repeated elements (may also be _data or _resp)
293 * Command structures are expected to overlay the params.raw member of the basic
294 * descriptor, and as such cannot exceed 16 bytes in length.
297 /* This macro is used to generate a compilation error if a structure
298 * is not exactly the correct length. It gives a divide by zero error if the
299 * structure is not of the correct size, otherwise it creates an enum that is
302 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
303 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
305 /* This macro is used extensively to ensure that command structures are 16
306 * bytes in length as they have to map to the raw array of that size.
308 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
310 /* internal (0x00XX) commands */
312 /* Get version (direct 0x0001) */
313 struct i40e_aqc_get_version
{
322 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version
);
324 /* Send driver version (indirect 0x0002) */
325 struct i40e_aqc_driver_version
{
329 u8 driver_subbuild_ver
;
335 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version
);
337 /* Queue Shutdown (direct 0x0003) */
338 struct i40e_aqc_queue_shutdown
{
339 __le32 driver_unloading
;
340 #define I40E_AQ_DRIVER_UNLOADING 0x1
344 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown
);
346 /* Set PF context (0x0004, direct) */
347 struct i40e_aqc_set_pf_context
{
352 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context
);
354 /* Request resource ownership (direct 0x0008)
355 * Release resource ownership (direct 0x0009)
357 #define I40E_AQ_RESOURCE_NVM 1
358 #define I40E_AQ_RESOURCE_SDP 2
359 #define I40E_AQ_RESOURCE_ACCESS_READ 1
360 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
361 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
362 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
364 struct i40e_aqc_request_resource
{
368 __le32 resource_number
;
372 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource
);
374 /* Get function capabilities (indirect 0x000A)
375 * Get device capabilities (indirect 0x000B)
377 struct i40e_aqc_list_capabilites
{
379 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
387 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites
);
389 struct i40e_aqc_list_capabilities_element_resp
{
401 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
402 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
403 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
404 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
405 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
406 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
407 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
408 #define I40E_AQ_CAP_ID_SRIOV 0x0012
409 #define I40E_AQ_CAP_ID_VF 0x0013
410 #define I40E_AQ_CAP_ID_VMDQ 0x0014
411 #define I40E_AQ_CAP_ID_8021QBG 0x0015
412 #define I40E_AQ_CAP_ID_8021QBR 0x0016
413 #define I40E_AQ_CAP_ID_VSI 0x0017
414 #define I40E_AQ_CAP_ID_DCB 0x0018
415 #define I40E_AQ_CAP_ID_FCOE 0x0021
416 #define I40E_AQ_CAP_ID_ISCSI 0x0022
417 #define I40E_AQ_CAP_ID_RSS 0x0040
418 #define I40E_AQ_CAP_ID_RXQ 0x0041
419 #define I40E_AQ_CAP_ID_TXQ 0x0042
420 #define I40E_AQ_CAP_ID_MSIX 0x0043
421 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
422 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
423 #define I40E_AQ_CAP_ID_1588 0x0046
424 #define I40E_AQ_CAP_ID_IWARP 0x0051
425 #define I40E_AQ_CAP_ID_LED 0x0061
426 #define I40E_AQ_CAP_ID_SDP 0x0062
427 #define I40E_AQ_CAP_ID_MDIO 0x0063
428 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
429 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
430 #define I40E_AQ_CAP_ID_CEM 0x00F2
432 /* Set CPPM Configuration (direct 0x0103) */
433 struct i40e_aqc_cppm_configuration
{
434 __le16 command_flags
;
435 #define I40E_AQ_CPPM_EN_LTRC 0x0800
436 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
437 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
438 #define I40E_AQ_CPPM_EN_HPTC 0x4000
439 #define I40E_AQ_CPPM_EN_DMARC 0x8000
448 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration
);
450 /* Set ARP Proxy command / response (indirect 0x0104) */
451 struct i40e_aqc_arp_proxy_data
{
452 __le16 command_flags
;
453 #define I40E_AQ_ARP_INIT_IPV4 0x0008
454 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
455 #define I40E_AQ_ARP_ENA 0x0020
456 #define I40E_AQ_ARP_ADD_IPV4 0x0040
457 #define I40E_AQ_ARP_DEL_IPV4 0x0080
465 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data
);
467 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
468 struct i40e_aqc_ns_proxy_data
{
469 __le16 table_idx_mac_addr_0
;
470 __le16 table_idx_mac_addr_1
;
471 __le16 table_idx_ipv6_0
;
472 __le16 table_idx_ipv6_1
;
474 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
475 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
476 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
477 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
478 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
479 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
480 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
481 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
482 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
483 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
484 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
487 u8 local_mac_addr
[6];
488 u8 ipv6_addr_0
[16]; /* Warning! spec specifies BE byte order */
492 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data
);
494 /* Manage LAA Command (0x0106) - obsolete */
495 struct i40e_aqc_mng_laa
{
496 __le16 command_flags
;
497 #define I40E_AQ_LAA_FLAG_WR 0x8000
504 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa
);
506 /* Manage MAC Address Read Command (indirect 0x0107) */
507 struct i40e_aqc_mac_address_read
{
508 __le16 command_flags
;
509 #define I40E_AQC_LAN_ADDR_VALID 0x10
510 #define I40E_AQC_SAN_ADDR_VALID 0x20
511 #define I40E_AQC_PORT_ADDR_VALID 0x40
512 #define I40E_AQC_WOL_ADDR_VALID 0x80
513 #define I40E_AQC_MC_MAG_EN_VALID 0x100
514 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
520 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read
);
522 struct i40e_aqc_mac_address_read_data
{
529 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data
);
531 /* Manage MAC Address Write Command (0x0108) */
532 struct i40e_aqc_mac_address_write
{
533 __le16 command_flags
;
534 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
535 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
536 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
537 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
538 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
545 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write
);
547 /* PXE commands (0x011x) */
549 /* Clear PXE Command and response (direct 0x0110) */
550 struct i40e_aqc_clear_pxe
{
555 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe
);
557 /* Switch configuration commands (0x02xx) */
559 /* Used by many indirect commands that only pass an seid and a buffer in the
562 struct i40e_aqc_switch_seid
{
569 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid
);
571 /* Get Switch Configuration command (indirect 0x0200)
572 * uses i40e_aqc_switch_seid for the descriptor
574 struct i40e_aqc_get_switch_config_header_resp
{
580 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp
);
582 struct i40e_aqc_switch_config_element_resp
{
584 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
585 #define I40E_AQ_SW_ELEM_TYPE_PF 2
586 #define I40E_AQ_SW_ELEM_TYPE_VF 3
587 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
588 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
589 #define I40E_AQ_SW_ELEM_TYPE_PV 16
590 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
591 #define I40E_AQ_SW_ELEM_TYPE_PA 18
592 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
594 #define I40E_AQ_SW_ELEM_REV_1 1
597 __le16 downlink_seid
;
600 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
601 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
602 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
607 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp
);
609 /* Get Switch Configuration (indirect 0x0200)
610 * an array of elements are returned in the response buffer
611 * the first in the array is the header, remainder are elements
613 struct i40e_aqc_get_switch_config_resp
{
614 struct i40e_aqc_get_switch_config_header_resp header
;
615 struct i40e_aqc_switch_config_element_resp element
[1];
618 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp
);
620 /* Add Statistics (direct 0x0201)
621 * Remove Statistics (direct 0x0202)
623 struct i40e_aqc_add_remove_statistics
{
630 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics
);
632 /* Set Port Parameters command (direct 0x0203) */
633 struct i40e_aqc_set_port_parameters
{
634 __le16 command_flags
;
635 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
636 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
637 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
638 __le16 bad_frame_vsi
;
639 __le16 default_seid
; /* reserved for command */
643 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters
);
645 /* Get Switch Resource Allocation (indirect 0x0204) */
646 struct i40e_aqc_get_switch_resource_alloc
{
647 u8 num_entries
; /* reserved for command */
653 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc
);
655 /* expect an array of these structs in the response buffer */
656 struct i40e_aqc_switch_resource_alloc_element_resp
{
658 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
659 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
660 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
661 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
662 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
663 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
664 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
665 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
666 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
667 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
668 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
669 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
670 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
671 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
672 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
673 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
674 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
675 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
676 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
681 __le16 total_unalloced
;
685 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp
);
687 /* Set Switch Configuration (direct 0x0205) */
688 struct i40e_aqc_set_switch_config
{
690 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
691 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
696 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config
);
698 /* Add VSI (indirect 0x0210)
699 * this indirect command uses struct i40e_aqc_vsi_properties_data
700 * as the indirect buffer (128 bytes)
702 * Update VSI (indirect 0x211)
703 * uses the same data structure as Add VSI
705 * Get VSI (indirect 0x0212)
706 * uses the same completion and data structure as Add VSI
708 struct i40e_aqc_add_get_update_vsi
{
711 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
712 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
713 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
718 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
719 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
720 #define I40E_AQ_VSI_TYPE_VF 0x0
721 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
722 #define I40E_AQ_VSI_TYPE_PF 0x2
723 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
724 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
729 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi
);
731 struct i40e_aqc_add_get_update_vsi_completion
{
740 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion
);
742 struct i40e_aqc_vsi_properties_data
{
743 /* first 96 byte are written by SW */
744 __le16 valid_sections
;
745 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
746 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
747 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
748 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
749 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
750 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
751 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
752 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
753 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
754 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
756 __le16 switch_id
; /* 12bit id combined with flags below */
757 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
758 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
759 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
760 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
761 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
763 /* security section */
765 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
766 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
767 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
770 __le16 pvid
; /* VLANS include priority bits */
773 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
774 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
775 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
776 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
777 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
778 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
779 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
780 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
781 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
782 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
783 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
784 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
785 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
786 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
787 u8 pvlan_reserved
[3];
788 /* ingress egress up sections */
789 __le32 ingress_table
; /* bitmap, 3 bits per up */
790 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
791 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
792 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
793 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
794 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
795 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
796 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
797 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
798 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
799 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
800 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
801 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
802 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
803 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
804 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
805 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
806 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
807 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
808 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
809 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
810 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
811 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
812 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
813 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
814 __le32 egress_table
; /* same defines as for ingress table */
815 /* cascaded PV section */
818 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
819 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
820 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
821 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
822 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
823 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
824 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
825 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
826 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
828 /* queue mapping section */
829 __le16 mapping_flags
;
830 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
831 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
832 __le16 queue_mapping
[16];
833 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
834 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
835 __le16 tc_mapping
[8];
836 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
837 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
838 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
839 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
840 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
841 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
842 /* queueing option section */
843 u8 queueing_opt_flags
;
844 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
845 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
846 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
847 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
848 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
849 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
850 u8 queueing_opt_reserved
[3];
851 /* scheduler section */
854 /* outer up section */
855 __le32 outer_up_table
; /* same structure and defines as ingress tbl */
857 /* last 32 bytes are written by FW */
859 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
860 __le16 stat_counter_idx
;
862 u8 resp_reserved
[12];
865 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data
);
867 /* Add Port Virtualizer (direct 0x0220)
868 * also used for update PV (direct 0x0221) but only flags are used
869 * (IS_CTRL_PORT only works on add PV)
871 struct i40e_aqc_add_update_pv
{
872 __le16 command_flags
;
873 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
874 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
875 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
876 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
878 __le16 connected_seid
;
882 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv
);
884 struct i40e_aqc_add_update_pv_completion
{
885 /* reserved for update; for add also encodes error if rc == ENOSPC */
887 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
888 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
889 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
890 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
894 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion
);
896 /* Get PV Params (direct 0x0222)
897 * uses i40e_aqc_switch_seid for the descriptor
900 struct i40e_aqc_get_pv_params_completion
{
903 __le16 pv_flags
; /* same flags as add_pv */
904 #define I40E_AQC_GET_PV_PV_TYPE 0x1
905 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
906 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
908 __le16 default_port_seid
;
911 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion
);
913 /* Add VEB (direct 0x0230) */
914 struct i40e_aqc_add_veb
{
916 __le16 downlink_seid
;
918 #define I40E_AQC_ADD_VEB_FLOATING 0x1
919 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
920 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
921 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
922 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
923 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
924 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
925 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
930 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb
);
932 struct i40e_aqc_add_veb_completion
{
935 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
937 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
938 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
939 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
940 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
941 __le16 statistic_index
;
946 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion
);
948 /* Get VEB Parameters (direct 0x0232)
949 * uses i40e_aqc_switch_seid for the descriptor
951 struct i40e_aqc_get_veb_parameters_completion
{
954 __le16 veb_flags
; /* only the first/last flags from 0x0230 is valid */
955 __le16 statistic_index
;
961 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion
);
963 /* Delete Element (direct 0x0243)
964 * uses the generic i40e_aqc_switch_seid
967 /* Add MAC-VLAN (indirect 0x0250) */
969 /* used for the command for most vlan commands */
970 struct i40e_aqc_macvlan
{
971 __le16 num_addresses
;
973 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
974 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
975 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
976 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
981 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan
);
983 /* indirect data for command and response */
984 struct i40e_aqc_add_macvlan_element_data
{
988 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
989 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
990 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
991 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
992 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
994 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
995 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
996 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
997 /* response section */
999 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1000 #define I40E_AQC_MM_HASH_MATCH 0x02
1001 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1005 struct i40e_aqc_add_remove_macvlan_completion
{
1006 __le16 perfect_mac_used
;
1007 __le16 perfect_mac_free
;
1008 __le16 unicast_hash_free
;
1009 __le16 multicast_hash_free
;
1014 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion
);
1016 /* Remove MAC-VLAN (indirect 0x0251)
1017 * uses i40e_aqc_macvlan for the descriptor
1018 * data points to an array of num_addresses of elements
1021 struct i40e_aqc_remove_macvlan_element_data
{
1025 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1026 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1027 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1028 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1032 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1033 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1034 u8 reply_reserved
[3];
1037 /* Add VLAN (indirect 0x0252)
1038 * Remove VLAN (indirect 0x0253)
1039 * use the generic i40e_aqc_macvlan for the command
1041 struct i40e_aqc_add_remove_vlan_element_data
{
1044 /* flags for add VLAN */
1045 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1046 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1047 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1048 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1049 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1050 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1051 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1052 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1053 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1054 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1055 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1056 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1057 /* flags for remove VLAN */
1058 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1061 /* flags for add VLAN */
1062 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1063 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1064 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1065 /* flags for remove VLAN */
1066 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1067 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1071 struct i40e_aqc_add_remove_vlan_completion
{
1079 /* Set VSI Promiscuous Modes (direct 0x0254) */
1080 struct i40e_aqc_set_vsi_promiscuous_modes
{
1081 __le16 promiscuous_flags
;
1083 /* flags used for both fields above */
1084 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1085 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1086 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1087 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1088 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1090 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1092 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1093 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1097 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes
);
1099 /* Add S/E-tag command (direct 0x0255)
1100 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1102 struct i40e_aqc_add_tag
{
1104 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1106 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1107 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1108 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1110 __le16 queue_number
;
1114 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag
);
1116 struct i40e_aqc_add_remove_tag_completion
{
1122 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion
);
1124 /* Remove S/E-tag command (direct 0x0256)
1125 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1127 struct i40e_aqc_remove_tag
{
1129 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1130 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1131 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1136 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag
);
1138 /* Add multicast E-Tag (direct 0x0257)
1139 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1140 * and no external data
1142 struct i40e_aqc_add_remove_mcast_etag
{
1145 u8 num_unicast_etags
;
1147 __le32 addr_high
; /* address of array of 2-byte s-tags */
1151 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag
);
1153 struct i40e_aqc_add_remove_mcast_etag_completion
{
1155 __le16 mcast_etags_used
;
1156 __le16 mcast_etags_free
;
1162 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion
);
1164 /* Update S/E-Tag (direct 0x0259) */
1165 struct i40e_aqc_update_tag
{
1167 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1168 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1169 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1175 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag
);
1177 struct i40e_aqc_update_tag_completion
{
1183 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion
);
1185 /* Add Control Packet filter (direct 0x025A)
1186 * Remove Control Packet filter (direct 0x025B)
1187 * uses the i40e_aqc_add_oveb_cloud,
1188 * and the generic direct completion structure
1190 struct i40e_aqc_add_remove_control_packet_filter
{
1194 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1195 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1196 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1197 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1198 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1200 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1201 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1202 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1207 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter
);
1209 struct i40e_aqc_add_remove_control_packet_filter_completion
{
1210 __le16 mac_etype_used
;
1212 __le16 mac_etype_free
;
1217 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion
);
1219 /* Add Cloud filters (indirect 0x025C)
1220 * Remove Cloud filters (indirect 0x025D)
1221 * uses the i40e_aqc_add_remove_cloud_filters,
1222 * and the generic indirect completion structure
1224 struct i40e_aqc_add_remove_cloud_filters
{
1228 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1229 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1230 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1236 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters
);
1238 struct i40e_aqc_add_remove_cloud_filters_element_data
{
1252 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1253 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1254 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1255 /* 0x0000 reserved */
1256 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1257 /* 0x0002 reserved */
1258 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1259 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1260 /* 0x0005 reserved */
1261 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1262 /* 0x0007 reserved */
1263 /* 0x0008 reserved */
1264 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1265 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1266 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1267 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1269 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1270 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1271 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1272 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1273 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1275 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1276 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1277 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1278 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1279 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1280 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1281 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1282 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1284 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1285 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1286 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1290 __le16 queue_number
;
1291 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1292 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1293 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1295 /* response section */
1296 u8 allocation_result
;
1297 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1298 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1299 u8 response_reserved
[7];
1302 struct i40e_aqc_remove_cloud_filters_completion
{
1303 __le16 perfect_ovlan_used
;
1304 __le16 perfect_ovlan_free
;
1311 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion
);
1313 /* Add Mirror Rule (indirect or direct 0x0260)
1314 * Delete Mirror Rule (indirect or direct 0x0261)
1315 * note: some rule types (4,5) do not use an external buffer.
1316 * take care to set the flags correctly.
1318 struct i40e_aqc_add_delete_mirror_rule
{
1321 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1322 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1323 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1324 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1325 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1326 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1327 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1328 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1330 __le16 destination
; /* VSI for add, rule id for delete */
1331 __le32 addr_high
; /* address of array of 2-byte VSI or VLAN ids */
1335 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule
);
1337 struct i40e_aqc_add_delete_mirror_rule_completion
{
1339 __le16 rule_id
; /* only used on add */
1340 __le16 mirror_rules_used
;
1341 __le16 mirror_rules_free
;
1346 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion
);
1350 /* PFC Ignore (direct 0x0301)
1351 * the command and response use the same descriptor structure
1353 struct i40e_aqc_pfc_ignore
{
1355 u8 command_flags
; /* unused on response */
1356 #define I40E_AQC_PFC_IGNORE_SET 0x80
1357 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1361 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore
);
1363 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1364 * with no parameters
1367 /* TX scheduler 0x04xx */
1369 /* Almost all the indirect commands use
1370 * this generic struct to pass the SEID in param0
1372 struct i40e_aqc_tx_sched_ind
{
1379 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind
);
1381 /* Several commands respond with a set of queue set handles */
1382 struct i40e_aqc_qs_handles_resp
{
1383 __le16 qs_handles
[8];
1386 /* Configure VSI BW limits (direct 0x0400) */
1387 struct i40e_aqc_configure_vsi_bw_limit
{
1392 u8 max_credit
; /* 0-3, limit = 2^max */
1396 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit
);
1398 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1399 * responds with i40e_aqc_qs_handles_resp
1401 struct i40e_aqc_configure_vsi_ets_sla_bw_data
{
1404 __le16 tc_bw_credits
[8]; /* FW writesback QS handles here */
1406 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1407 __le16 tc_bw_max
[2];
1411 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data
);
1413 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1414 * responds with i40e_aqc_qs_handles_resp
1416 struct i40e_aqc_configure_vsi_tc_bw_data
{
1419 u8 tc_bw_credits
[8];
1421 __le16 qs_handles
[8];
1424 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data
);
1426 /* Query vsi bw configuration (indirect 0x0408) */
1427 struct i40e_aqc_query_vsi_bw_config_resp
{
1429 u8 tc_suspended_bits
;
1431 __le16 qs_handles
[8];
1433 __le16 port_bw_limit
;
1435 u8 max_bw
; /* 0-3, limit = 2^max */
1439 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp
);
1441 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1442 struct i40e_aqc_query_vsi_ets_sla_config_resp
{
1445 u8 share_credits
[8];
1448 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1449 __le16 tc_bw_max
[2];
1452 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp
);
1454 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1455 struct i40e_aqc_configure_switching_comp_bw_limit
{
1460 u8 max_bw
; /* 0-3, limit = 2^max */
1464 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit
);
1466 /* Enable Physical Port ETS (indirect 0x0413)
1467 * Modify Physical Port ETS (indirect 0x0414)
1468 * Disable Physical Port ETS (indirect 0x0415)
1470 struct i40e_aqc_configure_switching_comp_ets_data
{
1474 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1475 u8 tc_strict_priority_flags
;
1477 u8 tc_bw_share_credits
[8];
1481 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data
);
1483 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1484 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data
{
1487 __le16 tc_bw_credit
[8];
1489 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1490 __le16 tc_bw_max
[2];
1494 I40E_CHECK_STRUCT_LEN(0x40,
1495 i40e_aqc_configure_switching_comp_ets_bw_limit_data
);
1497 /* Configure Switching Component Bandwidth Allocation per Tc
1500 struct i40e_aqc_configure_switching_comp_bw_config_data
{
1503 u8 absolute_credits
; /* bool */
1504 u8 tc_bw_share_credits
[8];
1508 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data
);
1510 /* Query Switching Component Configuration (indirect 0x0418) */
1511 struct i40e_aqc_query_switching_comp_ets_config_resp
{
1514 __le16 port_bw_limit
;
1516 u8 tc_bw_max
; /* 0-3, limit = 2^max */
1520 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp
);
1522 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1523 struct i40e_aqc_query_port_ets_config_resp
{
1527 u8 tc_strict_priority_bits
;
1529 u8 tc_bw_share_credits
[8];
1530 __le16 tc_bw_limits
[8];
1532 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1533 __le16 tc_bw_max
[2];
1537 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp
);
1539 /* Query Switching Component Bandwidth Allocation per Traffic Type
1542 struct i40e_aqc_query_switching_comp_bw_config_resp
{
1545 u8 absolute_credits_enable
; /* bool */
1546 u8 tc_bw_share_credits
[8];
1547 __le16 tc_bw_limits
[8];
1549 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1550 __le16 tc_bw_max
[2];
1553 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp
);
1555 /* Suspend/resume port TX traffic
1556 * (direct 0x041B and 0x041C) uses the generic SEID struct
1559 /* Configure partition BW
1562 struct i40e_aqc_configure_partition_bw_data
{
1563 __le16 pf_valid_bits
;
1564 u8 min_bw
[16]; /* guaranteed bandwidth */
1565 u8 max_bw
[16]; /* bandwidth limit */
1568 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data
);
1570 /* Get and set the active HMC resource profile and status.
1571 * (direct 0x0500) and (direct 0x0501)
1573 struct i40e_aq_get_set_hmc_resource_profile
{
1579 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile
);
1581 enum i40e_aq_hmc_profile
{
1582 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1583 I40E_HMC_PROFILE_DEFAULT
= 1,
1584 I40E_HMC_PROFILE_FAVOR_VF
= 2,
1585 I40E_HMC_PROFILE_EQUAL
= 3,
1588 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1589 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1591 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1593 /* set in param0 for get phy abilities to report qualified modules */
1594 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1595 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1597 enum i40e_aq_phy_type
{
1598 I40E_PHY_TYPE_SGMII
= 0x0,
1599 I40E_PHY_TYPE_1000BASE_KX
= 0x1,
1600 I40E_PHY_TYPE_10GBASE_KX4
= 0x2,
1601 I40E_PHY_TYPE_10GBASE_KR
= 0x3,
1602 I40E_PHY_TYPE_40GBASE_KR4
= 0x4,
1603 I40E_PHY_TYPE_XAUI
= 0x5,
1604 I40E_PHY_TYPE_XFI
= 0x6,
1605 I40E_PHY_TYPE_SFI
= 0x7,
1606 I40E_PHY_TYPE_XLAUI
= 0x8,
1607 I40E_PHY_TYPE_XLPPI
= 0x9,
1608 I40E_PHY_TYPE_40GBASE_CR4_CU
= 0xA,
1609 I40E_PHY_TYPE_10GBASE_CR1_CU
= 0xB,
1610 I40E_PHY_TYPE_10GBASE_AOC
= 0xC,
1611 I40E_PHY_TYPE_40GBASE_AOC
= 0xD,
1612 I40E_PHY_TYPE_100BASE_TX
= 0x11,
1613 I40E_PHY_TYPE_1000BASE_T
= 0x12,
1614 I40E_PHY_TYPE_10GBASE_T
= 0x13,
1615 I40E_PHY_TYPE_10GBASE_SR
= 0x14,
1616 I40E_PHY_TYPE_10GBASE_LR
= 0x15,
1617 I40E_PHY_TYPE_10GBASE_SFPP_CU
= 0x16,
1618 I40E_PHY_TYPE_10GBASE_CR1
= 0x17,
1619 I40E_PHY_TYPE_40GBASE_CR4
= 0x18,
1620 I40E_PHY_TYPE_40GBASE_SR4
= 0x19,
1621 I40E_PHY_TYPE_40GBASE_LR4
= 0x1A,
1622 I40E_PHY_TYPE_1000BASE_SX
= 0x1B,
1623 I40E_PHY_TYPE_1000BASE_LX
= 0x1C,
1624 I40E_PHY_TYPE_1000BASE_T_OPTICAL
= 0x1D,
1625 I40E_PHY_TYPE_20GBASE_KR2
= 0x1E,
1629 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1630 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1631 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1632 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1633 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1635 enum i40e_aq_link_speed
{
1636 I40E_LINK_SPEED_UNKNOWN
= 0,
1637 I40E_LINK_SPEED_100MB
= (1 << I40E_LINK_SPEED_100MB_SHIFT
),
1638 I40E_LINK_SPEED_1GB
= (1 << I40E_LINK_SPEED_1000MB_SHIFT
),
1639 I40E_LINK_SPEED_10GB
= (1 << I40E_LINK_SPEED_10GB_SHIFT
),
1640 I40E_LINK_SPEED_40GB
= (1 << I40E_LINK_SPEED_40GB_SHIFT
),
1641 I40E_LINK_SPEED_20GB
= (1 << I40E_LINK_SPEED_20GB_SHIFT
)
1644 struct i40e_aqc_module_desc
{
1652 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc
);
1654 struct i40e_aq_get_phy_abilities_resp
{
1655 __le32 phy_type
; /* bitmap using the above enum for offsets */
1656 u8 link_speed
; /* bitmap using the above enum bit patterns */
1658 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1659 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1660 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1661 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1662 #define I40E_AQ_PHY_AN_ENABLED 0x10
1663 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1664 __le16 eee_capability
;
1665 #define I40E_AQ_EEE_100BASE_TX 0x0002
1666 #define I40E_AQ_EEE_1000BASE_T 0x0004
1667 #define I40E_AQ_EEE_10GBASE_T 0x0008
1668 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1669 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1670 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1673 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1677 u8 qualified_module_count
;
1678 #define I40E_AQ_PHY_MAX_QMS 16
1679 struct i40e_aqc_module_desc qualified_module
[I40E_AQ_PHY_MAX_QMS
];
1682 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp
);
1684 /* Set PHY Config (direct 0x0601) */
1685 struct i40e_aq_set_phy_config
{ /* same bits as above in all */
1689 /* bits 0-2 use the values from get_phy_abilities_resp */
1690 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1691 #define I40E_AQ_PHY_ENABLE_AN 0x10
1692 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1693 __le16 eee_capability
;
1699 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config
);
1701 /* Set MAC Config command data structure (direct 0x0603) */
1702 struct i40e_aq_set_mac_config
{
1703 __le16 max_frame_size
;
1705 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1706 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1707 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1708 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1709 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1710 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1711 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1712 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1713 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1714 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1715 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1716 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1717 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1718 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1719 u8 tx_timer_priority
; /* bitmap */
1720 __le16 tx_timer_value
;
1721 __le16 fc_refresh_threshold
;
1725 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config
);
1727 /* Restart Auto-Negotiation (direct 0x605) */
1728 struct i40e_aqc_set_link_restart_an
{
1730 #define I40E_AQ_PHY_RESTART_AN 0x02
1731 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1735 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an
);
1737 /* Get Link Status cmd & response data structure (direct 0x0607) */
1738 struct i40e_aqc_get_link_status
{
1739 __le16 command_flags
; /* only field set on command */
1740 #define I40E_AQ_LSE_MASK 0x3
1741 #define I40E_AQ_LSE_NOP 0x0
1742 #define I40E_AQ_LSE_DISABLE 0x2
1743 #define I40E_AQ_LSE_ENABLE 0x3
1744 /* only response uses this flag */
1745 #define I40E_AQ_LSE_IS_ENABLED 0x1
1746 u8 phy_type
; /* i40e_aq_phy_type */
1747 u8 link_speed
; /* i40e_aq_link_speed */
1749 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1750 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1751 #define I40E_AQ_LINK_FAULT 0x02
1752 #define I40E_AQ_LINK_FAULT_TX 0x04
1753 #define I40E_AQ_LINK_FAULT_RX 0x08
1754 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1755 #define I40E_AQ_LINK_UP_PORT 0x20
1756 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1757 #define I40E_AQ_SIGNAL_DETECT 0x80
1759 #define I40E_AQ_AN_COMPLETED 0x01
1760 #define I40E_AQ_LP_AN_ABILITY 0x02
1761 #define I40E_AQ_PD_FAULT 0x04
1762 #define I40E_AQ_FEC_EN 0x08
1763 #define I40E_AQ_PHY_LOW_POWER 0x10
1764 #define I40E_AQ_LINK_PAUSE_TX 0x20
1765 #define I40E_AQ_LINK_PAUSE_RX 0x40
1766 #define I40E_AQ_QUALIFIED_MODULE 0x80
1768 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1769 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1770 #define I40E_AQ_LINK_TX_SHIFT 0x02
1771 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1772 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1773 #define I40E_AQ_LINK_TX_DRAINED 0x01
1774 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1775 #define I40E_AQ_LINK_FORCED_40G 0x10
1776 u8 loopback
; /* use defines from i40e_aqc_set_lb_mode */
1777 __le16 max_frame_size
;
1779 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1780 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1781 u8 external_power_ability
;
1782 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1783 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1784 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1785 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1789 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status
);
1791 /* Set event mask command (direct 0x613) */
1792 struct i40e_aqc_set_phy_int_mask
{
1795 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1796 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1797 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1798 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1799 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1800 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1801 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1802 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1803 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1807 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask
);
1809 /* Get Local AN advt register (direct 0x0614)
1810 * Set Local AN advt register (direct 0x0615)
1811 * Get Link Partner AN advt register (direct 0x0616)
1813 struct i40e_aqc_an_advt_reg
{
1814 __le32 local_an_reg0
;
1815 __le16 local_an_reg1
;
1819 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg
);
1821 /* Set Loopback mode (0x0618) */
1822 struct i40e_aqc_set_lb_mode
{
1824 #define I40E_AQ_LB_PHY_LOCAL 0x01
1825 #define I40E_AQ_LB_PHY_REMOTE 0x02
1826 #define I40E_AQ_LB_MAC_LOCAL 0x04
1830 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode
);
1832 /* Set PHY Debug command (0x0622) */
1833 struct i40e_aqc_set_phy_debug
{
1835 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1836 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1837 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1838 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1839 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1840 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1841 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1842 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1846 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug
);
1848 enum i40e_aq_phy_reg_type
{
1849 I40E_AQC_PHY_REG_INTERNAL
= 0x1,
1850 I40E_AQC_PHY_REG_EXERNAL_BASET
= 0x2,
1851 I40E_AQC_PHY_REG_EXERNAL_MODULE
= 0x3
1854 /* Run PHY Activity (0x0626) */
1855 struct i40e_aqc_run_phy_activity
{
1864 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity
);
1866 /* NVM Read command (indirect 0x0701)
1867 * NVM Erase commands (direct 0x0702)
1868 * NVM Update commands (indirect 0x0703)
1870 struct i40e_aqc_nvm_update
{
1872 #define I40E_AQ_NVM_LAST_CMD 0x01
1873 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1881 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update
);
1883 /* NVM Config Read (indirect 0x0704) */
1884 struct i40e_aqc_nvm_config_read
{
1886 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1887 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1888 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1889 __le16 element_count
;
1890 __le16 element_id
; /* Feature/field ID */
1891 __le16 element_id_msw
; /* MSWord of field ID */
1892 __le32 address_high
;
1896 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read
);
1898 /* NVM Config Write (indirect 0x0705) */
1899 struct i40e_aqc_nvm_config_write
{
1901 __le16 element_count
;
1903 __le32 address_high
;
1907 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write
);
1909 /* Used for 0x0704 as well as for 0x0705 commands */
1910 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1911 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1912 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1913 #define I40E_AQ_ANVM_FEATURE 0
1914 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1915 struct i40e_aqc_nvm_config_data_feature
{
1917 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1918 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1919 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1920 __le16 feature_options
;
1921 __le16 feature_selection
;
1924 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature
);
1926 struct i40e_aqc_nvm_config_data_immediate_field
{
1929 __le16 field_options
;
1933 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field
);
1935 /* OEM Post Update (indirect 0x0720)
1936 * no command data struct used
1938 struct i40e_aqc_nvm_oem_post_update
{
1939 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1944 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update
);
1946 struct i40e_aqc_nvm_oem_post_update_buffer
{
1953 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer
);
1955 /* Send to PF command (indirect 0x0801) id is only used by PF
1956 * Send to VF command (indirect 0x0802) id is only used by PF
1957 * Send to Peer PF command (indirect 0x0803)
1959 struct i40e_aqc_pf_vf_message
{
1966 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message
);
1968 /* Alternate structure */
1970 /* Direct write (direct 0x0900)
1971 * Direct read (direct 0x0902)
1973 struct i40e_aqc_alternate_write
{
1980 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write
);
1982 /* Indirect write (indirect 0x0901)
1983 * Indirect read (indirect 0x0903)
1986 struct i40e_aqc_alternate_ind_write
{
1993 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write
);
1995 /* Done alternate write (direct 0x0904)
1998 struct i40e_aqc_alternate_write_done
{
2000 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2001 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2002 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2003 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2007 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done
);
2009 /* Set OEM mode (direct 0x0905) */
2010 struct i40e_aqc_alternate_set_mode
{
2012 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2013 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2017 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode
);
2019 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2021 /* async events 0x10xx */
2023 /* Lan Queue Overflow Event (direct, 0x1001) */
2024 struct i40e_aqc_lan_overflow
{
2025 __le32 prtdcb_rupto
;
2030 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow
);
2032 /* Get LLDP MIB (indirect 0x0A00) */
2033 struct i40e_aqc_lldp_get_mib
{
2036 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2037 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2038 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2039 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2040 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2041 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2042 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2043 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2044 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2045 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2046 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2054 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib
);
2056 /* Configure LLDP MIB Change Event (direct 0x0A01)
2057 * also used for the event (with type in the command field)
2059 struct i40e_aqc_lldp_update_mib
{
2061 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2062 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2068 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib
);
2070 /* Add LLDP TLV (indirect 0x0A02)
2071 * Delete LLDP TLV (indirect 0x0A04)
2073 struct i40e_aqc_lldp_add_tlv
{
2074 u8 type
; /* only nearest bridge and non-TPMR from 0x0A00 */
2082 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv
);
2084 /* Update LLDP TLV (indirect 0x0A03) */
2085 struct i40e_aqc_lldp_update_tlv
{
2086 u8 type
; /* only nearest bridge and non-TPMR from 0x0A00 */
2095 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv
);
2097 /* Stop LLDP (direct 0x0A05) */
2098 struct i40e_aqc_lldp_stop
{
2100 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2101 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2105 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop
);
2107 /* Start LLDP (direct 0x0A06) */
2109 struct i40e_aqc_lldp_start
{
2111 #define I40E_AQ_LLDP_AGENT_START 0x1
2115 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start
);
2117 /* Get CEE DCBX Oper Config (0x0A07)
2118 * uses the generic descriptor struct
2119 * returns below as indirect response
2122 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2123 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2124 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2125 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2126 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2127 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2129 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2130 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2131 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2132 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2133 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2134 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2135 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2136 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2137 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2138 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2139 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2140 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2142 /* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2143 * word boundary layout issues, which the Linux compilers silently deal
2144 * with by adding padding, making the actual struct larger than designed.
2145 * However, the FW compiler for the NIC is less lenient and complains
2146 * about the struct. Hence, the struct defined here has an extra byte in
2147 * fields reserved3 and reserved4 to directly acknowledge that padding,
2148 * and the new length is used in the length check macro.
2150 struct i40e_aqc_get_cee_dcb_cfg_v1_resp
{
2158 __le16 oper_app_prio
;
2163 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp
);
2165 struct i40e_aqc_get_cee_dcb_cfg_resp
{
2170 __le16 oper_app_prio
;
2171 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2172 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2173 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2174 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2175 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2176 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2177 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2179 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2180 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2181 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2182 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2183 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2184 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2188 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp
);
2190 /* Set Local LLDP MIB (indirect 0x0A08)
2191 * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2193 struct i40e_aqc_lldp_set_local_mib
{
2194 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2195 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2196 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2197 SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2198 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2199 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
2200 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
2201 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2202 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2207 __le32 address_high
;
2211 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib
);
2213 /* Stop/Start LLDP Agent (direct 0x0A09)
2214 * Used for stopping/starting specific LLDP agent. e.g. DCBx
2216 struct i40e_aqc_lldp_stop_start_specific_agent
{
2217 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2218 #define I40E_AQC_START_SPECIFIC_AGENT_MASK \
2219 (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT)
2224 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent
);
2226 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2227 struct i40e_aqc_add_udp_tunnel
{
2231 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2232 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2233 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2234 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2238 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel
);
2240 struct i40e_aqc_add_udp_tunnel_completion
{
2242 u8 filter_entry_index
;
2244 #define I40E_AQC_SINGLE_PF 0x0
2245 #define I40E_AQC_MULTIPLE_PFS 0x1
2250 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion
);
2252 /* remove UDP Tunnel command (0x0B01) */
2253 struct i40e_aqc_remove_udp_tunnel
{
2255 u8 index
; /* 0 to 15 */
2259 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel
);
2261 struct i40e_aqc_del_udp_tunnel_completion
{
2263 u8 index
; /* 0 to 15 */
2265 u8 total_filters_used
;
2269 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion
);
2271 struct i40e_aqc_get_set_rss_key
{
2272 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2273 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2274 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2275 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2282 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key
);
2284 struct i40e_aqc_get_set_rss_key_data
{
2285 u8 standard_rss_key
[0x28];
2286 u8 extended_hash_key
[0xc];
2289 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data
);
2291 struct i40e_aqc_get_set_rss_lut
{
2292 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2293 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2294 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2295 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2297 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2298 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2299 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2301 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2302 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2309 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut
);
2311 /* tunnel key structure 0x0B10 */
2313 struct i40e_aqc_tunnel_key_structure
{
2316 u8 key1_len
; /* 0 to 15 */
2317 u8 key2_len
; /* 0 to 15 */
2319 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2320 /* response flags */
2321 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2322 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2323 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2324 u8 network_key_index
;
2325 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2326 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2327 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2328 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2332 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure
);
2334 /* OEM mode commands (direct 0xFE0x) */
2335 struct i40e_aqc_oem_param_change
{
2337 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2338 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2339 #define I40E_AQ_OEM_PARAM_MAC 2
2340 __le32 param_value1
;
2341 __le16 param_value2
;
2345 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change
);
2347 struct i40e_aqc_oem_state_change
{
2349 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2350 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2354 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change
);
2356 /* Initialize OCSD (0xFE02, direct) */
2357 struct i40e_aqc_opc_oem_ocsd_initialize
{
2360 __le32 ocsd_memory_block_addr_high
;
2361 __le32 ocsd_memory_block_addr_low
;
2362 __le32 requested_update_interval
;
2365 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize
);
2367 /* Initialize OCBB (0xFE03, direct) */
2368 struct i40e_aqc_opc_oem_ocbb_initialize
{
2371 __le32 ocbb_memory_block_addr_high
;
2372 __le32 ocbb_memory_block_addr_low
;
2376 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize
);
2378 /* debug commands */
2380 /* get device id (0xFF00) uses the generic structure */
2382 /* set test more (0xFF01, internal) */
2384 struct i40e_acq_set_test_mode
{
2386 #define I40E_AQ_TEST_PARTIAL 0
2387 #define I40E_AQ_TEST_FULL 1
2388 #define I40E_AQ_TEST_NVM 2
2391 #define I40E_AQ_TEST_OPEN 0
2392 #define I40E_AQ_TEST_CLOSE 1
2393 #define I40E_AQ_TEST_INC 2
2395 __le32 address_high
;
2399 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode
);
2401 /* Debug Read Register command (0xFF03)
2402 * Debug Write Register command (0xFF04)
2404 struct i40e_aqc_debug_reg_read_write
{
2411 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write
);
2413 /* Scatter/gather Reg Read (indirect 0xFF05)
2414 * Scatter/gather Reg Write (indirect 0xFF06)
2417 /* i40e_aq_desc is used for the command */
2418 struct i40e_aqc_debug_reg_sg_element_data
{
2423 /* Debug Modify register (direct 0xFF07) */
2424 struct i40e_aqc_debug_modify_reg
{
2431 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg
);
2433 /* dump internal data (0xFF08, indirect) */
2435 #define I40E_AQ_CLUSTER_ID_AUX 0
2436 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2437 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2438 #define I40E_AQ_CLUSTER_ID_HMC 3
2439 #define I40E_AQ_CLUSTER_ID_MAC0 4
2440 #define I40E_AQ_CLUSTER_ID_MAC1 5
2441 #define I40E_AQ_CLUSTER_ID_MAC2 6
2442 #define I40E_AQ_CLUSTER_ID_MAC3 7
2443 #define I40E_AQ_CLUSTER_ID_DCB 8
2444 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2445 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2446 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2448 struct i40e_aqc_debug_dump_internals
{
2453 __le32 address_high
;
2457 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals
);
2459 struct i40e_aqc_debug_modify_internals
{
2461 u8 cluster_specific_params
[7];
2462 __le32 address_high
;
2466 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals
);
2468 #endif /* _I40E_ADMINQ_CMD_H_ */