drivers/net/ethernet/intel/i40e/i40e_txrx.h

   1 /*******************************************************************************
   2  *
   3  * Intel Ethernet Controller XL710 Family Linux Driver
   4  * Copyright(c) 2013 - 2014 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef _I40E_TXRX_H_
  28 #define _I40E_TXRX_H_
  29
  30 /* Interrupt Throttling and Rate Limiting Goodies */
  31
  32 #define I40E_MAX_ITR               0x0FF0  /* reg uses 2 usec resolution */
  33 #define I40E_MIN_ITR               0x0001  /* reg uses 2 usec resolution */
  34 #define I40E_ITR_100K              0x0005
  35 #define I40E_ITR_20K               0x0019
  36 #define I40E_ITR_8K                0x003E
  37 #define I40E_ITR_4K                0x007A
  38 #define I40E_ITR_RX_DEF            I40E_ITR_8K
  39 #define I40E_ITR_TX_DEF            I40E_ITR_4K
  40 #define I40E_ITR_DYNAMIC           0x8000  /* use top bit as a flag */
  41 #define I40E_MIN_INT_RATE          250     /* ~= 1000000 / (I40E_MAX_ITR * 2) */
  42 #define I40E_MAX_INT_RATE          500000  /* == 1000000 / (I40E_MIN_ITR * 2) */
  43 #define I40E_DEFAULT_IRQ_WORK      256
  44 #define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1)
  45 #define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC))
  46 #define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1)
  47
  48 #define I40E_QUEUE_END_OF_LIST 0x7FF
  49
  50 /* this enum matches hardware bits and is meant to be used by DYN_CTLN
  51  * registers and QINT registers or more generally anywhere in the manual
  52  * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
  53  * register but instead is a special value meaning "don't update" ITR0/1/2.
  54  */
  55 enum i40e_dyn_idx_t {
  56         I40E_IDX_ITR0 = 0,
  57         I40E_IDX_ITR1 = 1,
  58         I40E_IDX_ITR2 = 2,
  59         I40E_ITR_NONE = 3       /* ITR_NONE must not be used as an index */
  60 };
  61
  62 /* these are indexes into ITRN registers */
  63 #define I40E_RX_ITR    I40E_IDX_ITR0
  64 #define I40E_TX_ITR    I40E_IDX_ITR1
  65 #define I40E_PE_ITR    I40E_IDX_ITR2
  66
  67 /* Supported RSS offloads */
  68 #define I40E_DEFAULT_RSS_HENA ( \
  69         BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
  70         BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
  71         BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
  72         BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
  73         BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
  74         BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
  75         BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
  76         BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
  77         BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
  78         BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
  79         BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
  80
  81 #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \
  82         BIT(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
  83         BIT(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
  84         BIT(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
  85         BIT(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
  86         BIT(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
  87         BIT(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
  88
  89 #define i40e_pf_get_default_rss_hena(pf) \
  90         (((pf)->flags & I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE) ? \
  91           I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA)
  92
  93 /* Supported Rx Buffer Sizes */
  94 #define I40E_RXBUFFER_512   512    /* Used for packet split */
  95 #define I40E_RXBUFFER_2048  2048
  96 #define I40E_RXBUFFER_3072  3072   /* For FCoE MTU of 2158 */
  97 #define I40E_RXBUFFER_4096  4096
  98 #define I40E_RXBUFFER_8192  8192
  99 #define I40E_MAX_RXBUFFER   9728  /* largest size for single descriptor */
 100
 101 /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
 102  * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
 103  * this adds up to 512 bytes of extra data meaning the smallest allocation
 104  * we could have is 1K.
 105  * i.e. RXBUFFER_512 --> size-1024 slab
 106  */
 107 #define I40E_RX_HDR_SIZE  I40E_RXBUFFER_512
 108
 109 /* How many Rx Buffers do we bundle into one write to the hardware ? */
 110 #define I40E_RX_BUFFER_WRITE    16      /* Must be power of 2 */
 111 #define I40E_RX_INCREMENT(r, i) \
 112         do {                                    \
 113                 (i)++;                          \
 114                 if ((i) == (r)->count)          \
 115                         i = 0;                  \
 116                 r->next_to_clean = i;           \
 117         } while (0)
 118
 119 #define I40E_RX_NEXT_DESC(r, i, n)              \
 120         do {                                    \
 121                 (i)++;                          \
 122                 if ((i) == (r)->count)          \
 123                         i = 0;                  \
 124                 (n) = I40E_RX_DESC((r), (i));   \
 125         } while (0)
 126
 127 #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n)             \
 128         do {                                            \
 129                 I40E_RX_NEXT_DESC((r), (i), (n));       \
 130                 prefetch((n));                          \
 131         } while (0)
 132
 133 #define i40e_rx_desc i40e_32byte_rx_desc
 134
 135 #define I40E_MAX_BUFFER_TXD     8
 136 #define I40E_MIN_TX_LEN         17
 137 #define I40E_MAX_DATA_PER_TXD   8192
 138
 139 /* Tx Descriptors needed, worst case */
 140 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
 141 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
 142 #define I40E_MIN_DESC_PENDING   4
 143
 144 #define I40E_TX_FLAGS_CSUM              BIT(0)
 145 #define I40E_TX_FLAGS_HW_VLAN           BIT(1)
 146 #define I40E_TX_FLAGS_SW_VLAN           BIT(2)
 147 #define I40E_TX_FLAGS_TSO               BIT(3)
 148 #define I40E_TX_FLAGS_IPV4              BIT(4)
 149 #define I40E_TX_FLAGS_IPV6              BIT(5)
 150 #define I40E_TX_FLAGS_FCCRC             BIT(6)
 151 #define I40E_TX_FLAGS_FSO               BIT(7)
 152 #define I40E_TX_FLAGS_TSYN              BIT(8)
 153 #define I40E_TX_FLAGS_FD_SB             BIT(9)
 154 #define I40E_TX_FLAGS_VXLAN_TUNNEL      BIT(10)
 155 #define I40E_TX_FLAGS_VLAN_MASK         0xffff0000
 156 #define I40E_TX_FLAGS_VLAN_PRIO_MASK    0xe0000000
 157 #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT   29
 158 #define I40E_TX_FLAGS_VLAN_SHIFT        16
 159
 160 struct i40e_tx_buffer {
 161         struct i40e_tx_desc *next_to_watch;
 162         union {
 163                 struct sk_buff *skb;
 164                 void *raw_buf;
 165         };
 166         unsigned int bytecount;
 167         unsigned short gso_segs;
 168         DEFINE_DMA_UNMAP_ADDR(dma);
 169         DEFINE_DMA_UNMAP_LEN(len);
 170         u32 tx_flags;
 171 };
 172
 173 struct i40e_rx_buffer {
 174         struct sk_buff *skb;
 175         void *hdr_buf;
 176         dma_addr_t dma;
 177         struct page *page;
 178         dma_addr_t page_dma;
 179         unsigned int page_offset;
 180 };
 181
 182 struct i40e_queue_stats {
 183         u64 packets;
 184         u64 bytes;
 185 };
 186
 187 struct i40e_tx_queue_stats {
 188         u64 restart_queue;
 189         u64 tx_busy;
 190         u64 tx_done_old;
 191 };
 192
 193 struct i40e_rx_queue_stats {
 194         u64 non_eop_descs;
 195         u64 alloc_page_failed;
 196         u64 alloc_buff_failed;
 197 };
 198
 199 enum i40e_ring_state_t {
 200         __I40E_TX_FDIR_INIT_DONE,
 201         __I40E_TX_XPS_INIT_DONE,
 202         __I40E_TX_DETECT_HANG,
 203         __I40E_HANG_CHECK_ARMED,
 204         __I40E_RX_PS_ENABLED,
 205         __I40E_RX_16BYTE_DESC_ENABLED,
 206 };
 207
 208 #define ring_is_ps_enabled(ring) \
 209         test_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
 210 #define set_ring_ps_enabled(ring) \
 211         set_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
 212 #define clear_ring_ps_enabled(ring) \
 213         clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state)
 214 #define check_for_tx_hang(ring) \
 215         test_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
 216 #define set_check_for_tx_hang(ring) \
 217         set_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
 218 #define clear_check_for_tx_hang(ring) \
 219         clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state)
 220 #define ring_is_16byte_desc_enabled(ring) \
 221         test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
 222 #define set_ring_16byte_desc_enabled(ring) \
 223         set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
 224 #define clear_ring_16byte_desc_enabled(ring) \
 225         clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state)
 226
 227 /* struct that defines a descriptor ring, associated with a VSI */
 228 struct i40e_ring {
 229         struct i40e_ring *next;         /* pointer to next ring in q_vector */
 230         void *desc;                     /* Descriptor ring memory */
 231         struct device *dev;             /* Used for DMA mapping */
 232         struct net_device *netdev;      /* netdev ring maps to */
 233         union {
 234                 struct i40e_tx_buffer *tx_bi;
 235                 struct i40e_rx_buffer *rx_bi;
 236         };
 237         unsigned long state;
 238         u16 queue_index;                /* Queue number of ring */
 239         u8 dcb_tc;                      /* Traffic class of ring */
 240         u8 __iomem *tail;
 241
 242         u16 count;                      /* Number of descriptors */
 243         u16 reg_idx;                    /* HW register index of the ring */
 244         u16 rx_hdr_len;
 245         u16 rx_buf_len;
 246         u8  dtype;
 247 #define I40E_RX_DTYPE_NO_SPLIT      0
 248 #define I40E_RX_DTYPE_HEADER_SPLIT  1
 249 #define I40E_RX_DTYPE_SPLIT_ALWAYS  2
 250         u8  hsplit;
 251 #define I40E_RX_SPLIT_L2      0x1
 252 #define I40E_RX_SPLIT_IP      0x2
 253 #define I40E_RX_SPLIT_TCP_UDP 0x4
 254 #define I40E_RX_SPLIT_SCTP    0x8
 255
 256         /* used in interrupt processing */
 257         u16 next_to_use;
 258         u16 next_to_clean;
 259
 260         u8 atr_sample_rate;
 261         u8 atr_count;
 262
 263         unsigned long last_rx_timestamp;
 264
 265         bool ring_active;               /* is ring online or not */
 266         bool arm_wb;            /* do something to arm write back */
 267
 268         u16 flags;
 269 #define I40E_TXR_FLAGS_WB_ON_ITR        BIT(0)
 270 #define I40E_TXR_FLAGS_OUTER_UDP_CSUM   BIT(1)
 271
 272         /* stats structs */
 273         struct i40e_queue_stats stats;
 274         struct u64_stats_sync syncp;
 275         union {
 276                 struct i40e_tx_queue_stats tx_stats;
 277                 struct i40e_rx_queue_stats rx_stats;
 278         };
 279
 280         unsigned int size;              /* length of descriptor ring in bytes */
 281         dma_addr_t dma;                 /* physical address of ring */
 282
 283         struct i40e_vsi *vsi;           /* Backreference to associated VSI */
 284         struct i40e_q_vector *q_vector; /* Backreference to associated vector */
 285
 286         struct rcu_head rcu;            /* to avoid race on free */
 287 } ____cacheline_internodealigned_in_smp;
 288
 289 enum i40e_latency_range {
 290         I40E_LOWEST_LATENCY = 0,
 291         I40E_LOW_LATENCY = 1,
 292         I40E_BULK_LATENCY = 2,
 293 };
 294
 295 struct i40e_ring_container {
 296         /* array of pointers to rings */
 297         struct i40e_ring *ring;
 298         unsigned int total_bytes;       /* total bytes processed this int */
 299         unsigned int total_packets;     /* total packets processed this int */
 300         u16 count;
 301         enum i40e_latency_range latency_range;
 302         u16 itr;
 303 };
 304
 305 /* iterator for handling rings in ring container */
 306 #define i40e_for_each_ring(pos, head) \
 307         for (pos = (head).ring; pos != NULL; pos = pos->next)
 308
 309 void i40e_alloc_rx_buffers_ps(struct i40e_ring *rxr, u16 cleaned_count);
 310 void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rxr, u16 cleaned_count);
 311 void i40e_alloc_rx_headers(struct i40e_ring *rxr);
 312 netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
 313 void i40e_clean_tx_ring(struct i40e_ring *tx_ring);
 314 void i40e_clean_rx_ring(struct i40e_ring *rx_ring);
 315 int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring);
 316 int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring);
 317 void i40e_free_tx_resources(struct i40e_ring *tx_ring);
 318 void i40e_free_rx_resources(struct i40e_ring *rx_ring);
 319 int i40e_napi_poll(struct napi_struct *napi, int budget);
 320 #ifdef I40E_FCOE
 321 void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
 322                  struct i40e_tx_buffer *first, u32 tx_flags,
 323                  const u8 hdr_len, u32 td_cmd, u32 td_offset);
 324 int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size);
 325 int i40e_xmit_descriptor_count(struct sk_buff *skb, struct i40e_ring *tx_ring);
 326 int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
 327                                struct i40e_ring *tx_ring, u32 *flags);
 328 #endif
 329 #endif /* _I40E_TXRX_H_ */