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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[deliverable/linux.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #include <linux/prefetch.h>
28
29 #include "i40evf.h"
30 #include "i40e_prototype.h"
31
32 static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34 {
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40 }
41
42 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
43
44 /**
45 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
46 * @ring: the ring that owns the buffer
47 * @tx_buffer: the buffer to free
48 **/
49 static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
50 struct i40e_tx_buffer *tx_buffer)
51 {
52 if (tx_buffer->skb) {
53 dev_kfree_skb_any(tx_buffer->skb);
54 if (dma_unmap_len(tx_buffer, len))
55 dma_unmap_single(ring->dev,
56 dma_unmap_addr(tx_buffer, dma),
57 dma_unmap_len(tx_buffer, len),
58 DMA_TO_DEVICE);
59 } else if (dma_unmap_len(tx_buffer, len)) {
60 dma_unmap_page(ring->dev,
61 dma_unmap_addr(tx_buffer, dma),
62 dma_unmap_len(tx_buffer, len),
63 DMA_TO_DEVICE);
64 }
65 tx_buffer->next_to_watch = NULL;
66 tx_buffer->skb = NULL;
67 dma_unmap_len_set(tx_buffer, len, 0);
68 /* tx_buffer must be completely set up in the transmit path */
69 }
70
71 /**
72 * i40evf_clean_tx_ring - Free any empty Tx buffers
73 * @tx_ring: ring to be cleaned
74 **/
75 void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
76 {
77 unsigned long bi_size;
78 u16 i;
79
80 /* ring already cleared, nothing to do */
81 if (!tx_ring->tx_bi)
82 return;
83
84 /* Free all the Tx ring sk_buffs */
85 for (i = 0; i < tx_ring->count; i++)
86 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
87
88 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
89 memset(tx_ring->tx_bi, 0, bi_size);
90
91 /* Zero out the descriptor ring */
92 memset(tx_ring->desc, 0, tx_ring->size);
93
94 tx_ring->next_to_use = 0;
95 tx_ring->next_to_clean = 0;
96
97 if (!tx_ring->netdev)
98 return;
99
100 /* cleanup Tx queue statistics */
101 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
102 tx_ring->queue_index));
103 }
104
105 /**
106 * i40evf_free_tx_resources - Free Tx resources per queue
107 * @tx_ring: Tx descriptor ring for a specific queue
108 *
109 * Free all transmit software resources
110 **/
111 void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
112 {
113 i40evf_clean_tx_ring(tx_ring);
114 kfree(tx_ring->tx_bi);
115 tx_ring->tx_bi = NULL;
116
117 if (tx_ring->desc) {
118 dma_free_coherent(tx_ring->dev, tx_ring->size,
119 tx_ring->desc, tx_ring->dma);
120 tx_ring->desc = NULL;
121 }
122 }
123
124 /**
125 * i40e_get_tx_pending - how many tx descriptors not processed
126 * @tx_ring: the ring of descriptors
127 *
128 * Since there is no access to the ring head register
129 * in XL710, we need to use our local copies
130 **/
131 static u32 i40e_get_tx_pending(struct i40e_ring *ring)
132 {
133 u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
134 ? ring->next_to_use
135 : ring->next_to_use + ring->count);
136 return ntu - ring->next_to_clean;
137 }
138
139 /**
140 * i40e_check_tx_hang - Is there a hang in the Tx queue
141 * @tx_ring: the ring of descriptors
142 **/
143 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
144 {
145 u32 tx_pending = i40e_get_tx_pending(tx_ring);
146 bool ret = false;
147
148 clear_check_for_tx_hang(tx_ring);
149
150 /* Check for a hung queue, but be thorough. This verifies
151 * that a transmit has been completed since the previous
152 * check AND there is at least one packet pending. The
153 * ARMED bit is set to indicate a potential hang. The
154 * bit is cleared if a pause frame is received to remove
155 * false hang detection due to PFC or 802.3x frames. By
156 * requiring this to fail twice we avoid races with
157 * PFC clearing the ARMED bit and conditions where we
158 * run the check_tx_hang logic with a transmit completion
159 * pending but without time to complete it yet.
160 */
161 if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
162 tx_pending) {
163 /* make sure it is true for two checks in a row */
164 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
165 &tx_ring->state);
166 } else {
167 /* update completed stats and disarm the hang check */
168 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
169 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
170 }
171
172 return ret;
173 }
174
175 /**
176 * i40e_get_head - Retrieve head from head writeback
177 * @tx_ring: tx ring to fetch head of
178 *
179 * Returns value of Tx ring head based on value stored
180 * in head write-back location
181 **/
182 static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
183 {
184 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
185
186 return le32_to_cpu(*(volatile __le32 *)head);
187 }
188
189 /**
190 * i40e_clean_tx_irq - Reclaim resources after transmit completes
191 * @tx_ring: tx ring to clean
192 * @budget: how many cleans we're allowed
193 *
194 * Returns true if there's any budget left (e.g. the clean is finished)
195 **/
196 static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
197 {
198 u16 i = tx_ring->next_to_clean;
199 struct i40e_tx_buffer *tx_buf;
200 struct i40e_tx_desc *tx_head;
201 struct i40e_tx_desc *tx_desc;
202 unsigned int total_packets = 0;
203 unsigned int total_bytes = 0;
204
205 tx_buf = &tx_ring->tx_bi[i];
206 tx_desc = I40E_TX_DESC(tx_ring, i);
207 i -= tx_ring->count;
208
209 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
210
211 do {
212 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
213
214 /* if next_to_watch is not set then there is no work pending */
215 if (!eop_desc)
216 break;
217
218 /* prevent any other reads prior to eop_desc */
219 read_barrier_depends();
220
221 /* we have caught up to head, no work left to do */
222 if (tx_head == tx_desc)
223 break;
224
225 /* clear next_to_watch to prevent false hangs */
226 tx_buf->next_to_watch = NULL;
227
228 /* update the statistics for this packet */
229 total_bytes += tx_buf->bytecount;
230 total_packets += tx_buf->gso_segs;
231
232 /* free the skb */
233 dev_kfree_skb_any(tx_buf->skb);
234
235 /* unmap skb header data */
236 dma_unmap_single(tx_ring->dev,
237 dma_unmap_addr(tx_buf, dma),
238 dma_unmap_len(tx_buf, len),
239 DMA_TO_DEVICE);
240
241 /* clear tx_buffer data */
242 tx_buf->skb = NULL;
243 dma_unmap_len_set(tx_buf, len, 0);
244
245 /* unmap remaining buffers */
246 while (tx_desc != eop_desc) {
247
248 tx_buf++;
249 tx_desc++;
250 i++;
251 if (unlikely(!i)) {
252 i -= tx_ring->count;
253 tx_buf = tx_ring->tx_bi;
254 tx_desc = I40E_TX_DESC(tx_ring, 0);
255 }
256
257 /* unmap any remaining paged data */
258 if (dma_unmap_len(tx_buf, len)) {
259 dma_unmap_page(tx_ring->dev,
260 dma_unmap_addr(tx_buf, dma),
261 dma_unmap_len(tx_buf, len),
262 DMA_TO_DEVICE);
263 dma_unmap_len_set(tx_buf, len, 0);
264 }
265 }
266
267 /* move us one more past the eop_desc for start of next pkt */
268 tx_buf++;
269 tx_desc++;
270 i++;
271 if (unlikely(!i)) {
272 i -= tx_ring->count;
273 tx_buf = tx_ring->tx_bi;
274 tx_desc = I40E_TX_DESC(tx_ring, 0);
275 }
276
277 /* update budget accounting */
278 budget--;
279 } while (likely(budget));
280
281 i += tx_ring->count;
282 tx_ring->next_to_clean = i;
283 u64_stats_update_begin(&tx_ring->syncp);
284 tx_ring->stats.bytes += total_bytes;
285 tx_ring->stats.packets += total_packets;
286 u64_stats_update_end(&tx_ring->syncp);
287 tx_ring->q_vector->tx.total_bytes += total_bytes;
288 tx_ring->q_vector->tx.total_packets += total_packets;
289
290 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
291 /* schedule immediate reset if we believe we hung */
292 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
293 " VSI <%d>\n"
294 " Tx Queue <%d>\n"
295 " next_to_use <%x>\n"
296 " next_to_clean <%x>\n",
297 tx_ring->vsi->seid,
298 tx_ring->queue_index,
299 tx_ring->next_to_use, i);
300 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
301 " time_stamp <%lx>\n"
302 " jiffies <%lx>\n",
303 tx_ring->tx_bi[i].time_stamp, jiffies);
304
305 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
306
307 dev_info(tx_ring->dev,
308 "tx hang detected on queue %d, resetting adapter\n",
309 tx_ring->queue_index);
310
311 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
312
313 /* the adapter is about to reset, no point in enabling stuff */
314 return true;
315 }
316
317 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
318 tx_ring->queue_index),
319 total_packets, total_bytes);
320
321 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
322 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
323 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
324 /* Make sure that anybody stopping the queue after this
325 * sees the new next_to_clean.
326 */
327 smp_mb();
328 if (__netif_subqueue_stopped(tx_ring->netdev,
329 tx_ring->queue_index) &&
330 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
331 netif_wake_subqueue(tx_ring->netdev,
332 tx_ring->queue_index);
333 ++tx_ring->tx_stats.restart_queue;
334 }
335 }
336
337 return budget > 0;
338 }
339
340 /**
341 * i40e_set_new_dynamic_itr - Find new ITR level
342 * @rc: structure containing ring performance data
343 *
344 * Stores a new ITR value based on packets and byte counts during
345 * the last interrupt. The advantage of per interrupt computation
346 * is faster updates and more accurate ITR for the current traffic
347 * pattern. Constants in this function were computed based on
348 * theoretical maximum wire speed and thresholds were set based on
349 * testing data as well as attempting to minimize response time
350 * while increasing bulk throughput.
351 **/
352 static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
353 {
354 enum i40e_latency_range new_latency_range = rc->latency_range;
355 u32 new_itr = rc->itr;
356 int bytes_per_int;
357
358 if (rc->total_packets == 0 || !rc->itr)
359 return;
360
361 /* simple throttlerate management
362 * 0-10MB/s lowest (100000 ints/s)
363 * 10-20MB/s low (20000 ints/s)
364 * 20-1249MB/s bulk (8000 ints/s)
365 */
366 bytes_per_int = rc->total_bytes / rc->itr;
367 switch (rc->itr) {
368 case I40E_LOWEST_LATENCY:
369 if (bytes_per_int > 10)
370 new_latency_range = I40E_LOW_LATENCY;
371 break;
372 case I40E_LOW_LATENCY:
373 if (bytes_per_int > 20)
374 new_latency_range = I40E_BULK_LATENCY;
375 else if (bytes_per_int <= 10)
376 new_latency_range = I40E_LOWEST_LATENCY;
377 break;
378 case I40E_BULK_LATENCY:
379 if (bytes_per_int <= 20)
380 rc->latency_range = I40E_LOW_LATENCY;
381 break;
382 }
383
384 switch (new_latency_range) {
385 case I40E_LOWEST_LATENCY:
386 new_itr = I40E_ITR_100K;
387 break;
388 case I40E_LOW_LATENCY:
389 new_itr = I40E_ITR_20K;
390 break;
391 case I40E_BULK_LATENCY:
392 new_itr = I40E_ITR_8K;
393 break;
394 default:
395 break;
396 }
397
398 if (new_itr != rc->itr) {
399 /* do an exponential smoothing */
400 new_itr = (10 * new_itr * rc->itr) /
401 ((9 * new_itr) + rc->itr);
402 rc->itr = new_itr & I40E_MAX_ITR;
403 }
404
405 rc->total_bytes = 0;
406 rc->total_packets = 0;
407 }
408
409 /**
410 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
411 * @q_vector: the vector to adjust
412 **/
413 static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
414 {
415 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
416 struct i40e_hw *hw = &q_vector->vsi->back->hw;
417 u32 reg_addr;
418 u16 old_itr;
419
420 reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
421 old_itr = q_vector->rx.itr;
422 i40e_set_new_dynamic_itr(&q_vector->rx);
423 if (old_itr != q_vector->rx.itr)
424 wr32(hw, reg_addr, q_vector->rx.itr);
425
426 reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
427 old_itr = q_vector->tx.itr;
428 i40e_set_new_dynamic_itr(&q_vector->tx);
429 if (old_itr != q_vector->tx.itr)
430 wr32(hw, reg_addr, q_vector->tx.itr);
431 }
432
433 /**
434 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
435 * @tx_ring: the tx ring to set up
436 *
437 * Return 0 on success, negative on error
438 **/
439 int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
440 {
441 struct device *dev = tx_ring->dev;
442 int bi_size;
443
444 if (!dev)
445 return -ENOMEM;
446
447 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
448 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
449 if (!tx_ring->tx_bi)
450 goto err;
451
452 /* round up to nearest 4K */
453 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
454 /* add u32 for head writeback, align after this takes care of
455 * guaranteeing this is at least one cache line in size
456 */
457 tx_ring->size += sizeof(u32);
458 tx_ring->size = ALIGN(tx_ring->size, 4096);
459 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
460 &tx_ring->dma, GFP_KERNEL);
461 if (!tx_ring->desc) {
462 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
463 tx_ring->size);
464 goto err;
465 }
466
467 tx_ring->next_to_use = 0;
468 tx_ring->next_to_clean = 0;
469 return 0;
470
471 err:
472 kfree(tx_ring->tx_bi);
473 tx_ring->tx_bi = NULL;
474 return -ENOMEM;
475 }
476
477 /**
478 * i40evf_clean_rx_ring - Free Rx buffers
479 * @rx_ring: ring to be cleaned
480 **/
481 void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
482 {
483 struct device *dev = rx_ring->dev;
484 struct i40e_rx_buffer *rx_bi;
485 unsigned long bi_size;
486 u16 i;
487
488 /* ring already cleared, nothing to do */
489 if (!rx_ring->rx_bi)
490 return;
491
492 /* Free all the Rx ring sk_buffs */
493 for (i = 0; i < rx_ring->count; i++) {
494 rx_bi = &rx_ring->rx_bi[i];
495 if (rx_bi->dma) {
496 dma_unmap_single(dev,
497 rx_bi->dma,
498 rx_ring->rx_buf_len,
499 DMA_FROM_DEVICE);
500 rx_bi->dma = 0;
501 }
502 if (rx_bi->skb) {
503 dev_kfree_skb(rx_bi->skb);
504 rx_bi->skb = NULL;
505 }
506 if (rx_bi->page) {
507 if (rx_bi->page_dma) {
508 dma_unmap_page(dev,
509 rx_bi->page_dma,
510 PAGE_SIZE / 2,
511 DMA_FROM_DEVICE);
512 rx_bi->page_dma = 0;
513 }
514 __free_page(rx_bi->page);
515 rx_bi->page = NULL;
516 rx_bi->page_offset = 0;
517 }
518 }
519
520 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
521 memset(rx_ring->rx_bi, 0, bi_size);
522
523 /* Zero out the descriptor ring */
524 memset(rx_ring->desc, 0, rx_ring->size);
525
526 rx_ring->next_to_clean = 0;
527 rx_ring->next_to_use = 0;
528 }
529
530 /**
531 * i40evf_free_rx_resources - Free Rx resources
532 * @rx_ring: ring to clean the resources from
533 *
534 * Free all receive software resources
535 **/
536 void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
537 {
538 i40evf_clean_rx_ring(rx_ring);
539 kfree(rx_ring->rx_bi);
540 rx_ring->rx_bi = NULL;
541
542 if (rx_ring->desc) {
543 dma_free_coherent(rx_ring->dev, rx_ring->size,
544 rx_ring->desc, rx_ring->dma);
545 rx_ring->desc = NULL;
546 }
547 }
548
549 /**
550 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
551 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
552 *
553 * Returns 0 on success, negative on failure
554 **/
555 int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
556 {
557 struct device *dev = rx_ring->dev;
558 int bi_size;
559
560 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
561 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
562 if (!rx_ring->rx_bi)
563 goto err;
564
565 /* Round up to nearest 4K */
566 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
567 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
568 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
569 rx_ring->size = ALIGN(rx_ring->size, 4096);
570 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
571 &rx_ring->dma, GFP_KERNEL);
572
573 if (!rx_ring->desc) {
574 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
575 rx_ring->size);
576 goto err;
577 }
578
579 rx_ring->next_to_clean = 0;
580 rx_ring->next_to_use = 0;
581
582 return 0;
583 err:
584 kfree(rx_ring->rx_bi);
585 rx_ring->rx_bi = NULL;
586 return -ENOMEM;
587 }
588
589 /**
590 * i40e_release_rx_desc - Store the new tail and head values
591 * @rx_ring: ring to bump
592 * @val: new head index
593 **/
594 static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
595 {
596 rx_ring->next_to_use = val;
597 /* Force memory writes to complete before letting h/w
598 * know there are new descriptors to fetch. (Only
599 * applicable for weak-ordered memory model archs,
600 * such as IA-64).
601 */
602 wmb();
603 writel(val, rx_ring->tail);
604 }
605
606 /**
607 * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
608 * @rx_ring: ring to place buffers on
609 * @cleaned_count: number of buffers to replace
610 **/
611 void i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
612 {
613 u16 i = rx_ring->next_to_use;
614 union i40e_rx_desc *rx_desc;
615 struct i40e_rx_buffer *bi;
616 struct sk_buff *skb;
617
618 /* do nothing if no valid netdev defined */
619 if (!rx_ring->netdev || !cleaned_count)
620 return;
621
622 while (cleaned_count--) {
623 rx_desc = I40E_RX_DESC(rx_ring, i);
624 bi = &rx_ring->rx_bi[i];
625 skb = bi->skb;
626
627 if (!skb) {
628 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
629 rx_ring->rx_buf_len);
630 if (!skb) {
631 rx_ring->rx_stats.alloc_buff_failed++;
632 goto no_buffers;
633 }
634 /* initialize queue mapping */
635 skb_record_rx_queue(skb, rx_ring->queue_index);
636 bi->skb = skb;
637 }
638
639 if (!bi->dma) {
640 bi->dma = dma_map_single(rx_ring->dev,
641 skb->data,
642 rx_ring->rx_buf_len,
643 DMA_FROM_DEVICE);
644 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
645 rx_ring->rx_stats.alloc_buff_failed++;
646 bi->dma = 0;
647 goto no_buffers;
648 }
649 }
650
651 if (ring_is_ps_enabled(rx_ring)) {
652 if (!bi->page) {
653 bi->page = alloc_page(GFP_ATOMIC);
654 if (!bi->page) {
655 rx_ring->rx_stats.alloc_page_failed++;
656 goto no_buffers;
657 }
658 }
659
660 if (!bi->page_dma) {
661 /* use a half page if we're re-using */
662 bi->page_offset ^= PAGE_SIZE / 2;
663 bi->page_dma = dma_map_page(rx_ring->dev,
664 bi->page,
665 bi->page_offset,
666 PAGE_SIZE / 2,
667 DMA_FROM_DEVICE);
668 if (dma_mapping_error(rx_ring->dev,
669 bi->page_dma)) {
670 rx_ring->rx_stats.alloc_page_failed++;
671 bi->page_dma = 0;
672 goto no_buffers;
673 }
674 }
675
676 /* Refresh the desc even if buffer_addrs didn't change
677 * because each write-back erases this info.
678 */
679 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
680 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
681 } else {
682 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
683 rx_desc->read.hdr_addr = 0;
684 }
685 i++;
686 if (i == rx_ring->count)
687 i = 0;
688 }
689
690 no_buffers:
691 if (rx_ring->next_to_use != i)
692 i40e_release_rx_desc(rx_ring, i);
693 }
694
695 /**
696 * i40e_receive_skb - Send a completed packet up the stack
697 * @rx_ring: rx ring in play
698 * @skb: packet to send up
699 * @vlan_tag: vlan tag for packet
700 **/
701 static void i40e_receive_skb(struct i40e_ring *rx_ring,
702 struct sk_buff *skb, u16 vlan_tag)
703 {
704 struct i40e_q_vector *q_vector = rx_ring->q_vector;
705 struct i40e_vsi *vsi = rx_ring->vsi;
706 u64 flags = vsi->back->flags;
707
708 if (vlan_tag & VLAN_VID_MASK)
709 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
710
711 if (flags & I40E_FLAG_IN_NETPOLL)
712 netif_rx(skb);
713 else
714 napi_gro_receive(&q_vector->napi, skb);
715 }
716
717 /**
718 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
719 * @vsi: the VSI we care about
720 * @skb: skb currently being received and modified
721 * @rx_status: status value of last descriptor in packet
722 * @rx_error: error value of last descriptor in packet
723 * @rx_ptype: ptype value of last descriptor in packet
724 **/
725 static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
726 struct sk_buff *skb,
727 u32 rx_status,
728 u32 rx_error,
729 u16 rx_ptype)
730 {
731 bool ipv4_tunnel, ipv6_tunnel;
732 __wsum rx_udp_csum;
733 __sum16 csum;
734 struct iphdr *iph;
735
736 ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
737 (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
738 ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
739 (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
740
741 skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
742 skb->ip_summed = CHECKSUM_NONE;
743
744 /* Rx csum enabled and ip headers found? */
745 if (!(vsi->netdev->features & NETIF_F_RXCSUM &&
746 rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
747 return;
748
749 /* likely incorrect csum if alternate IP extension headers found */
750 if (rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
751 return;
752
753 /* IP or L4 or outmost IP checksum error */
754 if (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
755 (1 << I40E_RX_DESC_ERROR_L4E_SHIFT) |
756 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))) {
757 vsi->back->hw_csum_rx_error++;
758 return;
759 }
760
761 if (ipv4_tunnel &&
762 !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
763 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
764 * it in the driver, hardware does not do it for us.
765 * Since L3L4P bit was set we assume a valid IHL value (>=5)
766 * so the total length of IPv4 header is IHL*4 bytes
767 */
768 skb->transport_header = skb->mac_header +
769 sizeof(struct ethhdr) +
770 (ip_hdr(skb)->ihl * 4);
771
772 /* Add 4 bytes for VLAN tagged packets */
773 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
774 skb->protocol == htons(ETH_P_8021AD))
775 ? VLAN_HLEN : 0;
776
777 rx_udp_csum = udp_csum(skb);
778 iph = ip_hdr(skb);
779 csum = csum_tcpudp_magic(
780 iph->saddr, iph->daddr,
781 (skb->len - skb_transport_offset(skb)),
782 IPPROTO_UDP, rx_udp_csum);
783
784 if (udp_hdr(skb)->check != csum) {
785 vsi->back->hw_csum_rx_error++;
786 return;
787 }
788 }
789
790 skb->ip_summed = CHECKSUM_UNNECESSARY;
791 }
792
793 /**
794 * i40e_rx_hash - returns the hash value from the Rx descriptor
795 * @ring: descriptor ring
796 * @rx_desc: specific descriptor
797 **/
798 static inline u32 i40e_rx_hash(struct i40e_ring *ring,
799 union i40e_rx_desc *rx_desc)
800 {
801 const __le64 rss_mask =
802 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
803 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
804
805 if ((ring->netdev->features & NETIF_F_RXHASH) &&
806 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
807 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
808 else
809 return 0;
810 }
811
812 /**
813 * i40e_ptype_to_hash - get a hash type
814 * @ptype: the ptype value from the descriptor
815 *
816 * Returns a hash type to be used by skb_set_hash
817 **/
818 static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
819 {
820 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
821
822 if (!decoded.known)
823 return PKT_HASH_TYPE_NONE;
824
825 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
826 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
827 return PKT_HASH_TYPE_L4;
828 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
829 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
830 return PKT_HASH_TYPE_L3;
831 else
832 return PKT_HASH_TYPE_L2;
833 }
834
835 /**
836 * i40e_clean_rx_irq - Reclaim resources after receive completes
837 * @rx_ring: rx ring to clean
838 * @budget: how many cleans we're allowed
839 *
840 * Returns true if there's any budget left (e.g. the clean is finished)
841 **/
842 static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
843 {
844 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
845 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
846 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
847 const int current_node = numa_node_id();
848 struct i40e_vsi *vsi = rx_ring->vsi;
849 u16 i = rx_ring->next_to_clean;
850 union i40e_rx_desc *rx_desc;
851 u32 rx_error, rx_status;
852 u8 rx_ptype;
853 u64 qword;
854
855 rx_desc = I40E_RX_DESC(rx_ring, i);
856 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
857 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
858 I40E_RXD_QW1_STATUS_SHIFT;
859
860 while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
861 union i40e_rx_desc *next_rxd;
862 struct i40e_rx_buffer *rx_bi;
863 struct sk_buff *skb;
864 u16 vlan_tag;
865 rx_bi = &rx_ring->rx_bi[i];
866 skb = rx_bi->skb;
867 prefetch(skb->data);
868
869 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
870 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
871 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
872 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
873 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
874 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
875
876 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
877 I40E_RXD_QW1_ERROR_SHIFT;
878 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
879 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
880
881 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
882 I40E_RXD_QW1_PTYPE_SHIFT;
883 rx_bi->skb = NULL;
884
885 /* This memory barrier is needed to keep us from reading
886 * any other fields out of the rx_desc until we know the
887 * STATUS_DD bit is set
888 */
889 rmb();
890
891 /* Get the header and possibly the whole packet
892 * If this is an skb from previous receive dma will be 0
893 */
894 if (rx_bi->dma) {
895 u16 len;
896
897 if (rx_hbo)
898 len = I40E_RX_HDR_SIZE;
899 else if (rx_sph)
900 len = rx_header_len;
901 else if (rx_packet_len)
902 len = rx_packet_len; /* 1buf/no split found */
903 else
904 len = rx_header_len; /* split always mode */
905
906 skb_put(skb, len);
907 dma_unmap_single(rx_ring->dev,
908 rx_bi->dma,
909 rx_ring->rx_buf_len,
910 DMA_FROM_DEVICE);
911 rx_bi->dma = 0;
912 }
913
914 /* Get the rest of the data if this was a header split */
915 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
916
917 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
918 rx_bi->page,
919 rx_bi->page_offset,
920 rx_packet_len);
921
922 skb->len += rx_packet_len;
923 skb->data_len += rx_packet_len;
924 skb->truesize += rx_packet_len;
925
926 if ((page_count(rx_bi->page) == 1) &&
927 (page_to_nid(rx_bi->page) == current_node))
928 get_page(rx_bi->page);
929 else
930 rx_bi->page = NULL;
931
932 dma_unmap_page(rx_ring->dev,
933 rx_bi->page_dma,
934 PAGE_SIZE / 2,
935 DMA_FROM_DEVICE);
936 rx_bi->page_dma = 0;
937 }
938 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
939
940 if (unlikely(
941 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
942 struct i40e_rx_buffer *next_buffer;
943
944 next_buffer = &rx_ring->rx_bi[i];
945
946 if (ring_is_ps_enabled(rx_ring)) {
947 rx_bi->skb = next_buffer->skb;
948 rx_bi->dma = next_buffer->dma;
949 next_buffer->skb = skb;
950 next_buffer->dma = 0;
951 }
952 rx_ring->rx_stats.non_eop_descs++;
953 goto next_desc;
954 }
955
956 /* ERR_MASK will only have valid bits if EOP set */
957 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
958 dev_kfree_skb_any(skb);
959 goto next_desc;
960 }
961
962 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
963 i40e_ptype_to_hash(rx_ptype));
964 /* probably a little skewed due to removing CRC */
965 total_rx_bytes += skb->len;
966 total_rx_packets++;
967
968 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
969
970 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
971
972 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
973 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
974 : 0;
975 i40e_receive_skb(rx_ring, skb, vlan_tag);
976
977 rx_ring->netdev->last_rx = jiffies;
978 budget--;
979 next_desc:
980 rx_desc->wb.qword1.status_error_len = 0;
981 if (!budget)
982 break;
983
984 cleaned_count++;
985 /* return some buffers to hardware, one at a time is too slow */
986 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
987 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
988 cleaned_count = 0;
989 }
990
991 /* use prefetched values */
992 rx_desc = next_rxd;
993 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
994 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
995 I40E_RXD_QW1_STATUS_SHIFT;
996 }
997
998 rx_ring->next_to_clean = i;
999 u64_stats_update_begin(&rx_ring->syncp);
1000 rx_ring->stats.packets += total_rx_packets;
1001 rx_ring->stats.bytes += total_rx_bytes;
1002 u64_stats_update_end(&rx_ring->syncp);
1003 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1004 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1005
1006 if (cleaned_count)
1007 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1008
1009 return budget > 0;
1010 }
1011
1012 /**
1013 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1014 * @napi: napi struct with our devices info in it
1015 * @budget: amount of work driver is allowed to do this pass, in packets
1016 *
1017 * This function will clean all queues associated with a q_vector.
1018 *
1019 * Returns the amount of work done
1020 **/
1021 int i40evf_napi_poll(struct napi_struct *napi, int budget)
1022 {
1023 struct i40e_q_vector *q_vector =
1024 container_of(napi, struct i40e_q_vector, napi);
1025 struct i40e_vsi *vsi = q_vector->vsi;
1026 struct i40e_ring *ring;
1027 bool clean_complete = true;
1028 int budget_per_ring;
1029
1030 if (test_bit(__I40E_DOWN, &vsi->state)) {
1031 napi_complete(napi);
1032 return 0;
1033 }
1034
1035 /* Since the actual Tx work is minimal, we can give the Tx a larger
1036 * budget and be more aggressive about cleaning up the Tx descriptors.
1037 */
1038 i40e_for_each_ring(ring, q_vector->tx)
1039 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1040
1041 /* We attempt to distribute budget to each Rx queue fairly, but don't
1042 * allow the budget to go below 1 because that would exit polling early.
1043 */
1044 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1045
1046 i40e_for_each_ring(ring, q_vector->rx)
1047 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring);
1048
1049 /* If work not completed, return budget and polling will return */
1050 if (!clean_complete)
1051 return budget;
1052
1053 /* Work is done so exit the polling mode and re-enable the interrupt */
1054 napi_complete(napi);
1055 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1056 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1057 i40e_update_dynamic_itr(q_vector);
1058
1059 if (!test_bit(__I40E_DOWN, &vsi->state))
1060 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1061
1062 return 0;
1063 }
1064
1065 /**
1066 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1067 * @skb: send buffer
1068 * @tx_ring: ring to send buffer on
1069 * @flags: the tx flags to be set
1070 *
1071 * Checks the skb and set up correspondingly several generic transmit flags
1072 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1073 *
1074 * Returns error code indicate the frame should be dropped upon error and the
1075 * otherwise returns 0 to indicate the flags has been set properly.
1076 **/
1077 static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1078 struct i40e_ring *tx_ring,
1079 u32 *flags)
1080 {
1081 __be16 protocol = skb->protocol;
1082 u32 tx_flags = 0;
1083
1084 /* if we have a HW VLAN tag being added, default to the HW one */
1085 if (vlan_tx_tag_present(skb)) {
1086 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1087 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1088 /* else if it is a SW VLAN, check the next protocol and store the tag */
1089 } else if (protocol == htons(ETH_P_8021Q)) {
1090 struct vlan_hdr *vhdr, _vhdr;
1091 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1092 if (!vhdr)
1093 return -EINVAL;
1094
1095 protocol = vhdr->h_vlan_encapsulated_proto;
1096 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1097 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1098 }
1099
1100 *flags = tx_flags;
1101 return 0;
1102 }
1103
1104 /**
1105 * i40e_tso - set up the tso context descriptor
1106 * @tx_ring: ptr to the ring to send
1107 * @skb: ptr to the skb we're sending
1108 * @tx_flags: the collected send information
1109 * @protocol: the send protocol
1110 * @hdr_len: ptr to the size of the packet header
1111 * @cd_tunneling: ptr to context descriptor bits
1112 *
1113 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1114 **/
1115 static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1116 u32 tx_flags, __be16 protocol, u8 *hdr_len,
1117 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1118 {
1119 u32 cd_cmd, cd_tso_len, cd_mss;
1120 struct ipv6hdr *ipv6h;
1121 struct tcphdr *tcph;
1122 struct iphdr *iph;
1123 u32 l4len;
1124 int err;
1125
1126 if (!skb_is_gso(skb))
1127 return 0;
1128
1129 err = skb_cow_head(skb, 0);
1130 if (err < 0)
1131 return err;
1132
1133 if (protocol == htons(ETH_P_IP)) {
1134 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1135 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1136 iph->tot_len = 0;
1137 iph->check = 0;
1138 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1139 0, IPPROTO_TCP, 0);
1140 } else if (skb_is_gso_v6(skb)) {
1141
1142 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1143 : ipv6_hdr(skb);
1144 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1145 ipv6h->payload_len = 0;
1146 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1147 0, IPPROTO_TCP, 0);
1148 }
1149
1150 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1151 *hdr_len = (skb->encapsulation
1152 ? (skb_inner_transport_header(skb) - skb->data)
1153 : skb_transport_offset(skb)) + l4len;
1154
1155 /* find the field values */
1156 cd_cmd = I40E_TX_CTX_DESC_TSO;
1157 cd_tso_len = skb->len - *hdr_len;
1158 cd_mss = skb_shinfo(skb)->gso_size;
1159 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1160 ((u64)cd_tso_len <<
1161 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1162 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1163 return 1;
1164 }
1165
1166 /**
1167 * i40e_tx_enable_csum - Enable Tx checksum offloads
1168 * @skb: send buffer
1169 * @tx_flags: Tx flags currently set
1170 * @td_cmd: Tx descriptor command bits to set
1171 * @td_offset: Tx descriptor header offsets to set
1172 * @cd_tunneling: ptr to context desc bits
1173 **/
1174 static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1175 u32 *td_cmd, u32 *td_offset,
1176 struct i40e_ring *tx_ring,
1177 u32 *cd_tunneling)
1178 {
1179 struct ipv6hdr *this_ipv6_hdr;
1180 unsigned int this_tcp_hdrlen;
1181 struct iphdr *this_ip_hdr;
1182 u32 network_hdr_len;
1183 u8 l4_hdr = 0;
1184
1185 if (skb->encapsulation) {
1186 network_hdr_len = skb_inner_network_header_len(skb);
1187 this_ip_hdr = inner_ip_hdr(skb);
1188 this_ipv6_hdr = inner_ipv6_hdr(skb);
1189 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1190
1191 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1192
1193 if (tx_flags & I40E_TX_FLAGS_TSO) {
1194 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1195 ip_hdr(skb)->check = 0;
1196 } else {
1197 *cd_tunneling |=
1198 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1199 }
1200 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1201 if (tx_flags & I40E_TX_FLAGS_TSO) {
1202 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1203 ip_hdr(skb)->check = 0;
1204 } else {
1205 *cd_tunneling |=
1206 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1207 }
1208 }
1209
1210 /* Now set the ctx descriptor fields */
1211 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1212 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1213 I40E_TXD_CTX_UDP_TUNNELING |
1214 ((skb_inner_network_offset(skb) -
1215 skb_transport_offset(skb)) >> 1) <<
1216 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1217
1218 } else {
1219 network_hdr_len = skb_network_header_len(skb);
1220 this_ip_hdr = ip_hdr(skb);
1221 this_ipv6_hdr = ipv6_hdr(skb);
1222 this_tcp_hdrlen = tcp_hdrlen(skb);
1223 }
1224
1225 /* Enable IP checksum offloads */
1226 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1227 l4_hdr = this_ip_hdr->protocol;
1228 /* the stack computes the IP header already, the only time we
1229 * need the hardware to recompute it is in the case of TSO.
1230 */
1231 if (tx_flags & I40E_TX_FLAGS_TSO) {
1232 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1233 this_ip_hdr->check = 0;
1234 } else {
1235 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1236 }
1237 /* Now set the td_offset for IP header length */
1238 *td_offset = (network_hdr_len >> 2) <<
1239 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1240 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1241 l4_hdr = this_ipv6_hdr->nexthdr;
1242 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1243 /* Now set the td_offset for IP header length */
1244 *td_offset = (network_hdr_len >> 2) <<
1245 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1246 }
1247 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1248 *td_offset |= (skb_network_offset(skb) >> 1) <<
1249 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1250
1251 /* Enable L4 checksum offloads */
1252 switch (l4_hdr) {
1253 case IPPROTO_TCP:
1254 /* enable checksum offloads */
1255 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1256 *td_offset |= (this_tcp_hdrlen >> 2) <<
1257 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1258 break;
1259 case IPPROTO_SCTP:
1260 /* enable SCTP checksum offload */
1261 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1262 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1263 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1264 break;
1265 case IPPROTO_UDP:
1266 /* enable UDP checksum offload */
1267 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1268 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1269 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1270 break;
1271 default:
1272 break;
1273 }
1274 }
1275
1276 /**
1277 * i40e_create_tx_ctx Build the Tx context descriptor
1278 * @tx_ring: ring to create the descriptor on
1279 * @cd_type_cmd_tso_mss: Quad Word 1
1280 * @cd_tunneling: Quad Word 0 - bits 0-31
1281 * @cd_l2tag2: Quad Word 0 - bits 32-63
1282 **/
1283 static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1284 const u64 cd_type_cmd_tso_mss,
1285 const u32 cd_tunneling, const u32 cd_l2tag2)
1286 {
1287 struct i40e_tx_context_desc *context_desc;
1288 int i = tx_ring->next_to_use;
1289
1290 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1291 !cd_tunneling && !cd_l2tag2)
1292 return;
1293
1294 /* grab the next descriptor */
1295 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1296
1297 i++;
1298 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1299
1300 /* cpu_to_le32 and assign to struct fields */
1301 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1302 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1303 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1304 }
1305
1306 /**
1307 * i40e_tx_map - Build the Tx descriptor
1308 * @tx_ring: ring to send buffer on
1309 * @skb: send buffer
1310 * @first: first buffer info buffer to use
1311 * @tx_flags: collected send information
1312 * @hdr_len: size of the packet header
1313 * @td_cmd: the command field in the descriptor
1314 * @td_offset: offset for checksum or crc
1315 **/
1316 static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1317 struct i40e_tx_buffer *first, u32 tx_flags,
1318 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1319 {
1320 unsigned int data_len = skb->data_len;
1321 unsigned int size = skb_headlen(skb);
1322 struct skb_frag_struct *frag;
1323 struct i40e_tx_buffer *tx_bi;
1324 struct i40e_tx_desc *tx_desc;
1325 u16 i = tx_ring->next_to_use;
1326 u32 td_tag = 0;
1327 dma_addr_t dma;
1328 u16 gso_segs;
1329
1330 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1331 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1332 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1333 I40E_TX_FLAGS_VLAN_SHIFT;
1334 }
1335
1336 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1337 gso_segs = skb_shinfo(skb)->gso_segs;
1338 else
1339 gso_segs = 1;
1340
1341 /* multiply data chunks by size of headers */
1342 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1343 first->gso_segs = gso_segs;
1344 first->skb = skb;
1345 first->tx_flags = tx_flags;
1346
1347 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1348
1349 tx_desc = I40E_TX_DESC(tx_ring, i);
1350 tx_bi = first;
1351
1352 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1353 if (dma_mapping_error(tx_ring->dev, dma))
1354 goto dma_error;
1355
1356 /* record length, and DMA address */
1357 dma_unmap_len_set(tx_bi, len, size);
1358 dma_unmap_addr_set(tx_bi, dma, dma);
1359
1360 tx_desc->buffer_addr = cpu_to_le64(dma);
1361
1362 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1363 tx_desc->cmd_type_offset_bsz =
1364 build_ctob(td_cmd, td_offset,
1365 I40E_MAX_DATA_PER_TXD, td_tag);
1366
1367 tx_desc++;
1368 i++;
1369 if (i == tx_ring->count) {
1370 tx_desc = I40E_TX_DESC(tx_ring, 0);
1371 i = 0;
1372 }
1373
1374 dma += I40E_MAX_DATA_PER_TXD;
1375 size -= I40E_MAX_DATA_PER_TXD;
1376
1377 tx_desc->buffer_addr = cpu_to_le64(dma);
1378 }
1379
1380 if (likely(!data_len))
1381 break;
1382
1383 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1384 size, td_tag);
1385
1386 tx_desc++;
1387 i++;
1388 if (i == tx_ring->count) {
1389 tx_desc = I40E_TX_DESC(tx_ring, 0);
1390 i = 0;
1391 }
1392
1393 size = skb_frag_size(frag);
1394 data_len -= size;
1395
1396 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1397 DMA_TO_DEVICE);
1398
1399 tx_bi = &tx_ring->tx_bi[i];
1400 }
1401
1402 /* Place RS bit on last descriptor of any packet that spans across the
1403 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1404 */
1405 #define WB_STRIDE 0x3
1406 if (((i & WB_STRIDE) != WB_STRIDE) &&
1407 (first <= &tx_ring->tx_bi[i]) &&
1408 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1409 tx_desc->cmd_type_offset_bsz =
1410 build_ctob(td_cmd, td_offset, size, td_tag) |
1411 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1412 I40E_TXD_QW1_CMD_SHIFT);
1413 } else {
1414 tx_desc->cmd_type_offset_bsz =
1415 build_ctob(td_cmd, td_offset, size, td_tag) |
1416 cpu_to_le64((u64)I40E_TXD_CMD <<
1417 I40E_TXD_QW1_CMD_SHIFT);
1418 }
1419
1420 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1421 tx_ring->queue_index),
1422 first->bytecount);
1423
1424 /* set the timestamp */
1425 first->time_stamp = jiffies;
1426
1427 /* Force memory writes to complete before letting h/w
1428 * know there are new descriptors to fetch. (Only
1429 * applicable for weak-ordered memory model archs,
1430 * such as IA-64).
1431 */
1432 wmb();
1433
1434 /* set next_to_watch value indicating a packet is present */
1435 first->next_to_watch = tx_desc;
1436
1437 i++;
1438 if (i == tx_ring->count)
1439 i = 0;
1440
1441 tx_ring->next_to_use = i;
1442
1443 /* notify HW of packet */
1444 writel(i, tx_ring->tail);
1445
1446 return;
1447
1448 dma_error:
1449 dev_info(tx_ring->dev, "TX DMA map failed\n");
1450
1451 /* clear dma mappings for failed tx_bi map */
1452 for (;;) {
1453 tx_bi = &tx_ring->tx_bi[i];
1454 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1455 if (tx_bi == first)
1456 break;
1457 if (i == 0)
1458 i = tx_ring->count;
1459 i--;
1460 }
1461
1462 tx_ring->next_to_use = i;
1463 }
1464
1465 /**
1466 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1467 * @tx_ring: the ring to be checked
1468 * @size: the size buffer we want to assure is available
1469 *
1470 * Returns -EBUSY if a stop is needed, else 0
1471 **/
1472 static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1473 {
1474 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1475 /* Memory barrier before checking head and tail */
1476 smp_mb();
1477
1478 /* Check again in a case another CPU has just made room available. */
1479 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1480 return -EBUSY;
1481
1482 /* A reprieve! - use start_queue because it doesn't call schedule */
1483 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1484 ++tx_ring->tx_stats.restart_queue;
1485 return 0;
1486 }
1487
1488 /**
1489 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1490 * @tx_ring: the ring to be checked
1491 * @size: the size buffer we want to assure is available
1492 *
1493 * Returns 0 if stop is not needed
1494 **/
1495 static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1496 {
1497 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1498 return 0;
1499 return __i40e_maybe_stop_tx(tx_ring, size);
1500 }
1501
1502 /**
1503 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1504 * @skb: send buffer
1505 * @tx_ring: ring to send buffer on
1506 *
1507 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1508 * there is not enough descriptors available in this ring since we need at least
1509 * one descriptor.
1510 **/
1511 static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1512 struct i40e_ring *tx_ring)
1513 {
1514 #if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1515 unsigned int f;
1516 #endif
1517 int count = 0;
1518
1519 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1520 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
1521 * + 4 desc gap to avoid the cache line where head is,
1522 * + 1 desc for context descriptor,
1523 * otherwise try next time
1524 */
1525 #if PAGE_SIZE > I40E_MAX_DATA_PER_TXD
1526 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1527 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
1528 #else
1529 count += skb_shinfo(skb)->nr_frags;
1530 #endif
1531 count += TXD_USE_COUNT(skb_headlen(skb));
1532 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
1533 tx_ring->tx_stats.tx_busy++;
1534 return 0;
1535 }
1536 return count;
1537 }
1538
1539 /**
1540 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1541 * @skb: send buffer
1542 * @tx_ring: ring to send buffer on
1543 *
1544 * Returns NETDEV_TX_OK if sent, else an error code
1545 **/
1546 static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1547 struct i40e_ring *tx_ring)
1548 {
1549 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1550 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1551 struct i40e_tx_buffer *first;
1552 u32 td_offset = 0;
1553 u32 tx_flags = 0;
1554 __be16 protocol;
1555 u32 td_cmd = 0;
1556 u8 hdr_len = 0;
1557 int tso;
1558 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1559 return NETDEV_TX_BUSY;
1560
1561 /* prepare the xmit flags */
1562 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1563 goto out_drop;
1564
1565 /* obtain protocol of skb */
1566 protocol = skb->protocol;
1567
1568 /* record the location of the first descriptor for this packet */
1569 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1570
1571 /* setup IPv4/IPv6 offloads */
1572 if (protocol == htons(ETH_P_IP))
1573 tx_flags |= I40E_TX_FLAGS_IPV4;
1574 else if (protocol == htons(ETH_P_IPV6))
1575 tx_flags |= I40E_TX_FLAGS_IPV6;
1576
1577 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1578 &cd_type_cmd_tso_mss, &cd_tunneling);
1579
1580 if (tso < 0)
1581 goto out_drop;
1582 else if (tso)
1583 tx_flags |= I40E_TX_FLAGS_TSO;
1584
1585 skb_tx_timestamp(skb);
1586
1587 /* always enable CRC insertion offload */
1588 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1589
1590 /* Always offload the checksum, since it's in the data descriptor */
1591 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1592 tx_flags |= I40E_TX_FLAGS_CSUM;
1593
1594 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1595 tx_ring, &cd_tunneling);
1596 }
1597
1598 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1599 cd_tunneling, cd_l2tag2);
1600
1601 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1602 td_cmd, td_offset);
1603
1604 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1605
1606 return NETDEV_TX_OK;
1607
1608 out_drop:
1609 dev_kfree_skb_any(skb);
1610 return NETDEV_TX_OK;
1611 }
1612
1613 /**
1614 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1615 * @skb: send buffer
1616 * @netdev: network interface device structure
1617 *
1618 * Returns NETDEV_TX_OK if sent, else an error code
1619 **/
1620 netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1621 {
1622 struct i40evf_adapter *adapter = netdev_priv(netdev);
1623 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1624
1625 /* hardware can't handle really short frames, hardware padding works
1626 * beyond this point
1627 */
1628 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1629 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1630 return NETDEV_TX_OK;
1631 skb->len = I40E_MIN_TX_LEN;
1632 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1633 }
1634
1635 return i40e_xmit_frame_ring(skb, tx_ring);
1636 }
Linux kernel - Deliverables
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