1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 ******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/if_ether.h>
36 #include "e1000_i210.h"
39 * igb_get_hw_semaphore_i210 - Acquire hardware semaphore
40 * @hw: pointer to the HW structure
42 * Acquire the HW semaphore to access the PHY or NVM
44 static s32
igb_get_hw_semaphore_i210(struct e1000_hw
*hw
)
47 s32 ret_val
= E1000_SUCCESS
;
48 s32 timeout
= hw
->nvm
.word_size
+ 1;
51 /* Get the FW semaphore. */
52 for (i
= 0; i
< timeout
; i
++) {
53 swsm
= rd32(E1000_SWSM
);
54 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
56 /* Semaphore acquired if bit latched */
57 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
64 /* Release semaphores */
65 igb_put_hw_semaphore(hw
);
66 hw_dbg("Driver can't access the NVM\n");
67 ret_val
= -E1000_ERR_NVM
;
76 * igb_acquire_nvm_i210 - Request for access to EEPROM
77 * @hw: pointer to the HW structure
79 * Acquire the necessary semaphores for exclusive access to the EEPROM.
80 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
81 * Return successful if access grant bit set, else clear the request for
82 * EEPROM access and return -E1000_ERR_NVM (-1).
84 s32
igb_acquire_nvm_i210(struct e1000_hw
*hw
)
86 return igb_acquire_swfw_sync_i210(hw
, E1000_SWFW_EEP_SM
);
90 * igb_release_nvm_i210 - Release exclusive access to EEPROM
91 * @hw: pointer to the HW structure
93 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
94 * then release the semaphores acquired.
96 void igb_release_nvm_i210(struct e1000_hw
*hw
)
98 igb_release_swfw_sync_i210(hw
, E1000_SWFW_EEP_SM
);
102 * igb_put_hw_semaphore_i210 - Release hardware semaphore
103 * @hw: pointer to the HW structure
105 * Release hardware semaphore used to access the PHY or NVM
107 static void igb_put_hw_semaphore_i210(struct e1000_hw
*hw
)
111 swsm
= rd32(E1000_SWSM
);
113 swsm
&= ~E1000_SWSM_SWESMBI
;
115 wr32(E1000_SWSM
, swsm
);
119 * igb_acquire_swfw_sync_i210 - Acquire SW/FW semaphore
120 * @hw: pointer to the HW structure
121 * @mask: specifies which semaphore to acquire
123 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
124 * will also specify which port we're acquiring the lock for.
126 s32
igb_acquire_swfw_sync_i210(struct e1000_hw
*hw
, u16 mask
)
130 u32 fwmask
= mask
<< 16;
131 s32 ret_val
= E1000_SUCCESS
;
132 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
134 while (i
< timeout
) {
135 if (igb_get_hw_semaphore_i210(hw
)) {
136 ret_val
= -E1000_ERR_SWFW_SYNC
;
140 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
141 if (!(swfw_sync
& fwmask
))
145 * Firmware currently using resource (fwmask)
147 igb_put_hw_semaphore_i210(hw
);
153 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
154 ret_val
= -E1000_ERR_SWFW_SYNC
;
159 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
161 igb_put_hw_semaphore_i210(hw
);
167 * igb_release_swfw_sync_i210 - Release SW/FW semaphore
168 * @hw: pointer to the HW structure
169 * @mask: specifies which semaphore to acquire
171 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
172 * will also specify which port we're releasing the lock for.
174 void igb_release_swfw_sync_i210(struct e1000_hw
*hw
, u16 mask
)
178 while (igb_get_hw_semaphore_i210(hw
) != E1000_SUCCESS
)
181 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
183 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
185 igb_put_hw_semaphore_i210(hw
);
189 * igb_read_nvm_srrd_i210 - Reads Shadow Ram using EERD register
190 * @hw: pointer to the HW structure
191 * @offset: offset of word in the Shadow Ram to read
192 * @words: number of words to read
193 * @data: word read from the Shadow Ram
195 * Reads a 16 bit word from the Shadow Ram using the EERD register.
196 * Uses necessary synchronization semaphores.
198 s32
igb_read_nvm_srrd_i210(struct e1000_hw
*hw
, u16 offset
, u16 words
,
201 s32 status
= E1000_SUCCESS
;
204 /* We cannot hold synchronization semaphores for too long,
205 * because of forceful takeover procedure. However it is more efficient
206 * to read in bursts than synchronizing access for each word. */
207 for (i
= 0; i
< words
; i
+= E1000_EERD_EEWR_MAX_COUNT
) {
208 count
= (words
- i
) / E1000_EERD_EEWR_MAX_COUNT
> 0 ?
209 E1000_EERD_EEWR_MAX_COUNT
: (words
- i
);
210 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
211 status
= igb_read_nvm_eerd(hw
, offset
, count
,
213 hw
->nvm
.ops
.release(hw
);
215 status
= E1000_ERR_SWFW_SYNC
;
218 if (status
!= E1000_SUCCESS
)
226 * igb_write_nvm_srwr - Write to Shadow Ram using EEWR
227 * @hw: pointer to the HW structure
228 * @offset: offset within the Shadow Ram to be written to
229 * @words: number of words to write
230 * @data: 16 bit word(s) to be written to the Shadow Ram
232 * Writes data to Shadow Ram at offset using EEWR register.
234 * If igb_update_nvm_checksum is not called after this function , the
235 * Shadow Ram will most likely contain an invalid checksum.
237 static s32
igb_write_nvm_srwr(struct e1000_hw
*hw
, u16 offset
, u16 words
,
240 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
242 u32 attempts
= 100000;
243 s32 ret_val
= E1000_SUCCESS
;
246 * A check for invalid values: offset too large, too many words,
247 * too many words for the offset, and not enough words.
249 if ((offset
>= nvm
->word_size
) || (words
> (nvm
->word_size
- offset
)) ||
251 hw_dbg("nvm parameter(s) out of bounds\n");
252 ret_val
= -E1000_ERR_NVM
;
256 for (i
= 0; i
< words
; i
++) {
257 eewr
= ((offset
+i
) << E1000_NVM_RW_ADDR_SHIFT
) |
258 (data
[i
] << E1000_NVM_RW_REG_DATA
) |
259 E1000_NVM_RW_REG_START
;
261 wr32(E1000_SRWR
, eewr
);
263 for (k
= 0; k
< attempts
; k
++) {
264 if (E1000_NVM_RW_REG_DONE
&
266 ret_val
= E1000_SUCCESS
;
272 if (ret_val
!= E1000_SUCCESS
) {
273 hw_dbg("Shadow RAM write EEWR timed out\n");
283 * igb_write_nvm_srwr_i210 - Write to Shadow RAM using EEWR
284 * @hw: pointer to the HW structure
285 * @offset: offset within the Shadow RAM to be written to
286 * @words: number of words to write
287 * @data: 16 bit word(s) to be written to the Shadow RAM
289 * Writes data to Shadow RAM at offset using EEWR register.
291 * If e1000_update_nvm_checksum is not called after this function , the
292 * data will not be committed to FLASH and also Shadow RAM will most likely
293 * contain an invalid checksum.
295 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
298 s32
igb_write_nvm_srwr_i210(struct e1000_hw
*hw
, u16 offset
, u16 words
,
301 s32 status
= E1000_SUCCESS
;
304 /* We cannot hold synchronization semaphores for too long,
305 * because of forceful takeover procedure. However it is more efficient
306 * to write in bursts than synchronizing access for each word.
308 for (i
= 0; i
< words
; i
+= E1000_EERD_EEWR_MAX_COUNT
) {
309 count
= (words
- i
) / E1000_EERD_EEWR_MAX_COUNT
> 0 ?
310 E1000_EERD_EEWR_MAX_COUNT
: (words
- i
);
311 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
312 status
= igb_write_nvm_srwr(hw
, offset
, count
,
314 hw
->nvm
.ops
.release(hw
);
316 status
= E1000_ERR_SWFW_SYNC
;
319 if (status
!= E1000_SUCCESS
)
327 * igb_read_nvm_i211 - Read NVM wrapper function for I211
328 * @hw: pointer to the HW structure
329 * @words: number of words to read
330 * @data: pointer to the data read
332 * Wrapper function to return data formerly found in the NVM.
334 s32
igb_read_nvm_i211(struct e1000_hw
*hw
, u16 offset
, u16 words
,
337 s32 ret_val
= E1000_SUCCESS
;
339 /* Only the MAC addr is required to be present in the iNVM */
342 ret_val
= igb_read_invm_i211(hw
, offset
, &data
[0]);
343 ret_val
|= igb_read_invm_i211(hw
, offset
+1, &data
[1]);
344 ret_val
|= igb_read_invm_i211(hw
, offset
+2, &data
[2]);
345 if (ret_val
!= E1000_SUCCESS
)
346 hw_dbg("MAC Addr not found in iNVM\n");
348 case NVM_INIT_CTRL_2
:
349 ret_val
= igb_read_invm_i211(hw
, (u8
)offset
, data
);
350 if (ret_val
!= E1000_SUCCESS
) {
351 *data
= NVM_INIT_CTRL_2_DEFAULT_I211
;
352 ret_val
= E1000_SUCCESS
;
355 case NVM_INIT_CTRL_4
:
356 ret_val
= igb_read_invm_i211(hw
, (u8
)offset
, data
);
357 if (ret_val
!= E1000_SUCCESS
) {
358 *data
= NVM_INIT_CTRL_4_DEFAULT_I211
;
359 ret_val
= E1000_SUCCESS
;
363 ret_val
= igb_read_invm_i211(hw
, (u8
)offset
, data
);
364 if (ret_val
!= E1000_SUCCESS
) {
365 *data
= NVM_LED_1_CFG_DEFAULT_I211
;
366 ret_val
= E1000_SUCCESS
;
369 case NVM_LED_0_2_CFG
:
370 igb_read_invm_i211(hw
, offset
, data
);
371 if (ret_val
!= E1000_SUCCESS
) {
372 *data
= NVM_LED_0_2_CFG_DEFAULT_I211
;
373 ret_val
= E1000_SUCCESS
;
376 case NVM_ID_LED_SETTINGS
:
377 ret_val
= igb_read_invm_i211(hw
, (u8
)offset
, data
);
378 if (ret_val
!= E1000_SUCCESS
) {
379 *data
= ID_LED_RESERVED_FFFF
;
380 ret_val
= E1000_SUCCESS
;
383 *data
= hw
->subsystem_device_id
;
386 *data
= hw
->subsystem_vendor_id
;
389 *data
= hw
->device_id
;
392 *data
= hw
->vendor_id
;
395 hw_dbg("NVM word 0x%02x is not mapped.\n", offset
);
396 *data
= NVM_RESERVED_WORD
;
403 * igb_read_invm_i211 - Reads OTP
404 * @hw: pointer to the HW structure
405 * @address: the word address (aka eeprom offset) to read
406 * @data: pointer to the data read
408 * Reads 16-bit words from the OTP. Return error when the word is not
411 s32
igb_read_invm_i211(struct e1000_hw
*hw
, u16 address
, u16
*data
)
413 s32 status
= -E1000_ERR_INVM_VALUE_NOT_FOUND
;
416 u8 record_type
, word_address
;
418 for (i
= 0; i
< E1000_INVM_SIZE
; i
++) {
419 invm_dword
= rd32(E1000_INVM_DATA_REG(i
));
420 /* Get record type */
421 record_type
= INVM_DWORD_TO_RECORD_TYPE(invm_dword
);
422 if (record_type
== E1000_INVM_UNINITIALIZED_STRUCTURE
)
424 if (record_type
== E1000_INVM_CSR_AUTOLOAD_STRUCTURE
)
425 i
+= E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS
;
426 if (record_type
== E1000_INVM_RSA_KEY_SHA256_STRUCTURE
)
427 i
+= E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS
;
428 if (record_type
== E1000_INVM_WORD_AUTOLOAD_STRUCTURE
) {
429 word_address
= INVM_DWORD_TO_WORD_ADDRESS(invm_dword
);
430 if (word_address
== (u8
)address
) {
431 *data
= INVM_DWORD_TO_WORD_DATA(invm_dword
);
432 hw_dbg("Read INVM Word 0x%02x = %x",
434 status
= E1000_SUCCESS
;
439 if (status
!= E1000_SUCCESS
)
440 hw_dbg("Requested word 0x%02x not found in OTP\n", address
);
445 * igb_read_invm_version - Reads iNVM version and image type
446 * @hw: pointer to the HW structure
447 * @invm_ver: version structure for the version read
449 * Reads iNVM version and image type.
451 s32
igb_read_invm_version(struct e1000_hw
*hw
,
452 struct e1000_fw_version
*invm_ver
) {
454 u32
*next_record
= NULL
;
457 u32 invm_blocks
= E1000_INVM_SIZE
- (E1000_INVM_ULT_BYTES_SIZE
/
458 E1000_INVM_RECORD_SIZE_IN_BYTES
);
459 u32 buffer
[E1000_INVM_SIZE
];
460 s32 status
= -E1000_ERR_INVM_VALUE_NOT_FOUND
;
463 /* Read iNVM memory */
464 for (i
= 0; i
< E1000_INVM_SIZE
; i
++) {
465 invm_dword
= rd32(E1000_INVM_DATA_REG(i
));
466 buffer
[i
] = invm_dword
;
469 /* Read version number */
470 for (i
= 1; i
< invm_blocks
; i
++) {
471 record
= &buffer
[invm_blocks
- i
];
472 next_record
= &buffer
[invm_blocks
- i
+ 1];
474 /* Check if we have first version location used */
475 if ((i
== 1) && ((*record
& E1000_INVM_VER_FIELD_ONE
) == 0)) {
477 status
= E1000_SUCCESS
;
480 /* Check if we have second version location used */
482 ((*record
& E1000_INVM_VER_FIELD_TWO
) == 0)) {
483 version
= (*record
& E1000_INVM_VER_FIELD_ONE
) >> 3;
484 status
= E1000_SUCCESS
;
487 /* Check if we have odd version location
488 * used and it is the last one used
490 else if ((((*record
& E1000_INVM_VER_FIELD_ONE
) == 0) &&
491 ((*record
& 0x3) == 0)) || (((*record
& 0x3) != 0) &&
493 version
= (*next_record
& E1000_INVM_VER_FIELD_TWO
)
495 status
= E1000_SUCCESS
;
498 /* Check if we have even version location
499 * used and it is the last one used
501 else if (((*record
& E1000_INVM_VER_FIELD_TWO
) == 0) &&
502 ((*record
& 0x3) == 0)) {
503 version
= (*record
& E1000_INVM_VER_FIELD_ONE
) >> 3;
504 status
= E1000_SUCCESS
;
509 if (status
== E1000_SUCCESS
) {
510 invm_ver
->invm_major
= (version
& E1000_INVM_MAJOR_MASK
)
511 >> E1000_INVM_MAJOR_SHIFT
;
512 invm_ver
->invm_minor
= version
& E1000_INVM_MINOR_MASK
;
514 /* Read Image Type */
515 for (i
= 1; i
< invm_blocks
; i
++) {
516 record
= &buffer
[invm_blocks
- i
];
517 next_record
= &buffer
[invm_blocks
- i
+ 1];
519 /* Check if we have image type in first location used */
520 if ((i
== 1) && ((*record
& E1000_INVM_IMGTYPE_FIELD
) == 0)) {
521 invm_ver
->invm_img_type
= 0;
522 status
= E1000_SUCCESS
;
525 /* Check if we have image type in first location used */
526 else if ((((*record
& 0x3) == 0) &&
527 ((*record
& E1000_INVM_IMGTYPE_FIELD
) == 0)) ||
528 ((((*record
& 0x3) != 0) && (i
!= 1)))) {
529 invm_ver
->invm_img_type
=
530 (*next_record
& E1000_INVM_IMGTYPE_FIELD
) >> 23;
531 status
= E1000_SUCCESS
;
539 * igb_validate_nvm_checksum_i210 - Validate EEPROM checksum
540 * @hw: pointer to the HW structure
542 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
543 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
545 s32
igb_validate_nvm_checksum_i210(struct e1000_hw
*hw
)
547 s32 status
= E1000_SUCCESS
;
548 s32 (*read_op_ptr
)(struct e1000_hw
*, u16
, u16
, u16
*);
550 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
553 * Replace the read function with semaphore grabbing with
554 * the one that skips this for a while.
555 * We have semaphore taken already here.
557 read_op_ptr
= hw
->nvm
.ops
.read
;
558 hw
->nvm
.ops
.read
= igb_read_nvm_eerd
;
560 status
= igb_validate_nvm_checksum(hw
);
562 /* Revert original read operation. */
563 hw
->nvm
.ops
.read
= read_op_ptr
;
565 hw
->nvm
.ops
.release(hw
);
567 status
= E1000_ERR_SWFW_SYNC
;
575 * igb_update_nvm_checksum_i210 - Update EEPROM checksum
576 * @hw: pointer to the HW structure
578 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
579 * up to the checksum. Then calculates the EEPROM checksum and writes the
580 * value to the EEPROM. Next commit EEPROM data onto the Flash.
582 s32
igb_update_nvm_checksum_i210(struct e1000_hw
*hw
)
584 s32 ret_val
= E1000_SUCCESS
;
589 * Read the first word from the EEPROM. If this times out or fails, do
590 * not continue or we could be in for a very long wait while every
593 ret_val
= igb_read_nvm_eerd(hw
, 0, 1, &nvm_data
);
594 if (ret_val
!= E1000_SUCCESS
) {
595 hw_dbg("EEPROM read failed\n");
599 if (hw
->nvm
.ops
.acquire(hw
) == E1000_SUCCESS
) {
601 * Do not use hw->nvm.ops.write, hw->nvm.ops.read
602 * because we do not want to take the synchronization
603 * semaphores twice here.
606 for (i
= 0; i
< NVM_CHECKSUM_REG
; i
++) {
607 ret_val
= igb_read_nvm_eerd(hw
, i
, 1, &nvm_data
);
609 hw
->nvm
.ops
.release(hw
);
610 hw_dbg("NVM Read Error while updating checksum.\n");
613 checksum
+= nvm_data
;
615 checksum
= (u16
) NVM_SUM
- checksum
;
616 ret_val
= igb_write_nvm_srwr(hw
, NVM_CHECKSUM_REG
, 1,
618 if (ret_val
!= E1000_SUCCESS
) {
619 hw
->nvm
.ops
.release(hw
);
620 hw_dbg("NVM Write Error while updating checksum.\n");
624 hw
->nvm
.ops
.release(hw
);
626 ret_val
= igb_update_flash_i210(hw
);
628 ret_val
= -E1000_ERR_SWFW_SYNC
;
635 * igb_pool_flash_update_done_i210 - Pool FLUDONE status.
636 * @hw: pointer to the HW structure
639 static s32
igb_pool_flash_update_done_i210(struct e1000_hw
*hw
)
641 s32 ret_val
= -E1000_ERR_NVM
;
644 for (i
= 0; i
< E1000_FLUDONE_ATTEMPTS
; i
++) {
645 reg
= rd32(E1000_EECD
);
646 if (reg
& E1000_EECD_FLUDONE_I210
) {
647 ret_val
= E1000_SUCCESS
;
657 * igb_update_flash_i210 - Commit EEPROM to the flash
658 * @hw: pointer to the HW structure
661 s32
igb_update_flash_i210(struct e1000_hw
*hw
)
663 s32 ret_val
= E1000_SUCCESS
;
666 ret_val
= igb_pool_flash_update_done_i210(hw
);
667 if (ret_val
== -E1000_ERR_NVM
) {
668 hw_dbg("Flash update time out\n");
672 flup
= rd32(E1000_EECD
) | E1000_EECD_FLUPD_I210
;
673 wr32(E1000_EECD
, flup
);
675 ret_val
= igb_pool_flash_update_done_i210(hw
);
676 if (ret_val
== E1000_SUCCESS
)
677 hw_dbg("Flash update complete\n");
679 hw_dbg("Flash update time out\n");
686 * igb_valid_led_default_i210 - Verify a valid default LED config
687 * @hw: pointer to the HW structure
688 * @data: pointer to the NVM (EEPROM)
690 * Read the EEPROM for the current default LED configuration. If the
691 * LED configuration is not valid, set to a valid LED configuration.
693 s32
igb_valid_led_default_i210(struct e1000_hw
*hw
, u16
*data
)
697 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
699 hw_dbg("NVM Read Error\n");
703 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
) {
704 switch (hw
->phy
.media_type
) {
705 case e1000_media_type_internal_serdes
:
706 *data
= ID_LED_DEFAULT_I210_SERDES
;
708 case e1000_media_type_copper
:
710 *data
= ID_LED_DEFAULT_I210
;