1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2014 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, see <http://www.gnu.org/licenses/>.
18 The full GNU General Public License is included in this distribution in
19 the file called "COPYING".
22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *******************************************************************************/
27 #include <linux/if_ether.h>
28 #include <linux/delay.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
33 #include "e1000_mac.h"
37 static s32
igb_set_default_fc(struct e1000_hw
*hw
);
38 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
);
41 * igb_get_bus_info_pcie - Get PCIe bus information
42 * @hw: pointer to the HW structure
44 * Determines and stores the system bus information for a particular
45 * network interface. The following bus information is determined and stored:
46 * bus speed, bus width, type (PCIe), and PCIe function.
48 s32
igb_get_bus_info_pcie(struct e1000_hw
*hw
)
50 struct e1000_bus_info
*bus
= &hw
->bus
;
55 bus
->type
= e1000_bus_type_pci_express
;
57 ret_val
= igb_read_pcie_cap_reg(hw
,
61 bus
->width
= e1000_bus_width_unknown
;
62 bus
->speed
= e1000_bus_speed_unknown
;
64 switch (pcie_link_status
& PCI_EXP_LNKSTA_CLS
) {
65 case PCI_EXP_LNKSTA_CLS_2_5GB
:
66 bus
->speed
= e1000_bus_speed_2500
;
68 case PCI_EXP_LNKSTA_CLS_5_0GB
:
69 bus
->speed
= e1000_bus_speed_5000
;
72 bus
->speed
= e1000_bus_speed_unknown
;
76 bus
->width
= (enum e1000_bus_width
)((pcie_link_status
&
77 PCI_EXP_LNKSTA_NLW
) >>
78 PCI_EXP_LNKSTA_NLW_SHIFT
);
81 reg
= rd32(E1000_STATUS
);
82 bus
->func
= (reg
& E1000_STATUS_FUNC_MASK
) >> E1000_STATUS_FUNC_SHIFT
;
88 * igb_clear_vfta - Clear VLAN filter table
89 * @hw: pointer to the HW structure
91 * Clears the register array which contains the VLAN filter table by
92 * setting all the values to 0.
94 void igb_clear_vfta(struct e1000_hw
*hw
)
98 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
99 array_wr32(E1000_VFTA
, offset
, 0);
105 * igb_write_vfta - Write value to VLAN filter table
106 * @hw: pointer to the HW structure
107 * @offset: register offset in VLAN filter table
108 * @value: register value written to VLAN filter table
110 * Writes value at the given offset in the register array which stores
111 * the VLAN filter table.
113 static void igb_write_vfta(struct e1000_hw
*hw
, u32 offset
, u32 value
)
115 array_wr32(E1000_VFTA
, offset
, value
);
119 /* Due to a hw errata, if the host tries to configure the VFTA register
120 * while performing queries from the BMC or DMA, then the VFTA in some
121 * cases won't be written.
125 * igb_clear_vfta_i350 - Clear VLAN filter table
126 * @hw: pointer to the HW structure
128 * Clears the register array which contains the VLAN filter table by
129 * setting all the values to 0.
131 void igb_clear_vfta_i350(struct e1000_hw
*hw
)
136 for (offset
= 0; offset
< E1000_VLAN_FILTER_TBL_SIZE
; offset
++) {
137 for (i
= 0; i
< 10; i
++)
138 array_wr32(E1000_VFTA
, offset
, 0);
145 * igb_write_vfta_i350 - Write value to VLAN filter table
146 * @hw: pointer to the HW structure
147 * @offset: register offset in VLAN filter table
148 * @value: register value written to VLAN filter table
150 * Writes value at the given offset in the register array which stores
151 * the VLAN filter table.
153 static void igb_write_vfta_i350(struct e1000_hw
*hw
, u32 offset
, u32 value
)
157 for (i
= 0; i
< 10; i
++)
158 array_wr32(E1000_VFTA
, offset
, value
);
164 * igb_init_rx_addrs - Initialize receive address's
165 * @hw: pointer to the HW structure
166 * @rar_count: receive address registers
168 * Setups the receive address registers by setting the base receive address
169 * register to the devices MAC address and clearing all the other receive
170 * address registers to 0.
172 void igb_init_rx_addrs(struct e1000_hw
*hw
, u16 rar_count
)
175 u8 mac_addr
[ETH_ALEN
] = {0};
177 /* Setup the receive address */
178 hw_dbg("Programming MAC Address into RAR[0]\n");
180 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.addr
, 0);
182 /* Zero out the other (rar_entry_count - 1) receive addresses */
183 hw_dbg("Clearing RAR[1-%u]\n", rar_count
-1);
184 for (i
= 1; i
< rar_count
; i
++)
185 hw
->mac
.ops
.rar_set(hw
, mac_addr
, i
);
189 * igb_vfta_set - enable or disable vlan in VLAN filter table
190 * @hw: pointer to the HW structure
191 * @vid: VLAN id to add or remove
192 * @add: if true add filter, if false remove
194 * Sets or clears a bit in the VLAN filter table array based on VLAN id
195 * and if we are adding or removing the filter
197 s32
igb_vfta_set(struct e1000_hw
*hw
, u32 vid
, bool add
)
199 u32 index
= (vid
>> E1000_VFTA_ENTRY_SHIFT
) & E1000_VFTA_ENTRY_MASK
;
200 u32 mask
= 1 << (vid
& E1000_VFTA_ENTRY_BIT_SHIFT_MASK
);
202 struct igb_adapter
*adapter
= hw
->back
;
205 vfta
= adapter
->shadow_vfta
[index
];
207 /* bit was set/cleared before we started */
208 if ((!!(vfta
& mask
)) == add
) {
209 ret_val
= -E1000_ERR_CONFIG
;
216 if ((hw
->mac
.type
== e1000_i350
) || (hw
->mac
.type
== e1000_i354
))
217 igb_write_vfta_i350(hw
, index
, vfta
);
219 igb_write_vfta(hw
, index
, vfta
);
220 adapter
->shadow_vfta
[index
] = vfta
;
226 * igb_check_alt_mac_addr - Check for alternate MAC addr
227 * @hw: pointer to the HW structure
229 * Checks the nvm for an alternate MAC address. An alternate MAC address
230 * can be setup by pre-boot software and must be treated like a permanent
231 * address and must override the actual permanent MAC address. If an
232 * alternate MAC address is found it is saved in the hw struct and
233 * programmed into RAR0 and the function returns success, otherwise the
234 * function returns an error.
236 s32
igb_check_alt_mac_addr(struct e1000_hw
*hw
)
240 u16 offset
, nvm_alt_mac_addr_offset
, nvm_data
;
241 u8 alt_mac_addr
[ETH_ALEN
];
243 /* Alternate MAC address is handled by the option ROM for 82580
244 * and newer. SW support not required.
246 if (hw
->mac
.type
>= e1000_82580
)
249 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ALT_MAC_ADDR_PTR
, 1,
250 &nvm_alt_mac_addr_offset
);
252 hw_dbg("NVM Read Error\n");
256 if ((nvm_alt_mac_addr_offset
== 0xFFFF) ||
257 (nvm_alt_mac_addr_offset
== 0x0000))
258 /* There is no Alternate MAC Address */
261 if (hw
->bus
.func
== E1000_FUNC_1
)
262 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN1
;
263 if (hw
->bus
.func
== E1000_FUNC_2
)
264 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN2
;
266 if (hw
->bus
.func
== E1000_FUNC_3
)
267 nvm_alt_mac_addr_offset
+= E1000_ALT_MAC_ADDRESS_OFFSET_LAN3
;
268 for (i
= 0; i
< ETH_ALEN
; i
+= 2) {
269 offset
= nvm_alt_mac_addr_offset
+ (i
>> 1);
270 ret_val
= hw
->nvm
.ops
.read(hw
, offset
, 1, &nvm_data
);
272 hw_dbg("NVM Read Error\n");
276 alt_mac_addr
[i
] = (u8
)(nvm_data
& 0xFF);
277 alt_mac_addr
[i
+ 1] = (u8
)(nvm_data
>> 8);
280 /* if multicast bit is set, the alternate address will not be used */
281 if (is_multicast_ether_addr(alt_mac_addr
)) {
282 hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
286 /* We have a valid alternate MAC address, and we want to treat it the
287 * same as the normal permanent MAC address stored by the HW into the
288 * RAR. Do this by mapping this address into RAR0.
290 hw
->mac
.ops
.rar_set(hw
, alt_mac_addr
, 0);
297 * igb_rar_set - Set receive address register
298 * @hw: pointer to the HW structure
299 * @addr: pointer to the receive address
300 * @index: receive address array register
302 * Sets the receive address array register at index to the address passed
305 void igb_rar_set(struct e1000_hw
*hw
, u8
*addr
, u32 index
)
307 u32 rar_low
, rar_high
;
309 /* HW expects these in little endian so we reverse the byte order
310 * from network order (big endian) to little endian
312 rar_low
= ((u32
) addr
[0] |
313 ((u32
) addr
[1] << 8) |
314 ((u32
) addr
[2] << 16) | ((u32
) addr
[3] << 24));
316 rar_high
= ((u32
) addr
[4] | ((u32
) addr
[5] << 8));
318 /* If MAC address zero, no need to set the AV bit */
319 if (rar_low
|| rar_high
)
320 rar_high
|= E1000_RAH_AV
;
322 /* Some bridges will combine consecutive 32-bit writes into
323 * a single burst write, which will malfunction on some parts.
324 * The flushes avoid this.
326 wr32(E1000_RAL(index
), rar_low
);
328 wr32(E1000_RAH(index
), rar_high
);
333 * igb_mta_set - Set multicast filter table address
334 * @hw: pointer to the HW structure
335 * @hash_value: determines the MTA register and bit to set
337 * The multicast table address is a register array of 32-bit registers.
338 * The hash_value is used to determine what register the bit is in, the
339 * current value is read, the new bit is OR'd in and the new value is
340 * written back into the register.
342 void igb_mta_set(struct e1000_hw
*hw
, u32 hash_value
)
344 u32 hash_bit
, hash_reg
, mta
;
346 /* The MTA is a register array of 32-bit registers. It is
347 * treated like an array of (32*mta_reg_count) bits. We want to
348 * set bit BitArray[hash_value]. So we figure out what register
349 * the bit is in, read it, OR in the new bit, then write
350 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
351 * mask to bits 31:5 of the hash value which gives us the
352 * register we're modifying. The hash bit within that register
353 * is determined by the lower 5 bits of the hash value.
355 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
356 hash_bit
= hash_value
& 0x1F;
358 mta
= array_rd32(E1000_MTA
, hash_reg
);
360 mta
|= (1 << hash_bit
);
362 array_wr32(E1000_MTA
, hash_reg
, mta
);
367 * igb_hash_mc_addr - Generate a multicast hash value
368 * @hw: pointer to the HW structure
369 * @mc_addr: pointer to a multicast address
371 * Generates a multicast address hash value which is used to determine
372 * the multicast filter table array address and new table value. See
375 static u32
igb_hash_mc_addr(struct e1000_hw
*hw
, u8
*mc_addr
)
377 u32 hash_value
, hash_mask
;
380 /* Register count multiplied by bits per register */
381 hash_mask
= (hw
->mac
.mta_reg_count
* 32) - 1;
383 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
384 * where 0xFF would still fall within the hash mask.
386 while (hash_mask
>> bit_shift
!= 0xFF)
389 /* The portion of the address that is used for the hash table
390 * is determined by the mc_filter_type setting.
391 * The algorithm is such that there is a total of 8 bits of shifting.
392 * The bit_shift for a mc_filter_type of 0 represents the number of
393 * left-shifts where the MSB of mc_addr[5] would still fall within
394 * the hash_mask. Case 0 does this exactly. Since there are a total
395 * of 8 bits of shifting, then mc_addr[4] will shift right the
396 * remaining number of bits. Thus 8 - bit_shift. The rest of the
397 * cases are a variation of this algorithm...essentially raising the
398 * number of bits to shift mc_addr[5] left, while still keeping the
399 * 8-bit shifting total.
401 * For example, given the following Destination MAC Address and an
402 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
403 * we can see that the bit_shift for case 0 is 4. These are the hash
404 * values resulting from each mc_filter_type...
405 * [0] [1] [2] [3] [4] [5]
409 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
410 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
411 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
412 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
414 switch (hw
->mac
.mc_filter_type
) {
429 hash_value
= hash_mask
& (((mc_addr
[4] >> (8 - bit_shift
)) |
430 (((u16
) mc_addr
[5]) << bit_shift
)));
436 * igb_update_mc_addr_list - Update Multicast addresses
437 * @hw: pointer to the HW structure
438 * @mc_addr_list: array of multicast addresses to program
439 * @mc_addr_count: number of multicast addresses to program
441 * Updates entire Multicast Table Array.
442 * The caller must have a packed mc_addr_list of multicast addresses.
444 void igb_update_mc_addr_list(struct e1000_hw
*hw
,
445 u8
*mc_addr_list
, u32 mc_addr_count
)
447 u32 hash_value
, hash_bit
, hash_reg
;
450 /* clear mta_shadow */
451 memset(&hw
->mac
.mta_shadow
, 0, sizeof(hw
->mac
.mta_shadow
));
453 /* update mta_shadow from mc_addr_list */
454 for (i
= 0; (u32
) i
< mc_addr_count
; i
++) {
455 hash_value
= igb_hash_mc_addr(hw
, mc_addr_list
);
457 hash_reg
= (hash_value
>> 5) & (hw
->mac
.mta_reg_count
- 1);
458 hash_bit
= hash_value
& 0x1F;
460 hw
->mac
.mta_shadow
[hash_reg
] |= (1 << hash_bit
);
461 mc_addr_list
+= (ETH_ALEN
);
464 /* replace the entire MTA table */
465 for (i
= hw
->mac
.mta_reg_count
- 1; i
>= 0; i
--)
466 array_wr32(E1000_MTA
, i
, hw
->mac
.mta_shadow
[i
]);
471 * igb_clear_hw_cntrs_base - Clear base hardware counters
472 * @hw: pointer to the HW structure
474 * Clears the base hardware counters by reading the counter registers.
476 void igb_clear_hw_cntrs_base(struct e1000_hw
*hw
)
518 * igb_check_for_copper_link - Check for link (Copper)
519 * @hw: pointer to the HW structure
521 * Checks to see of the link status of the hardware has changed. If a
522 * change in link status has been detected, then we read the PHY registers
523 * to get the current speed/duplex if link exists.
525 s32
igb_check_for_copper_link(struct e1000_hw
*hw
)
527 struct e1000_mac_info
*mac
= &hw
->mac
;
531 /* We only want to go out to the PHY registers to see if Auto-Neg
532 * has completed and/or if our link status has changed. The
533 * get_link_status flag is set upon receiving a Link Status
534 * Change or Rx Sequence Error interrupt.
536 if (!mac
->get_link_status
) {
541 /* First we want to see if the MII Status Register reports
542 * link. If so, then we want to get the current speed/duplex
545 ret_val
= igb_phy_has_link(hw
, 1, 0, &link
);
550 goto out
; /* No link detected */
552 mac
->get_link_status
= false;
554 /* Check if there was DownShift, must be checked
555 * immediately after link-up
557 igb_check_downshift(hw
);
559 /* If we are forcing speed/duplex, then we simply return since
560 * we have already determined whether we have link or not.
563 ret_val
= -E1000_ERR_CONFIG
;
567 /* Auto-Neg is enabled. Auto Speed Detection takes care
568 * of MAC speed/duplex configuration. So we only need to
569 * configure Collision Distance in the MAC.
571 igb_config_collision_dist(hw
);
573 /* Configure Flow Control now that Auto-Neg has completed.
574 * First, we need to restore the desired flow control
575 * settings because we may have had to re-autoneg with a
576 * different link partner.
578 ret_val
= igb_config_fc_after_link_up(hw
);
580 hw_dbg("Error configuring flow control\n");
587 * igb_setup_link - Setup flow control and link settings
588 * @hw: pointer to the HW structure
590 * Determines which flow control settings to use, then configures flow
591 * control. Calls the appropriate media-specific link configuration
592 * function. Assuming the adapter has a valid link partner, a valid link
593 * should be established. Assumes the hardware has previously been reset
594 * and the transmitter and receiver are not enabled.
596 s32
igb_setup_link(struct e1000_hw
*hw
)
600 /* In the case of the phy reset being blocked, we already have a link.
601 * We do not need to set it up again.
603 if (igb_check_reset_block(hw
))
606 /* If requested flow control is set to default, set flow control
607 * based on the EEPROM flow control settings.
609 if (hw
->fc
.requested_mode
== e1000_fc_default
) {
610 ret_val
= igb_set_default_fc(hw
);
615 /* We want to save off the original Flow Control configuration just
616 * in case we get disconnected and then reconnected into a different
617 * hub or switch with different Flow Control capabilities.
619 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
621 hw_dbg("After fix-ups FlowControl is now = %x\n", hw
->fc
.current_mode
);
623 /* Call the necessary media_type subroutine to configure the link. */
624 ret_val
= hw
->mac
.ops
.setup_physical_interface(hw
);
628 /* Initialize the flow control address, type, and PAUSE timer
629 * registers to their default values. This is done even if flow
630 * control is disabled, because it does not hurt anything to
631 * initialize these registers.
633 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
634 wr32(E1000_FCT
, FLOW_CONTROL_TYPE
);
635 wr32(E1000_FCAH
, FLOW_CONTROL_ADDRESS_HIGH
);
636 wr32(E1000_FCAL
, FLOW_CONTROL_ADDRESS_LOW
);
638 wr32(E1000_FCTTV
, hw
->fc
.pause_time
);
640 ret_val
= igb_set_fc_watermarks(hw
);
648 * igb_config_collision_dist - Configure collision distance
649 * @hw: pointer to the HW structure
651 * Configures the collision distance to the default value and is used
652 * during link setup. Currently no func pointer exists and all
653 * implementations are handled in the generic version of this function.
655 void igb_config_collision_dist(struct e1000_hw
*hw
)
659 tctl
= rd32(E1000_TCTL
);
661 tctl
&= ~E1000_TCTL_COLD
;
662 tctl
|= E1000_COLLISION_DISTANCE
<< E1000_COLD_SHIFT
;
664 wr32(E1000_TCTL
, tctl
);
669 * igb_set_fc_watermarks - Set flow control high/low watermarks
670 * @hw: pointer to the HW structure
672 * Sets the flow control high/low threshold (watermark) registers. If
673 * flow control XON frame transmission is enabled, then set XON frame
674 * tansmission as well.
676 static s32
igb_set_fc_watermarks(struct e1000_hw
*hw
)
679 u32 fcrtl
= 0, fcrth
= 0;
681 /* Set the flow control receive threshold registers. Normally,
682 * these registers will be set to a default threshold that may be
683 * adjusted later by the driver's runtime code. However, if the
684 * ability to transmit pause frames is not enabled, then these
685 * registers will be set to 0.
687 if (hw
->fc
.current_mode
& e1000_fc_tx_pause
) {
688 /* We need to set up the Receive Threshold high and low water
689 * marks as well as (optionally) enabling the transmission of
692 fcrtl
= hw
->fc
.low_water
;
694 fcrtl
|= E1000_FCRTL_XONE
;
696 fcrth
= hw
->fc
.high_water
;
698 wr32(E1000_FCRTL
, fcrtl
);
699 wr32(E1000_FCRTH
, fcrth
);
705 * igb_set_default_fc - Set flow control default values
706 * @hw: pointer to the HW structure
708 * Read the EEPROM for the default values for flow control and store the
711 static s32
igb_set_default_fc(struct e1000_hw
*hw
)
717 /* Read and store word 0x0F of the EEPROM. This word contains bits
718 * that determine the hardware's default PAUSE (flow control) mode,
719 * a bit that determines whether the HW defaults to enabling or
720 * disabling auto-negotiation, and the direction of the
721 * SW defined pins. If there is no SW over-ride of the flow
722 * control setting, then the variable hw->fc will
723 * be initialized based on a value in the EEPROM.
725 if (hw
->mac
.type
== e1000_i350
) {
726 lan_offset
= NVM_82580_LAN_FUNC_OFFSET(hw
->bus
.func
);
727 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL2_REG
728 + lan_offset
, 1, &nvm_data
);
730 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_INIT_CONTROL2_REG
,
735 hw_dbg("NVM Read Error\n");
739 if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) == 0)
740 hw
->fc
.requested_mode
= e1000_fc_none
;
741 else if ((nvm_data
& NVM_WORD0F_PAUSE_MASK
) ==
743 hw
->fc
.requested_mode
= e1000_fc_tx_pause
;
745 hw
->fc
.requested_mode
= e1000_fc_full
;
752 * igb_force_mac_fc - Force the MAC's flow control settings
753 * @hw: pointer to the HW structure
755 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
756 * device control register to reflect the adapter settings. TFCE and RFCE
757 * need to be explicitly set by software when a copper PHY is used because
758 * autonegotiation is managed by the PHY rather than the MAC. Software must
759 * also configure these bits when link is forced on a fiber connection.
761 s32
igb_force_mac_fc(struct e1000_hw
*hw
)
766 ctrl
= rd32(E1000_CTRL
);
768 /* Because we didn't get link via the internal auto-negotiation
769 * mechanism (we either forced link or we got link via PHY
770 * auto-neg), we have to manually enable/disable transmit an
771 * receive flow control.
773 * The "Case" statement below enables/disable flow control
774 * according to the "hw->fc.current_mode" parameter.
776 * The possible values of the "fc" parameter are:
777 * 0: Flow control is completely disabled
778 * 1: Rx flow control is enabled (we can receive pause
779 * frames but not send pause frames).
780 * 2: Tx flow control is enabled (we can send pause frames
781 * frames but we do not receive pause frames).
782 * 3: Both Rx and TX flow control (symmetric) is enabled.
783 * other: No other values should be possible at this point.
785 hw_dbg("hw->fc.current_mode = %u\n", hw
->fc
.current_mode
);
787 switch (hw
->fc
.current_mode
) {
789 ctrl
&= (~(E1000_CTRL_TFCE
| E1000_CTRL_RFCE
));
791 case e1000_fc_rx_pause
:
792 ctrl
&= (~E1000_CTRL_TFCE
);
793 ctrl
|= E1000_CTRL_RFCE
;
795 case e1000_fc_tx_pause
:
796 ctrl
&= (~E1000_CTRL_RFCE
);
797 ctrl
|= E1000_CTRL_TFCE
;
800 ctrl
|= (E1000_CTRL_TFCE
| E1000_CTRL_RFCE
);
803 hw_dbg("Flow control param set incorrectly\n");
804 ret_val
= -E1000_ERR_CONFIG
;
808 wr32(E1000_CTRL
, ctrl
);
815 * igb_config_fc_after_link_up - Configures flow control after link
816 * @hw: pointer to the HW structure
818 * Checks the status of auto-negotiation after link up to ensure that the
819 * speed and duplex were not forced. If the link needed to be forced, then
820 * flow control needs to be forced also. If auto-negotiation is enabled
821 * and did not fail, then we configure flow control based on our link
824 s32
igb_config_fc_after_link_up(struct e1000_hw
*hw
)
826 struct e1000_mac_info
*mac
= &hw
->mac
;
828 u32 pcs_status_reg
, pcs_adv_reg
, pcs_lp_ability_reg
, pcs_ctrl_reg
;
829 u16 mii_status_reg
, mii_nway_adv_reg
, mii_nway_lp_ability_reg
;
832 /* Check for the case where we have fiber media and auto-neg failed
833 * so we had to force link. In this case, we need to force the
834 * configuration of the MAC to match the "fc" parameter.
836 if (mac
->autoneg_failed
) {
837 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
838 ret_val
= igb_force_mac_fc(hw
);
840 if (hw
->phy
.media_type
== e1000_media_type_copper
)
841 ret_val
= igb_force_mac_fc(hw
);
845 hw_dbg("Error forcing flow control settings\n");
849 /* Check for the case where we have copper media and auto-neg is
850 * enabled. In this case, we need to check and see if Auto-Neg
851 * has completed, and if so, how the PHY and link partner has
852 * flow control configured.
854 if ((hw
->phy
.media_type
== e1000_media_type_copper
) && mac
->autoneg
) {
855 /* Read the MII Status Register and check to see if AutoNeg
856 * has completed. We read this twice because this reg has
857 * some "sticky" (latched) bits.
859 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
863 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_STATUS
,
868 if (!(mii_status_reg
& MII_SR_AUTONEG_COMPLETE
)) {
869 hw_dbg("Copper PHY and Auto Neg "
870 "has not completed.\n");
874 /* The AutoNeg process has completed, so we now need to
875 * read both the Auto Negotiation Advertisement
876 * Register (Address 4) and the Auto_Negotiation Base
877 * Page Ability Register (Address 5) to determine how
878 * flow control was negotiated.
880 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_AUTONEG_ADV
,
884 ret_val
= hw
->phy
.ops
.read_reg(hw
, PHY_LP_ABILITY
,
885 &mii_nway_lp_ability_reg
);
889 /* Two bits in the Auto Negotiation Advertisement Register
890 * (Address 4) and two bits in the Auto Negotiation Base
891 * Page Ability Register (Address 5) determine flow control
892 * for both the PHY and the link partner. The following
893 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
894 * 1999, describes these PAUSE resolution bits and how flow
895 * control is determined based upon these settings.
896 * NOTE: DC = Don't Care
898 * LOCAL DEVICE | LINK PARTNER
899 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
900 *-------|---------|-------|---------|--------------------
901 * 0 | 0 | DC | DC | e1000_fc_none
902 * 0 | 1 | 0 | DC | e1000_fc_none
903 * 0 | 1 | 1 | 0 | e1000_fc_none
904 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
905 * 1 | 0 | 0 | DC | e1000_fc_none
906 * 1 | DC | 1 | DC | e1000_fc_full
907 * 1 | 1 | 0 | 0 | e1000_fc_none
908 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
910 * Are both PAUSE bits set to 1? If so, this implies
911 * Symmetric Flow Control is enabled at both ends. The
912 * ASM_DIR bits are irrelevant per the spec.
914 * For Symmetric Flow Control:
916 * LOCAL DEVICE | LINK PARTNER
917 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
918 *-------|---------|-------|---------|--------------------
919 * 1 | DC | 1 | DC | E1000_fc_full
922 if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
923 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
)) {
924 /* Now we need to check if the user selected RX ONLY
925 * of pause frames. In this case, we had to advertise
926 * FULL flow control because we could not advertise RX
927 * ONLY. Hence, we must now check to see if we need to
928 * turn OFF the TRANSMISSION of PAUSE frames.
930 if (hw
->fc
.requested_mode
== e1000_fc_full
) {
931 hw
->fc
.current_mode
= e1000_fc_full
;
932 hw_dbg("Flow Control = FULL.\n");
934 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
935 hw_dbg("Flow Control = RX PAUSE frames only.\n");
938 /* For receiving PAUSE frames ONLY.
940 * LOCAL DEVICE | LINK PARTNER
941 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
942 *-------|---------|-------|---------|--------------------
943 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
945 else if (!(mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
946 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
947 (mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
948 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
949 hw
->fc
.current_mode
= e1000_fc_tx_pause
;
950 hw_dbg("Flow Control = TX PAUSE frames only.\n");
952 /* For transmitting PAUSE frames ONLY.
954 * LOCAL DEVICE | LINK PARTNER
955 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
956 *-------|---------|-------|---------|--------------------
957 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
959 else if ((mii_nway_adv_reg
& NWAY_AR_PAUSE
) &&
960 (mii_nway_adv_reg
& NWAY_AR_ASM_DIR
) &&
961 !(mii_nway_lp_ability_reg
& NWAY_LPAR_PAUSE
) &&
962 (mii_nway_lp_ability_reg
& NWAY_LPAR_ASM_DIR
)) {
963 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
964 hw_dbg("Flow Control = RX PAUSE frames only.\n");
966 /* Per the IEEE spec, at this point flow control should be
967 * disabled. However, we want to consider that we could
968 * be connected to a legacy switch that doesn't advertise
969 * desired flow control, but can be forced on the link
970 * partner. So if we advertised no flow control, that is
971 * what we will resolve to. If we advertised some kind of
972 * receive capability (Rx Pause Only or Full Flow Control)
973 * and the link partner advertised none, we will configure
974 * ourselves to enable Rx Flow Control only. We can do
975 * this safely for two reasons: If the link partner really
976 * didn't want flow control enabled, and we enable Rx, no
977 * harm done since we won't be receiving any PAUSE frames
978 * anyway. If the intent on the link partner was to have
979 * flow control enabled, then by us enabling RX only, we
980 * can at least receive pause frames and process them.
981 * This is a good idea because in most cases, since we are
982 * predominantly a server NIC, more times than not we will
983 * be asked to delay transmission of packets than asking
984 * our link partner to pause transmission of frames.
986 else if ((hw
->fc
.requested_mode
== e1000_fc_none
) ||
987 (hw
->fc
.requested_mode
== e1000_fc_tx_pause
) ||
988 (hw
->fc
.strict_ieee
)) {
989 hw
->fc
.current_mode
= e1000_fc_none
;
990 hw_dbg("Flow Control = NONE.\n");
992 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
993 hw_dbg("Flow Control = RX PAUSE frames only.\n");
996 /* Now we need to do one last check... If we auto-
997 * negotiated to HALF DUPLEX, flow control should not be
998 * enabled per IEEE 802.3 spec.
1000 ret_val
= hw
->mac
.ops
.get_speed_and_duplex(hw
, &speed
, &duplex
);
1002 hw_dbg("Error getting link speed and duplex\n");
1006 if (duplex
== HALF_DUPLEX
)
1007 hw
->fc
.current_mode
= e1000_fc_none
;
1009 /* Now we call a subroutine to actually force the MAC
1010 * controller to use the correct flow control settings.
1012 ret_val
= igb_force_mac_fc(hw
);
1014 hw_dbg("Error forcing flow control settings\n");
1018 /* Check for the case where we have SerDes media and auto-neg is
1019 * enabled. In this case, we need to check and see if Auto-Neg
1020 * has completed, and if so, how the PHY and link partner has
1021 * flow control configured.
1023 if ((hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
1025 /* Read the PCS_LSTS and check to see if AutoNeg
1028 pcs_status_reg
= rd32(E1000_PCS_LSTAT
);
1030 if (!(pcs_status_reg
& E1000_PCS_LSTS_AN_COMPLETE
)) {
1031 hw_dbg("PCS Auto Neg has not completed.\n");
1035 /* The AutoNeg process has completed, so we now need to
1036 * read both the Auto Negotiation Advertisement
1037 * Register (PCS_ANADV) and the Auto_Negotiation Base
1038 * Page Ability Register (PCS_LPAB) to determine how
1039 * flow control was negotiated.
1041 pcs_adv_reg
= rd32(E1000_PCS_ANADV
);
1042 pcs_lp_ability_reg
= rd32(E1000_PCS_LPAB
);
1044 /* Two bits in the Auto Negotiation Advertisement Register
1045 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1046 * Page Ability Register (PCS_LPAB) determine flow control
1047 * for both the PHY and the link partner. The following
1048 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1049 * 1999, describes these PAUSE resolution bits and how flow
1050 * control is determined based upon these settings.
1051 * NOTE: DC = Don't Care
1053 * LOCAL DEVICE | LINK PARTNER
1054 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1055 *-------|---------|-------|---------|--------------------
1056 * 0 | 0 | DC | DC | e1000_fc_none
1057 * 0 | 1 | 0 | DC | e1000_fc_none
1058 * 0 | 1 | 1 | 0 | e1000_fc_none
1059 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1060 * 1 | 0 | 0 | DC | e1000_fc_none
1061 * 1 | DC | 1 | DC | e1000_fc_full
1062 * 1 | 1 | 0 | 0 | e1000_fc_none
1063 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1065 * Are both PAUSE bits set to 1? If so, this implies
1066 * Symmetric Flow Control is enabled at both ends. The
1067 * ASM_DIR bits are irrelevant per the spec.
1069 * For Symmetric Flow Control:
1071 * LOCAL DEVICE | LINK PARTNER
1072 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1073 *-------|---------|-------|---------|--------------------
1074 * 1 | DC | 1 | DC | e1000_fc_full
1077 if ((pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1078 (pcs_lp_ability_reg
& E1000_TXCW_PAUSE
)) {
1079 /* Now we need to check if the user selected Rx ONLY
1080 * of pause frames. In this case, we had to advertise
1081 * FULL flow control because we could not advertise Rx
1082 * ONLY. Hence, we must now check to see if we need to
1083 * turn OFF the TRANSMISSION of PAUSE frames.
1085 if (hw
->fc
.requested_mode
== e1000_fc_full
) {
1086 hw
->fc
.current_mode
= e1000_fc_full
;
1087 hw_dbg("Flow Control = FULL.\n");
1089 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1090 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1093 /* For receiving PAUSE frames ONLY.
1095 * LOCAL DEVICE | LINK PARTNER
1096 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1097 *-------|---------|-------|---------|--------------------
1098 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1100 else if (!(pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1101 (pcs_adv_reg
& E1000_TXCW_ASM_DIR
) &&
1102 (pcs_lp_ability_reg
& E1000_TXCW_PAUSE
) &&
1103 (pcs_lp_ability_reg
& E1000_TXCW_ASM_DIR
)) {
1104 hw
->fc
.current_mode
= e1000_fc_tx_pause
;
1105 hw_dbg("Flow Control = Tx PAUSE frames only.\n");
1107 /* For transmitting PAUSE frames ONLY.
1109 * LOCAL DEVICE | LINK PARTNER
1110 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1111 *-------|---------|-------|---------|--------------------
1112 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1114 else if ((pcs_adv_reg
& E1000_TXCW_PAUSE
) &&
1115 (pcs_adv_reg
& E1000_TXCW_ASM_DIR
) &&
1116 !(pcs_lp_ability_reg
& E1000_TXCW_PAUSE
) &&
1117 (pcs_lp_ability_reg
& E1000_TXCW_ASM_DIR
)) {
1118 hw
->fc
.current_mode
= e1000_fc_rx_pause
;
1119 hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1121 /* Per the IEEE spec, at this point flow control
1122 * should be disabled.
1124 hw
->fc
.current_mode
= e1000_fc_none
;
1125 hw_dbg("Flow Control = NONE.\n");
1128 /* Now we call a subroutine to actually force the MAC
1129 * controller to use the correct flow control settings.
1131 pcs_ctrl_reg
= rd32(E1000_PCS_LCTL
);
1132 pcs_ctrl_reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1133 wr32(E1000_PCS_LCTL
, pcs_ctrl_reg
);
1135 ret_val
= igb_force_mac_fc(hw
);
1137 hw_dbg("Error forcing flow control settings\n");
1147 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1148 * @hw: pointer to the HW structure
1149 * @speed: stores the current speed
1150 * @duplex: stores the current duplex
1152 * Read the status register for the current speed/duplex and store the current
1153 * speed and duplex for copper connections.
1155 s32
igb_get_speed_and_duplex_copper(struct e1000_hw
*hw
, u16
*speed
,
1160 status
= rd32(E1000_STATUS
);
1161 if (status
& E1000_STATUS_SPEED_1000
) {
1162 *speed
= SPEED_1000
;
1163 hw_dbg("1000 Mbs, ");
1164 } else if (status
& E1000_STATUS_SPEED_100
) {
1166 hw_dbg("100 Mbs, ");
1172 if (status
& E1000_STATUS_FD
) {
1173 *duplex
= FULL_DUPLEX
;
1174 hw_dbg("Full Duplex\n");
1176 *duplex
= HALF_DUPLEX
;
1177 hw_dbg("Half Duplex\n");
1184 * igb_get_hw_semaphore - Acquire hardware semaphore
1185 * @hw: pointer to the HW structure
1187 * Acquire the HW semaphore to access the PHY or NVM
1189 s32
igb_get_hw_semaphore(struct e1000_hw
*hw
)
1193 s32 timeout
= hw
->nvm
.word_size
+ 1;
1196 /* Get the SW semaphore */
1197 while (i
< timeout
) {
1198 swsm
= rd32(E1000_SWSM
);
1199 if (!(swsm
& E1000_SWSM_SMBI
))
1207 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1208 ret_val
= -E1000_ERR_NVM
;
1212 /* Get the FW semaphore. */
1213 for (i
= 0; i
< timeout
; i
++) {
1214 swsm
= rd32(E1000_SWSM
);
1215 wr32(E1000_SWSM
, swsm
| E1000_SWSM_SWESMBI
);
1217 /* Semaphore acquired if bit latched */
1218 if (rd32(E1000_SWSM
) & E1000_SWSM_SWESMBI
)
1225 /* Release semaphores */
1226 igb_put_hw_semaphore(hw
);
1227 hw_dbg("Driver can't access the NVM\n");
1228 ret_val
= -E1000_ERR_NVM
;
1237 * igb_put_hw_semaphore - Release hardware semaphore
1238 * @hw: pointer to the HW structure
1240 * Release hardware semaphore used to access the PHY or NVM
1242 void igb_put_hw_semaphore(struct e1000_hw
*hw
)
1246 swsm
= rd32(E1000_SWSM
);
1248 swsm
&= ~(E1000_SWSM_SMBI
| E1000_SWSM_SWESMBI
);
1250 wr32(E1000_SWSM
, swsm
);
1254 * igb_get_auto_rd_done - Check for auto read completion
1255 * @hw: pointer to the HW structure
1257 * Check EEPROM for Auto Read done bit.
1259 s32
igb_get_auto_rd_done(struct e1000_hw
*hw
)
1265 while (i
< AUTO_READ_DONE_TIMEOUT
) {
1266 if (rd32(E1000_EECD
) & E1000_EECD_AUTO_RD
)
1272 if (i
== AUTO_READ_DONE_TIMEOUT
) {
1273 hw_dbg("Auto read by HW from NVM has not completed.\n");
1274 ret_val
= -E1000_ERR_RESET
;
1283 * igb_valid_led_default - Verify a valid default LED config
1284 * @hw: pointer to the HW structure
1285 * @data: pointer to the NVM (EEPROM)
1287 * Read the EEPROM for the current default LED configuration. If the
1288 * LED configuration is not valid, set to a valid LED configuration.
1290 static s32
igb_valid_led_default(struct e1000_hw
*hw
, u16
*data
)
1294 ret_val
= hw
->nvm
.ops
.read(hw
, NVM_ID_LED_SETTINGS
, 1, data
);
1296 hw_dbg("NVM Read Error\n");
1300 if (*data
== ID_LED_RESERVED_0000
|| *data
== ID_LED_RESERVED_FFFF
) {
1301 switch(hw
->phy
.media_type
) {
1302 case e1000_media_type_internal_serdes
:
1303 *data
= ID_LED_DEFAULT_82575_SERDES
;
1305 case e1000_media_type_copper
:
1307 *data
= ID_LED_DEFAULT
;
1317 * @hw: pointer to the HW structure
1320 s32
igb_id_led_init(struct e1000_hw
*hw
)
1322 struct e1000_mac_info
*mac
= &hw
->mac
;
1324 const u32 ledctl_mask
= 0x000000FF;
1325 const u32 ledctl_on
= E1000_LEDCTL_MODE_LED_ON
;
1326 const u32 ledctl_off
= E1000_LEDCTL_MODE_LED_OFF
;
1328 const u16 led_mask
= 0x0F;
1330 /* i210 and i211 devices have different LED mechanism */
1331 if ((hw
->mac
.type
== e1000_i210
) ||
1332 (hw
->mac
.type
== e1000_i211
))
1333 ret_val
= igb_valid_led_default_i210(hw
, &data
);
1335 ret_val
= igb_valid_led_default(hw
, &data
);
1340 mac
->ledctl_default
= rd32(E1000_LEDCTL
);
1341 mac
->ledctl_mode1
= mac
->ledctl_default
;
1342 mac
->ledctl_mode2
= mac
->ledctl_default
;
1344 for (i
= 0; i
< 4; i
++) {
1345 temp
= (data
>> (i
<< 2)) & led_mask
;
1347 case ID_LED_ON1_DEF2
:
1348 case ID_LED_ON1_ON2
:
1349 case ID_LED_ON1_OFF2
:
1350 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1351 mac
->ledctl_mode1
|= ledctl_on
<< (i
<< 3);
1353 case ID_LED_OFF1_DEF2
:
1354 case ID_LED_OFF1_ON2
:
1355 case ID_LED_OFF1_OFF2
:
1356 mac
->ledctl_mode1
&= ~(ledctl_mask
<< (i
<< 3));
1357 mac
->ledctl_mode1
|= ledctl_off
<< (i
<< 3);
1364 case ID_LED_DEF1_ON2
:
1365 case ID_LED_ON1_ON2
:
1366 case ID_LED_OFF1_ON2
:
1367 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1368 mac
->ledctl_mode2
|= ledctl_on
<< (i
<< 3);
1370 case ID_LED_DEF1_OFF2
:
1371 case ID_LED_ON1_OFF2
:
1372 case ID_LED_OFF1_OFF2
:
1373 mac
->ledctl_mode2
&= ~(ledctl_mask
<< (i
<< 3));
1374 mac
->ledctl_mode2
|= ledctl_off
<< (i
<< 3);
1387 * igb_cleanup_led - Set LED config to default operation
1388 * @hw: pointer to the HW structure
1390 * Remove the current LED configuration and set the LED configuration
1391 * to the default value, saved from the EEPROM.
1393 s32
igb_cleanup_led(struct e1000_hw
*hw
)
1395 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_default
);
1400 * igb_blink_led - Blink LED
1401 * @hw: pointer to the HW structure
1403 * Blink the led's which are set to be on.
1405 s32
igb_blink_led(struct e1000_hw
*hw
)
1407 u32 ledctl_blink
= 0;
1410 if (hw
->phy
.media_type
== e1000_media_type_fiber
) {
1411 /* always blink LED0 for PCI-E fiber */
1412 ledctl_blink
= E1000_LEDCTL_LED0_BLINK
|
1413 (E1000_LEDCTL_MODE_LED_ON
<< E1000_LEDCTL_LED0_MODE_SHIFT
);
1415 /* Set the blink bit for each LED that's "on" (0x0E)
1416 * (or "off" if inverted) in ledctl_mode2. The blink
1417 * logic in hardware only works when mode is set to "on"
1418 * so it must be changed accordingly when the mode is
1419 * "off" and inverted.
1421 ledctl_blink
= hw
->mac
.ledctl_mode2
;
1422 for (i
= 0; i
< 32; i
+= 8) {
1423 u32 mode
= (hw
->mac
.ledctl_mode2
>> i
) &
1424 E1000_LEDCTL_LED0_MODE_MASK
;
1425 u32 led_default
= hw
->mac
.ledctl_default
>> i
;
1427 if ((!(led_default
& E1000_LEDCTL_LED0_IVRT
) &&
1428 (mode
== E1000_LEDCTL_MODE_LED_ON
)) ||
1429 ((led_default
& E1000_LEDCTL_LED0_IVRT
) &&
1430 (mode
== E1000_LEDCTL_MODE_LED_OFF
))) {
1432 ~(E1000_LEDCTL_LED0_MODE_MASK
<< i
);
1433 ledctl_blink
|= (E1000_LEDCTL_LED0_BLINK
|
1434 E1000_LEDCTL_MODE_LED_ON
) << i
;
1439 wr32(E1000_LEDCTL
, ledctl_blink
);
1445 * igb_led_off - Turn LED off
1446 * @hw: pointer to the HW structure
1450 s32
igb_led_off(struct e1000_hw
*hw
)
1452 switch (hw
->phy
.media_type
) {
1453 case e1000_media_type_copper
:
1454 wr32(E1000_LEDCTL
, hw
->mac
.ledctl_mode1
);
1464 * igb_disable_pcie_master - Disables PCI-express master access
1465 * @hw: pointer to the HW structure
1467 * Returns 0 (0) if successful, else returns -10
1468 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1469 * the master requests to be disabled.
1471 * Disables PCI-Express master access and verifies there are no pending
1474 s32
igb_disable_pcie_master(struct e1000_hw
*hw
)
1477 s32 timeout
= MASTER_DISABLE_TIMEOUT
;
1480 if (hw
->bus
.type
!= e1000_bus_type_pci_express
)
1483 ctrl
= rd32(E1000_CTRL
);
1484 ctrl
|= E1000_CTRL_GIO_MASTER_DISABLE
;
1485 wr32(E1000_CTRL
, ctrl
);
1488 if (!(rd32(E1000_STATUS
) &
1489 E1000_STATUS_GIO_MASTER_ENABLE
))
1496 hw_dbg("Master requests are pending.\n");
1497 ret_val
= -E1000_ERR_MASTER_REQUESTS_PENDING
;
1506 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1507 * @hw: pointer to the HW structure
1509 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1510 * set, which is forced to MDI mode only.
1512 s32
igb_validate_mdi_setting(struct e1000_hw
*hw
)
1516 /* All MDI settings are supported on 82580 and newer. */
1517 if (hw
->mac
.type
>= e1000_82580
)
1520 if (!hw
->mac
.autoneg
&& (hw
->phy
.mdix
== 0 || hw
->phy
.mdix
== 3)) {
1521 hw_dbg("Invalid MDI setting detected\n");
1523 ret_val
= -E1000_ERR_CONFIG
;
1532 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1533 * @hw: pointer to the HW structure
1534 * @reg: 32bit register offset such as E1000_SCTL
1535 * @offset: register offset to write to
1536 * @data: data to write at register offset
1538 * Writes an address/data control type register. There are several of these
1539 * and they all have the format address << 8 | data and bit 31 is polled for
1542 s32
igb_write_8bit_ctrl_reg(struct e1000_hw
*hw
, u32 reg
,
1543 u32 offset
, u8 data
)
1545 u32 i
, regvalue
= 0;
1548 /* Set up the address and data */
1549 regvalue
= ((u32
)data
) | (offset
<< E1000_GEN_CTL_ADDRESS_SHIFT
);
1550 wr32(reg
, regvalue
);
1552 /* Poll the ready bit to see if the MDI read completed */
1553 for (i
= 0; i
< E1000_GEN_POLL_TIMEOUT
; i
++) {
1555 regvalue
= rd32(reg
);
1556 if (regvalue
& E1000_GEN_CTL_READY
)
1559 if (!(regvalue
& E1000_GEN_CTL_READY
)) {
1560 hw_dbg("Reg %08x did not indicate ready\n", reg
);
1561 ret_val
= -E1000_ERR_PHY
;
1570 * igb_enable_mng_pass_thru - Enable processing of ARP's
1571 * @hw: pointer to the HW structure
1573 * Verifies the hardware needs to leave interface enabled so that frames can
1574 * be directed to and from the management interface.
1576 bool igb_enable_mng_pass_thru(struct e1000_hw
*hw
)
1580 bool ret_val
= false;
1582 if (!hw
->mac
.asf_firmware_present
)
1585 manc
= rd32(E1000_MANC
);
1587 if (!(manc
& E1000_MANC_RCV_TCO_EN
))
1590 if (hw
->mac
.arc_subsystem_valid
) {
1591 fwsm
= rd32(E1000_FWSM
);
1592 factps
= rd32(E1000_FACTPS
);
1594 if (!(factps
& E1000_FACTPS_MNGCG
) &&
1595 ((fwsm
& E1000_FWSM_MODE_MASK
) ==
1596 (e1000_mng_mode_pt
<< E1000_FWSM_MODE_SHIFT
))) {
1601 if ((manc
& E1000_MANC_SMBUS_EN
) &&
1602 !(manc
& E1000_MANC_ASF_EN
)) {