projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
igb: Fix code comments and whitespace
[deliverable/linux.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2013 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* ethtool support for igb */
29
30 #include <linux/vmalloc.h>
31 #include <linux/netdevice.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/if_ether.h>
36 #include <linux/ethtool.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/highmem.h>
41
42 #include "igb.h"
43
44 struct igb_stats {
45 char stat_string[ETH_GSTRING_LEN];
46 int sizeof_stat;
47 int stat_offset;
48 };
49
50 #define IGB_STAT(_name, _stat) { \
51 .stat_string = _name, \
52 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
53 .stat_offset = offsetof(struct igb_adapter, _stat) \
54 }
55 static const struct igb_stats igb_gstrings_stats[] = {
56 IGB_STAT("rx_packets", stats.gprc),
57 IGB_STAT("tx_packets", stats.gptc),
58 IGB_STAT("rx_bytes", stats.gorc),
59 IGB_STAT("tx_bytes", stats.gotc),
60 IGB_STAT("rx_broadcast", stats.bprc),
61 IGB_STAT("tx_broadcast", stats.bptc),
62 IGB_STAT("rx_multicast", stats.mprc),
63 IGB_STAT("tx_multicast", stats.mptc),
64 IGB_STAT("multicast", stats.mprc),
65 IGB_STAT("collisions", stats.colc),
66 IGB_STAT("rx_crc_errors", stats.crcerrs),
67 IGB_STAT("rx_no_buffer_count", stats.rnbc),
68 IGB_STAT("rx_missed_errors", stats.mpc),
69 IGB_STAT("tx_aborted_errors", stats.ecol),
70 IGB_STAT("tx_carrier_errors", stats.tncrs),
71 IGB_STAT("tx_window_errors", stats.latecol),
72 IGB_STAT("tx_abort_late_coll", stats.latecol),
73 IGB_STAT("tx_deferred_ok", stats.dc),
74 IGB_STAT("tx_single_coll_ok", stats.scc),
75 IGB_STAT("tx_multi_coll_ok", stats.mcc),
76 IGB_STAT("tx_timeout_count", tx_timeout_count),
77 IGB_STAT("rx_long_length_errors", stats.roc),
78 IGB_STAT("rx_short_length_errors", stats.ruc),
79 IGB_STAT("rx_align_errors", stats.algnerrc),
80 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
81 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
82 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
83 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
84 IGB_STAT("tx_flow_control_xon", stats.xontxc),
85 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
86 IGB_STAT("rx_long_byte_count", stats.gorc),
87 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
88 IGB_STAT("tx_smbus", stats.mgptc),
89 IGB_STAT("rx_smbus", stats.mgprc),
90 IGB_STAT("dropped_smbus", stats.mgpdc),
91 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
92 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
93 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
94 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
95 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
96 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
97 };
98
99 #define IGB_NETDEV_STAT(_net_stat) { \
100 .stat_string = __stringify(_net_stat), \
101 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
102 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
103 }
104 static const struct igb_stats igb_gstrings_net_stats[] = {
105 IGB_NETDEV_STAT(rx_errors),
106 IGB_NETDEV_STAT(tx_errors),
107 IGB_NETDEV_STAT(tx_dropped),
108 IGB_NETDEV_STAT(rx_length_errors),
109 IGB_NETDEV_STAT(rx_over_errors),
110 IGB_NETDEV_STAT(rx_frame_errors),
111 IGB_NETDEV_STAT(rx_fifo_errors),
112 IGB_NETDEV_STAT(tx_fifo_errors),
113 IGB_NETDEV_STAT(tx_heartbeat_errors)
114 };
115
116 #define IGB_GLOBAL_STATS_LEN \
117 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
118 #define IGB_NETDEV_STATS_LEN \
119 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
120 #define IGB_RX_QUEUE_STATS_LEN \
121 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
122
123 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
124
125 #define IGB_QUEUE_STATS_LEN \
126 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
127 IGB_RX_QUEUE_STATS_LEN) + \
128 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
129 IGB_TX_QUEUE_STATS_LEN))
130 #define IGB_STATS_LEN \
131 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
132
133 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
134 "Register test (offline)", "Eeprom test (offline)",
135 "Interrupt test (offline)", "Loopback test (offline)",
136 "Link test (on/offline)"
137 };
138 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
139
140 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
141 {
142 struct igb_adapter *adapter = netdev_priv(netdev);
143 struct e1000_hw *hw = &adapter->hw;
144 u32 status;
145
146 if (hw->phy.media_type == e1000_media_type_copper) {
147
148 ecmd->supported = (SUPPORTED_10baseT_Half |
149 SUPPORTED_10baseT_Full |
150 SUPPORTED_100baseT_Half |
151 SUPPORTED_100baseT_Full |
152 SUPPORTED_1000baseT_Full|
153 SUPPORTED_Autoneg |
154 SUPPORTED_TP |
155 SUPPORTED_Pause);
156 ecmd->advertising = ADVERTISED_TP;
157
158 if (hw->mac.autoneg == 1) {
159 ecmd->advertising |= ADVERTISED_Autoneg;
160 /* the e1000 autoneg seems to match ethtool nicely */
161 ecmd->advertising |= hw->phy.autoneg_advertised;
162 }
163
164 if (hw->mac.autoneg != 1)
165 ecmd->advertising &= ~(ADVERTISED_Pause |
166 ADVERTISED_Asym_Pause);
167
168 if (hw->fc.requested_mode == e1000_fc_full)
169 ecmd->advertising |= ADVERTISED_Pause;
170 else if (hw->fc.requested_mode == e1000_fc_rx_pause)
171 ecmd->advertising |= (ADVERTISED_Pause |
172 ADVERTISED_Asym_Pause);
173 else if (hw->fc.requested_mode == e1000_fc_tx_pause)
174 ecmd->advertising |= ADVERTISED_Asym_Pause;
175 else
176 ecmd->advertising &= ~(ADVERTISED_Pause |
177 ADVERTISED_Asym_Pause);
178
179 ecmd->port = PORT_TP;
180 ecmd->phy_address = hw->phy.addr;
181 ecmd->transceiver = XCVR_INTERNAL;
182 } else {
183 ecmd->supported = (SUPPORTED_1000baseT_Full |
184 SUPPORTED_100baseT_Full |
185 SUPPORTED_Autoneg |
186 SUPPORTED_FIBRE |
187 SUPPORTED_Pause);
188
189 ecmd->advertising = ADVERTISED_FIBRE;
190
191 if (adapter->link_speed == SPEED_100)
192 ecmd->advertising = ADVERTISED_100baseT_Full;
193 else if (adapter->link_speed == SPEED_1000)
194 ecmd->advertising = ADVERTISED_1000baseT_Full;
195
196 if (hw->mac.autoneg == 1)
197 ecmd->advertising |= ADVERTISED_Autoneg;
198
199 ecmd->port = PORT_FIBRE;
200 ecmd->transceiver = XCVR_EXTERNAL;
201 }
202
203 status = rd32(E1000_STATUS);
204
205 if (status & E1000_STATUS_LU) {
206
207 if (status & E1000_STATUS_SPEED_1000)
208 ethtool_cmd_speed_set(ecmd, SPEED_1000);
209 else if (status & E1000_STATUS_SPEED_100)
210 ethtool_cmd_speed_set(ecmd, SPEED_100);
211 else
212 ethtool_cmd_speed_set(ecmd, SPEED_10);
213
214 if ((status & E1000_STATUS_FD) ||
215 hw->phy.media_type != e1000_media_type_copper)
216 ecmd->duplex = DUPLEX_FULL;
217 else
218 ecmd->duplex = DUPLEX_HALF;
219 } else {
220 ethtool_cmd_speed_set(ecmd, -1);
221 ecmd->duplex = -1;
222 }
223
224 if ((hw->phy.media_type == e1000_media_type_fiber) ||
225 hw->mac.autoneg)
226 ecmd->autoneg = AUTONEG_ENABLE;
227 else
228 ecmd->autoneg = AUTONEG_DISABLE;
229
230 /* MDI-X => 2; MDI =>1; Invalid =>0 */
231 if (hw->phy.media_type == e1000_media_type_copper)
232 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
233 ETH_TP_MDI;
234 else
235 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
236
237 if (hw->phy.mdix == AUTO_ALL_MODES)
238 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
239 else
240 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
241
242 return 0;
243 }
244
245 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
246 {
247 struct igb_adapter *adapter = netdev_priv(netdev);
248 struct e1000_hw *hw = &adapter->hw;
249
250 /* When SoL/IDER sessions are active, autoneg/speed/duplex
251 * cannot be changed
252 */
253 if (igb_check_reset_block(hw)) {
254 dev_err(&adapter->pdev->dev,
255 "Cannot change link characteristics when SoL/IDER is active.\n");
256 return -EINVAL;
257 }
258
259 /* MDI setting is only allowed when autoneg enabled because
260 * some hardware doesn't allow MDI setting when speed or
261 * duplex is forced.
262 */
263 if (ecmd->eth_tp_mdix_ctrl) {
264 if (hw->phy.media_type != e1000_media_type_copper)
265 return -EOPNOTSUPP;
266
267 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
268 (ecmd->autoneg != AUTONEG_ENABLE)) {
269 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
270 return -EINVAL;
271 }
272 }
273
274 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
275 msleep(1);
276
277 if (ecmd->autoneg == AUTONEG_ENABLE) {
278 hw->mac.autoneg = 1;
279 if (hw->phy.media_type == e1000_media_type_fiber) {
280 hw->phy.autoneg_advertised = ecmd->advertising |
281 ADVERTISED_FIBRE |
282 ADVERTISED_Autoneg;
283 if (adapter->link_speed == SPEED_1000)
284 hw->phy.autoneg_advertised =
285 ADVERTISED_1000baseT_Full;
286 else if (adapter->link_speed == SPEED_100)
287 hw->phy.autoneg_advertised =
288 ADVERTISED_100baseT_Full;
289 } else {
290 hw->phy.autoneg_advertised = ecmd->advertising |
291 ADVERTISED_TP |
292 ADVERTISED_Autoneg;
293 }
294 ecmd->advertising = hw->phy.autoneg_advertised;
295 if (adapter->fc_autoneg)
296 hw->fc.requested_mode = e1000_fc_default;
297 } else {
298 u32 speed = ethtool_cmd_speed(ecmd);
299 /* calling this overrides forced MDI setting */
300 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
301 clear_bit(__IGB_RESETTING, &adapter->state);
302 return -EINVAL;
303 }
304 }
305
306 /* MDI-X => 2; MDI => 1; Auto => 3 */
307 if (ecmd->eth_tp_mdix_ctrl) {
308 /* fix up the value for auto (3 => 0) as zero is mapped
309 * internally to auto
310 */
311 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
312 hw->phy.mdix = AUTO_ALL_MODES;
313 else
314 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
315 }
316
317 /* reset the link */
318 if (netif_running(adapter->netdev)) {
319 igb_down(adapter);
320 igb_up(adapter);
321 } else
322 igb_reset(adapter);
323
324 clear_bit(__IGB_RESETTING, &adapter->state);
325 return 0;
326 }
327
328 static u32 igb_get_link(struct net_device *netdev)
329 {
330 struct igb_adapter *adapter = netdev_priv(netdev);
331 struct e1000_mac_info *mac = &adapter->hw.mac;
332
333 /* If the link is not reported up to netdev, interrupts are disabled,
334 * and so the physical link state may have changed since we last
335 * looked. Set get_link_status to make sure that the true link
336 * state is interrogated, rather than pulling a cached and possibly
337 * stale link state from the driver.
338 */
339 if (!netif_carrier_ok(netdev))
340 mac->get_link_status = 1;
341
342 return igb_has_link(adapter);
343 }
344
345 static void igb_get_pauseparam(struct net_device *netdev,
346 struct ethtool_pauseparam *pause)
347 {
348 struct igb_adapter *adapter = netdev_priv(netdev);
349 struct e1000_hw *hw = &adapter->hw;
350
351 pause->autoneg =
352 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
353
354 if (hw->fc.current_mode == e1000_fc_rx_pause)
355 pause->rx_pause = 1;
356 else if (hw->fc.current_mode == e1000_fc_tx_pause)
357 pause->tx_pause = 1;
358 else if (hw->fc.current_mode == e1000_fc_full) {
359 pause->rx_pause = 1;
360 pause->tx_pause = 1;
361 }
362 }
363
364 static int igb_set_pauseparam(struct net_device *netdev,
365 struct ethtool_pauseparam *pause)
366 {
367 struct igb_adapter *adapter = netdev_priv(netdev);
368 struct e1000_hw *hw = &adapter->hw;
369 int retval = 0;
370
371 adapter->fc_autoneg = pause->autoneg;
372
373 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
374 msleep(1);
375
376 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
377 hw->fc.requested_mode = e1000_fc_default;
378 if (netif_running(adapter->netdev)) {
379 igb_down(adapter);
380 igb_up(adapter);
381 } else {
382 igb_reset(adapter);
383 }
384 } else {
385 if (pause->rx_pause && pause->tx_pause)
386 hw->fc.requested_mode = e1000_fc_full;
387 else if (pause->rx_pause && !pause->tx_pause)
388 hw->fc.requested_mode = e1000_fc_rx_pause;
389 else if (!pause->rx_pause && pause->tx_pause)
390 hw->fc.requested_mode = e1000_fc_tx_pause;
391 else if (!pause->rx_pause && !pause->tx_pause)
392 hw->fc.requested_mode = e1000_fc_none;
393
394 hw->fc.current_mode = hw->fc.requested_mode;
395
396 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
397 igb_force_mac_fc(hw) : igb_setup_link(hw));
398 }
399
400 clear_bit(__IGB_RESETTING, &adapter->state);
401 return retval;
402 }
403
404 static u32 igb_get_msglevel(struct net_device *netdev)
405 {
406 struct igb_adapter *adapter = netdev_priv(netdev);
407 return adapter->msg_enable;
408 }
409
410 static void igb_set_msglevel(struct net_device *netdev, u32 data)
411 {
412 struct igb_adapter *adapter = netdev_priv(netdev);
413 adapter->msg_enable = data;
414 }
415
416 static int igb_get_regs_len(struct net_device *netdev)
417 {
418 #define IGB_REGS_LEN 739
419 return IGB_REGS_LEN * sizeof(u32);
420 }
421
422 static void igb_get_regs(struct net_device *netdev,
423 struct ethtool_regs *regs, void *p)
424 {
425 struct igb_adapter *adapter = netdev_priv(netdev);
426 struct e1000_hw *hw = &adapter->hw;
427 u32 *regs_buff = p;
428 u8 i;
429
430 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
431
432 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
433
434 /* General Registers */
435 regs_buff[0] = rd32(E1000_CTRL);
436 regs_buff[1] = rd32(E1000_STATUS);
437 regs_buff[2] = rd32(E1000_CTRL_EXT);
438 regs_buff[3] = rd32(E1000_MDIC);
439 regs_buff[4] = rd32(E1000_SCTL);
440 regs_buff[5] = rd32(E1000_CONNSW);
441 regs_buff[6] = rd32(E1000_VET);
442 regs_buff[7] = rd32(E1000_LEDCTL);
443 regs_buff[8] = rd32(E1000_PBA);
444 regs_buff[9] = rd32(E1000_PBS);
445 regs_buff[10] = rd32(E1000_FRTIMER);
446 regs_buff[11] = rd32(E1000_TCPTIMER);
447
448 /* NVM Register */
449 regs_buff[12] = rd32(E1000_EECD);
450
451 /* Interrupt */
452 /* Reading EICS for EICR because they read the
453 * same but EICS does not clear on read
454 */
455 regs_buff[13] = rd32(E1000_EICS);
456 regs_buff[14] = rd32(E1000_EICS);
457 regs_buff[15] = rd32(E1000_EIMS);
458 regs_buff[16] = rd32(E1000_EIMC);
459 regs_buff[17] = rd32(E1000_EIAC);
460 regs_buff[18] = rd32(E1000_EIAM);
461 /* Reading ICS for ICR because they read the
462 * same but ICS does not clear on read
463 */
464 regs_buff[19] = rd32(E1000_ICS);
465 regs_buff[20] = rd32(E1000_ICS);
466 regs_buff[21] = rd32(E1000_IMS);
467 regs_buff[22] = rd32(E1000_IMC);
468 regs_buff[23] = rd32(E1000_IAC);
469 regs_buff[24] = rd32(E1000_IAM);
470 regs_buff[25] = rd32(E1000_IMIRVP);
471
472 /* Flow Control */
473 regs_buff[26] = rd32(E1000_FCAL);
474 regs_buff[27] = rd32(E1000_FCAH);
475 regs_buff[28] = rd32(E1000_FCTTV);
476 regs_buff[29] = rd32(E1000_FCRTL);
477 regs_buff[30] = rd32(E1000_FCRTH);
478 regs_buff[31] = rd32(E1000_FCRTV);
479
480 /* Receive */
481 regs_buff[32] = rd32(E1000_RCTL);
482 regs_buff[33] = rd32(E1000_RXCSUM);
483 regs_buff[34] = rd32(E1000_RLPML);
484 regs_buff[35] = rd32(E1000_RFCTL);
485 regs_buff[36] = rd32(E1000_MRQC);
486 regs_buff[37] = rd32(E1000_VT_CTL);
487
488 /* Transmit */
489 regs_buff[38] = rd32(E1000_TCTL);
490 regs_buff[39] = rd32(E1000_TCTL_EXT);
491 regs_buff[40] = rd32(E1000_TIPG);
492 regs_buff[41] = rd32(E1000_DTXCTL);
493
494 /* Wake Up */
495 regs_buff[42] = rd32(E1000_WUC);
496 regs_buff[43] = rd32(E1000_WUFC);
497 regs_buff[44] = rd32(E1000_WUS);
498 regs_buff[45] = rd32(E1000_IPAV);
499 regs_buff[46] = rd32(E1000_WUPL);
500
501 /* MAC */
502 regs_buff[47] = rd32(E1000_PCS_CFG0);
503 regs_buff[48] = rd32(E1000_PCS_LCTL);
504 regs_buff[49] = rd32(E1000_PCS_LSTAT);
505 regs_buff[50] = rd32(E1000_PCS_ANADV);
506 regs_buff[51] = rd32(E1000_PCS_LPAB);
507 regs_buff[52] = rd32(E1000_PCS_NPTX);
508 regs_buff[53] = rd32(E1000_PCS_LPABNP);
509
510 /* Statistics */
511 regs_buff[54] = adapter->stats.crcerrs;
512 regs_buff[55] = adapter->stats.algnerrc;
513 regs_buff[56] = adapter->stats.symerrs;
514 regs_buff[57] = adapter->stats.rxerrc;
515 regs_buff[58] = adapter->stats.mpc;
516 regs_buff[59] = adapter->stats.scc;
517 regs_buff[60] = adapter->stats.ecol;
518 regs_buff[61] = adapter->stats.mcc;
519 regs_buff[62] = adapter->stats.latecol;
520 regs_buff[63] = adapter->stats.colc;
521 regs_buff[64] = adapter->stats.dc;
522 regs_buff[65] = adapter->stats.tncrs;
523 regs_buff[66] = adapter->stats.sec;
524 regs_buff[67] = adapter->stats.htdpmc;
525 regs_buff[68] = adapter->stats.rlec;
526 regs_buff[69] = adapter->stats.xonrxc;
527 regs_buff[70] = adapter->stats.xontxc;
528 regs_buff[71] = adapter->stats.xoffrxc;
529 regs_buff[72] = adapter->stats.xofftxc;
530 regs_buff[73] = adapter->stats.fcruc;
531 regs_buff[74] = adapter->stats.prc64;
532 regs_buff[75] = adapter->stats.prc127;
533 regs_buff[76] = adapter->stats.prc255;
534 regs_buff[77] = adapter->stats.prc511;
535 regs_buff[78] = adapter->stats.prc1023;
536 regs_buff[79] = adapter->stats.prc1522;
537 regs_buff[80] = adapter->stats.gprc;
538 regs_buff[81] = adapter->stats.bprc;
539 regs_buff[82] = adapter->stats.mprc;
540 regs_buff[83] = adapter->stats.gptc;
541 regs_buff[84] = adapter->stats.gorc;
542 regs_buff[86] = adapter->stats.gotc;
543 regs_buff[88] = adapter->stats.rnbc;
544 regs_buff[89] = adapter->stats.ruc;
545 regs_buff[90] = adapter->stats.rfc;
546 regs_buff[91] = adapter->stats.roc;
547 regs_buff[92] = adapter->stats.rjc;
548 regs_buff[93] = adapter->stats.mgprc;
549 regs_buff[94] = adapter->stats.mgpdc;
550 regs_buff[95] = adapter->stats.mgptc;
551 regs_buff[96] = adapter->stats.tor;
552 regs_buff[98] = adapter->stats.tot;
553 regs_buff[100] = adapter->stats.tpr;
554 regs_buff[101] = adapter->stats.tpt;
555 regs_buff[102] = adapter->stats.ptc64;
556 regs_buff[103] = adapter->stats.ptc127;
557 regs_buff[104] = adapter->stats.ptc255;
558 regs_buff[105] = adapter->stats.ptc511;
559 regs_buff[106] = adapter->stats.ptc1023;
560 regs_buff[107] = adapter->stats.ptc1522;
561 regs_buff[108] = adapter->stats.mptc;
562 regs_buff[109] = adapter->stats.bptc;
563 regs_buff[110] = adapter->stats.tsctc;
564 regs_buff[111] = adapter->stats.iac;
565 regs_buff[112] = adapter->stats.rpthc;
566 regs_buff[113] = adapter->stats.hgptc;
567 regs_buff[114] = adapter->stats.hgorc;
568 regs_buff[116] = adapter->stats.hgotc;
569 regs_buff[118] = adapter->stats.lenerrs;
570 regs_buff[119] = adapter->stats.scvpc;
571 regs_buff[120] = adapter->stats.hrmpc;
572
573 for (i = 0; i < 4; i++)
574 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
575 for (i = 0; i < 4; i++)
576 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
577 for (i = 0; i < 4; i++)
578 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
579 for (i = 0; i < 4; i++)
580 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
581 for (i = 0; i < 4; i++)
582 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
583 for (i = 0; i < 4; i++)
584 regs_buff[141 + i] = rd32(E1000_RDH(i));
585 for (i = 0; i < 4; i++)
586 regs_buff[145 + i] = rd32(E1000_RDT(i));
587 for (i = 0; i < 4; i++)
588 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
589
590 for (i = 0; i < 10; i++)
591 regs_buff[153 + i] = rd32(E1000_EITR(i));
592 for (i = 0; i < 8; i++)
593 regs_buff[163 + i] = rd32(E1000_IMIR(i));
594 for (i = 0; i < 8; i++)
595 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
596 for (i = 0; i < 16; i++)
597 regs_buff[179 + i] = rd32(E1000_RAL(i));
598 for (i = 0; i < 16; i++)
599 regs_buff[195 + i] = rd32(E1000_RAH(i));
600
601 for (i = 0; i < 4; i++)
602 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
603 for (i = 0; i < 4; i++)
604 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
605 for (i = 0; i < 4; i++)
606 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
607 for (i = 0; i < 4; i++)
608 regs_buff[223 + i] = rd32(E1000_TDH(i));
609 for (i = 0; i < 4; i++)
610 regs_buff[227 + i] = rd32(E1000_TDT(i));
611 for (i = 0; i < 4; i++)
612 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
613 for (i = 0; i < 4; i++)
614 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
615 for (i = 0; i < 4; i++)
616 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
617 for (i = 0; i < 4; i++)
618 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
619
620 for (i = 0; i < 4; i++)
621 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
622 for (i = 0; i < 4; i++)
623 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
624 for (i = 0; i < 32; i++)
625 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
626 for (i = 0; i < 128; i++)
627 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
628 for (i = 0; i < 128; i++)
629 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
630 for (i = 0; i < 4; i++)
631 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
632
633 regs_buff[547] = rd32(E1000_TDFH);
634 regs_buff[548] = rd32(E1000_TDFT);
635 regs_buff[549] = rd32(E1000_TDFHS);
636 regs_buff[550] = rd32(E1000_TDFPC);
637
638 if (hw->mac.type > e1000_82580) {
639 regs_buff[551] = adapter->stats.o2bgptc;
640 regs_buff[552] = adapter->stats.b2ospc;
641 regs_buff[553] = adapter->stats.o2bspc;
642 regs_buff[554] = adapter->stats.b2ogprc;
643 }
644
645 if (hw->mac.type != e1000_82576)
646 return;
647 for (i = 0; i < 12; i++)
648 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
649 for (i = 0; i < 4; i++)
650 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
651 for (i = 0; i < 12; i++)
652 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
653 for (i = 0; i < 12; i++)
654 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
655 for (i = 0; i < 12; i++)
656 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
657 for (i = 0; i < 12; i++)
658 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
659 for (i = 0; i < 12; i++)
660 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
661 for (i = 0; i < 12; i++)
662 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
663
664 for (i = 0; i < 12; i++)
665 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
666 for (i = 0; i < 12; i++)
667 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
668 for (i = 0; i < 12; i++)
669 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
670 for (i = 0; i < 12; i++)
671 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
672 for (i = 0; i < 12; i++)
673 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
674 for (i = 0; i < 12; i++)
675 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
676 for (i = 0; i < 12; i++)
677 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
678 for (i = 0; i < 12; i++)
679 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
680 }
681
682 static int igb_get_eeprom_len(struct net_device *netdev)
683 {
684 struct igb_adapter *adapter = netdev_priv(netdev);
685 return adapter->hw.nvm.word_size * 2;
686 }
687
688 static int igb_get_eeprom(struct net_device *netdev,
689 struct ethtool_eeprom *eeprom, u8 *bytes)
690 {
691 struct igb_adapter *adapter = netdev_priv(netdev);
692 struct e1000_hw *hw = &adapter->hw;
693 u16 *eeprom_buff;
694 int first_word, last_word;
695 int ret_val = 0;
696 u16 i;
697
698 if (eeprom->len == 0)
699 return -EINVAL;
700
701 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
702
703 first_word = eeprom->offset >> 1;
704 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
705
706 eeprom_buff = kmalloc(sizeof(u16) *
707 (last_word - first_word + 1), GFP_KERNEL);
708 if (!eeprom_buff)
709 return -ENOMEM;
710
711 if (hw->nvm.type == e1000_nvm_eeprom_spi)
712 ret_val = hw->nvm.ops.read(hw, first_word,
713 last_word - first_word + 1,
714 eeprom_buff);
715 else {
716 for (i = 0; i < last_word - first_word + 1; i++) {
717 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
718 &eeprom_buff[i]);
719 if (ret_val)
720 break;
721 }
722 }
723
724 /* Device's eeprom is always little-endian, word addressable */
725 for (i = 0; i < last_word - first_word + 1; i++)
726 le16_to_cpus(&eeprom_buff[i]);
727
728 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
729 eeprom->len);
730 kfree(eeprom_buff);
731
732 return ret_val;
733 }
734
735 static int igb_set_eeprom(struct net_device *netdev,
736 struct ethtool_eeprom *eeprom, u8 *bytes)
737 {
738 struct igb_adapter *adapter = netdev_priv(netdev);
739 struct e1000_hw *hw = &adapter->hw;
740 u16 *eeprom_buff;
741 void *ptr;
742 int max_len, first_word, last_word, ret_val = 0;
743 u16 i;
744
745 if (eeprom->len == 0)
746 return -EOPNOTSUPP;
747
748 if (hw->mac.type == e1000_i211)
749 return -EOPNOTSUPP;
750
751 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
752 return -EFAULT;
753
754 max_len = hw->nvm.word_size * 2;
755
756 first_word = eeprom->offset >> 1;
757 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
758 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
759 if (!eeprom_buff)
760 return -ENOMEM;
761
762 ptr = (void *)eeprom_buff;
763
764 if (eeprom->offset & 1) {
765 /* need read/modify/write of first changed EEPROM word
766 * only the second byte of the word is being modified
767 */
768 ret_val = hw->nvm.ops.read(hw, first_word, 1,
769 &eeprom_buff[0]);
770 ptr++;
771 }
772 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
773 /* need read/modify/write of last changed EEPROM word
774 * only the first byte of the word is being modified
775 */
776 ret_val = hw->nvm.ops.read(hw, last_word, 1,
777 &eeprom_buff[last_word - first_word]);
778 }
779
780 /* Device's eeprom is always little-endian, word addressable */
781 for (i = 0; i < last_word - first_word + 1; i++)
782 le16_to_cpus(&eeprom_buff[i]);
783
784 memcpy(ptr, bytes, eeprom->len);
785
786 for (i = 0; i < last_word - first_word + 1; i++)
787 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
788
789 ret_val = hw->nvm.ops.write(hw, first_word,
790 last_word - first_word + 1, eeprom_buff);
791
792 /* Update the checksum over the first part of the EEPROM if needed
793 * and flush shadow RAM for 82573 controllers
794 */
795 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
796 hw->nvm.ops.update(hw);
797
798 igb_set_fw_version(adapter);
799 kfree(eeprom_buff);
800 return ret_val;
801 }
802
803 static void igb_get_drvinfo(struct net_device *netdev,
804 struct ethtool_drvinfo *drvinfo)
805 {
806 struct igb_adapter *adapter = netdev_priv(netdev);
807
808 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
809 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
810
811 /* EEPROM image version # is reported as firmware version # for
812 * 82575 controllers
813 */
814 strlcpy(drvinfo->fw_version, adapter->fw_version,
815 sizeof(drvinfo->fw_version));
816 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
817 sizeof(drvinfo->bus_info));
818 drvinfo->n_stats = IGB_STATS_LEN;
819 drvinfo->testinfo_len = IGB_TEST_LEN;
820 drvinfo->regdump_len = igb_get_regs_len(netdev);
821 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
822 }
823
824 static void igb_get_ringparam(struct net_device *netdev,
825 struct ethtool_ringparam *ring)
826 {
827 struct igb_adapter *adapter = netdev_priv(netdev);
828
829 ring->rx_max_pending = IGB_MAX_RXD;
830 ring->tx_max_pending = IGB_MAX_TXD;
831 ring->rx_pending = adapter->rx_ring_count;
832 ring->tx_pending = adapter->tx_ring_count;
833 }
834
835 static int igb_set_ringparam(struct net_device *netdev,
836 struct ethtool_ringparam *ring)
837 {
838 struct igb_adapter *adapter = netdev_priv(netdev);
839 struct igb_ring *temp_ring;
840 int i, err = 0;
841 u16 new_rx_count, new_tx_count;
842
843 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
844 return -EINVAL;
845
846 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
847 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
848 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
849
850 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
851 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
852 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
853
854 if ((new_tx_count == adapter->tx_ring_count) &&
855 (new_rx_count == adapter->rx_ring_count)) {
856 /* nothing to do */
857 return 0;
858 }
859
860 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
861 msleep(1);
862
863 if (!netif_running(adapter->netdev)) {
864 for (i = 0; i < adapter->num_tx_queues; i++)
865 adapter->tx_ring[i]->count = new_tx_count;
866 for (i = 0; i < adapter->num_rx_queues; i++)
867 adapter->rx_ring[i]->count = new_rx_count;
868 adapter->tx_ring_count = new_tx_count;
869 adapter->rx_ring_count = new_rx_count;
870 goto clear_reset;
871 }
872
873 if (adapter->num_tx_queues > adapter->num_rx_queues)
874 temp_ring = vmalloc(adapter->num_tx_queues *
875 sizeof(struct igb_ring));
876 else
877 temp_ring = vmalloc(adapter->num_rx_queues *
878 sizeof(struct igb_ring));
879
880 if (!temp_ring) {
881 err = -ENOMEM;
882 goto clear_reset;
883 }
884
885 igb_down(adapter);
886
887 /* We can't just free everything and then setup again,
888 * because the ISRs in MSI-X mode get passed pointers
889 * to the Tx and Rx ring structs.
890 */
891 if (new_tx_count != adapter->tx_ring_count) {
892 for (i = 0; i < adapter->num_tx_queues; i++) {
893 memcpy(&temp_ring[i], adapter->tx_ring[i],
894 sizeof(struct igb_ring));
895
896 temp_ring[i].count = new_tx_count;
897 err = igb_setup_tx_resources(&temp_ring[i]);
898 if (err) {
899 while (i) {
900 i--;
901 igb_free_tx_resources(&temp_ring[i]);
902 }
903 goto err_setup;
904 }
905 }
906
907 for (i = 0; i < adapter->num_tx_queues; i++) {
908 igb_free_tx_resources(adapter->tx_ring[i]);
909
910 memcpy(adapter->tx_ring[i], &temp_ring[i],
911 sizeof(struct igb_ring));
912 }
913
914 adapter->tx_ring_count = new_tx_count;
915 }
916
917 if (new_rx_count != adapter->rx_ring_count) {
918 for (i = 0; i < adapter->num_rx_queues; i++) {
919 memcpy(&temp_ring[i], adapter->rx_ring[i],
920 sizeof(struct igb_ring));
921
922 temp_ring[i].count = new_rx_count;
923 err = igb_setup_rx_resources(&temp_ring[i]);
924 if (err) {
925 while (i) {
926 i--;
927 igb_free_rx_resources(&temp_ring[i]);
928 }
929 goto err_setup;
930 }
931
932 }
933
934 for (i = 0; i < adapter->num_rx_queues; i++) {
935 igb_free_rx_resources(adapter->rx_ring[i]);
936
937 memcpy(adapter->rx_ring[i], &temp_ring[i],
938 sizeof(struct igb_ring));
939 }
940
941 adapter->rx_ring_count = new_rx_count;
942 }
943 err_setup:
944 igb_up(adapter);
945 vfree(temp_ring);
946 clear_reset:
947 clear_bit(__IGB_RESETTING, &adapter->state);
948 return err;
949 }
950
951 /* ethtool register test data */
952 struct igb_reg_test {
953 u16 reg;
954 u16 reg_offset;
955 u16 array_len;
956 u16 test_type;
957 u32 mask;
958 u32 write;
959 };
960
961 /* In the hardware, registers are laid out either singly, in arrays
962 * spaced 0x100 bytes apart, or in contiguous tables. We assume
963 * most tests take place on arrays or single registers (handled
964 * as a single-element array) and special-case the tables.
965 * Table tests are always pattern tests.
966 *
967 * We also make provision for some required setup steps by specifying
968 * registers to be written without any read-back testing.
969 */
970
971 #define PATTERN_TEST 1
972 #define SET_READ_TEST 2
973 #define WRITE_NO_TEST 3
974 #define TABLE32_TEST 4
975 #define TABLE64_TEST_LO 5
976 #define TABLE64_TEST_HI 6
977
978 /* i210 reg test */
979 static struct igb_reg_test reg_test_i210[] = {
980 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
981 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
982 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
983 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
984 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
985 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
986 /* RDH is read-only for i210, only test RDT. */
987 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
988 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
989 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
990 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
991 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
992 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
993 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
994 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
995 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
996 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
997 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
998 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
999 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1000 0xFFFFFFFF, 0xFFFFFFFF },
1001 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1002 0x900FFFFF, 0xFFFFFFFF },
1003 { E1000_MTA, 0, 128, TABLE32_TEST,
1004 0xFFFFFFFF, 0xFFFFFFFF },
1005 { 0, 0, 0, 0, 0 }
1006 };
1007
1008 /* i350 reg test */
1009 static struct igb_reg_test reg_test_i350[] = {
1010 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1011 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1012 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1013 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1014 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1015 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1016 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1017 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1018 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1019 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1020 /* RDH is read-only for i350, only test RDT. */
1021 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1022 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1023 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1024 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1025 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1026 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1027 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1028 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1029 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1030 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1031 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1032 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1033 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1034 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1035 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1036 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1037 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1038 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1039 0xFFFFFFFF, 0xFFFFFFFF },
1040 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1041 0xC3FFFFFF, 0xFFFFFFFF },
1042 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1043 0xFFFFFFFF, 0xFFFFFFFF },
1044 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1045 0xC3FFFFFF, 0xFFFFFFFF },
1046 { E1000_MTA, 0, 128, TABLE32_TEST,
1047 0xFFFFFFFF, 0xFFFFFFFF },
1048 { 0, 0, 0, 0 }
1049 };
1050
1051 /* 82580 reg test */
1052 static struct igb_reg_test reg_test_82580[] = {
1053 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1054 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1055 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1056 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1057 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1058 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1059 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1060 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1061 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1062 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1063 /* RDH is read-only for 82580, only test RDT. */
1064 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1065 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1066 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1067 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1068 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1069 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1070 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1071 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1072 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1073 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1074 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1075 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1076 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1077 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1078 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1079 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1080 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1081 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1082 0xFFFFFFFF, 0xFFFFFFFF },
1083 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1084 0x83FFFFFF, 0xFFFFFFFF },
1085 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1086 0xFFFFFFFF, 0xFFFFFFFF },
1087 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1088 0x83FFFFFF, 0xFFFFFFFF },
1089 { E1000_MTA, 0, 128, TABLE32_TEST,
1090 0xFFFFFFFF, 0xFFFFFFFF },
1091 { 0, 0, 0, 0 }
1092 };
1093
1094 /* 82576 reg test */
1095 static struct igb_reg_test reg_test_82576[] = {
1096 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1097 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1098 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1099 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1100 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1101 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1102 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1103 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1104 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1105 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1106 /* Enable all RX queues before testing. */
1107 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1108 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1109 /* RDH is read-only for 82576, only test RDT. */
1110 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1111 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1112 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1113 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1114 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1115 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1116 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1117 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1118 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1119 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1120 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1121 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1122 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1123 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1124 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1125 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1126 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1127 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1128 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1129 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1130 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1131 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1132 { 0, 0, 0, 0 }
1133 };
1134
1135 /* 82575 register test */
1136 static struct igb_reg_test reg_test_82575[] = {
1137 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1138 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1139 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1140 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1141 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1142 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1143 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1144 /* Enable all four RX queues before testing. */
1145 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1146 /* RDH is read-only for 82575, only test RDT. */
1147 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1148 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1149 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1150 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1151 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1152 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1153 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1154 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1155 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1156 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1157 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1158 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1159 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1160 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1161 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1162 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1163 { 0, 0, 0, 0 }
1164 };
1165
1166 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1167 int reg, u32 mask, u32 write)
1168 {
1169 struct e1000_hw *hw = &adapter->hw;
1170 u32 pat, val;
1171 static const u32 _test[] =
1172 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1173 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1174 wr32(reg, (_test[pat] & write));
1175 val = rd32(reg) & mask;
1176 if (val != (_test[pat] & write & mask)) {
1177 dev_err(&adapter->pdev->dev,
1178 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1179 reg, val, (_test[pat] & write & mask));
1180 *data = reg;
1181 return 1;
1182 }
1183 }
1184
1185 return 0;
1186 }
1187
1188 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1189 int reg, u32 mask, u32 write)
1190 {
1191 struct e1000_hw *hw = &adapter->hw;
1192 u32 val;
1193 wr32(reg, write & mask);
1194 val = rd32(reg);
1195 if ((write & mask) != (val & mask)) {
1196 dev_err(&adapter->pdev->dev,
1197 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg,
1198 (val & mask), (write & mask));
1199 *data = reg;
1200 return 1;
1201 }
1202
1203 return 0;
1204 }
1205
1206 #define REG_PATTERN_TEST(reg, mask, write) \
1207 do { \
1208 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1209 return 1; \
1210 } while (0)
1211
1212 #define REG_SET_AND_CHECK(reg, mask, write) \
1213 do { \
1214 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1215 return 1; \
1216 } while (0)
1217
1218 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1219 {
1220 struct e1000_hw *hw = &adapter->hw;
1221 struct igb_reg_test *test;
1222 u32 value, before, after;
1223 u32 i, toggle;
1224
1225 switch (adapter->hw.mac.type) {
1226 case e1000_i350:
1227 test = reg_test_i350;
1228 toggle = 0x7FEFF3FF;
1229 break;
1230 case e1000_i210:
1231 case e1000_i211:
1232 test = reg_test_i210;
1233 toggle = 0x7FEFF3FF;
1234 break;
1235 case e1000_82580:
1236 test = reg_test_82580;
1237 toggle = 0x7FEFF3FF;
1238 break;
1239 case e1000_82576:
1240 test = reg_test_82576;
1241 toggle = 0x7FFFF3FF;
1242 break;
1243 default:
1244 test = reg_test_82575;
1245 toggle = 0x7FFFF3FF;
1246 break;
1247 }
1248
1249 /* Because the status register is such a special case,
1250 * we handle it separately from the rest of the register
1251 * tests. Some bits are read-only, some toggle, and some
1252 * are writable on newer MACs.
1253 */
1254 before = rd32(E1000_STATUS);
1255 value = (rd32(E1000_STATUS) & toggle);
1256 wr32(E1000_STATUS, toggle);
1257 after = rd32(E1000_STATUS) & toggle;
1258 if (value != after) {
1259 dev_err(&adapter->pdev->dev,
1260 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1261 after, value);
1262 *data = 1;
1263 return 1;
1264 }
1265 /* restore previous status */
1266 wr32(E1000_STATUS, before);
1267
1268 /* Perform the remainder of the register test, looping through
1269 * the test table until we either fail or reach the null entry.
1270 */
1271 while (test->reg) {
1272 for (i = 0; i < test->array_len; i++) {
1273 switch (test->test_type) {
1274 case PATTERN_TEST:
1275 REG_PATTERN_TEST(test->reg +
1276 (i * test->reg_offset),
1277 test->mask,
1278 test->write);
1279 break;
1280 case SET_READ_TEST:
1281 REG_SET_AND_CHECK(test->reg +
1282 (i * test->reg_offset),
1283 test->mask,
1284 test->write);
1285 break;
1286 case WRITE_NO_TEST:
1287 writel(test->write,
1288 (adapter->hw.hw_addr + test->reg)
1289 + (i * test->reg_offset));
1290 break;
1291 case TABLE32_TEST:
1292 REG_PATTERN_TEST(test->reg + (i * 4),
1293 test->mask,
1294 test->write);
1295 break;
1296 case TABLE64_TEST_LO:
1297 REG_PATTERN_TEST(test->reg + (i * 8),
1298 test->mask,
1299 test->write);
1300 break;
1301 case TABLE64_TEST_HI:
1302 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1303 test->mask,
1304 test->write);
1305 break;
1306 }
1307 }
1308 test++;
1309 }
1310
1311 *data = 0;
1312 return 0;
1313 }
1314
1315 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1316 {
1317 *data = 0;
1318
1319 /* Validate eeprom on all parts but i211 */
1320 if (adapter->hw.mac.type != e1000_i211) {
1321 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1322 *data = 2;
1323 }
1324
1325 return *data;
1326 }
1327
1328 static irqreturn_t igb_test_intr(int irq, void *data)
1329 {
1330 struct igb_adapter *adapter = (struct igb_adapter *) data;
1331 struct e1000_hw *hw = &adapter->hw;
1332
1333 adapter->test_icr |= rd32(E1000_ICR);
1334
1335 return IRQ_HANDLED;
1336 }
1337
1338 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1339 {
1340 struct e1000_hw *hw = &adapter->hw;
1341 struct net_device *netdev = adapter->netdev;
1342 u32 mask, ics_mask, i = 0, shared_int = true;
1343 u32 irq = adapter->pdev->irq;
1344
1345 *data = 0;
1346
1347 /* Hook up test interrupt handler just for this test */
1348 if (adapter->msix_entries) {
1349 if (request_irq(adapter->msix_entries[0].vector,
1350 igb_test_intr, 0, netdev->name, adapter)) {
1351 *data = 1;
1352 return -1;
1353 }
1354 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1355 shared_int = false;
1356 if (request_irq(irq,
1357 igb_test_intr, 0, netdev->name, adapter)) {
1358 *data = 1;
1359 return -1;
1360 }
1361 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1362 netdev->name, adapter)) {
1363 shared_int = false;
1364 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1365 netdev->name, adapter)) {
1366 *data = 1;
1367 return -1;
1368 }
1369 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1370 (shared_int ? "shared" : "unshared"));
1371
1372 /* Disable all the interrupts */
1373 wr32(E1000_IMC, ~0);
1374 wrfl();
1375 msleep(10);
1376
1377 /* Define all writable bits for ICS */
1378 switch (hw->mac.type) {
1379 case e1000_82575:
1380 ics_mask = 0x37F47EDD;
1381 break;
1382 case e1000_82576:
1383 ics_mask = 0x77D4FBFD;
1384 break;
1385 case e1000_82580:
1386 ics_mask = 0x77DCFED5;
1387 break;
1388 case e1000_i350:
1389 case e1000_i210:
1390 case e1000_i211:
1391 ics_mask = 0x77DCFED5;
1392 break;
1393 default:
1394 ics_mask = 0x7FFFFFFF;
1395 break;
1396 }
1397
1398 /* Test each interrupt */
1399 for (; i < 31; i++) {
1400 /* Interrupt to test */
1401 mask = 1 << i;
1402
1403 if (!(mask & ics_mask))
1404 continue;
1405
1406 if (!shared_int) {
1407 /* Disable the interrupt to be reported in
1408 * the cause register and then force the same
1409 * interrupt and see if one gets posted. If
1410 * an interrupt was posted to the bus, the
1411 * test failed.
1412 */
1413 adapter->test_icr = 0;
1414
1415 /* Flush any pending interrupts */
1416 wr32(E1000_ICR, ~0);
1417
1418 wr32(E1000_IMC, mask);
1419 wr32(E1000_ICS, mask);
1420 wrfl();
1421 msleep(10);
1422
1423 if (adapter->test_icr & mask) {
1424 *data = 3;
1425 break;
1426 }
1427 }
1428
1429 /* Enable the interrupt to be reported in
1430 * the cause register and then force the same
1431 * interrupt and see if one gets posted. If
1432 * an interrupt was not posted to the bus, the
1433 * test failed.
1434 */
1435 adapter->test_icr = 0;
1436
1437 /* Flush any pending interrupts */
1438 wr32(E1000_ICR, ~0);
1439
1440 wr32(E1000_IMS, mask);
1441 wr32(E1000_ICS, mask);
1442 wrfl();
1443 msleep(10);
1444
1445 if (!(adapter->test_icr & mask)) {
1446 *data = 4;
1447 break;
1448 }
1449
1450 if (!shared_int) {
1451 /* Disable the other interrupts to be reported in
1452 * the cause register and then force the other
1453 * interrupts and see if any get posted. If
1454 * an interrupt was posted to the bus, the
1455 * test failed.
1456 */
1457 adapter->test_icr = 0;
1458
1459 /* Flush any pending interrupts */
1460 wr32(E1000_ICR, ~0);
1461
1462 wr32(E1000_IMC, ~mask);
1463 wr32(E1000_ICS, ~mask);
1464 wrfl();
1465 msleep(10);
1466
1467 if (adapter->test_icr & mask) {
1468 *data = 5;
1469 break;
1470 }
1471 }
1472 }
1473
1474 /* Disable all the interrupts */
1475 wr32(E1000_IMC, ~0);
1476 wrfl();
1477 msleep(10);
1478
1479 /* Unhook test interrupt handler */
1480 if (adapter->msix_entries)
1481 free_irq(adapter->msix_entries[0].vector, adapter);
1482 else
1483 free_irq(irq, adapter);
1484
1485 return *data;
1486 }
1487
1488 static void igb_free_desc_rings(struct igb_adapter *adapter)
1489 {
1490 igb_free_tx_resources(&adapter->test_tx_ring);
1491 igb_free_rx_resources(&adapter->test_rx_ring);
1492 }
1493
1494 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1495 {
1496 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1497 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1498 struct e1000_hw *hw = &adapter->hw;
1499 int ret_val;
1500
1501 /* Setup Tx descriptor ring and Tx buffers */
1502 tx_ring->count = IGB_DEFAULT_TXD;
1503 tx_ring->dev = &adapter->pdev->dev;
1504 tx_ring->netdev = adapter->netdev;
1505 tx_ring->reg_idx = adapter->vfs_allocated_count;
1506
1507 if (igb_setup_tx_resources(tx_ring)) {
1508 ret_val = 1;
1509 goto err_nomem;
1510 }
1511
1512 igb_setup_tctl(adapter);
1513 igb_configure_tx_ring(adapter, tx_ring);
1514
1515 /* Setup Rx descriptor ring and Rx buffers */
1516 rx_ring->count = IGB_DEFAULT_RXD;
1517 rx_ring->dev = &adapter->pdev->dev;
1518 rx_ring->netdev = adapter->netdev;
1519 rx_ring->reg_idx = adapter->vfs_allocated_count;
1520
1521 if (igb_setup_rx_resources(rx_ring)) {
1522 ret_val = 3;
1523 goto err_nomem;
1524 }
1525
1526 /* set the default queue to queue 0 of PF */
1527 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1528
1529 /* enable receive ring */
1530 igb_setup_rctl(adapter);
1531 igb_configure_rx_ring(adapter, rx_ring);
1532
1533 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1534
1535 return 0;
1536
1537 err_nomem:
1538 igb_free_desc_rings(adapter);
1539 return ret_val;
1540 }
1541
1542 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1543 {
1544 struct e1000_hw *hw = &adapter->hw;
1545
1546 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1547 igb_write_phy_reg(hw, 29, 0x001F);
1548 igb_write_phy_reg(hw, 30, 0x8FFC);
1549 igb_write_phy_reg(hw, 29, 0x001A);
1550 igb_write_phy_reg(hw, 30, 0x8FF0);
1551 }
1552
1553 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1554 {
1555 struct e1000_hw *hw = &adapter->hw;
1556 u32 ctrl_reg = 0;
1557
1558 hw->mac.autoneg = false;
1559
1560 if (hw->phy.type == e1000_phy_m88) {
1561 if (hw->phy.id != I210_I_PHY_ID) {
1562 /* Auto-MDI/MDIX Off */
1563 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1564 /* reset to update Auto-MDI/MDIX */
1565 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1566 /* autoneg off */
1567 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1568 } else {
1569 /* force 1000, set loopback */
1570 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1571 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1572 }
1573 }
1574
1575 /* add small delay to avoid loopback test failure */
1576 msleep(50);
1577
1578 /* force 1000, set loopback */
1579 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1580
1581 /* Now set up the MAC to the same speed/duplex as the PHY. */
1582 ctrl_reg = rd32(E1000_CTRL);
1583 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1584 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1585 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1586 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1587 E1000_CTRL_FD | /* Force Duplex to FULL */
1588 E1000_CTRL_SLU); /* Set link up enable bit */
1589
1590 if (hw->phy.type == e1000_phy_m88)
1591 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1592
1593 wr32(E1000_CTRL, ctrl_reg);
1594
1595 /* Disable the receiver on the PHY so when a cable is plugged in, the
1596 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1597 */
1598 if (hw->phy.type == e1000_phy_m88)
1599 igb_phy_disable_receiver(adapter);
1600
1601 mdelay(500);
1602 return 0;
1603 }
1604
1605 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1606 {
1607 return igb_integrated_phy_loopback(adapter);
1608 }
1609
1610 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1611 {
1612 struct e1000_hw *hw = &adapter->hw;
1613 u32 reg;
1614
1615 reg = rd32(E1000_CTRL_EXT);
1616
1617 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1618 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1619 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1620 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1621 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1622 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1623
1624 /* Enable DH89xxCC MPHY for near end loopback */
1625 reg = rd32(E1000_MPHY_ADDR_CTL);
1626 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1627 E1000_MPHY_PCS_CLK_REG_OFFSET;
1628 wr32(E1000_MPHY_ADDR_CTL, reg);
1629
1630 reg = rd32(E1000_MPHY_DATA);
1631 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1632 wr32(E1000_MPHY_DATA, reg);
1633 }
1634
1635 reg = rd32(E1000_RCTL);
1636 reg |= E1000_RCTL_LBM_TCVR;
1637 wr32(E1000_RCTL, reg);
1638
1639 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1640
1641 reg = rd32(E1000_CTRL);
1642 reg &= ~(E1000_CTRL_RFCE |
1643 E1000_CTRL_TFCE |
1644 E1000_CTRL_LRST);
1645 reg |= E1000_CTRL_SLU |
1646 E1000_CTRL_FD;
1647 wr32(E1000_CTRL, reg);
1648
1649 /* Unset switch control to serdes energy detect */
1650 reg = rd32(E1000_CONNSW);
1651 reg &= ~E1000_CONNSW_ENRGSRC;
1652 wr32(E1000_CONNSW, reg);
1653
1654 /* Unset sigdetect for SERDES loopback on
1655 * 82580 and i350 devices.
1656 */
1657 switch (hw->mac.type) {
1658 case e1000_82580:
1659 case e1000_i350:
1660 reg = rd32(E1000_PCS_CFG0);
1661 reg |= E1000_PCS_CFG_IGN_SD;
1662 wr32(E1000_PCS_CFG0, reg);
1663 break;
1664 default:
1665 break;
1666 }
1667
1668 /* Set PCS register for forced speed */
1669 reg = rd32(E1000_PCS_LCTL);
1670 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1671 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1672 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1673 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1674 E1000_PCS_LCTL_FSD | /* Force Speed */
1675 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1676 wr32(E1000_PCS_LCTL, reg);
1677
1678 return 0;
1679 }
1680
1681 return igb_set_phy_loopback(adapter);
1682 }
1683
1684 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1685 {
1686 struct e1000_hw *hw = &adapter->hw;
1687 u32 rctl;
1688 u16 phy_reg;
1689
1690 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1691 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1692 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1693 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1694 u32 reg;
1695
1696 /* Disable near end loopback on DH89xxCC */
1697 reg = rd32(E1000_MPHY_ADDR_CTL);
1698 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1699 E1000_MPHY_PCS_CLK_REG_OFFSET;
1700 wr32(E1000_MPHY_ADDR_CTL, reg);
1701
1702 reg = rd32(E1000_MPHY_DATA);
1703 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1704 wr32(E1000_MPHY_DATA, reg);
1705 }
1706
1707 rctl = rd32(E1000_RCTL);
1708 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1709 wr32(E1000_RCTL, rctl);
1710
1711 hw->mac.autoneg = true;
1712 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1713 if (phy_reg & MII_CR_LOOPBACK) {
1714 phy_reg &= ~MII_CR_LOOPBACK;
1715 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1716 igb_phy_sw_reset(hw);
1717 }
1718 }
1719
1720 static void igb_create_lbtest_frame(struct sk_buff *skb,
1721 unsigned int frame_size)
1722 {
1723 memset(skb->data, 0xFF, frame_size);
1724 frame_size /= 2;
1725 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1726 memset(&skb->data[frame_size + 10], 0xBE, 1);
1727 memset(&skb->data[frame_size + 12], 0xAF, 1);
1728 }
1729
1730 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1731 unsigned int frame_size)
1732 {
1733 unsigned char *data;
1734 bool match = true;
1735
1736 frame_size >>= 1;
1737
1738 data = kmap(rx_buffer->page);
1739
1740 if (data[3] != 0xFF ||
1741 data[frame_size + 10] != 0xBE ||
1742 data[frame_size + 12] != 0xAF)
1743 match = false;
1744
1745 kunmap(rx_buffer->page);
1746
1747 return match;
1748 }
1749
1750 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1751 struct igb_ring *tx_ring,
1752 unsigned int size)
1753 {
1754 union e1000_adv_rx_desc *rx_desc;
1755 struct igb_rx_buffer *rx_buffer_info;
1756 struct igb_tx_buffer *tx_buffer_info;
1757 u16 rx_ntc, tx_ntc, count = 0;
1758
1759 /* initialize next to clean and descriptor values */
1760 rx_ntc = rx_ring->next_to_clean;
1761 tx_ntc = tx_ring->next_to_clean;
1762 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1763
1764 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
1765 /* check Rx buffer */
1766 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1767
1768 /* sync Rx buffer for CPU read */
1769 dma_sync_single_for_cpu(rx_ring->dev,
1770 rx_buffer_info->dma,
1771 IGB_RX_BUFSZ,
1772 DMA_FROM_DEVICE);
1773
1774 /* verify contents of skb */
1775 if (igb_check_lbtest_frame(rx_buffer_info, size))
1776 count++;
1777
1778 /* sync Rx buffer for device write */
1779 dma_sync_single_for_device(rx_ring->dev,
1780 rx_buffer_info->dma,
1781 IGB_RX_BUFSZ,
1782 DMA_FROM_DEVICE);
1783
1784 /* unmap buffer on Tx side */
1785 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1786 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1787
1788 /* increment Rx/Tx next to clean counters */
1789 rx_ntc++;
1790 if (rx_ntc == rx_ring->count)
1791 rx_ntc = 0;
1792 tx_ntc++;
1793 if (tx_ntc == tx_ring->count)
1794 tx_ntc = 0;
1795
1796 /* fetch next descriptor */
1797 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1798 }
1799
1800 netdev_tx_reset_queue(txring_txq(tx_ring));
1801
1802 /* re-map buffers to ring, store next to clean values */
1803 igb_alloc_rx_buffers(rx_ring, count);
1804 rx_ring->next_to_clean = rx_ntc;
1805 tx_ring->next_to_clean = tx_ntc;
1806
1807 return count;
1808 }
1809
1810 static int igb_run_loopback_test(struct igb_adapter *adapter)
1811 {
1812 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1813 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1814 u16 i, j, lc, good_cnt;
1815 int ret_val = 0;
1816 unsigned int size = IGB_RX_HDR_LEN;
1817 netdev_tx_t tx_ret_val;
1818 struct sk_buff *skb;
1819
1820 /* allocate test skb */
1821 skb = alloc_skb(size, GFP_KERNEL);
1822 if (!skb)
1823 return 11;
1824
1825 /* place data into test skb */
1826 igb_create_lbtest_frame(skb, size);
1827 skb_put(skb, size);
1828
1829 /* Calculate the loop count based on the largest descriptor ring
1830 * The idea is to wrap the largest ring a number of times using 64
1831 * send/receive pairs during each loop
1832 */
1833
1834 if (rx_ring->count <= tx_ring->count)
1835 lc = ((tx_ring->count / 64) * 2) + 1;
1836 else
1837 lc = ((rx_ring->count / 64) * 2) + 1;
1838
1839 for (j = 0; j <= lc; j++) { /* loop count loop */
1840 /* reset count of good packets */
1841 good_cnt = 0;
1842
1843 /* place 64 packets on the transmit queue*/
1844 for (i = 0; i < 64; i++) {
1845 skb_get(skb);
1846 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1847 if (tx_ret_val == NETDEV_TX_OK)
1848 good_cnt++;
1849 }
1850
1851 if (good_cnt != 64) {
1852 ret_val = 12;
1853 break;
1854 }
1855
1856 /* allow 200 milliseconds for packets to go from Tx to Rx */
1857 msleep(200);
1858
1859 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1860 if (good_cnt != 64) {
1861 ret_val = 13;
1862 break;
1863 }
1864 } /* end loop count loop */
1865
1866 /* free the original skb */
1867 kfree_skb(skb);
1868
1869 return ret_val;
1870 }
1871
1872 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1873 {
1874 /* PHY loopback cannot be performed if SoL/IDER
1875 * sessions are active
1876 */
1877 if (igb_check_reset_block(&adapter->hw)) {
1878 dev_err(&adapter->pdev->dev,
1879 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1880 *data = 0;
1881 goto out;
1882 }
1883 *data = igb_setup_desc_rings(adapter);
1884 if (*data)
1885 goto out;
1886 *data = igb_setup_loopback_test(adapter);
1887 if (*data)
1888 goto err_loopback;
1889 *data = igb_run_loopback_test(adapter);
1890 igb_loopback_cleanup(adapter);
1891
1892 err_loopback:
1893 igb_free_desc_rings(adapter);
1894 out:
1895 return *data;
1896 }
1897
1898 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1899 {
1900 struct e1000_hw *hw = &adapter->hw;
1901 *data = 0;
1902 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1903 int i = 0;
1904 hw->mac.serdes_has_link = false;
1905
1906 /* On some blade server designs, link establishment
1907 * could take as long as 2-3 minutes
1908 */
1909 do {
1910 hw->mac.ops.check_for_link(&adapter->hw);
1911 if (hw->mac.serdes_has_link)
1912 return *data;
1913 msleep(20);
1914 } while (i++ < 3750);
1915
1916 *data = 1;
1917 } else {
1918 hw->mac.ops.check_for_link(&adapter->hw);
1919 if (hw->mac.autoneg)
1920 msleep(5000);
1921
1922 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1923 *data = 1;
1924 }
1925 return *data;
1926 }
1927
1928 static void igb_diag_test(struct net_device *netdev,
1929 struct ethtool_test *eth_test, u64 *data)
1930 {
1931 struct igb_adapter *adapter = netdev_priv(netdev);
1932 u16 autoneg_advertised;
1933 u8 forced_speed_duplex, autoneg;
1934 bool if_running = netif_running(netdev);
1935
1936 set_bit(__IGB_TESTING, &adapter->state);
1937 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1938 /* Offline tests */
1939
1940 /* save speed, duplex, autoneg settings */
1941 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1942 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1943 autoneg = adapter->hw.mac.autoneg;
1944
1945 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1946
1947 /* power up link for link test */
1948 igb_power_up_link(adapter);
1949
1950 /* Link test performed before hardware reset so autoneg doesn't
1951 * interfere with test result
1952 */
1953 if (igb_link_test(adapter, &data[4]))
1954 eth_test->flags |= ETH_TEST_FL_FAILED;
1955
1956 if (if_running)
1957 /* indicate we're in test mode */
1958 dev_close(netdev);
1959 else
1960 igb_reset(adapter);
1961
1962 if (igb_reg_test(adapter, &data[0]))
1963 eth_test->flags |= ETH_TEST_FL_FAILED;
1964
1965 igb_reset(adapter);
1966 if (igb_eeprom_test(adapter, &data[1]))
1967 eth_test->flags |= ETH_TEST_FL_FAILED;
1968
1969 igb_reset(adapter);
1970 if (igb_intr_test(adapter, &data[2]))
1971 eth_test->flags |= ETH_TEST_FL_FAILED;
1972
1973 igb_reset(adapter);
1974 /* power up link for loopback test */
1975 igb_power_up_link(adapter);
1976 if (igb_loopback_test(adapter, &data[3]))
1977 eth_test->flags |= ETH_TEST_FL_FAILED;
1978
1979 /* restore speed, duplex, autoneg settings */
1980 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1981 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1982 adapter->hw.mac.autoneg = autoneg;
1983
1984 /* force this routine to wait until autoneg complete/timeout */
1985 adapter->hw.phy.autoneg_wait_to_complete = true;
1986 igb_reset(adapter);
1987 adapter->hw.phy.autoneg_wait_to_complete = false;
1988
1989 clear_bit(__IGB_TESTING, &adapter->state);
1990 if (if_running)
1991 dev_open(netdev);
1992 } else {
1993 dev_info(&adapter->pdev->dev, "online testing starting\n");
1994
1995 /* PHY is powered down when interface is down */
1996 if (if_running && igb_link_test(adapter, &data[4]))
1997 eth_test->flags |= ETH_TEST_FL_FAILED;
1998 else
1999 data[4] = 0;
2000
2001 /* Online tests aren't run; pass by default */
2002 data[0] = 0;
2003 data[1] = 0;
2004 data[2] = 0;
2005 data[3] = 0;
2006
2007 clear_bit(__IGB_TESTING, &adapter->state);
2008 }
2009 msleep_interruptible(4 * 1000);
2010 }
2011
2012 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2013 {
2014 struct igb_adapter *adapter = netdev_priv(netdev);
2015
2016 wol->supported = WAKE_UCAST | WAKE_MCAST |
2017 WAKE_BCAST | WAKE_MAGIC |
2018 WAKE_PHY;
2019 wol->wolopts = 0;
2020
2021 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2022 return;
2023
2024 /* apply any specific unsupported masks here */
2025 switch (adapter->hw.device_id) {
2026 default:
2027 break;
2028 }
2029
2030 if (adapter->wol & E1000_WUFC_EX)
2031 wol->wolopts |= WAKE_UCAST;
2032 if (adapter->wol & E1000_WUFC_MC)
2033 wol->wolopts |= WAKE_MCAST;
2034 if (adapter->wol & E1000_WUFC_BC)
2035 wol->wolopts |= WAKE_BCAST;
2036 if (adapter->wol & E1000_WUFC_MAG)
2037 wol->wolopts |= WAKE_MAGIC;
2038 if (adapter->wol & E1000_WUFC_LNKC)
2039 wol->wolopts |= WAKE_PHY;
2040 }
2041
2042 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2043 {
2044 struct igb_adapter *adapter = netdev_priv(netdev);
2045
2046 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2047 return -EOPNOTSUPP;
2048
2049 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2050 return wol->wolopts ? -EOPNOTSUPP : 0;
2051
2052 /* these settings will always override what we currently have */
2053 adapter->wol = 0;
2054
2055 if (wol->wolopts & WAKE_UCAST)
2056 adapter->wol |= E1000_WUFC_EX;
2057 if (wol->wolopts & WAKE_MCAST)
2058 adapter->wol |= E1000_WUFC_MC;
2059 if (wol->wolopts & WAKE_BCAST)
2060 adapter->wol |= E1000_WUFC_BC;
2061 if (wol->wolopts & WAKE_MAGIC)
2062 adapter->wol |= E1000_WUFC_MAG;
2063 if (wol->wolopts & WAKE_PHY)
2064 adapter->wol |= E1000_WUFC_LNKC;
2065 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2066
2067 return 0;
2068 }
2069
2070 /* bit defines for adapter->led_status */
2071 #define IGB_LED_ON 0
2072
2073 static int igb_set_phys_id(struct net_device *netdev,
2074 enum ethtool_phys_id_state state)
2075 {
2076 struct igb_adapter *adapter = netdev_priv(netdev);
2077 struct e1000_hw *hw = &adapter->hw;
2078
2079 switch (state) {
2080 case ETHTOOL_ID_ACTIVE:
2081 igb_blink_led(hw);
2082 return 2;
2083 case ETHTOOL_ID_ON:
2084 igb_blink_led(hw);
2085 break;
2086 case ETHTOOL_ID_OFF:
2087 igb_led_off(hw);
2088 break;
2089 case ETHTOOL_ID_INACTIVE:
2090 igb_led_off(hw);
2091 clear_bit(IGB_LED_ON, &adapter->led_status);
2092 igb_cleanup_led(hw);
2093 break;
2094 }
2095
2096 return 0;
2097 }
2098
2099 static int igb_set_coalesce(struct net_device *netdev,
2100 struct ethtool_coalesce *ec)
2101 {
2102 struct igb_adapter *adapter = netdev_priv(netdev);
2103 int i;
2104
2105 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2106 ((ec->rx_coalesce_usecs > 3) &&
2107 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2108 (ec->rx_coalesce_usecs == 2))
2109 return -EINVAL;
2110
2111 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2112 ((ec->tx_coalesce_usecs > 3) &&
2113 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2114 (ec->tx_coalesce_usecs == 2))
2115 return -EINVAL;
2116
2117 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2118 return -EINVAL;
2119
2120 /* If ITR is disabled, disable DMAC */
2121 if (ec->rx_coalesce_usecs == 0) {
2122 if (adapter->flags & IGB_FLAG_DMAC)
2123 adapter->flags &= ~IGB_FLAG_DMAC;
2124 }
2125
2126 /* convert to rate of irq's per second */
2127 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2128 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2129 else
2130 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2131
2132 /* convert to rate of irq's per second */
2133 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2134 adapter->tx_itr_setting = adapter->rx_itr_setting;
2135 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2136 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2137 else
2138 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2139
2140 for (i = 0; i < adapter->num_q_vectors; i++) {
2141 struct igb_q_vector *q_vector = adapter->q_vector[i];
2142 q_vector->tx.work_limit = adapter->tx_work_limit;
2143 if (q_vector->rx.ring)
2144 q_vector->itr_val = adapter->rx_itr_setting;
2145 else
2146 q_vector->itr_val = adapter->tx_itr_setting;
2147 if (q_vector->itr_val && q_vector->itr_val <= 3)
2148 q_vector->itr_val = IGB_START_ITR;
2149 q_vector->set_itr = 1;
2150 }
2151
2152 return 0;
2153 }
2154
2155 static int igb_get_coalesce(struct net_device *netdev,
2156 struct ethtool_coalesce *ec)
2157 {
2158 struct igb_adapter *adapter = netdev_priv(netdev);
2159
2160 if (adapter->rx_itr_setting <= 3)
2161 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2162 else
2163 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2164
2165 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2166 if (adapter->tx_itr_setting <= 3)
2167 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2168 else
2169 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2170 }
2171
2172 return 0;
2173 }
2174
2175 static int igb_nway_reset(struct net_device *netdev)
2176 {
2177 struct igb_adapter *adapter = netdev_priv(netdev);
2178 if (netif_running(netdev))
2179 igb_reinit_locked(adapter);
2180 return 0;
2181 }
2182
2183 static int igb_get_sset_count(struct net_device *netdev, int sset)
2184 {
2185 switch (sset) {
2186 case ETH_SS_STATS:
2187 return IGB_STATS_LEN;
2188 case ETH_SS_TEST:
2189 return IGB_TEST_LEN;
2190 default:
2191 return -ENOTSUPP;
2192 }
2193 }
2194
2195 static void igb_get_ethtool_stats(struct net_device *netdev,
2196 struct ethtool_stats *stats, u64 *data)
2197 {
2198 struct igb_adapter *adapter = netdev_priv(netdev);
2199 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2200 unsigned int start;
2201 struct igb_ring *ring;
2202 int i, j;
2203 char *p;
2204
2205 spin_lock(&adapter->stats64_lock);
2206 igb_update_stats(adapter, net_stats);
2207
2208 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2209 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2210 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2211 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2212 }
2213 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2214 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2215 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2216 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2217 }
2218 for (j = 0; j < adapter->num_tx_queues; j++) {
2219 u64 restart2;
2220
2221 ring = adapter->tx_ring[j];
2222 do {
2223 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2224 data[i] = ring->tx_stats.packets;
2225 data[i+1] = ring->tx_stats.bytes;
2226 data[i+2] = ring->tx_stats.restart_queue;
2227 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2228 do {
2229 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2230 restart2 = ring->tx_stats.restart_queue2;
2231 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2232 data[i+2] += restart2;
2233
2234 i += IGB_TX_QUEUE_STATS_LEN;
2235 }
2236 for (j = 0; j < adapter->num_rx_queues; j++) {
2237 ring = adapter->rx_ring[j];
2238 do {
2239 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2240 data[i] = ring->rx_stats.packets;
2241 data[i+1] = ring->rx_stats.bytes;
2242 data[i+2] = ring->rx_stats.drops;
2243 data[i+3] = ring->rx_stats.csum_err;
2244 data[i+4] = ring->rx_stats.alloc_failed;
2245 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2246 i += IGB_RX_QUEUE_STATS_LEN;
2247 }
2248 spin_unlock(&adapter->stats64_lock);
2249 }
2250
2251 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2252 {
2253 struct igb_adapter *adapter = netdev_priv(netdev);
2254 u8 *p = data;
2255 int i;
2256
2257 switch (stringset) {
2258 case ETH_SS_TEST:
2259 memcpy(data, *igb_gstrings_test,
2260 IGB_TEST_LEN*ETH_GSTRING_LEN);
2261 break;
2262 case ETH_SS_STATS:
2263 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2264 memcpy(p, igb_gstrings_stats[i].stat_string,
2265 ETH_GSTRING_LEN);
2266 p += ETH_GSTRING_LEN;
2267 }
2268 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2269 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2270 ETH_GSTRING_LEN);
2271 p += ETH_GSTRING_LEN;
2272 }
2273 for (i = 0; i < adapter->num_tx_queues; i++) {
2274 sprintf(p, "tx_queue_%u_packets", i);
2275 p += ETH_GSTRING_LEN;
2276 sprintf(p, "tx_queue_%u_bytes", i);
2277 p += ETH_GSTRING_LEN;
2278 sprintf(p, "tx_queue_%u_restart", i);
2279 p += ETH_GSTRING_LEN;
2280 }
2281 for (i = 0; i < adapter->num_rx_queues; i++) {
2282 sprintf(p, "rx_queue_%u_packets", i);
2283 p += ETH_GSTRING_LEN;
2284 sprintf(p, "rx_queue_%u_bytes", i);
2285 p += ETH_GSTRING_LEN;
2286 sprintf(p, "rx_queue_%u_drops", i);
2287 p += ETH_GSTRING_LEN;
2288 sprintf(p, "rx_queue_%u_csum_err", i);
2289 p += ETH_GSTRING_LEN;
2290 sprintf(p, "rx_queue_%u_alloc_failed", i);
2291 p += ETH_GSTRING_LEN;
2292 }
2293 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2294 break;
2295 }
2296 }
2297
2298 static int igb_get_ts_info(struct net_device *dev,
2299 struct ethtool_ts_info *info)
2300 {
2301 struct igb_adapter *adapter = netdev_priv(dev);
2302
2303 switch (adapter->hw.mac.type) {
2304 case e1000_82575:
2305 info->so_timestamping =
2306 SOF_TIMESTAMPING_TX_SOFTWARE |
2307 SOF_TIMESTAMPING_RX_SOFTWARE |
2308 SOF_TIMESTAMPING_SOFTWARE;
2309 return 0;
2310 case e1000_82576:
2311 case e1000_82580:
2312 case e1000_i350:
2313 case e1000_i210:
2314 case e1000_i211:
2315 info->so_timestamping =
2316 SOF_TIMESTAMPING_TX_SOFTWARE |
2317 SOF_TIMESTAMPING_RX_SOFTWARE |
2318 SOF_TIMESTAMPING_SOFTWARE |
2319 SOF_TIMESTAMPING_TX_HARDWARE |
2320 SOF_TIMESTAMPING_RX_HARDWARE |
2321 SOF_TIMESTAMPING_RAW_HARDWARE;
2322
2323 if (adapter->ptp_clock)
2324 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2325 else
2326 info->phc_index = -1;
2327
2328 info->tx_types =
2329 (1 << HWTSTAMP_TX_OFF) |
2330 (1 << HWTSTAMP_TX_ON);
2331
2332 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
2333
2334 /* 82576 does not support timestamping all packets. */
2335 if (adapter->hw.mac.type >= e1000_82580)
2336 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2337 else
2338 info->rx_filters |=
2339 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2340 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2341 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2342 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2343 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2344 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2345 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2346
2347 return 0;
2348 default:
2349 return -EOPNOTSUPP;
2350 }
2351 }
2352
2353 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2354 struct ethtool_rxnfc *cmd)
2355 {
2356 cmd->data = 0;
2357
2358 /* Report default options for RSS on igb */
2359 switch (cmd->flow_type) {
2360 case TCP_V4_FLOW:
2361 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2362 case UDP_V4_FLOW:
2363 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2364 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2365 case SCTP_V4_FLOW:
2366 case AH_ESP_V4_FLOW:
2367 case AH_V4_FLOW:
2368 case ESP_V4_FLOW:
2369 case IPV4_FLOW:
2370 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2371 break;
2372 case TCP_V6_FLOW:
2373 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2374 case UDP_V6_FLOW:
2375 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2376 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2377 case SCTP_V6_FLOW:
2378 case AH_ESP_V6_FLOW:
2379 case AH_V6_FLOW:
2380 case ESP_V6_FLOW:
2381 case IPV6_FLOW:
2382 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2383 break;
2384 default:
2385 return -EINVAL;
2386 }
2387
2388 return 0;
2389 }
2390
2391 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2392 u32 *rule_locs)
2393 {
2394 struct igb_adapter *adapter = netdev_priv(dev);
2395 int ret = -EOPNOTSUPP;
2396
2397 switch (cmd->cmd) {
2398 case ETHTOOL_GRXRINGS:
2399 cmd->data = adapter->num_rx_queues;
2400 ret = 0;
2401 break;
2402 case ETHTOOL_GRXFH:
2403 ret = igb_get_rss_hash_opts(adapter, cmd);
2404 break;
2405 default:
2406 break;
2407 }
2408
2409 return ret;
2410 }
2411
2412 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2413 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2414 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2415 struct ethtool_rxnfc *nfc)
2416 {
2417 u32 flags = adapter->flags;
2418
2419 /* RSS does not support anything other than hashing
2420 * to queues on src and dst IPs and ports
2421 */
2422 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2423 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2424 return -EINVAL;
2425
2426 switch (nfc->flow_type) {
2427 case TCP_V4_FLOW:
2428 case TCP_V6_FLOW:
2429 if (!(nfc->data & RXH_IP_SRC) ||
2430 !(nfc->data & RXH_IP_DST) ||
2431 !(nfc->data & RXH_L4_B_0_1) ||
2432 !(nfc->data & RXH_L4_B_2_3))
2433 return -EINVAL;
2434 break;
2435 case UDP_V4_FLOW:
2436 if (!(nfc->data & RXH_IP_SRC) ||
2437 !(nfc->data & RXH_IP_DST))
2438 return -EINVAL;
2439 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2440 case 0:
2441 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2442 break;
2443 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2444 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2445 break;
2446 default:
2447 return -EINVAL;
2448 }
2449 break;
2450 case UDP_V6_FLOW:
2451 if (!(nfc->data & RXH_IP_SRC) ||
2452 !(nfc->data & RXH_IP_DST))
2453 return -EINVAL;
2454 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2455 case 0:
2456 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2457 break;
2458 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2459 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2460 break;
2461 default:
2462 return -EINVAL;
2463 }
2464 break;
2465 case AH_ESP_V4_FLOW:
2466 case AH_V4_FLOW:
2467 case ESP_V4_FLOW:
2468 case SCTP_V4_FLOW:
2469 case AH_ESP_V6_FLOW:
2470 case AH_V6_FLOW:
2471 case ESP_V6_FLOW:
2472 case SCTP_V6_FLOW:
2473 if (!(nfc->data & RXH_IP_SRC) ||
2474 !(nfc->data & RXH_IP_DST) ||
2475 (nfc->data & RXH_L4_B_0_1) ||
2476 (nfc->data & RXH_L4_B_2_3))
2477 return -EINVAL;
2478 break;
2479 default:
2480 return -EINVAL;
2481 }
2482
2483 /* if we changed something we need to update flags */
2484 if (flags != adapter->flags) {
2485 struct e1000_hw *hw = &adapter->hw;
2486 u32 mrqc = rd32(E1000_MRQC);
2487
2488 if ((flags & UDP_RSS_FLAGS) &&
2489 !(adapter->flags & UDP_RSS_FLAGS))
2490 dev_err(&adapter->pdev->dev,
2491 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2492
2493 adapter->flags = flags;
2494
2495 /* Perform hash on these packet types */
2496 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2497 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2498 E1000_MRQC_RSS_FIELD_IPV6 |
2499 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2500
2501 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2502 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2503
2504 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2505 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2506
2507 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2508 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2509
2510 wr32(E1000_MRQC, mrqc);
2511 }
2512
2513 return 0;
2514 }
2515
2516 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2517 {
2518 struct igb_adapter *adapter = netdev_priv(dev);
2519 int ret = -EOPNOTSUPP;
2520
2521 switch (cmd->cmd) {
2522 case ETHTOOL_SRXFH:
2523 ret = igb_set_rss_hash_opt(adapter, cmd);
2524 break;
2525 default:
2526 break;
2527 }
2528
2529 return ret;
2530 }
2531
2532 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2533 {
2534 struct igb_adapter *adapter = netdev_priv(netdev);
2535 struct e1000_hw *hw = &adapter->hw;
2536 u32 ipcnfg, eeer;
2537
2538 if ((hw->mac.type < e1000_i350) ||
2539 (hw->phy.media_type != e1000_media_type_copper))
2540 return -EOPNOTSUPP;
2541
2542 edata->supported = (SUPPORTED_1000baseT_Full |
2543 SUPPORTED_100baseT_Full);
2544
2545 ipcnfg = rd32(E1000_IPCNFG);
2546 eeer = rd32(E1000_EEER);
2547
2548 /* EEE status on negotiated link */
2549 if (ipcnfg & E1000_IPCNFG_EEE_1G_AN)
2550 edata->advertised = ADVERTISED_1000baseT_Full;
2551
2552 if (ipcnfg & E1000_IPCNFG_EEE_100M_AN)
2553 edata->advertised |= ADVERTISED_100baseT_Full;
2554
2555 if (eeer & E1000_EEER_EEE_NEG)
2556 edata->eee_active = true;
2557
2558 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2559
2560 if (eeer & E1000_EEER_TX_LPI_EN)
2561 edata->tx_lpi_enabled = true;
2562
2563 /* Report correct negotiated EEE status for devices that
2564 * wrongly report EEE at half-duplex
2565 */
2566 if (adapter->link_duplex == HALF_DUPLEX) {
2567 edata->eee_enabled = false;
2568 edata->eee_active = false;
2569 edata->tx_lpi_enabled = false;
2570 edata->advertised &= ~edata->advertised;
2571 }
2572
2573 return 0;
2574 }
2575
2576 static int igb_set_eee(struct net_device *netdev,
2577 struct ethtool_eee *edata)
2578 {
2579 struct igb_adapter *adapter = netdev_priv(netdev);
2580 struct e1000_hw *hw = &adapter->hw;
2581 struct ethtool_eee eee_curr;
2582 s32 ret_val;
2583
2584 if ((hw->mac.type < e1000_i350) ||
2585 (hw->phy.media_type != e1000_media_type_copper))
2586 return -EOPNOTSUPP;
2587
2588 ret_val = igb_get_eee(netdev, &eee_curr);
2589 if (ret_val)
2590 return ret_val;
2591
2592 if (eee_curr.eee_enabled) {
2593 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2594 dev_err(&adapter->pdev->dev,
2595 "Setting EEE tx-lpi is not supported\n");
2596 return -EINVAL;
2597 }
2598
2599 /* Tx LPI timer is not implemented currently */
2600 if (edata->tx_lpi_timer) {
2601 dev_err(&adapter->pdev->dev,
2602 "Setting EEE Tx LPI timer is not supported\n");
2603 return -EINVAL;
2604 }
2605
2606 if (eee_curr.advertised != edata->advertised) {
2607 dev_err(&adapter->pdev->dev,
2608 "Setting EEE Advertisement is not supported\n");
2609 return -EINVAL;
2610 }
2611
2612 } else if (!edata->eee_enabled) {
2613 dev_err(&adapter->pdev->dev,
2614 "Setting EEE options are not supported with EEE disabled\n");
2615 return -EINVAL;
2616 }
2617
2618 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2619 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2620 igb_set_eee_i350(hw);
2621
2622 /* reset link */
2623 if (!netif_running(netdev))
2624 igb_reset(adapter);
2625 }
2626
2627 return 0;
2628 }
2629
2630 static int igb_get_module_info(struct net_device *netdev,
2631 struct ethtool_modinfo *modinfo)
2632 {
2633 struct igb_adapter *adapter = netdev_priv(netdev);
2634 struct e1000_hw *hw = &adapter->hw;
2635 u32 status = E1000_SUCCESS;
2636 u16 sff8472_rev, addr_mode;
2637 bool page_swap = false;
2638
2639 if ((hw->phy.media_type == e1000_media_type_copper) ||
2640 (hw->phy.media_type == e1000_media_type_unknown))
2641 return -EOPNOTSUPP;
2642
2643 /* Check whether we support SFF-8472 or not */
2644 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
2645 if (status != E1000_SUCCESS)
2646 return -EIO;
2647
2648 /* addressing mode is not supported */
2649 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
2650 if (status != E1000_SUCCESS)
2651 return -EIO;
2652
2653 /* addressing mode is not supported */
2654 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
2655 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2656 page_swap = true;
2657 }
2658
2659 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
2660 /* We have an SFP, but it does not support SFF-8472 */
2661 modinfo->type = ETH_MODULE_SFF_8079;
2662 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2663 } else {
2664 /* We have an SFP which supports a revision of SFF-8472 */
2665 modinfo->type = ETH_MODULE_SFF_8472;
2666 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2667 }
2668
2669 return 0;
2670 }
2671
2672 static int igb_get_module_eeprom(struct net_device *netdev,
2673 struct ethtool_eeprom *ee, u8 *data)
2674 {
2675 struct igb_adapter *adapter = netdev_priv(netdev);
2676 struct e1000_hw *hw = &adapter->hw;
2677 u32 status = E1000_SUCCESS;
2678 u16 *dataword;
2679 u16 first_word, last_word;
2680 int i = 0;
2681
2682 if (ee->len == 0)
2683 return -EINVAL;
2684
2685 first_word = ee->offset >> 1;
2686 last_word = (ee->offset + ee->len - 1) >> 1;
2687
2688 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
2689 GFP_KERNEL);
2690 if (!dataword)
2691 return -ENOMEM;
2692
2693 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
2694 for (i = 0; i < last_word - first_word + 1; i++) {
2695 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
2696 if (status != E1000_SUCCESS)
2697 /* Error occurred while reading module */
2698 return -EIO;
2699
2700 be16_to_cpus(&dataword[i]);
2701 }
2702
2703 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
2704 kfree(dataword);
2705
2706 return 0;
2707 }
2708
2709 static int igb_ethtool_begin(struct net_device *netdev)
2710 {
2711 struct igb_adapter *adapter = netdev_priv(netdev);
2712 pm_runtime_get_sync(&adapter->pdev->dev);
2713 return 0;
2714 }
2715
2716 static void igb_ethtool_complete(struct net_device *netdev)
2717 {
2718 struct igb_adapter *adapter = netdev_priv(netdev);
2719 pm_runtime_put(&adapter->pdev->dev);
2720 }
2721
2722 static const struct ethtool_ops igb_ethtool_ops = {
2723 .get_settings = igb_get_settings,
2724 .set_settings = igb_set_settings,
2725 .get_drvinfo = igb_get_drvinfo,
2726 .get_regs_len = igb_get_regs_len,
2727 .get_regs = igb_get_regs,
2728 .get_wol = igb_get_wol,
2729 .set_wol = igb_set_wol,
2730 .get_msglevel = igb_get_msglevel,
2731 .set_msglevel = igb_set_msglevel,
2732 .nway_reset = igb_nway_reset,
2733 .get_link = igb_get_link,
2734 .get_eeprom_len = igb_get_eeprom_len,
2735 .get_eeprom = igb_get_eeprom,
2736 .set_eeprom = igb_set_eeprom,
2737 .get_ringparam = igb_get_ringparam,
2738 .set_ringparam = igb_set_ringparam,
2739 .get_pauseparam = igb_get_pauseparam,
2740 .set_pauseparam = igb_set_pauseparam,
2741 .self_test = igb_diag_test,
2742 .get_strings = igb_get_strings,
2743 .set_phys_id = igb_set_phys_id,
2744 .get_sset_count = igb_get_sset_count,
2745 .get_ethtool_stats = igb_get_ethtool_stats,
2746 .get_coalesce = igb_get_coalesce,
2747 .set_coalesce = igb_set_coalesce,
2748 .get_ts_info = igb_get_ts_info,
2749 .get_rxnfc = igb_get_rxnfc,
2750 .set_rxnfc = igb_set_rxnfc,
2751 .get_eee = igb_get_eee,
2752 .set_eee = igb_set_eee,
2753 .get_module_info = igb_get_module_info,
2754 .get_module_eeprom = igb_get_module_eeprom,
2755 .begin = igb_ethtool_begin,
2756 .complete = igb_ethtool_complete,
2757 };
2758
2759 void igb_set_ethtool_ops(struct net_device *netdev)
2760 {
2761 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2762 }
Linux kernel - Deliverables
This page took 0.094229 seconds and 5 git commands to generate.