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ixgbe: Add X550 support function pointers
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_common.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/netdevice.h>
33
34 #include "ixgbe.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37
38 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
39 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
40 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
41 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
42 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
44 u16 count);
45 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
46 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
47 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
49
50 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
51 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
52 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
57 u16 offset);
58 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
59
60 /**
61 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
62 * control
63 * @hw: pointer to hardware structure
64 *
65 * There are several phys that do not support autoneg flow control. This
66 * function check the device id to see if the associated phy supports
67 * autoneg flow control.
68 **/
69 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
70 {
71 bool supported = false;
72 ixgbe_link_speed speed;
73 bool link_up;
74
75 switch (hw->phy.media_type) {
76 case ixgbe_media_type_fiber:
77 hw->mac.ops.check_link(hw, &speed, &link_up, false);
78 /* if link is down, assume supported */
79 if (link_up)
80 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
81 true : false;
82 else
83 supported = true;
84 break;
85 case ixgbe_media_type_backplane:
86 supported = true;
87 break;
88 case ixgbe_media_type_copper:
89 /* only some copper devices support flow control autoneg */
90 switch (hw->device_id) {
91 case IXGBE_DEV_ID_82599_T3_LOM:
92 case IXGBE_DEV_ID_X540T:
93 case IXGBE_DEV_ID_X540T1:
94 supported = true;
95 break;
96 default:
97 break;
98 }
99 default:
100 break;
101 }
102
103 return supported;
104 }
105
106 /**
107 * ixgbe_setup_fc - Set up flow control
108 * @hw: pointer to hardware structure
109 *
110 * Called at init time to set up flow control.
111 **/
112 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
113 {
114 s32 ret_val = 0;
115 u32 reg = 0, reg_bp = 0;
116 u16 reg_cu = 0;
117 bool locked = false;
118
119 /*
120 * Validate the requested mode. Strict IEEE mode does not allow
121 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
122 */
123 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
124 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
125 return IXGBE_ERR_INVALID_LINK_SETTINGS;
126 }
127
128 /*
129 * 10gig parts do not have a word in the EEPROM to determine the
130 * default flow control setting, so we explicitly set it to full.
131 */
132 if (hw->fc.requested_mode == ixgbe_fc_default)
133 hw->fc.requested_mode = ixgbe_fc_full;
134
135 /*
136 * Set up the 1G and 10G flow control advertisement registers so the
137 * HW will be able to do fc autoneg once the cable is plugged in. If
138 * we link at 10G, the 1G advertisement is harmless and vice versa.
139 */
140 switch (hw->phy.media_type) {
141 case ixgbe_media_type_backplane:
142 /* some MAC's need RMW protection on AUTOC */
143 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &reg_bp);
144 if (ret_val)
145 return ret_val;
146
147 /* only backplane uses autoc so fall though */
148 case ixgbe_media_type_fiber:
149 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
150
151 break;
152 case ixgbe_media_type_copper:
153 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
154 MDIO_MMD_AN, &reg_cu);
155 break;
156 default:
157 break;
158 }
159
160 /*
161 * The possible values of fc.requested_mode are:
162 * 0: Flow control is completely disabled
163 * 1: Rx flow control is enabled (we can receive pause frames,
164 * but not send pause frames).
165 * 2: Tx flow control is enabled (we can send pause frames but
166 * we do not support receiving pause frames).
167 * 3: Both Rx and Tx flow control (symmetric) are enabled.
168 * other: Invalid.
169 */
170 switch (hw->fc.requested_mode) {
171 case ixgbe_fc_none:
172 /* Flow control completely disabled by software override. */
173 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
174 if (hw->phy.media_type == ixgbe_media_type_backplane)
175 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
176 IXGBE_AUTOC_ASM_PAUSE);
177 else if (hw->phy.media_type == ixgbe_media_type_copper)
178 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
179 break;
180 case ixgbe_fc_tx_pause:
181 /*
182 * Tx Flow control is enabled, and Rx Flow control is
183 * disabled by software override.
184 */
185 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
186 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
187 if (hw->phy.media_type == ixgbe_media_type_backplane) {
188 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
189 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
190 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
191 reg_cu |= IXGBE_TAF_ASM_PAUSE;
192 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
193 }
194 break;
195 case ixgbe_fc_rx_pause:
196 /*
197 * Rx Flow control is enabled and Tx Flow control is
198 * disabled by software override. Since there really
199 * isn't a way to advertise that we are capable of RX
200 * Pause ONLY, we will advertise that we support both
201 * symmetric and asymmetric Rx PAUSE, as such we fall
202 * through to the fc_full statement. Later, we will
203 * disable the adapter's ability to send PAUSE frames.
204 */
205 case ixgbe_fc_full:
206 /* Flow control (both Rx and Tx) is enabled by SW override. */
207 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
208 if (hw->phy.media_type == ixgbe_media_type_backplane)
209 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
210 IXGBE_AUTOC_ASM_PAUSE;
211 else if (hw->phy.media_type == ixgbe_media_type_copper)
212 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
213 break;
214 default:
215 hw_dbg(hw, "Flow control param set incorrectly\n");
216 return IXGBE_ERR_CONFIG;
217 }
218
219 if (hw->mac.type != ixgbe_mac_X540) {
220 /*
221 * Enable auto-negotiation between the MAC & PHY;
222 * the MAC will advertise clause 37 flow control.
223 */
224 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
225 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
226
227 /* Disable AN timeout */
228 if (hw->fc.strict_ieee)
229 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
230
231 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
232 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
233 }
234
235 /*
236 * AUTOC restart handles negotiation of 1G and 10G on backplane
237 * and copper. There is no need to set the PCS1GCTL register.
238 *
239 */
240 if (hw->phy.media_type == ixgbe_media_type_backplane) {
241 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
242 * LESM is on, likewise reset_pipeline requries the lock as
243 * it also writes AUTOC.
244 */
245 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
246 if (ret_val)
247 return ret_val;
248
249 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
250 ixgbe_device_supports_autoneg_fc(hw)) {
251 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
252 MDIO_MMD_AN, reg_cu);
253 }
254
255 hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
256 return ret_val;
257 }
258
259 /**
260 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
261 * @hw: pointer to hardware structure
262 *
263 * Starts the hardware by filling the bus info structure and media type, clears
264 * all on chip counters, initializes receive address registers, multicast
265 * table, VLAN filter table, calls routine to set up link and flow control
266 * settings, and leaves transmit and receive units disabled and uninitialized
267 **/
268 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
269 {
270 s32 ret_val;
271 u32 ctrl_ext;
272
273 /* Set the media type */
274 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
275
276 /* Identify the PHY */
277 hw->phy.ops.identify(hw);
278
279 /* Clear the VLAN filter table */
280 hw->mac.ops.clear_vfta(hw);
281
282 /* Clear statistics registers */
283 hw->mac.ops.clear_hw_cntrs(hw);
284
285 /* Set No Snoop Disable */
286 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
287 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
288 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
289 IXGBE_WRITE_FLUSH(hw);
290
291 /* Setup flow control */
292 ret_val = ixgbe_setup_fc(hw);
293 if (!ret_val)
294 return 0;
295
296 /* Clear adapter stopped flag */
297 hw->adapter_stopped = false;
298
299 return ret_val;
300 }
301
302 /**
303 * ixgbe_start_hw_gen2 - Init sequence for common device family
304 * @hw: pointer to hw structure
305 *
306 * Performs the init sequence common to the second generation
307 * of 10 GbE devices.
308 * Devices in the second generation:
309 * 82599
310 * X540
311 **/
312 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
313 {
314 u32 i;
315 u32 regval;
316
317 /* Clear the rate limiters */
318 for (i = 0; i < hw->mac.max_tx_queues; i++) {
319 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
320 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
321 }
322 IXGBE_WRITE_FLUSH(hw);
323
324 /* Disable relaxed ordering */
325 for (i = 0; i < hw->mac.max_tx_queues; i++) {
326 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
327 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
328 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
329 }
330
331 for (i = 0; i < hw->mac.max_rx_queues; i++) {
332 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
333 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
334 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
335 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
336 }
337
338 return 0;
339 }
340
341 /**
342 * ixgbe_init_hw_generic - Generic hardware initialization
343 * @hw: pointer to hardware structure
344 *
345 * Initialize the hardware by resetting the hardware, filling the bus info
346 * structure and media type, clears all on chip counters, initializes receive
347 * address registers, multicast table, VLAN filter table, calls routine to set
348 * up link and flow control settings, and leaves transmit and receive units
349 * disabled and uninitialized
350 **/
351 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
352 {
353 s32 status;
354
355 /* Reset the hardware */
356 status = hw->mac.ops.reset_hw(hw);
357
358 if (status == 0) {
359 /* Start the HW */
360 status = hw->mac.ops.start_hw(hw);
361 }
362
363 return status;
364 }
365
366 /**
367 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
368 * @hw: pointer to hardware structure
369 *
370 * Clears all hardware statistics counters by reading them from the hardware
371 * Statistics counters are clear on read.
372 **/
373 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
374 {
375 u16 i = 0;
376
377 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
378 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
379 IXGBE_READ_REG(hw, IXGBE_ERRBC);
380 IXGBE_READ_REG(hw, IXGBE_MSPDC);
381 for (i = 0; i < 8; i++)
382 IXGBE_READ_REG(hw, IXGBE_MPC(i));
383
384 IXGBE_READ_REG(hw, IXGBE_MLFC);
385 IXGBE_READ_REG(hw, IXGBE_MRFC);
386 IXGBE_READ_REG(hw, IXGBE_RLEC);
387 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
388 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
389 if (hw->mac.type >= ixgbe_mac_82599EB) {
390 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
391 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
392 } else {
393 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
394 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
395 }
396
397 for (i = 0; i < 8; i++) {
398 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
399 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
400 if (hw->mac.type >= ixgbe_mac_82599EB) {
401 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
402 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
403 } else {
404 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
405 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
406 }
407 }
408 if (hw->mac.type >= ixgbe_mac_82599EB)
409 for (i = 0; i < 8; i++)
410 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
411 IXGBE_READ_REG(hw, IXGBE_PRC64);
412 IXGBE_READ_REG(hw, IXGBE_PRC127);
413 IXGBE_READ_REG(hw, IXGBE_PRC255);
414 IXGBE_READ_REG(hw, IXGBE_PRC511);
415 IXGBE_READ_REG(hw, IXGBE_PRC1023);
416 IXGBE_READ_REG(hw, IXGBE_PRC1522);
417 IXGBE_READ_REG(hw, IXGBE_GPRC);
418 IXGBE_READ_REG(hw, IXGBE_BPRC);
419 IXGBE_READ_REG(hw, IXGBE_MPRC);
420 IXGBE_READ_REG(hw, IXGBE_GPTC);
421 IXGBE_READ_REG(hw, IXGBE_GORCL);
422 IXGBE_READ_REG(hw, IXGBE_GORCH);
423 IXGBE_READ_REG(hw, IXGBE_GOTCL);
424 IXGBE_READ_REG(hw, IXGBE_GOTCH);
425 if (hw->mac.type == ixgbe_mac_82598EB)
426 for (i = 0; i < 8; i++)
427 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
428 IXGBE_READ_REG(hw, IXGBE_RUC);
429 IXGBE_READ_REG(hw, IXGBE_RFC);
430 IXGBE_READ_REG(hw, IXGBE_ROC);
431 IXGBE_READ_REG(hw, IXGBE_RJC);
432 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
433 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
434 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
435 IXGBE_READ_REG(hw, IXGBE_TORL);
436 IXGBE_READ_REG(hw, IXGBE_TORH);
437 IXGBE_READ_REG(hw, IXGBE_TPR);
438 IXGBE_READ_REG(hw, IXGBE_TPT);
439 IXGBE_READ_REG(hw, IXGBE_PTC64);
440 IXGBE_READ_REG(hw, IXGBE_PTC127);
441 IXGBE_READ_REG(hw, IXGBE_PTC255);
442 IXGBE_READ_REG(hw, IXGBE_PTC511);
443 IXGBE_READ_REG(hw, IXGBE_PTC1023);
444 IXGBE_READ_REG(hw, IXGBE_PTC1522);
445 IXGBE_READ_REG(hw, IXGBE_MPTC);
446 IXGBE_READ_REG(hw, IXGBE_BPTC);
447 for (i = 0; i < 16; i++) {
448 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
449 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
450 if (hw->mac.type >= ixgbe_mac_82599EB) {
451 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
452 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
453 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
454 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
455 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
456 } else {
457 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
458 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
459 }
460 }
461
462 if (hw->mac.type == ixgbe_mac_X540) {
463 if (hw->phy.id == 0)
464 hw->phy.ops.identify(hw);
465 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
466 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
467 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
468 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
469 }
470
471 return 0;
472 }
473
474 /**
475 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
476 * @hw: pointer to hardware structure
477 * @pba_num: stores the part number string from the EEPROM
478 * @pba_num_size: part number string buffer length
479 *
480 * Reads the part number string from the EEPROM.
481 **/
482 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
483 u32 pba_num_size)
484 {
485 s32 ret_val;
486 u16 data;
487 u16 pba_ptr;
488 u16 offset;
489 u16 length;
490
491 if (pba_num == NULL) {
492 hw_dbg(hw, "PBA string buffer was null\n");
493 return IXGBE_ERR_INVALID_ARGUMENT;
494 }
495
496 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
497 if (ret_val) {
498 hw_dbg(hw, "NVM Read Error\n");
499 return ret_val;
500 }
501
502 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
503 if (ret_val) {
504 hw_dbg(hw, "NVM Read Error\n");
505 return ret_val;
506 }
507
508 /*
509 * if data is not ptr guard the PBA must be in legacy format which
510 * means pba_ptr is actually our second data word for the PBA number
511 * and we can decode it into an ascii string
512 */
513 if (data != IXGBE_PBANUM_PTR_GUARD) {
514 hw_dbg(hw, "NVM PBA number is not stored as string\n");
515
516 /* we will need 11 characters to store the PBA */
517 if (pba_num_size < 11) {
518 hw_dbg(hw, "PBA string buffer too small\n");
519 return IXGBE_ERR_NO_SPACE;
520 }
521
522 /* extract hex string from data and pba_ptr */
523 pba_num[0] = (data >> 12) & 0xF;
524 pba_num[1] = (data >> 8) & 0xF;
525 pba_num[2] = (data >> 4) & 0xF;
526 pba_num[3] = data & 0xF;
527 pba_num[4] = (pba_ptr >> 12) & 0xF;
528 pba_num[5] = (pba_ptr >> 8) & 0xF;
529 pba_num[6] = '-';
530 pba_num[7] = 0;
531 pba_num[8] = (pba_ptr >> 4) & 0xF;
532 pba_num[9] = pba_ptr & 0xF;
533
534 /* put a null character on the end of our string */
535 pba_num[10] = '\0';
536
537 /* switch all the data but the '-' to hex char */
538 for (offset = 0; offset < 10; offset++) {
539 if (pba_num[offset] < 0xA)
540 pba_num[offset] += '0';
541 else if (pba_num[offset] < 0x10)
542 pba_num[offset] += 'A' - 0xA;
543 }
544
545 return 0;
546 }
547
548 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
549 if (ret_val) {
550 hw_dbg(hw, "NVM Read Error\n");
551 return ret_val;
552 }
553
554 if (length == 0xFFFF || length == 0) {
555 hw_dbg(hw, "NVM PBA number section invalid length\n");
556 return IXGBE_ERR_PBA_SECTION;
557 }
558
559 /* check if pba_num buffer is big enough */
560 if (pba_num_size < (((u32)length * 2) - 1)) {
561 hw_dbg(hw, "PBA string buffer too small\n");
562 return IXGBE_ERR_NO_SPACE;
563 }
564
565 /* trim pba length from start of string */
566 pba_ptr++;
567 length--;
568
569 for (offset = 0; offset < length; offset++) {
570 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
571 if (ret_val) {
572 hw_dbg(hw, "NVM Read Error\n");
573 return ret_val;
574 }
575 pba_num[offset * 2] = (u8)(data >> 8);
576 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
577 }
578 pba_num[offset * 2] = '\0';
579
580 return 0;
581 }
582
583 /**
584 * ixgbe_get_mac_addr_generic - Generic get MAC address
585 * @hw: pointer to hardware structure
586 * @mac_addr: Adapter MAC address
587 *
588 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
589 * A reset of the adapter must be performed prior to calling this function
590 * in order for the MAC address to have been loaded from the EEPROM into RAR0
591 **/
592 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
593 {
594 u32 rar_high;
595 u32 rar_low;
596 u16 i;
597
598 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
599 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
600
601 for (i = 0; i < 4; i++)
602 mac_addr[i] = (u8)(rar_low >> (i*8));
603
604 for (i = 0; i < 2; i++)
605 mac_addr[i+4] = (u8)(rar_high >> (i*8));
606
607 return 0;
608 }
609
610 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
611 {
612 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
613 case IXGBE_PCI_LINK_WIDTH_1:
614 return ixgbe_bus_width_pcie_x1;
615 case IXGBE_PCI_LINK_WIDTH_2:
616 return ixgbe_bus_width_pcie_x2;
617 case IXGBE_PCI_LINK_WIDTH_4:
618 return ixgbe_bus_width_pcie_x4;
619 case IXGBE_PCI_LINK_WIDTH_8:
620 return ixgbe_bus_width_pcie_x8;
621 default:
622 return ixgbe_bus_width_unknown;
623 }
624 }
625
626 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
627 {
628 switch (link_status & IXGBE_PCI_LINK_SPEED) {
629 case IXGBE_PCI_LINK_SPEED_2500:
630 return ixgbe_bus_speed_2500;
631 case IXGBE_PCI_LINK_SPEED_5000:
632 return ixgbe_bus_speed_5000;
633 case IXGBE_PCI_LINK_SPEED_8000:
634 return ixgbe_bus_speed_8000;
635 default:
636 return ixgbe_bus_speed_unknown;
637 }
638 }
639
640 /**
641 * ixgbe_get_bus_info_generic - Generic set PCI bus info
642 * @hw: pointer to hardware structure
643 *
644 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
645 **/
646 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
647 {
648 u16 link_status;
649
650 hw->bus.type = ixgbe_bus_type_pci_express;
651
652 /* Get the negotiated link width and speed from PCI config space */
653 link_status = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_LINK_STATUS);
654
655 hw->bus.width = ixgbe_convert_bus_width(link_status);
656 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
657
658 hw->mac.ops.set_lan_id(hw);
659
660 return 0;
661 }
662
663 /**
664 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
665 * @hw: pointer to the HW structure
666 *
667 * Determines the LAN function id by reading memory-mapped registers
668 * and swaps the port value if requested.
669 **/
670 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
671 {
672 struct ixgbe_bus_info *bus = &hw->bus;
673 u32 reg;
674
675 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
676 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
677 bus->lan_id = bus->func;
678
679 /* check for a port swap */
680 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
681 if (reg & IXGBE_FACTPS_LFS)
682 bus->func ^= 0x1;
683 }
684
685 /**
686 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
687 * @hw: pointer to hardware structure
688 *
689 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
690 * disables transmit and receive units. The adapter_stopped flag is used by
691 * the shared code and drivers to determine if the adapter is in a stopped
692 * state and should not touch the hardware.
693 **/
694 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
695 {
696 u32 reg_val;
697 u16 i;
698
699 /*
700 * Set the adapter_stopped flag so other driver functions stop touching
701 * the hardware
702 */
703 hw->adapter_stopped = true;
704
705 /* Disable the receive unit */
706 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
707
708 /* Clear interrupt mask to stop interrupts from being generated */
709 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
710
711 /* Clear any pending interrupts, flush previous writes */
712 IXGBE_READ_REG(hw, IXGBE_EICR);
713
714 /* Disable the transmit unit. Each queue must be disabled. */
715 for (i = 0; i < hw->mac.max_tx_queues; i++)
716 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
717
718 /* Disable the receive unit by stopping each queue */
719 for (i = 0; i < hw->mac.max_rx_queues; i++) {
720 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
721 reg_val &= ~IXGBE_RXDCTL_ENABLE;
722 reg_val |= IXGBE_RXDCTL_SWFLSH;
723 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
724 }
725
726 /* flush all queues disables */
727 IXGBE_WRITE_FLUSH(hw);
728 usleep_range(1000, 2000);
729
730 /*
731 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
732 * access and verify no pending requests
733 */
734 return ixgbe_disable_pcie_master(hw);
735 }
736
737 /**
738 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
739 * @hw: pointer to hardware structure
740 * @index: led number to turn on
741 **/
742 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
743 {
744 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
745
746 /* To turn on the LED, set mode to ON. */
747 led_reg &= ~IXGBE_LED_MODE_MASK(index);
748 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
749 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
750 IXGBE_WRITE_FLUSH(hw);
751
752 return 0;
753 }
754
755 /**
756 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
757 * @hw: pointer to hardware structure
758 * @index: led number to turn off
759 **/
760 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
761 {
762 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
763
764 /* To turn off the LED, set mode to OFF. */
765 led_reg &= ~IXGBE_LED_MODE_MASK(index);
766 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
767 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
768 IXGBE_WRITE_FLUSH(hw);
769
770 return 0;
771 }
772
773 /**
774 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
775 * @hw: pointer to hardware structure
776 *
777 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
778 * ixgbe_hw struct in order to set up EEPROM access.
779 **/
780 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
781 {
782 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
783 u32 eec;
784 u16 eeprom_size;
785
786 if (eeprom->type == ixgbe_eeprom_uninitialized) {
787 eeprom->type = ixgbe_eeprom_none;
788 /* Set default semaphore delay to 10ms which is a well
789 * tested value */
790 eeprom->semaphore_delay = 10;
791 /* Clear EEPROM page size, it will be initialized as needed */
792 eeprom->word_page_size = 0;
793
794 /*
795 * Check for EEPROM present first.
796 * If not present leave as none
797 */
798 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
799 if (eec & IXGBE_EEC_PRES) {
800 eeprom->type = ixgbe_eeprom_spi;
801
802 /*
803 * SPI EEPROM is assumed here. This code would need to
804 * change if a future EEPROM is not SPI.
805 */
806 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
807 IXGBE_EEC_SIZE_SHIFT);
808 eeprom->word_size = 1 << (eeprom_size +
809 IXGBE_EEPROM_WORD_SIZE_SHIFT);
810 }
811
812 if (eec & IXGBE_EEC_ADDR_SIZE)
813 eeprom->address_bits = 16;
814 else
815 eeprom->address_bits = 8;
816 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: %d\n",
817 eeprom->type, eeprom->word_size, eeprom->address_bits);
818 }
819
820 return 0;
821 }
822
823 /**
824 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
825 * @hw: pointer to hardware structure
826 * @offset: offset within the EEPROM to write
827 * @words: number of words
828 * @data: 16 bit word(s) to write to EEPROM
829 *
830 * Reads 16 bit word(s) from EEPROM through bit-bang method
831 **/
832 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
833 u16 words, u16 *data)
834 {
835 s32 status;
836 u16 i, count;
837
838 hw->eeprom.ops.init_params(hw);
839
840 if (words == 0)
841 return IXGBE_ERR_INVALID_ARGUMENT;
842
843 if (offset + words > hw->eeprom.word_size)
844 return IXGBE_ERR_EEPROM;
845
846 /*
847 * The EEPROM page size cannot be queried from the chip. We do lazy
848 * initialization. It is worth to do that when we write large buffer.
849 */
850 if ((hw->eeprom.word_page_size == 0) &&
851 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
852 ixgbe_detect_eeprom_page_size_generic(hw, offset);
853
854 /*
855 * We cannot hold synchronization semaphores for too long
856 * to avoid other entity starvation. However it is more efficient
857 * to read in bursts than synchronizing access for each word.
858 */
859 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
860 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
861 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
862 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
863 count, &data[i]);
864
865 if (status != 0)
866 break;
867 }
868
869 return status;
870 }
871
872 /**
873 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
874 * @hw: pointer to hardware structure
875 * @offset: offset within the EEPROM to be written to
876 * @words: number of word(s)
877 * @data: 16 bit word(s) to be written to the EEPROM
878 *
879 * If ixgbe_eeprom_update_checksum is not called after this function, the
880 * EEPROM will most likely contain an invalid checksum.
881 **/
882 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
883 u16 words, u16 *data)
884 {
885 s32 status;
886 u16 word;
887 u16 page_size;
888 u16 i;
889 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
890
891 /* Prepare the EEPROM for writing */
892 status = ixgbe_acquire_eeprom(hw);
893 if (status)
894 return status;
895
896 if (ixgbe_ready_eeprom(hw) != 0) {
897 ixgbe_release_eeprom(hw);
898 return IXGBE_ERR_EEPROM;
899 }
900
901 for (i = 0; i < words; i++) {
902 ixgbe_standby_eeprom(hw);
903
904 /* Send the WRITE ENABLE command (8 bit opcode) */
905 ixgbe_shift_out_eeprom_bits(hw,
906 IXGBE_EEPROM_WREN_OPCODE_SPI,
907 IXGBE_EEPROM_OPCODE_BITS);
908
909 ixgbe_standby_eeprom(hw);
910
911 /* Some SPI eeproms use the 8th address bit embedded
912 * in the opcode
913 */
914 if ((hw->eeprom.address_bits == 8) &&
915 ((offset + i) >= 128))
916 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
917
918 /* Send the Write command (8-bit opcode + addr) */
919 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
920 IXGBE_EEPROM_OPCODE_BITS);
921 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
922 hw->eeprom.address_bits);
923
924 page_size = hw->eeprom.word_page_size;
925
926 /* Send the data in burst via SPI */
927 do {
928 word = data[i];
929 word = (word >> 8) | (word << 8);
930 ixgbe_shift_out_eeprom_bits(hw, word, 16);
931
932 if (page_size == 0)
933 break;
934
935 /* do not wrap around page */
936 if (((offset + i) & (page_size - 1)) ==
937 (page_size - 1))
938 break;
939 } while (++i < words);
940
941 ixgbe_standby_eeprom(hw);
942 usleep_range(10000, 20000);
943 }
944 /* Done with writing - release the EEPROM */
945 ixgbe_release_eeprom(hw);
946
947 return 0;
948 }
949
950 /**
951 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
952 * @hw: pointer to hardware structure
953 * @offset: offset within the EEPROM to be written to
954 * @data: 16 bit word to be written to the EEPROM
955 *
956 * If ixgbe_eeprom_update_checksum is not called after this function, the
957 * EEPROM will most likely contain an invalid checksum.
958 **/
959 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
960 {
961 hw->eeprom.ops.init_params(hw);
962
963 if (offset >= hw->eeprom.word_size)
964 return IXGBE_ERR_EEPROM;
965
966 return ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
967 }
968
969 /**
970 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
971 * @hw: pointer to hardware structure
972 * @offset: offset within the EEPROM to be read
973 * @words: number of word(s)
974 * @data: read 16 bit words(s) from EEPROM
975 *
976 * Reads 16 bit word(s) from EEPROM through bit-bang method
977 **/
978 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
979 u16 words, u16 *data)
980 {
981 s32 status;
982 u16 i, count;
983
984 hw->eeprom.ops.init_params(hw);
985
986 if (words == 0)
987 return IXGBE_ERR_INVALID_ARGUMENT;
988
989 if (offset + words > hw->eeprom.word_size)
990 return IXGBE_ERR_EEPROM;
991
992 /*
993 * We cannot hold synchronization semaphores for too long
994 * to avoid other entity starvation. However it is more efficient
995 * to read in bursts than synchronizing access for each word.
996 */
997 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
998 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
999 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1000
1001 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1002 count, &data[i]);
1003
1004 if (status)
1005 return status;
1006 }
1007
1008 return 0;
1009 }
1010
1011 /**
1012 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1013 * @hw: pointer to hardware structure
1014 * @offset: offset within the EEPROM to be read
1015 * @words: number of word(s)
1016 * @data: read 16 bit word(s) from EEPROM
1017 *
1018 * Reads 16 bit word(s) from EEPROM through bit-bang method
1019 **/
1020 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1021 u16 words, u16 *data)
1022 {
1023 s32 status;
1024 u16 word_in;
1025 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1026 u16 i;
1027
1028 /* Prepare the EEPROM for reading */
1029 status = ixgbe_acquire_eeprom(hw);
1030 if (status)
1031 return status;
1032
1033 if (ixgbe_ready_eeprom(hw) != 0) {
1034 ixgbe_release_eeprom(hw);
1035 return IXGBE_ERR_EEPROM;
1036 }
1037
1038 for (i = 0; i < words; i++) {
1039 ixgbe_standby_eeprom(hw);
1040 /* Some SPI eeproms use the 8th address bit embedded
1041 * in the opcode
1042 */
1043 if ((hw->eeprom.address_bits == 8) &&
1044 ((offset + i) >= 128))
1045 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1046
1047 /* Send the READ command (opcode + addr) */
1048 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1049 IXGBE_EEPROM_OPCODE_BITS);
1050 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1051 hw->eeprom.address_bits);
1052
1053 /* Read the data. */
1054 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1055 data[i] = (word_in >> 8) | (word_in << 8);
1056 }
1057
1058 /* End this read operation */
1059 ixgbe_release_eeprom(hw);
1060
1061 return 0;
1062 }
1063
1064 /**
1065 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1066 * @hw: pointer to hardware structure
1067 * @offset: offset within the EEPROM to be read
1068 * @data: read 16 bit value from EEPROM
1069 *
1070 * Reads 16 bit value from EEPROM through bit-bang method
1071 **/
1072 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1073 u16 *data)
1074 {
1075 hw->eeprom.ops.init_params(hw);
1076
1077 if (offset >= hw->eeprom.word_size)
1078 return IXGBE_ERR_EEPROM;
1079
1080 return ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1081 }
1082
1083 /**
1084 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1085 * @hw: pointer to hardware structure
1086 * @offset: offset of word in the EEPROM to read
1087 * @words: number of word(s)
1088 * @data: 16 bit word(s) from the EEPROM
1089 *
1090 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1091 **/
1092 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1093 u16 words, u16 *data)
1094 {
1095 u32 eerd;
1096 s32 status;
1097 u32 i;
1098
1099 hw->eeprom.ops.init_params(hw);
1100
1101 if (words == 0)
1102 return IXGBE_ERR_INVALID_ARGUMENT;
1103
1104 if (offset >= hw->eeprom.word_size)
1105 return IXGBE_ERR_EEPROM;
1106
1107 for (i = 0; i < words; i++) {
1108 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1109 IXGBE_EEPROM_RW_REG_START;
1110
1111 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1112 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1113
1114 if (status == 0) {
1115 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1116 IXGBE_EEPROM_RW_REG_DATA);
1117 } else {
1118 hw_dbg(hw, "Eeprom read timed out\n");
1119 return status;
1120 }
1121 }
1122
1123 return 0;
1124 }
1125
1126 /**
1127 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1128 * @hw: pointer to hardware structure
1129 * @offset: offset within the EEPROM to be used as a scratch pad
1130 *
1131 * Discover EEPROM page size by writing marching data at given offset.
1132 * This function is called only when we are writing a new large buffer
1133 * at given offset so the data would be overwritten anyway.
1134 **/
1135 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1136 u16 offset)
1137 {
1138 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1139 s32 status;
1140 u16 i;
1141
1142 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1143 data[i] = i;
1144
1145 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1146 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1147 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1148 hw->eeprom.word_page_size = 0;
1149 if (status)
1150 return status;
1151
1152 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1153 if (status)
1154 return status;
1155
1156 /*
1157 * When writing in burst more than the actual page size
1158 * EEPROM address wraps around current page.
1159 */
1160 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1161
1162 hw_dbg(hw, "Detected EEPROM page size = %d words.\n",
1163 hw->eeprom.word_page_size);
1164 return 0;
1165 }
1166
1167 /**
1168 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1169 * @hw: pointer to hardware structure
1170 * @offset: offset of word in the EEPROM to read
1171 * @data: word read from the EEPROM
1172 *
1173 * Reads a 16 bit word from the EEPROM using the EERD register.
1174 **/
1175 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1176 {
1177 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1178 }
1179
1180 /**
1181 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1182 * @hw: pointer to hardware structure
1183 * @offset: offset of word in the EEPROM to write
1184 * @words: number of words
1185 * @data: word(s) write to the EEPROM
1186 *
1187 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1188 **/
1189 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1190 u16 words, u16 *data)
1191 {
1192 u32 eewr;
1193 s32 status;
1194 u16 i;
1195
1196 hw->eeprom.ops.init_params(hw);
1197
1198 if (words == 0)
1199 return IXGBE_ERR_INVALID_ARGUMENT;
1200
1201 if (offset >= hw->eeprom.word_size)
1202 return IXGBE_ERR_EEPROM;
1203
1204 for (i = 0; i < words; i++) {
1205 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1206 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1207 IXGBE_EEPROM_RW_REG_START;
1208
1209 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1210 if (status) {
1211 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1212 return status;
1213 }
1214
1215 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1216
1217 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1218 if (status) {
1219 hw_dbg(hw, "Eeprom write EEWR timed out\n");
1220 return status;
1221 }
1222 }
1223
1224 return 0;
1225 }
1226
1227 /**
1228 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1229 * @hw: pointer to hardware structure
1230 * @offset: offset of word in the EEPROM to write
1231 * @data: word write to the EEPROM
1232 *
1233 * Write a 16 bit word to the EEPROM using the EEWR register.
1234 **/
1235 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1236 {
1237 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1238 }
1239
1240 /**
1241 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1242 * @hw: pointer to hardware structure
1243 * @ee_reg: EEPROM flag for polling
1244 *
1245 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1246 * read or write is done respectively.
1247 **/
1248 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1249 {
1250 u32 i;
1251 u32 reg;
1252
1253 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1254 if (ee_reg == IXGBE_NVM_POLL_READ)
1255 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1256 else
1257 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1258
1259 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1260 return 0;
1261 }
1262 udelay(5);
1263 }
1264 return IXGBE_ERR_EEPROM;
1265 }
1266
1267 /**
1268 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1269 * @hw: pointer to hardware structure
1270 *
1271 * Prepares EEPROM for access using bit-bang method. This function should
1272 * be called before issuing a command to the EEPROM.
1273 **/
1274 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1275 {
1276 u32 eec;
1277 u32 i;
1278
1279 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
1280 return IXGBE_ERR_SWFW_SYNC;
1281
1282 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1283
1284 /* Request EEPROM Access */
1285 eec |= IXGBE_EEC_REQ;
1286 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1287
1288 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1289 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1290 if (eec & IXGBE_EEC_GNT)
1291 break;
1292 udelay(5);
1293 }
1294
1295 /* Release if grant not acquired */
1296 if (!(eec & IXGBE_EEC_GNT)) {
1297 eec &= ~IXGBE_EEC_REQ;
1298 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1299 hw_dbg(hw, "Could not acquire EEPROM grant\n");
1300
1301 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1302 return IXGBE_ERR_EEPROM;
1303 }
1304
1305 /* Setup EEPROM for Read/Write */
1306 /* Clear CS and SK */
1307 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1308 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1309 IXGBE_WRITE_FLUSH(hw);
1310 udelay(1);
1311 return 0;
1312 }
1313
1314 /**
1315 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1316 * @hw: pointer to hardware structure
1317 *
1318 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1319 **/
1320 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1321 {
1322 u32 timeout = 2000;
1323 u32 i;
1324 u32 swsm;
1325
1326 /* Get SMBI software semaphore between device drivers first */
1327 for (i = 0; i < timeout; i++) {
1328 /*
1329 * If the SMBI bit is 0 when we read it, then the bit will be
1330 * set and we have the semaphore
1331 */
1332 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1333 if (!(swsm & IXGBE_SWSM_SMBI))
1334 break;
1335 usleep_range(50, 100);
1336 }
1337
1338 if (i == timeout) {
1339 hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore not granted.\n");
1340 /* this release is particularly important because our attempts
1341 * above to get the semaphore may have succeeded, and if there
1342 * was a timeout, we should unconditionally clear the semaphore
1343 * bits to free the driver to make progress
1344 */
1345 ixgbe_release_eeprom_semaphore(hw);
1346
1347 usleep_range(50, 100);
1348 /* one last try
1349 * If the SMBI bit is 0 when we read it, then the bit will be
1350 * set and we have the semaphore
1351 */
1352 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1353 if (swsm & IXGBE_SWSM_SMBI) {
1354 hw_dbg(hw, "Software semaphore SMBI between device drivers not granted.\n");
1355 return IXGBE_ERR_EEPROM;
1356 }
1357 }
1358
1359 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1360 for (i = 0; i < timeout; i++) {
1361 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1362
1363 /* Set the SW EEPROM semaphore bit to request access */
1364 swsm |= IXGBE_SWSM_SWESMBI;
1365 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1366
1367 /* If we set the bit successfully then we got the
1368 * semaphore.
1369 */
1370 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1371 if (swsm & IXGBE_SWSM_SWESMBI)
1372 break;
1373
1374 usleep_range(50, 100);
1375 }
1376
1377 /* Release semaphores and return error if SW EEPROM semaphore
1378 * was not granted because we don't have access to the EEPROM
1379 */
1380 if (i >= timeout) {
1381 hw_dbg(hw, "SWESMBI Software EEPROM semaphore not granted.\n");
1382 ixgbe_release_eeprom_semaphore(hw);
1383 return IXGBE_ERR_EEPROM;
1384 }
1385
1386 return 0;
1387 }
1388
1389 /**
1390 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1391 * @hw: pointer to hardware structure
1392 *
1393 * This function clears hardware semaphore bits.
1394 **/
1395 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1396 {
1397 u32 swsm;
1398
1399 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1400
1401 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1402 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1403 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1404 IXGBE_WRITE_FLUSH(hw);
1405 }
1406
1407 /**
1408 * ixgbe_ready_eeprom - Polls for EEPROM ready
1409 * @hw: pointer to hardware structure
1410 **/
1411 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1412 {
1413 u16 i;
1414 u8 spi_stat_reg;
1415
1416 /*
1417 * Read "Status Register" repeatedly until the LSB is cleared. The
1418 * EEPROM will signal that the command has been completed by clearing
1419 * bit 0 of the internal status register. If it's not cleared within
1420 * 5 milliseconds, then error out.
1421 */
1422 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1423 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1424 IXGBE_EEPROM_OPCODE_BITS);
1425 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1426 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1427 break;
1428
1429 udelay(5);
1430 ixgbe_standby_eeprom(hw);
1431 }
1432
1433 /*
1434 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1435 * devices (and only 0-5mSec on 5V devices)
1436 */
1437 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1438 hw_dbg(hw, "SPI EEPROM Status error\n");
1439 return IXGBE_ERR_EEPROM;
1440 }
1441
1442 return 0;
1443 }
1444
1445 /**
1446 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1447 * @hw: pointer to hardware structure
1448 **/
1449 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1450 {
1451 u32 eec;
1452
1453 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1454
1455 /* Toggle CS to flush commands */
1456 eec |= IXGBE_EEC_CS;
1457 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1458 IXGBE_WRITE_FLUSH(hw);
1459 udelay(1);
1460 eec &= ~IXGBE_EEC_CS;
1461 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1462 IXGBE_WRITE_FLUSH(hw);
1463 udelay(1);
1464 }
1465
1466 /**
1467 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1468 * @hw: pointer to hardware structure
1469 * @data: data to send to the EEPROM
1470 * @count: number of bits to shift out
1471 **/
1472 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1473 u16 count)
1474 {
1475 u32 eec;
1476 u32 mask;
1477 u32 i;
1478
1479 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1480
1481 /*
1482 * Mask is used to shift "count" bits of "data" out to the EEPROM
1483 * one bit at a time. Determine the starting bit based on count
1484 */
1485 mask = 0x01 << (count - 1);
1486
1487 for (i = 0; i < count; i++) {
1488 /*
1489 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1490 * "1", and then raising and then lowering the clock (the SK
1491 * bit controls the clock input to the EEPROM). A "0" is
1492 * shifted out to the EEPROM by setting "DI" to "0" and then
1493 * raising and then lowering the clock.
1494 */
1495 if (data & mask)
1496 eec |= IXGBE_EEC_DI;
1497 else
1498 eec &= ~IXGBE_EEC_DI;
1499
1500 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1501 IXGBE_WRITE_FLUSH(hw);
1502
1503 udelay(1);
1504
1505 ixgbe_raise_eeprom_clk(hw, &eec);
1506 ixgbe_lower_eeprom_clk(hw, &eec);
1507
1508 /*
1509 * Shift mask to signify next bit of data to shift in to the
1510 * EEPROM
1511 */
1512 mask = mask >> 1;
1513 }
1514
1515 /* We leave the "DI" bit set to "0" when we leave this routine. */
1516 eec &= ~IXGBE_EEC_DI;
1517 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1518 IXGBE_WRITE_FLUSH(hw);
1519 }
1520
1521 /**
1522 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1523 * @hw: pointer to hardware structure
1524 **/
1525 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1526 {
1527 u32 eec;
1528 u32 i;
1529 u16 data = 0;
1530
1531 /*
1532 * In order to read a register from the EEPROM, we need to shift
1533 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1534 * the clock input to the EEPROM (setting the SK bit), and then reading
1535 * the value of the "DO" bit. During this "shifting in" process the
1536 * "DI" bit should always be clear.
1537 */
1538 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1539
1540 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1541
1542 for (i = 0; i < count; i++) {
1543 data = data << 1;
1544 ixgbe_raise_eeprom_clk(hw, &eec);
1545
1546 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1547
1548 eec &= ~(IXGBE_EEC_DI);
1549 if (eec & IXGBE_EEC_DO)
1550 data |= 1;
1551
1552 ixgbe_lower_eeprom_clk(hw, &eec);
1553 }
1554
1555 return data;
1556 }
1557
1558 /**
1559 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1560 * @hw: pointer to hardware structure
1561 * @eec: EEC register's current value
1562 **/
1563 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1564 {
1565 /*
1566 * Raise the clock input to the EEPROM
1567 * (setting the SK bit), then delay
1568 */
1569 *eec = *eec | IXGBE_EEC_SK;
1570 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1571 IXGBE_WRITE_FLUSH(hw);
1572 udelay(1);
1573 }
1574
1575 /**
1576 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
1577 * @hw: pointer to hardware structure
1578 * @eecd: EECD's current value
1579 **/
1580 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
1581 {
1582 /*
1583 * Lower the clock input to the EEPROM (clearing the SK bit), then
1584 * delay
1585 */
1586 *eec = *eec & ~IXGBE_EEC_SK;
1587 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
1588 IXGBE_WRITE_FLUSH(hw);
1589 udelay(1);
1590 }
1591
1592 /**
1593 * ixgbe_release_eeprom - Release EEPROM, release semaphores
1594 * @hw: pointer to hardware structure
1595 **/
1596 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1597 {
1598 u32 eec;
1599
1600 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1601
1602 eec |= IXGBE_EEC_CS; /* Pull CS high */
1603 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1604
1605 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1606 IXGBE_WRITE_FLUSH(hw);
1607
1608 udelay(1);
1609
1610 /* Stop requesting EEPROM access */
1611 eec &= ~IXGBE_EEC_REQ;
1612 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1613
1614 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1615
1616 /*
1617 * Delay before attempt to obtain semaphore again to allow FW
1618 * access. semaphore_delay is in ms we need us for usleep_range
1619 */
1620 usleep_range(hw->eeprom.semaphore_delay * 1000,
1621 hw->eeprom.semaphore_delay * 2000);
1622 }
1623
1624 /**
1625 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1626 * @hw: pointer to hardware structure
1627 **/
1628 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1629 {
1630 u16 i;
1631 u16 j;
1632 u16 checksum = 0;
1633 u16 length = 0;
1634 u16 pointer = 0;
1635 u16 word = 0;
1636
1637 /* Include 0x0-0x3F in the checksum */
1638 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1639 if (hw->eeprom.ops.read(hw, i, &word)) {
1640 hw_dbg(hw, "EEPROM read failed\n");
1641 break;
1642 }
1643 checksum += word;
1644 }
1645
1646 /* Include all data from pointers except for the fw pointer */
1647 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1648 if (hw->eeprom.ops.read(hw, i, &pointer)) {
1649 hw_dbg(hw, "EEPROM read failed\n");
1650 return IXGBE_ERR_EEPROM;
1651 }
1652
1653 /* If the pointer seems invalid */
1654 if (pointer == 0xFFFF || pointer == 0)
1655 continue;
1656
1657 if (hw->eeprom.ops.read(hw, pointer, &length)) {
1658 hw_dbg(hw, "EEPROM read failed\n");
1659 return IXGBE_ERR_EEPROM;
1660 }
1661
1662 if (length == 0xFFFF || length == 0)
1663 continue;
1664
1665 for (j = pointer + 1; j <= pointer + length; j++) {
1666 if (hw->eeprom.ops.read(hw, j, &word)) {
1667 hw_dbg(hw, "EEPROM read failed\n");
1668 return IXGBE_ERR_EEPROM;
1669 }
1670 checksum += word;
1671 }
1672 }
1673
1674 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1675
1676 return (s32)checksum;
1677 }
1678
1679 /**
1680 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1681 * @hw: pointer to hardware structure
1682 * @checksum_val: calculated checksum
1683 *
1684 * Performs checksum calculation and validates the EEPROM checksum. If the
1685 * caller does not need checksum_val, the value can be NULL.
1686 **/
1687 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1688 u16 *checksum_val)
1689 {
1690 s32 status;
1691 u16 checksum;
1692 u16 read_checksum = 0;
1693
1694 /*
1695 * Read the first word from the EEPROM. If this times out or fails, do
1696 * not continue or we could be in for a very long wait while every
1697 * EEPROM read fails
1698 */
1699 status = hw->eeprom.ops.read(hw, 0, &checksum);
1700 if (status) {
1701 hw_dbg(hw, "EEPROM read failed\n");
1702 return status;
1703 }
1704
1705 status = hw->eeprom.ops.calc_checksum(hw);
1706 if (status < 0)
1707 return status;
1708
1709 checksum = (u16)(status & 0xffff);
1710
1711 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1712 if (status) {
1713 hw_dbg(hw, "EEPROM read failed\n");
1714 return status;
1715 }
1716
1717 /* Verify read checksum from EEPROM is the same as
1718 * calculated checksum
1719 */
1720 if (read_checksum != checksum)
1721 status = IXGBE_ERR_EEPROM_CHECKSUM;
1722
1723 /* If the user cares, return the calculated checksum */
1724 if (checksum_val)
1725 *checksum_val = checksum;
1726
1727 return status;
1728 }
1729
1730 /**
1731 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1732 * @hw: pointer to hardware structure
1733 **/
1734 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1735 {
1736 s32 status;
1737 u16 checksum;
1738
1739 /*
1740 * Read the first word from the EEPROM. If this times out or fails, do
1741 * not continue or we could be in for a very long wait while every
1742 * EEPROM read fails
1743 */
1744 status = hw->eeprom.ops.read(hw, 0, &checksum);
1745 if (status) {
1746 hw_dbg(hw, "EEPROM read failed\n");
1747 return status;
1748 }
1749
1750 status = hw->eeprom.ops.calc_checksum(hw);
1751 if (status < 0)
1752 return status;
1753
1754 checksum = (u16)(status & 0xffff);
1755
1756 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
1757
1758 return status;
1759 }
1760
1761 /**
1762 * ixgbe_set_rar_generic - Set Rx address register
1763 * @hw: pointer to hardware structure
1764 * @index: Receive address register to write
1765 * @addr: Address to put into receive address register
1766 * @vmdq: VMDq "set" or "pool" index
1767 * @enable_addr: set flag that address is active
1768 *
1769 * Puts an ethernet address into a receive address register.
1770 **/
1771 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1772 u32 enable_addr)
1773 {
1774 u32 rar_low, rar_high;
1775 u32 rar_entries = hw->mac.num_rar_entries;
1776
1777 /* Make sure we are using a valid rar index range */
1778 if (index >= rar_entries) {
1779 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1780 return IXGBE_ERR_INVALID_ARGUMENT;
1781 }
1782
1783 /* setup VMDq pool selection before this RAR gets enabled */
1784 hw->mac.ops.set_vmdq(hw, index, vmdq);
1785
1786 /*
1787 * HW expects these in little endian so we reverse the byte
1788 * order from network order (big endian) to little endian
1789 */
1790 rar_low = ((u32)addr[0] |
1791 ((u32)addr[1] << 8) |
1792 ((u32)addr[2] << 16) |
1793 ((u32)addr[3] << 24));
1794 /*
1795 * Some parts put the VMDq setting in the extra RAH bits,
1796 * so save everything except the lower 16 bits that hold part
1797 * of the address and the address valid bit.
1798 */
1799 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1800 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1801 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1802
1803 if (enable_addr != 0)
1804 rar_high |= IXGBE_RAH_AV;
1805
1806 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1807 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1808
1809 return 0;
1810 }
1811
1812 /**
1813 * ixgbe_clear_rar_generic - Remove Rx address register
1814 * @hw: pointer to hardware structure
1815 * @index: Receive address register to write
1816 *
1817 * Clears an ethernet address from a receive address register.
1818 **/
1819 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1820 {
1821 u32 rar_high;
1822 u32 rar_entries = hw->mac.num_rar_entries;
1823
1824 /* Make sure we are using a valid rar index range */
1825 if (index >= rar_entries) {
1826 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1827 return IXGBE_ERR_INVALID_ARGUMENT;
1828 }
1829
1830 /*
1831 * Some parts put the VMDq setting in the extra RAH bits,
1832 * so save everything except the lower 16 bits that hold part
1833 * of the address and the address valid bit.
1834 */
1835 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1836 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1837
1838 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1839 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1840
1841 /* clear VMDq pool/queue selection for this RAR */
1842 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1843
1844 return 0;
1845 }
1846
1847 /**
1848 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1849 * @hw: pointer to hardware structure
1850 *
1851 * Places the MAC address in receive address register 0 and clears the rest
1852 * of the receive address registers. Clears the multicast table. Assumes
1853 * the receiver is in reset when the routine is called.
1854 **/
1855 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1856 {
1857 u32 i;
1858 u32 rar_entries = hw->mac.num_rar_entries;
1859
1860 /*
1861 * If the current mac address is valid, assume it is a software override
1862 * to the permanent address.
1863 * Otherwise, use the permanent address from the eeprom.
1864 */
1865 if (!is_valid_ether_addr(hw->mac.addr)) {
1866 /* Get the MAC address from the RAR0 for later reference */
1867 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1868
1869 hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
1870 } else {
1871 /* Setup the receive address. */
1872 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1873 hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
1874
1875 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1876
1877 /* clear VMDq pool/queue selection for RAR 0 */
1878 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
1879 }
1880 hw->addr_ctrl.overflow_promisc = 0;
1881
1882 hw->addr_ctrl.rar_used_count = 1;
1883
1884 /* Zero out the other receive addresses. */
1885 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1886 for (i = 1; i < rar_entries; i++) {
1887 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1888 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1889 }
1890
1891 /* Clear the MTA */
1892 hw->addr_ctrl.mta_in_use = 0;
1893 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1894
1895 hw_dbg(hw, " Clearing MTA\n");
1896 for (i = 0; i < hw->mac.mcft_size; i++)
1897 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1898
1899 if (hw->mac.ops.init_uta_tables)
1900 hw->mac.ops.init_uta_tables(hw);
1901
1902 return 0;
1903 }
1904
1905 /**
1906 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1907 * @hw: pointer to hardware structure
1908 * @mc_addr: the multicast address
1909 *
1910 * Extracts the 12 bits, from a multicast address, to determine which
1911 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1912 * incoming rx multicast addresses, to determine the bit-vector to check in
1913 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1914 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1915 * to mc_filter_type.
1916 **/
1917 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1918 {
1919 u32 vector = 0;
1920
1921 switch (hw->mac.mc_filter_type) {
1922 case 0: /* use bits [47:36] of the address */
1923 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1924 break;
1925 case 1: /* use bits [46:35] of the address */
1926 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1927 break;
1928 case 2: /* use bits [45:34] of the address */
1929 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1930 break;
1931 case 3: /* use bits [43:32] of the address */
1932 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1933 break;
1934 default: /* Invalid mc_filter_type */
1935 hw_dbg(hw, "MC filter type param set incorrectly\n");
1936 break;
1937 }
1938
1939 /* vector can only be 12-bits or boundary will be exceeded */
1940 vector &= 0xFFF;
1941 return vector;
1942 }
1943
1944 /**
1945 * ixgbe_set_mta - Set bit-vector in multicast table
1946 * @hw: pointer to hardware structure
1947 * @hash_value: Multicast address hash value
1948 *
1949 * Sets the bit-vector in the multicast table.
1950 **/
1951 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1952 {
1953 u32 vector;
1954 u32 vector_bit;
1955 u32 vector_reg;
1956
1957 hw->addr_ctrl.mta_in_use++;
1958
1959 vector = ixgbe_mta_vector(hw, mc_addr);
1960 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1961
1962 /*
1963 * The MTA is a register array of 128 32-bit registers. It is treated
1964 * like an array of 4096 bits. We want to set bit
1965 * BitArray[vector_value]. So we figure out what register the bit is
1966 * in, read it, OR in the new bit, then write back the new value. The
1967 * register is determined by the upper 7 bits of the vector value and
1968 * the bit within that register are determined by the lower 5 bits of
1969 * the value.
1970 */
1971 vector_reg = (vector >> 5) & 0x7F;
1972 vector_bit = vector & 0x1F;
1973 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
1974 }
1975
1976 /**
1977 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1978 * @hw: pointer to hardware structure
1979 * @netdev: pointer to net device structure
1980 *
1981 * The given list replaces any existing list. Clears the MC addrs from receive
1982 * address registers and the multicast table. Uses unused receive address
1983 * registers for the first multicast addresses, and hashes the rest into the
1984 * multicast table.
1985 **/
1986 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
1987 struct net_device *netdev)
1988 {
1989 struct netdev_hw_addr *ha;
1990 u32 i;
1991
1992 /*
1993 * Set the new number of MC addresses that we are being requested to
1994 * use.
1995 */
1996 hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
1997 hw->addr_ctrl.mta_in_use = 0;
1998
1999 /* Clear mta_shadow */
2000 hw_dbg(hw, " Clearing MTA\n");
2001 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2002
2003 /* Update mta shadow */
2004 netdev_for_each_mc_addr(ha, netdev) {
2005 hw_dbg(hw, " Adding the multicast addresses:\n");
2006 ixgbe_set_mta(hw, ha->addr);
2007 }
2008
2009 /* Enable mta */
2010 for (i = 0; i < hw->mac.mcft_size; i++)
2011 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2012 hw->mac.mta_shadow[i]);
2013
2014 if (hw->addr_ctrl.mta_in_use > 0)
2015 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2016 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2017
2018 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
2019 return 0;
2020 }
2021
2022 /**
2023 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2024 * @hw: pointer to hardware structure
2025 *
2026 * Enables multicast address in RAR and the use of the multicast hash table.
2027 **/
2028 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2029 {
2030 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2031
2032 if (a->mta_in_use > 0)
2033 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2034 hw->mac.mc_filter_type);
2035
2036 return 0;
2037 }
2038
2039 /**
2040 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2041 * @hw: pointer to hardware structure
2042 *
2043 * Disables multicast address in RAR and the use of the multicast hash table.
2044 **/
2045 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2046 {
2047 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2048
2049 if (a->mta_in_use > 0)
2050 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2051
2052 return 0;
2053 }
2054
2055 /**
2056 * ixgbe_fc_enable_generic - Enable flow control
2057 * @hw: pointer to hardware structure
2058 *
2059 * Enable flow control according to the current settings.
2060 **/
2061 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2062 {
2063 u32 mflcn_reg, fccfg_reg;
2064 u32 reg;
2065 u32 fcrtl, fcrth;
2066 int i;
2067
2068 /* Validate the water mark configuration. */
2069 if (!hw->fc.pause_time)
2070 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2071
2072 /* Low water mark of zero causes XOFF floods */
2073 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2074 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2075 hw->fc.high_water[i]) {
2076 if (!hw->fc.low_water[i] ||
2077 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2078 hw_dbg(hw, "Invalid water mark configuration\n");
2079 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2080 }
2081 }
2082 }
2083
2084 /* Negotiate the fc mode to use */
2085 ixgbe_fc_autoneg(hw);
2086
2087 /* Disable any previous flow control settings */
2088 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2089 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2090
2091 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2092 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2093
2094 /*
2095 * The possible values of fc.current_mode are:
2096 * 0: Flow control is completely disabled
2097 * 1: Rx flow control is enabled (we can receive pause frames,
2098 * but not send pause frames).
2099 * 2: Tx flow control is enabled (we can send pause frames but
2100 * we do not support receiving pause frames).
2101 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2102 * other: Invalid.
2103 */
2104 switch (hw->fc.current_mode) {
2105 case ixgbe_fc_none:
2106 /*
2107 * Flow control is disabled by software override or autoneg.
2108 * The code below will actually disable it in the HW.
2109 */
2110 break;
2111 case ixgbe_fc_rx_pause:
2112 /*
2113 * Rx Flow control is enabled and Tx Flow control is
2114 * disabled by software override. Since there really
2115 * isn't a way to advertise that we are capable of RX
2116 * Pause ONLY, we will advertise that we support both
2117 * symmetric and asymmetric Rx PAUSE. Later, we will
2118 * disable the adapter's ability to send PAUSE frames.
2119 */
2120 mflcn_reg |= IXGBE_MFLCN_RFCE;
2121 break;
2122 case ixgbe_fc_tx_pause:
2123 /*
2124 * Tx Flow control is enabled, and Rx Flow control is
2125 * disabled by software override.
2126 */
2127 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2128 break;
2129 case ixgbe_fc_full:
2130 /* Flow control (both Rx and Tx) is enabled by SW override. */
2131 mflcn_reg |= IXGBE_MFLCN_RFCE;
2132 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2133 break;
2134 default:
2135 hw_dbg(hw, "Flow control param set incorrectly\n");
2136 return IXGBE_ERR_CONFIG;
2137 }
2138
2139 /* Set 802.3x based flow control settings. */
2140 mflcn_reg |= IXGBE_MFLCN_DPF;
2141 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2142 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2143
2144 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2145 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
2146 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2147 hw->fc.high_water[i]) {
2148 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2149 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2150 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2151 } else {
2152 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2153 /*
2154 * In order to prevent Tx hangs when the internal Tx
2155 * switch is enabled we must set the high water mark
2156 * to the maximum FCRTH value. This allows the Tx
2157 * switch to function even under heavy Rx workloads.
2158 */
2159 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2160 }
2161
2162 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2163 }
2164
2165 /* Configure pause time (2 TCs per register) */
2166 reg = hw->fc.pause_time * 0x00010001;
2167 for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
2168 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2169
2170 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2171
2172 return 0;
2173 }
2174
2175 /**
2176 * ixgbe_negotiate_fc - Negotiate flow control
2177 * @hw: pointer to hardware structure
2178 * @adv_reg: flow control advertised settings
2179 * @lp_reg: link partner's flow control settings
2180 * @adv_sym: symmetric pause bit in advertisement
2181 * @adv_asm: asymmetric pause bit in advertisement
2182 * @lp_sym: symmetric pause bit in link partner advertisement
2183 * @lp_asm: asymmetric pause bit in link partner advertisement
2184 *
2185 * Find the intersection between advertised settings and link partner's
2186 * advertised settings
2187 **/
2188 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2189 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2190 {
2191 if ((!(adv_reg)) || (!(lp_reg)))
2192 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2193
2194 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2195 /*
2196 * Now we need to check if the user selected Rx ONLY
2197 * of pause frames. In this case, we had to advertise
2198 * FULL flow control because we could not advertise RX
2199 * ONLY. Hence, we must now check to see if we need to
2200 * turn OFF the TRANSMISSION of PAUSE frames.
2201 */
2202 if (hw->fc.requested_mode == ixgbe_fc_full) {
2203 hw->fc.current_mode = ixgbe_fc_full;
2204 hw_dbg(hw, "Flow Control = FULL.\n");
2205 } else {
2206 hw->fc.current_mode = ixgbe_fc_rx_pause;
2207 hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
2208 }
2209 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2210 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2211 hw->fc.current_mode = ixgbe_fc_tx_pause;
2212 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
2213 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2214 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2215 hw->fc.current_mode = ixgbe_fc_rx_pause;
2216 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
2217 } else {
2218 hw->fc.current_mode = ixgbe_fc_none;
2219 hw_dbg(hw, "Flow Control = NONE.\n");
2220 }
2221 return 0;
2222 }
2223
2224 /**
2225 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2226 * @hw: pointer to hardware structure
2227 *
2228 * Enable flow control according on 1 gig fiber.
2229 **/
2230 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2231 {
2232 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2233 s32 ret_val;
2234
2235 /*
2236 * On multispeed fiber at 1g, bail out if
2237 * - link is up but AN did not complete, or if
2238 * - link is up and AN completed but timed out
2239 */
2240
2241 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2242 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2243 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2244 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2245
2246 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2247 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2248
2249 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2250 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2251 IXGBE_PCS1GANA_ASM_PAUSE,
2252 IXGBE_PCS1GANA_SYM_PAUSE,
2253 IXGBE_PCS1GANA_ASM_PAUSE);
2254
2255 return ret_val;
2256 }
2257
2258 /**
2259 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2260 * @hw: pointer to hardware structure
2261 *
2262 * Enable flow control according to IEEE clause 37.
2263 **/
2264 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2265 {
2266 u32 links2, anlp1_reg, autoc_reg, links;
2267 s32 ret_val;
2268
2269 /*
2270 * On backplane, bail out if
2271 * - backplane autoneg was not completed, or if
2272 * - we are 82599 and link partner is not AN enabled
2273 */
2274 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2275 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2276 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2277
2278 if (hw->mac.type == ixgbe_mac_82599EB) {
2279 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2280 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2281 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2282 }
2283 /*
2284 * Read the 10g AN autoc and LP ability registers and resolve
2285 * local flow control settings accordingly
2286 */
2287 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2288 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2289
2290 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2291 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2292 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2293
2294 return ret_val;
2295 }
2296
2297 /**
2298 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2299 * @hw: pointer to hardware structure
2300 *
2301 * Enable flow control according to IEEE clause 37.
2302 **/
2303 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2304 {
2305 u16 technology_ability_reg = 0;
2306 u16 lp_technology_ability_reg = 0;
2307
2308 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
2309 MDIO_MMD_AN,
2310 &technology_ability_reg);
2311 hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
2312 MDIO_MMD_AN,
2313 &lp_technology_ability_reg);
2314
2315 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2316 (u32)lp_technology_ability_reg,
2317 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2318 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2319 }
2320
2321 /**
2322 * ixgbe_fc_autoneg - Configure flow control
2323 * @hw: pointer to hardware structure
2324 *
2325 * Compares our advertised flow control capabilities to those advertised by
2326 * our link partner, and determines the proper flow control mode to use.
2327 **/
2328 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2329 {
2330 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2331 ixgbe_link_speed speed;
2332 bool link_up;
2333
2334 /*
2335 * AN should have completed when the cable was plugged in.
2336 * Look for reasons to bail out. Bail out if:
2337 * - FC autoneg is disabled, or if
2338 * - link is not up.
2339 *
2340 * Since we're being called from an LSC, link is already known to be up.
2341 * So use link_up_wait_to_complete=false.
2342 */
2343 if (hw->fc.disable_fc_autoneg)
2344 goto out;
2345
2346 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2347 if (!link_up)
2348 goto out;
2349
2350 switch (hw->phy.media_type) {
2351 /* Autoneg flow control on fiber adapters */
2352 case ixgbe_media_type_fiber:
2353 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2354 ret_val = ixgbe_fc_autoneg_fiber(hw);
2355 break;
2356
2357 /* Autoneg flow control on backplane adapters */
2358 case ixgbe_media_type_backplane:
2359 ret_val = ixgbe_fc_autoneg_backplane(hw);
2360 break;
2361
2362 /* Autoneg flow control on copper adapters */
2363 case ixgbe_media_type_copper:
2364 if (ixgbe_device_supports_autoneg_fc(hw))
2365 ret_val = ixgbe_fc_autoneg_copper(hw);
2366 break;
2367
2368 default:
2369 break;
2370 }
2371
2372 out:
2373 if (ret_val == 0) {
2374 hw->fc.fc_was_autonegged = true;
2375 } else {
2376 hw->fc.fc_was_autonegged = false;
2377 hw->fc.current_mode = hw->fc.requested_mode;
2378 }
2379 }
2380
2381 /**
2382 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2383 * @hw: pointer to hardware structure
2384 *
2385 * System-wide timeout range is encoded in PCIe Device Control2 register.
2386 *
2387 * Add 10% to specified maximum and return the number of times to poll for
2388 * completion timeout, in units of 100 microsec. Never return less than
2389 * 800 = 80 millisec.
2390 **/
2391 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
2392 {
2393 s16 devctl2;
2394 u32 pollcnt;
2395
2396 devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
2397 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
2398
2399 switch (devctl2) {
2400 case IXGBE_PCIDEVCTRL2_65_130ms:
2401 pollcnt = 1300; /* 130 millisec */
2402 break;
2403 case IXGBE_PCIDEVCTRL2_260_520ms:
2404 pollcnt = 5200; /* 520 millisec */
2405 break;
2406 case IXGBE_PCIDEVCTRL2_1_2s:
2407 pollcnt = 20000; /* 2 sec */
2408 break;
2409 case IXGBE_PCIDEVCTRL2_4_8s:
2410 pollcnt = 80000; /* 8 sec */
2411 break;
2412 case IXGBE_PCIDEVCTRL2_17_34s:
2413 pollcnt = 34000; /* 34 sec */
2414 break;
2415 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
2416 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
2417 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
2418 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
2419 default:
2420 pollcnt = 800; /* 80 millisec minimum */
2421 break;
2422 }
2423
2424 /* add 10% to spec maximum */
2425 return (pollcnt * 11) / 10;
2426 }
2427
2428 /**
2429 * ixgbe_disable_pcie_master - Disable PCI-express master access
2430 * @hw: pointer to hardware structure
2431 *
2432 * Disables PCI-Express master access and verifies there are no pending
2433 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2434 * bit hasn't caused the master requests to be disabled, else 0
2435 * is returned signifying master requests disabled.
2436 **/
2437 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2438 {
2439 u32 i, poll;
2440 u16 value;
2441
2442 /* Always set this bit to ensure any future transactions are blocked */
2443 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2444
2445 /* Exit if master requests are blocked */
2446 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
2447 ixgbe_removed(hw->hw_addr))
2448 return 0;
2449
2450 /* Poll for master request bit to clear */
2451 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2452 udelay(100);
2453 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2454 return 0;
2455 }
2456
2457 /*
2458 * Two consecutive resets are required via CTRL.RST per datasheet
2459 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2460 * of this need. The first reset prevents new master requests from
2461 * being issued by our device. We then must wait 1usec or more for any
2462 * remaining completions from the PCIe bus to trickle in, and then reset
2463 * again to clear out any effects they may have had on our device.
2464 */
2465 hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
2466 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2467
2468 /*
2469 * Before proceeding, make sure that the PCIe block does not have
2470 * transactions pending.
2471 */
2472 poll = ixgbe_pcie_timeout_poll(hw);
2473 for (i = 0; i < poll; i++) {
2474 udelay(100);
2475 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
2476 if (ixgbe_removed(hw->hw_addr))
2477 return 0;
2478 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2479 return 0;
2480 }
2481
2482 hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
2483 return IXGBE_ERR_MASTER_REQUESTS_PENDING;
2484 }
2485
2486 /**
2487 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2488 * @hw: pointer to hardware structure
2489 * @mask: Mask to specify which semaphore to acquire
2490 *
2491 * Acquires the SWFW semaphore through the GSSR register for the specified
2492 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2493 **/
2494 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2495 {
2496 u32 gssr = 0;
2497 u32 swmask = mask;
2498 u32 fwmask = mask << 5;
2499 u32 timeout = 200;
2500 u32 i;
2501
2502 for (i = 0; i < timeout; i++) {
2503 /*
2504 * SW NVM semaphore bit is used for access to all
2505 * SW_FW_SYNC bits (not just NVM)
2506 */
2507 if (ixgbe_get_eeprom_semaphore(hw))
2508 return IXGBE_ERR_SWFW_SYNC;
2509
2510 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2511 if (!(gssr & (fwmask | swmask))) {
2512 gssr |= swmask;
2513 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2514 ixgbe_release_eeprom_semaphore(hw);
2515 return 0;
2516 } else {
2517 /* Resource is currently in use by FW or SW */
2518 ixgbe_release_eeprom_semaphore(hw);
2519 usleep_range(5000, 10000);
2520 }
2521 }
2522
2523 /* If time expired clear the bits holding the lock and retry */
2524 if (gssr & (fwmask | swmask))
2525 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
2526
2527 usleep_range(5000, 10000);
2528 return IXGBE_ERR_SWFW_SYNC;
2529 }
2530
2531 /**
2532 * ixgbe_release_swfw_sync - Release SWFW semaphore
2533 * @hw: pointer to hardware structure
2534 * @mask: Mask to specify which semaphore to release
2535 *
2536 * Releases the SWFW semaphore through the GSSR register for the specified
2537 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2538 **/
2539 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
2540 {
2541 u32 gssr;
2542 u32 swmask = mask;
2543
2544 ixgbe_get_eeprom_semaphore(hw);
2545
2546 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2547 gssr &= ~swmask;
2548 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2549
2550 ixgbe_release_eeprom_semaphore(hw);
2551 }
2552
2553 /**
2554 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
2555 * @hw: pointer to hardware structure
2556 * @reg_val: Value we read from AUTOC
2557 * @locked: bool to indicate whether the SW/FW lock should be taken. Never
2558 * true in this the generic case.
2559 *
2560 * The default case requires no protection so just to the register read.
2561 **/
2562 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
2563 {
2564 *locked = false;
2565 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2566 return 0;
2567 }
2568
2569 /**
2570 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
2571 * @hw: pointer to hardware structure
2572 * @reg_val: value to write to AUTOC
2573 * @locked: bool to indicate whether the SW/FW lock was already taken by
2574 * previous read.
2575 **/
2576 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
2577 {
2578 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
2579 return 0;
2580 }
2581
2582 /**
2583 * ixgbe_disable_rx_buff_generic - Stops the receive data path
2584 * @hw: pointer to hardware structure
2585 *
2586 * Stops the receive data path and waits for the HW to internally
2587 * empty the Rx security block.
2588 **/
2589 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
2590 {
2591 #define IXGBE_MAX_SECRX_POLL 40
2592 int i;
2593 int secrxreg;
2594
2595 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2596 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2597 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2598 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2599 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2600 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2601 break;
2602 else
2603 /* Use interrupt-safe sleep just in case */
2604 udelay(1000);
2605 }
2606
2607 /* For informational purposes only */
2608 if (i >= IXGBE_MAX_SECRX_POLL)
2609 hw_dbg(hw, "Rx unit being enabled before security path fully disabled. Continuing with init.\n");
2610
2611 return 0;
2612
2613 }
2614
2615 /**
2616 * ixgbe_enable_rx_buff - Enables the receive data path
2617 * @hw: pointer to hardware structure
2618 *
2619 * Enables the receive data path
2620 **/
2621 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
2622 {
2623 int secrxreg;
2624
2625 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2626 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2627 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2628 IXGBE_WRITE_FLUSH(hw);
2629
2630 return 0;
2631 }
2632
2633 /**
2634 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2635 * @hw: pointer to hardware structure
2636 * @regval: register value to write to RXCTRL
2637 *
2638 * Enables the Rx DMA unit
2639 **/
2640 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2641 {
2642 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2643
2644 return 0;
2645 }
2646
2647 /**
2648 * ixgbe_blink_led_start_generic - Blink LED based on index.
2649 * @hw: pointer to hardware structure
2650 * @index: led number to blink
2651 **/
2652 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2653 {
2654 ixgbe_link_speed speed = 0;
2655 bool link_up = false;
2656 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2657 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2658 bool locked = false;
2659 s32 ret_val;
2660
2661 /*
2662 * Link must be up to auto-blink the LEDs;
2663 * Force it if link is down.
2664 */
2665 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2666
2667 if (!link_up) {
2668 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2669 if (ret_val)
2670 return ret_val;
2671
2672 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2673 autoc_reg |= IXGBE_AUTOC_FLU;
2674
2675 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2676 if (ret_val)
2677 return ret_val;
2678
2679 IXGBE_WRITE_FLUSH(hw);
2680
2681 usleep_range(10000, 20000);
2682 }
2683
2684 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2685 led_reg |= IXGBE_LED_BLINK(index);
2686 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2687 IXGBE_WRITE_FLUSH(hw);
2688
2689 return 0;
2690 }
2691
2692 /**
2693 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2694 * @hw: pointer to hardware structure
2695 * @index: led number to stop blinking
2696 **/
2697 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2698 {
2699 u32 autoc_reg = 0;
2700 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2701 bool locked = false;
2702 s32 ret_val;
2703
2704 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
2705 if (ret_val)
2706 return ret_val;
2707
2708 autoc_reg &= ~IXGBE_AUTOC_FLU;
2709 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2710
2711 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
2712 if (ret_val)
2713 return ret_val;
2714
2715 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2716 led_reg &= ~IXGBE_LED_BLINK(index);
2717 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2718 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2719 IXGBE_WRITE_FLUSH(hw);
2720
2721 return 0;
2722 }
2723
2724 /**
2725 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2726 * @hw: pointer to hardware structure
2727 * @san_mac_offset: SAN MAC address offset
2728 *
2729 * This function will read the EEPROM location for the SAN MAC address
2730 * pointer, and returns the value at that location. This is used in both
2731 * get and set mac_addr routines.
2732 **/
2733 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
2734 u16 *san_mac_offset)
2735 {
2736 s32 ret_val;
2737
2738 /*
2739 * First read the EEPROM pointer to see if the MAC addresses are
2740 * available.
2741 */
2742 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
2743 san_mac_offset);
2744 if (ret_val)
2745 hw_err(hw, "eeprom read at offset %d failed\n",
2746 IXGBE_SAN_MAC_ADDR_PTR);
2747
2748 return ret_val;
2749 }
2750
2751 /**
2752 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2753 * @hw: pointer to hardware structure
2754 * @san_mac_addr: SAN MAC address
2755 *
2756 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2757 * per-port, so set_lan_id() must be called before reading the addresses.
2758 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2759 * upon for non-SFP connections, so we must call it here.
2760 **/
2761 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2762 {
2763 u16 san_mac_data, san_mac_offset;
2764 u8 i;
2765 s32 ret_val;
2766
2767 /*
2768 * First read the EEPROM pointer to see if the MAC addresses are
2769 * available. If they're not, no point in calling set_lan_id() here.
2770 */
2771 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2772 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
2773
2774 goto san_mac_addr_clr;
2775
2776 /* make sure we know which port we need to program */
2777 hw->mac.ops.set_lan_id(hw);
2778 /* apply the port offset to the address offset */
2779 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2780 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2781 for (i = 0; i < 3; i++) {
2782 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
2783 &san_mac_data);
2784 if (ret_val) {
2785 hw_err(hw, "eeprom read at offset %d failed\n",
2786 san_mac_offset);
2787 goto san_mac_addr_clr;
2788 }
2789 san_mac_addr[i * 2] = (u8)(san_mac_data);
2790 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2791 san_mac_offset++;
2792 }
2793 return 0;
2794
2795 san_mac_addr_clr:
2796 /* No addresses available in this EEPROM. It's not necessarily an
2797 * error though, so just wipe the local address and return.
2798 */
2799 for (i = 0; i < 6; i++)
2800 san_mac_addr[i] = 0xFF;
2801 return ret_val;
2802 }
2803
2804 /**
2805 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2806 * @hw: pointer to hardware structure
2807 *
2808 * Read PCIe configuration space, and get the MSI-X vector count from
2809 * the capabilities table.
2810 **/
2811 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2812 {
2813 u16 msix_count;
2814 u16 max_msix_count;
2815 u16 pcie_offset;
2816
2817 switch (hw->mac.type) {
2818 case ixgbe_mac_82598EB:
2819 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
2820 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
2821 break;
2822 case ixgbe_mac_82599EB:
2823 case ixgbe_mac_X540:
2824 case ixgbe_mac_X550:
2825 case ixgbe_mac_X550EM_x:
2826 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
2827 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
2828 break;
2829 default:
2830 return 1;
2831 }
2832
2833 msix_count = ixgbe_read_pci_cfg_word(hw, pcie_offset);
2834 if (ixgbe_removed(hw->hw_addr))
2835 msix_count = 0;
2836 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2837
2838 /* MSI-X count is zero-based in HW */
2839 msix_count++;
2840
2841 if (msix_count > max_msix_count)
2842 msix_count = max_msix_count;
2843
2844 return msix_count;
2845 }
2846
2847 /**
2848 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2849 * @hw: pointer to hardware struct
2850 * @rar: receive address register index to disassociate
2851 * @vmdq: VMDq pool index to remove from the rar
2852 **/
2853 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2854 {
2855 u32 mpsar_lo, mpsar_hi;
2856 u32 rar_entries = hw->mac.num_rar_entries;
2857
2858 /* Make sure we are using a valid rar index range */
2859 if (rar >= rar_entries) {
2860 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2861 return IXGBE_ERR_INVALID_ARGUMENT;
2862 }
2863
2864 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2865 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2866
2867 if (ixgbe_removed(hw->hw_addr))
2868 return 0;
2869
2870 if (!mpsar_lo && !mpsar_hi)
2871 return 0;
2872
2873 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
2874 if (mpsar_lo) {
2875 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2876 mpsar_lo = 0;
2877 }
2878 if (mpsar_hi) {
2879 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2880 mpsar_hi = 0;
2881 }
2882 } else if (vmdq < 32) {
2883 mpsar_lo &= ~(1 << vmdq);
2884 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
2885 } else {
2886 mpsar_hi &= ~(1 << (vmdq - 32));
2887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
2888 }
2889
2890 /* was that the last pool using this rar? */
2891 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
2892 hw->mac.ops.clear_rar(hw, rar);
2893 return 0;
2894 }
2895
2896 /**
2897 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2898 * @hw: pointer to hardware struct
2899 * @rar: receive address register index to associate with a VMDq index
2900 * @vmdq: VMDq pool index
2901 **/
2902 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2903 {
2904 u32 mpsar;
2905 u32 rar_entries = hw->mac.num_rar_entries;
2906
2907 /* Make sure we are using a valid rar index range */
2908 if (rar >= rar_entries) {
2909 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
2910 return IXGBE_ERR_INVALID_ARGUMENT;
2911 }
2912
2913 if (vmdq < 32) {
2914 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2915 mpsar |= 1 << vmdq;
2916 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2917 } else {
2918 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
2919 mpsar |= 1 << (vmdq - 32);
2920 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
2921 }
2922 return 0;
2923 }
2924
2925 /**
2926 * This function should only be involved in the IOV mode.
2927 * In IOV mode, Default pool is next pool after the number of
2928 * VFs advertized and not 0.
2929 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
2930 *
2931 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
2932 * @hw: pointer to hardware struct
2933 * @vmdq: VMDq pool index
2934 **/
2935 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
2936 {
2937 u32 rar = hw->mac.san_mac_rar_index;
2938
2939 if (vmdq < 32) {
2940 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
2941 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
2942 } else {
2943 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
2944 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
2945 }
2946
2947 return 0;
2948 }
2949
2950 /**
2951 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2952 * @hw: pointer to hardware structure
2953 **/
2954 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
2955 {
2956 int i;
2957
2958 for (i = 0; i < 128; i++)
2959 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2960
2961 return 0;
2962 }
2963
2964 /**
2965 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2966 * @hw: pointer to hardware structure
2967 * @vlan: VLAN id to write to VLAN filter
2968 *
2969 * return the VLVF index where this VLAN id should be placed
2970 *
2971 **/
2972 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
2973 {
2974 u32 bits = 0;
2975 u32 first_empty_slot = 0;
2976 s32 regindex;
2977
2978 /* short cut the special case */
2979 if (vlan == 0)
2980 return 0;
2981
2982 /*
2983 * Search for the vlan id in the VLVF entries. Save off the first empty
2984 * slot found along the way
2985 */
2986 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
2987 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
2988 if (!bits && !(first_empty_slot))
2989 first_empty_slot = regindex;
2990 else if ((bits & 0x0FFF) == vlan)
2991 break;
2992 }
2993
2994 /*
2995 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2996 * in the VLVF. Else use the first empty VLVF register for this
2997 * vlan id.
2998 */
2999 if (regindex >= IXGBE_VLVF_ENTRIES) {
3000 if (first_empty_slot)
3001 regindex = first_empty_slot;
3002 else {
3003 hw_dbg(hw, "No space in VLVF.\n");
3004 regindex = IXGBE_ERR_NO_SPACE;
3005 }
3006 }
3007
3008 return regindex;
3009 }
3010
3011 /**
3012 * ixgbe_set_vfta_generic - Set VLAN filter table
3013 * @hw: pointer to hardware structure
3014 * @vlan: VLAN id to write to VLAN filter
3015 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3016 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3017 *
3018 * Turn on/off specified VLAN in the VLAN filter table.
3019 **/
3020 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3021 bool vlan_on)
3022 {
3023 s32 regindex;
3024 u32 bitindex;
3025 u32 vfta;
3026 u32 bits;
3027 u32 vt;
3028 u32 targetbit;
3029 bool vfta_changed = false;
3030
3031 if (vlan > 4095)
3032 return IXGBE_ERR_PARAM;
3033
3034 /*
3035 * this is a 2 part operation - first the VFTA, then the
3036 * VLVF and VLVFB if VT Mode is set
3037 * We don't write the VFTA until we know the VLVF part succeeded.
3038 */
3039
3040 /* Part 1
3041 * The VFTA is a bitstring made up of 128 32-bit registers
3042 * that enable the particular VLAN id, much like the MTA:
3043 * bits[11-5]: which register
3044 * bits[4-0]: which bit in the register
3045 */
3046 regindex = (vlan >> 5) & 0x7F;
3047 bitindex = vlan & 0x1F;
3048 targetbit = (1 << bitindex);
3049 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3050
3051 if (vlan_on) {
3052 if (!(vfta & targetbit)) {
3053 vfta |= targetbit;
3054 vfta_changed = true;
3055 }
3056 } else {
3057 if ((vfta & targetbit)) {
3058 vfta &= ~targetbit;
3059 vfta_changed = true;
3060 }
3061 }
3062
3063 /* Part 2
3064 * If VT Mode is set
3065 * Either vlan_on
3066 * make sure the vlan is in VLVF
3067 * set the vind bit in the matching VLVFB
3068 * Or !vlan_on
3069 * clear the pool bit and possibly the vind
3070 */
3071 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3072 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3073 s32 vlvf_index;
3074
3075 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3076 if (vlvf_index < 0)
3077 return vlvf_index;
3078
3079 if (vlan_on) {
3080 /* set the pool bit */
3081 if (vind < 32) {
3082 bits = IXGBE_READ_REG(hw,
3083 IXGBE_VLVFB(vlvf_index*2));
3084 bits |= (1 << vind);
3085 IXGBE_WRITE_REG(hw,
3086 IXGBE_VLVFB(vlvf_index*2),
3087 bits);
3088 } else {
3089 bits = IXGBE_READ_REG(hw,
3090 IXGBE_VLVFB((vlvf_index*2)+1));
3091 bits |= (1 << (vind-32));
3092 IXGBE_WRITE_REG(hw,
3093 IXGBE_VLVFB((vlvf_index*2)+1),
3094 bits);
3095 }
3096 } else {
3097 /* clear the pool bit */
3098 if (vind < 32) {
3099 bits = IXGBE_READ_REG(hw,
3100 IXGBE_VLVFB(vlvf_index*2));
3101 bits &= ~(1 << vind);
3102 IXGBE_WRITE_REG(hw,
3103 IXGBE_VLVFB(vlvf_index*2),
3104 bits);
3105 bits |= IXGBE_READ_REG(hw,
3106 IXGBE_VLVFB((vlvf_index*2)+1));
3107 } else {
3108 bits = IXGBE_READ_REG(hw,
3109 IXGBE_VLVFB((vlvf_index*2)+1));
3110 bits &= ~(1 << (vind-32));
3111 IXGBE_WRITE_REG(hw,
3112 IXGBE_VLVFB((vlvf_index*2)+1),
3113 bits);
3114 bits |= IXGBE_READ_REG(hw,
3115 IXGBE_VLVFB(vlvf_index*2));
3116 }
3117 }
3118
3119 /*
3120 * If there are still bits set in the VLVFB registers
3121 * for the VLAN ID indicated we need to see if the
3122 * caller is requesting that we clear the VFTA entry bit.
3123 * If the caller has requested that we clear the VFTA
3124 * entry bit but there are still pools/VFs using this VLAN
3125 * ID entry then ignore the request. We're not worried
3126 * about the case where we're turning the VFTA VLAN ID
3127 * entry bit on, only when requested to turn it off as
3128 * there may be multiple pools and/or VFs using the
3129 * VLAN ID entry. In that case we cannot clear the
3130 * VFTA bit until all pools/VFs using that VLAN ID have also
3131 * been cleared. This will be indicated by "bits" being
3132 * zero.
3133 */
3134 if (bits) {
3135 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3136 (IXGBE_VLVF_VIEN | vlan));
3137 if (!vlan_on) {
3138 /* someone wants to clear the vfta entry
3139 * but some pools/VFs are still using it.
3140 * Ignore it. */
3141 vfta_changed = false;
3142 }
3143 } else {
3144 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3145 }
3146 }
3147
3148 if (vfta_changed)
3149 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3150
3151 return 0;
3152 }
3153
3154 /**
3155 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3156 * @hw: pointer to hardware structure
3157 *
3158 * Clears the VLAN filer table, and the VMDq index associated with the filter
3159 **/
3160 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3161 {
3162 u32 offset;
3163
3164 for (offset = 0; offset < hw->mac.vft_size; offset++)
3165 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3166
3167 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3168 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3169 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3170 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3171 }
3172
3173 return 0;
3174 }
3175
3176 /**
3177 * ixgbe_check_mac_link_generic - Determine link and speed status
3178 * @hw: pointer to hardware structure
3179 * @speed: pointer to link speed
3180 * @link_up: true when link is up
3181 * @link_up_wait_to_complete: bool used to wait for link up or not
3182 *
3183 * Reads the links register to determine if link is up and the current speed
3184 **/
3185 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3186 bool *link_up, bool link_up_wait_to_complete)
3187 {
3188 u32 links_reg, links_orig;
3189 u32 i;
3190
3191 /* clear the old state */
3192 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3193
3194 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3195
3196 if (links_orig != links_reg) {
3197 hw_dbg(hw, "LINKS changed from %08X to %08X\n",
3198 links_orig, links_reg);
3199 }
3200
3201 if (link_up_wait_to_complete) {
3202 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
3203 if (links_reg & IXGBE_LINKS_UP) {
3204 *link_up = true;
3205 break;
3206 } else {
3207 *link_up = false;
3208 }
3209 msleep(100);
3210 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3211 }
3212 } else {
3213 if (links_reg & IXGBE_LINKS_UP)
3214 *link_up = true;
3215 else
3216 *link_up = false;
3217 }
3218
3219 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3220 case IXGBE_LINKS_SPEED_10G_82599:
3221 if ((hw->mac.type >= ixgbe_mac_X550) &&
3222 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3223 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3224 else
3225 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3226 break;
3227 case IXGBE_LINKS_SPEED_1G_82599:
3228 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3229 break;
3230 case IXGBE_LINKS_SPEED_100_82599:
3231 if ((hw->mac.type >= ixgbe_mac_X550) &&
3232 (links_reg & IXGBE_LINKS_SPEED_NON_STD))
3233 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3234 else
3235 *speed = IXGBE_LINK_SPEED_100_FULL;
3236 break;
3237 default:
3238 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3239 }
3240
3241 return 0;
3242 }
3243
3244 /**
3245 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3246 * the EEPROM
3247 * @hw: pointer to hardware structure
3248 * @wwnn_prefix: the alternative WWNN prefix
3249 * @wwpn_prefix: the alternative WWPN prefix
3250 *
3251 * This function will read the EEPROM from the alternative SAN MAC address
3252 * block to check the support for the alternative WWNN/WWPN prefix support.
3253 **/
3254 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3255 u16 *wwpn_prefix)
3256 {
3257 u16 offset, caps;
3258 u16 alt_san_mac_blk_offset;
3259
3260 /* clear output first */
3261 *wwnn_prefix = 0xFFFF;
3262 *wwpn_prefix = 0xFFFF;
3263
3264 /* check if alternative SAN MAC is supported */
3265 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
3266 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
3267 goto wwn_prefix_err;
3268
3269 if ((alt_san_mac_blk_offset == 0) ||
3270 (alt_san_mac_blk_offset == 0xFFFF))
3271 return 0;
3272
3273 /* check capability in alternative san mac address block */
3274 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
3275 if (hw->eeprom.ops.read(hw, offset, &caps))
3276 goto wwn_prefix_err;
3277 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
3278 return 0;
3279
3280 /* get the corresponding prefix for WWNN/WWPN */
3281 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
3282 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
3283 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3284
3285 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
3286 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
3287 goto wwn_prefix_err;
3288
3289 return 0;
3290
3291 wwn_prefix_err:
3292 hw_err(hw, "eeprom read at offset %d failed\n", offset);
3293 return 0;
3294 }
3295
3296 /**
3297 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3298 * @hw: pointer to hardware structure
3299 * @enable: enable or disable switch for anti-spoofing
3300 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3301 *
3302 **/
3303 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3304 {
3305 int j;
3306 int pf_target_reg = pf >> 3;
3307 int pf_target_shift = pf % 8;
3308 u32 pfvfspoof = 0;
3309
3310 if (hw->mac.type == ixgbe_mac_82598EB)
3311 return;
3312
3313 if (enable)
3314 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3315
3316 /*
3317 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3318 * MAC anti-spoof enables in each register array element.
3319 */
3320 for (j = 0; j < pf_target_reg; j++)
3321 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3322
3323 /*
3324 * The PF should be allowed to spoof so that it can support
3325 * emulation mode NICs. Do not set the bits assigned to the PF
3326 */
3327 pfvfspoof &= (1 << pf_target_shift) - 1;
3328 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3329
3330 /*
3331 * Remaining pools belong to the PF so they do not need to have
3332 * anti-spoofing enabled.
3333 */
3334 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3335 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3336 }
3337
3338 /**
3339 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3340 * @hw: pointer to hardware structure
3341 * @enable: enable or disable switch for VLAN anti-spoofing
3342 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3343 *
3344 **/
3345 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3346 {
3347 int vf_target_reg = vf >> 3;
3348 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3349 u32 pfvfspoof;
3350
3351 if (hw->mac.type == ixgbe_mac_82598EB)
3352 return;
3353
3354 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3355 if (enable)
3356 pfvfspoof |= (1 << vf_target_shift);
3357 else
3358 pfvfspoof &= ~(1 << vf_target_shift);
3359 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3360 }
3361
3362 /**
3363 * ixgbe_get_device_caps_generic - Get additional device capabilities
3364 * @hw: pointer to hardware structure
3365 * @device_caps: the EEPROM word with the extra device capabilities
3366 *
3367 * This function will read the EEPROM location for the device capabilities,
3368 * and return the word through device_caps.
3369 **/
3370 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
3371 {
3372 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3373
3374 return 0;
3375 }
3376
3377 /**
3378 * ixgbe_set_rxpba_generic - Initialize RX packet buffer
3379 * @hw: pointer to hardware structure
3380 * @num_pb: number of packet buffers to allocate
3381 * @headroom: reserve n KB of headroom
3382 * @strategy: packet buffer allocation strategy
3383 **/
3384 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
3385 int num_pb,
3386 u32 headroom,
3387 int strategy)
3388 {
3389 u32 pbsize = hw->mac.rx_pb_size;
3390 int i = 0;
3391 u32 rxpktsize, txpktsize, txpbthresh;
3392
3393 /* Reserve headroom */
3394 pbsize -= headroom;
3395
3396 if (!num_pb)
3397 num_pb = 1;
3398
3399 /* Divide remaining packet buffer space amongst the number
3400 * of packet buffers requested using supplied strategy.
3401 */
3402 switch (strategy) {
3403 case (PBA_STRATEGY_WEIGHTED):
3404 /* pba_80_48 strategy weight first half of packet buffer with
3405 * 5/8 of the packet buffer space.
3406 */
3407 rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
3408 pbsize -= rxpktsize * (num_pb / 2);
3409 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
3410 for (; i < (num_pb / 2); i++)
3411 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3412 /* Fall through to configure remaining packet buffers */
3413 case (PBA_STRATEGY_EQUAL):
3414 /* Divide the remaining Rx packet buffer evenly among the TCs */
3415 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
3416 for (; i < num_pb; i++)
3417 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
3418 break;
3419 default:
3420 break;
3421 }
3422
3423 /*
3424 * Setup Tx packet buffer and threshold equally for all TCs
3425 * TXPBTHRESH register is set in K so divide by 1024 and subtract
3426 * 10 since the largest packet we support is just over 9K.
3427 */
3428 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
3429 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
3430 for (i = 0; i < num_pb; i++) {
3431 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3432 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3433 }
3434
3435 /* Clear unused TCs, if any, to zero buffer size*/
3436 for (; i < IXGBE_MAX_PB; i++) {
3437 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3438 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3439 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3440 }
3441 }
3442
3443 /**
3444 * ixgbe_calculate_checksum - Calculate checksum for buffer
3445 * @buffer: pointer to EEPROM
3446 * @length: size of EEPROM to calculate a checksum for
3447 *
3448 * Calculates the checksum for some buffer on a specified length. The
3449 * checksum calculated is returned.
3450 **/
3451 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3452 {
3453 u32 i;
3454 u8 sum = 0;
3455
3456 if (!buffer)
3457 return 0;
3458
3459 for (i = 0; i < length; i++)
3460 sum += buffer[i];
3461
3462 return (u8) (0 - sum);
3463 }
3464
3465 /**
3466 * ixgbe_host_interface_command - Issue command to manageability block
3467 * @hw: pointer to the HW structure
3468 * @buffer: contains the command to write and where the return status will
3469 * be placed
3470 * @length: length of buffer, must be multiple of 4 bytes
3471 * @timeout: time in ms to wait for command completion
3472 * @return_data: read and return data from the buffer (true) or not (false)
3473 * Needed because FW structures are big endian and decoding of
3474 * these fields can be 8 bit or 16 bit based on command. Decoding
3475 * is not easily understood without making a table of commands.
3476 * So we will leave this up to the caller to read back the data
3477 * in these cases.
3478 *
3479 * Communicates with the manageability block. On success return 0
3480 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3481 **/
3482 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3483 u32 length, u32 timeout,
3484 bool return_data)
3485 {
3486 u32 hicr, i, bi, fwsts;
3487 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3488 u16 buf_len, dword_len;
3489
3490 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3491 hw_dbg(hw, "Buffer length failure buffersize-%d.\n", length);
3492 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3493 }
3494
3495 /* Set bit 9 of FWSTS clearing FW reset indication */
3496 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
3497 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
3498
3499 /* Check that the host interface is enabled. */
3500 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3501 if ((hicr & IXGBE_HICR_EN) == 0) {
3502 hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
3503 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3504 }
3505
3506 /* Calculate length in DWORDs. We must be DWORD aligned */
3507 if ((length % (sizeof(u32))) != 0) {
3508 hw_dbg(hw, "Buffer length failure, not aligned to dword");
3509 return IXGBE_ERR_INVALID_ARGUMENT;
3510 }
3511
3512 dword_len = length >> 2;
3513
3514 /*
3515 * The device driver writes the relevant command block
3516 * into the ram area.
3517 */
3518 for (i = 0; i < dword_len; i++)
3519 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3520 i, cpu_to_le32(buffer[i]));
3521
3522 /* Setting this bit tells the ARC that a new command is pending. */
3523 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3524
3525 for (i = 0; i < timeout; i++) {
3526 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3527 if (!(hicr & IXGBE_HICR_C))
3528 break;
3529 usleep_range(1000, 2000);
3530 }
3531
3532 /* Check command successful completion. */
3533 if ((timeout != 0 && i == timeout) ||
3534 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3535 hw_dbg(hw, "Command has failed with no status valid.\n");
3536 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3537 }
3538
3539 if (!return_data)
3540 return 0;
3541
3542 /* Calculate length in DWORDs */
3543 dword_len = hdr_size >> 2;
3544
3545 /* first pull in the header so we know the buffer length */
3546 for (bi = 0; bi < dword_len; bi++) {
3547 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3548 le32_to_cpus(&buffer[bi]);
3549 }
3550
3551 /* If there is any thing in data position pull it in */
3552 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3553 if (buf_len == 0)
3554 return 0;
3555
3556 if (length < (buf_len + hdr_size)) {
3557 hw_dbg(hw, "Buffer not large enough for reply message.\n");
3558 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
3559 }
3560
3561 /* Calculate length in DWORDs, add 3 for odd lengths */
3562 dword_len = (buf_len + 3) >> 2;
3563
3564 /* Pull in the rest of the buffer (bi is where we left off)*/
3565 for (; bi <= dword_len; bi++) {
3566 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3567 le32_to_cpus(&buffer[bi]);
3568 }
3569
3570 return 0;
3571 }
3572
3573 /**
3574 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3575 * @hw: pointer to the HW structure
3576 * @maj: driver version major number
3577 * @min: driver version minor number
3578 * @build: driver version build number
3579 * @sub: driver version sub build number
3580 *
3581 * Sends driver version number to firmware through the manageability
3582 * block. On success return 0
3583 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
3584 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
3585 **/
3586 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
3587 u8 build, u8 sub)
3588 {
3589 struct ixgbe_hic_drv_info fw_cmd;
3590 int i;
3591 s32 ret_val;
3592
3593 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM))
3594 return IXGBE_ERR_SWFW_SYNC;
3595
3596 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
3597 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
3598 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
3599 fw_cmd.port_num = (u8)hw->bus.func;
3600 fw_cmd.ver_maj = maj;
3601 fw_cmd.ver_min = min;
3602 fw_cmd.ver_build = build;
3603 fw_cmd.ver_sub = sub;
3604 fw_cmd.hdr.checksum = 0;
3605 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
3606 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
3607 fw_cmd.pad = 0;
3608 fw_cmd.pad2 = 0;
3609
3610 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
3611 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
3612 sizeof(fw_cmd),
3613 IXGBE_HI_COMMAND_TIMEOUT,
3614 true);
3615 if (ret_val != 0)
3616 continue;
3617
3618 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
3619 FW_CEM_RESP_STATUS_SUCCESS)
3620 ret_val = 0;
3621 else
3622 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3623
3624 break;
3625 }
3626
3627 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
3628 return ret_val;
3629 }
3630
3631 /**
3632 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
3633 * @hw: pointer to the hardware structure
3634 *
3635 * The 82599 and x540 MACs can experience issues if TX work is still pending
3636 * when a reset occurs. This function prevents this by flushing the PCIe
3637 * buffers on the system.
3638 **/
3639 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
3640 {
3641 u32 gcr_ext, hlreg0, i, poll;
3642 u16 value;
3643
3644 /*
3645 * If double reset is not requested then all transactions should
3646 * already be clear and as such there is no work to do
3647 */
3648 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
3649 return;
3650
3651 /*
3652 * Set loopback enable to prevent any transmits from being sent
3653 * should the link come up. This assumes that the RXCTRL.RXEN bit
3654 * has already been cleared.
3655 */
3656 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3657 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
3658
3659 /* wait for a last completion before clearing buffers */
3660 IXGBE_WRITE_FLUSH(hw);
3661 usleep_range(3000, 6000);
3662
3663 /* Before proceeding, make sure that the PCIe block does not have
3664 * transactions pending.
3665 */
3666 poll = ixgbe_pcie_timeout_poll(hw);
3667 for (i = 0; i < poll; i++) {
3668 usleep_range(100, 200);
3669 value = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_STATUS);
3670 if (ixgbe_removed(hw->hw_addr))
3671 break;
3672 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3673 break;
3674 }
3675
3676 /* initiate cleaning flow for buffers in the PCIe transaction layer */
3677 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3678 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
3679 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
3680
3681 /* Flush all writes and allow 20usec for all transactions to clear */
3682 IXGBE_WRITE_FLUSH(hw);
3683 udelay(20);
3684
3685 /* restore previous register values */
3686 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3687 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3688 }
3689
3690 static const u8 ixgbe_emc_temp_data[4] = {
3691 IXGBE_EMC_INTERNAL_DATA,
3692 IXGBE_EMC_DIODE1_DATA,
3693 IXGBE_EMC_DIODE2_DATA,
3694 IXGBE_EMC_DIODE3_DATA
3695 };
3696 static const u8 ixgbe_emc_therm_limit[4] = {
3697 IXGBE_EMC_INTERNAL_THERM_LIMIT,
3698 IXGBE_EMC_DIODE1_THERM_LIMIT,
3699 IXGBE_EMC_DIODE2_THERM_LIMIT,
3700 IXGBE_EMC_DIODE3_THERM_LIMIT
3701 };
3702
3703 /**
3704 * ixgbe_get_ets_data - Extracts the ETS bit data
3705 * @hw: pointer to hardware structure
3706 * @ets_cfg: extected ETS data
3707 * @ets_offset: offset of ETS data
3708 *
3709 * Returns error code.
3710 **/
3711 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
3712 u16 *ets_offset)
3713 {
3714 s32 status;
3715
3716 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
3717 if (status)
3718 return status;
3719
3720 if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF))
3721 return IXGBE_NOT_IMPLEMENTED;
3722
3723 status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
3724 if (status)
3725 return status;
3726
3727 if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED)
3728 return IXGBE_NOT_IMPLEMENTED;
3729
3730 return 0;
3731 }
3732
3733 /**
3734 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
3735 * @hw: pointer to hardware structure
3736 *
3737 * Returns the thermal sensor data structure
3738 **/
3739 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
3740 {
3741 s32 status;
3742 u16 ets_offset;
3743 u16 ets_cfg;
3744 u16 ets_sensor;
3745 u8 num_sensors;
3746 u8 i;
3747 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3748
3749 /* Only support thermal sensors attached to physical port 0 */
3750 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3751 return IXGBE_NOT_IMPLEMENTED;
3752
3753 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3754 if (status)
3755 return status;
3756
3757 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3758 if (num_sensors > IXGBE_MAX_SENSORS)
3759 num_sensors = IXGBE_MAX_SENSORS;
3760
3761 for (i = 0; i < num_sensors; i++) {
3762 u8 sensor_index;
3763 u8 sensor_location;
3764
3765 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
3766 &ets_sensor);
3767 if (status)
3768 return status;
3769
3770 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3771 IXGBE_ETS_DATA_INDEX_SHIFT);
3772 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3773 IXGBE_ETS_DATA_LOC_SHIFT);
3774
3775 if (sensor_location != 0) {
3776 status = hw->phy.ops.read_i2c_byte(hw,
3777 ixgbe_emc_temp_data[sensor_index],
3778 IXGBE_I2C_THERMAL_SENSOR_ADDR,
3779 &data->sensor[i].temp);
3780 if (status)
3781 return status;
3782 }
3783 }
3784
3785 return 0;
3786 }
3787
3788 /**
3789 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
3790 * @hw: pointer to hardware structure
3791 *
3792 * Inits the thermal sensor thresholds according to the NVM map
3793 * and save off the threshold and location values into mac.thermal_sensor_data
3794 **/
3795 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
3796 {
3797 s32 status;
3798 u16 ets_offset;
3799 u16 ets_cfg;
3800 u16 ets_sensor;
3801 u8 low_thresh_delta;
3802 u8 num_sensors;
3803 u8 therm_limit;
3804 u8 i;
3805 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3806
3807 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
3808
3809 /* Only support thermal sensors attached to physical port 0 */
3810 if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
3811 return IXGBE_NOT_IMPLEMENTED;
3812
3813 status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
3814 if (status)
3815 return status;
3816
3817 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
3818 IXGBE_ETS_LTHRES_DELTA_SHIFT);
3819 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
3820 if (num_sensors > IXGBE_MAX_SENSORS)
3821 num_sensors = IXGBE_MAX_SENSORS;
3822
3823 for (i = 0; i < num_sensors; i++) {
3824 u8 sensor_index;
3825 u8 sensor_location;
3826
3827 if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
3828 hw_err(hw, "eeprom read at offset %d failed\n",
3829 ets_offset + 1 + i);
3830 continue;
3831 }
3832 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
3833 IXGBE_ETS_DATA_INDEX_SHIFT);
3834 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
3835 IXGBE_ETS_DATA_LOC_SHIFT);
3836 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
3837
3838 hw->phy.ops.write_i2c_byte(hw,
3839 ixgbe_emc_therm_limit[sensor_index],
3840 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
3841
3842 if (sensor_location == 0)
3843 continue;
3844
3845 data->sensor[i].location = sensor_location;
3846 data->sensor[i].caution_thresh = therm_limit;
3847 data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
3848 }
3849
3850 return 0;
3851 }
3852
Linux kernel - Deliverables
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