drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29
  30 #include "ixgbe.h"
  31 #include "ixgbe_type.h"
  32 #include "ixgbe_dcb.h"
  33 #include "ixgbe_dcb_82598.h"
  34 #include "ixgbe_dcb_82599.h"
  35
  36 /**
  37  * ixgbe_ieee_credits - This calculates the ieee traffic class
  38  * credits from the configured bandwidth percentages. Credits
  39  * are the smallest unit programmable into the underlying
  40  * hardware. The IEEE 802.1Qaz specification do not use bandwidth
  41  * groups so this is much simplified from the CEE case.
  42  */
  43 static s32 ixgbe_ieee_credits(__u8 *bw, __u16 *refill,
  44                               __u16 *max, int max_frame)
  45 {
  46         int min_percent = 100;
  47         int min_credit, multiplier;
  48         int i;
  49
  50         min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
  51                         DCB_CREDIT_QUANTUM;
  52
  53         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  54                 if (bw[i] < min_percent && bw[i])
  55                         min_percent = bw[i];
  56         }
  57
  58         multiplier = (min_credit / min_percent) + 1;
  59
  60         /* Find out the hw credits for each TC */
  61         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
  62                 int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL);
  63
  64                 if (val < min_credit)
  65                         val = min_credit;
  66                 refill[i] = val;
  67
  68                 max[i] = bw[i] ? (bw[i] * MAX_CREDIT)/100 : min_credit;
  69         }
  70         return 0;
  71 }
  72
  73 /**
  74  * ixgbe_dcb_calculate_tc_credits - Calculates traffic class credits
  75  * @ixgbe_dcb_config: Struct containing DCB settings.
  76  * @direction: Configuring either Tx or Rx.
  77  *
  78  * This function calculates the credits allocated to each traffic class.
  79  * It should be called only after the rules are checked by
  80  * ixgbe_dcb_check_config().
  81  */
  82 s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *hw,
  83                                    struct ixgbe_dcb_config *dcb_config,
  84                                    int max_frame, u8 direction)
  85 {
  86         struct tc_bw_alloc *p;
  87         int min_credit;
  88         int min_multiplier;
  89         int min_percent = 100;
  90         s32 ret_val = 0;
  91         /* Initialization values default for Tx settings */
  92         u32 credit_refill       = 0;
  93         u32 credit_max          = 0;
  94         u16 link_percentage     = 0;
  95         u8  bw_percent          = 0;
  96         u8  i;
  97
  98         if (dcb_config == NULL) {
  99                 ret_val = DCB_ERR_CONFIG;
 100                 goto out;
 101         }
 102
 103         min_credit = ((max_frame / 2) + DCB_CREDIT_QUANTUM - 1) /
 104                         DCB_CREDIT_QUANTUM;
 105
 106         /* Find smallest link percentage */
 107         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 108                 p = &dcb_config->tc_config[i].path[direction];
 109                 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
 110                 link_percentage = p->bwg_percent;
 111
 112                 link_percentage = (link_percentage * bw_percent) / 100;
 113
 114                 if (link_percentage && link_percentage < min_percent)
 115                         min_percent = link_percentage;
 116         }
 117
 118         /*
 119          * The ratio between traffic classes will control the bandwidth
 120          * percentages seen on the wire. To calculate this ratio we use
 121          * a multiplier. It is required that the refill credits must be
 122          * larger than the max frame size so here we find the smallest
 123          * multiplier that will allow all bandwidth percentages to be
 124          * greater than the max frame size.
 125          */
 126         min_multiplier = (min_credit / min_percent) + 1;
 127
 128         /* Find out the link percentage for each TC first */
 129         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 130                 p = &dcb_config->tc_config[i].path[direction];
 131                 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
 132
 133                 link_percentage = p->bwg_percent;
 134                 /* Must be careful of integer division for very small nums */
 135                 link_percentage = (link_percentage * bw_percent) / 100;
 136                 if (p->bwg_percent > 0 && link_percentage == 0)
 137                         link_percentage = 1;
 138
 139                 /* Save link_percentage for reference */
 140                 p->link_percent = (u8)link_percentage;
 141
 142                 /* Calculate credit refill ratio using multiplier */
 143                 credit_refill = min(link_percentage * min_multiplier,
 144                                     MAX_CREDIT_REFILL);
 145                 p->data_credits_refill = (u16)credit_refill;
 146
 147                 /* Calculate maximum credit for the TC */
 148                 credit_max = (link_percentage * MAX_CREDIT) / 100;
 149
 150                 /*
 151                  * Adjustment based on rule checking, if the percentage
 152                  * of a TC is too small, the maximum credit may not be
 153                  * enough to send out a jumbo frame in data plane arbitration.
 154                  */
 155                 if (credit_max && (credit_max < min_credit))
 156                         credit_max = min_credit;
 157
 158                 if (direction == DCB_TX_CONFIG) {
 159                         /*
 160                          * Adjustment based on rule checking, if the
 161                          * percentage of a TC is too small, the maximum
 162                          * credit may not be enough to send out a TSO
 163                          * packet in descriptor plane arbitration.
 164                          */
 165                         if ((hw->mac.type == ixgbe_mac_82598EB) &&
 166                             credit_max &&
 167                             (credit_max < MINIMUM_CREDIT_FOR_TSO))
 168                                 credit_max = MINIMUM_CREDIT_FOR_TSO;
 169
 170                         dcb_config->tc_config[i].desc_credits_max =
 171                                 (u16)credit_max;
 172                 }
 173
 174                 p->data_credits_max = (u16)credit_max;
 175         }
 176
 177 out:
 178         return ret_val;
 179 }
 180
 181 void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en)
 182 {
 183         struct tc_configuration *tc_config = &cfg->tc_config[0];
 184         int tc;
 185
 186         for (*pfc_en = 0, tc = 0; tc < MAX_TRAFFIC_CLASS; tc++) {
 187                 if (tc_config[tc].dcb_pfc != pfc_disabled)
 188                         *pfc_en |= 1 << tc;
 189         }
 190 }
 191
 192 void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *cfg, int direction,
 193                              u16 *refill)
 194 {
 195         struct tc_configuration *tc_config = &cfg->tc_config[0];
 196         int tc;
 197
 198         for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
 199                 refill[tc] = tc_config[tc].path[direction].data_credits_refill;
 200 }
 201
 202 void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *cfg, u16 *max)
 203 {
 204         struct tc_configuration *tc_config = &cfg->tc_config[0];
 205         int tc;
 206
 207         for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
 208                 max[tc] = tc_config[tc].desc_credits_max;
 209 }
 210
 211 void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *cfg, int direction,
 212                             u8 *bwgid)
 213 {
 214         struct tc_configuration *tc_config = &cfg->tc_config[0];
 215         int tc;
 216
 217         for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
 218                 bwgid[tc] = tc_config[tc].path[direction].bwg_id;
 219 }
 220
 221 void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *cfg, int direction,
 222                             u8 *ptype)
 223 {
 224         struct tc_configuration *tc_config = &cfg->tc_config[0];
 225         int tc;
 226
 227         for (tc = 0; tc < MAX_TRAFFIC_CLASS; tc++)
 228                 ptype[tc] = tc_config[tc].path[direction].prio_type;
 229 }
 230
 231 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
 232 {
 233         struct tc_configuration *tc_config = &cfg->tc_config[0];
 234         u8 prio_mask = 1 << up;
 235         u8 tc = cfg->num_tcs.pg_tcs;
 236
 237         /* If tc is 0 then DCB is likely not enabled or supported */
 238         if (!tc)
 239                 goto out;
 240
 241         /*
 242          * Test from maximum TC to 1 and report the first match we find.  If
 243          * we find no match we can assume that the TC is 0 since the TC must
 244          * be set for all user priorities
 245          */
 246         for (tc--; tc; tc--) {
 247                 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
 248                         break;
 249         }
 250 out:
 251         return tc;
 252 }
 253
 254 void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *cfg, int direction, u8 *map)
 255 {
 256         u8 up;
 257
 258         for (up = 0; up < MAX_USER_PRIORITY; up++)
 259                 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
 260 }
 261
 262 /**
 263  * ixgbe_dcb_hw_config - Config and enable DCB
 264  * @hw: pointer to hardware structure
 265  * @dcb_config: pointer to ixgbe_dcb_config structure
 266  *
 267  * Configure dcb settings and enable dcb mode.
 268  */
 269 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
 270                         struct ixgbe_dcb_config *dcb_config)
 271 {
 272         s32 ret = 0;
 273         u8 pfc_en;
 274         u8 ptype[MAX_TRAFFIC_CLASS];
 275         u8 bwgid[MAX_TRAFFIC_CLASS];
 276         u8 prio_tc[MAX_TRAFFIC_CLASS];
 277         u16 refill[MAX_TRAFFIC_CLASS];
 278         u16 max[MAX_TRAFFIC_CLASS];
 279
 280         /* Unpack CEE standard containers */
 281         ixgbe_dcb_unpack_pfc(dcb_config, &pfc_en);
 282         ixgbe_dcb_unpack_refill(dcb_config, DCB_TX_CONFIG, refill);
 283         ixgbe_dcb_unpack_max(dcb_config, max);
 284         ixgbe_dcb_unpack_bwgid(dcb_config, DCB_TX_CONFIG, bwgid);
 285         ixgbe_dcb_unpack_prio(dcb_config, DCB_TX_CONFIG, ptype);
 286         ixgbe_dcb_unpack_map(dcb_config, DCB_TX_CONFIG, prio_tc);
 287
 288         switch (hw->mac.type) {
 289         case ixgbe_mac_82598EB:
 290                 ret = ixgbe_dcb_hw_config_82598(hw, pfc_en, refill, max,
 291                                                 bwgid, ptype);
 292                 break;
 293         case ixgbe_mac_82599EB:
 294         case ixgbe_mac_X540:
 295                 ret = ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
 296                                                 bwgid, ptype, prio_tc);
 297                 break;
 298         default:
 299                 break;
 300         }
 301         return ret;
 302 }
 303
 304 /* Helper routines to abstract HW specifics from DCB netlink ops */
 305 s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
 306 {
 307         int ret = -EINVAL;
 308
 309         switch (hw->mac.type) {
 310         case ixgbe_mac_82598EB:
 311                 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
 312                 break;
 313         case ixgbe_mac_82599EB:
 314         case ixgbe_mac_X540:
 315                 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
 316                 break;
 317         default:
 318                 break;
 319         }
 320         return ret;
 321 }
 322
 323 s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max_frame)
 324 {
 325         __u16 refill[IEEE_8021QAZ_MAX_TCS], max[IEEE_8021QAZ_MAX_TCS];
 326         __u8 prio_type[IEEE_8021QAZ_MAX_TCS];
 327         int i;
 328
 329         /* naively give each TC a bwg to map onto CEE hardware */
 330         __u8 bwg_id[IEEE_8021QAZ_MAX_TCS] = {0, 1, 2, 3, 4, 5, 6, 7};
 331
 332         /* Map TSA onto CEE prio type */
 333         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 334                 switch (ets->tc_tsa[i]) {
 335                 case IEEE_8021QAZ_TSA_STRICT:
 336                         prio_type[i] = 2;
 337                         break;
 338                 case IEEE_8021QAZ_TSA_ETS:
 339                         prio_type[i] = 0;
 340                         break;
 341                 default:
 342                         /* Hardware only supports priority strict or
 343                          * ETS transmission selection algorithms if
 344                          * we receive some other value from dcbnl
 345                          * throw an error
 346                          */
 347                         return -EINVAL;
 348                 }
 349         }
 350
 351         ixgbe_ieee_credits(ets->tc_tx_bw, refill, max, max_frame);
 352         return ixgbe_dcb_hw_ets_config(hw, refill, max,
 353                                        bwg_id, prio_type, ets->prio_tc);
 354 }
 355
 356 s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw,
 357                             u16 *refill, u16 *max, u8 *bwg_id,
 358                             u8 *prio_type, u8 *prio_tc)
 359 {
 360         switch (hw->mac.type) {
 361         case ixgbe_mac_82598EB:
 362                 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max,
 363                                                         prio_type);
 364                 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
 365                                                              bwg_id, prio_type);
 366                 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
 367                                                              bwg_id, prio_type);
 368                 break;
 369         case ixgbe_mac_82599EB:
 370         case ixgbe_mac_X540:
 371                 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
 372                                                   bwg_id, prio_type, prio_tc);
 373                 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
 374                                                        bwg_id, prio_type);
 375                 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
 376                                                        prio_type, prio_tc);
 377                 break;
 378         default:
 379                 break;
 380         }
 381         return 0;
 382 }
 383
 384 static void ixgbe_dcb_read_rtrup2tc_82599(struct ixgbe_hw *hw, u8 *map)
 385 {
 386         u32 reg, i;
 387
 388         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
 389         for (i = 0; i < MAX_USER_PRIORITY; i++)
 390                 map[i] = IXGBE_RTRUP2TC_UP_MASK &
 391                         (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
 392 }
 393
 394 void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map)
 395 {
 396         switch (hw->mac.type) {
 397         case ixgbe_mac_82599EB:
 398         case ixgbe_mac_X540:
 399                 ixgbe_dcb_read_rtrup2tc_82599(hw, map);
 400                 break;
 401         default:
 402                 break;
 403         }
 404 }