1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
55 char ixgbe_driver_name
[] = "ixgbe";
56 static const char ixgbe_driver_string
[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version
[] = DRV_VERSION
;
64 static const char ixgbe_copyright
[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
67 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
68 [board_82598
] = &ixgbe_82598_info
,
69 [board_82599
] = &ixgbe_82599_info
,
70 [board_X540
] = &ixgbe_X540_info
,
73 /* ixgbe_pci_tbl - PCI Device ID Table
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
82 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
), board_82598
},
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
), board_82598
},
84 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
), board_82598
},
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
), board_82598
},
86 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
), board_82598
},
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
), board_82598
},
88 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
), board_82598
},
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
), board_82598
},
90 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
), board_82598
},
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
), board_82598
},
92 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
), board_82598
},
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
), board_82598
},
94 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
), board_82599
},
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
), board_82599
},
96 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
), board_82599
},
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
), board_82599
},
98 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
), board_82599
},
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
), board_82599
},
100 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
), board_82599
},
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_BACKPLANE_FCOE
), board_82599
},
102 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_FCOE
), board_82599
},
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
), board_82599
},
104 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
), board_82599
},
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_X540T
), board_X540
},
106 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_SF2
), board_82599
},
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_LS
), board_82599
},
108 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599EN_SFP
), board_82599
},
109 /* required last entry */
112 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
114 #ifdef CONFIG_IXGBE_DCA
115 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
117 static struct notifier_block dca_notifier
= {
118 .notifier_call
= ixgbe_notify_dca
,
124 #ifdef CONFIG_PCI_IOV
125 static unsigned int max_vfs
;
126 module_param(max_vfs
, uint
, 0);
127 MODULE_PARM_DESC(max_vfs
,
128 "Maximum number of virtual functions to allocate per physical function");
129 #endif /* CONFIG_PCI_IOV */
131 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
132 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
133 MODULE_LICENSE("GPL");
134 MODULE_VERSION(DRV_VERSION
);
136 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
138 static void ixgbe_service_event_schedule(struct ixgbe_adapter
*adapter
)
140 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
) &&
141 !test_and_set_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
))
142 schedule_work(&adapter
->service_task
);
145 static void ixgbe_service_event_complete(struct ixgbe_adapter
*adapter
)
147 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
));
149 /* flush memory to make sure state is correct before next watchdog */
150 smp_mb__before_clear_bit();
151 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
154 struct ixgbe_reg_info
{
159 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
161 /* General Registers */
162 {IXGBE_CTRL
, "CTRL"},
163 {IXGBE_STATUS
, "STATUS"},
164 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
166 /* Interrupt Registers */
167 {IXGBE_EICR
, "EICR"},
170 {IXGBE_SRRCTL(0), "SRRCTL"},
171 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
172 {IXGBE_RDLEN(0), "RDLEN"},
173 {IXGBE_RDH(0), "RDH"},
174 {IXGBE_RDT(0), "RDT"},
175 {IXGBE_RXDCTL(0), "RXDCTL"},
176 {IXGBE_RDBAL(0), "RDBAL"},
177 {IXGBE_RDBAH(0), "RDBAH"},
180 {IXGBE_TDBAL(0), "TDBAL"},
181 {IXGBE_TDBAH(0), "TDBAH"},
182 {IXGBE_TDLEN(0), "TDLEN"},
183 {IXGBE_TDH(0), "TDH"},
184 {IXGBE_TDT(0), "TDT"},
185 {IXGBE_TXDCTL(0), "TXDCTL"},
187 /* List Terminator */
193 * ixgbe_regdump - register printout routine
195 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
201 switch (reginfo
->ofs
) {
202 case IXGBE_SRRCTL(0):
203 for (i
= 0; i
< 64; i
++)
204 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
206 case IXGBE_DCA_RXCTRL(0):
207 for (i
= 0; i
< 64; i
++)
208 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
211 for (i
= 0; i
< 64; i
++)
212 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
215 for (i
= 0; i
< 64; i
++)
216 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
219 for (i
= 0; i
< 64; i
++)
220 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
222 case IXGBE_RXDCTL(0):
223 for (i
= 0; i
< 64; i
++)
224 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
227 for (i
= 0; i
< 64; i
++)
228 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
231 for (i
= 0; i
< 64; i
++)
232 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
235 for (i
= 0; i
< 64; i
++)
236 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
239 for (i
= 0; i
< 64; i
++)
240 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
243 for (i
= 0; i
< 64; i
++)
244 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
247 for (i
= 0; i
< 64; i
++)
248 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
251 for (i
= 0; i
< 64; i
++)
252 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
254 case IXGBE_TXDCTL(0):
255 for (i
= 0; i
< 64; i
++)
256 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
259 pr_info("%-15s %08x\n", reginfo
->name
,
260 IXGBE_READ_REG(hw
, reginfo
->ofs
));
264 for (i
= 0; i
< 8; i
++) {
265 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
266 pr_err("%-15s", rname
);
267 for (j
= 0; j
< 8; j
++)
268 pr_cont(" %08x", regs
[i
*8+j
]);
275 * ixgbe_dump - Print registers, tx-rings and rx-rings
277 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
279 struct net_device
*netdev
= adapter
->netdev
;
280 struct ixgbe_hw
*hw
= &adapter
->hw
;
281 struct ixgbe_reg_info
*reginfo
;
283 struct ixgbe_ring
*tx_ring
;
284 struct ixgbe_tx_buffer
*tx_buffer_info
;
285 union ixgbe_adv_tx_desc
*tx_desc
;
286 struct my_u0
{ u64 a
; u64 b
; } *u0
;
287 struct ixgbe_ring
*rx_ring
;
288 union ixgbe_adv_rx_desc
*rx_desc
;
289 struct ixgbe_rx_buffer
*rx_buffer_info
;
293 if (!netif_msg_hw(adapter
))
296 /* Print netdevice Info */
298 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
299 pr_info("Device Name state "
300 "trans_start last_rx\n");
301 pr_info("%-15s %016lX %016lX %016lX\n",
308 /* Print Registers */
309 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
310 pr_info(" Register Name Value\n");
311 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
312 reginfo
->name
; reginfo
++) {
313 ixgbe_regdump(hw
, reginfo
);
316 /* Print TX Ring Summary */
317 if (!netdev
|| !netif_running(netdev
))
320 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
321 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
322 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
323 tx_ring
= adapter
->tx_ring
[n
];
325 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
326 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
327 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
328 (u64
)tx_buffer_info
->dma
,
329 tx_buffer_info
->length
,
330 tx_buffer_info
->next_to_watch
,
331 (u64
)tx_buffer_info
->time_stamp
);
335 if (!netif_msg_tx_done(adapter
))
336 goto rx_ring_summary
;
338 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
340 /* Transmit Descriptor Formats
342 * Advanced Transmit Descriptor
343 * +--------------------------------------------------------------+
344 * 0 | Buffer Address [63:0] |
345 * +--------------------------------------------------------------+
346 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
347 * +--------------------------------------------------------------+
348 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
351 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
352 tx_ring
= adapter
->tx_ring
[n
];
353 pr_info("------------------------------------\n");
354 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
355 pr_info("------------------------------------\n");
356 pr_info("T [desc] [address 63:0 ] "
357 "[PlPOIdStDDt Ln] [bi->dma ] "
358 "leng ntw timestamp bi->skb\n");
360 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
361 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
362 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
363 u0
= (struct my_u0
*)tx_desc
;
364 pr_info("T [0x%03X] %016llX %016llX %016llX"
365 " %04X %p %016llX %p", i
,
368 (u64
)tx_buffer_info
->dma
,
369 tx_buffer_info
->length
,
370 tx_buffer_info
->next_to_watch
,
371 (u64
)tx_buffer_info
->time_stamp
,
372 tx_buffer_info
->skb
);
373 if (i
== tx_ring
->next_to_use
&&
374 i
== tx_ring
->next_to_clean
)
376 else if (i
== tx_ring
->next_to_use
)
378 else if (i
== tx_ring
->next_to_clean
)
383 if (netif_msg_pktdata(adapter
) &&
384 tx_buffer_info
->dma
!= 0)
385 print_hex_dump(KERN_INFO
, "",
386 DUMP_PREFIX_ADDRESS
, 16, 1,
387 phys_to_virt(tx_buffer_info
->dma
),
388 tx_buffer_info
->length
, true);
392 /* Print RX Rings Summary */
394 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
395 pr_info("Queue [NTU] [NTC]\n");
396 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
397 rx_ring
= adapter
->rx_ring
[n
];
398 pr_info("%5d %5X %5X\n",
399 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
403 if (!netif_msg_rx_status(adapter
))
406 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
408 /* Advanced Receive Descriptor (Read) Format
410 * +-----------------------------------------------------+
411 * 0 | Packet Buffer Address [63:1] |A0/NSE|
412 * +----------------------------------------------+------+
413 * 8 | Header Buffer Address [63:1] | DD |
414 * +-----------------------------------------------------+
417 * Advanced Receive Descriptor (Write-Back) Format
419 * 63 48 47 32 31 30 21 20 16 15 4 3 0
420 * +------------------------------------------------------+
421 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
422 * | Checksum Ident | | | | Type | Type |
423 * +------------------------------------------------------+
424 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
425 * +------------------------------------------------------+
426 * 63 48 47 32 31 20 19 0
428 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
429 rx_ring
= adapter
->rx_ring
[n
];
430 pr_info("------------------------------------\n");
431 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
432 pr_info("------------------------------------\n");
433 pr_info("R [desc] [ PktBuf A0] "
434 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
435 "<-- Adv Rx Read format\n");
436 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
437 "[vl er S cks ln] ---------------- [bi->skb] "
438 "<-- Adv Rx Write-Back format\n");
440 for (i
= 0; i
< rx_ring
->count
; i
++) {
441 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
442 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
443 u0
= (struct my_u0
*)rx_desc
;
444 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
445 if (staterr
& IXGBE_RXD_STAT_DD
) {
446 /* Descriptor Done */
447 pr_info("RWB[0x%03X] %016llX "
448 "%016llX ---------------- %p", i
,
451 rx_buffer_info
->skb
);
453 pr_info("R [0x%03X] %016llX "
454 "%016llX %016llX %p", i
,
457 (u64
)rx_buffer_info
->dma
,
458 rx_buffer_info
->skb
);
460 if (netif_msg_pktdata(adapter
)) {
461 print_hex_dump(KERN_INFO
, "",
462 DUMP_PREFIX_ADDRESS
, 16, 1,
463 phys_to_virt(rx_buffer_info
->dma
),
464 rx_ring
->rx_buf_len
, true);
466 if (rx_ring
->rx_buf_len
468 print_hex_dump(KERN_INFO
, "",
469 DUMP_PREFIX_ADDRESS
, 16, 1,
471 rx_buffer_info
->page_dma
+
472 rx_buffer_info
->page_offset
478 if (i
== rx_ring
->next_to_use
)
480 else if (i
== rx_ring
->next_to_clean
)
492 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
496 /* Let firmware take over control of h/w */
497 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
498 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
499 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
502 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
506 /* Let firmware know the driver has taken over */
507 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
508 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
509 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
513 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
514 * @adapter: pointer to adapter struct
515 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
516 * @queue: queue to map the corresponding interrupt to
517 * @msix_vector: the vector to map to the corresponding queue
520 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
521 u8 queue
, u8 msix_vector
)
524 struct ixgbe_hw
*hw
= &adapter
->hw
;
525 switch (hw
->mac
.type
) {
526 case ixgbe_mac_82598EB
:
527 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
530 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
531 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
532 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
533 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
534 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
536 case ixgbe_mac_82599EB
:
538 if (direction
== -1) {
540 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
541 index
= ((queue
& 1) * 8);
542 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
543 ivar
&= ~(0xFF << index
);
544 ivar
|= (msix_vector
<< index
);
545 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
548 /* tx or rx causes */
549 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
550 index
= ((16 * (queue
& 1)) + (8 * direction
));
551 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
552 ivar
&= ~(0xFF << index
);
553 ivar
|= (msix_vector
<< index
);
554 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
562 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
567 switch (adapter
->hw
.mac
.type
) {
568 case ixgbe_mac_82598EB
:
569 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
570 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
572 case ixgbe_mac_82599EB
:
574 mask
= (qmask
& 0xFFFFFFFF);
575 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
576 mask
= (qmask
>> 32);
577 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
584 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring
*ring
,
585 struct ixgbe_tx_buffer
*tx_buffer
)
587 if (tx_buffer
->dma
) {
588 if (tx_buffer
->tx_flags
& IXGBE_TX_FLAGS_MAPPED_AS_PAGE
)
589 dma_unmap_page(ring
->dev
,
594 dma_unmap_single(ring
->dev
,
602 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*tx_ring
,
603 struct ixgbe_tx_buffer
*tx_buffer_info
)
605 ixgbe_unmap_tx_resource(tx_ring
, tx_buffer_info
);
606 if (tx_buffer_info
->skb
)
607 dev_kfree_skb_any(tx_buffer_info
->skb
);
608 tx_buffer_info
->skb
= NULL
;
609 /* tx_buffer_info must be completely set up in the transmit path */
612 static void ixgbe_update_xoff_received(struct ixgbe_adapter
*adapter
)
614 struct ixgbe_hw
*hw
= &adapter
->hw
;
615 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
620 if ((hw
->fc
.current_mode
== ixgbe_fc_full
) ||
621 (hw
->fc
.current_mode
== ixgbe_fc_rx_pause
)) {
622 switch (hw
->mac
.type
) {
623 case ixgbe_mac_82598EB
:
624 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
627 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
629 hwstats
->lxoffrxc
+= data
;
631 /* refill credits (no tx hang) if we received xoff */
635 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
636 clear_bit(__IXGBE_HANG_CHECK_ARMED
,
637 &adapter
->tx_ring
[i
]->state
);
639 } else if (!(adapter
->dcb_cfg
.pfc_mode_enable
))
642 /* update stats for each tc, only valid with PFC enabled */
643 for (i
= 0; i
< MAX_TX_PACKET_BUFFERS
; i
++) {
644 switch (hw
->mac
.type
) {
645 case ixgbe_mac_82598EB
:
646 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
649 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
651 hwstats
->pxoffrxc
[i
] += xoff
[i
];
654 /* disarm tx queues that have received xoff frames */
655 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
656 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
657 u8 tc
= tx_ring
->dcb_tc
;
660 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
664 static u64
ixgbe_get_tx_completed(struct ixgbe_ring
*ring
)
666 return ring
->tx_stats
.completed
;
669 static u64
ixgbe_get_tx_pending(struct ixgbe_ring
*ring
)
671 struct ixgbe_adapter
*adapter
= netdev_priv(ring
->netdev
);
672 struct ixgbe_hw
*hw
= &adapter
->hw
;
674 u32 head
= IXGBE_READ_REG(hw
, IXGBE_TDH(ring
->reg_idx
));
675 u32 tail
= IXGBE_READ_REG(hw
, IXGBE_TDT(ring
->reg_idx
));
678 return (head
< tail
) ?
679 tail
- head
: (tail
+ ring
->count
- head
);
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring
*tx_ring
)
686 u32 tx_done
= ixgbe_get_tx_completed(tx_ring
);
687 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
688 u32 tx_pending
= ixgbe_get_tx_pending(tx_ring
);
691 clear_check_for_tx_hang(tx_ring
);
694 * Check for a hung queue, but be thorough. This verifies
695 * that a transmit has been completed since the previous
696 * check AND there is at least one packet pending. The
697 * ARMED bit is set to indicate a potential hang. The
698 * bit is cleared if a pause frame is received to remove
699 * false hang detection due to PFC or 802.3x frames. By
700 * requiring this to fail twice we avoid races with
701 * pfc clearing the ARMED bit and conditions where we
702 * run the check_tx_hang logic with a transmit completion
703 * pending but without time to complete it yet.
705 if ((tx_done_old
== tx_done
) && tx_pending
) {
706 /* make sure it is true for two checks in a row */
707 ret
= test_and_set_bit(__IXGBE_HANG_CHECK_ARMED
,
710 /* update completed stats and continue */
711 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
712 /* reset the countdown */
713 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
720 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
721 * @adapter: driver private struct
723 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter
*adapter
)
726 /* Do the reset outside of interrupt context */
727 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
728 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
729 ixgbe_service_event_schedule(adapter
);
734 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
735 * @q_vector: structure containing interrupt and ring information
736 * @tx_ring: tx ring to clean
738 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
739 struct ixgbe_ring
*tx_ring
)
741 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
742 struct ixgbe_tx_buffer
*tx_buffer
;
743 union ixgbe_adv_tx_desc
*tx_desc
;
744 unsigned int total_bytes
= 0, total_packets
= 0;
745 unsigned int budget
= q_vector
->tx
.work_limit
;
746 u16 i
= tx_ring
->next_to_clean
;
748 tx_buffer
= &tx_ring
->tx_buffer_info
[i
];
749 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
751 for (; budget
; budget
--) {
752 union ixgbe_adv_tx_desc
*eop_desc
= tx_buffer
->next_to_watch
;
754 /* if next_to_watch is not set then there is no work pending */
758 /* if DD is not set pending work has not been completed */
759 if (!(eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)))
762 /* count the packet as being completed */
763 tx_ring
->tx_stats
.completed
++;
765 /* clear next_to_watch to prevent false hangs */
766 tx_buffer
->next_to_watch
= NULL
;
768 /* prevent any other reads prior to eop_desc being verified */
772 ixgbe_unmap_tx_resource(tx_ring
, tx_buffer
);
773 tx_desc
->wb
.status
= 0;
774 if (likely(tx_desc
== eop_desc
)) {
776 dev_kfree_skb_any(tx_buffer
->skb
);
777 tx_buffer
->skb
= NULL
;
779 total_bytes
+= tx_buffer
->bytecount
;
780 total_packets
+= tx_buffer
->gso_segs
;
786 if (unlikely(i
== tx_ring
->count
)) {
789 tx_buffer
= tx_ring
->tx_buffer_info
;
790 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, 0);
796 tx_ring
->next_to_clean
= i
;
797 u64_stats_update_begin(&tx_ring
->syncp
);
798 tx_ring
->stats
.bytes
+= total_bytes
;
799 tx_ring
->stats
.packets
+= total_packets
;
800 u64_stats_update_end(&tx_ring
->syncp
);
801 q_vector
->tx
.total_bytes
+= total_bytes
;
802 q_vector
->tx
.total_packets
+= total_packets
;
804 if (check_for_tx_hang(tx_ring
) && ixgbe_check_tx_hang(tx_ring
)) {
805 /* schedule immediate reset if we believe we hung */
806 struct ixgbe_hw
*hw
= &adapter
->hw
;
807 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
808 e_err(drv
, "Detected Tx Unit Hang\n"
810 " TDH, TDT <%x>, <%x>\n"
811 " next_to_use <%x>\n"
812 " next_to_clean <%x>\n"
813 "tx_buffer_info[next_to_clean]\n"
814 " time_stamp <%lx>\n"
816 tx_ring
->queue_index
,
817 IXGBE_READ_REG(hw
, IXGBE_TDH(tx_ring
->reg_idx
)),
818 IXGBE_READ_REG(hw
, IXGBE_TDT(tx_ring
->reg_idx
)),
819 tx_ring
->next_to_use
, i
,
820 tx_ring
->tx_buffer_info
[i
].time_stamp
, jiffies
);
822 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
825 "tx hang %d detected on queue %d, resetting adapter\n",
826 adapter
->tx_timeout_count
+ 1, tx_ring
->queue_index
);
828 /* schedule immediate reset if we believe we hung */
829 ixgbe_tx_timeout_reset(adapter
);
831 /* the adapter is about to reset, no point in enabling stuff */
835 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
836 if (unlikely(total_packets
&& netif_carrier_ok(tx_ring
->netdev
) &&
837 (ixgbe_desc_unused(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
838 /* Make sure that anybody stopping the queue after this
839 * sees the new next_to_clean.
842 if (__netif_subqueue_stopped(tx_ring
->netdev
, tx_ring
->queue_index
) &&
843 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
844 netif_wake_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
845 ++tx_ring
->tx_stats
.restart_queue
;
852 #ifdef CONFIG_IXGBE_DCA
853 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
854 struct ixgbe_ring
*rx_ring
,
857 struct ixgbe_hw
*hw
= &adapter
->hw
;
859 u8 reg_idx
= rx_ring
->reg_idx
;
861 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
));
862 switch (hw
->mac
.type
) {
863 case ixgbe_mac_82598EB
:
864 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
865 rxctrl
|= dca3_get_tag(rx_ring
->dev
, cpu
);
867 case ixgbe_mac_82599EB
:
869 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
870 rxctrl
|= (dca3_get_tag(rx_ring
->dev
, cpu
) <<
871 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
876 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
877 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
878 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
879 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
), rxctrl
);
882 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
883 struct ixgbe_ring
*tx_ring
,
886 struct ixgbe_hw
*hw
= &adapter
->hw
;
888 u8 reg_idx
= tx_ring
->reg_idx
;
890 switch (hw
->mac
.type
) {
891 case ixgbe_mac_82598EB
:
892 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
));
893 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
894 txctrl
|= dca3_get_tag(tx_ring
->dev
, cpu
);
895 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
896 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
), txctrl
);
898 case ixgbe_mac_82599EB
:
900 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
));
901 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
902 txctrl
|= (dca3_get_tag(tx_ring
->dev
, cpu
) <<
903 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
904 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
905 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
), txctrl
);
912 static void ixgbe_update_dca(struct ixgbe_q_vector
*q_vector
)
914 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
915 struct ixgbe_ring
*ring
;
918 if (q_vector
->cpu
== cpu
)
921 for (ring
= q_vector
->tx
.ring
; ring
!= NULL
; ring
= ring
->next
)
922 ixgbe_update_tx_dca(adapter
, ring
, cpu
);
924 for (ring
= q_vector
->rx
.ring
; ring
!= NULL
; ring
= ring
->next
)
925 ixgbe_update_rx_dca(adapter
, ring
, cpu
);
932 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
937 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
940 /* always use CB2 mode, difference is masked in the CB driver */
941 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
943 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
944 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
948 for (i
= 0; i
< num_q_vectors
; i
++) {
949 adapter
->q_vector
[i
]->cpu
= -1;
950 ixgbe_update_dca(adapter
->q_vector
[i
]);
954 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
956 struct ixgbe_adapter
*adapter
= dev_get_drvdata(dev
);
957 unsigned long event
= *(unsigned long *)data
;
959 if (!(adapter
->flags
& IXGBE_FLAG_DCA_CAPABLE
))
963 case DCA_PROVIDER_ADD
:
964 /* if we're already enabled, don't do it again */
965 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
967 if (dca_add_requester(dev
) == 0) {
968 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
969 ixgbe_setup_dca(adapter
);
972 /* Fall Through since DCA is disabled. */
973 case DCA_PROVIDER_REMOVE
:
974 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
975 dca_remove_requester(dev
);
976 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
977 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
984 #endif /* CONFIG_IXGBE_DCA */
986 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc
*rx_desc
,
989 skb
->rxhash
= le32_to_cpu(rx_desc
->wb
.lower
.hi_dword
.rss
);
993 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
994 * @adapter: address of board private structure
995 * @rx_desc: advanced rx descriptor
997 * Returns : true if it is FCoE pkt
999 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter
*adapter
,
1000 union ixgbe_adv_rx_desc
*rx_desc
)
1002 __le16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1004 return (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
1005 ((pkt_info
& cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK
)) ==
1006 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE
<<
1007 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT
)));
1011 * ixgbe_receive_skb - Send a completed packet up the stack
1012 * @adapter: board private structure
1013 * @skb: packet to send up
1014 * @status: hardware indication of status of receive
1015 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1016 * @rx_desc: rx descriptor
1018 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
1019 struct sk_buff
*skb
, u8 status
,
1020 struct ixgbe_ring
*ring
,
1021 union ixgbe_adv_rx_desc
*rx_desc
)
1023 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1024 struct napi_struct
*napi
= &q_vector
->napi
;
1025 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
1026 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
1028 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
1029 __vlan_hwaccel_put_tag(skb
, tag
);
1031 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
1032 napi_gro_receive(napi
, skb
);
1038 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1039 * @adapter: address of board private structure
1040 * @status_err: hardware indication of status of receive
1041 * @skb: skb currently being received and modified
1042 * @status_err: status error value of last descriptor in packet
1044 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
1045 union ixgbe_adv_rx_desc
*rx_desc
,
1046 struct sk_buff
*skb
,
1049 skb
->ip_summed
= CHECKSUM_NONE
;
1051 /* Rx csum disabled */
1052 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
1055 /* if IP and error */
1056 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
1057 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
1058 adapter
->hw_csum_rx_error
++;
1062 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
1065 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1066 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1069 * 82599 errata, UDP frames with a 0 checksum can be marked as
1072 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1073 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1076 adapter
->hw_csum_rx_error
++;
1080 /* It must be a TCP or UDP packet with a valid checksum */
1081 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1084 static inline void ixgbe_release_rx_desc(struct ixgbe_ring
*rx_ring
, u32 val
)
1087 * Force memory writes to complete before letting h/w
1088 * know there are new descriptors to fetch. (Only
1089 * applicable for weak-ordered memory model archs,
1093 writel(val
, rx_ring
->tail
);
1097 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1098 * @rx_ring: ring to place buffers on
1099 * @cleaned_count: number of buffers to replace
1101 void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*rx_ring
, u16 cleaned_count
)
1103 union ixgbe_adv_rx_desc
*rx_desc
;
1104 struct ixgbe_rx_buffer
*bi
;
1105 struct sk_buff
*skb
;
1106 u16 i
= rx_ring
->next_to_use
;
1108 /* do nothing if no valid netdev defined */
1109 if (!rx_ring
->netdev
)
1112 while (cleaned_count
--) {
1113 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1114 bi
= &rx_ring
->rx_buffer_info
[i
];
1118 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1119 rx_ring
->rx_buf_len
);
1121 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1124 /* initialize queue mapping */
1125 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1130 bi
->dma
= dma_map_single(rx_ring
->dev
,
1132 rx_ring
->rx_buf_len
,
1134 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
1135 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1141 if (ring_is_ps_enabled(rx_ring
)) {
1143 bi
->page
= alloc_page(GFP_ATOMIC
| __GFP_COLD
);
1145 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1150 if (!bi
->page_dma
) {
1151 /* use a half page if we're re-using */
1152 bi
->page_offset
^= PAGE_SIZE
/ 2;
1153 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
1158 if (dma_mapping_error(rx_ring
->dev
,
1160 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1166 /* Refresh the desc even if buffer_addrs didn't change
1167 * because each write-back erases this info. */
1168 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1169 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1171 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1172 rx_desc
->read
.hdr_addr
= 0;
1176 if (i
== rx_ring
->count
)
1181 if (rx_ring
->next_to_use
!= i
) {
1182 rx_ring
->next_to_use
= i
;
1183 ixgbe_release_rx_desc(rx_ring
, i
);
1187 static inline u16
ixgbe_get_hlen(union ixgbe_adv_rx_desc
*rx_desc
)
1189 /* HW will not DMA in data larger than the given buffer, even if it
1190 * parses the (NFS, of course) header to be larger. In that case, it
1191 * fills the header buffer and spills the rest into the page.
1193 u16 hdr_info
= le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
);
1194 u16 hlen
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1195 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1196 if (hlen
> IXGBE_RX_HDR_SIZE
)
1197 hlen
= IXGBE_RX_HDR_SIZE
;
1202 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1203 * @skb: pointer to the last skb in the rsc queue
1205 * This function changes a queue full of hw rsc buffers into a completed
1206 * packet. It uses the ->prev pointers to find the first packet and then
1207 * turns it into the frag list owner.
1209 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
1211 unsigned int frag_list_size
= 0;
1212 unsigned int skb_cnt
= 1;
1215 struct sk_buff
*prev
= skb
->prev
;
1216 frag_list_size
+= skb
->len
;
1222 skb_shinfo(skb
)->frag_list
= skb
->next
;
1224 skb
->len
+= frag_list_size
;
1225 skb
->data_len
+= frag_list_size
;
1226 skb
->truesize
+= frag_list_size
;
1227 IXGBE_RSC_CB(skb
)->skb_cnt
= skb_cnt
;
1232 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc
*rx_desc
)
1234 return !!(le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1235 IXGBE_RXDADV_RSCCNT_MASK
);
1238 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1239 struct ixgbe_ring
*rx_ring
,
1242 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1243 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1244 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1245 struct sk_buff
*skb
;
1246 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1247 const int current_node
= numa_node_id();
1250 #endif /* IXGBE_FCOE */
1253 u16 cleaned_count
= 0;
1254 bool pkt_is_rsc
= false;
1256 i
= rx_ring
->next_to_clean
;
1257 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1258 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1260 while (staterr
& IXGBE_RXD_STAT_DD
) {
1263 rmb(); /* read descriptor and rx_buffer_info after status DD */
1265 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1267 skb
= rx_buffer_info
->skb
;
1268 rx_buffer_info
->skb
= NULL
;
1269 prefetch(skb
->data
);
1271 if (ring_is_rsc_enabled(rx_ring
))
1272 pkt_is_rsc
= ixgbe_get_rsc_state(rx_desc
);
1274 /* linear means we are building an skb from multiple pages */
1275 if (!skb_is_nonlinear(skb
)) {
1278 !(staterr
& IXGBE_RXD_STAT_EOP
) &&
1281 * When HWRSC is enabled, delay unmapping
1282 * of the first packet. It carries the
1283 * header information, HW may still
1284 * access the header after the writeback.
1285 * Only unmap it when EOP is reached
1287 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1288 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1290 dma_unmap_single(rx_ring
->dev
,
1291 rx_buffer_info
->dma
,
1292 rx_ring
->rx_buf_len
,
1295 rx_buffer_info
->dma
= 0;
1297 if (ring_is_ps_enabled(rx_ring
)) {
1298 hlen
= ixgbe_get_hlen(rx_desc
);
1299 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1301 hlen
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1306 /* assume packet split since header is unmapped */
1307 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1311 dma_unmap_page(rx_ring
->dev
,
1312 rx_buffer_info
->page_dma
,
1315 rx_buffer_info
->page_dma
= 0;
1316 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1317 rx_buffer_info
->page
,
1318 rx_buffer_info
->page_offset
,
1321 if ((page_count(rx_buffer_info
->page
) == 1) &&
1322 (page_to_nid(rx_buffer_info
->page
) == current_node
))
1323 get_page(rx_buffer_info
->page
);
1325 rx_buffer_info
->page
= NULL
;
1327 skb
->len
+= upper_len
;
1328 skb
->data_len
+= upper_len
;
1329 skb
->truesize
+= PAGE_SIZE
/ 2;
1333 if (i
== rx_ring
->count
)
1336 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1341 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1342 IXGBE_RXDADV_NEXTP_SHIFT
;
1343 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1345 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1348 if (!(staterr
& IXGBE_RXD_STAT_EOP
)) {
1349 if (ring_is_ps_enabled(rx_ring
)) {
1350 rx_buffer_info
->skb
= next_buffer
->skb
;
1351 rx_buffer_info
->dma
= next_buffer
->dma
;
1352 next_buffer
->skb
= skb
;
1353 next_buffer
->dma
= 0;
1355 skb
->next
= next_buffer
->skb
;
1356 skb
->next
->prev
= skb
;
1358 rx_ring
->rx_stats
.non_eop_descs
++;
1363 skb
= ixgbe_transform_rsc_queue(skb
);
1364 /* if we got here without RSC the packet is invalid */
1366 __pskb_trim(skb
, 0);
1367 rx_buffer_info
->skb
= skb
;
1372 if (ring_is_rsc_enabled(rx_ring
)) {
1373 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1374 dma_unmap_single(rx_ring
->dev
,
1375 IXGBE_RSC_CB(skb
)->dma
,
1376 rx_ring
->rx_buf_len
,
1378 IXGBE_RSC_CB(skb
)->dma
= 0;
1379 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1383 if (ring_is_ps_enabled(rx_ring
))
1384 rx_ring
->rx_stats
.rsc_count
+=
1385 skb_shinfo(skb
)->nr_frags
;
1387 rx_ring
->rx_stats
.rsc_count
+=
1388 IXGBE_RSC_CB(skb
)->skb_cnt
;
1389 rx_ring
->rx_stats
.rsc_flush
++;
1392 /* ERR_MASK will only have valid bits if EOP set */
1393 if (unlikely(staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
)) {
1394 dev_kfree_skb_any(skb
);
1398 ixgbe_rx_checksum(adapter
, rx_desc
, skb
, staterr
);
1399 if (adapter
->netdev
->features
& NETIF_F_RXHASH
)
1400 ixgbe_rx_hash(rx_desc
, skb
);
1402 /* probably a little skewed due to removing CRC */
1403 total_rx_bytes
+= skb
->len
;
1406 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1408 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1409 if (ixgbe_rx_is_fcoe(adapter
, rx_desc
)) {
1410 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
,
1413 dev_kfree_skb_any(skb
);
1417 #endif /* IXGBE_FCOE */
1418 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1422 rx_desc
->wb
.upper
.status_error
= 0;
1427 /* return some buffers to hardware, one at a time is too slow */
1428 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1429 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1433 /* use prefetched values */
1435 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1438 rx_ring
->next_to_clean
= i
;
1439 cleaned_count
= ixgbe_desc_unused(rx_ring
);
1442 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1445 /* include DDPed FCoE data */
1446 if (ddp_bytes
> 0) {
1449 mss
= rx_ring
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1450 sizeof(struct fc_frame_header
) -
1451 sizeof(struct fcoe_crc_eof
);
1454 total_rx_bytes
+= ddp_bytes
;
1455 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1457 #endif /* IXGBE_FCOE */
1459 u64_stats_update_begin(&rx_ring
->syncp
);
1460 rx_ring
->stats
.packets
+= total_rx_packets
;
1461 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1462 u64_stats_update_end(&rx_ring
->syncp
);
1463 q_vector
->rx
.total_packets
+= total_rx_packets
;
1464 q_vector
->rx
.total_bytes
+= total_rx_bytes
;
1470 * ixgbe_configure_msix - Configure MSI-X hardware
1471 * @adapter: board private structure
1473 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1476 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1478 struct ixgbe_q_vector
*q_vector
;
1479 int q_vectors
, v_idx
;
1482 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1484 /* Populate MSIX to EITR Select */
1485 if (adapter
->num_vfs
> 32) {
1486 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
1487 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
1491 * Populate the IVAR table and set the ITR values to the
1492 * corresponding register.
1494 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1495 struct ixgbe_ring
*ring
;
1496 q_vector
= adapter
->q_vector
[v_idx
];
1498 for (ring
= q_vector
->rx
.ring
; ring
!= NULL
; ring
= ring
->next
)
1499 ixgbe_set_ivar(adapter
, 0, ring
->reg_idx
, v_idx
);
1501 for (ring
= q_vector
->tx
.ring
; ring
!= NULL
; ring
= ring
->next
)
1502 ixgbe_set_ivar(adapter
, 1, ring
->reg_idx
, v_idx
);
1504 if (q_vector
->tx
.ring
&& !q_vector
->rx
.ring
) {
1505 /* tx only vector */
1506 if (adapter
->tx_itr_setting
== 1)
1507 q_vector
->itr
= IXGBE_10K_ITR
;
1509 q_vector
->itr
= adapter
->tx_itr_setting
;
1511 /* rx or rx/tx vector */
1512 if (adapter
->rx_itr_setting
== 1)
1513 q_vector
->itr
= IXGBE_20K_ITR
;
1515 q_vector
->itr
= adapter
->rx_itr_setting
;
1518 ixgbe_write_eitr(q_vector
);
1521 switch (adapter
->hw
.mac
.type
) {
1522 case ixgbe_mac_82598EB
:
1523 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1526 case ixgbe_mac_82599EB
:
1527 case ixgbe_mac_X540
:
1528 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1533 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1535 /* set up to autoclear timer, and the vectors */
1536 mask
= IXGBE_EIMS_ENABLE_MASK
;
1537 mask
&= ~(IXGBE_EIMS_OTHER
|
1538 IXGBE_EIMS_MAILBOX
|
1541 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1544 enum latency_range
{
1548 latency_invalid
= 255
1552 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1553 * @q_vector: structure containing interrupt and ring information
1554 * @ring_container: structure containing ring performance data
1556 * Stores a new ITR value based on packets and byte
1557 * counts during the last interrupt. The advantage of per interrupt
1558 * computation is faster updates and more accurate ITR for the current
1559 * traffic pattern. Constants in this function were computed
1560 * based on theoretical maximum wire speed and thresholds were set based
1561 * on testing data as well as attempting to minimize response time
1562 * while increasing bulk throughput.
1563 * this functionality is controlled by the InterruptThrottleRate module
1564 * parameter (see ixgbe_param.c)
1566 static void ixgbe_update_itr(struct ixgbe_q_vector
*q_vector
,
1567 struct ixgbe_ring_container
*ring_container
)
1570 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1571 int bytes
= ring_container
->total_bytes
;
1572 int packets
= ring_container
->total_packets
;
1574 u8 itr_setting
= ring_container
->itr
;
1579 /* simple throttlerate management
1580 * 0-20MB/s lowest (100000 ints/s)
1581 * 20-100MB/s low (20000 ints/s)
1582 * 100-1249MB/s bulk (8000 ints/s)
1584 /* what was last interrupt timeslice? */
1585 timepassed_us
= q_vector
->itr
>> 2;
1586 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1588 switch (itr_setting
) {
1589 case lowest_latency
:
1590 if (bytes_perint
> adapter
->eitr_low
)
1591 itr_setting
= low_latency
;
1594 if (bytes_perint
> adapter
->eitr_high
)
1595 itr_setting
= bulk_latency
;
1596 else if (bytes_perint
<= adapter
->eitr_low
)
1597 itr_setting
= lowest_latency
;
1600 if (bytes_perint
<= adapter
->eitr_high
)
1601 itr_setting
= low_latency
;
1605 /* clear work counters since we have the values we need */
1606 ring_container
->total_bytes
= 0;
1607 ring_container
->total_packets
= 0;
1609 /* write updated itr to ring container */
1610 ring_container
->itr
= itr_setting
;
1614 * ixgbe_write_eitr - write EITR register in hardware specific way
1615 * @q_vector: structure containing interrupt and ring information
1617 * This function is made to be called by ethtool and by the driver
1618 * when it needs to update EITR registers at runtime. Hardware
1619 * specific quirks/differences are taken care of here.
1621 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1623 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1624 struct ixgbe_hw
*hw
= &adapter
->hw
;
1625 int v_idx
= q_vector
->v_idx
;
1626 u32 itr_reg
= q_vector
->itr
;
1628 switch (adapter
->hw
.mac
.type
) {
1629 case ixgbe_mac_82598EB
:
1630 /* must write high and low 16 bits to reset counter */
1631 itr_reg
|= (itr_reg
<< 16);
1633 case ixgbe_mac_82599EB
:
1634 case ixgbe_mac_X540
:
1636 * set the WDIS bit to not clear the timer bits and cause an
1637 * immediate assertion of the interrupt
1639 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1644 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1647 static void ixgbe_set_itr(struct ixgbe_q_vector
*q_vector
)
1649 u32 new_itr
= q_vector
->itr
;
1652 ixgbe_update_itr(q_vector
, &q_vector
->tx
);
1653 ixgbe_update_itr(q_vector
, &q_vector
->rx
);
1655 current_itr
= max(q_vector
->rx
.itr
, q_vector
->tx
.itr
);
1657 switch (current_itr
) {
1658 /* counts and packets in update_itr are dependent on these numbers */
1659 case lowest_latency
:
1660 new_itr
= IXGBE_100K_ITR
;
1663 new_itr
= IXGBE_20K_ITR
;
1666 new_itr
= IXGBE_8K_ITR
;
1672 if (new_itr
!= q_vector
->itr
) {
1673 /* do an exponential smoothing */
1674 new_itr
= (10 * new_itr
* q_vector
->itr
) /
1675 ((9 * new_itr
) + q_vector
->itr
);
1677 /* save the algorithm value here */
1678 q_vector
->itr
= new_itr
& IXGBE_MAX_EITR
;
1680 ixgbe_write_eitr(q_vector
);
1685 * ixgbe_check_overtemp_subtask - check for over tempurature
1686 * @adapter: pointer to adapter
1688 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter
*adapter
)
1690 struct ixgbe_hw
*hw
= &adapter
->hw
;
1691 u32 eicr
= adapter
->interrupt_event
;
1693 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
1696 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1697 !(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_EVENT
))
1700 adapter
->flags2
&= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1702 switch (hw
->device_id
) {
1703 case IXGBE_DEV_ID_82599_T3_LOM
:
1705 * Since the warning interrupt is for both ports
1706 * we don't have to check if:
1707 * - This interrupt wasn't for our port.
1708 * - We may have missed the interrupt so always have to
1709 * check if we got a LSC
1711 if (!(eicr
& IXGBE_EICR_GPI_SDP0
) &&
1712 !(eicr
& IXGBE_EICR_LSC
))
1715 if (!(eicr
& IXGBE_EICR_LSC
) && hw
->mac
.ops
.check_link
) {
1717 bool link_up
= false;
1719 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1725 /* Check if this is not due to overtemp */
1726 if (hw
->phy
.ops
.check_overtemp(hw
) != IXGBE_ERR_OVERTEMP
)
1731 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1736 "Network adapter has been stopped because it has over heated. "
1737 "Restart the computer. If the problem persists, "
1738 "power off the system and replace the adapter\n");
1740 adapter
->interrupt_event
= 0;
1743 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1745 struct ixgbe_hw
*hw
= &adapter
->hw
;
1747 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1748 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1749 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1750 /* write to clear the interrupt */
1751 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1755 static void ixgbe_check_overtemp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1757 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
))
1760 switch (adapter
->hw
.mac
.type
) {
1761 case ixgbe_mac_82599EB
:
1763 * Need to check link state so complete overtemp check
1766 if (((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)) &&
1767 (!test_bit(__IXGBE_DOWN
, &adapter
->state
))) {
1768 adapter
->interrupt_event
= eicr
;
1769 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1770 ixgbe_service_event_schedule(adapter
);
1774 case ixgbe_mac_X540
:
1775 if (!(eicr
& IXGBE_EICR_TS
))
1783 "Network adapter has been stopped because it has over heated. "
1784 "Restart the computer. If the problem persists, "
1785 "power off the system and replace the adapter\n");
1788 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1790 struct ixgbe_hw
*hw
= &adapter
->hw
;
1792 if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1793 /* Clear the interrupt */
1794 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1795 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1796 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
1797 ixgbe_service_event_schedule(adapter
);
1801 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1802 /* Clear the interrupt */
1803 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1804 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1805 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
1806 ixgbe_service_event_schedule(adapter
);
1811 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1813 struct ixgbe_hw
*hw
= &adapter
->hw
;
1816 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1817 adapter
->link_check_timeout
= jiffies
;
1818 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1819 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1820 IXGBE_WRITE_FLUSH(hw
);
1821 ixgbe_service_event_schedule(adapter
);
1825 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1829 struct ixgbe_hw
*hw
= &adapter
->hw
;
1831 switch (hw
->mac
.type
) {
1832 case ixgbe_mac_82598EB
:
1833 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1834 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, mask
);
1836 case ixgbe_mac_82599EB
:
1837 case ixgbe_mac_X540
:
1838 mask
= (qmask
& 0xFFFFFFFF);
1840 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(0), mask
);
1841 mask
= (qmask
>> 32);
1843 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(1), mask
);
1848 /* skip the flush */
1851 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1855 struct ixgbe_hw
*hw
= &adapter
->hw
;
1857 switch (hw
->mac
.type
) {
1858 case ixgbe_mac_82598EB
:
1859 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1860 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, mask
);
1862 case ixgbe_mac_82599EB
:
1863 case ixgbe_mac_X540
:
1864 mask
= (qmask
& 0xFFFFFFFF);
1866 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(0), mask
);
1867 mask
= (qmask
>> 32);
1869 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(1), mask
);
1874 /* skip the flush */
1878 * ixgbe_irq_enable - Enable default interrupt generation settings
1879 * @adapter: board private structure
1881 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
1884 u32 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
1886 /* don't reenable LSC while waiting for link */
1887 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
)
1888 mask
&= ~IXGBE_EIMS_LSC
;
1890 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
1891 switch (adapter
->hw
.mac
.type
) {
1892 case ixgbe_mac_82599EB
:
1893 mask
|= IXGBE_EIMS_GPI_SDP0
;
1895 case ixgbe_mac_X540
:
1896 mask
|= IXGBE_EIMS_TS
;
1901 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
1902 mask
|= IXGBE_EIMS_GPI_SDP1
;
1903 switch (adapter
->hw
.mac
.type
) {
1904 case ixgbe_mac_82599EB
:
1905 mask
|= IXGBE_EIMS_GPI_SDP1
;
1906 mask
|= IXGBE_EIMS_GPI_SDP2
;
1907 case ixgbe_mac_X540
:
1908 mask
|= IXGBE_EIMS_ECC
;
1909 mask
|= IXGBE_EIMS_MAILBOX
;
1914 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
1915 !(adapter
->flags2
& IXGBE_FLAG2_FDIR_REQUIRES_REINIT
))
1916 mask
|= IXGBE_EIMS_FLOW_DIR
;
1918 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1920 ixgbe_irq_enable_queues(adapter
, ~0);
1922 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1925 static irqreturn_t
ixgbe_msix_other(int irq
, void *data
)
1927 struct ixgbe_adapter
*adapter
= data
;
1928 struct ixgbe_hw
*hw
= &adapter
->hw
;
1932 * Workaround for Silicon errata. Use clear-by-write instead
1933 * of clear-by-read. Reading with EICS will return the
1934 * interrupt causes without clearing, which later be done
1935 * with the write to EICR.
1937 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1938 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1940 if (eicr
& IXGBE_EICR_LSC
)
1941 ixgbe_check_lsc(adapter
);
1943 if (eicr
& IXGBE_EICR_MAILBOX
)
1944 ixgbe_msg_task(adapter
);
1946 switch (hw
->mac
.type
) {
1947 case ixgbe_mac_82599EB
:
1948 case ixgbe_mac_X540
:
1949 if (eicr
& IXGBE_EICR_ECC
)
1950 e_info(link
, "Received unrecoverable ECC Err, please "
1952 /* Handle Flow Director Full threshold interrupt */
1953 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1954 int reinit_count
= 0;
1956 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1957 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
1958 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE
,
1963 /* no more flow director interrupts until after init */
1964 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_FLOW_DIR
);
1965 adapter
->flags2
|= IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
1966 ixgbe_service_event_schedule(adapter
);
1969 ixgbe_check_sfp_event(adapter
, eicr
);
1970 ixgbe_check_overtemp_event(adapter
, eicr
);
1976 ixgbe_check_fan_failure(adapter
, eicr
);
1978 /* re-enable the original interrupt state, no lsc, no queues */
1979 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1980 ixgbe_irq_enable(adapter
, false, false);
1985 static irqreturn_t
ixgbe_msix_clean_rings(int irq
, void *data
)
1987 struct ixgbe_q_vector
*q_vector
= data
;
1989 /* EIAM disabled interrupts (on this vector) for us */
1991 if (q_vector
->rx
.ring
|| q_vector
->tx
.ring
)
1992 napi_schedule(&q_vector
->napi
);
1997 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2000 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2001 struct ixgbe_ring
*rx_ring
= a
->rx_ring
[r_idx
];
2003 rx_ring
->q_vector
= q_vector
;
2004 rx_ring
->next
= q_vector
->rx
.ring
;
2005 q_vector
->rx
.ring
= rx_ring
;
2006 q_vector
->rx
.count
++;
2009 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2012 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2013 struct ixgbe_ring
*tx_ring
= a
->tx_ring
[t_idx
];
2015 tx_ring
->q_vector
= q_vector
;
2016 tx_ring
->next
= q_vector
->tx
.ring
;
2017 q_vector
->tx
.ring
= tx_ring
;
2018 q_vector
->tx
.count
++;
2019 q_vector
->tx
.work_limit
= a
->tx_work_limit
;
2023 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2024 * @adapter: board private structure to initialize
2026 * This function maps descriptor rings to the queue-specific vectors
2027 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2028 * one vector per ring/queue, but on a constrained vector budget, we
2029 * group the rings as "efficiently" as possible. You would add new
2030 * mapping configurations in here.
2032 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
)
2034 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2035 int rxr_remaining
= adapter
->num_rx_queues
, rxr_idx
= 0;
2036 int txr_remaining
= adapter
->num_tx_queues
, txr_idx
= 0;
2039 /* only one q_vector if MSI-X is disabled. */
2040 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2044 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2045 * group them so there are multiple queues per vector.
2047 * Re-adjusting *qpv takes care of the remainder.
2049 for (; v_start
< q_vectors
&& rxr_remaining
; v_start
++) {
2050 int rqpv
= DIV_ROUND_UP(rxr_remaining
, q_vectors
- v_start
);
2051 for (; rqpv
; rqpv
--, rxr_idx
++, rxr_remaining
--)
2052 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2056 * If there are not enough q_vectors for each ring to have it's own
2057 * vector then we must pair up Rx/Tx on a each vector
2059 if ((v_start
+ txr_remaining
) > q_vectors
)
2062 for (; v_start
< q_vectors
&& txr_remaining
; v_start
++) {
2063 int tqpv
= DIV_ROUND_UP(txr_remaining
, q_vectors
- v_start
);
2064 for (; tqpv
; tqpv
--, txr_idx
++, txr_remaining
--)
2065 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2070 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2071 * @adapter: board private structure
2073 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2074 * interrupts from the kernel.
2076 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2078 struct net_device
*netdev
= adapter
->netdev
;
2079 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2083 for (vector
= 0; vector
< q_vectors
; vector
++) {
2084 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[vector
];
2085 struct msix_entry
*entry
= &adapter
->msix_entries
[vector
];
2087 if (q_vector
->tx
.ring
&& q_vector
->rx
.ring
) {
2088 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2089 "%s-%s-%d", netdev
->name
, "TxRx", ri
++);
2091 } else if (q_vector
->rx
.ring
) {
2092 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2093 "%s-%s-%d", netdev
->name
, "rx", ri
++);
2094 } else if (q_vector
->tx
.ring
) {
2095 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2096 "%s-%s-%d", netdev
->name
, "tx", ti
++);
2098 /* skip this unused q_vector */
2101 err
= request_irq(entry
->vector
, &ixgbe_msix_clean_rings
, 0,
2102 q_vector
->name
, q_vector
);
2104 e_err(probe
, "request_irq failed for MSIX interrupt "
2105 "Error: %d\n", err
);
2106 goto free_queue_irqs
;
2108 /* If Flow Director is enabled, set interrupt affinity */
2109 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
2110 /* assign the mask for this irq */
2111 irq_set_affinity_hint(entry
->vector
,
2112 q_vector
->affinity_mask
);
2116 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2117 ixgbe_msix_other
, 0, netdev
->name
, adapter
);
2119 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2120 goto free_queue_irqs
;
2128 irq_set_affinity_hint(adapter
->msix_entries
[vector
].vector
,
2130 free_irq(adapter
->msix_entries
[vector
].vector
,
2131 adapter
->q_vector
[vector
]);
2133 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2134 pci_disable_msix(adapter
->pdev
);
2135 kfree(adapter
->msix_entries
);
2136 adapter
->msix_entries
= NULL
;
2141 * ixgbe_intr - legacy mode Interrupt Handler
2142 * @irq: interrupt number
2143 * @data: pointer to a network interface device structure
2145 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2147 struct ixgbe_adapter
*adapter
= data
;
2148 struct ixgbe_hw
*hw
= &adapter
->hw
;
2149 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2153 * Workaround for silicon errata on 82598. Mask the interrupts
2154 * before the read of EICR.
2156 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2158 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2159 * therefore no explicit interrupt disable is necessary */
2160 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2163 * shared interrupt alert!
2164 * make sure interrupts are enabled because the read will
2165 * have disabled interrupts due to EIAM
2166 * finish the workaround of silicon errata on 82598. Unmask
2167 * the interrupt that we masked before the EICR read.
2169 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2170 ixgbe_irq_enable(adapter
, true, true);
2171 return IRQ_NONE
; /* Not our interrupt */
2174 if (eicr
& IXGBE_EICR_LSC
)
2175 ixgbe_check_lsc(adapter
);
2177 switch (hw
->mac
.type
) {
2178 case ixgbe_mac_82599EB
:
2179 ixgbe_check_sfp_event(adapter
, eicr
);
2181 case ixgbe_mac_X540
:
2182 if (eicr
& IXGBE_EICR_ECC
)
2183 e_info(link
, "Received unrecoverable ECC err, please "
2185 ixgbe_check_overtemp_event(adapter
, eicr
);
2191 ixgbe_check_fan_failure(adapter
, eicr
);
2193 if (napi_schedule_prep(&(q_vector
->napi
))) {
2194 /* would disable interrupts here but EIAM disabled it */
2195 __napi_schedule(&(q_vector
->napi
));
2199 * re-enable link(maybe) and non-queue interrupts, no flush.
2200 * ixgbe_poll will re-enable the queue interrupts
2203 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2204 ixgbe_irq_enable(adapter
, false, false);
2209 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2211 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2214 /* legacy and MSI only use one vector */
2215 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2218 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2219 adapter
->rx_ring
[i
]->q_vector
= NULL
;
2220 adapter
->rx_ring
[i
]->next
= NULL
;
2222 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2223 adapter
->tx_ring
[i
]->q_vector
= NULL
;
2224 adapter
->tx_ring
[i
]->next
= NULL
;
2227 for (i
= 0; i
< q_vectors
; i
++) {
2228 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2229 memset(&q_vector
->rx
, 0, sizeof(struct ixgbe_ring_container
));
2230 memset(&q_vector
->tx
, 0, sizeof(struct ixgbe_ring_container
));
2235 * ixgbe_request_irq - initialize interrupts
2236 * @adapter: board private structure
2238 * Attempts to configure interrupts using the best available
2239 * capabilities of the hardware and kernel.
2241 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2243 struct net_device
*netdev
= adapter
->netdev
;
2246 /* map all of the rings to the q_vectors */
2247 ixgbe_map_rings_to_vectors(adapter
);
2249 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
2250 err
= ixgbe_request_msix_irqs(adapter
);
2251 else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)
2252 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2253 netdev
->name
, adapter
);
2255 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2256 netdev
->name
, adapter
);
2259 e_err(probe
, "request_irq failed, Error %d\n", err
);
2261 /* place q_vectors and rings back into a known good state */
2262 ixgbe_reset_q_vectors(adapter
);
2268 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2270 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2273 q_vectors
= adapter
->num_msix_vectors
;
2275 free_irq(adapter
->msix_entries
[i
].vector
, adapter
);
2278 for (; i
>= 0; i
--) {
2279 /* free only the irqs that were actually requested */
2280 if (!adapter
->q_vector
[i
]->rx
.ring
&&
2281 !adapter
->q_vector
[i
]->tx
.ring
)
2284 /* clear the affinity_mask in the IRQ descriptor */
2285 irq_set_affinity_hint(adapter
->msix_entries
[i
].vector
,
2288 free_irq(adapter
->msix_entries
[i
].vector
,
2289 adapter
->q_vector
[i
]);
2292 free_irq(adapter
->pdev
->irq
, adapter
);
2295 /* clear q_vector state information */
2296 ixgbe_reset_q_vectors(adapter
);
2300 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2301 * @adapter: board private structure
2303 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2305 switch (adapter
->hw
.mac
.type
) {
2306 case ixgbe_mac_82598EB
:
2307 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2309 case ixgbe_mac_82599EB
:
2310 case ixgbe_mac_X540
:
2311 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2312 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2313 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2318 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2319 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2321 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2322 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2324 synchronize_irq(adapter
->pdev
->irq
);
2329 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2332 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2334 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2337 if (adapter
->rx_itr_setting
== 1)
2338 q_vector
->itr
= IXGBE_20K_ITR
;
2340 q_vector
->itr
= adapter
->rx_itr_setting
;
2342 ixgbe_write_eitr(q_vector
);
2344 ixgbe_set_ivar(adapter
, 0, 0, 0);
2345 ixgbe_set_ivar(adapter
, 1, 0, 0);
2347 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2351 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2352 * @adapter: board private structure
2353 * @ring: structure containing ring specific data
2355 * Configure the Tx descriptor ring after a reset.
2357 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2358 struct ixgbe_ring
*ring
)
2360 struct ixgbe_hw
*hw
= &adapter
->hw
;
2361 u64 tdba
= ring
->dma
;
2363 u32 txdctl
= IXGBE_TXDCTL_ENABLE
;
2364 u8 reg_idx
= ring
->reg_idx
;
2366 /* disable queue to avoid issues while updating state */
2367 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), 0);
2368 IXGBE_WRITE_FLUSH(hw
);
2370 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2371 (tdba
& DMA_BIT_MASK(32)));
2372 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2373 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2374 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2375 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2376 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2377 ring
->tail
= hw
->hw_addr
+ IXGBE_TDT(reg_idx
);
2380 * set WTHRESH to encourage burst writeback, it should not be set
2381 * higher than 1 when ITR is 0 as it could cause false TX hangs
2383 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2384 * to or less than the number of on chip descriptors, which is
2387 if (!adapter
->tx_itr_setting
|| !adapter
->rx_itr_setting
)
2388 txdctl
|= (1 << 16); /* WTHRESH = 1 */
2390 txdctl
|= (8 << 16); /* WTHRESH = 8 */
2392 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2393 txdctl
|= (1 << 8) | /* HTHRESH = 1 */
2394 32; /* PTHRESH = 32 */
2396 /* reinitialize flowdirector state */
2397 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
2398 adapter
->atr_sample_rate
) {
2399 ring
->atr_sample_rate
= adapter
->atr_sample_rate
;
2400 ring
->atr_count
= 0;
2401 set_bit(__IXGBE_TX_FDIR_INIT_DONE
, &ring
->state
);
2403 ring
->atr_sample_rate
= 0;
2406 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &ring
->state
);
2409 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2411 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2412 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2413 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2416 /* poll to verify queue is enabled */
2418 usleep_range(1000, 2000);
2419 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2420 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2422 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2425 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2427 struct ixgbe_hw
*hw
= &adapter
->hw
;
2430 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2432 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2435 /* disable the arbiter while setting MTQC */
2436 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2437 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2438 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2440 /* set transmit pool layout */
2441 switch (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2442 case (IXGBE_FLAG_SRIOV_ENABLED
):
2443 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2444 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2448 reg
= IXGBE_MTQC_64Q_1PB
;
2450 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_4TC_4TQ
;
2452 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
;
2454 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, reg
);
2456 /* Enable Security TX Buffer IFG for multiple pb */
2458 reg
= IXGBE_READ_REG(hw
, IXGBE_SECTXMINIFG
);
2459 reg
|= IXGBE_SECTX_DCB
;
2460 IXGBE_WRITE_REG(hw
, IXGBE_SECTXMINIFG
, reg
);
2465 /* re-enable the arbiter */
2466 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2467 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2471 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2472 * @adapter: board private structure
2474 * Configure the Tx unit of the MAC after a reset.
2476 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2478 struct ixgbe_hw
*hw
= &adapter
->hw
;
2482 ixgbe_setup_mtqc(adapter
);
2484 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2485 /* DMATXCTL.EN must be before Tx queues are enabled */
2486 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2487 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2488 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2491 /* Setup the HW Tx Head and Tail descriptor pointers */
2492 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2493 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2496 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2498 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2499 struct ixgbe_ring
*rx_ring
)
2502 u8 reg_idx
= rx_ring
->reg_idx
;
2504 switch (adapter
->hw
.mac
.type
) {
2505 case ixgbe_mac_82598EB
: {
2506 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2507 const int mask
= feature
[RING_F_RSS
].mask
;
2508 reg_idx
= reg_idx
& mask
;
2511 case ixgbe_mac_82599EB
:
2512 case ixgbe_mac_X540
:
2517 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
));
2519 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2520 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2521 if (adapter
->num_vfs
)
2522 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2524 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2525 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2527 if (ring_is_ps_enabled(rx_ring
)) {
2528 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2529 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2531 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2533 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2535 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2536 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2537 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2540 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
), srrctl
);
2543 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2545 struct ixgbe_hw
*hw
= &adapter
->hw
;
2546 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2547 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2548 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2549 u32 mrqc
= 0, reta
= 0;
2552 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2553 int maxq
= adapter
->ring_feature
[RING_F_RSS
].indices
;
2556 maxq
= min(maxq
, adapter
->num_tx_queues
/ tcs
);
2558 /* Fill out hash function seeds */
2559 for (i
= 0; i
< 10; i
++)
2560 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2562 /* Fill out redirection table */
2563 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2566 /* reta = 4-byte sliding window of
2567 * 0x00..(indices-1)(indices-1)00..etc. */
2568 reta
= (reta
<< 8) | (j
* 0x11);
2570 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2573 /* Disable indicating checksum in descriptor, enables RSS hash */
2574 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2575 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2576 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2578 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
&&
2579 (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)) {
2580 mrqc
= IXGBE_MRQC_RSSEN
;
2582 int mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2583 | IXGBE_FLAG_SRIOV_ENABLED
);
2586 case (IXGBE_FLAG_RSS_ENABLED
):
2588 mrqc
= IXGBE_MRQC_RSSEN
;
2590 mrqc
= IXGBE_MRQC_RTRSS4TCEN
;
2592 mrqc
= IXGBE_MRQC_RTRSS8TCEN
;
2594 case (IXGBE_FLAG_SRIOV_ENABLED
):
2595 mrqc
= IXGBE_MRQC_VMDQEN
;
2602 /* Perform hash on these packet types */
2603 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2604 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2605 | IXGBE_MRQC_RSS_FIELD_IPV6
2606 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2608 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2612 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2613 * @adapter: address of board private structure
2614 * @index: index of ring to set
2616 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2617 struct ixgbe_ring
*ring
)
2619 struct ixgbe_hw
*hw
= &adapter
->hw
;
2622 u8 reg_idx
= ring
->reg_idx
;
2624 if (!ring_is_rsc_enabled(ring
))
2627 rx_buf_len
= ring
->rx_buf_len
;
2628 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2629 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2631 * we must limit the number of descriptors so that the
2632 * total size of max desc * buf_len is not greater
2635 if (ring_is_ps_enabled(ring
)) {
2636 #if (MAX_SKB_FRAGS > 16)
2637 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2638 #elif (MAX_SKB_FRAGS > 8)
2639 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2640 #elif (MAX_SKB_FRAGS > 4)
2641 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2643 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2646 if (rx_buf_len
< IXGBE_RXBUFFER_4K
)
2647 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2648 else if (rx_buf_len
< IXGBE_RXBUFFER_8K
)
2649 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2651 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2653 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2657 * ixgbe_set_uta - Set unicast filter table address
2658 * @adapter: board private structure
2660 * The unicast table address is a register array of 32-bit registers.
2661 * The table is meant to be used in a way similar to how the MTA is used
2662 * however due to certain limitations in the hardware it is necessary to
2663 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2664 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2666 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
2668 struct ixgbe_hw
*hw
= &adapter
->hw
;
2671 /* The UTA table only exists on 82599 hardware and newer */
2672 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
2675 /* we only need to do this if VMDq is enabled */
2676 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2679 for (i
= 0; i
< 128; i
++)
2680 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
2683 #define IXGBE_MAX_RX_DESC_POLL 10
2684 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2685 struct ixgbe_ring
*ring
)
2687 struct ixgbe_hw
*hw
= &adapter
->hw
;
2688 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2690 u8 reg_idx
= ring
->reg_idx
;
2692 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2693 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2694 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2698 usleep_range(1000, 2000);
2699 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2700 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
2703 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
2704 "the polling period\n", reg_idx
);
2708 void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
2709 struct ixgbe_ring
*ring
)
2711 struct ixgbe_hw
*hw
= &adapter
->hw
;
2712 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
2714 u8 reg_idx
= ring
->reg_idx
;
2716 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2717 rxdctl
&= ~IXGBE_RXDCTL_ENABLE
;
2719 /* write value back with RXDCTL.ENABLE bit cleared */
2720 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
2722 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2723 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2726 /* the hardware may take up to 100us to really disable the rx queue */
2729 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2730 } while (--wait_loop
&& (rxdctl
& IXGBE_RXDCTL_ENABLE
));
2733 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2734 "the polling period\n", reg_idx
);
2738 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
2739 struct ixgbe_ring
*ring
)
2741 struct ixgbe_hw
*hw
= &adapter
->hw
;
2742 u64 rdba
= ring
->dma
;
2744 u8 reg_idx
= ring
->reg_idx
;
2746 /* disable queue to avoid issues while updating state */
2747 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
2748 ixgbe_disable_rx_queue(adapter
, ring
);
2750 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
2751 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
2752 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
2753 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
2754 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
2755 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
2756 ring
->tail
= hw
->hw_addr
+ IXGBE_RDT(reg_idx
);
2758 ixgbe_configure_srrctl(adapter
, ring
);
2759 ixgbe_configure_rscctl(adapter
, ring
);
2761 /* If operating in IOV mode set RLPML for X540 */
2762 if ((adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) &&
2763 hw
->mac
.type
== ixgbe_mac_X540
) {
2764 rxdctl
&= ~IXGBE_RXDCTL_RLPMLMASK
;
2765 rxdctl
|= ((ring
->netdev
->mtu
+ ETH_HLEN
+
2766 ETH_FCS_LEN
+ VLAN_HLEN
) | IXGBE_RXDCTL_RLPML_EN
);
2769 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2771 * enable cache line friendly hardware writes:
2772 * PTHRESH=32 descriptors (half the internal cache),
2773 * this also removes ugly rx_no_buffer_count increment
2774 * HTHRESH=4 descriptors (to minimize latency on fetch)
2775 * WTHRESH=8 burst writeback up to two cache lines
2777 rxdctl
&= ~0x3FFFFF;
2781 /* enable receive descriptor ring */
2782 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2783 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
2785 ixgbe_rx_desc_queue_enable(adapter
, ring
);
2786 ixgbe_alloc_rx_buffers(ring
, ixgbe_desc_unused(ring
));
2789 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
2791 struct ixgbe_hw
*hw
= &adapter
->hw
;
2794 /* PSRTYPE must be initialized in non 82598 adapters */
2795 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2796 IXGBE_PSRTYPE_UDPHDR
|
2797 IXGBE_PSRTYPE_IPV4HDR
|
2798 IXGBE_PSRTYPE_L2HDR
|
2799 IXGBE_PSRTYPE_IPV6HDR
;
2801 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2804 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
2805 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
2807 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
2808 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
2812 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
2814 struct ixgbe_hw
*hw
= &adapter
->hw
;
2817 u32 reg_offset
, vf_shift
;
2821 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2824 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2825 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
2826 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
2827 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2829 vf_shift
= adapter
->num_vfs
% 32;
2830 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
2832 /* Enable only the PF's pool for Tx/Rx */
2833 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2834 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
2835 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2836 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
2837 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2839 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2840 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2843 * Set up VF register offsets for selected VT Mode,
2844 * i.e. 32 or 64 VFs for SR-IOV
2846 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2847 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
2848 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
2849 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
2851 /* enable Tx loopback for VF/PF communication */
2852 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2853 /* Enable MAC Anti-Spoofing */
2854 hw
->mac
.ops
.set_mac_anti_spoofing(hw
,
2855 (adapter
->num_vfs
!= 0),
2857 /* For VFs that have spoof checking turned off */
2858 for (i
= 0; i
< adapter
->num_vfs
; i
++) {
2859 if (!adapter
->vfinfo
[i
].spoofchk_enabled
)
2860 ixgbe_ndo_set_vf_spoofchk(adapter
->netdev
, i
, false);
2864 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
2866 struct ixgbe_hw
*hw
= &adapter
->hw
;
2867 struct net_device
*netdev
= adapter
->netdev
;
2868 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2870 struct ixgbe_ring
*rx_ring
;
2874 /* Decide whether to use packet split mode or not */
2876 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2878 /* Do not use packet split if we're in SR-IOV Mode */
2879 if (adapter
->num_vfs
)
2880 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
2882 /* Disable packet split due to 82599 erratum #45 */
2883 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2884 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
2887 /* adjust max frame to be able to do baby jumbo for FCoE */
2888 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
2889 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2890 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2892 #endif /* IXGBE_FCOE */
2893 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2894 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2895 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2896 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2898 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2901 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2902 max_frame
+= VLAN_HLEN
;
2904 /* Set the RX buffer length according to the mode */
2905 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2906 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2908 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2909 (netdev
->mtu
<= ETH_DATA_LEN
))
2910 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2912 * Make best use of allocation by using all but 1K of a
2913 * power of 2 allocation that will be used for skb->head.
2915 else if (max_frame
<= IXGBE_RXBUFFER_3K
)
2916 rx_buf_len
= IXGBE_RXBUFFER_3K
;
2917 else if (max_frame
<= IXGBE_RXBUFFER_7K
)
2918 rx_buf_len
= IXGBE_RXBUFFER_7K
;
2919 else if (max_frame
<= IXGBE_RXBUFFER_15K
)
2920 rx_buf_len
= IXGBE_RXBUFFER_15K
;
2922 rx_buf_len
= IXGBE_MAX_RXBUFFER
;
2925 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2926 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2927 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2928 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2931 * Setup the HW Rx Head and Tail Descriptor Pointers and
2932 * the Base and Length of the Rx Descriptor Ring
2934 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2935 rx_ring
= adapter
->rx_ring
[i
];
2936 rx_ring
->rx_buf_len
= rx_buf_len
;
2938 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2939 set_ring_ps_enabled(rx_ring
);
2941 clear_ring_ps_enabled(rx_ring
);
2943 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
2944 set_ring_rsc_enabled(rx_ring
);
2946 clear_ring_rsc_enabled(rx_ring
);
2949 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2950 struct ixgbe_ring_feature
*f
;
2951 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2952 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2953 clear_ring_ps_enabled(rx_ring
);
2954 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2955 rx_ring
->rx_buf_len
=
2956 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2957 } else if (!ring_is_rsc_enabled(rx_ring
) &&
2958 !ring_is_ps_enabled(rx_ring
)) {
2959 rx_ring
->rx_buf_len
=
2960 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2963 #endif /* IXGBE_FCOE */
2967 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
2969 struct ixgbe_hw
*hw
= &adapter
->hw
;
2970 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2972 switch (hw
->mac
.type
) {
2973 case ixgbe_mac_82598EB
:
2975 * For VMDq support of different descriptor types or
2976 * buffer sizes through the use of multiple SRRCTL
2977 * registers, RDRXCTL.MVMEN must be set to 1
2979 * also, the manual doesn't mention it clearly but DCA hints
2980 * will only use queue 0's tags unless this bit is set. Side
2981 * effects of setting this bit are only that SRRCTL must be
2982 * fully programmed [0..15]
2984 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2986 case ixgbe_mac_82599EB
:
2987 case ixgbe_mac_X540
:
2988 /* Disable RSC for ACK packets */
2989 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2990 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2991 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2992 /* hardware requires some bits to be set by default */
2993 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
2994 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2997 /* We should do nothing since we don't know this hardware */
3001 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3005 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3006 * @adapter: board private structure
3008 * Configure the Rx unit of the MAC after a reset.
3010 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3012 struct ixgbe_hw
*hw
= &adapter
->hw
;
3016 /* disable receives while setting up the descriptors */
3017 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3018 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3020 ixgbe_setup_psrtype(adapter
);
3021 ixgbe_setup_rdrxctl(adapter
);
3023 /* Program registers for the distribution of queues */
3024 ixgbe_setup_mrqc(adapter
);
3026 ixgbe_set_uta(adapter
);
3028 /* set_rx_buffer_len must be called before ring initialization */
3029 ixgbe_set_rx_buffer_len(adapter
);
3032 * Setup the HW Rx Head and Tail Descriptor Pointers and
3033 * the Base and Length of the Rx Descriptor Ring
3035 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3036 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3038 /* disable drop enable for 82598 parts */
3039 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3040 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3042 /* enable all receives */
3043 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3044 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3047 static int ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3049 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3050 struct ixgbe_hw
*hw
= &adapter
->hw
;
3051 int pool_ndx
= adapter
->num_vfs
;
3053 /* add VID to filter table */
3054 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3055 set_bit(vid
, adapter
->active_vlans
);
3060 static int ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3062 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3063 struct ixgbe_hw
*hw
= &adapter
->hw
;
3064 int pool_ndx
= adapter
->num_vfs
;
3066 /* remove VID from filter table */
3067 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3068 clear_bit(vid
, adapter
->active_vlans
);
3074 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3075 * @adapter: driver data
3077 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3079 struct ixgbe_hw
*hw
= &adapter
->hw
;
3082 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3083 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3084 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3088 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3089 * @adapter: driver data
3091 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3093 struct ixgbe_hw
*hw
= &adapter
->hw
;
3096 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3097 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3098 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3099 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3103 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3104 * @adapter: driver data
3106 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3108 struct ixgbe_hw
*hw
= &adapter
->hw
;
3112 switch (hw
->mac
.type
) {
3113 case ixgbe_mac_82598EB
:
3114 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3115 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3116 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3118 case ixgbe_mac_82599EB
:
3119 case ixgbe_mac_X540
:
3120 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3121 j
= adapter
->rx_ring
[i
]->reg_idx
;
3122 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3123 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3124 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3133 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3134 * @adapter: driver data
3136 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3138 struct ixgbe_hw
*hw
= &adapter
->hw
;
3142 switch (hw
->mac
.type
) {
3143 case ixgbe_mac_82598EB
:
3144 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3145 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3146 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3148 case ixgbe_mac_82599EB
:
3149 case ixgbe_mac_X540
:
3150 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3151 j
= adapter
->rx_ring
[i
]->reg_idx
;
3152 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3153 vlnctrl
|= IXGBE_RXDCTL_VME
;
3154 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3162 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3166 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3168 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3169 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3173 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3174 * @netdev: network interface device structure
3176 * Writes unicast address list to the RAR table.
3177 * Returns: -ENOMEM on failure/insufficient address space
3178 * 0 on no addresses written
3179 * X on writing X addresses to the RAR table
3181 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3183 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3184 struct ixgbe_hw
*hw
= &adapter
->hw
;
3185 unsigned int vfn
= adapter
->num_vfs
;
3186 unsigned int rar_entries
= IXGBE_MAX_PF_MACVLANS
;
3189 /* return ENOMEM indicating insufficient memory for addresses */
3190 if (netdev_uc_count(netdev
) > rar_entries
)
3193 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3194 struct netdev_hw_addr
*ha
;
3195 /* return error if we do not support writing to RAR table */
3196 if (!hw
->mac
.ops
.set_rar
)
3199 netdev_for_each_uc_addr(ha
, netdev
) {
3202 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3207 /* write the addresses in reverse order to avoid write combining */
3208 for (; rar_entries
> 0 ; rar_entries
--)
3209 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3215 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3216 * @netdev: network interface device structure
3218 * The set_rx_method entry point is called whenever the unicast/multicast
3219 * address list or the network interface flags are updated. This routine is
3220 * responsible for configuring the hardware for proper unicast, multicast and
3223 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3225 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3226 struct ixgbe_hw
*hw
= &adapter
->hw
;
3227 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3230 /* Check for Promiscuous and All Multicast modes */
3232 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3234 /* set all bits that we expect to always be set */
3235 fctrl
|= IXGBE_FCTRL_BAM
;
3236 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3237 fctrl
|= IXGBE_FCTRL_PMCF
;
3239 /* clear the bits we are changing the status of */
3240 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3242 if (netdev
->flags
& IFF_PROMISC
) {
3243 hw
->addr_ctrl
.user_set_promisc
= true;
3244 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3245 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3246 /* don't hardware filter vlans in promisc mode */
3247 ixgbe_vlan_filter_disable(adapter
);
3249 if (netdev
->flags
& IFF_ALLMULTI
) {
3250 fctrl
|= IXGBE_FCTRL_MPE
;
3251 vmolr
|= IXGBE_VMOLR_MPE
;
3254 * Write addresses to the MTA, if the attempt fails
3255 * then we should just turn on promiscuous mode so
3256 * that we can at least receive multicast traffic
3258 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3259 vmolr
|= IXGBE_VMOLR_ROMPE
;
3261 ixgbe_vlan_filter_enable(adapter
);
3262 hw
->addr_ctrl
.user_set_promisc
= false;
3264 * Write addresses to available RAR registers, if there is not
3265 * sufficient space to store all the addresses then enable
3266 * unicast promiscuous mode
3268 count
= ixgbe_write_uc_addr_list(netdev
);
3270 fctrl
|= IXGBE_FCTRL_UPE
;
3271 vmolr
|= IXGBE_VMOLR_ROPE
;
3275 if (adapter
->num_vfs
) {
3276 ixgbe_restore_vf_multicasts(adapter
);
3277 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3278 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3280 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3283 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3285 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3286 ixgbe_vlan_strip_enable(adapter
);
3288 ixgbe_vlan_strip_disable(adapter
);
3291 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3294 struct ixgbe_q_vector
*q_vector
;
3295 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3297 /* legacy and MSI only use one vector */
3298 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3301 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3302 q_vector
= adapter
->q_vector
[q_idx
];
3303 napi_enable(&q_vector
->napi
);
3307 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3310 struct ixgbe_q_vector
*q_vector
;
3311 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3313 /* legacy and MSI only use one vector */
3314 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3317 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3318 q_vector
= adapter
->q_vector
[q_idx
];
3319 napi_disable(&q_vector
->napi
);
3323 #ifdef CONFIG_IXGBE_DCB
3325 * ixgbe_configure_dcb - Configure DCB hardware
3326 * @adapter: ixgbe adapter struct
3328 * This is called by the driver on open to configure the DCB hardware.
3329 * This is also called by the gennetlink interface when reconfiguring
3332 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3334 struct ixgbe_hw
*hw
= &adapter
->hw
;
3335 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3337 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3338 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3339 netif_set_gso_max_size(adapter
->netdev
, 65536);
3343 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3344 netif_set_gso_max_size(adapter
->netdev
, 32768);
3347 /* Enable VLAN tag insert/strip */
3348 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3350 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3353 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3354 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3357 /* reconfigure the hardware */
3358 if (adapter
->dcbx_cap
& DCB_CAP_DCBX_VER_CEE
) {
3359 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3361 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3363 ixgbe_dcb_hw_config(hw
, &adapter
->dcb_cfg
);
3364 } else if (adapter
->ixgbe_ieee_ets
&& adapter
->ixgbe_ieee_pfc
) {
3365 ixgbe_dcb_hw_ets(&adapter
->hw
,
3366 adapter
->ixgbe_ieee_ets
,
3368 ixgbe_dcb_hw_pfc_config(&adapter
->hw
,
3369 adapter
->ixgbe_ieee_pfc
->pfc_en
,
3370 adapter
->ixgbe_ieee_ets
->prio_tc
);
3373 /* Enable RSS Hash per TC */
3374 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3378 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
3380 u8 cnt
= adapter
->netdev
->tc_to_txq
[i
].count
;
3385 reg
|= msb
<< IXGBE_RQTC_SHIFT_TC(i
);
3387 IXGBE_WRITE_REG(hw
, IXGBE_RQTC
, reg
);
3392 /* Additional bittime to account for IXGBE framing */
3393 #define IXGBE_ETH_FRAMING 20
3396 * ixgbe_hpbthresh - calculate high water mark for flow control
3398 * @adapter: board private structure to calculate for
3399 * @pb - packet buffer to calculate
3401 static int ixgbe_hpbthresh(struct ixgbe_adapter
*adapter
, int pb
)
3403 struct ixgbe_hw
*hw
= &adapter
->hw
;
3404 struct net_device
*dev
= adapter
->netdev
;
3405 int link
, tc
, kb
, marker
;
3408 /* Calculate max LAN frame size */
3409 tc
= link
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ IXGBE_ETH_FRAMING
;
3412 /* FCoE traffic class uses FCOE jumbo frames */
3413 if (dev
->features
& NETIF_F_FCOE_MTU
) {
3416 #ifdef CONFIG_IXGBE_DCB
3417 fcoe_pb
= netdev_get_prio_tc_map(dev
, adapter
->fcoe
.up
);
3420 if (fcoe_pb
== pb
&& tc
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
3421 tc
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3425 /* Calculate delay value for device */
3426 switch (hw
->mac
.type
) {
3427 case ixgbe_mac_X540
:
3428 dv_id
= IXGBE_DV_X540(link
, tc
);
3431 dv_id
= IXGBE_DV(link
, tc
);
3435 /* Loopback switch introduces additional latency */
3436 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3437 dv_id
+= IXGBE_B2BT(tc
);
3439 /* Delay value is calculated in bit times convert to KB */
3440 kb
= IXGBE_BT2KB(dv_id
);
3441 rx_pba
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(pb
)) >> 10;
3443 marker
= rx_pba
- kb
;
3445 /* It is possible that the packet buffer is not large enough
3446 * to provide required headroom. In this case throw an error
3447 * to user and a do the best we can.
3450 e_warn(drv
, "Packet Buffer(%i) can not provide enough"
3451 "headroom to support flow control."
3452 "Decrease MTU or number of traffic classes\n", pb
);
3460 * ixgbe_lpbthresh - calculate low water mark for for flow control
3462 * @adapter: board private structure to calculate for
3463 * @pb - packet buffer to calculate
3465 static int ixgbe_lpbthresh(struct ixgbe_adapter
*adapter
)
3467 struct ixgbe_hw
*hw
= &adapter
->hw
;
3468 struct net_device
*dev
= adapter
->netdev
;
3472 /* Calculate max LAN frame size */
3473 tc
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3475 /* Calculate delay value for device */
3476 switch (hw
->mac
.type
) {
3477 case ixgbe_mac_X540
:
3478 dv_id
= IXGBE_LOW_DV_X540(tc
);
3481 dv_id
= IXGBE_LOW_DV(tc
);
3485 /* Delay value is calculated in bit times convert to KB */
3486 return IXGBE_BT2KB(dv_id
);
3490 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3492 static void ixgbe_pbthresh_setup(struct ixgbe_adapter
*adapter
)
3494 struct ixgbe_hw
*hw
= &adapter
->hw
;
3495 int num_tc
= netdev_get_num_tc(adapter
->netdev
);
3501 hw
->fc
.low_water
= ixgbe_lpbthresh(adapter
);
3503 for (i
= 0; i
< num_tc
; i
++) {
3504 hw
->fc
.high_water
[i
] = ixgbe_hpbthresh(adapter
, i
);
3506 /* Low water marks must not be larger than high water marks */
3507 if (hw
->fc
.low_water
> hw
->fc
.high_water
[i
])
3508 hw
->fc
.low_water
= 0;
3512 static void ixgbe_configure_pb(struct ixgbe_adapter
*adapter
)
3514 struct ixgbe_hw
*hw
= &adapter
->hw
;
3516 u8 tc
= netdev_get_num_tc(adapter
->netdev
);
3518 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3519 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3520 hdrm
= 32 << adapter
->fdir_pballoc
;
3524 hw
->mac
.ops
.set_rxpba(hw
, tc
, hdrm
, PBA_STRATEGY_EQUAL
);
3525 ixgbe_pbthresh_setup(adapter
);
3528 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter
*adapter
)
3530 struct ixgbe_hw
*hw
= &adapter
->hw
;
3531 struct hlist_node
*node
, *node2
;
3532 struct ixgbe_fdir_filter
*filter
;
3534 spin_lock(&adapter
->fdir_perfect_lock
);
3536 if (!hlist_empty(&adapter
->fdir_filter_list
))
3537 ixgbe_fdir_set_input_mask_82599(hw
, &adapter
->fdir_mask
);
3539 hlist_for_each_entry_safe(filter
, node
, node2
,
3540 &adapter
->fdir_filter_list
, fdir_node
) {
3541 ixgbe_fdir_write_perfect_filter_82599(hw
,
3544 (filter
->action
== IXGBE_FDIR_DROP_QUEUE
) ?
3545 IXGBE_FDIR_DROP_QUEUE
:
3546 adapter
->rx_ring
[filter
->action
]->reg_idx
);
3549 spin_unlock(&adapter
->fdir_perfect_lock
);
3552 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3554 ixgbe_configure_pb(adapter
);
3555 #ifdef CONFIG_IXGBE_DCB
3556 ixgbe_configure_dcb(adapter
);
3559 ixgbe_set_rx_mode(adapter
->netdev
);
3560 ixgbe_restore_vlan(adapter
);
3563 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3564 ixgbe_configure_fcoe(adapter
);
3566 #endif /* IXGBE_FCOE */
3567 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3568 ixgbe_init_fdir_signature_82599(&adapter
->hw
,
3569 adapter
->fdir_pballoc
);
3570 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3571 ixgbe_init_fdir_perfect_82599(&adapter
->hw
,
3572 adapter
->fdir_pballoc
);
3573 ixgbe_fdir_filter_restore(adapter
);
3576 ixgbe_configure_virtualization(adapter
);
3578 ixgbe_configure_tx(adapter
);
3579 ixgbe_configure_rx(adapter
);
3582 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3584 switch (hw
->phy
.type
) {
3585 case ixgbe_phy_sfp_avago
:
3586 case ixgbe_phy_sfp_ftl
:
3587 case ixgbe_phy_sfp_intel
:
3588 case ixgbe_phy_sfp_unknown
:
3589 case ixgbe_phy_sfp_passive_tyco
:
3590 case ixgbe_phy_sfp_passive_unknown
:
3591 case ixgbe_phy_sfp_active_unknown
:
3592 case ixgbe_phy_sfp_ftl_active
:
3595 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3603 * ixgbe_sfp_link_config - set up SFP+ link
3604 * @adapter: pointer to private adapter struct
3606 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3609 * We are assuming the worst case scenario here, and that
3610 * is that an SFP was inserted/removed after the reset
3611 * but before SFP detection was enabled. As such the best
3612 * solution is to just start searching as soon as we start
3614 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
3615 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
3617 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
3621 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3622 * @hw: pointer to private hardware struct
3624 * Returns 0 on success, negative on failure
3626 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3629 bool negotiation
, link_up
= false;
3630 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3632 if (hw
->mac
.ops
.check_link
)
3633 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3638 autoneg
= hw
->phy
.autoneg_advertised
;
3639 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
3640 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3645 if (hw
->mac
.ops
.setup_link
)
3646 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3651 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3653 struct ixgbe_hw
*hw
= &adapter
->hw
;
3656 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3657 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3659 gpie
|= IXGBE_GPIE_EIAME
;
3661 * use EIAM to auto-mask when MSI-X interrupt is asserted
3662 * this saves a register write for every interrupt
3664 switch (hw
->mac
.type
) {
3665 case ixgbe_mac_82598EB
:
3666 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3668 case ixgbe_mac_82599EB
:
3669 case ixgbe_mac_X540
:
3671 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3672 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3676 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3677 * specifically only auto mask tx and rx interrupts */
3678 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3681 /* XXX: to interrupt immediately for EICS writes, enable this */
3682 /* gpie |= IXGBE_GPIE_EIMEN; */
3684 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3685 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3686 gpie
|= IXGBE_GPIE_VTMODE_64
;
3689 /* Enable Thermal over heat sensor interrupt */
3690 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) {
3691 switch (adapter
->hw
.mac
.type
) {
3692 case ixgbe_mac_82599EB
:
3693 gpie
|= IXGBE_SDP0_GPIEN
;
3695 case ixgbe_mac_X540
:
3696 gpie
|= IXGBE_EIMS_TS
;
3703 /* Enable fan failure interrupt */
3704 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3705 gpie
|= IXGBE_SDP1_GPIEN
;
3707 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3708 gpie
|= IXGBE_SDP1_GPIEN
;
3709 gpie
|= IXGBE_SDP2_GPIEN
;
3712 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3715 static void ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3717 struct ixgbe_hw
*hw
= &adapter
->hw
;
3721 ixgbe_get_hw_control(adapter
);
3722 ixgbe_setup_gpie(adapter
);
3724 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3725 ixgbe_configure_msix(adapter
);
3727 ixgbe_configure_msi_and_legacy(adapter
);
3729 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3730 if (hw
->mac
.ops
.enable_tx_laser
&&
3731 ((hw
->phy
.multispeed_fiber
) ||
3732 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
3733 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
3734 hw
->mac
.ops
.enable_tx_laser(hw
);
3736 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3737 ixgbe_napi_enable_all(adapter
);
3739 if (ixgbe_is_sfp(hw
)) {
3740 ixgbe_sfp_link_config(adapter
);
3742 err
= ixgbe_non_sfp_link_config(hw
);
3744 e_err(probe
, "link_config FAILED %d\n", err
);
3747 /* clear any pending interrupts, may auto mask */
3748 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3749 ixgbe_irq_enable(adapter
, true, true);
3752 * If this adapter has a fan, check to see if we had a failure
3753 * before we enabled the interrupt.
3755 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3756 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3757 if (esdp
& IXGBE_ESDP_SDP1
)
3758 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3761 /* enable transmits */
3762 netif_tx_start_all_queues(adapter
->netdev
);
3764 /* bring the link up in the watchdog, this could race with our first
3765 * link up interrupt but shouldn't be a problem */
3766 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3767 adapter
->link_check_timeout
= jiffies
;
3768 mod_timer(&adapter
->service_timer
, jiffies
);
3770 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3771 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3772 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3773 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3776 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3778 WARN_ON(in_interrupt());
3779 /* put off any impending NetWatchDogTimeout */
3780 adapter
->netdev
->trans_start
= jiffies
;
3782 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3783 usleep_range(1000, 2000);
3784 ixgbe_down(adapter
);
3786 * If SR-IOV enabled then wait a bit before bringing the adapter
3787 * back up to give the VFs time to respond to the reset. The
3788 * two second wait is based upon the watchdog timer cycle in
3791 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3794 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3797 void ixgbe_up(struct ixgbe_adapter
*adapter
)
3799 /* hardware has been reset, we need to reload some things */
3800 ixgbe_configure(adapter
);
3802 ixgbe_up_complete(adapter
);
3805 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3807 struct ixgbe_hw
*hw
= &adapter
->hw
;
3810 /* lock SFP init bit to prevent race conditions with the watchdog */
3811 while (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
3812 usleep_range(1000, 2000);
3814 /* clear all SFP and link config related flags while holding SFP_INIT */
3815 adapter
->flags2
&= ~(IXGBE_FLAG2_SEARCH_FOR_SFP
|
3816 IXGBE_FLAG2_SFP_NEEDS_RESET
);
3817 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
3819 err
= hw
->mac
.ops
.init_hw(hw
);
3822 case IXGBE_ERR_SFP_NOT_PRESENT
:
3823 case IXGBE_ERR_SFP_NOT_SUPPORTED
:
3825 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3826 e_dev_err("master disable timed out\n");
3828 case IXGBE_ERR_EEPROM_VERSION
:
3829 /* We are running on a pre-production device, log a warning */
3830 e_dev_warn("This device is a pre-production adapter/LOM. "
3831 "Please be aware there may be issues associated with "
3832 "your hardware. If you are experiencing problems "
3833 "please contact your Intel or hardware "
3834 "representative who provided you with this "
3838 e_dev_err("Hardware Error: %d\n", err
);
3841 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
3843 /* reprogram the RAR[0] in case user changed it. */
3844 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3849 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3850 * @rx_ring: ring to free buffers from
3852 static void ixgbe_clean_rx_ring(struct ixgbe_ring
*rx_ring
)
3854 struct device
*dev
= rx_ring
->dev
;
3858 /* ring already cleared, nothing to do */
3859 if (!rx_ring
->rx_buffer_info
)
3862 /* Free all the Rx ring sk_buffs */
3863 for (i
= 0; i
< rx_ring
->count
; i
++) {
3864 struct ixgbe_rx_buffer
*rx_buffer_info
;
3866 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3867 if (rx_buffer_info
->dma
) {
3868 dma_unmap_single(rx_ring
->dev
, rx_buffer_info
->dma
,
3869 rx_ring
->rx_buf_len
,
3871 rx_buffer_info
->dma
= 0;
3873 if (rx_buffer_info
->skb
) {
3874 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3875 rx_buffer_info
->skb
= NULL
;
3877 struct sk_buff
*this = skb
;
3878 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3879 dma_unmap_single(dev
,
3880 IXGBE_RSC_CB(this)->dma
,
3881 rx_ring
->rx_buf_len
,
3883 IXGBE_RSC_CB(this)->dma
= 0;
3884 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3887 dev_kfree_skb(this);
3890 if (!rx_buffer_info
->page
)
3892 if (rx_buffer_info
->page_dma
) {
3893 dma_unmap_page(dev
, rx_buffer_info
->page_dma
,
3894 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3895 rx_buffer_info
->page_dma
= 0;
3897 put_page(rx_buffer_info
->page
);
3898 rx_buffer_info
->page
= NULL
;
3899 rx_buffer_info
->page_offset
= 0;
3902 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3903 memset(rx_ring
->rx_buffer_info
, 0, size
);
3905 /* Zero out the descriptor ring */
3906 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3908 rx_ring
->next_to_clean
= 0;
3909 rx_ring
->next_to_use
= 0;
3913 * ixgbe_clean_tx_ring - Free Tx Buffers
3914 * @tx_ring: ring to be cleaned
3916 static void ixgbe_clean_tx_ring(struct ixgbe_ring
*tx_ring
)
3918 struct ixgbe_tx_buffer
*tx_buffer_info
;
3922 /* ring already cleared, nothing to do */
3923 if (!tx_ring
->tx_buffer_info
)
3926 /* Free all the Tx ring sk_buffs */
3927 for (i
= 0; i
< tx_ring
->count
; i
++) {
3928 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3929 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
3932 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3933 memset(tx_ring
->tx_buffer_info
, 0, size
);
3935 /* Zero out the descriptor ring */
3936 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3938 tx_ring
->next_to_use
= 0;
3939 tx_ring
->next_to_clean
= 0;
3943 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3944 * @adapter: board private structure
3946 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3950 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3951 ixgbe_clean_rx_ring(adapter
->rx_ring
[i
]);
3955 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3956 * @adapter: board private structure
3958 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3962 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3963 ixgbe_clean_tx_ring(adapter
->tx_ring
[i
]);
3966 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter
*adapter
)
3968 struct hlist_node
*node
, *node2
;
3969 struct ixgbe_fdir_filter
*filter
;
3971 spin_lock(&adapter
->fdir_perfect_lock
);
3973 hlist_for_each_entry_safe(filter
, node
, node2
,
3974 &adapter
->fdir_filter_list
, fdir_node
) {
3975 hlist_del(&filter
->fdir_node
);
3978 adapter
->fdir_filter_count
= 0;
3980 spin_unlock(&adapter
->fdir_perfect_lock
);
3983 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3985 struct net_device
*netdev
= adapter
->netdev
;
3986 struct ixgbe_hw
*hw
= &adapter
->hw
;
3990 /* signal that we are down to the interrupt handler */
3991 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3993 /* disable receives */
3994 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3995 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3997 /* disable all enabled rx queues */
3998 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3999 /* this call also flushes the previous write */
4000 ixgbe_disable_rx_queue(adapter
, adapter
->rx_ring
[i
]);
4002 usleep_range(10000, 20000);
4004 netif_tx_stop_all_queues(netdev
);
4006 /* call carrier off first to avoid false dev_watchdog timeouts */
4007 netif_carrier_off(netdev
);
4008 netif_tx_disable(netdev
);
4010 ixgbe_irq_disable(adapter
);
4012 ixgbe_napi_disable_all(adapter
);
4014 adapter
->flags2
&= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT
|
4015 IXGBE_FLAG2_RESET_REQUESTED
);
4016 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
4018 del_timer_sync(&adapter
->service_timer
);
4020 if (adapter
->num_vfs
) {
4021 /* Clear EITR Select mapping */
4022 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
4024 /* Mark all the VFs as inactive */
4025 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
4026 adapter
->vfinfo
[i
].clear_to_send
= false;
4028 /* ping all the active vfs to let them know we are going down */
4029 ixgbe_ping_all_vfs(adapter
);
4031 /* Disable all VFTE/VFRE TX/RX */
4032 ixgbe_disable_tx_rx(adapter
);
4035 /* disable transmits in the hardware now that interrupts are off */
4036 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4037 u8 reg_idx
= adapter
->tx_ring
[i
]->reg_idx
;
4038 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), IXGBE_TXDCTL_SWFLSH
);
4041 /* Disable the Tx DMA engine on 82599 and X540 */
4042 switch (hw
->mac
.type
) {
4043 case ixgbe_mac_82599EB
:
4044 case ixgbe_mac_X540
:
4045 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
4046 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
4047 ~IXGBE_DMATXCTL_TE
));
4053 if (!pci_channel_offline(adapter
->pdev
))
4054 ixgbe_reset(adapter
);
4056 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4057 if (hw
->mac
.ops
.disable_tx_laser
&&
4058 ((hw
->phy
.multispeed_fiber
) ||
4059 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
4060 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
4061 hw
->mac
.ops
.disable_tx_laser(hw
);
4063 ixgbe_clean_all_tx_rings(adapter
);
4064 ixgbe_clean_all_rx_rings(adapter
);
4066 #ifdef CONFIG_IXGBE_DCA
4067 /* since we reset the hardware DCA settings were cleared */
4068 ixgbe_setup_dca(adapter
);
4073 * ixgbe_poll - NAPI Rx polling callback
4074 * @napi: structure for representing this polling device
4075 * @budget: how many packets driver is allowed to clean
4077 * This function is used for legacy and MSI, NAPI mode
4079 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
4081 struct ixgbe_q_vector
*q_vector
=
4082 container_of(napi
, struct ixgbe_q_vector
, napi
);
4083 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
4084 struct ixgbe_ring
*ring
;
4085 int per_ring_budget
;
4086 bool clean_complete
= true;
4088 #ifdef CONFIG_IXGBE_DCA
4089 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
4090 ixgbe_update_dca(q_vector
);
4093 for (ring
= q_vector
->tx
.ring
; ring
!= NULL
; ring
= ring
->next
)
4094 clean_complete
&= !!ixgbe_clean_tx_irq(q_vector
, ring
);
4096 /* attempt to distribute budget to each queue fairly, but don't allow
4097 * the budget to go below 1 because we'll exit polling */
4098 if (q_vector
->rx
.count
> 1)
4099 per_ring_budget
= max(budget
/q_vector
->rx
.count
, 1);
4101 per_ring_budget
= budget
;
4103 for (ring
= q_vector
->rx
.ring
; ring
!= NULL
; ring
= ring
->next
)
4104 clean_complete
&= ixgbe_clean_rx_irq(q_vector
, ring
,
4107 /* If all work not completed, return budget and keep polling */
4108 if (!clean_complete
)
4111 /* all work done, exit the polling mode */
4112 napi_complete(napi
);
4113 if (adapter
->rx_itr_setting
& 1)
4114 ixgbe_set_itr(q_vector
);
4115 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
4116 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
4122 * ixgbe_tx_timeout - Respond to a Tx Hang
4123 * @netdev: network interface device structure
4125 static void ixgbe_tx_timeout(struct net_device
*netdev
)
4127 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4129 /* Do the reset outside of interrupt context */
4130 ixgbe_tx_timeout_reset(adapter
);
4134 * ixgbe_set_rss_queues: Allocate queues for RSS
4135 * @adapter: board private structure to initialize
4137 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4138 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4141 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4144 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4146 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4148 adapter
->num_rx_queues
= f
->indices
;
4149 adapter
->num_tx_queues
= f
->indices
;
4159 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4160 * @adapter: board private structure to initialize
4162 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4163 * to the original CPU that initiated the Tx session. This runs in addition
4164 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4165 * Rx load across CPUs using RSS.
4168 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4171 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4173 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4176 /* Flow Director must have RSS enabled */
4177 if ((adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) &&
4178 (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)) {
4179 adapter
->num_tx_queues
= f_fdir
->indices
;
4180 adapter
->num_rx_queues
= f_fdir
->indices
;
4183 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4190 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4191 * @adapter: board private structure to initialize
4193 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4194 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4195 * rx queues out of the max number of rx queues, instead, it is used as the
4196 * index of the first rx queue used by FCoE.
4199 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4201 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4203 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4206 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4208 adapter
->num_rx_queues
= 1;
4209 adapter
->num_tx_queues
= 1;
4211 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4212 e_info(probe
, "FCoE enabled with RSS\n");
4213 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
4214 ixgbe_set_fdir_queues(adapter
);
4216 ixgbe_set_rss_queues(adapter
);
4219 /* adding FCoE rx rings to the end */
4220 f
->mask
= adapter
->num_rx_queues
;
4221 adapter
->num_rx_queues
+= f
->indices
;
4222 adapter
->num_tx_queues
+= f
->indices
;
4226 #endif /* IXGBE_FCOE */
4228 /* Artificial max queue cap per traffic class in DCB mode */
4229 #define DCB_QUEUE_CAP 8
4231 #ifdef CONFIG_IXGBE_DCB
4232 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
4234 int per_tc_q
, q
, i
, offset
= 0;
4235 struct net_device
*dev
= adapter
->netdev
;
4236 int tcs
= netdev_get_num_tc(dev
);
4241 /* Map queue offset and counts onto allocated tx queues */
4242 per_tc_q
= min(dev
->num_tx_queues
/ tcs
, (unsigned int)DCB_QUEUE_CAP
);
4243 q
= min((int)num_online_cpus(), per_tc_q
);
4245 for (i
= 0; i
< tcs
; i
++) {
4246 netdev_set_tc_queue(dev
, i
, q
, offset
);
4250 adapter
->num_tx_queues
= q
* tcs
;
4251 adapter
->num_rx_queues
= q
* tcs
;
4254 /* FCoE enabled queues require special configuration indexed
4255 * by feature specific indices and mask. Here we map FCoE
4256 * indices onto the DCB queue pairs allowing FCoE to own
4257 * configuration later.
4259 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4261 struct ixgbe_ring_feature
*f
=
4262 &adapter
->ring_feature
[RING_F_FCOE
];
4264 tc
= netdev_get_prio_tc_map(dev
, adapter
->fcoe
.up
);
4265 f
->indices
= dev
->tc_to_txq
[tc
].count
;
4266 f
->mask
= dev
->tc_to_txq
[tc
].offset
;
4275 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4276 * @adapter: board private structure to initialize
4278 * IOV doesn't actually use anything, so just NAK the
4279 * request for now and let the other queue routines
4280 * figure out what to do.
4282 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4288 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4289 * @adapter: board private structure to initialize
4291 * This is the top level queue allocation routine. The order here is very
4292 * important, starting with the "most" number of features turned on at once,
4293 * and ending with the smallest set of features. This way large combinations
4294 * can be allocated if they're turned on, and smaller combinations are the
4295 * fallthrough conditions.
4298 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4300 /* Start with base case */
4301 adapter
->num_rx_queues
= 1;
4302 adapter
->num_tx_queues
= 1;
4303 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4304 adapter
->num_rx_queues_per_pool
= 1;
4306 if (ixgbe_set_sriov_queues(adapter
))
4309 #ifdef CONFIG_IXGBE_DCB
4310 if (ixgbe_set_dcb_queues(adapter
))
4315 if (ixgbe_set_fcoe_queues(adapter
))
4318 #endif /* IXGBE_FCOE */
4319 if (ixgbe_set_fdir_queues(adapter
))
4322 if (ixgbe_set_rss_queues(adapter
))
4325 /* fallback to base case */
4326 adapter
->num_rx_queues
= 1;
4327 adapter
->num_tx_queues
= 1;
4330 /* Notify the stack of the (possibly) reduced queue counts. */
4331 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4332 return netif_set_real_num_rx_queues(adapter
->netdev
,
4333 adapter
->num_rx_queues
);
4336 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4339 int err
, vector_threshold
;
4341 /* We'll want at least 3 (vector_threshold):
4344 * 3) Other (Link Status Change, etc.)
4345 * 4) TCP Timer (optional)
4347 vector_threshold
= MIN_MSIX_COUNT
;
4349 /* The more we get, the more we will assign to Tx/Rx Cleanup
4350 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4351 * Right now, we simply care about how many we'll get; we'll
4352 * set them up later while requesting irq's.
4354 while (vectors
>= vector_threshold
) {
4355 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4357 if (!err
) /* Success in acquiring all requested vectors. */
4360 vectors
= 0; /* Nasty failure, quit now */
4361 else /* err == number of vectors we should try again with */
4365 if (vectors
< vector_threshold
) {
4366 /* Can't allocate enough MSI-X interrupts? Oh well.
4367 * This just means we'll go with either a single MSI
4368 * vector or fall back to legacy interrupts.
4370 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4371 "Unable to allocate MSI-X interrupts\n");
4372 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4373 kfree(adapter
->msix_entries
);
4374 adapter
->msix_entries
= NULL
;
4376 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4378 * Adjust for only the vectors we'll use, which is minimum
4379 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4380 * vectors we were allocated.
4382 adapter
->num_msix_vectors
= min(vectors
,
4383 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4388 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4389 * @adapter: board private structure to initialize
4391 * Cache the descriptor ring offsets for RSS to the assigned rings.
4394 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4398 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
4401 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4402 adapter
->rx_ring
[i
]->reg_idx
= i
;
4403 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4404 adapter
->tx_ring
[i
]->reg_idx
= i
;
4409 #ifdef CONFIG_IXGBE_DCB
4411 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4412 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter
*adapter
, u8 tc
,
4413 unsigned int *tx
, unsigned int *rx
)
4415 struct net_device
*dev
= adapter
->netdev
;
4416 struct ixgbe_hw
*hw
= &adapter
->hw
;
4417 u8 num_tcs
= netdev_get_num_tc(dev
);
4422 switch (hw
->mac
.type
) {
4423 case ixgbe_mac_82598EB
:
4427 case ixgbe_mac_82599EB
:
4428 case ixgbe_mac_X540
:
4433 } else if (tc
< 5) {
4434 *tx
= ((tc
+ 2) << 4);
4436 } else if (tc
< num_tcs
) {
4437 *tx
= ((tc
+ 8) << 3);
4466 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4467 * @adapter: board private structure to initialize
4469 * Cache the descriptor ring offsets for DCB to the assigned rings.
4472 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4474 struct net_device
*dev
= adapter
->netdev
;
4476 u8 num_tcs
= netdev_get_num_tc(dev
);
4481 for (i
= 0, k
= 0; i
< num_tcs
; i
++) {
4482 unsigned int tx_s
, rx_s
;
4483 u16 count
= dev
->tc_to_txq
[i
].count
;
4485 ixgbe_get_first_reg_idx(adapter
, i
, &tx_s
, &rx_s
);
4486 for (j
= 0; j
< count
; j
++, k
++) {
4487 adapter
->tx_ring
[k
]->reg_idx
= tx_s
+ j
;
4488 adapter
->rx_ring
[k
]->reg_idx
= rx_s
+ j
;
4489 adapter
->tx_ring
[k
]->dcb_tc
= i
;
4490 adapter
->rx_ring
[k
]->dcb_tc
= i
;
4499 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4500 * @adapter: board private structure to initialize
4502 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4505 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4510 if ((adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) &&
4511 (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)) {
4512 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4513 adapter
->rx_ring
[i
]->reg_idx
= i
;
4514 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4515 adapter
->tx_ring
[i
]->reg_idx
= i
;
4524 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4525 * @adapter: board private structure to initialize
4527 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4530 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4532 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4534 u8 fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4536 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4539 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4540 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
)
4541 ixgbe_cache_ring_fdir(adapter
);
4543 ixgbe_cache_ring_rss(adapter
);
4545 fcoe_rx_i
= f
->mask
;
4546 fcoe_tx_i
= f
->mask
;
4548 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4549 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4550 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4555 #endif /* IXGBE_FCOE */
4557 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4558 * @adapter: board private structure to initialize
4560 * SR-IOV doesn't use any descriptor rings but changes the default if
4561 * no other mapping is used.
4564 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4566 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4567 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4568 if (adapter
->num_vfs
)
4575 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4576 * @adapter: board private structure to initialize
4578 * Once we know the feature-set enabled for the device, we'll cache
4579 * the register offset the descriptor ring is assigned to.
4581 * Note, the order the various feature calls is important. It must start with
4582 * the "most" features enabled at the same time, then trickle down to the
4583 * least amount of features turned on at once.
4585 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4587 /* start with default case */
4588 adapter
->rx_ring
[0]->reg_idx
= 0;
4589 adapter
->tx_ring
[0]->reg_idx
= 0;
4591 if (ixgbe_cache_ring_sriov(adapter
))
4594 #ifdef CONFIG_IXGBE_DCB
4595 if (ixgbe_cache_ring_dcb(adapter
))
4600 if (ixgbe_cache_ring_fcoe(adapter
))
4602 #endif /* IXGBE_FCOE */
4604 if (ixgbe_cache_ring_fdir(adapter
))
4607 if (ixgbe_cache_ring_rss(adapter
))
4612 * ixgbe_alloc_queues - Allocate memory for all rings
4613 * @adapter: board private structure to initialize
4615 * We allocate one ring per queue at run-time since we don't know the
4616 * number of queues at compile-time. The polling_netdev array is
4617 * intended for Multiqueue, but should work fine with a single queue.
4619 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4621 int rx
= 0, tx
= 0, nid
= adapter
->node
;
4623 if (nid
< 0 || !node_online(nid
))
4624 nid
= first_online_node
;
4626 for (; tx
< adapter
->num_tx_queues
; tx
++) {
4627 struct ixgbe_ring
*ring
;
4629 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4631 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4633 goto err_allocation
;
4634 ring
->count
= adapter
->tx_ring_count
;
4635 ring
->queue_index
= tx
;
4636 ring
->numa_node
= nid
;
4637 ring
->dev
= &adapter
->pdev
->dev
;
4638 ring
->netdev
= adapter
->netdev
;
4640 adapter
->tx_ring
[tx
] = ring
;
4643 for (; rx
< adapter
->num_rx_queues
; rx
++) {
4644 struct ixgbe_ring
*ring
;
4646 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4648 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4650 goto err_allocation
;
4651 ring
->count
= adapter
->rx_ring_count
;
4652 ring
->queue_index
= rx
;
4653 ring
->numa_node
= nid
;
4654 ring
->dev
= &adapter
->pdev
->dev
;
4655 ring
->netdev
= adapter
->netdev
;
4657 adapter
->rx_ring
[rx
] = ring
;
4660 ixgbe_cache_ring_register(adapter
);
4666 kfree(adapter
->tx_ring
[--tx
]);
4669 kfree(adapter
->rx_ring
[--rx
]);
4674 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4675 * @adapter: board private structure to initialize
4677 * Attempt to configure the interrupts using the best available
4678 * capabilities of the hardware and the kernel.
4680 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4682 struct ixgbe_hw
*hw
= &adapter
->hw
;
4684 int vector
, v_budget
;
4687 * It's easy to be greedy for MSI-X vectors, but it really
4688 * doesn't do us much good if we have a lot more vectors
4689 * than CPU's. So let's be conservative and only ask for
4690 * (roughly) the same number of vectors as there are CPU's.
4692 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4693 (int)num_online_cpus()) + NON_Q_VECTORS
;
4696 * At the same time, hardware can only support a maximum of
4697 * hw.mac->max_msix_vectors vectors. With features
4698 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4699 * descriptor queues supported by our device. Thus, we cap it off in
4700 * those rare cases where the cpu count also exceeds our vector limit.
4702 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4704 /* A failure in MSI-X entry allocation isn't fatal, but it does
4705 * mean we disable MSI-X capabilities of the adapter. */
4706 adapter
->msix_entries
= kcalloc(v_budget
,
4707 sizeof(struct msix_entry
), GFP_KERNEL
);
4708 if (adapter
->msix_entries
) {
4709 for (vector
= 0; vector
< v_budget
; vector
++)
4710 adapter
->msix_entries
[vector
].entry
= vector
;
4712 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4714 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4718 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4719 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4720 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
4722 "ATR is not supported while multiple "
4723 "queues are disabled. Disabling Flow Director\n");
4725 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4726 adapter
->atr_sample_rate
= 0;
4727 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4728 ixgbe_disable_sriov(adapter
);
4730 err
= ixgbe_set_num_queues(adapter
);
4734 err
= pci_enable_msi(adapter
->pdev
);
4736 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4738 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4739 "Unable to allocate MSI interrupt, "
4740 "falling back to legacy. Error: %d\n", err
);
4750 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4751 * @adapter: board private structure to initialize
4753 * We allocate one q_vector per queue interrupt. If allocation fails we
4756 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4758 int v_idx
, num_q_vectors
;
4759 struct ixgbe_q_vector
*q_vector
;
4761 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4762 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4766 for (v_idx
= 0; v_idx
< num_q_vectors
; v_idx
++) {
4767 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4768 GFP_KERNEL
, adapter
->node
);
4770 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4775 q_vector
->adapter
= adapter
;
4776 q_vector
->v_idx
= v_idx
;
4778 /* Allocate the affinity_hint cpumask, configure the mask */
4779 if (!alloc_cpumask_var(&q_vector
->affinity_mask
, GFP_KERNEL
))
4781 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
4782 netif_napi_add(adapter
->netdev
, &q_vector
->napi
,
4784 adapter
->q_vector
[v_idx
] = q_vector
;
4792 q_vector
= adapter
->q_vector
[v_idx
];
4793 netif_napi_del(&q_vector
->napi
);
4794 free_cpumask_var(q_vector
->affinity_mask
);
4796 adapter
->q_vector
[v_idx
] = NULL
;
4802 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4803 * @adapter: board private structure to initialize
4805 * This function frees the memory allocated to the q_vectors. In addition if
4806 * NAPI is enabled it will delete any references to the NAPI struct prior
4807 * to freeing the q_vector.
4809 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4811 int v_idx
, num_q_vectors
;
4813 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4814 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4818 for (v_idx
= 0; v_idx
< num_q_vectors
; v_idx
++) {
4819 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[v_idx
];
4820 adapter
->q_vector
[v_idx
] = NULL
;
4821 netif_napi_del(&q_vector
->napi
);
4822 free_cpumask_var(q_vector
->affinity_mask
);
4827 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4829 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4830 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4831 pci_disable_msix(adapter
->pdev
);
4832 kfree(adapter
->msix_entries
);
4833 adapter
->msix_entries
= NULL
;
4834 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4835 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4836 pci_disable_msi(adapter
->pdev
);
4841 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4842 * @adapter: board private structure to initialize
4844 * We determine which interrupt scheme to use based on...
4845 * - Kernel support (MSI, MSI-X)
4846 * - which can be user-defined (via MODULE_PARAM)
4847 * - Hardware queue count (num_*_queues)
4848 * - defined by miscellaneous hardware support/features (RSS, etc.)
4850 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4854 /* Number of supported queues */
4855 err
= ixgbe_set_num_queues(adapter
);
4859 err
= ixgbe_set_interrupt_capability(adapter
);
4861 e_dev_err("Unable to setup interrupt capabilities\n");
4862 goto err_set_interrupt
;
4865 err
= ixgbe_alloc_q_vectors(adapter
);
4867 e_dev_err("Unable to allocate memory for queue vectors\n");
4868 goto err_alloc_q_vectors
;
4871 err
= ixgbe_alloc_queues(adapter
);
4873 e_dev_err("Unable to allocate memory for queues\n");
4874 goto err_alloc_queues
;
4877 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4878 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
4879 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4881 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4886 ixgbe_free_q_vectors(adapter
);
4887 err_alloc_q_vectors
:
4888 ixgbe_reset_interrupt_capability(adapter
);
4894 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4895 * @adapter: board private structure to clear interrupt scheme on
4897 * We go through and clear interrupt specific resources and reset the structure
4898 * to pre-load conditions
4900 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4904 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4905 kfree(adapter
->tx_ring
[i
]);
4906 adapter
->tx_ring
[i
] = NULL
;
4908 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4909 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4911 /* ixgbe_get_stats64() might access this ring, we must wait
4912 * a grace period before freeing it.
4914 kfree_rcu(ring
, rcu
);
4915 adapter
->rx_ring
[i
] = NULL
;
4918 adapter
->num_tx_queues
= 0;
4919 adapter
->num_rx_queues
= 0;
4921 ixgbe_free_q_vectors(adapter
);
4922 ixgbe_reset_interrupt_capability(adapter
);
4926 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4927 * @adapter: board private structure to initialize
4929 * ixgbe_sw_init initializes the Adapter private data structure.
4930 * Fields are initialized based on PCI device information and
4931 * OS network device settings (MTU size).
4933 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4935 struct ixgbe_hw
*hw
= &adapter
->hw
;
4936 struct pci_dev
*pdev
= adapter
->pdev
;
4938 #ifdef CONFIG_IXGBE_DCB
4940 struct tc_configuration
*tc
;
4943 /* PCI config space info */
4945 hw
->vendor_id
= pdev
->vendor
;
4946 hw
->device_id
= pdev
->device
;
4947 hw
->revision_id
= pdev
->revision
;
4948 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4949 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4951 /* Set capability flags */
4952 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4953 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4954 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4955 switch (hw
->mac
.type
) {
4956 case ixgbe_mac_82598EB
:
4957 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4958 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4959 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4961 case ixgbe_mac_X540
:
4962 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
4963 case ixgbe_mac_82599EB
:
4964 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4965 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4966 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4967 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
4968 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
4969 /* Flow Director hash filters enabled */
4970 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4971 adapter
->atr_sample_rate
= 20;
4972 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4973 IXGBE_MAX_FDIR_INDICES
;
4974 adapter
->fdir_pballoc
= IXGBE_FDIR_PBALLOC_64K
;
4976 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4977 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4978 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4979 #ifdef CONFIG_IXGBE_DCB
4980 /* Default traffic class to use for FCoE */
4981 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
4983 #endif /* IXGBE_FCOE */
4989 /* n-tuple support exists, always init our spinlock */
4990 spin_lock_init(&adapter
->fdir_perfect_lock
);
4992 #ifdef CONFIG_IXGBE_DCB
4993 switch (hw
->mac
.type
) {
4994 case ixgbe_mac_X540
:
4995 adapter
->dcb_cfg
.num_tcs
.pg_tcs
= X540_TRAFFIC_CLASS
;
4996 adapter
->dcb_cfg
.num_tcs
.pfc_tcs
= X540_TRAFFIC_CLASS
;
4999 adapter
->dcb_cfg
.num_tcs
.pg_tcs
= MAX_TRAFFIC_CLASS
;
5000 adapter
->dcb_cfg
.num_tcs
.pfc_tcs
= MAX_TRAFFIC_CLASS
;
5004 /* Configure DCB traffic classes */
5005 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
5006 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
5007 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
5008 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5009 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
5010 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5011 tc
->dcb_pfc
= pfc_disabled
;
5014 /* Initialize default user to priority mapping, UPx->TC0 */
5015 tc
= &adapter
->dcb_cfg
.tc_config
[0];
5016 tc
->path
[DCB_TX_CONFIG
].up_to_tc_bitmap
= 0xFF;
5017 tc
->path
[DCB_RX_CONFIG
].up_to_tc_bitmap
= 0xFF;
5019 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
5020 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
5021 adapter
->dcb_cfg
.pfc_mode_enable
= false;
5022 adapter
->dcb_set_bitmap
= 0x00;
5023 adapter
->dcbx_cap
= DCB_CAP_DCBX_HOST
| DCB_CAP_DCBX_VER_CEE
;
5024 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
5029 /* default flow control settings */
5030 hw
->fc
.requested_mode
= ixgbe_fc_full
;
5031 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
5033 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
5035 ixgbe_pbthresh_setup(adapter
);
5036 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
5037 hw
->fc
.send_xon
= true;
5038 hw
->fc
.disable_fc_autoneg
= false;
5040 /* enable itr by default in dynamic mode */
5041 adapter
->rx_itr_setting
= 1;
5042 adapter
->tx_itr_setting
= 1;
5044 /* set defaults for eitr in MegaBytes */
5045 adapter
->eitr_low
= 10;
5046 adapter
->eitr_high
= 20;
5048 /* set default ring sizes */
5049 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
5050 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
5052 /* set default work limits */
5053 adapter
->tx_work_limit
= IXGBE_DEFAULT_TX_WORK
;
5055 /* initialize eeprom parameters */
5056 if (ixgbe_init_eeprom_params_generic(hw
)) {
5057 e_dev_err("EEPROM initialization failed\n");
5061 /* enable rx csum by default */
5062 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
5064 /* get assigned NUMA node */
5065 adapter
->node
= dev_to_node(&pdev
->dev
);
5067 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5073 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5074 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5076 * Return 0 on success, negative on failure
5078 int ixgbe_setup_tx_resources(struct ixgbe_ring
*tx_ring
)
5080 struct device
*dev
= tx_ring
->dev
;
5083 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
5084 tx_ring
->tx_buffer_info
= vzalloc_node(size
, tx_ring
->numa_node
);
5085 if (!tx_ring
->tx_buffer_info
)
5086 tx_ring
->tx_buffer_info
= vzalloc(size
);
5087 if (!tx_ring
->tx_buffer_info
)
5090 /* round up to nearest 4K */
5091 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
5092 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
5094 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
5095 &tx_ring
->dma
, GFP_KERNEL
);
5099 tx_ring
->next_to_use
= 0;
5100 tx_ring
->next_to_clean
= 0;
5104 vfree(tx_ring
->tx_buffer_info
);
5105 tx_ring
->tx_buffer_info
= NULL
;
5106 dev_err(dev
, "Unable to allocate memory for the Tx descriptor ring\n");
5111 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5112 * @adapter: board private structure
5114 * If this function returns with an error, then it's possible one or
5115 * more of the rings is populated (while the rest are not). It is the
5116 * callers duty to clean those orphaned rings.
5118 * Return 0 on success, negative on failure
5120 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5124 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5125 err
= ixgbe_setup_tx_resources(adapter
->tx_ring
[i
]);
5128 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5136 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5137 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5139 * Returns 0 on success, negative on failure
5141 int ixgbe_setup_rx_resources(struct ixgbe_ring
*rx_ring
)
5143 struct device
*dev
= rx_ring
->dev
;
5146 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5147 rx_ring
->rx_buffer_info
= vzalloc_node(size
, rx_ring
->numa_node
);
5148 if (!rx_ring
->rx_buffer_info
)
5149 rx_ring
->rx_buffer_info
= vzalloc(size
);
5150 if (!rx_ring
->rx_buffer_info
)
5153 /* Round up to nearest 4K */
5154 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5155 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5157 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
5158 &rx_ring
->dma
, GFP_KERNEL
);
5163 rx_ring
->next_to_clean
= 0;
5164 rx_ring
->next_to_use
= 0;
5168 vfree(rx_ring
->rx_buffer_info
);
5169 rx_ring
->rx_buffer_info
= NULL
;
5170 dev_err(dev
, "Unable to allocate memory for the Rx descriptor ring\n");
5175 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5176 * @adapter: board private structure
5178 * If this function returns with an error, then it's possible one or
5179 * more of the rings is populated (while the rest are not). It is the
5180 * callers duty to clean those orphaned rings.
5182 * Return 0 on success, negative on failure
5184 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5188 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5189 err
= ixgbe_setup_rx_resources(adapter
->rx_ring
[i
]);
5192 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5200 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5201 * @tx_ring: Tx descriptor ring for a specific queue
5203 * Free all transmit software resources
5205 void ixgbe_free_tx_resources(struct ixgbe_ring
*tx_ring
)
5207 ixgbe_clean_tx_ring(tx_ring
);
5209 vfree(tx_ring
->tx_buffer_info
);
5210 tx_ring
->tx_buffer_info
= NULL
;
5212 /* if not set, then don't free */
5216 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
5217 tx_ring
->desc
, tx_ring
->dma
);
5219 tx_ring
->desc
= NULL
;
5223 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5224 * @adapter: board private structure
5226 * Free all transmit software resources
5228 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5232 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5233 if (adapter
->tx_ring
[i
]->desc
)
5234 ixgbe_free_tx_resources(adapter
->tx_ring
[i
]);
5238 * ixgbe_free_rx_resources - Free Rx Resources
5239 * @rx_ring: ring to clean the resources from
5241 * Free all receive software resources
5243 void ixgbe_free_rx_resources(struct ixgbe_ring
*rx_ring
)
5245 ixgbe_clean_rx_ring(rx_ring
);
5247 vfree(rx_ring
->rx_buffer_info
);
5248 rx_ring
->rx_buffer_info
= NULL
;
5250 /* if not set, then don't free */
5254 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
5255 rx_ring
->desc
, rx_ring
->dma
);
5257 rx_ring
->desc
= NULL
;
5261 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5262 * @adapter: board private structure
5264 * Free all receive software resources
5266 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5270 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5271 if (adapter
->rx_ring
[i
]->desc
)
5272 ixgbe_free_rx_resources(adapter
->rx_ring
[i
]);
5276 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5277 * @netdev: network interface device structure
5278 * @new_mtu: new value for maximum frame size
5280 * Returns 0 on success, negative on failure
5282 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5284 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5285 struct ixgbe_hw
*hw
= &adapter
->hw
;
5286 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5288 /* MTU < 68 is an error and causes problems on some kernels */
5289 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
&&
5290 hw
->mac
.type
!= ixgbe_mac_X540
) {
5291 if ((new_mtu
< 68) || (max_frame
> MAXIMUM_ETHERNET_VLAN_SIZE
))
5294 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5298 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5299 /* must set new MTU before calling down or up */
5300 netdev
->mtu
= new_mtu
;
5302 if (netif_running(netdev
))
5303 ixgbe_reinit_locked(adapter
);
5309 * ixgbe_open - Called when a network interface is made active
5310 * @netdev: network interface device structure
5312 * Returns 0 on success, negative value on failure
5314 * The open entry point is called when a network interface is made
5315 * active by the system (IFF_UP). At this point all resources needed
5316 * for transmit and receive operations are allocated, the interrupt
5317 * handler is registered with the OS, the watchdog timer is started,
5318 * and the stack is notified that the interface is ready.
5320 static int ixgbe_open(struct net_device
*netdev
)
5322 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5325 /* disallow open during test */
5326 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5329 netif_carrier_off(netdev
);
5331 /* allocate transmit descriptors */
5332 err
= ixgbe_setup_all_tx_resources(adapter
);
5336 /* allocate receive descriptors */
5337 err
= ixgbe_setup_all_rx_resources(adapter
);
5341 ixgbe_configure(adapter
);
5343 err
= ixgbe_request_irq(adapter
);
5347 ixgbe_up_complete(adapter
);
5353 ixgbe_free_all_rx_resources(adapter
);
5355 ixgbe_free_all_tx_resources(adapter
);
5356 ixgbe_reset(adapter
);
5362 * ixgbe_close - Disables a network interface
5363 * @netdev: network interface device structure
5365 * Returns 0, this is not allowed to fail
5367 * The close entry point is called when an interface is de-activated
5368 * by the OS. The hardware is still under the drivers control, but
5369 * needs to be disabled. A global MAC reset is issued to stop the
5370 * hardware, and all transmit and receive resources are freed.
5372 static int ixgbe_close(struct net_device
*netdev
)
5374 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5376 ixgbe_down(adapter
);
5377 ixgbe_free_irq(adapter
);
5379 ixgbe_fdir_filter_exit(adapter
);
5381 ixgbe_free_all_tx_resources(adapter
);
5382 ixgbe_free_all_rx_resources(adapter
);
5384 ixgbe_release_hw_control(adapter
);
5390 static int ixgbe_resume(struct pci_dev
*pdev
)
5392 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5393 struct net_device
*netdev
= adapter
->netdev
;
5396 pci_set_power_state(pdev
, PCI_D0
);
5397 pci_restore_state(pdev
);
5399 * pci_restore_state clears dev->state_saved so call
5400 * pci_save_state to restore it.
5402 pci_save_state(pdev
);
5404 err
= pci_enable_device_mem(pdev
);
5406 e_dev_err("Cannot enable PCI device from suspend\n");
5409 pci_set_master(pdev
);
5411 pci_wake_from_d3(pdev
, false);
5413 err
= ixgbe_init_interrupt_scheme(adapter
);
5415 e_dev_err("Cannot initialize interrupts for device\n");
5419 ixgbe_reset(adapter
);
5421 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5423 if (netif_running(netdev
)) {
5424 err
= ixgbe_open(netdev
);
5429 netif_device_attach(netdev
);
5433 #endif /* CONFIG_PM */
5435 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5437 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5438 struct net_device
*netdev
= adapter
->netdev
;
5439 struct ixgbe_hw
*hw
= &adapter
->hw
;
5441 u32 wufc
= adapter
->wol
;
5446 netif_device_detach(netdev
);
5448 if (netif_running(netdev
)) {
5449 ixgbe_down(adapter
);
5450 ixgbe_free_irq(adapter
);
5451 ixgbe_free_all_tx_resources(adapter
);
5452 ixgbe_free_all_rx_resources(adapter
);
5455 ixgbe_clear_interrupt_scheme(adapter
);
5457 kfree(adapter
->ixgbe_ieee_pfc
);
5458 kfree(adapter
->ixgbe_ieee_ets
);
5462 retval
= pci_save_state(pdev
);
5468 ixgbe_set_rx_mode(netdev
);
5470 /* turn on all-multi mode if wake on multicast is enabled */
5471 if (wufc
& IXGBE_WUFC_MC
) {
5472 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5473 fctrl
|= IXGBE_FCTRL_MPE
;
5474 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5477 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5478 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5479 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5481 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5483 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5484 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5487 switch (hw
->mac
.type
) {
5488 case ixgbe_mac_82598EB
:
5489 pci_wake_from_d3(pdev
, false);
5491 case ixgbe_mac_82599EB
:
5492 case ixgbe_mac_X540
:
5493 pci_wake_from_d3(pdev
, !!wufc
);
5499 *enable_wake
= !!wufc
;
5501 ixgbe_release_hw_control(adapter
);
5503 pci_disable_device(pdev
);
5509 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5514 retval
= __ixgbe_shutdown(pdev
, &wake
);
5519 pci_prepare_to_sleep(pdev
);
5521 pci_wake_from_d3(pdev
, false);
5522 pci_set_power_state(pdev
, PCI_D3hot
);
5527 #endif /* CONFIG_PM */
5529 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5533 __ixgbe_shutdown(pdev
, &wake
);
5535 if (system_state
== SYSTEM_POWER_OFF
) {
5536 pci_wake_from_d3(pdev
, wake
);
5537 pci_set_power_state(pdev
, PCI_D3hot
);
5542 * ixgbe_update_stats - Update the board statistics counters.
5543 * @adapter: board private structure
5545 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5547 struct net_device
*netdev
= adapter
->netdev
;
5548 struct ixgbe_hw
*hw
= &adapter
->hw
;
5549 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5551 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5552 u64 non_eop_descs
= 0, restart_queue
= 0, tx_busy
= 0;
5553 u64 alloc_rx_page_failed
= 0, alloc_rx_buff_failed
= 0;
5554 u64 bytes
= 0, packets
= 0;
5556 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
5558 u64 fcoe_noddp_counts_sum
= 0, fcoe_noddp_ext_buff_counts_sum
= 0;
5559 #endif /* IXGBE_FCOE */
5561 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5562 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5565 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5568 for (i
= 0; i
< 16; i
++)
5569 adapter
->hw_rx_no_dma_resources
+=
5570 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5571 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5572 rsc_count
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_count
;
5573 rsc_flush
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_flush
;
5575 adapter
->rsc_total_count
= rsc_count
;
5576 adapter
->rsc_total_flush
= rsc_flush
;
5579 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5580 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[i
];
5581 non_eop_descs
+= rx_ring
->rx_stats
.non_eop_descs
;
5582 alloc_rx_page_failed
+= rx_ring
->rx_stats
.alloc_rx_page_failed
;
5583 alloc_rx_buff_failed
+= rx_ring
->rx_stats
.alloc_rx_buff_failed
;
5584 bytes
+= rx_ring
->stats
.bytes
;
5585 packets
+= rx_ring
->stats
.packets
;
5587 adapter
->non_eop_descs
= non_eop_descs
;
5588 adapter
->alloc_rx_page_failed
= alloc_rx_page_failed
;
5589 adapter
->alloc_rx_buff_failed
= alloc_rx_buff_failed
;
5590 netdev
->stats
.rx_bytes
= bytes
;
5591 netdev
->stats
.rx_packets
= packets
;
5595 /* gather some stats to the adapter struct that are per queue */
5596 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5597 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5598 restart_queue
+= tx_ring
->tx_stats
.restart_queue
;
5599 tx_busy
+= tx_ring
->tx_stats
.tx_busy
;
5600 bytes
+= tx_ring
->stats
.bytes
;
5601 packets
+= tx_ring
->stats
.packets
;
5603 adapter
->restart_queue
= restart_queue
;
5604 adapter
->tx_busy
= tx_busy
;
5605 netdev
->stats
.tx_bytes
= bytes
;
5606 netdev
->stats
.tx_packets
= packets
;
5608 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5610 /* 8 register reads */
5611 for (i
= 0; i
< 8; i
++) {
5612 /* for packet buffers not used, the register should read 0 */
5613 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5615 hwstats
->mpc
[i
] += mpc
;
5616 total_mpc
+= hwstats
->mpc
[i
];
5617 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5618 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5619 switch (hw
->mac
.type
) {
5620 case ixgbe_mac_82598EB
:
5621 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5622 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5623 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5624 hwstats
->pxonrxc
[i
] +=
5625 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5627 case ixgbe_mac_82599EB
:
5628 case ixgbe_mac_X540
:
5629 hwstats
->pxonrxc
[i
] +=
5630 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5637 /*16 register reads */
5638 for (i
= 0; i
< 16; i
++) {
5639 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5640 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5641 if ((hw
->mac
.type
== ixgbe_mac_82599EB
) ||
5642 (hw
->mac
.type
== ixgbe_mac_X540
)) {
5643 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC_L(i
));
5644 IXGBE_READ_REG(hw
, IXGBE_QBTC_H(i
)); /* to clear */
5645 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC_L(i
));
5646 IXGBE_READ_REG(hw
, IXGBE_QBRC_H(i
)); /* to clear */
5650 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5651 /* work around hardware counting issue */
5652 hwstats
->gprc
-= missed_rx
;
5654 ixgbe_update_xoff_received(adapter
);
5656 /* 82598 hardware only has a 32 bit counter in the high register */
5657 switch (hw
->mac
.type
) {
5658 case ixgbe_mac_82598EB
:
5659 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5660 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5661 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5662 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5664 case ixgbe_mac_X540
:
5665 /* OS2BMC stats are X540 only*/
5666 hwstats
->o2bgptc
+= IXGBE_READ_REG(hw
, IXGBE_O2BGPTC
);
5667 hwstats
->o2bspc
+= IXGBE_READ_REG(hw
, IXGBE_O2BSPC
);
5668 hwstats
->b2ospc
+= IXGBE_READ_REG(hw
, IXGBE_B2OSPC
);
5669 hwstats
->b2ogprc
+= IXGBE_READ_REG(hw
, IXGBE_B2OGPRC
);
5670 case ixgbe_mac_82599EB
:
5671 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5672 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
5673 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5674 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
5675 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5676 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5677 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5678 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5679 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5681 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5682 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5683 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5684 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5685 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5686 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5687 /* Add up per cpu counters for total ddp aloc fail */
5688 if (fcoe
->pcpu_noddp
&& fcoe
->pcpu_noddp_ext_buff
) {
5689 for_each_possible_cpu(cpu
) {
5690 fcoe_noddp_counts_sum
+=
5691 *per_cpu_ptr(fcoe
->pcpu_noddp
, cpu
);
5692 fcoe_noddp_ext_buff_counts_sum
+=
5694 pcpu_noddp_ext_buff
, cpu
);
5697 hwstats
->fcoe_noddp
= fcoe_noddp_counts_sum
;
5698 hwstats
->fcoe_noddp_ext_buff
= fcoe_noddp_ext_buff_counts_sum
;
5699 #endif /* IXGBE_FCOE */
5704 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5705 hwstats
->bprc
+= bprc
;
5706 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5707 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5708 hwstats
->mprc
-= bprc
;
5709 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5710 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5711 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5712 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5713 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5714 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5715 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5716 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5717 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5718 hwstats
->lxontxc
+= lxon
;
5719 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5720 hwstats
->lxofftxc
+= lxoff
;
5721 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5722 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5724 * 82598 errata - tx of flow control packets is included in tx counters
5726 xon_off_tot
= lxon
+ lxoff
;
5727 hwstats
->gptc
-= xon_off_tot
;
5728 hwstats
->mptc
-= xon_off_tot
;
5729 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5730 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5731 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5732 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5733 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5734 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5735 hwstats
->ptc64
-= xon_off_tot
;
5736 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5737 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5738 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5739 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5740 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5741 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5743 /* Fill out the OS statistics structure */
5744 netdev
->stats
.multicast
= hwstats
->mprc
;
5747 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5748 netdev
->stats
.rx_dropped
= 0;
5749 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5750 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5751 netdev
->stats
.rx_missed_errors
= total_mpc
;
5755 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5756 * @adapter - pointer to the device adapter structure
5758 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter
*adapter
)
5760 struct ixgbe_hw
*hw
= &adapter
->hw
;
5763 if (!(adapter
->flags2
& IXGBE_FLAG2_FDIR_REQUIRES_REINIT
))
5766 adapter
->flags2
&= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
5768 /* if interface is down do nothing */
5769 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5772 /* do nothing if we are not using signature filters */
5773 if (!(adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
))
5776 adapter
->fdir_overflow
++;
5778 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5779 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5780 set_bit(__IXGBE_TX_FDIR_INIT_DONE
,
5781 &(adapter
->tx_ring
[i
]->state
));
5782 /* re-enable flow director interrupts */
5783 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_FLOW_DIR
);
5785 e_err(probe
, "failed to finish FDIR re-initialization, "
5786 "ignored adding FDIR ATR filters\n");
5791 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5792 * @adapter - pointer to the device adapter structure
5794 * This function serves two purposes. First it strobes the interrupt lines
5795 * in order to make certain interrupts are occurring. Secondly it sets the
5796 * bits needed to check for TX hangs. As a result we should immediately
5797 * determine if a hang has occurred.
5799 static void ixgbe_check_hang_subtask(struct ixgbe_adapter
*adapter
)
5801 struct ixgbe_hw
*hw
= &adapter
->hw
;
5805 /* If we're down or resetting, just bail */
5806 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5807 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5810 /* Force detection of hung controller */
5811 if (netif_carrier_ok(adapter
->netdev
)) {
5812 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5813 set_check_for_tx_hang(adapter
->tx_ring
[i
]);
5816 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5818 * for legacy and MSI interrupts don't set any bits
5819 * that are enabled for EIAM, because this operation
5820 * would set *both* EIMS and EICS for any bit in EIAM
5822 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5823 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5825 /* get one bit for every active tx/rx interrupt vector */
5826 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5827 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5828 if (qv
->rx
.ring
|| qv
->tx
.ring
)
5829 eics
|= ((u64
)1 << i
);
5833 /* Cause software interrupt to ensure rings are cleaned */
5834 ixgbe_irq_rearm_queues(adapter
, eics
);
5839 * ixgbe_watchdog_update_link - update the link status
5840 * @adapter - pointer to the device adapter structure
5841 * @link_speed - pointer to a u32 to store the link_speed
5843 static void ixgbe_watchdog_update_link(struct ixgbe_adapter
*adapter
)
5845 struct ixgbe_hw
*hw
= &adapter
->hw
;
5846 u32 link_speed
= adapter
->link_speed
;
5847 bool link_up
= adapter
->link_up
;
5850 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
))
5853 if (hw
->mac
.ops
.check_link
) {
5854 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5856 /* always assume link is up, if no check link function */
5857 link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
5861 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5862 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5863 hw
->mac
.ops
.fc_enable(hw
, i
);
5865 hw
->mac
.ops
.fc_enable(hw
, 0);
5870 time_after(jiffies
, (adapter
->link_check_timeout
+
5871 IXGBE_TRY_LINK_TIMEOUT
))) {
5872 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5873 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5874 IXGBE_WRITE_FLUSH(hw
);
5877 adapter
->link_up
= link_up
;
5878 adapter
->link_speed
= link_speed
;
5882 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5883 * print link up message
5884 * @adapter - pointer to the device adapter structure
5886 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter
*adapter
)
5888 struct net_device
*netdev
= adapter
->netdev
;
5889 struct ixgbe_hw
*hw
= &adapter
->hw
;
5890 u32 link_speed
= adapter
->link_speed
;
5891 bool flow_rx
, flow_tx
;
5893 /* only continue if link was previously down */
5894 if (netif_carrier_ok(netdev
))
5897 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
5899 switch (hw
->mac
.type
) {
5900 case ixgbe_mac_82598EB
: {
5901 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5902 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5903 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5904 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5907 case ixgbe_mac_X540
:
5908 case ixgbe_mac_82599EB
: {
5909 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5910 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5911 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5912 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5920 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
5921 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5923 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5925 (link_speed
== IXGBE_LINK_SPEED_100_FULL
?
5928 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5930 (flow_tx
? "TX" : "None"))));
5932 netif_carrier_on(netdev
);
5933 ixgbe_check_vf_rate_limit(adapter
);
5937 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5938 * print link down message
5939 * @adapter - pointer to the adapter structure
5941 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter
* adapter
)
5943 struct net_device
*netdev
= adapter
->netdev
;
5944 struct ixgbe_hw
*hw
= &adapter
->hw
;
5946 adapter
->link_up
= false;
5947 adapter
->link_speed
= 0;
5949 /* only continue if link was up previously */
5950 if (!netif_carrier_ok(netdev
))
5953 /* poll for SFP+ cable when link is down */
5954 if (ixgbe_is_sfp(hw
) && hw
->mac
.type
== ixgbe_mac_82598EB
)
5955 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
5957 e_info(drv
, "NIC Link is Down\n");
5958 netif_carrier_off(netdev
);
5962 * ixgbe_watchdog_flush_tx - flush queues on link down
5963 * @adapter - pointer to the device adapter structure
5965 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter
*adapter
)
5968 int some_tx_pending
= 0;
5970 if (!netif_carrier_ok(adapter
->netdev
)) {
5971 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5972 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5973 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5974 some_tx_pending
= 1;
5979 if (some_tx_pending
) {
5980 /* We've lost link, so the controller stops DMA,
5981 * but we've got queued Tx work that's never going
5982 * to get done, so reset controller to flush Tx.
5983 * (Do the reset outside of interrupt context).
5985 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
5990 static void ixgbe_spoof_check(struct ixgbe_adapter
*adapter
)
5994 /* Do not perform spoof check for 82598 */
5995 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
5998 ssvpc
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SSVPC
);
6001 * ssvpc register is cleared on read, if zero then no
6002 * spoofed packets in the last interval.
6007 e_warn(drv
, "%d Spoofed packets detected\n", ssvpc
);
6011 * ixgbe_watchdog_subtask - check and bring link up
6012 * @adapter - pointer to the device adapter structure
6014 static void ixgbe_watchdog_subtask(struct ixgbe_adapter
*adapter
)
6016 /* if interface is down do nothing */
6017 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
6018 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
6021 ixgbe_watchdog_update_link(adapter
);
6023 if (adapter
->link_up
)
6024 ixgbe_watchdog_link_is_up(adapter
);
6026 ixgbe_watchdog_link_is_down(adapter
);
6028 ixgbe_spoof_check(adapter
);
6029 ixgbe_update_stats(adapter
);
6031 ixgbe_watchdog_flush_tx(adapter
);
6035 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6036 * @adapter - the ixgbe adapter structure
6038 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter
*adapter
)
6040 struct ixgbe_hw
*hw
= &adapter
->hw
;
6043 /* not searching for SFP so there is nothing to do here */
6044 if (!(adapter
->flags2
& IXGBE_FLAG2_SEARCH_FOR_SFP
) &&
6045 !(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6048 /* someone else is in init, wait until next service event */
6049 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6052 err
= hw
->phy
.ops
.identify_sfp(hw
);
6053 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6056 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
) {
6057 /* If no cable is present, then we need to reset
6058 * the next time we find a good cable. */
6059 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
6066 /* exit if reset not needed */
6067 if (!(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6070 adapter
->flags2
&= ~IXGBE_FLAG2_SFP_NEEDS_RESET
;
6073 * A module may be identified correctly, but the EEPROM may not have
6074 * support for that module. setup_sfp() will fail in that case, so
6075 * we should not allow that module to load.
6077 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
6078 err
= hw
->phy
.ops
.reset(hw
);
6080 err
= hw
->mac
.ops
.setup_sfp(hw
);
6082 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6085 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
6086 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
6089 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6091 if ((err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) &&
6092 (adapter
->netdev
->reg_state
== NETREG_REGISTERED
)) {
6093 e_dev_err("failed to initialize because an unsupported "
6094 "SFP+ module type was detected.\n");
6095 e_dev_err("Reload the driver after installing a "
6096 "supported module.\n");
6097 unregister_netdev(adapter
->netdev
);
6102 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6103 * @adapter - the ixgbe adapter structure
6105 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter
*adapter
)
6107 struct ixgbe_hw
*hw
= &adapter
->hw
;
6111 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_CONFIG
))
6114 /* someone else is in init, wait until next service event */
6115 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6118 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
6120 autoneg
= hw
->phy
.autoneg_advertised
;
6121 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
6122 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
6123 if (hw
->mac
.ops
.setup_link
)
6124 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
6126 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
6127 adapter
->link_check_timeout
= jiffies
;
6128 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6131 #ifdef CONFIG_PCI_IOV
6132 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter
*adapter
)
6135 struct ixgbe_hw
*hw
= &adapter
->hw
;
6136 struct net_device
*netdev
= adapter
->netdev
;
6140 gpc
= IXGBE_READ_REG(hw
, IXGBE_TXDGPC
);
6141 if (gpc
) /* If incrementing then no need for the check below */
6144 * Check to see if a bad DMA write target from an errant or
6145 * malicious VF has caused a PCIe error. If so then we can
6146 * issue a VFLR to the offending VF(s) and then resume without
6147 * requesting a full slot reset.
6150 for (vf
= 0; vf
< adapter
->num_vfs
; vf
++) {
6151 ciaa
= (vf
<< 16) | 0x80000000;
6152 /* 32 bit read so align, we really want status at offset 6 */
6153 ciaa
|= PCI_COMMAND
;
6154 IXGBE_WRITE_REG(hw
, IXGBE_CIAA_82599
, ciaa
);
6155 ciad
= IXGBE_READ_REG(hw
, IXGBE_CIAD_82599
);
6157 /* disable debug mode asap after reading data */
6158 IXGBE_WRITE_REG(hw
, IXGBE_CIAA_82599
, ciaa
);
6159 /* Get the upper 16 bits which will be the PCI status reg */
6161 if (ciad
& PCI_STATUS_REC_MASTER_ABORT
) {
6162 netdev_err(netdev
, "VF %d Hung DMA\n", vf
);
6164 ciaa
= (vf
<< 16) | 0x80000000;
6166 IXGBE_WRITE_REG(hw
, IXGBE_CIAA_82599
, ciaa
);
6167 ciad
= 0x00008000; /* VFLR */
6168 IXGBE_WRITE_REG(hw
, IXGBE_CIAD_82599
, ciad
);
6170 IXGBE_WRITE_REG(hw
, IXGBE_CIAA_82599
, ciaa
);
6177 * ixgbe_service_timer - Timer Call-back
6178 * @data: pointer to adapter cast into an unsigned long
6180 static void ixgbe_service_timer(unsigned long data
)
6182 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
6183 unsigned long next_event_offset
;
6186 #ifdef CONFIG_PCI_IOV
6190 * don't bother with SR-IOV VF DMA hang check if there are
6191 * no VFs or the link is down
6193 if (!adapter
->num_vfs
||
6194 (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
)) {
6196 goto normal_timer_service
;
6199 /* If we have VFs allocated then we must check for DMA hangs */
6200 ixgbe_check_for_bad_vf(adapter
);
6201 next_event_offset
= HZ
/ 50;
6202 adapter
->timer_event_accumulator
++;
6204 if (adapter
->timer_event_accumulator
>= 100) {
6206 adapter
->timer_event_accumulator
= 0;
6209 goto schedule_event
;
6211 normal_timer_service
:
6213 /* poll faster when waiting for link */
6214 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
)
6215 next_event_offset
= HZ
/ 10;
6217 next_event_offset
= HZ
* 2;
6219 #ifdef CONFIG_PCI_IOV
6222 /* Reset the timer */
6223 mod_timer(&adapter
->service_timer
, next_event_offset
+ jiffies
);
6226 ixgbe_service_event_schedule(adapter
);
6229 static void ixgbe_reset_subtask(struct ixgbe_adapter
*adapter
)
6231 if (!(adapter
->flags2
& IXGBE_FLAG2_RESET_REQUESTED
))
6234 adapter
->flags2
&= ~IXGBE_FLAG2_RESET_REQUESTED
;
6236 /* If we're already down or resetting, just bail */
6237 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
6238 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
6241 ixgbe_dump(adapter
);
6242 netdev_err(adapter
->netdev
, "Reset adapter\n");
6243 adapter
->tx_timeout_count
++;
6245 ixgbe_reinit_locked(adapter
);
6249 * ixgbe_service_task - manages and runs subtasks
6250 * @work: pointer to work_struct containing our data
6252 static void ixgbe_service_task(struct work_struct
*work
)
6254 struct ixgbe_adapter
*adapter
= container_of(work
,
6255 struct ixgbe_adapter
,
6258 ixgbe_reset_subtask(adapter
);
6259 ixgbe_sfp_detection_subtask(adapter
);
6260 ixgbe_sfp_link_config_subtask(adapter
);
6261 ixgbe_check_overtemp_subtask(adapter
);
6262 ixgbe_watchdog_subtask(adapter
);
6263 ixgbe_fdir_reinit_subtask(adapter
);
6264 ixgbe_check_hang_subtask(adapter
);
6266 ixgbe_service_event_complete(adapter
);
6269 void ixgbe_tx_ctxtdesc(struct ixgbe_ring
*tx_ring
, u32 vlan_macip_lens
,
6270 u32 fcoe_sof_eof
, u32 type_tucmd
, u32 mss_l4len_idx
)
6272 struct ixgbe_adv_tx_context_desc
*context_desc
;
6273 u16 i
= tx_ring
->next_to_use
;
6275 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6278 tx_ring
->next_to_use
= (i
< tx_ring
->count
) ? i
: 0;
6280 /* set bits to identify this as an advanced context descriptor */
6281 type_tucmd
|= IXGBE_TXD_CMD_DEXT
| IXGBE_ADVTXD_DTYP_CTXT
;
6283 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6284 context_desc
->seqnum_seed
= cpu_to_le32(fcoe_sof_eof
);
6285 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd
);
6286 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
6289 static int ixgbe_tso(struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
6290 u32 tx_flags
, __be16 protocol
, u8
*hdr_len
)
6293 u32 vlan_macip_lens
, type_tucmd
;
6294 u32 mss_l4len_idx
, l4len
;
6296 if (!skb_is_gso(skb
))
6299 if (skb_header_cloned(skb
)) {
6300 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
6305 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6306 type_tucmd
= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6308 if (protocol
== __constant_htons(ETH_P_IP
)) {
6309 struct iphdr
*iph
= ip_hdr(skb
);
6312 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6316 type_tucmd
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6317 } else if (skb_is_gso_v6(skb
)) {
6318 ipv6_hdr(skb
)->payload_len
= 0;
6319 tcp_hdr(skb
)->check
=
6320 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
6321 &ipv6_hdr(skb
)->daddr
,
6325 l4len
= tcp_hdrlen(skb
);
6326 *hdr_len
= skb_transport_offset(skb
) + l4len
;
6328 /* mss_l4len_id: use 1 as index for TSO */
6329 mss_l4len_idx
= l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
;
6330 mss_l4len_idx
|= skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
;
6331 mss_l4len_idx
|= 1 << IXGBE_ADVTXD_IDX_SHIFT
;
6333 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6334 vlan_macip_lens
= skb_network_header_len(skb
);
6335 vlan_macip_lens
|= skb_network_offset(skb
) << IXGBE_ADVTXD_MACLEN_SHIFT
;
6336 vlan_macip_lens
|= tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
;
6338 ixgbe_tx_ctxtdesc(tx_ring
, vlan_macip_lens
, 0, type_tucmd
,
6344 static bool ixgbe_tx_csum(struct ixgbe_ring
*tx_ring
,
6345 struct sk_buff
*skb
, u32 tx_flags
,
6348 u32 vlan_macip_lens
= 0;
6349 u32 mss_l4len_idx
= 0;
6352 if (skb
->ip_summed
!= CHECKSUM_PARTIAL
) {
6353 if (!(tx_flags
& IXGBE_TX_FLAGS_HW_VLAN
) &&
6354 !(tx_flags
& IXGBE_TX_FLAGS_TXSW
))
6359 case __constant_htons(ETH_P_IP
):
6360 vlan_macip_lens
|= skb_network_header_len(skb
);
6361 type_tucmd
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6362 l4_hdr
= ip_hdr(skb
)->protocol
;
6364 case __constant_htons(ETH_P_IPV6
):
6365 vlan_macip_lens
|= skb_network_header_len(skb
);
6366 l4_hdr
= ipv6_hdr(skb
)->nexthdr
;
6369 if (unlikely(net_ratelimit())) {
6370 dev_warn(tx_ring
->dev
,
6371 "partial checksum but proto=%x!\n",
6379 type_tucmd
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6380 mss_l4len_idx
= tcp_hdrlen(skb
) <<
6381 IXGBE_ADVTXD_L4LEN_SHIFT
;
6384 type_tucmd
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6385 mss_l4len_idx
= sizeof(struct sctphdr
) <<
6386 IXGBE_ADVTXD_L4LEN_SHIFT
;
6389 mss_l4len_idx
= sizeof(struct udphdr
) <<
6390 IXGBE_ADVTXD_L4LEN_SHIFT
;
6393 if (unlikely(net_ratelimit())) {
6394 dev_warn(tx_ring
->dev
,
6395 "partial checksum but l4 proto=%x!\n",
6402 vlan_macip_lens
|= skb_network_offset(skb
) << IXGBE_ADVTXD_MACLEN_SHIFT
;
6403 vlan_macip_lens
|= tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
;
6405 ixgbe_tx_ctxtdesc(tx_ring
, vlan_macip_lens
, 0,
6406 type_tucmd
, mss_l4len_idx
);
6408 return (skb
->ip_summed
== CHECKSUM_PARTIAL
);
6411 static __le32
ixgbe_tx_cmd_type(u32 tx_flags
)
6413 /* set type for advanced descriptor with frame checksum insertion */
6414 __le32 cmd_type
= cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA
|
6415 IXGBE_ADVTXD_DCMD_IFCS
|
6416 IXGBE_ADVTXD_DCMD_DEXT
);
6418 /* set HW vlan bit if vlan is present */
6419 if (tx_flags
& IXGBE_TX_FLAGS_HW_VLAN
)
6420 cmd_type
|= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE
);
6422 /* set segmentation enable bits for TSO/FSO */
6424 if ((tx_flags
& IXGBE_TX_FLAGS_TSO
) || (tx_flags
& IXGBE_TX_FLAGS_FSO
))
6426 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6428 cmd_type
|= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE
);
6433 static __le32
ixgbe_tx_olinfo_status(u32 tx_flags
, unsigned int paylen
)
6435 __le32 olinfo_status
=
6436 cpu_to_le32(paylen
<< IXGBE_ADVTXD_PAYLEN_SHIFT
);
6438 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6439 olinfo_status
|= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM
|
6440 (1 << IXGBE_ADVTXD_IDX_SHIFT
));
6441 /* enble IPv4 checksum for TSO */
6442 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6443 olinfo_status
|= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM
);
6446 /* enable L4 checksum for TSO and TX checksum offload */
6447 if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6448 olinfo_status
|= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM
);
6451 /* use index 1 context for FCOE/FSO */
6452 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6453 olinfo_status
|= cpu_to_le32(IXGBE_ADVTXD_CC
|
6454 (1 << IXGBE_ADVTXD_IDX_SHIFT
));
6458 * Check Context must be set if Tx switch is enabled, which it
6459 * always is for case where virtual functions are running
6461 if (tx_flags
& IXGBE_TX_FLAGS_TXSW
)
6462 olinfo_status
|= cpu_to_le32(IXGBE_ADVTXD_CC
);
6464 return olinfo_status
;
6467 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6470 static void ixgbe_tx_map(struct ixgbe_ring
*tx_ring
,
6471 struct sk_buff
*skb
,
6472 struct ixgbe_tx_buffer
*first
,
6476 struct device
*dev
= tx_ring
->dev
;
6477 struct ixgbe_tx_buffer
*tx_buffer_info
;
6478 union ixgbe_adv_tx_desc
*tx_desc
;
6480 __le32 cmd_type
, olinfo_status
;
6481 struct skb_frag_struct
*frag
;
6483 unsigned int data_len
= skb
->data_len
;
6484 unsigned int size
= skb_headlen(skb
);
6486 u32 paylen
= skb
->len
- hdr_len
;
6487 u16 i
= tx_ring
->next_to_use
;
6491 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6492 if (data_len
>= sizeof(struct fcoe_crc_eof
)) {
6493 data_len
-= sizeof(struct fcoe_crc_eof
);
6495 size
-= sizeof(struct fcoe_crc_eof
) - data_len
;
6501 dma
= dma_map_single(dev
, skb
->data
, size
, DMA_TO_DEVICE
);
6502 if (dma_mapping_error(dev
, dma
))
6505 cmd_type
= ixgbe_tx_cmd_type(tx_flags
);
6506 olinfo_status
= ixgbe_tx_olinfo_status(tx_flags
, paylen
);
6508 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6511 while (size
> IXGBE_MAX_DATA_PER_TXD
) {
6512 tx_desc
->read
.buffer_addr
= cpu_to_le64(dma
+ offset
);
6513 tx_desc
->read
.cmd_type_len
=
6514 cmd_type
| cpu_to_le32(IXGBE_MAX_DATA_PER_TXD
);
6515 tx_desc
->read
.olinfo_status
= olinfo_status
;
6517 offset
+= IXGBE_MAX_DATA_PER_TXD
;
6518 size
-= IXGBE_MAX_DATA_PER_TXD
;
6522 if (i
== tx_ring
->count
) {
6523 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, 0);
6528 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6529 tx_buffer_info
->length
= offset
+ size
;
6530 tx_buffer_info
->tx_flags
= tx_flags
;
6531 tx_buffer_info
->dma
= dma
;
6533 tx_desc
->read
.buffer_addr
= cpu_to_le64(dma
+ offset
);
6534 tx_desc
->read
.cmd_type_len
= cmd_type
| cpu_to_le32(size
);
6535 tx_desc
->read
.olinfo_status
= olinfo_status
;
6540 frag
= &skb_shinfo(skb
)->frags
[f
];
6542 size
= min_t(unsigned int, data_len
, skb_frag_size(frag
));
6544 size
= skb_frag_size(frag
);
6550 tx_flags
|= IXGBE_TX_FLAGS_MAPPED_AS_PAGE
;
6552 dma
= skb_frag_dma_map(dev
, frag
, 0, size
, DMA_TO_DEVICE
);
6553 if (dma_mapping_error(dev
, dma
))
6558 if (i
== tx_ring
->count
) {
6559 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, 0);
6564 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(IXGBE_TXD_CMD
);
6567 if (i
== tx_ring
->count
)
6570 tx_ring
->next_to_use
= i
;
6572 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6573 gso_segs
= skb_shinfo(skb
)->gso_segs
;
6575 /* adjust for FCoE Sequence Offload */
6576 else if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6577 gso_segs
= DIV_ROUND_UP(skb
->len
- hdr_len
,
6578 skb_shinfo(skb
)->gso_size
);
6579 #endif /* IXGBE_FCOE */
6583 /* multiply data chunks by size of headers */
6584 tx_buffer_info
->bytecount
= paylen
+ (gso_segs
* hdr_len
);
6585 tx_buffer_info
->gso_segs
= gso_segs
;
6586 tx_buffer_info
->skb
= skb
;
6588 /* set the timestamp */
6589 first
->time_stamp
= jiffies
;
6592 * Force memory writes to complete before letting h/w
6593 * know there are new descriptors to fetch. (Only
6594 * applicable for weak-ordered memory model archs,
6599 /* set next_to_watch value indicating a packet is present */
6600 first
->next_to_watch
= tx_desc
;
6602 /* notify HW of packet */
6603 writel(i
, tx_ring
->tail
);
6607 dev_err(dev
, "TX DMA map failed\n");
6609 /* clear dma mappings for failed tx_buffer_info map */
6611 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6612 ixgbe_unmap_tx_resource(tx_ring
, tx_buffer_info
);
6613 if (tx_buffer_info
== first
)
6620 dev_kfree_skb_any(skb
);
6622 tx_ring
->next_to_use
= i
;
6625 static void ixgbe_atr(struct ixgbe_ring
*ring
, struct sk_buff
*skb
,
6626 u32 tx_flags
, __be16 protocol
)
6628 struct ixgbe_q_vector
*q_vector
= ring
->q_vector
;
6629 union ixgbe_atr_hash_dword input
= { .dword
= 0 };
6630 union ixgbe_atr_hash_dword common
= { .dword
= 0 };
6632 unsigned char *network
;
6634 struct ipv6hdr
*ipv6
;
6639 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6643 /* do nothing if sampling is disabled */
6644 if (!ring
->atr_sample_rate
)
6649 /* snag network header to get L4 type and address */
6650 hdr
.network
= skb_network_header(skb
);
6652 /* Currently only IPv4/IPv6 with TCP is supported */
6653 if ((protocol
!= __constant_htons(ETH_P_IPV6
) ||
6654 hdr
.ipv6
->nexthdr
!= IPPROTO_TCP
) &&
6655 (protocol
!= __constant_htons(ETH_P_IP
) ||
6656 hdr
.ipv4
->protocol
!= IPPROTO_TCP
))
6661 /* skip this packet since it is invalid or the socket is closing */
6665 /* sample on all syn packets or once every atr sample count */
6666 if (!th
->syn
&& (ring
->atr_count
< ring
->atr_sample_rate
))
6669 /* reset sample count */
6670 ring
->atr_count
= 0;
6672 vlan_id
= htons(tx_flags
>> IXGBE_TX_FLAGS_VLAN_SHIFT
);
6675 * src and dst are inverted, think how the receiver sees them
6677 * The input is broken into two sections, a non-compressed section
6678 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6679 * is XORed together and stored in the compressed dword.
6681 input
.formatted
.vlan_id
= vlan_id
;
6684 * since src port and flex bytes occupy the same word XOR them together
6685 * and write the value to source port portion of compressed dword
6687 if (tx_flags
& (IXGBE_TX_FLAGS_SW_VLAN
| IXGBE_TX_FLAGS_HW_VLAN
))
6688 common
.port
.src
^= th
->dest
^ __constant_htons(ETH_P_8021Q
);
6690 common
.port
.src
^= th
->dest
^ protocol
;
6691 common
.port
.dst
^= th
->source
;
6693 if (protocol
== __constant_htons(ETH_P_IP
)) {
6694 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV4
;
6695 common
.ip
^= hdr
.ipv4
->saddr
^ hdr
.ipv4
->daddr
;
6697 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV6
;
6698 common
.ip
^= hdr
.ipv6
->saddr
.s6_addr32
[0] ^
6699 hdr
.ipv6
->saddr
.s6_addr32
[1] ^
6700 hdr
.ipv6
->saddr
.s6_addr32
[2] ^
6701 hdr
.ipv6
->saddr
.s6_addr32
[3] ^
6702 hdr
.ipv6
->daddr
.s6_addr32
[0] ^
6703 hdr
.ipv6
->daddr
.s6_addr32
[1] ^
6704 hdr
.ipv6
->daddr
.s6_addr32
[2] ^
6705 hdr
.ipv6
->daddr
.s6_addr32
[3];
6708 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6709 ixgbe_fdir_add_signature_filter_82599(&q_vector
->adapter
->hw
,
6710 input
, common
, ring
->queue_index
);
6713 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, u16 size
)
6715 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6716 /* Herbert's original patch had:
6717 * smp_mb__after_netif_stop_queue();
6718 * but since that doesn't exist yet, just open code it. */
6721 /* We need to check again in a case another CPU has just
6722 * made room available. */
6723 if (likely(ixgbe_desc_unused(tx_ring
) < size
))
6726 /* A reprieve! - use start_queue because it doesn't call schedule */
6727 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6728 ++tx_ring
->tx_stats
.restart_queue
;
6732 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, u16 size
)
6734 if (likely(ixgbe_desc_unused(tx_ring
) >= size
))
6736 return __ixgbe_maybe_stop_tx(tx_ring
, size
);
6739 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6741 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6742 int txq
= skb_rx_queue_recorded(skb
) ? skb_get_rx_queue(skb
) :
6745 __be16 protocol
= vlan_get_protocol(skb
);
6747 if (((protocol
== htons(ETH_P_FCOE
)) ||
6748 (protocol
== htons(ETH_P_FIP
))) &&
6749 (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)) {
6750 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6751 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6756 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6757 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6758 txq
-= dev
->real_num_tx_queues
;
6762 return skb_tx_hash(dev
, skb
);
6765 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
,
6766 struct ixgbe_adapter
*adapter
,
6767 struct ixgbe_ring
*tx_ring
)
6769 struct ixgbe_tx_buffer
*first
;
6772 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6775 u16 count
= TXD_USE_COUNT(skb_headlen(skb
));
6776 __be16 protocol
= skb
->protocol
;
6780 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6781 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6782 * + 2 desc gap to keep tail from touching head,
6783 * + 1 desc for context descriptor,
6784 * otherwise try next time
6786 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6787 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6788 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6790 count
+= skb_shinfo(skb
)->nr_frags
;
6792 if (ixgbe_maybe_stop_tx(tx_ring
, count
+ 3)) {
6793 tx_ring
->tx_stats
.tx_busy
++;
6794 return NETDEV_TX_BUSY
;
6797 #ifdef CONFIG_PCI_IOV
6798 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6799 tx_flags
|= IXGBE_TX_FLAGS_TXSW
;
6802 /* if we have a HW VLAN tag being added default to the HW one */
6803 if (vlan_tx_tag_present(skb
)) {
6804 tx_flags
|= vlan_tx_tag_get(skb
) << IXGBE_TX_FLAGS_VLAN_SHIFT
;
6805 tx_flags
|= IXGBE_TX_FLAGS_HW_VLAN
;
6806 /* else if it is a SW VLAN check the next protocol and store the tag */
6807 } else if (protocol
== __constant_htons(ETH_P_8021Q
)) {
6808 struct vlan_hdr
*vhdr
, _vhdr
;
6809 vhdr
= skb_header_pointer(skb
, ETH_HLEN
, sizeof(_vhdr
), &_vhdr
);
6813 protocol
= vhdr
->h_vlan_encapsulated_proto
;
6814 tx_flags
|= ntohs(vhdr
->h_vlan_TCI
) << IXGBE_TX_FLAGS_VLAN_SHIFT
;
6815 tx_flags
|= IXGBE_TX_FLAGS_SW_VLAN
;
6818 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6819 if ((adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) &&
6820 ((tx_flags
& (IXGBE_TX_FLAGS_HW_VLAN
| IXGBE_TX_FLAGS_SW_VLAN
)) ||
6821 (skb
->priority
!= TC_PRIO_CONTROL
))) {
6822 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6823 tx_flags
|= (skb
->priority
& 0x7) <<
6824 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT
;
6825 if (tx_flags
& IXGBE_TX_FLAGS_SW_VLAN
) {
6826 struct vlan_ethhdr
*vhdr
;
6827 if (skb_header_cloned(skb
) &&
6828 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
))
6830 vhdr
= (struct vlan_ethhdr
*)skb
->data
;
6831 vhdr
->h_vlan_TCI
= htons(tx_flags
>>
6832 IXGBE_TX_FLAGS_VLAN_SHIFT
);
6834 tx_flags
|= IXGBE_TX_FLAGS_HW_VLAN
;
6838 /* record the location of the first descriptor for this packet */
6839 first
= &tx_ring
->tx_buffer_info
[tx_ring
->next_to_use
];
6842 /* setup tx offload for FCoE */
6843 if ((protocol
== __constant_htons(ETH_P_FCOE
)) &&
6844 (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)) {
6845 tso
= ixgbe_fso(tx_ring
, skb
, tx_flags
, &hdr_len
);
6849 tx_flags
|= IXGBE_TX_FLAGS_FSO
|
6850 IXGBE_TX_FLAGS_FCOE
;
6852 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6857 #endif /* IXGBE_FCOE */
6858 /* setup IPv4/IPv6 offloads */
6859 if (protocol
== __constant_htons(ETH_P_IP
))
6860 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6862 tso
= ixgbe_tso(tx_ring
, skb
, tx_flags
, protocol
, &hdr_len
);
6866 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6867 else if (ixgbe_tx_csum(tx_ring
, skb
, tx_flags
, protocol
))
6868 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6870 /* add the ATR filter if ATR is on */
6871 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE
, &tx_ring
->state
))
6872 ixgbe_atr(tx_ring
, skb
, tx_flags
, protocol
);
6876 #endif /* IXGBE_FCOE */
6877 ixgbe_tx_map(tx_ring
, skb
, first
, tx_flags
, hdr_len
);
6879 ixgbe_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
6881 return NETDEV_TX_OK
;
6884 dev_kfree_skb_any(skb
);
6885 return NETDEV_TX_OK
;
6888 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6890 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6891 struct ixgbe_ring
*tx_ring
;
6893 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6894 return ixgbe_xmit_frame_ring(skb
, adapter
, tx_ring
);
6898 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6899 * @netdev: network interface device structure
6900 * @p: pointer to an address structure
6902 * Returns 0 on success, negative on failure
6904 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6906 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6907 struct ixgbe_hw
*hw
= &adapter
->hw
;
6908 struct sockaddr
*addr
= p
;
6910 if (!is_valid_ether_addr(addr
->sa_data
))
6911 return -EADDRNOTAVAIL
;
6913 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6914 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6916 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6923 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6925 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6926 struct ixgbe_hw
*hw
= &adapter
->hw
;
6930 if (prtad
!= hw
->phy
.mdio
.prtad
)
6932 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6938 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6939 u16 addr
, u16 value
)
6941 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6942 struct ixgbe_hw
*hw
= &adapter
->hw
;
6944 if (prtad
!= hw
->phy
.mdio
.prtad
)
6946 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6949 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6951 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6953 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6957 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6959 * @netdev: network interface device structure
6961 * Returns non-zero on failure
6963 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6966 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6967 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6969 if (is_valid_ether_addr(mac
->san_addr
)) {
6971 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6978 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6980 * @netdev: network interface device structure
6982 * Returns non-zero on failure
6984 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6987 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6988 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6990 if (is_valid_ether_addr(mac
->san_addr
)) {
6992 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6998 #ifdef CONFIG_NET_POLL_CONTROLLER
7000 * Polling 'interrupt' - used by things like netconsole to send skbs
7001 * without having to re-enable interrupts. It's not called while
7002 * the interrupt routine is executing.
7004 static void ixgbe_netpoll(struct net_device
*netdev
)
7006 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7009 /* if interface is down do nothing */
7010 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
7013 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
7014 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
7015 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
7016 for (i
= 0; i
< num_q_vectors
; i
++) {
7017 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
7018 ixgbe_msix_clean_rings(0, q_vector
);
7021 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
7023 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
7027 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
7028 struct rtnl_link_stats64
*stats
)
7030 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7034 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
7035 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->rx_ring
[i
]);
7041 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7042 packets
= ring
->stats
.packets
;
7043 bytes
= ring
->stats
.bytes
;
7044 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7045 stats
->rx_packets
+= packets
;
7046 stats
->rx_bytes
+= bytes
;
7050 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
7051 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->tx_ring
[i
]);
7057 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7058 packets
= ring
->stats
.packets
;
7059 bytes
= ring
->stats
.bytes
;
7060 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7061 stats
->tx_packets
+= packets
;
7062 stats
->tx_bytes
+= bytes
;
7066 /* following stats updated by ixgbe_watchdog_task() */
7067 stats
->multicast
= netdev
->stats
.multicast
;
7068 stats
->rx_errors
= netdev
->stats
.rx_errors
;
7069 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
7070 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
7071 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
7075 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7076 * #adapter: pointer to ixgbe_adapter
7077 * @tc: number of traffic classes currently enabled
7079 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7080 * 802.1Q priority maps to a packet buffer that exists.
7082 static void ixgbe_validate_rtr(struct ixgbe_adapter
*adapter
, u8 tc
)
7084 struct ixgbe_hw
*hw
= &adapter
->hw
;
7088 /* 82598 have a static priority to TC mapping that can not
7089 * be changed so no validation is needed.
7091 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
7094 reg
= IXGBE_READ_REG(hw
, IXGBE_RTRUP2TC
);
7097 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
7098 u8 up2tc
= reg
>> (i
* IXGBE_RTRUP2TC_UP_SHIFT
);
7100 /* If up2tc is out of bounds default to zero */
7102 reg
&= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT
);
7106 IXGBE_WRITE_REG(hw
, IXGBE_RTRUP2TC
, reg
);
7112 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7115 * @netdev: net device to configure
7116 * @tc: number of traffic classes to enable
7118 int ixgbe_setup_tc(struct net_device
*dev
, u8 tc
)
7120 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7121 struct ixgbe_hw
*hw
= &adapter
->hw
;
7123 /* Multiple traffic classes requires multiple queues */
7124 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
7125 e_err(drv
, "Enable failed, needs MSI-X\n");
7129 /* Hardware supports up to 8 traffic classes */
7130 if (tc
> adapter
->dcb_cfg
.num_tcs
.pg_tcs
||
7131 (hw
->mac
.type
== ixgbe_mac_82598EB
&& tc
< MAX_TRAFFIC_CLASS
))
7134 /* Hardware has to reinitialize queues and interrupts to
7135 * match packet buffer alignment. Unfortunately, the
7136 * hardware is not flexible enough to do this dynamically.
7138 if (netif_running(dev
))
7140 ixgbe_clear_interrupt_scheme(adapter
);
7143 netdev_set_num_tc(dev
, tc
);
7144 adapter
->last_lfc_mode
= adapter
->hw
.fc
.current_mode
;
7146 adapter
->flags
|= IXGBE_FLAG_DCB_ENABLED
;
7147 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
7149 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
7150 adapter
->hw
.fc
.requested_mode
= ixgbe_fc_none
;
7152 netdev_reset_tc(dev
);
7154 adapter
->hw
.fc
.requested_mode
= adapter
->last_lfc_mode
;
7156 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
7157 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
7159 adapter
->temp_dcb_cfg
.pfc_mode_enable
= false;
7160 adapter
->dcb_cfg
.pfc_mode_enable
= false;
7163 ixgbe_init_interrupt_scheme(adapter
);
7164 ixgbe_validate_rtr(adapter
, tc
);
7165 if (netif_running(dev
))
7171 void ixgbe_do_reset(struct net_device
*netdev
)
7173 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7175 if (netif_running(netdev
))
7176 ixgbe_reinit_locked(adapter
);
7178 ixgbe_reset(adapter
);
7181 static netdev_features_t
ixgbe_fix_features(struct net_device
*netdev
,
7182 netdev_features_t data
)
7184 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7187 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
7188 data
&= ~NETIF_F_HW_VLAN_RX
;
7191 /* return error if RXHASH is being enabled when RSS is not supported */
7192 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
7193 data
&= ~NETIF_F_RXHASH
;
7195 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7196 if (!(data
& NETIF_F_RXCSUM
))
7197 data
&= ~NETIF_F_LRO
;
7199 /* Turn off LRO if not RSC capable or invalid ITR settings */
7200 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)) {
7201 data
&= ~NETIF_F_LRO
;
7202 } else if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
7203 (adapter
->rx_itr_setting
!= 1 &&
7204 adapter
->rx_itr_setting
> IXGBE_MAX_RSC_INT_RATE
)) {
7205 data
&= ~NETIF_F_LRO
;
7206 e_info(probe
, "rx-usecs set too low, not enabling RSC\n");
7212 static int ixgbe_set_features(struct net_device
*netdev
,
7213 netdev_features_t data
)
7215 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7216 bool need_reset
= false;
7218 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7219 if (!(data
& NETIF_F_RXCSUM
))
7220 adapter
->flags
&= ~IXGBE_FLAG_RX_CSUM_ENABLED
;
7222 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
7224 /* Make sure RSC matches LRO, reset if change */
7225 if (!!(data
& NETIF_F_LRO
) !=
7226 !!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)) {
7227 adapter
->flags2
^= IXGBE_FLAG2_RSC_ENABLED
;
7228 switch (adapter
->hw
.mac
.type
) {
7229 case ixgbe_mac_X540
:
7230 case ixgbe_mac_82599EB
:
7239 * Check if Flow Director n-tuple support was enabled or disabled. If
7240 * the state changed, we need to reset.
7242 if (!(adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
7243 /* turn off ATR, enable perfect filters and reset */
7244 if (data
& NETIF_F_NTUPLE
) {
7245 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
7246 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
7249 } else if (!(data
& NETIF_F_NTUPLE
)) {
7250 /* turn off Flow Director, set ATR and reset */
7251 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
7252 if ((adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) &&
7253 !(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
7254 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
7259 ixgbe_do_reset(netdev
);
7265 static const struct net_device_ops ixgbe_netdev_ops
= {
7266 .ndo_open
= ixgbe_open
,
7267 .ndo_stop
= ixgbe_close
,
7268 .ndo_start_xmit
= ixgbe_xmit_frame
,
7269 .ndo_select_queue
= ixgbe_select_queue
,
7270 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
7271 .ndo_validate_addr
= eth_validate_addr
,
7272 .ndo_set_mac_address
= ixgbe_set_mac
,
7273 .ndo_change_mtu
= ixgbe_change_mtu
,
7274 .ndo_tx_timeout
= ixgbe_tx_timeout
,
7275 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
7276 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
7277 .ndo_do_ioctl
= ixgbe_ioctl
,
7278 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
7279 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
7280 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
7281 .ndo_set_vf_spoofchk
= ixgbe_ndo_set_vf_spoofchk
,
7282 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
7283 .ndo_get_stats64
= ixgbe_get_stats64
,
7284 .ndo_setup_tc
= ixgbe_setup_tc
,
7285 #ifdef CONFIG_NET_POLL_CONTROLLER
7286 .ndo_poll_controller
= ixgbe_netpoll
,
7289 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
7290 .ndo_fcoe_ddp_target
= ixgbe_fcoe_ddp_target
,
7291 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
7292 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
7293 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
7294 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
7295 #endif /* IXGBE_FCOE */
7296 .ndo_set_features
= ixgbe_set_features
,
7297 .ndo_fix_features
= ixgbe_fix_features
,
7300 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
7301 const struct ixgbe_info
*ii
)
7303 #ifdef CONFIG_PCI_IOV
7304 struct ixgbe_hw
*hw
= &adapter
->hw
;
7306 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
7309 /* The 82599 supports up to 64 VFs per physical function
7310 * but this implementation limits allocation to 63 so that
7311 * basic networking resources are still available to the
7314 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
7315 ixgbe_enable_sriov(adapter
, ii
);
7316 #endif /* CONFIG_PCI_IOV */
7320 * ixgbe_probe - Device Initialization Routine
7321 * @pdev: PCI device information struct
7322 * @ent: entry in ixgbe_pci_tbl
7324 * Returns 0 on success, negative on failure
7326 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7327 * The OS initialization, configuring of the adapter private structure,
7328 * and a hardware reset occur.
7330 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
7331 const struct pci_device_id
*ent
)
7333 struct net_device
*netdev
;
7334 struct ixgbe_adapter
*adapter
= NULL
;
7335 struct ixgbe_hw
*hw
;
7336 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
7337 static int cards_found
;
7338 int i
, err
, pci_using_dac
;
7339 u8 part_str
[IXGBE_PBANUM_LENGTH
];
7340 unsigned int indices
= num_possible_cpus();
7347 /* Catch broken hardware that put the wrong VF device ID in
7348 * the PCIe SR-IOV capability.
7350 if (pdev
->is_virtfn
) {
7351 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
7352 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
7356 err
= pci_enable_device_mem(pdev
);
7360 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
7361 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
7364 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
7366 err
= dma_set_coherent_mask(&pdev
->dev
,
7370 "No usable DMA configuration, aborting\n");
7377 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
7378 IORESOURCE_MEM
), ixgbe_driver_name
);
7381 "pci_request_selected_regions failed 0x%x\n", err
);
7385 pci_enable_pcie_error_reporting(pdev
);
7387 pci_set_master(pdev
);
7388 pci_save_state(pdev
);
7390 #ifdef CONFIG_IXGBE_DCB
7391 indices
*= MAX_TRAFFIC_CLASS
;
7394 if (ii
->mac
== ixgbe_mac_82598EB
)
7395 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
7397 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
7400 indices
+= min_t(unsigned int, num_possible_cpus(),
7401 IXGBE_MAX_FCOE_INDICES
);
7403 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
7406 goto err_alloc_etherdev
;
7409 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
7411 adapter
= netdev_priv(netdev
);
7412 pci_set_drvdata(pdev
, adapter
);
7414 adapter
->netdev
= netdev
;
7415 adapter
->pdev
= pdev
;
7418 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
7420 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
7421 pci_resource_len(pdev
, 0));
7427 for (i
= 1; i
<= 5; i
++) {
7428 if (pci_resource_len(pdev
, i
) == 0)
7432 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
7433 ixgbe_set_ethtool_ops(netdev
);
7434 netdev
->watchdog_timeo
= 5 * HZ
;
7435 strncpy(netdev
->name
, pci_name(pdev
), sizeof(netdev
->name
) - 1);
7437 adapter
->bd_number
= cards_found
;
7440 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
7441 hw
->mac
.type
= ii
->mac
;
7444 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
7445 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
7446 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7447 if (!(eec
& (1 << 8)))
7448 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
7451 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
7452 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
7453 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7454 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
7455 hw
->phy
.mdio
.mmds
= 0;
7456 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
7457 hw
->phy
.mdio
.dev
= netdev
;
7458 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
7459 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
7461 ii
->get_invariants(hw
);
7463 /* setup the private structure */
7464 err
= ixgbe_sw_init(adapter
);
7468 /* Make it possible the adapter to be woken up via WOL */
7469 switch (adapter
->hw
.mac
.type
) {
7470 case ixgbe_mac_82599EB
:
7471 case ixgbe_mac_X540
:
7472 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7479 * If there is a fan on this device and it has failed log the
7482 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
7483 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
7484 if (esdp
& IXGBE_ESDP_SDP1
)
7485 e_crit(probe
, "Fan has stopped, replace the adapter\n");
7488 /* reset_hw fills in the perm_addr as well */
7489 hw
->phy
.reset_if_overtemp
= true;
7490 err
= hw
->mac
.ops
.reset_hw(hw
);
7491 hw
->phy
.reset_if_overtemp
= false;
7492 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
7493 hw
->mac
.type
== ixgbe_mac_82598EB
) {
7495 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
7496 e_dev_err("failed to load because an unsupported SFP+ "
7497 "module type was detected.\n");
7498 e_dev_err("Reload the driver after installing a supported "
7502 e_dev_err("HW Init failed: %d\n", err
);
7506 ixgbe_probe_vf(adapter
, ii
);
7508 netdev
->features
= NETIF_F_SG
|
7511 NETIF_F_HW_VLAN_TX
|
7512 NETIF_F_HW_VLAN_RX
|
7513 NETIF_F_HW_VLAN_FILTER
|
7519 netdev
->hw_features
= netdev
->features
;
7521 switch (adapter
->hw
.mac
.type
) {
7522 case ixgbe_mac_82599EB
:
7523 case ixgbe_mac_X540
:
7524 netdev
->features
|= NETIF_F_SCTP_CSUM
;
7525 netdev
->hw_features
|= NETIF_F_SCTP_CSUM
|
7532 netdev
->vlan_features
|= NETIF_F_TSO
;
7533 netdev
->vlan_features
|= NETIF_F_TSO6
;
7534 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
7535 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
7536 netdev
->vlan_features
|= NETIF_F_SG
;
7538 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
7540 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7541 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
7542 IXGBE_FLAG_DCB_ENABLED
);
7544 #ifdef CONFIG_IXGBE_DCB
7545 netdev
->dcbnl_ops
= &dcbnl_ops
;
7549 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7550 if (hw
->mac
.ops
.get_device_caps
) {
7551 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
7552 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
7553 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
7556 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7557 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
7558 netdev
->vlan_features
|= NETIF_F_FSO
;
7559 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
7561 #endif /* IXGBE_FCOE */
7562 if (pci_using_dac
) {
7563 netdev
->features
|= NETIF_F_HIGHDMA
;
7564 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
7567 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
7568 netdev
->hw_features
|= NETIF_F_LRO
;
7569 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
7570 netdev
->features
|= NETIF_F_LRO
;
7572 /* make sure the EEPROM is good */
7573 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
7574 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7579 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7580 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7582 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
7583 e_dev_err("invalid MAC address\n");
7588 setup_timer(&adapter
->service_timer
, &ixgbe_service_timer
,
7589 (unsigned long) adapter
);
7591 INIT_WORK(&adapter
->service_task
, ixgbe_service_task
);
7592 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
7594 err
= ixgbe_init_interrupt_scheme(adapter
);
7598 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)) {
7599 netdev
->hw_features
&= ~NETIF_F_RXHASH
;
7600 netdev
->features
&= ~NETIF_F_RXHASH
;
7603 /* WOL not supported for all but the following */
7605 switch (pdev
->device
) {
7606 case IXGBE_DEV_ID_82599_SFP
:
7607 /* Only this subdevice supports WOL */
7608 if (pdev
->subsystem_device
== IXGBE_SUBDEV_ID_82599_SFP
)
7609 adapter
->wol
= IXGBE_WUFC_MAG
;
7611 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
7612 /* All except this subdevice support WOL */
7613 if (pdev
->subsystem_device
!= IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
)
7614 adapter
->wol
= IXGBE_WUFC_MAG
;
7616 case IXGBE_DEV_ID_82599_KX4
:
7617 adapter
->wol
= IXGBE_WUFC_MAG
;
7619 case IXGBE_DEV_ID_X540T
:
7620 /* Check eeprom to see if it is enabled */
7621 hw
->eeprom
.ops
.read(hw
, 0x2c, &adapter
->eeprom_cap
);
7622 wol_cap
= adapter
->eeprom_cap
& IXGBE_DEVICE_CAPS_WOL_MASK
;
7624 if ((wol_cap
== IXGBE_DEVICE_CAPS_WOL_PORT0_1
) ||
7625 ((wol_cap
== IXGBE_DEVICE_CAPS_WOL_PORT0
) &&
7626 (hw
->bus
.func
== 0)))
7627 adapter
->wol
= IXGBE_WUFC_MAG
;
7630 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
7632 /* save off EEPROM version number */
7633 hw
->eeprom
.ops
.read(hw
, 0x2e, &adapter
->eeprom_verh
);
7634 hw
->eeprom
.ops
.read(hw
, 0x2d, &adapter
->eeprom_verl
);
7636 /* pick up the PCI bus settings for reporting later */
7637 hw
->mac
.ops
.get_bus_info(hw
);
7639 /* print bus type/speed/width info */
7640 e_dev_info("(PCI Express:%s:%s) %pM\n",
7641 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0GT/s" :
7642 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5GT/s" :
7644 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
7645 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
7646 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
7650 err
= ixgbe_read_pba_string_generic(hw
, part_str
, IXGBE_PBANUM_LENGTH
);
7652 strncpy(part_str
, "Unknown", IXGBE_PBANUM_LENGTH
);
7653 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
7654 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7655 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
7658 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7659 hw
->mac
.type
, hw
->phy
.type
, part_str
);
7661 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
7662 e_dev_warn("PCI-Express bandwidth available for this card is "
7663 "not sufficient for optimal performance.\n");
7664 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7668 /* reset the hardware with the new settings */
7669 err
= hw
->mac
.ops
.start_hw(hw
);
7671 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7672 /* We are running on a pre-production device, log a warning */
7673 e_dev_warn("This device is a pre-production adapter/LOM. "
7674 "Please be aware there may be issues associated "
7675 "with your hardware. If you are experiencing "
7676 "problems please contact your Intel or hardware "
7677 "representative who provided you with this "
7680 strcpy(netdev
->name
, "eth%d");
7681 err
= register_netdev(netdev
);
7685 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7686 if (hw
->mac
.ops
.disable_tx_laser
&&
7687 ((hw
->phy
.multispeed_fiber
) ||
7688 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
7689 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
7690 hw
->mac
.ops
.disable_tx_laser(hw
);
7692 /* carrier off reporting is important to ethtool even BEFORE open */
7693 netif_carrier_off(netdev
);
7695 #ifdef CONFIG_IXGBE_DCA
7696 if (dca_add_requester(&pdev
->dev
) == 0) {
7697 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7698 ixgbe_setup_dca(adapter
);
7701 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7702 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7703 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7704 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7707 /* firmware requires driver version to be 0xFFFFFFFF
7708 * since os does not support feature
7710 if (hw
->mac
.ops
.set_fw_drv_ver
)
7711 hw
->mac
.ops
.set_fw_drv_ver(hw
, 0xFF, 0xFF, 0xFF,
7714 /* add san mac addr to netdev */
7715 ixgbe_add_sanmac_netdev(netdev
);
7717 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7722 ixgbe_release_hw_control(adapter
);
7723 ixgbe_clear_interrupt_scheme(adapter
);
7726 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7727 ixgbe_disable_sriov(adapter
);
7728 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
7729 iounmap(hw
->hw_addr
);
7731 free_netdev(netdev
);
7733 pci_release_selected_regions(pdev
,
7734 pci_select_bars(pdev
, IORESOURCE_MEM
));
7737 pci_disable_device(pdev
);
7742 * ixgbe_remove - Device Removal Routine
7743 * @pdev: PCI device information struct
7745 * ixgbe_remove is called by the PCI subsystem to alert the driver
7746 * that it should release a PCI device. The could be caused by a
7747 * Hot-Plug event, or because the driver is going to be removed from
7750 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7752 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7753 struct net_device
*netdev
= adapter
->netdev
;
7755 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7756 cancel_work_sync(&adapter
->service_task
);
7758 #ifdef CONFIG_IXGBE_DCA
7759 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7760 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7761 dca_remove_requester(&pdev
->dev
);
7762 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7767 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7768 ixgbe_cleanup_fcoe(adapter
);
7770 #endif /* IXGBE_FCOE */
7772 /* remove the added san mac */
7773 ixgbe_del_sanmac_netdev(netdev
);
7775 if (netdev
->reg_state
== NETREG_REGISTERED
)
7776 unregister_netdev(netdev
);
7778 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7779 if (!(ixgbe_check_vf_assignment(adapter
)))
7780 ixgbe_disable_sriov(adapter
);
7782 e_dev_warn("Unloading driver while VFs are assigned "
7783 "- VFs will not be deallocated\n");
7786 ixgbe_clear_interrupt_scheme(adapter
);
7788 ixgbe_release_hw_control(adapter
);
7790 iounmap(adapter
->hw
.hw_addr
);
7791 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7794 e_dev_info("complete\n");
7796 free_netdev(netdev
);
7798 pci_disable_pcie_error_reporting(pdev
);
7800 pci_disable_device(pdev
);
7804 * ixgbe_io_error_detected - called when PCI error is detected
7805 * @pdev: Pointer to PCI device
7806 * @state: The current pci connection state
7808 * This function is called after a PCI bus error affecting
7809 * this device has been detected.
7811 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7812 pci_channel_state_t state
)
7814 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7815 struct net_device
*netdev
= adapter
->netdev
;
7817 #ifdef CONFIG_PCI_IOV
7818 struct pci_dev
*bdev
, *vfdev
;
7819 u32 dw0
, dw1
, dw2
, dw3
;
7821 u16 req_id
, pf_func
;
7823 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
||
7824 adapter
->num_vfs
== 0)
7825 goto skip_bad_vf_detection
;
7827 bdev
= pdev
->bus
->self
;
7828 while (bdev
&& (bdev
->pcie_type
!= PCI_EXP_TYPE_ROOT_PORT
))
7829 bdev
= bdev
->bus
->self
;
7832 goto skip_bad_vf_detection
;
7834 pos
= pci_find_ext_capability(bdev
, PCI_EXT_CAP_ID_ERR
);
7836 goto skip_bad_vf_detection
;
7838 pci_read_config_dword(bdev
, pos
+ PCI_ERR_HEADER_LOG
, &dw0
);
7839 pci_read_config_dword(bdev
, pos
+ PCI_ERR_HEADER_LOG
+ 4, &dw1
);
7840 pci_read_config_dword(bdev
, pos
+ PCI_ERR_HEADER_LOG
+ 8, &dw2
);
7841 pci_read_config_dword(bdev
, pos
+ PCI_ERR_HEADER_LOG
+ 12, &dw3
);
7844 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7845 if (!(req_id
& 0x0080))
7846 goto skip_bad_vf_detection
;
7848 pf_func
= req_id
& 0x01;
7849 if ((pf_func
& 1) == (pdev
->devfn
& 1)) {
7850 unsigned int device_id
;
7852 vf
= (req_id
& 0x7F) >> 1;
7853 e_dev_err("VF %d has caused a PCIe error\n", vf
);
7854 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7855 "%8.8x\tdw3: %8.8x\n",
7856 dw0
, dw1
, dw2
, dw3
);
7857 switch (adapter
->hw
.mac
.type
) {
7858 case ixgbe_mac_82599EB
:
7859 device_id
= IXGBE_82599_VF_DEVICE_ID
;
7861 case ixgbe_mac_X540
:
7862 device_id
= IXGBE_X540_VF_DEVICE_ID
;
7869 /* Find the pci device of the offending VF */
7870 vfdev
= pci_get_device(IXGBE_INTEL_VENDOR_ID
, device_id
, NULL
);
7872 if (vfdev
->devfn
== (req_id
& 0xFF))
7874 vfdev
= pci_get_device(IXGBE_INTEL_VENDOR_ID
,
7878 * There's a slim chance the VF could have been hot plugged,
7879 * so if it is no longer present we don't need to issue the
7880 * VFLR. Just clean up the AER in that case.
7883 e_dev_err("Issuing VFLR to VF %d\n", vf
);
7884 pci_write_config_dword(vfdev
, 0xA8, 0x00008000);
7887 pci_cleanup_aer_uncorrect_error_status(pdev
);
7891 * Even though the error may have occurred on the other port
7892 * we still need to increment the vf error reference count for
7893 * both ports because the I/O resume function will be called
7896 adapter
->vferr_refcount
++;
7898 return PCI_ERS_RESULT_RECOVERED
;
7900 skip_bad_vf_detection
:
7901 #endif /* CONFIG_PCI_IOV */
7902 netif_device_detach(netdev
);
7904 if (state
== pci_channel_io_perm_failure
)
7905 return PCI_ERS_RESULT_DISCONNECT
;
7907 if (netif_running(netdev
))
7908 ixgbe_down(adapter
);
7909 pci_disable_device(pdev
);
7911 /* Request a slot reset. */
7912 return PCI_ERS_RESULT_NEED_RESET
;
7916 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7917 * @pdev: Pointer to PCI device
7919 * Restart the card from scratch, as if from a cold-boot.
7921 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7923 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7924 pci_ers_result_t result
;
7927 if (pci_enable_device_mem(pdev
)) {
7928 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7929 result
= PCI_ERS_RESULT_DISCONNECT
;
7931 pci_set_master(pdev
);
7932 pci_restore_state(pdev
);
7933 pci_save_state(pdev
);
7935 pci_wake_from_d3(pdev
, false);
7937 ixgbe_reset(adapter
);
7938 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7939 result
= PCI_ERS_RESULT_RECOVERED
;
7942 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7944 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7945 "failed 0x%0x\n", err
);
7946 /* non-fatal, continue */
7953 * ixgbe_io_resume - called when traffic can start flowing again.
7954 * @pdev: Pointer to PCI device
7956 * This callback is called when the error recovery driver tells us that
7957 * its OK to resume normal operation.
7959 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7961 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7962 struct net_device
*netdev
= adapter
->netdev
;
7964 #ifdef CONFIG_PCI_IOV
7965 if (adapter
->vferr_refcount
) {
7966 e_info(drv
, "Resuming after VF err\n");
7967 adapter
->vferr_refcount
--;
7972 if (netif_running(netdev
))
7975 netif_device_attach(netdev
);
7978 static struct pci_error_handlers ixgbe_err_handler
= {
7979 .error_detected
= ixgbe_io_error_detected
,
7980 .slot_reset
= ixgbe_io_slot_reset
,
7981 .resume
= ixgbe_io_resume
,
7984 static struct pci_driver ixgbe_driver
= {
7985 .name
= ixgbe_driver_name
,
7986 .id_table
= ixgbe_pci_tbl
,
7987 .probe
= ixgbe_probe
,
7988 .remove
= __devexit_p(ixgbe_remove
),
7990 .suspend
= ixgbe_suspend
,
7991 .resume
= ixgbe_resume
,
7993 .shutdown
= ixgbe_shutdown
,
7994 .err_handler
= &ixgbe_err_handler
7998 * ixgbe_init_module - Driver Registration Routine
8000 * ixgbe_init_module is the first routine called when the driver is
8001 * loaded. All it does is register with the PCI subsystem.
8003 static int __init
ixgbe_init_module(void)
8006 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
8007 pr_info("%s\n", ixgbe_copyright
);
8009 #ifdef CONFIG_IXGBE_DCA
8010 dca_register_notify(&dca_notifier
);
8013 ret
= pci_register_driver(&ixgbe_driver
);
8017 module_init(ixgbe_init_module
);
8020 * ixgbe_exit_module - Driver Exit Cleanup Routine
8022 * ixgbe_exit_module is called just before the driver is removed
8025 static void __exit
ixgbe_exit_module(void)
8027 #ifdef CONFIG_IXGBE_DCA
8028 dca_unregister_notify(&dca_notifier
);
8030 pci_unregister_driver(&ixgbe_driver
);
8031 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8034 #ifdef CONFIG_IXGBE_DCA
8035 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
8040 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
8041 __ixgbe_notify_dca
);
8043 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
8046 #endif /* CONFIG_IXGBE_DCA */
8048 module_exit(ixgbe_exit_module
);