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ixgbe: UTA table incorrectly programmed
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #ifdef IXGBE_FCOE
59 char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
61 #else
62 static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #endif
65 #define MAJ 3
66 #define MIN 8
67 #define BUILD 21
68 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
69 __stringify(BUILD) "-k"
70 const char ixgbe_driver_version[] = DRV_VERSION;
71 static const char ixgbe_copyright[] =
72 "Copyright (c) 1999-2012 Intel Corporation.";
73
74 static const struct ixgbe_info *ixgbe_info_tbl[] = {
75 [board_82598] = &ixgbe_82598_info,
76 [board_82599] = &ixgbe_82599_info,
77 [board_X540] = &ixgbe_X540_info,
78 };
79
80 /* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 /* required last entry */
118 {0, }
119 };
120 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
122 #ifdef CONFIG_IXGBE_DCA
123 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 void *p);
125 static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129 };
130 #endif
131
132 #ifdef CONFIG_PCI_IOV
133 static unsigned int max_vfs;
134 module_param(max_vfs, uint, 0);
135 MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function");
137 #endif /* CONFIG_PCI_IOV */
138
139 static unsigned int allow_unsupported_sfp;
140 module_param(allow_unsupported_sfp, uint, 0);
141 MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
144 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145 static int debug = -1;
146 module_param(debug, int, 0);
147 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
149 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151 MODULE_LICENSE("GPL");
152 MODULE_VERSION(DRV_VERSION);
153
154 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155 {
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159 }
160
161 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162 {
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
165 /* flush memory to make sure state is correct before next watchdog */
166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168 }
169
170 struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173 };
174
175 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205 };
206
207
208 /*
209 * ixgbe_regdump - register printout routine
210 */
211 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212 {
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
275 pr_info("%-15s %08x\n", reginfo->name,
276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
282 pr_err("%-15s", rname);
283 for (j = 0; j < 8; j++)
284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
286 }
287
288 }
289
290 /*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293 static void ixgbe_dump(struct ixgbe_adapter *adapter)
294 {
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
300 struct ixgbe_tx_buffer *tx_buffer;
301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
315 pr_info("Device Name state "
316 "trans_start last_rx\n");
317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
326 pr_info(" Register Name Value\n");
327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
377 tx_buffer = &tx_ring->tx_buffer_info[i];
378 u0 = (struct my_u0 *)tx_desc;
379 pr_info("T [0x%03X] %016llX %016llX %016llX"
380 " %04X %p %016llX %p", i,
381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
390 pr_cont(" NTC/U\n");
391 else if (i == tx_ring->next_to_use)
392 pr_cont(" NTU\n");
393 else if (i == tx_ring->next_to_clean)
394 pr_cont(" NTC\n");
395 else
396 pr_cont("\n");
397
398 if (netif_msg_pktdata(adapter) &&
399 dma_unmap_len(tx_buffer, len) != 0)
400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
406 }
407 }
408
409 /* Print RX Rings Summary */
410 rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
412 pr_info("Queue [NTU] [NTC]\n");
413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
464 pr_info("RWB[0x%03X] %016llX "
465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
470 pr_info("R [0x%03X] %016llX "
471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
481 ixgbe_rx_bufsz(rx_ring), true);
482 }
483 }
484
485 if (i == rx_ring->next_to_use)
486 pr_cont(" NTU\n");
487 else if (i == rx_ring->next_to_clean)
488 pr_cont(" NTC\n");
489 else
490 pr_cont("\n");
491
492 }
493 }
494
495 exit:
496 return;
497 }
498
499 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500 {
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
507 }
508
509 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510 {
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
517 }
518
519 /*
520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
528 u8 queue, u8 msix_vector)
529 {
530 u32 ivar, index;
531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
544 case ixgbe_mac_X540:
545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
567 }
568
569 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
570 u64 qmask)
571 {
572 u32 mask;
573
574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
578 break;
579 case ixgbe_mac_82599EB:
580 case ixgbe_mac_X540:
581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
585 break;
586 default:
587 break;
588 }
589 }
590
591 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
593 {
594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
597 dma_unmap_single(ring->dev,
598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
606 }
607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
611 }
612
613 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
614 {
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
617 u32 data = 0;
618 u32 xoff[8] = {0};
619 int i;
620
621 if ((hw->fc.current_mode == ixgbe_fc_full) ||
622 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
623 switch (hw->mac.type) {
624 case ixgbe_mac_82598EB:
625 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
626 break;
627 default:
628 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
629 }
630 hwstats->lxoffrxc += data;
631
632 /* refill credits (no tx hang) if we received xoff */
633 if (!data)
634 return;
635
636 for (i = 0; i < adapter->num_tx_queues; i++)
637 clear_bit(__IXGBE_HANG_CHECK_ARMED,
638 &adapter->tx_ring[i]->state);
639 return;
640 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
641 return;
642
643 /* update stats for each tc, only valid with PFC enabled */
644 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
645 switch (hw->mac.type) {
646 case ixgbe_mac_82598EB:
647 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
648 break;
649 default:
650 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
651 }
652 hwstats->pxoffrxc[i] += xoff[i];
653 }
654
655 /* disarm tx queues that have received xoff frames */
656 for (i = 0; i < adapter->num_tx_queues; i++) {
657 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
658 u8 tc = tx_ring->dcb_tc;
659
660 if (xoff[tc])
661 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
662 }
663 }
664
665 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
666 {
667 return ring->stats.packets;
668 }
669
670 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
671 {
672 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
673 struct ixgbe_hw *hw = &adapter->hw;
674
675 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
676 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
677
678 if (head != tail)
679 return (head < tail) ?
680 tail - head : (tail + ring->count - head);
681
682 return 0;
683 }
684
685 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
686 {
687 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
688 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
689 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
690 bool ret = false;
691
692 clear_check_for_tx_hang(tx_ring);
693
694 /*
695 * Check for a hung queue, but be thorough. This verifies
696 * that a transmit has been completed since the previous
697 * check AND there is at least one packet pending. The
698 * ARMED bit is set to indicate a potential hang. The
699 * bit is cleared if a pause frame is received to remove
700 * false hang detection due to PFC or 802.3x frames. By
701 * requiring this to fail twice we avoid races with
702 * pfc clearing the ARMED bit and conditions where we
703 * run the check_tx_hang logic with a transmit completion
704 * pending but without time to complete it yet.
705 */
706 if ((tx_done_old == tx_done) && tx_pending) {
707 /* make sure it is true for two checks in a row */
708 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
709 &tx_ring->state);
710 } else {
711 /* update completed stats and continue */
712 tx_ring->tx_stats.tx_done_old = tx_done;
713 /* reset the countdown */
714 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
715 }
716
717 return ret;
718 }
719
720 /**
721 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
722 * @adapter: driver private struct
723 **/
724 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
725 {
726
727 /* Do the reset outside of interrupt context */
728 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
729 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
730 ixgbe_service_event_schedule(adapter);
731 }
732 }
733
734 /**
735 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
736 * @q_vector: structure containing interrupt and ring information
737 * @tx_ring: tx ring to clean
738 **/
739 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
740 struct ixgbe_ring *tx_ring)
741 {
742 struct ixgbe_adapter *adapter = q_vector->adapter;
743 struct ixgbe_tx_buffer *tx_buffer;
744 union ixgbe_adv_tx_desc *tx_desc;
745 unsigned int total_bytes = 0, total_packets = 0;
746 unsigned int budget = q_vector->tx.work_limit;
747 unsigned int i = tx_ring->next_to_clean;
748
749 if (test_bit(__IXGBE_DOWN, &adapter->state))
750 return true;
751
752 tx_buffer = &tx_ring->tx_buffer_info[i];
753 tx_desc = IXGBE_TX_DESC(tx_ring, i);
754 i -= tx_ring->count;
755
756 do {
757 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
758
759 /* if next_to_watch is not set then there is no work pending */
760 if (!eop_desc)
761 break;
762
763 /* prevent any other reads prior to eop_desc */
764 rmb();
765
766 /* if DD is not set pending work has not been completed */
767 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
768 break;
769
770 /* clear next_to_watch to prevent false hangs */
771 tx_buffer->next_to_watch = NULL;
772
773 /* update the statistics for this packet */
774 total_bytes += tx_buffer->bytecount;
775 total_packets += tx_buffer->gso_segs;
776
777 /* free the skb */
778 dev_kfree_skb_any(tx_buffer->skb);
779
780 /* unmap skb header data */
781 dma_unmap_single(tx_ring->dev,
782 dma_unmap_addr(tx_buffer, dma),
783 dma_unmap_len(tx_buffer, len),
784 DMA_TO_DEVICE);
785
786 /* clear tx_buffer data */
787 tx_buffer->skb = NULL;
788 dma_unmap_len_set(tx_buffer, len, 0);
789
790 /* unmap remaining buffers */
791 while (tx_desc != eop_desc) {
792 tx_buffer++;
793 tx_desc++;
794 i++;
795 if (unlikely(!i)) {
796 i -= tx_ring->count;
797 tx_buffer = tx_ring->tx_buffer_info;
798 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
799 }
800
801 /* unmap any remaining paged data */
802 if (dma_unmap_len(tx_buffer, len)) {
803 dma_unmap_page(tx_ring->dev,
804 dma_unmap_addr(tx_buffer, dma),
805 dma_unmap_len(tx_buffer, len),
806 DMA_TO_DEVICE);
807 dma_unmap_len_set(tx_buffer, len, 0);
808 }
809 }
810
811 /* move us one more past the eop_desc for start of next pkt */
812 tx_buffer++;
813 tx_desc++;
814 i++;
815 if (unlikely(!i)) {
816 i -= tx_ring->count;
817 tx_buffer = tx_ring->tx_buffer_info;
818 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
819 }
820
821 /* issue prefetch for next Tx descriptor */
822 prefetch(tx_desc);
823
824 /* update budget accounting */
825 budget--;
826 } while (likely(budget));
827
828 i += tx_ring->count;
829 tx_ring->next_to_clean = i;
830 u64_stats_update_begin(&tx_ring->syncp);
831 tx_ring->stats.bytes += total_bytes;
832 tx_ring->stats.packets += total_packets;
833 u64_stats_update_end(&tx_ring->syncp);
834 q_vector->tx.total_bytes += total_bytes;
835 q_vector->tx.total_packets += total_packets;
836
837 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
838 /* schedule immediate reset if we believe we hung */
839 struct ixgbe_hw *hw = &adapter->hw;
840 e_err(drv, "Detected Tx Unit Hang\n"
841 " Tx Queue <%d>\n"
842 " TDH, TDT <%x>, <%x>\n"
843 " next_to_use <%x>\n"
844 " next_to_clean <%x>\n"
845 "tx_buffer_info[next_to_clean]\n"
846 " time_stamp <%lx>\n"
847 " jiffies <%lx>\n",
848 tx_ring->queue_index,
849 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
850 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
851 tx_ring->next_to_use, i,
852 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
853
854 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
855
856 e_info(probe,
857 "tx hang %d detected on queue %d, resetting adapter\n",
858 adapter->tx_timeout_count + 1, tx_ring->queue_index);
859
860 /* schedule immediate reset if we believe we hung */
861 ixgbe_tx_timeout_reset(adapter);
862
863 /* the adapter is about to reset, no point in enabling stuff */
864 return true;
865 }
866
867 netdev_tx_completed_queue(txring_txq(tx_ring),
868 total_packets, total_bytes);
869
870 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
871 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
872 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
873 /* Make sure that anybody stopping the queue after this
874 * sees the new next_to_clean.
875 */
876 smp_mb();
877 if (__netif_subqueue_stopped(tx_ring->netdev,
878 tx_ring->queue_index)
879 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
880 netif_wake_subqueue(tx_ring->netdev,
881 tx_ring->queue_index);
882 ++tx_ring->tx_stats.restart_queue;
883 }
884 }
885
886 return !!budget;
887 }
888
889 #ifdef CONFIG_IXGBE_DCA
890 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
891 struct ixgbe_ring *tx_ring,
892 int cpu)
893 {
894 struct ixgbe_hw *hw = &adapter->hw;
895 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
896 u16 reg_offset;
897
898 switch (hw->mac.type) {
899 case ixgbe_mac_82598EB:
900 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
901 break;
902 case ixgbe_mac_82599EB:
903 case ixgbe_mac_X540:
904 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
905 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
906 break;
907 default:
908 /* for unknown hardware do not write register */
909 return;
910 }
911
912 /*
913 * We can enable relaxed ordering for reads, but not writes when
914 * DCA is enabled. This is due to a known issue in some chipsets
915 * which will cause the DCA tag to be cleared.
916 */
917 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
918 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
919 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
920
921 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
922 }
923
924 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
925 struct ixgbe_ring *rx_ring,
926 int cpu)
927 {
928 struct ixgbe_hw *hw = &adapter->hw;
929 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
930 u8 reg_idx = rx_ring->reg_idx;
931
932
933 switch (hw->mac.type) {
934 case ixgbe_mac_82599EB:
935 case ixgbe_mac_X540:
936 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
937 break;
938 default:
939 break;
940 }
941
942 /*
943 * We can enable relaxed ordering for reads, but not writes when
944 * DCA is enabled. This is due to a known issue in some chipsets
945 * which will cause the DCA tag to be cleared.
946 */
947 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
948 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
949 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
950
951 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
952 }
953
954 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
955 {
956 struct ixgbe_adapter *adapter = q_vector->adapter;
957 struct ixgbe_ring *ring;
958 int cpu = get_cpu();
959
960 if (q_vector->cpu == cpu)
961 goto out_no_update;
962
963 ixgbe_for_each_ring(ring, q_vector->tx)
964 ixgbe_update_tx_dca(adapter, ring, cpu);
965
966 ixgbe_for_each_ring(ring, q_vector->rx)
967 ixgbe_update_rx_dca(adapter, ring, cpu);
968
969 q_vector->cpu = cpu;
970 out_no_update:
971 put_cpu();
972 }
973
974 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
975 {
976 int num_q_vectors;
977 int i;
978
979 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
980 return;
981
982 /* always use CB2 mode, difference is masked in the CB driver */
983 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
984
985 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
986 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
987 else
988 num_q_vectors = 1;
989
990 for (i = 0; i < num_q_vectors; i++) {
991 adapter->q_vector[i]->cpu = -1;
992 ixgbe_update_dca(adapter->q_vector[i]);
993 }
994 }
995
996 static int __ixgbe_notify_dca(struct device *dev, void *data)
997 {
998 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
999 unsigned long event = *(unsigned long *)data;
1000
1001 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1002 return 0;
1003
1004 switch (event) {
1005 case DCA_PROVIDER_ADD:
1006 /* if we're already enabled, don't do it again */
1007 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1008 break;
1009 if (dca_add_requester(dev) == 0) {
1010 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1011 ixgbe_setup_dca(adapter);
1012 break;
1013 }
1014 /* Fall Through since DCA is disabled. */
1015 case DCA_PROVIDER_REMOVE:
1016 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1017 dca_remove_requester(dev);
1018 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1020 }
1021 break;
1022 }
1023
1024 return 0;
1025 }
1026
1027 #endif /* CONFIG_IXGBE_DCA */
1028 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1029 union ixgbe_adv_rx_desc *rx_desc,
1030 struct sk_buff *skb)
1031 {
1032 if (ring->netdev->features & NETIF_F_RXHASH)
1033 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1034 }
1035
1036 #ifdef IXGBE_FCOE
1037 /**
1038 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1039 * @adapter: address of board private structure
1040 * @rx_desc: advanced rx descriptor
1041 *
1042 * Returns : true if it is FCoE pkt
1043 */
1044 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1045 union ixgbe_adv_rx_desc *rx_desc)
1046 {
1047 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1048
1049 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1050 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1051 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1052 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1053 }
1054
1055 #endif /* IXGBE_FCOE */
1056 /**
1057 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1058 * @ring: structure containing ring specific data
1059 * @rx_desc: current Rx descriptor being processed
1060 * @skb: skb currently being received and modified
1061 **/
1062 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1063 union ixgbe_adv_rx_desc *rx_desc,
1064 struct sk_buff *skb)
1065 {
1066 skb_checksum_none_assert(skb);
1067
1068 /* Rx csum disabled */
1069 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1070 return;
1071
1072 /* if IP and error */
1073 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1074 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1075 ring->rx_stats.csum_err++;
1076 return;
1077 }
1078
1079 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1080 return;
1081
1082 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1083 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1084
1085 /*
1086 * 82599 errata, UDP frames with a 0 checksum can be marked as
1087 * checksum errors.
1088 */
1089 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1090 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1091 return;
1092
1093 ring->rx_stats.csum_err++;
1094 return;
1095 }
1096
1097 /* It must be a TCP or UDP packet with a valid checksum */
1098 skb->ip_summed = CHECKSUM_UNNECESSARY;
1099 }
1100
1101 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1102 {
1103 rx_ring->next_to_use = val;
1104
1105 /* update next to alloc since we have filled the ring */
1106 rx_ring->next_to_alloc = val;
1107 /*
1108 * Force memory writes to complete before letting h/w
1109 * know there are new descriptors to fetch. (Only
1110 * applicable for weak-ordered memory model archs,
1111 * such as IA-64).
1112 */
1113 wmb();
1114 writel(val, rx_ring->tail);
1115 }
1116
1117 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1118 struct ixgbe_rx_buffer *bi)
1119 {
1120 struct page *page = bi->page;
1121 dma_addr_t dma = bi->dma;
1122
1123 /* since we are recycling buffers we should seldom need to alloc */
1124 if (likely(dma))
1125 return true;
1126
1127 /* alloc new page for storage */
1128 if (likely(!page)) {
1129 page = alloc_pages(GFP_ATOMIC | __GFP_COLD,
1130 ixgbe_rx_pg_order(rx_ring));
1131 if (unlikely(!page)) {
1132 rx_ring->rx_stats.alloc_rx_page_failed++;
1133 return false;
1134 }
1135 bi->page = page;
1136 }
1137
1138 /* map page for use */
1139 dma = dma_map_page(rx_ring->dev, page, 0,
1140 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1141
1142 /*
1143 * if mapping failed free memory back to system since
1144 * there isn't much point in holding memory we can't use
1145 */
1146 if (dma_mapping_error(rx_ring->dev, dma)) {
1147 put_page(page);
1148 bi->page = NULL;
1149
1150 rx_ring->rx_stats.alloc_rx_page_failed++;
1151 return false;
1152 }
1153
1154 bi->dma = dma;
1155 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1156
1157 return true;
1158 }
1159
1160 /**
1161 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1162 * @rx_ring: ring to place buffers on
1163 * @cleaned_count: number of buffers to replace
1164 **/
1165 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1166 {
1167 union ixgbe_adv_rx_desc *rx_desc;
1168 struct ixgbe_rx_buffer *bi;
1169 u16 i = rx_ring->next_to_use;
1170
1171 /* nothing to do */
1172 if (!cleaned_count)
1173 return;
1174
1175 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1176 bi = &rx_ring->rx_buffer_info[i];
1177 i -= rx_ring->count;
1178
1179 do {
1180 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1181 break;
1182
1183 /*
1184 * Refresh the desc even if buffer_addrs didn't change
1185 * because each write-back erases this info.
1186 */
1187 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1188
1189 rx_desc++;
1190 bi++;
1191 i++;
1192 if (unlikely(!i)) {
1193 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1194 bi = rx_ring->rx_buffer_info;
1195 i -= rx_ring->count;
1196 }
1197
1198 /* clear the hdr_addr for the next_to_use descriptor */
1199 rx_desc->read.hdr_addr = 0;
1200
1201 cleaned_count--;
1202 } while (cleaned_count);
1203
1204 i += rx_ring->count;
1205
1206 if (rx_ring->next_to_use != i)
1207 ixgbe_release_rx_desc(rx_ring, i);
1208 }
1209
1210 /**
1211 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1212 * @data: pointer to the start of the headers
1213 * @max_len: total length of section to find headers in
1214 *
1215 * This function is meant to determine the length of headers that will
1216 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1217 * motivation of doing this is to only perform one pull for IPv4 TCP
1218 * packets so that we can do basic things like calculating the gso_size
1219 * based on the average data per packet.
1220 **/
1221 static unsigned int ixgbe_get_headlen(unsigned char *data,
1222 unsigned int max_len)
1223 {
1224 union {
1225 unsigned char *network;
1226 /* l2 headers */
1227 struct ethhdr *eth;
1228 struct vlan_hdr *vlan;
1229 /* l3 headers */
1230 struct iphdr *ipv4;
1231 } hdr;
1232 __be16 protocol;
1233 u8 nexthdr = 0; /* default to not TCP */
1234 u8 hlen;
1235
1236 /* this should never happen, but better safe than sorry */
1237 if (max_len < ETH_HLEN)
1238 return max_len;
1239
1240 /* initialize network frame pointer */
1241 hdr.network = data;
1242
1243 /* set first protocol and move network header forward */
1244 protocol = hdr.eth->h_proto;
1245 hdr.network += ETH_HLEN;
1246
1247 /* handle any vlan tag if present */
1248 if (protocol == __constant_htons(ETH_P_8021Q)) {
1249 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1250 return max_len;
1251
1252 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1253 hdr.network += VLAN_HLEN;
1254 }
1255
1256 /* handle L3 protocols */
1257 if (protocol == __constant_htons(ETH_P_IP)) {
1258 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1259 return max_len;
1260
1261 /* access ihl as a u8 to avoid unaligned access on ia64 */
1262 hlen = (hdr.network[0] & 0x0F) << 2;
1263
1264 /* verify hlen meets minimum size requirements */
1265 if (hlen < sizeof(struct iphdr))
1266 return hdr.network - data;
1267
1268 /* record next protocol */
1269 nexthdr = hdr.ipv4->protocol;
1270 hdr.network += hlen;
1271 #ifdef IXGBE_FCOE
1272 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1273 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1274 return max_len;
1275 hdr.network += FCOE_HEADER_LEN;
1276 #endif
1277 } else {
1278 return hdr.network - data;
1279 }
1280
1281 /* finally sort out TCP */
1282 if (nexthdr == IPPROTO_TCP) {
1283 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1284 return max_len;
1285
1286 /* access doff as a u8 to avoid unaligned access on ia64 */
1287 hlen = (hdr.network[12] & 0xF0) >> 2;
1288
1289 /* verify hlen meets minimum size requirements */
1290 if (hlen < sizeof(struct tcphdr))
1291 return hdr.network - data;
1292
1293 hdr.network += hlen;
1294 }
1295
1296 /*
1297 * If everything has gone correctly hdr.network should be the
1298 * data section of the packet and will be the end of the header.
1299 * If not then it probably represents the end of the last recognized
1300 * header.
1301 */
1302 if ((hdr.network - data) < max_len)
1303 return hdr.network - data;
1304 else
1305 return max_len;
1306 }
1307
1308 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1309 union ixgbe_adv_rx_desc *rx_desc,
1310 struct sk_buff *skb)
1311 {
1312 __le32 rsc_enabled;
1313 u32 rsc_cnt;
1314
1315 if (!ring_is_rsc_enabled(rx_ring))
1316 return;
1317
1318 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1319 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1320
1321 /* If this is an RSC frame rsc_cnt should be non-zero */
1322 if (!rsc_enabled)
1323 return;
1324
1325 rsc_cnt = le32_to_cpu(rsc_enabled);
1326 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1327
1328 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1329 }
1330
1331 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1332 struct sk_buff *skb)
1333 {
1334 u16 hdr_len = skb_headlen(skb);
1335
1336 /* set gso_size to avoid messing up TCP MSS */
1337 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1338 IXGBE_CB(skb)->append_cnt);
1339 }
1340
1341 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1342 struct sk_buff *skb)
1343 {
1344 /* if append_cnt is 0 then frame is not RSC */
1345 if (!IXGBE_CB(skb)->append_cnt)
1346 return;
1347
1348 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1349 rx_ring->rx_stats.rsc_flush++;
1350
1351 ixgbe_set_rsc_gso_size(rx_ring, skb);
1352
1353 /* gso_size is computed using append_cnt so always clear it last */
1354 IXGBE_CB(skb)->append_cnt = 0;
1355 }
1356
1357 /**
1358 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1359 * @rx_ring: rx descriptor ring packet is being transacted on
1360 * @rx_desc: pointer to the EOP Rx descriptor
1361 * @skb: pointer to current skb being populated
1362 *
1363 * This function checks the ring, descriptor, and packet information in
1364 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1365 * other fields within the skb.
1366 **/
1367 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1368 union ixgbe_adv_rx_desc *rx_desc,
1369 struct sk_buff *skb)
1370 {
1371 ixgbe_update_rsc_stats(rx_ring, skb);
1372
1373 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1374
1375 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1376
1377 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1378 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1379 __vlan_hwaccel_put_tag(skb, vid);
1380 }
1381
1382 skb_record_rx_queue(skb, rx_ring->queue_index);
1383
1384 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1385 }
1386
1387 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1388 struct sk_buff *skb)
1389 {
1390 struct ixgbe_adapter *adapter = q_vector->adapter;
1391
1392 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1393 napi_gro_receive(&q_vector->napi, skb);
1394 else
1395 netif_rx(skb);
1396 }
1397
1398 /**
1399 * ixgbe_is_non_eop - process handling of non-EOP buffers
1400 * @rx_ring: Rx ring being processed
1401 * @rx_desc: Rx descriptor for current buffer
1402 * @skb: Current socket buffer containing buffer in progress
1403 *
1404 * This function updates next to clean. If the buffer is an EOP buffer
1405 * this function exits returning false, otherwise it will place the
1406 * sk_buff in the next buffer to be chained and return true indicating
1407 * that this is in fact a non-EOP buffer.
1408 **/
1409 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1410 union ixgbe_adv_rx_desc *rx_desc,
1411 struct sk_buff *skb)
1412 {
1413 u32 ntc = rx_ring->next_to_clean + 1;
1414
1415 /* fetch, update, and store next to clean */
1416 ntc = (ntc < rx_ring->count) ? ntc : 0;
1417 rx_ring->next_to_clean = ntc;
1418
1419 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1420
1421 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1422 return false;
1423
1424 /* append_cnt indicates packet is RSC, if so fetch nextp */
1425 if (IXGBE_CB(skb)->append_cnt) {
1426 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1427 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1428 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1429 }
1430
1431 /* place skb in next buffer to be received */
1432 rx_ring->rx_buffer_info[ntc].skb = skb;
1433 rx_ring->rx_stats.non_eop_descs++;
1434
1435 return true;
1436 }
1437
1438 /**
1439 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1440 * @rx_ring: rx descriptor ring packet is being transacted on
1441 * @rx_desc: pointer to the EOP Rx descriptor
1442 * @skb: pointer to current skb being fixed
1443 *
1444 * Check for corrupted packet headers caused by senders on the local L2
1445 * embedded NIC switch not setting up their Tx Descriptors right. These
1446 * should be very rare.
1447 *
1448 * Also address the case where we are pulling data in on pages only
1449 * and as such no data is present in the skb header.
1450 *
1451 * In addition if skb is not at least 60 bytes we need to pad it so that
1452 * it is large enough to qualify as a valid Ethernet frame.
1453 *
1454 * Returns true if an error was encountered and skb was freed.
1455 **/
1456 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1457 union ixgbe_adv_rx_desc *rx_desc,
1458 struct sk_buff *skb)
1459 {
1460 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1461 struct net_device *netdev = rx_ring->netdev;
1462 unsigned char *va;
1463 unsigned int pull_len;
1464
1465 /* if the page was released unmap it, else just sync our portion */
1466 if (unlikely(IXGBE_CB(skb)->page_released)) {
1467 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1468 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1469 IXGBE_CB(skb)->page_released = false;
1470 } else {
1471 dma_sync_single_range_for_cpu(rx_ring->dev,
1472 IXGBE_CB(skb)->dma,
1473 frag->page_offset,
1474 ixgbe_rx_bufsz(rx_ring),
1475 DMA_FROM_DEVICE);
1476 }
1477 IXGBE_CB(skb)->dma = 0;
1478
1479 /* verify that the packet does not have any known errors */
1480 if (unlikely(ixgbe_test_staterr(rx_desc,
1481 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1482 !(netdev->features & NETIF_F_RXALL))) {
1483 dev_kfree_skb_any(skb);
1484 return true;
1485 }
1486
1487 /*
1488 * it is valid to use page_address instead of kmap since we are
1489 * working with pages allocated out of the lomem pool per
1490 * alloc_page(GFP_ATOMIC)
1491 */
1492 va = skb_frag_address(frag);
1493
1494 /*
1495 * we need the header to contain the greater of either ETH_HLEN or
1496 * 60 bytes if the skb->len is less than 60 for skb_pad.
1497 */
1498 pull_len = skb_frag_size(frag);
1499 if (pull_len > 256)
1500 pull_len = ixgbe_get_headlen(va, pull_len);
1501
1502 /* align pull length to size of long to optimize memcpy performance */
1503 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1504
1505 /* update all of the pointers */
1506 skb_frag_size_sub(frag, pull_len);
1507 frag->page_offset += pull_len;
1508 skb->data_len -= pull_len;
1509 skb->tail += pull_len;
1510
1511 /*
1512 * if we sucked the frag empty then we should free it,
1513 * if there are other frags here something is screwed up in hardware
1514 */
1515 if (skb_frag_size(frag) == 0) {
1516 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1517 skb_shinfo(skb)->nr_frags = 0;
1518 __skb_frag_unref(frag);
1519 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1520 }
1521
1522 /* if skb_pad returns an error the skb was freed */
1523 if (unlikely(skb->len < 60)) {
1524 int pad_len = 60 - skb->len;
1525
1526 if (skb_pad(skb, pad_len))
1527 return true;
1528 __skb_put(skb, pad_len);
1529 }
1530
1531 return false;
1532 }
1533
1534 /**
1535 * ixgbe_can_reuse_page - determine if we can reuse a page
1536 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1537 *
1538 * Returns true if page can be reused in another Rx buffer
1539 **/
1540 static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1541 {
1542 struct page *page = rx_buffer->page;
1543
1544 /* if we are only owner of page and it is local we can reuse it */
1545 return likely(page_count(page) == 1) &&
1546 likely(page_to_nid(page) == numa_node_id());
1547 }
1548
1549 /**
1550 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1551 * @rx_ring: rx descriptor ring to store buffers on
1552 * @old_buff: donor buffer to have page reused
1553 *
1554 * Syncronizes page for reuse by the adapter
1555 **/
1556 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1557 struct ixgbe_rx_buffer *old_buff)
1558 {
1559 struct ixgbe_rx_buffer *new_buff;
1560 u16 nta = rx_ring->next_to_alloc;
1561 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1562
1563 new_buff = &rx_ring->rx_buffer_info[nta];
1564
1565 /* update, and store next to alloc */
1566 nta++;
1567 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1568
1569 /* transfer page from old buffer to new buffer */
1570 new_buff->page = old_buff->page;
1571 new_buff->dma = old_buff->dma;
1572
1573 /* flip page offset to other buffer and store to new_buff */
1574 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1575
1576 /* sync the buffer for use by the device */
1577 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1578 new_buff->page_offset, bufsz,
1579 DMA_FROM_DEVICE);
1580
1581 /* bump ref count on page before it is given to the stack */
1582 get_page(new_buff->page);
1583 }
1584
1585 /**
1586 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1587 * @rx_ring: rx descriptor ring to transact packets on
1588 * @rx_buffer: buffer containing page to add
1589 * @rx_desc: descriptor containing length of buffer written by hardware
1590 * @skb: sk_buff to place the data into
1591 *
1592 * This function is based on skb_add_rx_frag. I would have used that
1593 * function however it doesn't handle the truesize case correctly since we
1594 * are allocating more memory than might be used for a single receive.
1595 **/
1596 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1597 struct ixgbe_rx_buffer *rx_buffer,
1598 struct sk_buff *skb, int size)
1599 {
1600 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1601 rx_buffer->page, rx_buffer->page_offset,
1602 size);
1603 skb->len += size;
1604 skb->data_len += size;
1605 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1606 }
1607
1608 /**
1609 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1610 * @q_vector: structure containing interrupt and ring information
1611 * @rx_ring: rx descriptor ring to transact packets on
1612 * @budget: Total limit on number of packets to process
1613 *
1614 * This function provides a "bounce buffer" approach to Rx interrupt
1615 * processing. The advantage to this is that on systems that have
1616 * expensive overhead for IOMMU access this provides a means of avoiding
1617 * it by maintaining the mapping of the page to the syste.
1618 *
1619 * Returns true if all work is completed without reaching budget
1620 **/
1621 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1622 struct ixgbe_ring *rx_ring,
1623 int budget)
1624 {
1625 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1626 #ifdef IXGBE_FCOE
1627 struct ixgbe_adapter *adapter = q_vector->adapter;
1628 int ddp_bytes = 0;
1629 #endif /* IXGBE_FCOE */
1630 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1631
1632 do {
1633 struct ixgbe_rx_buffer *rx_buffer;
1634 union ixgbe_adv_rx_desc *rx_desc;
1635 struct sk_buff *skb;
1636 struct page *page;
1637 u16 ntc;
1638
1639 /* return some buffers to hardware, one at a time is too slow */
1640 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1641 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1642 cleaned_count = 0;
1643 }
1644
1645 ntc = rx_ring->next_to_clean;
1646 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1647 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1648
1649 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1650 break;
1651
1652 /*
1653 * This memory barrier is needed to keep us from reading
1654 * any other fields out of the rx_desc until we know the
1655 * RXD_STAT_DD bit is set
1656 */
1657 rmb();
1658
1659 page = rx_buffer->page;
1660 prefetchw(page);
1661
1662 skb = rx_buffer->skb;
1663
1664 if (likely(!skb)) {
1665 void *page_addr = page_address(page) +
1666 rx_buffer->page_offset;
1667
1668 /* prefetch first cache line of first page */
1669 prefetch(page_addr);
1670 #if L1_CACHE_BYTES < 128
1671 prefetch(page_addr + L1_CACHE_BYTES);
1672 #endif
1673
1674 /* allocate a skb to store the frags */
1675 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1676 IXGBE_RX_HDR_SIZE);
1677 if (unlikely(!skb)) {
1678 rx_ring->rx_stats.alloc_rx_buff_failed++;
1679 break;
1680 }
1681
1682 /*
1683 * we will be copying header into skb->data in
1684 * pskb_may_pull so it is in our interest to prefetch
1685 * it now to avoid a possible cache miss
1686 */
1687 prefetchw(skb->data);
1688
1689 /*
1690 * Delay unmapping of the first packet. It carries the
1691 * header information, HW may still access the header
1692 * after the writeback. Only unmap it when EOP is
1693 * reached
1694 */
1695 IXGBE_CB(skb)->dma = rx_buffer->dma;
1696 } else {
1697 /* we are reusing so sync this buffer for CPU use */
1698 dma_sync_single_range_for_cpu(rx_ring->dev,
1699 rx_buffer->dma,
1700 rx_buffer->page_offset,
1701 ixgbe_rx_bufsz(rx_ring),
1702 DMA_FROM_DEVICE);
1703 }
1704
1705 /* pull page into skb */
1706 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1707 le16_to_cpu(rx_desc->wb.upper.length));
1708
1709 if (ixgbe_can_reuse_page(rx_buffer)) {
1710 /* hand second half of page back to the ring */
1711 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1712 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1713 /* the page has been released from the ring */
1714 IXGBE_CB(skb)->page_released = true;
1715 } else {
1716 /* we are not reusing the buffer so unmap it */
1717 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1718 ixgbe_rx_pg_size(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721
1722 /* clear contents of buffer_info */
1723 rx_buffer->skb = NULL;
1724 rx_buffer->dma = 0;
1725 rx_buffer->page = NULL;
1726
1727 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1728
1729 cleaned_count++;
1730
1731 /* place incomplete frames back on ring for completion */
1732 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1733 continue;
1734
1735 /* verify the packet layout is correct */
1736 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1737 continue;
1738
1739 /* probably a little skewed due to removing CRC */
1740 total_rx_bytes += skb->len;
1741 total_rx_packets++;
1742
1743 /* populate checksum, timestamp, VLAN, and protocol */
1744 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1745
1746 #ifdef IXGBE_FCOE
1747 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1748 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1749 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1750 if (!ddp_bytes) {
1751 dev_kfree_skb_any(skb);
1752 continue;
1753 }
1754 }
1755
1756 #endif /* IXGBE_FCOE */
1757 ixgbe_rx_skb(q_vector, skb);
1758
1759 /* update budget accounting */
1760 budget--;
1761 } while (likely(budget));
1762
1763 #ifdef IXGBE_FCOE
1764 /* include DDPed FCoE data */
1765 if (ddp_bytes > 0) {
1766 unsigned int mss;
1767
1768 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1769 sizeof(struct fc_frame_header) -
1770 sizeof(struct fcoe_crc_eof);
1771 if (mss > 512)
1772 mss &= ~511;
1773 total_rx_bytes += ddp_bytes;
1774 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1775 }
1776
1777 #endif /* IXGBE_FCOE */
1778 u64_stats_update_begin(&rx_ring->syncp);
1779 rx_ring->stats.packets += total_rx_packets;
1780 rx_ring->stats.bytes += total_rx_bytes;
1781 u64_stats_update_end(&rx_ring->syncp);
1782 q_vector->rx.total_packets += total_rx_packets;
1783 q_vector->rx.total_bytes += total_rx_bytes;
1784
1785 if (cleaned_count)
1786 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1787
1788 return !!budget;
1789 }
1790
1791 /**
1792 * ixgbe_configure_msix - Configure MSI-X hardware
1793 * @adapter: board private structure
1794 *
1795 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1796 * interrupts.
1797 **/
1798 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1799 {
1800 struct ixgbe_q_vector *q_vector;
1801 int q_vectors, v_idx;
1802 u32 mask;
1803
1804 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1805
1806 /* Populate MSIX to EITR Select */
1807 if (adapter->num_vfs > 32) {
1808 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1809 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1810 }
1811
1812 /*
1813 * Populate the IVAR table and set the ITR values to the
1814 * corresponding register.
1815 */
1816 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1817 struct ixgbe_ring *ring;
1818 q_vector = adapter->q_vector[v_idx];
1819
1820 ixgbe_for_each_ring(ring, q_vector->rx)
1821 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1822
1823 ixgbe_for_each_ring(ring, q_vector->tx)
1824 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1825
1826 if (q_vector->tx.ring && !q_vector->rx.ring) {
1827 /* tx only vector */
1828 if (adapter->tx_itr_setting == 1)
1829 q_vector->itr = IXGBE_10K_ITR;
1830 else
1831 q_vector->itr = adapter->tx_itr_setting;
1832 } else {
1833 /* rx or rx/tx vector */
1834 if (adapter->rx_itr_setting == 1)
1835 q_vector->itr = IXGBE_20K_ITR;
1836 else
1837 q_vector->itr = adapter->rx_itr_setting;
1838 }
1839
1840 ixgbe_write_eitr(q_vector);
1841 }
1842
1843 switch (adapter->hw.mac.type) {
1844 case ixgbe_mac_82598EB:
1845 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1846 v_idx);
1847 break;
1848 case ixgbe_mac_82599EB:
1849 case ixgbe_mac_X540:
1850 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1851 break;
1852 default:
1853 break;
1854 }
1855 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1856
1857 /* set up to autoclear timer, and the vectors */
1858 mask = IXGBE_EIMS_ENABLE_MASK;
1859 mask &= ~(IXGBE_EIMS_OTHER |
1860 IXGBE_EIMS_MAILBOX |
1861 IXGBE_EIMS_LSC);
1862
1863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1864 }
1865
1866 enum latency_range {
1867 lowest_latency = 0,
1868 low_latency = 1,
1869 bulk_latency = 2,
1870 latency_invalid = 255
1871 };
1872
1873 /**
1874 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1875 * @q_vector: structure containing interrupt and ring information
1876 * @ring_container: structure containing ring performance data
1877 *
1878 * Stores a new ITR value based on packets and byte
1879 * counts during the last interrupt. The advantage of per interrupt
1880 * computation is faster updates and more accurate ITR for the current
1881 * traffic pattern. Constants in this function were computed
1882 * based on theoretical maximum wire speed and thresholds were set based
1883 * on testing data as well as attempting to minimize response time
1884 * while increasing bulk throughput.
1885 * this functionality is controlled by the InterruptThrottleRate module
1886 * parameter (see ixgbe_param.c)
1887 **/
1888 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1889 struct ixgbe_ring_container *ring_container)
1890 {
1891 int bytes = ring_container->total_bytes;
1892 int packets = ring_container->total_packets;
1893 u32 timepassed_us;
1894 u64 bytes_perint;
1895 u8 itr_setting = ring_container->itr;
1896
1897 if (packets == 0)
1898 return;
1899
1900 /* simple throttlerate management
1901 * 0-10MB/s lowest (100000 ints/s)
1902 * 10-20MB/s low (20000 ints/s)
1903 * 20-1249MB/s bulk (8000 ints/s)
1904 */
1905 /* what was last interrupt timeslice? */
1906 timepassed_us = q_vector->itr >> 2;
1907 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1908
1909 switch (itr_setting) {
1910 case lowest_latency:
1911 if (bytes_perint > 10)
1912 itr_setting = low_latency;
1913 break;
1914 case low_latency:
1915 if (bytes_perint > 20)
1916 itr_setting = bulk_latency;
1917 else if (bytes_perint <= 10)
1918 itr_setting = lowest_latency;
1919 break;
1920 case bulk_latency:
1921 if (bytes_perint <= 20)
1922 itr_setting = low_latency;
1923 break;
1924 }
1925
1926 /* clear work counters since we have the values we need */
1927 ring_container->total_bytes = 0;
1928 ring_container->total_packets = 0;
1929
1930 /* write updated itr to ring container */
1931 ring_container->itr = itr_setting;
1932 }
1933
1934 /**
1935 * ixgbe_write_eitr - write EITR register in hardware specific way
1936 * @q_vector: structure containing interrupt and ring information
1937 *
1938 * This function is made to be called by ethtool and by the driver
1939 * when it needs to update EITR registers at runtime. Hardware
1940 * specific quirks/differences are taken care of here.
1941 */
1942 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1943 {
1944 struct ixgbe_adapter *adapter = q_vector->adapter;
1945 struct ixgbe_hw *hw = &adapter->hw;
1946 int v_idx = q_vector->v_idx;
1947 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
1948
1949 switch (adapter->hw.mac.type) {
1950 case ixgbe_mac_82598EB:
1951 /* must write high and low 16 bits to reset counter */
1952 itr_reg |= (itr_reg << 16);
1953 break;
1954 case ixgbe_mac_82599EB:
1955 case ixgbe_mac_X540:
1956 /*
1957 * set the WDIS bit to not clear the timer bits and cause an
1958 * immediate assertion of the interrupt
1959 */
1960 itr_reg |= IXGBE_EITR_CNT_WDIS;
1961 break;
1962 default:
1963 break;
1964 }
1965 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1966 }
1967
1968 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1969 {
1970 u32 new_itr = q_vector->itr;
1971 u8 current_itr;
1972
1973 ixgbe_update_itr(q_vector, &q_vector->tx);
1974 ixgbe_update_itr(q_vector, &q_vector->rx);
1975
1976 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1977
1978 switch (current_itr) {
1979 /* counts and packets in update_itr are dependent on these numbers */
1980 case lowest_latency:
1981 new_itr = IXGBE_100K_ITR;
1982 break;
1983 case low_latency:
1984 new_itr = IXGBE_20K_ITR;
1985 break;
1986 case bulk_latency:
1987 new_itr = IXGBE_8K_ITR;
1988 break;
1989 default:
1990 break;
1991 }
1992
1993 if (new_itr != q_vector->itr) {
1994 /* do an exponential smoothing */
1995 new_itr = (10 * new_itr * q_vector->itr) /
1996 ((9 * new_itr) + q_vector->itr);
1997
1998 /* save the algorithm value here */
1999 q_vector->itr = new_itr;
2000
2001 ixgbe_write_eitr(q_vector);
2002 }
2003 }
2004
2005 /**
2006 * ixgbe_check_overtemp_subtask - check for over temperature
2007 * @adapter: pointer to adapter
2008 **/
2009 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2010 {
2011 struct ixgbe_hw *hw = &adapter->hw;
2012 u32 eicr = adapter->interrupt_event;
2013
2014 if (test_bit(__IXGBE_DOWN, &adapter->state))
2015 return;
2016
2017 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2018 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2019 return;
2020
2021 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2022
2023 switch (hw->device_id) {
2024 case IXGBE_DEV_ID_82599_T3_LOM:
2025 /*
2026 * Since the warning interrupt is for both ports
2027 * we don't have to check if:
2028 * - This interrupt wasn't for our port.
2029 * - We may have missed the interrupt so always have to
2030 * check if we got a LSC
2031 */
2032 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2033 !(eicr & IXGBE_EICR_LSC))
2034 return;
2035
2036 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2037 u32 autoneg;
2038 bool link_up = false;
2039
2040 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2041
2042 if (link_up)
2043 return;
2044 }
2045
2046 /* Check if this is not due to overtemp */
2047 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2048 return;
2049
2050 break;
2051 default:
2052 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2053 return;
2054 break;
2055 }
2056 e_crit(drv,
2057 "Network adapter has been stopped because it has over heated. "
2058 "Restart the computer. If the problem persists, "
2059 "power off the system and replace the adapter\n");
2060
2061 adapter->interrupt_event = 0;
2062 }
2063
2064 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2065 {
2066 struct ixgbe_hw *hw = &adapter->hw;
2067
2068 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2069 (eicr & IXGBE_EICR_GPI_SDP1)) {
2070 e_crit(probe, "Fan has stopped, replace the adapter\n");
2071 /* write to clear the interrupt */
2072 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2073 }
2074 }
2075
2076 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2077 {
2078 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2079 return;
2080
2081 switch (adapter->hw.mac.type) {
2082 case ixgbe_mac_82599EB:
2083 /*
2084 * Need to check link state so complete overtemp check
2085 * on service task
2086 */
2087 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2088 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2089 adapter->interrupt_event = eicr;
2090 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2091 ixgbe_service_event_schedule(adapter);
2092 return;
2093 }
2094 return;
2095 case ixgbe_mac_X540:
2096 if (!(eicr & IXGBE_EICR_TS))
2097 return;
2098 break;
2099 default:
2100 return;
2101 }
2102
2103 e_crit(drv,
2104 "Network adapter has been stopped because it has over heated. "
2105 "Restart the computer. If the problem persists, "
2106 "power off the system and replace the adapter\n");
2107 }
2108
2109 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2110 {
2111 struct ixgbe_hw *hw = &adapter->hw;
2112
2113 if (eicr & IXGBE_EICR_GPI_SDP2) {
2114 /* Clear the interrupt */
2115 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2116 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2117 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2118 ixgbe_service_event_schedule(adapter);
2119 }
2120 }
2121
2122 if (eicr & IXGBE_EICR_GPI_SDP1) {
2123 /* Clear the interrupt */
2124 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2125 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2126 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2127 ixgbe_service_event_schedule(adapter);
2128 }
2129 }
2130 }
2131
2132 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2133 {
2134 struct ixgbe_hw *hw = &adapter->hw;
2135
2136 adapter->lsc_int++;
2137 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2138 adapter->link_check_timeout = jiffies;
2139 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2140 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2141 IXGBE_WRITE_FLUSH(hw);
2142 ixgbe_service_event_schedule(adapter);
2143 }
2144 }
2145
2146 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2147 u64 qmask)
2148 {
2149 u32 mask;
2150 struct ixgbe_hw *hw = &adapter->hw;
2151
2152 switch (hw->mac.type) {
2153 case ixgbe_mac_82598EB:
2154 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2155 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2156 break;
2157 case ixgbe_mac_82599EB:
2158 case ixgbe_mac_X540:
2159 mask = (qmask & 0xFFFFFFFF);
2160 if (mask)
2161 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2162 mask = (qmask >> 32);
2163 if (mask)
2164 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2165 break;
2166 default:
2167 break;
2168 }
2169 /* skip the flush */
2170 }
2171
2172 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2173 u64 qmask)
2174 {
2175 u32 mask;
2176 struct ixgbe_hw *hw = &adapter->hw;
2177
2178 switch (hw->mac.type) {
2179 case ixgbe_mac_82598EB:
2180 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2181 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2182 break;
2183 case ixgbe_mac_82599EB:
2184 case ixgbe_mac_X540:
2185 mask = (qmask & 0xFFFFFFFF);
2186 if (mask)
2187 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2188 mask = (qmask >> 32);
2189 if (mask)
2190 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2191 break;
2192 default:
2193 break;
2194 }
2195 /* skip the flush */
2196 }
2197
2198 /**
2199 * ixgbe_irq_enable - Enable default interrupt generation settings
2200 * @adapter: board private structure
2201 **/
2202 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2203 bool flush)
2204 {
2205 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2206
2207 /* don't reenable LSC while waiting for link */
2208 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2209 mask &= ~IXGBE_EIMS_LSC;
2210
2211 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2212 switch (adapter->hw.mac.type) {
2213 case ixgbe_mac_82599EB:
2214 mask |= IXGBE_EIMS_GPI_SDP0;
2215 break;
2216 case ixgbe_mac_X540:
2217 mask |= IXGBE_EIMS_TS;
2218 break;
2219 default:
2220 break;
2221 }
2222 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2223 mask |= IXGBE_EIMS_GPI_SDP1;
2224 switch (adapter->hw.mac.type) {
2225 case ixgbe_mac_82599EB:
2226 mask |= IXGBE_EIMS_GPI_SDP1;
2227 mask |= IXGBE_EIMS_GPI_SDP2;
2228 case ixgbe_mac_X540:
2229 mask |= IXGBE_EIMS_ECC;
2230 mask |= IXGBE_EIMS_MAILBOX;
2231 break;
2232 default:
2233 break;
2234 }
2235 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2236 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2237 mask |= IXGBE_EIMS_FLOW_DIR;
2238
2239 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2240 if (queues)
2241 ixgbe_irq_enable_queues(adapter, ~0);
2242 if (flush)
2243 IXGBE_WRITE_FLUSH(&adapter->hw);
2244 }
2245
2246 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2247 {
2248 struct ixgbe_adapter *adapter = data;
2249 struct ixgbe_hw *hw = &adapter->hw;
2250 u32 eicr;
2251
2252 /*
2253 * Workaround for Silicon errata. Use clear-by-write instead
2254 * of clear-by-read. Reading with EICS will return the
2255 * interrupt causes without clearing, which later be done
2256 * with the write to EICR.
2257 */
2258 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2259 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2260
2261 if (eicr & IXGBE_EICR_LSC)
2262 ixgbe_check_lsc(adapter);
2263
2264 if (eicr & IXGBE_EICR_MAILBOX)
2265 ixgbe_msg_task(adapter);
2266
2267 switch (hw->mac.type) {
2268 case ixgbe_mac_82599EB:
2269 case ixgbe_mac_X540:
2270 if (eicr & IXGBE_EICR_ECC)
2271 e_info(link, "Received unrecoverable ECC Err, please "
2272 "reboot\n");
2273 /* Handle Flow Director Full threshold interrupt */
2274 if (eicr & IXGBE_EICR_FLOW_DIR) {
2275 int reinit_count = 0;
2276 int i;
2277 for (i = 0; i < adapter->num_tx_queues; i++) {
2278 struct ixgbe_ring *ring = adapter->tx_ring[i];
2279 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2280 &ring->state))
2281 reinit_count++;
2282 }
2283 if (reinit_count) {
2284 /* no more flow director interrupts until after init */
2285 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2286 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2287 ixgbe_service_event_schedule(adapter);
2288 }
2289 }
2290 ixgbe_check_sfp_event(adapter, eicr);
2291 ixgbe_check_overtemp_event(adapter, eicr);
2292 break;
2293 default:
2294 break;
2295 }
2296
2297 ixgbe_check_fan_failure(adapter, eicr);
2298
2299 /* re-enable the original interrupt state, no lsc, no queues */
2300 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2301 ixgbe_irq_enable(adapter, false, false);
2302
2303 return IRQ_HANDLED;
2304 }
2305
2306 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2307 {
2308 struct ixgbe_q_vector *q_vector = data;
2309
2310 /* EIAM disabled interrupts (on this vector) for us */
2311
2312 if (q_vector->rx.ring || q_vector->tx.ring)
2313 napi_schedule(&q_vector->napi);
2314
2315 return IRQ_HANDLED;
2316 }
2317
2318 /**
2319 * ixgbe_poll - NAPI Rx polling callback
2320 * @napi: structure for representing this polling device
2321 * @budget: how many packets driver is allowed to clean
2322 *
2323 * This function is used for legacy and MSI, NAPI mode
2324 **/
2325 int ixgbe_poll(struct napi_struct *napi, int budget)
2326 {
2327 struct ixgbe_q_vector *q_vector =
2328 container_of(napi, struct ixgbe_q_vector, napi);
2329 struct ixgbe_adapter *adapter = q_vector->adapter;
2330 struct ixgbe_ring *ring;
2331 int per_ring_budget;
2332 bool clean_complete = true;
2333
2334 #ifdef CONFIG_IXGBE_DCA
2335 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2336 ixgbe_update_dca(q_vector);
2337 #endif
2338
2339 ixgbe_for_each_ring(ring, q_vector->tx)
2340 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2341
2342 /* attempt to distribute budget to each queue fairly, but don't allow
2343 * the budget to go below 1 because we'll exit polling */
2344 if (q_vector->rx.count > 1)
2345 per_ring_budget = max(budget/q_vector->rx.count, 1);
2346 else
2347 per_ring_budget = budget;
2348
2349 ixgbe_for_each_ring(ring, q_vector->rx)
2350 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2351 per_ring_budget);
2352
2353 /* If all work not completed, return budget and keep polling */
2354 if (!clean_complete)
2355 return budget;
2356
2357 /* all work done, exit the polling mode */
2358 napi_complete(napi);
2359 if (adapter->rx_itr_setting & 1)
2360 ixgbe_set_itr(q_vector);
2361 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2362 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2363
2364 return 0;
2365 }
2366
2367 /**
2368 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2369 * @adapter: board private structure
2370 *
2371 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2372 * interrupts from the kernel.
2373 **/
2374 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2375 {
2376 struct net_device *netdev = adapter->netdev;
2377 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2378 int vector, err;
2379 int ri = 0, ti = 0;
2380
2381 for (vector = 0; vector < q_vectors; vector++) {
2382 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2383 struct msix_entry *entry = &adapter->msix_entries[vector];
2384
2385 if (q_vector->tx.ring && q_vector->rx.ring) {
2386 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2387 "%s-%s-%d", netdev->name, "TxRx", ri++);
2388 ti++;
2389 } else if (q_vector->rx.ring) {
2390 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2391 "%s-%s-%d", netdev->name, "rx", ri++);
2392 } else if (q_vector->tx.ring) {
2393 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2394 "%s-%s-%d", netdev->name, "tx", ti++);
2395 } else {
2396 /* skip this unused q_vector */
2397 continue;
2398 }
2399 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2400 q_vector->name, q_vector);
2401 if (err) {
2402 e_err(probe, "request_irq failed for MSIX interrupt "
2403 "Error: %d\n", err);
2404 goto free_queue_irqs;
2405 }
2406 /* If Flow Director is enabled, set interrupt affinity */
2407 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2408 /* assign the mask for this irq */
2409 irq_set_affinity_hint(entry->vector,
2410 &q_vector->affinity_mask);
2411 }
2412 }
2413
2414 err = request_irq(adapter->msix_entries[vector].vector,
2415 ixgbe_msix_other, 0, netdev->name, adapter);
2416 if (err) {
2417 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2418 goto free_queue_irqs;
2419 }
2420
2421 return 0;
2422
2423 free_queue_irqs:
2424 while (vector) {
2425 vector--;
2426 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2427 NULL);
2428 free_irq(adapter->msix_entries[vector].vector,
2429 adapter->q_vector[vector]);
2430 }
2431 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2432 pci_disable_msix(adapter->pdev);
2433 kfree(adapter->msix_entries);
2434 adapter->msix_entries = NULL;
2435 return err;
2436 }
2437
2438 /**
2439 * ixgbe_intr - legacy mode Interrupt Handler
2440 * @irq: interrupt number
2441 * @data: pointer to a network interface device structure
2442 **/
2443 static irqreturn_t ixgbe_intr(int irq, void *data)
2444 {
2445 struct ixgbe_adapter *adapter = data;
2446 struct ixgbe_hw *hw = &adapter->hw;
2447 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2448 u32 eicr;
2449
2450 /*
2451 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2452 * before the read of EICR.
2453 */
2454 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2455
2456 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2457 * therefore no explicit interrupt disable is necessary */
2458 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2459 if (!eicr) {
2460 /*
2461 * shared interrupt alert!
2462 * make sure interrupts are enabled because the read will
2463 * have disabled interrupts due to EIAM
2464 * finish the workaround of silicon errata on 82598. Unmask
2465 * the interrupt that we masked before the EICR read.
2466 */
2467 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2468 ixgbe_irq_enable(adapter, true, true);
2469 return IRQ_NONE; /* Not our interrupt */
2470 }
2471
2472 if (eicr & IXGBE_EICR_LSC)
2473 ixgbe_check_lsc(adapter);
2474
2475 switch (hw->mac.type) {
2476 case ixgbe_mac_82599EB:
2477 ixgbe_check_sfp_event(adapter, eicr);
2478 /* Fall through */
2479 case ixgbe_mac_X540:
2480 if (eicr & IXGBE_EICR_ECC)
2481 e_info(link, "Received unrecoverable ECC err, please "
2482 "reboot\n");
2483 ixgbe_check_overtemp_event(adapter, eicr);
2484 break;
2485 default:
2486 break;
2487 }
2488
2489 ixgbe_check_fan_failure(adapter, eicr);
2490
2491 /* would disable interrupts here but EIAM disabled it */
2492 napi_schedule(&q_vector->napi);
2493
2494 /*
2495 * re-enable link(maybe) and non-queue interrupts, no flush.
2496 * ixgbe_poll will re-enable the queue interrupts
2497 */
2498 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2499 ixgbe_irq_enable(adapter, false, false);
2500
2501 return IRQ_HANDLED;
2502 }
2503
2504 /**
2505 * ixgbe_request_irq - initialize interrupts
2506 * @adapter: board private structure
2507 *
2508 * Attempts to configure interrupts using the best available
2509 * capabilities of the hardware and kernel.
2510 **/
2511 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2512 {
2513 struct net_device *netdev = adapter->netdev;
2514 int err;
2515
2516 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2517 err = ixgbe_request_msix_irqs(adapter);
2518 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2519 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2520 netdev->name, adapter);
2521 else
2522 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2523 netdev->name, adapter);
2524
2525 if (err)
2526 e_err(probe, "request_irq failed, Error %d\n", err);
2527
2528 return err;
2529 }
2530
2531 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2532 {
2533 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2534 int i, q_vectors;
2535
2536 q_vectors = adapter->num_msix_vectors;
2537 i = q_vectors - 1;
2538 free_irq(adapter->msix_entries[i].vector, adapter);
2539 i--;
2540
2541 for (; i >= 0; i--) {
2542 /* free only the irqs that were actually requested */
2543 if (!adapter->q_vector[i]->rx.ring &&
2544 !adapter->q_vector[i]->tx.ring)
2545 continue;
2546
2547 /* clear the affinity_mask in the IRQ descriptor */
2548 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2549 NULL);
2550
2551 free_irq(adapter->msix_entries[i].vector,
2552 adapter->q_vector[i]);
2553 }
2554 } else {
2555 free_irq(adapter->pdev->irq, adapter);
2556 }
2557 }
2558
2559 /**
2560 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2561 * @adapter: board private structure
2562 **/
2563 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2564 {
2565 switch (adapter->hw.mac.type) {
2566 case ixgbe_mac_82598EB:
2567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2568 break;
2569 case ixgbe_mac_82599EB:
2570 case ixgbe_mac_X540:
2571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2572 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2574 break;
2575 default:
2576 break;
2577 }
2578 IXGBE_WRITE_FLUSH(&adapter->hw);
2579 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2580 int i;
2581 for (i = 0; i < adapter->num_msix_vectors; i++)
2582 synchronize_irq(adapter->msix_entries[i].vector);
2583 } else {
2584 synchronize_irq(adapter->pdev->irq);
2585 }
2586 }
2587
2588 /**
2589 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2590 *
2591 **/
2592 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2593 {
2594 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2595
2596 /* rx/tx vector */
2597 if (adapter->rx_itr_setting == 1)
2598 q_vector->itr = IXGBE_20K_ITR;
2599 else
2600 q_vector->itr = adapter->rx_itr_setting;
2601
2602 ixgbe_write_eitr(q_vector);
2603
2604 ixgbe_set_ivar(adapter, 0, 0, 0);
2605 ixgbe_set_ivar(adapter, 1, 0, 0);
2606
2607 e_info(hw, "Legacy interrupt IVAR setup done\n");
2608 }
2609
2610 /**
2611 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2612 * @adapter: board private structure
2613 * @ring: structure containing ring specific data
2614 *
2615 * Configure the Tx descriptor ring after a reset.
2616 **/
2617 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2618 struct ixgbe_ring *ring)
2619 {
2620 struct ixgbe_hw *hw = &adapter->hw;
2621 u64 tdba = ring->dma;
2622 int wait_loop = 10;
2623 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2624 u8 reg_idx = ring->reg_idx;
2625
2626 /* disable queue to avoid issues while updating state */
2627 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2628 IXGBE_WRITE_FLUSH(hw);
2629
2630 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2631 (tdba & DMA_BIT_MASK(32)));
2632 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2633 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2634 ring->count * sizeof(union ixgbe_adv_tx_desc));
2635 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2636 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2637 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2638
2639 /*
2640 * set WTHRESH to encourage burst writeback, it should not be set
2641 * higher than 1 when ITR is 0 as it could cause false TX hangs
2642 *
2643 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2644 * to or less than the number of on chip descriptors, which is
2645 * currently 40.
2646 */
2647 if (!ring->q_vector || (ring->q_vector->itr < 8))
2648 txdctl |= (1 << 16); /* WTHRESH = 1 */
2649 else
2650 txdctl |= (8 << 16); /* WTHRESH = 8 */
2651
2652 /*
2653 * Setting PTHRESH to 32 both improves performance
2654 * and avoids a TX hang with DFP enabled
2655 */
2656 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2657 32; /* PTHRESH = 32 */
2658
2659 /* reinitialize flowdirector state */
2660 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2661 adapter->atr_sample_rate) {
2662 ring->atr_sample_rate = adapter->atr_sample_rate;
2663 ring->atr_count = 0;
2664 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2665 } else {
2666 ring->atr_sample_rate = 0;
2667 }
2668
2669 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2670
2671 /* enable queue */
2672 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2673
2674 netdev_tx_reset_queue(txring_txq(ring));
2675
2676 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2677 if (hw->mac.type == ixgbe_mac_82598EB &&
2678 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2679 return;
2680
2681 /* poll to verify queue is enabled */
2682 do {
2683 usleep_range(1000, 2000);
2684 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2685 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2686 if (!wait_loop)
2687 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2688 }
2689
2690 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2691 {
2692 struct ixgbe_hw *hw = &adapter->hw;
2693 u32 rttdcs;
2694 u32 reg;
2695 u8 tcs = netdev_get_num_tc(adapter->netdev);
2696
2697 if (hw->mac.type == ixgbe_mac_82598EB)
2698 return;
2699
2700 /* disable the arbiter while setting MTQC */
2701 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2702 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2703 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2704
2705 /* set transmit pool layout */
2706 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2707 case (IXGBE_FLAG_SRIOV_ENABLED):
2708 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2709 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2710 break;
2711 default:
2712 if (!tcs)
2713 reg = IXGBE_MTQC_64Q_1PB;
2714 else if (tcs <= 4)
2715 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2716 else
2717 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2718
2719 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2720
2721 /* Enable Security TX Buffer IFG for multiple pb */
2722 if (tcs) {
2723 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2724 reg |= IXGBE_SECTX_DCB;
2725 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2726 }
2727 break;
2728 }
2729
2730 /* re-enable the arbiter */
2731 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2732 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2733 }
2734
2735 /**
2736 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2737 * @adapter: board private structure
2738 *
2739 * Configure the Tx unit of the MAC after a reset.
2740 **/
2741 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2742 {
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 u32 dmatxctl;
2745 u32 i;
2746
2747 ixgbe_setup_mtqc(adapter);
2748
2749 if (hw->mac.type != ixgbe_mac_82598EB) {
2750 /* DMATXCTL.EN must be before Tx queues are enabled */
2751 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2752 dmatxctl |= IXGBE_DMATXCTL_TE;
2753 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2754 }
2755
2756 /* Setup the HW Tx Head and Tail descriptor pointers */
2757 for (i = 0; i < adapter->num_tx_queues; i++)
2758 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2759 }
2760
2761 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2762
2763 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2764 struct ixgbe_ring *rx_ring)
2765 {
2766 u32 srrctl;
2767 u8 reg_idx = rx_ring->reg_idx;
2768
2769 switch (adapter->hw.mac.type) {
2770 case ixgbe_mac_82598EB: {
2771 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2772 const int mask = feature[RING_F_RSS].mask;
2773 reg_idx = reg_idx & mask;
2774 }
2775 break;
2776 case ixgbe_mac_82599EB:
2777 case ixgbe_mac_X540:
2778 default:
2779 break;
2780 }
2781
2782 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2783
2784 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2785 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2786 if (adapter->num_vfs)
2787 srrctl |= IXGBE_SRRCTL_DROP_EN;
2788
2789 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2790 IXGBE_SRRCTL_BSIZEHDR_MASK;
2791
2792 #if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2793 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2794 #else
2795 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2796 #endif
2797 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2798
2799 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2800 }
2801
2802 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2803 {
2804 struct ixgbe_hw *hw = &adapter->hw;
2805 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2806 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2807 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2808 u32 mrqc = 0, reta = 0;
2809 u32 rxcsum;
2810 int i, j;
2811 u8 tcs = netdev_get_num_tc(adapter->netdev);
2812 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2813
2814 if (tcs)
2815 maxq = min(maxq, adapter->num_tx_queues / tcs);
2816
2817 /* Fill out hash function seeds */
2818 for (i = 0; i < 10; i++)
2819 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2820
2821 /* Fill out redirection table */
2822 for (i = 0, j = 0; i < 128; i++, j++) {
2823 if (j == maxq)
2824 j = 0;
2825 /* reta = 4-byte sliding window of
2826 * 0x00..(indices-1)(indices-1)00..etc. */
2827 reta = (reta << 8) | (j * 0x11);
2828 if ((i & 3) == 3)
2829 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2830 }
2831
2832 /* Disable indicating checksum in descriptor, enables RSS hash */
2833 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2834 rxcsum |= IXGBE_RXCSUM_PCSD;
2835 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2836
2837 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2838 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2839 mrqc = IXGBE_MRQC_RSSEN;
2840 } else {
2841 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2842 | IXGBE_FLAG_SRIOV_ENABLED);
2843
2844 switch (mask) {
2845 case (IXGBE_FLAG_RSS_ENABLED):
2846 if (!tcs)
2847 mrqc = IXGBE_MRQC_RSSEN;
2848 else if (tcs <= 4)
2849 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2850 else
2851 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2852 break;
2853 case (IXGBE_FLAG_SRIOV_ENABLED):
2854 mrqc = IXGBE_MRQC_VMDQEN;
2855 break;
2856 default:
2857 break;
2858 }
2859 }
2860
2861 /* Perform hash on these packet types */
2862 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2863 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2864 | IXGBE_MRQC_RSS_FIELD_IPV6
2865 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2866
2867 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2868 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2869 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2870 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2871
2872 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2873 }
2874
2875 /**
2876 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2877 * @adapter: address of board private structure
2878 * @index: index of ring to set
2879 **/
2880 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2881 struct ixgbe_ring *ring)
2882 {
2883 struct ixgbe_hw *hw = &adapter->hw;
2884 u32 rscctrl;
2885 u8 reg_idx = ring->reg_idx;
2886
2887 if (!ring_is_rsc_enabled(ring))
2888 return;
2889
2890 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2891 rscctrl |= IXGBE_RSCCTL_RSCEN;
2892 /*
2893 * we must limit the number of descriptors so that the
2894 * total size of max desc * buf_len is not greater
2895 * than 65536
2896 */
2897 #if (PAGE_SIZE <= 8192)
2898 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2899 #elif (PAGE_SIZE <= 16384)
2900 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2901 #else
2902 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2903 #endif
2904 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2905 }
2906
2907 #define IXGBE_MAX_RX_DESC_POLL 10
2908 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2909 struct ixgbe_ring *ring)
2910 {
2911 struct ixgbe_hw *hw = &adapter->hw;
2912 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2913 u32 rxdctl;
2914 u8 reg_idx = ring->reg_idx;
2915
2916 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2917 if (hw->mac.type == ixgbe_mac_82598EB &&
2918 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2919 return;
2920
2921 do {
2922 usleep_range(1000, 2000);
2923 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2924 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2925
2926 if (!wait_loop) {
2927 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2928 "the polling period\n", reg_idx);
2929 }
2930 }
2931
2932 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2933 struct ixgbe_ring *ring)
2934 {
2935 struct ixgbe_hw *hw = &adapter->hw;
2936 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2937 u32 rxdctl;
2938 u8 reg_idx = ring->reg_idx;
2939
2940 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2941 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2942
2943 /* write value back with RXDCTL.ENABLE bit cleared */
2944 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2945
2946 if (hw->mac.type == ixgbe_mac_82598EB &&
2947 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2948 return;
2949
2950 /* the hardware may take up to 100us to really disable the rx queue */
2951 do {
2952 udelay(10);
2953 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2954 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2955
2956 if (!wait_loop) {
2957 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2958 "the polling period\n", reg_idx);
2959 }
2960 }
2961
2962 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2963 struct ixgbe_ring *ring)
2964 {
2965 struct ixgbe_hw *hw = &adapter->hw;
2966 u64 rdba = ring->dma;
2967 u32 rxdctl;
2968 u8 reg_idx = ring->reg_idx;
2969
2970 /* disable queue to avoid issues while updating state */
2971 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2972 ixgbe_disable_rx_queue(adapter, ring);
2973
2974 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2975 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2976 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2977 ring->count * sizeof(union ixgbe_adv_rx_desc));
2978 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2979 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2980 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2981
2982 ixgbe_configure_srrctl(adapter, ring);
2983 ixgbe_configure_rscctl(adapter, ring);
2984
2985 /* If operating in IOV mode set RLPML for X540 */
2986 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2987 hw->mac.type == ixgbe_mac_X540) {
2988 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2989 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2990 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2991 }
2992
2993 if (hw->mac.type == ixgbe_mac_82598EB) {
2994 /*
2995 * enable cache line friendly hardware writes:
2996 * PTHRESH=32 descriptors (half the internal cache),
2997 * this also removes ugly rx_no_buffer_count increment
2998 * HTHRESH=4 descriptors (to minimize latency on fetch)
2999 * WTHRESH=8 burst writeback up to two cache lines
3000 */
3001 rxdctl &= ~0x3FFFFF;
3002 rxdctl |= 0x080420;
3003 }
3004
3005 /* enable receive descriptor ring */
3006 rxdctl |= IXGBE_RXDCTL_ENABLE;
3007 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3008
3009 ixgbe_rx_desc_queue_enable(adapter, ring);
3010 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3011 }
3012
3013 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3014 {
3015 struct ixgbe_hw *hw = &adapter->hw;
3016 int p;
3017
3018 /* PSRTYPE must be initialized in non 82598 adapters */
3019 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3020 IXGBE_PSRTYPE_UDPHDR |
3021 IXGBE_PSRTYPE_IPV4HDR |
3022 IXGBE_PSRTYPE_L2HDR |
3023 IXGBE_PSRTYPE_IPV6HDR;
3024
3025 if (hw->mac.type == ixgbe_mac_82598EB)
3026 return;
3027
3028 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3029 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3030
3031 for (p = 0; p < adapter->num_rx_pools; p++)
3032 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3033 psrtype);
3034 }
3035
3036 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3037 {
3038 struct ixgbe_hw *hw = &adapter->hw;
3039 u32 gcr_ext;
3040 u32 vt_reg_bits;
3041 u32 reg_offset, vf_shift;
3042 u32 vmdctl;
3043 int i;
3044
3045 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3046 return;
3047
3048 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3049 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3050 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3051 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3052
3053 vf_shift = adapter->num_vfs % 32;
3054 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3055
3056 /* Enable only the PF's pool for Tx/Rx */
3057 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3058 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3059 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3060 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3061 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3062
3063 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3064 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3065
3066 /*
3067 * Set up VF register offsets for selected VT Mode,
3068 * i.e. 32 or 64 VFs for SR-IOV
3069 */
3070 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3071 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3072 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3073 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3074
3075 /* enable Tx loopback for VF/PF communication */
3076 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3077 /* Enable MAC Anti-Spoofing */
3078 hw->mac.ops.set_mac_anti_spoofing(hw,
3079 (adapter->num_vfs != 0),
3080 adapter->num_vfs);
3081 /* For VFs that have spoof checking turned off */
3082 for (i = 0; i < adapter->num_vfs; i++) {
3083 if (!adapter->vfinfo[i].spoofchk_enabled)
3084 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3085 }
3086 }
3087
3088 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3089 {
3090 struct ixgbe_hw *hw = &adapter->hw;
3091 struct net_device *netdev = adapter->netdev;
3092 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3093 struct ixgbe_ring *rx_ring;
3094 int i;
3095 u32 mhadd, hlreg0;
3096
3097 #ifdef IXGBE_FCOE
3098 /* adjust max frame to be able to do baby jumbo for FCoE */
3099 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3100 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3101 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3102
3103 #endif /* IXGBE_FCOE */
3104 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3105 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3106 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3107 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3108
3109 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3110 }
3111
3112 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3113 max_frame += VLAN_HLEN;
3114
3115 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3116 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3117 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3118 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3119
3120 /*
3121 * Setup the HW Rx Head and Tail Descriptor Pointers and
3122 * the Base and Length of the Rx Descriptor Ring
3123 */
3124 for (i = 0; i < adapter->num_rx_queues; i++) {
3125 rx_ring = adapter->rx_ring[i];
3126 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3127 set_ring_rsc_enabled(rx_ring);
3128 else
3129 clear_ring_rsc_enabled(rx_ring);
3130 #ifdef IXGBE_FCOE
3131 if (netdev->features & NETIF_F_FCOE_MTU) {
3132 struct ixgbe_ring_feature *f;
3133 f = &adapter->ring_feature[RING_F_FCOE];
3134 if ((i >= f->mask) && (i < f->mask + f->indices))
3135 set_bit(__IXGBE_RX_FCOE_BUFSZ, &rx_ring->state);
3136 }
3137 #endif /* IXGBE_FCOE */
3138 }
3139 }
3140
3141 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3142 {
3143 struct ixgbe_hw *hw = &adapter->hw;
3144 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3145
3146 switch (hw->mac.type) {
3147 case ixgbe_mac_82598EB:
3148 /*
3149 * For VMDq support of different descriptor types or
3150 * buffer sizes through the use of multiple SRRCTL
3151 * registers, RDRXCTL.MVMEN must be set to 1
3152 *
3153 * also, the manual doesn't mention it clearly but DCA hints
3154 * will only use queue 0's tags unless this bit is set. Side
3155 * effects of setting this bit are only that SRRCTL must be
3156 * fully programmed [0..15]
3157 */
3158 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3159 break;
3160 case ixgbe_mac_82599EB:
3161 case ixgbe_mac_X540:
3162 /* Disable RSC for ACK packets */
3163 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3164 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3165 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3166 /* hardware requires some bits to be set by default */
3167 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3168 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3169 break;
3170 default:
3171 /* We should do nothing since we don't know this hardware */
3172 return;
3173 }
3174
3175 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3176 }
3177
3178 /**
3179 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3180 * @adapter: board private structure
3181 *
3182 * Configure the Rx unit of the MAC after a reset.
3183 **/
3184 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3185 {
3186 struct ixgbe_hw *hw = &adapter->hw;
3187 int i;
3188 u32 rxctrl;
3189
3190 /* disable receives while setting up the descriptors */
3191 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3192 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3193
3194 ixgbe_setup_psrtype(adapter);
3195 ixgbe_setup_rdrxctl(adapter);
3196
3197 /* Program registers for the distribution of queues */
3198 ixgbe_setup_mrqc(adapter);
3199
3200 /* set_rx_buffer_len must be called before ring initialization */
3201 ixgbe_set_rx_buffer_len(adapter);
3202
3203 /*
3204 * Setup the HW Rx Head and Tail Descriptor Pointers and
3205 * the Base and Length of the Rx Descriptor Ring
3206 */
3207 for (i = 0; i < adapter->num_rx_queues; i++)
3208 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3209
3210 /* disable drop enable for 82598 parts */
3211 if (hw->mac.type == ixgbe_mac_82598EB)
3212 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3213
3214 /* enable all receives */
3215 rxctrl |= IXGBE_RXCTRL_RXEN;
3216 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3217 }
3218
3219 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3220 {
3221 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3222 struct ixgbe_hw *hw = &adapter->hw;
3223 int pool_ndx = adapter->num_vfs;
3224
3225 /* add VID to filter table */
3226 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3227 set_bit(vid, adapter->active_vlans);
3228
3229 return 0;
3230 }
3231
3232 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3233 {
3234 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3235 struct ixgbe_hw *hw = &adapter->hw;
3236 int pool_ndx = adapter->num_vfs;
3237
3238 /* remove VID from filter table */
3239 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3240 clear_bit(vid, adapter->active_vlans);
3241
3242 return 0;
3243 }
3244
3245 /**
3246 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3247 * @adapter: driver data
3248 */
3249 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3250 {
3251 struct ixgbe_hw *hw = &adapter->hw;
3252 u32 vlnctrl;
3253
3254 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3255 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3256 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3257 }
3258
3259 /**
3260 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3261 * @adapter: driver data
3262 */
3263 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3264 {
3265 struct ixgbe_hw *hw = &adapter->hw;
3266 u32 vlnctrl;
3267
3268 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3269 vlnctrl |= IXGBE_VLNCTRL_VFE;
3270 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3271 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3272 }
3273
3274 /**
3275 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3276 * @adapter: driver data
3277 */
3278 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3279 {
3280 struct ixgbe_hw *hw = &adapter->hw;
3281 u32 vlnctrl;
3282 int i, j;
3283
3284 switch (hw->mac.type) {
3285 case ixgbe_mac_82598EB:
3286 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3287 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3288 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3289 break;
3290 case ixgbe_mac_82599EB:
3291 case ixgbe_mac_X540:
3292 for (i = 0; i < adapter->num_rx_queues; i++) {
3293 j = adapter->rx_ring[i]->reg_idx;
3294 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3295 vlnctrl &= ~IXGBE_RXDCTL_VME;
3296 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3297 }
3298 break;
3299 default:
3300 break;
3301 }
3302 }
3303
3304 /**
3305 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3306 * @adapter: driver data
3307 */
3308 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3309 {
3310 struct ixgbe_hw *hw = &adapter->hw;
3311 u32 vlnctrl;
3312 int i, j;
3313
3314 switch (hw->mac.type) {
3315 case ixgbe_mac_82598EB:
3316 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3317 vlnctrl |= IXGBE_VLNCTRL_VME;
3318 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3319 break;
3320 case ixgbe_mac_82599EB:
3321 case ixgbe_mac_X540:
3322 for (i = 0; i < adapter->num_rx_queues; i++) {
3323 j = adapter->rx_ring[i]->reg_idx;
3324 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3325 vlnctrl |= IXGBE_RXDCTL_VME;
3326 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3327 }
3328 break;
3329 default:
3330 break;
3331 }
3332 }
3333
3334 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3335 {
3336 u16 vid;
3337
3338 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3339
3340 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3341 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3342 }
3343
3344 /**
3345 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3346 * @netdev: network interface device structure
3347 *
3348 * Writes unicast address list to the RAR table.
3349 * Returns: -ENOMEM on failure/insufficient address space
3350 * 0 on no addresses written
3351 * X on writing X addresses to the RAR table
3352 **/
3353 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3354 {
3355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3356 struct ixgbe_hw *hw = &adapter->hw;
3357 unsigned int vfn = adapter->num_vfs;
3358 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3359 int count = 0;
3360
3361 /* return ENOMEM indicating insufficient memory for addresses */
3362 if (netdev_uc_count(netdev) > rar_entries)
3363 return -ENOMEM;
3364
3365 if (!netdev_uc_empty(netdev) && rar_entries) {
3366 struct netdev_hw_addr *ha;
3367 /* return error if we do not support writing to RAR table */
3368 if (!hw->mac.ops.set_rar)
3369 return -ENOMEM;
3370
3371 netdev_for_each_uc_addr(ha, netdev) {
3372 if (!rar_entries)
3373 break;
3374 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3375 vfn, IXGBE_RAH_AV);
3376 count++;
3377 }
3378 }
3379 /* write the addresses in reverse order to avoid write combining */
3380 for (; rar_entries > 0 ; rar_entries--)
3381 hw->mac.ops.clear_rar(hw, rar_entries);
3382
3383 return count;
3384 }
3385
3386 /**
3387 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3388 * @netdev: network interface device structure
3389 *
3390 * The set_rx_method entry point is called whenever the unicast/multicast
3391 * address list or the network interface flags are updated. This routine is
3392 * responsible for configuring the hardware for proper unicast, multicast and
3393 * promiscuous mode.
3394 **/
3395 void ixgbe_set_rx_mode(struct net_device *netdev)
3396 {
3397 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3398 struct ixgbe_hw *hw = &adapter->hw;
3399 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3400 int count;
3401
3402 /* Check for Promiscuous and All Multicast modes */
3403
3404 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3405
3406 /* set all bits that we expect to always be set */
3407 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3408 fctrl |= IXGBE_FCTRL_BAM;
3409 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3410 fctrl |= IXGBE_FCTRL_PMCF;
3411
3412 /* clear the bits we are changing the status of */
3413 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3414
3415 if (netdev->flags & IFF_PROMISC) {
3416 hw->addr_ctrl.user_set_promisc = true;
3417 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3418 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3419 /* don't hardware filter vlans in promisc mode */
3420 ixgbe_vlan_filter_disable(adapter);
3421 } else {
3422 if (netdev->flags & IFF_ALLMULTI) {
3423 fctrl |= IXGBE_FCTRL_MPE;
3424 vmolr |= IXGBE_VMOLR_MPE;
3425 } else {
3426 /*
3427 * Write addresses to the MTA, if the attempt fails
3428 * then we should just turn on promiscuous mode so
3429 * that we can at least receive multicast traffic
3430 */
3431 hw->mac.ops.update_mc_addr_list(hw, netdev);
3432 vmolr |= IXGBE_VMOLR_ROMPE;
3433 }
3434 ixgbe_vlan_filter_enable(adapter);
3435 hw->addr_ctrl.user_set_promisc = false;
3436 }
3437
3438 /*
3439 * Write addresses to available RAR registers, if there is not
3440 * sufficient space to store all the addresses then enable
3441 * unicast promiscuous mode
3442 */
3443 count = ixgbe_write_uc_addr_list(netdev);
3444 if (count < 0) {
3445 fctrl |= IXGBE_FCTRL_UPE;
3446 vmolr |= IXGBE_VMOLR_ROPE;
3447 }
3448
3449 if (adapter->num_vfs) {
3450 ixgbe_restore_vf_multicasts(adapter);
3451 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3452 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3453 IXGBE_VMOLR_ROPE);
3454 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3455 }
3456
3457 /* This is useful for sniffing bad packets. */
3458 if (adapter->netdev->features & NETIF_F_RXALL) {
3459 /* UPE and MPE will be handled by normal PROMISC logic
3460 * in e1000e_set_rx_mode */
3461 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3462 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3463 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3464
3465 fctrl &= ~(IXGBE_FCTRL_DPF);
3466 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3467 }
3468
3469 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3470
3471 if (netdev->features & NETIF_F_HW_VLAN_RX)
3472 ixgbe_vlan_strip_enable(adapter);
3473 else
3474 ixgbe_vlan_strip_disable(adapter);
3475 }
3476
3477 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3478 {
3479 int q_idx;
3480 struct ixgbe_q_vector *q_vector;
3481 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3482
3483 /* legacy and MSI only use one vector */
3484 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3485 q_vectors = 1;
3486
3487 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3488 q_vector = adapter->q_vector[q_idx];
3489 napi_enable(&q_vector->napi);
3490 }
3491 }
3492
3493 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3494 {
3495 int q_idx;
3496 struct ixgbe_q_vector *q_vector;
3497 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3498
3499 /* legacy and MSI only use one vector */
3500 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3501 q_vectors = 1;
3502
3503 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3504 q_vector = adapter->q_vector[q_idx];
3505 napi_disable(&q_vector->napi);
3506 }
3507 }
3508
3509 #ifdef CONFIG_IXGBE_DCB
3510 /*
3511 * ixgbe_configure_dcb - Configure DCB hardware
3512 * @adapter: ixgbe adapter struct
3513 *
3514 * This is called by the driver on open to configure the DCB hardware.
3515 * This is also called by the gennetlink interface when reconfiguring
3516 * the DCB state.
3517 */
3518 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3519 {
3520 struct ixgbe_hw *hw = &adapter->hw;
3521 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3522
3523 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3524 if (hw->mac.type == ixgbe_mac_82598EB)
3525 netif_set_gso_max_size(adapter->netdev, 65536);
3526 return;
3527 }
3528
3529 if (hw->mac.type == ixgbe_mac_82598EB)
3530 netif_set_gso_max_size(adapter->netdev, 32768);
3531
3532
3533 /* Enable VLAN tag insert/strip */
3534 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3535
3536 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3537
3538 #ifdef IXGBE_FCOE
3539 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3540 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3541 #endif
3542
3543 /* reconfigure the hardware */
3544 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3545 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3546 DCB_TX_CONFIG);
3547 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3548 DCB_RX_CONFIG);
3549 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3550 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3551 ixgbe_dcb_hw_ets(&adapter->hw,
3552 adapter->ixgbe_ieee_ets,
3553 max_frame);
3554 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3555 adapter->ixgbe_ieee_pfc->pfc_en,
3556 adapter->ixgbe_ieee_ets->prio_tc);
3557 }
3558
3559 /* Enable RSS Hash per TC */
3560 if (hw->mac.type != ixgbe_mac_82598EB) {
3561 int i;
3562 u32 reg = 0;
3563
3564 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3565 u8 msb = 0;
3566 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3567
3568 while (cnt >>= 1)
3569 msb++;
3570
3571 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3572 }
3573 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3574 }
3575 }
3576 #endif
3577
3578 /* Additional bittime to account for IXGBE framing */
3579 #define IXGBE_ETH_FRAMING 20
3580
3581 /*
3582 * ixgbe_hpbthresh - calculate high water mark for flow control
3583 *
3584 * @adapter: board private structure to calculate for
3585 * @pb - packet buffer to calculate
3586 */
3587 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3588 {
3589 struct ixgbe_hw *hw = &adapter->hw;
3590 struct net_device *dev = adapter->netdev;
3591 int link, tc, kb, marker;
3592 u32 dv_id, rx_pba;
3593
3594 /* Calculate max LAN frame size */
3595 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3596
3597 #ifdef IXGBE_FCOE
3598 /* FCoE traffic class uses FCOE jumbo frames */
3599 if (dev->features & NETIF_F_FCOE_MTU) {
3600 int fcoe_pb = 0;
3601
3602 #ifdef CONFIG_IXGBE_DCB
3603 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3604
3605 #endif
3606 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3607 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3608 }
3609 #endif
3610
3611 /* Calculate delay value for device */
3612 switch (hw->mac.type) {
3613 case ixgbe_mac_X540:
3614 dv_id = IXGBE_DV_X540(link, tc);
3615 break;
3616 default:
3617 dv_id = IXGBE_DV(link, tc);
3618 break;
3619 }
3620
3621 /* Loopback switch introduces additional latency */
3622 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3623 dv_id += IXGBE_B2BT(tc);
3624
3625 /* Delay value is calculated in bit times convert to KB */
3626 kb = IXGBE_BT2KB(dv_id);
3627 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3628
3629 marker = rx_pba - kb;
3630
3631 /* It is possible that the packet buffer is not large enough
3632 * to provide required headroom. In this case throw an error
3633 * to user and a do the best we can.
3634 */
3635 if (marker < 0) {
3636 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3637 "headroom to support flow control."
3638 "Decrease MTU or number of traffic classes\n", pb);
3639 marker = tc + 1;
3640 }
3641
3642 return marker;
3643 }
3644
3645 /*
3646 * ixgbe_lpbthresh - calculate low water mark for for flow control
3647 *
3648 * @adapter: board private structure to calculate for
3649 * @pb - packet buffer to calculate
3650 */
3651 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3652 {
3653 struct ixgbe_hw *hw = &adapter->hw;
3654 struct net_device *dev = adapter->netdev;
3655 int tc;
3656 u32 dv_id;
3657
3658 /* Calculate max LAN frame size */
3659 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3660
3661 /* Calculate delay value for device */
3662 switch (hw->mac.type) {
3663 case ixgbe_mac_X540:
3664 dv_id = IXGBE_LOW_DV_X540(tc);
3665 break;
3666 default:
3667 dv_id = IXGBE_LOW_DV(tc);
3668 break;
3669 }
3670
3671 /* Delay value is calculated in bit times convert to KB */
3672 return IXGBE_BT2KB(dv_id);
3673 }
3674
3675 /*
3676 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3677 */
3678 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3679 {
3680 struct ixgbe_hw *hw = &adapter->hw;
3681 int num_tc = netdev_get_num_tc(adapter->netdev);
3682 int i;
3683
3684 if (!num_tc)
3685 num_tc = 1;
3686
3687 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3688
3689 for (i = 0; i < num_tc; i++) {
3690 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3691
3692 /* Low water marks must not be larger than high water marks */
3693 if (hw->fc.low_water > hw->fc.high_water[i])
3694 hw->fc.low_water = 0;
3695 }
3696 }
3697
3698 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3699 {
3700 struct ixgbe_hw *hw = &adapter->hw;
3701 int hdrm;
3702 u8 tc = netdev_get_num_tc(adapter->netdev);
3703
3704 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3705 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3706 hdrm = 32 << adapter->fdir_pballoc;
3707 else
3708 hdrm = 0;
3709
3710 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3711 ixgbe_pbthresh_setup(adapter);
3712 }
3713
3714 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3715 {
3716 struct ixgbe_hw *hw = &adapter->hw;
3717 struct hlist_node *node, *node2;
3718 struct ixgbe_fdir_filter *filter;
3719
3720 spin_lock(&adapter->fdir_perfect_lock);
3721
3722 if (!hlist_empty(&adapter->fdir_filter_list))
3723 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3724
3725 hlist_for_each_entry_safe(filter, node, node2,
3726 &adapter->fdir_filter_list, fdir_node) {
3727 ixgbe_fdir_write_perfect_filter_82599(hw,
3728 &filter->filter,
3729 filter->sw_idx,
3730 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3731 IXGBE_FDIR_DROP_QUEUE :
3732 adapter->rx_ring[filter->action]->reg_idx);
3733 }
3734
3735 spin_unlock(&adapter->fdir_perfect_lock);
3736 }
3737
3738 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3739 {
3740 struct ixgbe_hw *hw = &adapter->hw;
3741
3742 ixgbe_configure_pb(adapter);
3743 #ifdef CONFIG_IXGBE_DCB
3744 ixgbe_configure_dcb(adapter);
3745 #endif
3746
3747 ixgbe_set_rx_mode(adapter->netdev);
3748 ixgbe_restore_vlan(adapter);
3749
3750 #ifdef IXGBE_FCOE
3751 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3752 ixgbe_configure_fcoe(adapter);
3753
3754 #endif /* IXGBE_FCOE */
3755
3756 switch (hw->mac.type) {
3757 case ixgbe_mac_82599EB:
3758 case ixgbe_mac_X540:
3759 hw->mac.ops.disable_rx_buff(hw);
3760 break;
3761 default:
3762 break;
3763 }
3764
3765 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3766 ixgbe_init_fdir_signature_82599(&adapter->hw,
3767 adapter->fdir_pballoc);
3768 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3769 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3770 adapter->fdir_pballoc);
3771 ixgbe_fdir_filter_restore(adapter);
3772 }
3773
3774 switch (hw->mac.type) {
3775 case ixgbe_mac_82599EB:
3776 case ixgbe_mac_X540:
3777 hw->mac.ops.enable_rx_buff(hw);
3778 break;
3779 default:
3780 break;
3781 }
3782
3783 ixgbe_configure_virtualization(adapter);
3784
3785 ixgbe_configure_tx(adapter);
3786 ixgbe_configure_rx(adapter);
3787 }
3788
3789 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3790 {
3791 switch (hw->phy.type) {
3792 case ixgbe_phy_sfp_avago:
3793 case ixgbe_phy_sfp_ftl:
3794 case ixgbe_phy_sfp_intel:
3795 case ixgbe_phy_sfp_unknown:
3796 case ixgbe_phy_sfp_passive_tyco:
3797 case ixgbe_phy_sfp_passive_unknown:
3798 case ixgbe_phy_sfp_active_unknown:
3799 case ixgbe_phy_sfp_ftl_active:
3800 return true;
3801 case ixgbe_phy_nl:
3802 if (hw->mac.type == ixgbe_mac_82598EB)
3803 return true;
3804 default:
3805 return false;
3806 }
3807 }
3808
3809 /**
3810 * ixgbe_sfp_link_config - set up SFP+ link
3811 * @adapter: pointer to private adapter struct
3812 **/
3813 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3814 {
3815 /*
3816 * We are assuming the worst case scenario here, and that
3817 * is that an SFP was inserted/removed after the reset
3818 * but before SFP detection was enabled. As such the best
3819 * solution is to just start searching as soon as we start
3820 */
3821 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3822 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3823
3824 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3825 }
3826
3827 /**
3828 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3829 * @hw: pointer to private hardware struct
3830 *
3831 * Returns 0 on success, negative on failure
3832 **/
3833 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3834 {
3835 u32 autoneg;
3836 bool negotiation, link_up = false;
3837 u32 ret = IXGBE_ERR_LINK_SETUP;
3838
3839 if (hw->mac.ops.check_link)
3840 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3841
3842 if (ret)
3843 goto link_cfg_out;
3844
3845 autoneg = hw->phy.autoneg_advertised;
3846 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3847 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3848 &negotiation);
3849 if (ret)
3850 goto link_cfg_out;
3851
3852 if (hw->mac.ops.setup_link)
3853 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3854 link_cfg_out:
3855 return ret;
3856 }
3857
3858 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3859 {
3860 struct ixgbe_hw *hw = &adapter->hw;
3861 u32 gpie = 0;
3862
3863 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3864 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3865 IXGBE_GPIE_OCD;
3866 gpie |= IXGBE_GPIE_EIAME;
3867 /*
3868 * use EIAM to auto-mask when MSI-X interrupt is asserted
3869 * this saves a register write for every interrupt
3870 */
3871 switch (hw->mac.type) {
3872 case ixgbe_mac_82598EB:
3873 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3874 break;
3875 case ixgbe_mac_82599EB:
3876 case ixgbe_mac_X540:
3877 default:
3878 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3879 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3880 break;
3881 }
3882 } else {
3883 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3884 * specifically only auto mask tx and rx interrupts */
3885 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3886 }
3887
3888 /* XXX: to interrupt immediately for EICS writes, enable this */
3889 /* gpie |= IXGBE_GPIE_EIMEN; */
3890
3891 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3892 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3893 gpie |= IXGBE_GPIE_VTMODE_64;
3894 }
3895
3896 /* Enable Thermal over heat sensor interrupt */
3897 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3898 switch (adapter->hw.mac.type) {
3899 case ixgbe_mac_82599EB:
3900 gpie |= IXGBE_SDP0_GPIEN;
3901 break;
3902 case ixgbe_mac_X540:
3903 gpie |= IXGBE_EIMS_TS;
3904 break;
3905 default:
3906 break;
3907 }
3908 }
3909
3910 /* Enable fan failure interrupt */
3911 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3912 gpie |= IXGBE_SDP1_GPIEN;
3913
3914 if (hw->mac.type == ixgbe_mac_82599EB) {
3915 gpie |= IXGBE_SDP1_GPIEN;
3916 gpie |= IXGBE_SDP2_GPIEN;
3917 }
3918
3919 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3920 }
3921
3922 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3923 {
3924 struct ixgbe_hw *hw = &adapter->hw;
3925 int err;
3926 u32 ctrl_ext;
3927
3928 ixgbe_get_hw_control(adapter);
3929 ixgbe_setup_gpie(adapter);
3930
3931 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3932 ixgbe_configure_msix(adapter);
3933 else
3934 ixgbe_configure_msi_and_legacy(adapter);
3935
3936 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3937 if (hw->mac.ops.enable_tx_laser &&
3938 ((hw->phy.multispeed_fiber) ||
3939 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3940 (hw->mac.type == ixgbe_mac_82599EB))))
3941 hw->mac.ops.enable_tx_laser(hw);
3942
3943 clear_bit(__IXGBE_DOWN, &adapter->state);
3944 ixgbe_napi_enable_all(adapter);
3945
3946 if (ixgbe_is_sfp(hw)) {
3947 ixgbe_sfp_link_config(adapter);
3948 } else {
3949 err = ixgbe_non_sfp_link_config(hw);
3950 if (err)
3951 e_err(probe, "link_config FAILED %d\n", err);
3952 }
3953
3954 /* clear any pending interrupts, may auto mask */
3955 IXGBE_READ_REG(hw, IXGBE_EICR);
3956 ixgbe_irq_enable(adapter, true, true);
3957
3958 /*
3959 * If this adapter has a fan, check to see if we had a failure
3960 * before we enabled the interrupt.
3961 */
3962 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3963 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3964 if (esdp & IXGBE_ESDP_SDP1)
3965 e_crit(drv, "Fan has stopped, replace the adapter\n");
3966 }
3967
3968 /* enable transmits */
3969 netif_tx_start_all_queues(adapter->netdev);
3970
3971 /* bring the link up in the watchdog, this could race with our first
3972 * link up interrupt but shouldn't be a problem */
3973 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3974 adapter->link_check_timeout = jiffies;
3975 mod_timer(&adapter->service_timer, jiffies);
3976
3977 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3978 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3979 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3980 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3981 }
3982
3983 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3984 {
3985 WARN_ON(in_interrupt());
3986 /* put off any impending NetWatchDogTimeout */
3987 adapter->netdev->trans_start = jiffies;
3988
3989 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3990 usleep_range(1000, 2000);
3991 ixgbe_down(adapter);
3992 /*
3993 * If SR-IOV enabled then wait a bit before bringing the adapter
3994 * back up to give the VFs time to respond to the reset. The
3995 * two second wait is based upon the watchdog timer cycle in
3996 * the VF driver.
3997 */
3998 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3999 msleep(2000);
4000 ixgbe_up(adapter);
4001 clear_bit(__IXGBE_RESETTING, &adapter->state);
4002 }
4003
4004 void ixgbe_up(struct ixgbe_adapter *adapter)
4005 {
4006 /* hardware has been reset, we need to reload some things */
4007 ixgbe_configure(adapter);
4008
4009 ixgbe_up_complete(adapter);
4010 }
4011
4012 void ixgbe_reset(struct ixgbe_adapter *adapter)
4013 {
4014 struct ixgbe_hw *hw = &adapter->hw;
4015 int err;
4016
4017 /* lock SFP init bit to prevent race conditions with the watchdog */
4018 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4019 usleep_range(1000, 2000);
4020
4021 /* clear all SFP and link config related flags while holding SFP_INIT */
4022 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4023 IXGBE_FLAG2_SFP_NEEDS_RESET);
4024 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4025
4026 err = hw->mac.ops.init_hw(hw);
4027 switch (err) {
4028 case 0:
4029 case IXGBE_ERR_SFP_NOT_PRESENT:
4030 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4031 break;
4032 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4033 e_dev_err("master disable timed out\n");
4034 break;
4035 case IXGBE_ERR_EEPROM_VERSION:
4036 /* We are running on a pre-production device, log a warning */
4037 e_dev_warn("This device is a pre-production adapter/LOM. "
4038 "Please be aware there may be issues associated with "
4039 "your hardware. If you are experiencing problems "
4040 "please contact your Intel or hardware "
4041 "representative who provided you with this "
4042 "hardware.\n");
4043 break;
4044 default:
4045 e_dev_err("Hardware Error: %d\n", err);
4046 }
4047
4048 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4049
4050 /* reprogram the RAR[0] in case user changed it. */
4051 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4052 IXGBE_RAH_AV);
4053 }
4054
4055 /**
4056 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4057 * @rx_ring: ring to setup
4058 *
4059 * On many IA platforms the L1 cache has a critical stride of 4K, this
4060 * results in each receive buffer starting in the same cache set. To help
4061 * reduce the pressure on this cache set we can interleave the offsets so
4062 * that only every other buffer will be in the same cache set.
4063 **/
4064 static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4065 {
4066 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4067 u16 i;
4068
4069 for (i = 0; i < rx_ring->count; i += 2) {
4070 rx_buffer[0].page_offset = 0;
4071 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4072 rx_buffer = &rx_buffer[2];
4073 }
4074 }
4075
4076 /**
4077 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4078 * @rx_ring: ring to free buffers from
4079 **/
4080 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4081 {
4082 struct device *dev = rx_ring->dev;
4083 unsigned long size;
4084 u16 i;
4085
4086 /* ring already cleared, nothing to do */
4087 if (!rx_ring->rx_buffer_info)
4088 return;
4089
4090 /* Free all the Rx ring sk_buffs */
4091 for (i = 0; i < rx_ring->count; i++) {
4092 struct ixgbe_rx_buffer *rx_buffer;
4093
4094 rx_buffer = &rx_ring->rx_buffer_info[i];
4095 if (rx_buffer->skb) {
4096 struct sk_buff *skb = rx_buffer->skb;
4097 if (IXGBE_CB(skb)->page_released) {
4098 dma_unmap_page(dev,
4099 IXGBE_CB(skb)->dma,
4100 ixgbe_rx_bufsz(rx_ring),
4101 DMA_FROM_DEVICE);
4102 IXGBE_CB(skb)->page_released = false;
4103 }
4104 dev_kfree_skb(skb);
4105 }
4106 rx_buffer->skb = NULL;
4107 if (rx_buffer->dma)
4108 dma_unmap_page(dev, rx_buffer->dma,
4109 ixgbe_rx_pg_size(rx_ring),
4110 DMA_FROM_DEVICE);
4111 rx_buffer->dma = 0;
4112 if (rx_buffer->page)
4113 put_page(rx_buffer->page);
4114 rx_buffer->page = NULL;
4115 }
4116
4117 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4118 memset(rx_ring->rx_buffer_info, 0, size);
4119
4120 ixgbe_init_rx_page_offset(rx_ring);
4121
4122 /* Zero out the descriptor ring */
4123 memset(rx_ring->desc, 0, rx_ring->size);
4124
4125 rx_ring->next_to_alloc = 0;
4126 rx_ring->next_to_clean = 0;
4127 rx_ring->next_to_use = 0;
4128 }
4129
4130 /**
4131 * ixgbe_clean_tx_ring - Free Tx Buffers
4132 * @tx_ring: ring to be cleaned
4133 **/
4134 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4135 {
4136 struct ixgbe_tx_buffer *tx_buffer_info;
4137 unsigned long size;
4138 u16 i;
4139
4140 /* ring already cleared, nothing to do */
4141 if (!tx_ring->tx_buffer_info)
4142 return;
4143
4144 /* Free all the Tx ring sk_buffs */
4145 for (i = 0; i < tx_ring->count; i++) {
4146 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4147 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4148 }
4149
4150 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4151 memset(tx_ring->tx_buffer_info, 0, size);
4152
4153 /* Zero out the descriptor ring */
4154 memset(tx_ring->desc, 0, tx_ring->size);
4155
4156 tx_ring->next_to_use = 0;
4157 tx_ring->next_to_clean = 0;
4158 }
4159
4160 /**
4161 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4162 * @adapter: board private structure
4163 **/
4164 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4165 {
4166 int i;
4167
4168 for (i = 0; i < adapter->num_rx_queues; i++)
4169 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4170 }
4171
4172 /**
4173 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4174 * @adapter: board private structure
4175 **/
4176 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4177 {
4178 int i;
4179
4180 for (i = 0; i < adapter->num_tx_queues; i++)
4181 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4182 }
4183
4184 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4185 {
4186 struct hlist_node *node, *node2;
4187 struct ixgbe_fdir_filter *filter;
4188
4189 spin_lock(&adapter->fdir_perfect_lock);
4190
4191 hlist_for_each_entry_safe(filter, node, node2,
4192 &adapter->fdir_filter_list, fdir_node) {
4193 hlist_del(&filter->fdir_node);
4194 kfree(filter);
4195 }
4196 adapter->fdir_filter_count = 0;
4197
4198 spin_unlock(&adapter->fdir_perfect_lock);
4199 }
4200
4201 void ixgbe_down(struct ixgbe_adapter *adapter)
4202 {
4203 struct net_device *netdev = adapter->netdev;
4204 struct ixgbe_hw *hw = &adapter->hw;
4205 u32 rxctrl;
4206 int i;
4207
4208 /* signal that we are down to the interrupt handler */
4209 set_bit(__IXGBE_DOWN, &adapter->state);
4210
4211 /* disable receives */
4212 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4213 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4214
4215 /* disable all enabled rx queues */
4216 for (i = 0; i < adapter->num_rx_queues; i++)
4217 /* this call also flushes the previous write */
4218 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4219
4220 usleep_range(10000, 20000);
4221
4222 netif_tx_stop_all_queues(netdev);
4223
4224 /* call carrier off first to avoid false dev_watchdog timeouts */
4225 netif_carrier_off(netdev);
4226 netif_tx_disable(netdev);
4227
4228 ixgbe_irq_disable(adapter);
4229
4230 ixgbe_napi_disable_all(adapter);
4231
4232 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4233 IXGBE_FLAG2_RESET_REQUESTED);
4234 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4235
4236 del_timer_sync(&adapter->service_timer);
4237
4238 if (adapter->num_vfs) {
4239 /* Clear EITR Select mapping */
4240 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4241
4242 /* Mark all the VFs as inactive */
4243 for (i = 0 ; i < adapter->num_vfs; i++)
4244 adapter->vfinfo[i].clear_to_send = false;
4245
4246 /* ping all the active vfs to let them know we are going down */
4247 ixgbe_ping_all_vfs(adapter);
4248
4249 /* Disable all VFTE/VFRE TX/RX */
4250 ixgbe_disable_tx_rx(adapter);
4251 }
4252
4253 /* disable transmits in the hardware now that interrupts are off */
4254 for (i = 0; i < adapter->num_tx_queues; i++) {
4255 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4256 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4257 }
4258
4259 /* Disable the Tx DMA engine on 82599 and X540 */
4260 switch (hw->mac.type) {
4261 case ixgbe_mac_82599EB:
4262 case ixgbe_mac_X540:
4263 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4264 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4265 ~IXGBE_DMATXCTL_TE));
4266 break;
4267 default:
4268 break;
4269 }
4270
4271 if (!pci_channel_offline(adapter->pdev))
4272 ixgbe_reset(adapter);
4273
4274 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4275 if (hw->mac.ops.disable_tx_laser &&
4276 ((hw->phy.multispeed_fiber) ||
4277 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4278 (hw->mac.type == ixgbe_mac_82599EB))))
4279 hw->mac.ops.disable_tx_laser(hw);
4280
4281 ixgbe_clean_all_tx_rings(adapter);
4282 ixgbe_clean_all_rx_rings(adapter);
4283
4284 #ifdef CONFIG_IXGBE_DCA
4285 /* since we reset the hardware DCA settings were cleared */
4286 ixgbe_setup_dca(adapter);
4287 #endif
4288 }
4289
4290 /**
4291 * ixgbe_tx_timeout - Respond to a Tx Hang
4292 * @netdev: network interface device structure
4293 **/
4294 static void ixgbe_tx_timeout(struct net_device *netdev)
4295 {
4296 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4297
4298 /* Do the reset outside of interrupt context */
4299 ixgbe_tx_timeout_reset(adapter);
4300 }
4301
4302 /**
4303 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4304 * @adapter: board private structure to initialize
4305 *
4306 * ixgbe_sw_init initializes the Adapter private data structure.
4307 * Fields are initialized based on PCI device information and
4308 * OS network device settings (MTU size).
4309 **/
4310 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4311 {
4312 struct ixgbe_hw *hw = &adapter->hw;
4313 struct pci_dev *pdev = adapter->pdev;
4314 unsigned int rss;
4315 #ifdef CONFIG_IXGBE_DCB
4316 int j;
4317 struct tc_configuration *tc;
4318 #endif
4319
4320 /* PCI config space info */
4321
4322 hw->vendor_id = pdev->vendor;
4323 hw->device_id = pdev->device;
4324 hw->revision_id = pdev->revision;
4325 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4326 hw->subsystem_device_id = pdev->subsystem_device;
4327
4328 /* Set capability flags */
4329 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4330 adapter->ring_feature[RING_F_RSS].indices = rss;
4331 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4332 switch (hw->mac.type) {
4333 case ixgbe_mac_82598EB:
4334 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4335 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4336 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4337 break;
4338 case ixgbe_mac_X540:
4339 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4340 case ixgbe_mac_82599EB:
4341 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4342 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4343 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4344 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4345 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4346 /* Flow Director hash filters enabled */
4347 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4348 adapter->atr_sample_rate = 20;
4349 adapter->ring_feature[RING_F_FDIR].indices =
4350 IXGBE_MAX_FDIR_INDICES;
4351 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4352 #ifdef IXGBE_FCOE
4353 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4354 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4355 adapter->ring_feature[RING_F_FCOE].indices = 0;
4356 #ifdef CONFIG_IXGBE_DCB
4357 /* Default traffic class to use for FCoE */
4358 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4359 #endif
4360 #endif /* IXGBE_FCOE */
4361 break;
4362 default:
4363 break;
4364 }
4365
4366 /* n-tuple support exists, always init our spinlock */
4367 spin_lock_init(&adapter->fdir_perfect_lock);
4368
4369 #ifdef CONFIG_IXGBE_DCB
4370 switch (hw->mac.type) {
4371 case ixgbe_mac_X540:
4372 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4373 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4374 break;
4375 default:
4376 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4377 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4378 break;
4379 }
4380
4381 /* Configure DCB traffic classes */
4382 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4383 tc = &adapter->dcb_cfg.tc_config[j];
4384 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4385 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4386 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4387 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4388 tc->dcb_pfc = pfc_disabled;
4389 }
4390
4391 /* Initialize default user to priority mapping, UPx->TC0 */
4392 tc = &adapter->dcb_cfg.tc_config[0];
4393 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4394 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4395
4396 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4397 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4398 adapter->dcb_cfg.pfc_mode_enable = false;
4399 adapter->dcb_set_bitmap = 0x00;
4400 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4401 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4402 MAX_TRAFFIC_CLASS);
4403
4404 #endif
4405
4406 /* default flow control settings */
4407 hw->fc.requested_mode = ixgbe_fc_full;
4408 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4409 #ifdef CONFIG_DCB
4410 adapter->last_lfc_mode = hw->fc.current_mode;
4411 #endif
4412 ixgbe_pbthresh_setup(adapter);
4413 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4414 hw->fc.send_xon = true;
4415 hw->fc.disable_fc_autoneg = false;
4416
4417 /* enable itr by default in dynamic mode */
4418 adapter->rx_itr_setting = 1;
4419 adapter->tx_itr_setting = 1;
4420
4421 /* set default ring sizes */
4422 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4423 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4424
4425 /* set default work limits */
4426 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4427
4428 /* initialize eeprom parameters */
4429 if (ixgbe_init_eeprom_params_generic(hw)) {
4430 e_dev_err("EEPROM initialization failed\n");
4431 return -EIO;
4432 }
4433
4434 set_bit(__IXGBE_DOWN, &adapter->state);
4435
4436 return 0;
4437 }
4438
4439 /**
4440 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4441 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4442 *
4443 * Return 0 on success, negative on failure
4444 **/
4445 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4446 {
4447 struct device *dev = tx_ring->dev;
4448 int orig_node = dev_to_node(dev);
4449 int numa_node = -1;
4450 int size;
4451
4452 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4453
4454 if (tx_ring->q_vector)
4455 numa_node = tx_ring->q_vector->numa_node;
4456
4457 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4458 if (!tx_ring->tx_buffer_info)
4459 tx_ring->tx_buffer_info = vzalloc(size);
4460 if (!tx_ring->tx_buffer_info)
4461 goto err;
4462
4463 /* round up to nearest 4K */
4464 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4465 tx_ring->size = ALIGN(tx_ring->size, 4096);
4466
4467 set_dev_node(dev, numa_node);
4468 tx_ring->desc = dma_alloc_coherent(dev,
4469 tx_ring->size,
4470 &tx_ring->dma,
4471 GFP_KERNEL);
4472 set_dev_node(dev, orig_node);
4473 if (!tx_ring->desc)
4474 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4475 &tx_ring->dma, GFP_KERNEL);
4476 if (!tx_ring->desc)
4477 goto err;
4478
4479 tx_ring->next_to_use = 0;
4480 tx_ring->next_to_clean = 0;
4481 return 0;
4482
4483 err:
4484 vfree(tx_ring->tx_buffer_info);
4485 tx_ring->tx_buffer_info = NULL;
4486 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4487 return -ENOMEM;
4488 }
4489
4490 /**
4491 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4492 * @adapter: board private structure
4493 *
4494 * If this function returns with an error, then it's possible one or
4495 * more of the rings is populated (while the rest are not). It is the
4496 * callers duty to clean those orphaned rings.
4497 *
4498 * Return 0 on success, negative on failure
4499 **/
4500 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4501 {
4502 int i, err = 0;
4503
4504 for (i = 0; i < adapter->num_tx_queues; i++) {
4505 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4506 if (!err)
4507 continue;
4508 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4509 break;
4510 }
4511
4512 return err;
4513 }
4514
4515 /**
4516 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4517 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4518 *
4519 * Returns 0 on success, negative on failure
4520 **/
4521 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4522 {
4523 struct device *dev = rx_ring->dev;
4524 int orig_node = dev_to_node(dev);
4525 int numa_node = -1;
4526 int size;
4527
4528 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4529
4530 if (rx_ring->q_vector)
4531 numa_node = rx_ring->q_vector->numa_node;
4532
4533 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4534 if (!rx_ring->rx_buffer_info)
4535 rx_ring->rx_buffer_info = vzalloc(size);
4536 if (!rx_ring->rx_buffer_info)
4537 goto err;
4538
4539 /* Round up to nearest 4K */
4540 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4541 rx_ring->size = ALIGN(rx_ring->size, 4096);
4542
4543 set_dev_node(dev, numa_node);
4544 rx_ring->desc = dma_alloc_coherent(dev,
4545 rx_ring->size,
4546 &rx_ring->dma,
4547 GFP_KERNEL);
4548 set_dev_node(dev, orig_node);
4549 if (!rx_ring->desc)
4550 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4551 &rx_ring->dma, GFP_KERNEL);
4552 if (!rx_ring->desc)
4553 goto err;
4554
4555 rx_ring->next_to_clean = 0;
4556 rx_ring->next_to_use = 0;
4557
4558 ixgbe_init_rx_page_offset(rx_ring);
4559
4560 return 0;
4561 err:
4562 vfree(rx_ring->rx_buffer_info);
4563 rx_ring->rx_buffer_info = NULL;
4564 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4565 return -ENOMEM;
4566 }
4567
4568 /**
4569 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4570 * @adapter: board private structure
4571 *
4572 * If this function returns with an error, then it's possible one or
4573 * more of the rings is populated (while the rest are not). It is the
4574 * callers duty to clean those orphaned rings.
4575 *
4576 * Return 0 on success, negative on failure
4577 **/
4578 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4579 {
4580 int i, err = 0;
4581
4582 for (i = 0; i < adapter->num_rx_queues; i++) {
4583 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4584 if (!err)
4585 continue;
4586 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4587 break;
4588 }
4589
4590 return err;
4591 }
4592
4593 /**
4594 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4595 * @tx_ring: Tx descriptor ring for a specific queue
4596 *
4597 * Free all transmit software resources
4598 **/
4599 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4600 {
4601 ixgbe_clean_tx_ring(tx_ring);
4602
4603 vfree(tx_ring->tx_buffer_info);
4604 tx_ring->tx_buffer_info = NULL;
4605
4606 /* if not set, then don't free */
4607 if (!tx_ring->desc)
4608 return;
4609
4610 dma_free_coherent(tx_ring->dev, tx_ring->size,
4611 tx_ring->desc, tx_ring->dma);
4612
4613 tx_ring->desc = NULL;
4614 }
4615
4616 /**
4617 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4618 * @adapter: board private structure
4619 *
4620 * Free all transmit software resources
4621 **/
4622 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4623 {
4624 int i;
4625
4626 for (i = 0; i < adapter->num_tx_queues; i++)
4627 if (adapter->tx_ring[i]->desc)
4628 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4629 }
4630
4631 /**
4632 * ixgbe_free_rx_resources - Free Rx Resources
4633 * @rx_ring: ring to clean the resources from
4634 *
4635 * Free all receive software resources
4636 **/
4637 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4638 {
4639 ixgbe_clean_rx_ring(rx_ring);
4640
4641 vfree(rx_ring->rx_buffer_info);
4642 rx_ring->rx_buffer_info = NULL;
4643
4644 /* if not set, then don't free */
4645 if (!rx_ring->desc)
4646 return;
4647
4648 dma_free_coherent(rx_ring->dev, rx_ring->size,
4649 rx_ring->desc, rx_ring->dma);
4650
4651 rx_ring->desc = NULL;
4652 }
4653
4654 /**
4655 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4656 * @adapter: board private structure
4657 *
4658 * Free all receive software resources
4659 **/
4660 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4661 {
4662 int i;
4663
4664 for (i = 0; i < adapter->num_rx_queues; i++)
4665 if (adapter->rx_ring[i]->desc)
4666 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4667 }
4668
4669 /**
4670 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4671 * @netdev: network interface device structure
4672 * @new_mtu: new value for maximum frame size
4673 *
4674 * Returns 0 on success, negative on failure
4675 **/
4676 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4677 {
4678 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4679 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4680
4681 /* MTU < 68 is an error and causes problems on some kernels */
4682 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4683 return -EINVAL;
4684
4685 /*
4686 * For 82599EB we cannot allow PF to change MTU greater than 1500
4687 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4688 * don't allocate and chain buffers correctly.
4689 */
4690 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4691 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4692 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4693 return -EINVAL;
4694
4695 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4696
4697 /* must set new MTU before calling down or up */
4698 netdev->mtu = new_mtu;
4699
4700 if (netif_running(netdev))
4701 ixgbe_reinit_locked(adapter);
4702
4703 return 0;
4704 }
4705
4706 /**
4707 * ixgbe_open - Called when a network interface is made active
4708 * @netdev: network interface device structure
4709 *
4710 * Returns 0 on success, negative value on failure
4711 *
4712 * The open entry point is called when a network interface is made
4713 * active by the system (IFF_UP). At this point all resources needed
4714 * for transmit and receive operations are allocated, the interrupt
4715 * handler is registered with the OS, the watchdog timer is started,
4716 * and the stack is notified that the interface is ready.
4717 **/
4718 static int ixgbe_open(struct net_device *netdev)
4719 {
4720 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4721 int err;
4722
4723 /* disallow open during test */
4724 if (test_bit(__IXGBE_TESTING, &adapter->state))
4725 return -EBUSY;
4726
4727 netif_carrier_off(netdev);
4728
4729 /* allocate transmit descriptors */
4730 err = ixgbe_setup_all_tx_resources(adapter);
4731 if (err)
4732 goto err_setup_tx;
4733
4734 /* allocate receive descriptors */
4735 err = ixgbe_setup_all_rx_resources(adapter);
4736 if (err)
4737 goto err_setup_rx;
4738
4739 ixgbe_configure(adapter);
4740
4741 err = ixgbe_request_irq(adapter);
4742 if (err)
4743 goto err_req_irq;
4744
4745 ixgbe_up_complete(adapter);
4746
4747 return 0;
4748
4749 err_req_irq:
4750 err_setup_rx:
4751 ixgbe_free_all_rx_resources(adapter);
4752 err_setup_tx:
4753 ixgbe_free_all_tx_resources(adapter);
4754 ixgbe_reset(adapter);
4755
4756 return err;
4757 }
4758
4759 /**
4760 * ixgbe_close - Disables a network interface
4761 * @netdev: network interface device structure
4762 *
4763 * Returns 0, this is not allowed to fail
4764 *
4765 * The close entry point is called when an interface is de-activated
4766 * by the OS. The hardware is still under the drivers control, but
4767 * needs to be disabled. A global MAC reset is issued to stop the
4768 * hardware, and all transmit and receive resources are freed.
4769 **/
4770 static int ixgbe_close(struct net_device *netdev)
4771 {
4772 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4773
4774 ixgbe_down(adapter);
4775 ixgbe_free_irq(adapter);
4776
4777 ixgbe_fdir_filter_exit(adapter);
4778
4779 ixgbe_free_all_tx_resources(adapter);
4780 ixgbe_free_all_rx_resources(adapter);
4781
4782 ixgbe_release_hw_control(adapter);
4783
4784 return 0;
4785 }
4786
4787 #ifdef CONFIG_PM
4788 static int ixgbe_resume(struct pci_dev *pdev)
4789 {
4790 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4791 struct net_device *netdev = adapter->netdev;
4792 u32 err;
4793
4794 pci_set_power_state(pdev, PCI_D0);
4795 pci_restore_state(pdev);
4796 /*
4797 * pci_restore_state clears dev->state_saved so call
4798 * pci_save_state to restore it.
4799 */
4800 pci_save_state(pdev);
4801
4802 err = pci_enable_device_mem(pdev);
4803 if (err) {
4804 e_dev_err("Cannot enable PCI device from suspend\n");
4805 return err;
4806 }
4807 pci_set_master(pdev);
4808
4809 pci_wake_from_d3(pdev, false);
4810
4811 err = ixgbe_init_interrupt_scheme(adapter);
4812 if (err) {
4813 e_dev_err("Cannot initialize interrupts for device\n");
4814 return err;
4815 }
4816
4817 ixgbe_reset(adapter);
4818
4819 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4820
4821 if (netif_running(netdev)) {
4822 err = ixgbe_open(netdev);
4823 if (err)
4824 return err;
4825 }
4826
4827 netif_device_attach(netdev);
4828
4829 return 0;
4830 }
4831 #endif /* CONFIG_PM */
4832
4833 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4834 {
4835 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4836 struct net_device *netdev = adapter->netdev;
4837 struct ixgbe_hw *hw = &adapter->hw;
4838 u32 ctrl, fctrl;
4839 u32 wufc = adapter->wol;
4840 #ifdef CONFIG_PM
4841 int retval = 0;
4842 #endif
4843
4844 netif_device_detach(netdev);
4845
4846 if (netif_running(netdev)) {
4847 ixgbe_down(adapter);
4848 ixgbe_free_irq(adapter);
4849 ixgbe_free_all_tx_resources(adapter);
4850 ixgbe_free_all_rx_resources(adapter);
4851 }
4852
4853 ixgbe_clear_interrupt_scheme(adapter);
4854 #ifdef CONFIG_DCB
4855 kfree(adapter->ixgbe_ieee_pfc);
4856 kfree(adapter->ixgbe_ieee_ets);
4857 #endif
4858
4859 #ifdef CONFIG_PM
4860 retval = pci_save_state(pdev);
4861 if (retval)
4862 return retval;
4863
4864 #endif
4865 if (wufc) {
4866 ixgbe_set_rx_mode(netdev);
4867
4868 /* turn on all-multi mode if wake on multicast is enabled */
4869 if (wufc & IXGBE_WUFC_MC) {
4870 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4871 fctrl |= IXGBE_FCTRL_MPE;
4872 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4873 }
4874
4875 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4876 ctrl |= IXGBE_CTRL_GIO_DIS;
4877 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4878
4879 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4880 } else {
4881 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4882 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4883 }
4884
4885 switch (hw->mac.type) {
4886 case ixgbe_mac_82598EB:
4887 pci_wake_from_d3(pdev, false);
4888 break;
4889 case ixgbe_mac_82599EB:
4890 case ixgbe_mac_X540:
4891 pci_wake_from_d3(pdev, !!wufc);
4892 break;
4893 default:
4894 break;
4895 }
4896
4897 *enable_wake = !!wufc;
4898
4899 ixgbe_release_hw_control(adapter);
4900
4901 pci_disable_device(pdev);
4902
4903 return 0;
4904 }
4905
4906 #ifdef CONFIG_PM
4907 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4908 {
4909 int retval;
4910 bool wake;
4911
4912 retval = __ixgbe_shutdown(pdev, &wake);
4913 if (retval)
4914 return retval;
4915
4916 if (wake) {
4917 pci_prepare_to_sleep(pdev);
4918 } else {
4919 pci_wake_from_d3(pdev, false);
4920 pci_set_power_state(pdev, PCI_D3hot);
4921 }
4922
4923 return 0;
4924 }
4925 #endif /* CONFIG_PM */
4926
4927 static void ixgbe_shutdown(struct pci_dev *pdev)
4928 {
4929 bool wake;
4930
4931 __ixgbe_shutdown(pdev, &wake);
4932
4933 if (system_state == SYSTEM_POWER_OFF) {
4934 pci_wake_from_d3(pdev, wake);
4935 pci_set_power_state(pdev, PCI_D3hot);
4936 }
4937 }
4938
4939 /**
4940 * ixgbe_update_stats - Update the board statistics counters.
4941 * @adapter: board private structure
4942 **/
4943 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4944 {
4945 struct net_device *netdev = adapter->netdev;
4946 struct ixgbe_hw *hw = &adapter->hw;
4947 struct ixgbe_hw_stats *hwstats = &adapter->stats;
4948 u64 total_mpc = 0;
4949 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4950 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
4951 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
4952 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
4953 #ifdef IXGBE_FCOE
4954 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4955 unsigned int cpu;
4956 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
4957 #endif /* IXGBE_FCOE */
4958
4959 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4960 test_bit(__IXGBE_RESETTING, &adapter->state))
4961 return;
4962
4963 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4964 u64 rsc_count = 0;
4965 u64 rsc_flush = 0;
4966 for (i = 0; i < 16; i++)
4967 adapter->hw_rx_no_dma_resources +=
4968 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4969 for (i = 0; i < adapter->num_rx_queues; i++) {
4970 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
4971 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
4972 }
4973 adapter->rsc_total_count = rsc_count;
4974 adapter->rsc_total_flush = rsc_flush;
4975 }
4976
4977 for (i = 0; i < adapter->num_rx_queues; i++) {
4978 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
4979 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
4980 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
4981 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
4982 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
4983 bytes += rx_ring->stats.bytes;
4984 packets += rx_ring->stats.packets;
4985 }
4986 adapter->non_eop_descs = non_eop_descs;
4987 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
4988 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
4989 adapter->hw_csum_rx_error = hw_csum_rx_error;
4990 netdev->stats.rx_bytes = bytes;
4991 netdev->stats.rx_packets = packets;
4992
4993 bytes = 0;
4994 packets = 0;
4995 /* gather some stats to the adapter struct that are per queue */
4996 for (i = 0; i < adapter->num_tx_queues; i++) {
4997 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
4998 restart_queue += tx_ring->tx_stats.restart_queue;
4999 tx_busy += tx_ring->tx_stats.tx_busy;
5000 bytes += tx_ring->stats.bytes;
5001 packets += tx_ring->stats.packets;
5002 }
5003 adapter->restart_queue = restart_queue;
5004 adapter->tx_busy = tx_busy;
5005 netdev->stats.tx_bytes = bytes;
5006 netdev->stats.tx_packets = packets;
5007
5008 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5009
5010 /* 8 register reads */
5011 for (i = 0; i < 8; i++) {
5012 /* for packet buffers not used, the register should read 0 */
5013 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5014 missed_rx += mpc;
5015 hwstats->mpc[i] += mpc;
5016 total_mpc += hwstats->mpc[i];
5017 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5018 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5019 switch (hw->mac.type) {
5020 case ixgbe_mac_82598EB:
5021 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5022 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5023 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5024 hwstats->pxonrxc[i] +=
5025 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5026 break;
5027 case ixgbe_mac_82599EB:
5028 case ixgbe_mac_X540:
5029 hwstats->pxonrxc[i] +=
5030 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5031 break;
5032 default:
5033 break;
5034 }
5035 }
5036
5037 /*16 register reads */
5038 for (i = 0; i < 16; i++) {
5039 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5040 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5041 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5042 (hw->mac.type == ixgbe_mac_X540)) {
5043 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5044 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5045 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5046 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5047 }
5048 }
5049
5050 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5051 /* work around hardware counting issue */
5052 hwstats->gprc -= missed_rx;
5053
5054 ixgbe_update_xoff_received(adapter);
5055
5056 /* 82598 hardware only has a 32 bit counter in the high register */
5057 switch (hw->mac.type) {
5058 case ixgbe_mac_82598EB:
5059 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5060 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5061 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5062 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5063 break;
5064 case ixgbe_mac_X540:
5065 /* OS2BMC stats are X540 only*/
5066 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5067 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5068 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5069 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5070 case ixgbe_mac_82599EB:
5071 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5072 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5073 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5074 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5075 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5076 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5077 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5078 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5079 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5080 #ifdef IXGBE_FCOE
5081 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5082 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5083 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5084 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5085 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5086 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5087 /* Add up per cpu counters for total ddp aloc fail */
5088 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5089 for_each_possible_cpu(cpu) {
5090 fcoe_noddp_counts_sum +=
5091 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5092 fcoe_noddp_ext_buff_counts_sum +=
5093 *per_cpu_ptr(fcoe->
5094 pcpu_noddp_ext_buff, cpu);
5095 }
5096 }
5097 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5098 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5099 #endif /* IXGBE_FCOE */
5100 break;
5101 default:
5102 break;
5103 }
5104 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5105 hwstats->bprc += bprc;
5106 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5107 if (hw->mac.type == ixgbe_mac_82598EB)
5108 hwstats->mprc -= bprc;
5109 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5110 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5111 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5112 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5113 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5114 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5115 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5116 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5117 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5118 hwstats->lxontxc += lxon;
5119 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5120 hwstats->lxofftxc += lxoff;
5121 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5122 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5123 /*
5124 * 82598 errata - tx of flow control packets is included in tx counters
5125 */
5126 xon_off_tot = lxon + lxoff;
5127 hwstats->gptc -= xon_off_tot;
5128 hwstats->mptc -= xon_off_tot;
5129 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5130 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5131 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5132 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5133 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5134 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5135 hwstats->ptc64 -= xon_off_tot;
5136 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5137 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5138 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5139 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5140 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5141 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5142
5143 /* Fill out the OS statistics structure */
5144 netdev->stats.multicast = hwstats->mprc;
5145
5146 /* Rx Errors */
5147 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5148 netdev->stats.rx_dropped = 0;
5149 netdev->stats.rx_length_errors = hwstats->rlec;
5150 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5151 netdev->stats.rx_missed_errors = total_mpc;
5152 }
5153
5154 /**
5155 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5156 * @adapter - pointer to the device adapter structure
5157 **/
5158 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5159 {
5160 struct ixgbe_hw *hw = &adapter->hw;
5161 int i;
5162
5163 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5164 return;
5165
5166 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5167
5168 /* if interface is down do nothing */
5169 if (test_bit(__IXGBE_DOWN, &adapter->state))
5170 return;
5171
5172 /* do nothing if we are not using signature filters */
5173 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5174 return;
5175
5176 adapter->fdir_overflow++;
5177
5178 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5179 for (i = 0; i < adapter->num_tx_queues; i++)
5180 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5181 &(adapter->tx_ring[i]->state));
5182 /* re-enable flow director interrupts */
5183 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5184 } else {
5185 e_err(probe, "failed to finish FDIR re-initialization, "
5186 "ignored adding FDIR ATR filters\n");
5187 }
5188 }
5189
5190 /**
5191 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5192 * @adapter - pointer to the device adapter structure
5193 *
5194 * This function serves two purposes. First it strobes the interrupt lines
5195 * in order to make certain interrupts are occurring. Secondly it sets the
5196 * bits needed to check for TX hangs. As a result we should immediately
5197 * determine if a hang has occurred.
5198 */
5199 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5200 {
5201 struct ixgbe_hw *hw = &adapter->hw;
5202 u64 eics = 0;
5203 int i;
5204
5205 /* If we're down or resetting, just bail */
5206 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5207 test_bit(__IXGBE_RESETTING, &adapter->state))
5208 return;
5209
5210 /* Force detection of hung controller */
5211 if (netif_carrier_ok(adapter->netdev)) {
5212 for (i = 0; i < adapter->num_tx_queues; i++)
5213 set_check_for_tx_hang(adapter->tx_ring[i]);
5214 }
5215
5216 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5217 /*
5218 * for legacy and MSI interrupts don't set any bits
5219 * that are enabled for EIAM, because this operation
5220 * would set *both* EIMS and EICS for any bit in EIAM
5221 */
5222 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5223 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5224 } else {
5225 /* get one bit for every active tx/rx interrupt vector */
5226 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5227 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5228 if (qv->rx.ring || qv->tx.ring)
5229 eics |= ((u64)1 << i);
5230 }
5231 }
5232
5233 /* Cause software interrupt to ensure rings are cleaned */
5234 ixgbe_irq_rearm_queues(adapter, eics);
5235
5236 }
5237
5238 /**
5239 * ixgbe_watchdog_update_link - update the link status
5240 * @adapter - pointer to the device adapter structure
5241 * @link_speed - pointer to a u32 to store the link_speed
5242 **/
5243 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5244 {
5245 struct ixgbe_hw *hw = &adapter->hw;
5246 u32 link_speed = adapter->link_speed;
5247 bool link_up = adapter->link_up;
5248 int i;
5249
5250 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5251 return;
5252
5253 if (hw->mac.ops.check_link) {
5254 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5255 } else {
5256 /* always assume link is up, if no check link function */
5257 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5258 link_up = true;
5259 }
5260 if (link_up) {
5261 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5262 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5263 hw->mac.ops.fc_enable(hw, i);
5264 } else {
5265 hw->mac.ops.fc_enable(hw, 0);
5266 }
5267 }
5268
5269 if (link_up ||
5270 time_after(jiffies, (adapter->link_check_timeout +
5271 IXGBE_TRY_LINK_TIMEOUT))) {
5272 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5273 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5274 IXGBE_WRITE_FLUSH(hw);
5275 }
5276
5277 adapter->link_up = link_up;
5278 adapter->link_speed = link_speed;
5279 }
5280
5281 /**
5282 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5283 * print link up message
5284 * @adapter - pointer to the device adapter structure
5285 **/
5286 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5287 {
5288 struct net_device *netdev = adapter->netdev;
5289 struct ixgbe_hw *hw = &adapter->hw;
5290 u32 link_speed = adapter->link_speed;
5291 bool flow_rx, flow_tx;
5292
5293 /* only continue if link was previously down */
5294 if (netif_carrier_ok(netdev))
5295 return;
5296
5297 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5298
5299 switch (hw->mac.type) {
5300 case ixgbe_mac_82598EB: {
5301 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5302 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5303 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5304 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5305 }
5306 break;
5307 case ixgbe_mac_X540:
5308 case ixgbe_mac_82599EB: {
5309 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5310 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5311 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5312 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5313 }
5314 break;
5315 default:
5316 flow_tx = false;
5317 flow_rx = false;
5318 break;
5319 }
5320 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5321 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5322 "10 Gbps" :
5323 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5324 "1 Gbps" :
5325 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5326 "100 Mbps" :
5327 "unknown speed"))),
5328 ((flow_rx && flow_tx) ? "RX/TX" :
5329 (flow_rx ? "RX" :
5330 (flow_tx ? "TX" : "None"))));
5331
5332 netif_carrier_on(netdev);
5333 ixgbe_check_vf_rate_limit(adapter);
5334 }
5335
5336 /**
5337 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5338 * print link down message
5339 * @adapter - pointer to the adapter structure
5340 **/
5341 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5342 {
5343 struct net_device *netdev = adapter->netdev;
5344 struct ixgbe_hw *hw = &adapter->hw;
5345
5346 adapter->link_up = false;
5347 adapter->link_speed = 0;
5348
5349 /* only continue if link was up previously */
5350 if (!netif_carrier_ok(netdev))
5351 return;
5352
5353 /* poll for SFP+ cable when link is down */
5354 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5355 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5356
5357 e_info(drv, "NIC Link is Down\n");
5358 netif_carrier_off(netdev);
5359 }
5360
5361 /**
5362 * ixgbe_watchdog_flush_tx - flush queues on link down
5363 * @adapter - pointer to the device adapter structure
5364 **/
5365 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5366 {
5367 int i;
5368 int some_tx_pending = 0;
5369
5370 if (!netif_carrier_ok(adapter->netdev)) {
5371 for (i = 0; i < adapter->num_tx_queues; i++) {
5372 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5373 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5374 some_tx_pending = 1;
5375 break;
5376 }
5377 }
5378
5379 if (some_tx_pending) {
5380 /* We've lost link, so the controller stops DMA,
5381 * but we've got queued Tx work that's never going
5382 * to get done, so reset controller to flush Tx.
5383 * (Do the reset outside of interrupt context).
5384 */
5385 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5386 }
5387 }
5388 }
5389
5390 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5391 {
5392 u32 ssvpc;
5393
5394 /* Do not perform spoof check for 82598 */
5395 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5396 return;
5397
5398 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5399
5400 /*
5401 * ssvpc register is cleared on read, if zero then no
5402 * spoofed packets in the last interval.
5403 */
5404 if (!ssvpc)
5405 return;
5406
5407 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5408 }
5409
5410 /**
5411 * ixgbe_watchdog_subtask - check and bring link up
5412 * @adapter - pointer to the device adapter structure
5413 **/
5414 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5415 {
5416 /* if interface is down do nothing */
5417 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5418 test_bit(__IXGBE_RESETTING, &adapter->state))
5419 return;
5420
5421 ixgbe_watchdog_update_link(adapter);
5422
5423 if (adapter->link_up)
5424 ixgbe_watchdog_link_is_up(adapter);
5425 else
5426 ixgbe_watchdog_link_is_down(adapter);
5427
5428 ixgbe_spoof_check(adapter);
5429 ixgbe_update_stats(adapter);
5430
5431 ixgbe_watchdog_flush_tx(adapter);
5432 }
5433
5434 /**
5435 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5436 * @adapter - the ixgbe adapter structure
5437 **/
5438 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5439 {
5440 struct ixgbe_hw *hw = &adapter->hw;
5441 s32 err;
5442
5443 /* not searching for SFP so there is nothing to do here */
5444 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5445 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5446 return;
5447
5448 /* someone else is in init, wait until next service event */
5449 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5450 return;
5451
5452 err = hw->phy.ops.identify_sfp(hw);
5453 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5454 goto sfp_out;
5455
5456 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5457 /* If no cable is present, then we need to reset
5458 * the next time we find a good cable. */
5459 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5460 }
5461
5462 /* exit on error */
5463 if (err)
5464 goto sfp_out;
5465
5466 /* exit if reset not needed */
5467 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5468 goto sfp_out;
5469
5470 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5471
5472 /*
5473 * A module may be identified correctly, but the EEPROM may not have
5474 * support for that module. setup_sfp() will fail in that case, so
5475 * we should not allow that module to load.
5476 */
5477 if (hw->mac.type == ixgbe_mac_82598EB)
5478 err = hw->phy.ops.reset(hw);
5479 else
5480 err = hw->mac.ops.setup_sfp(hw);
5481
5482 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5483 goto sfp_out;
5484
5485 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5486 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5487
5488 sfp_out:
5489 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5490
5491 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5492 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5493 e_dev_err("failed to initialize because an unsupported "
5494 "SFP+ module type was detected.\n");
5495 e_dev_err("Reload the driver after installing a "
5496 "supported module.\n");
5497 unregister_netdev(adapter->netdev);
5498 }
5499 }
5500
5501 /**
5502 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5503 * @adapter - the ixgbe adapter structure
5504 **/
5505 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5506 {
5507 struct ixgbe_hw *hw = &adapter->hw;
5508 u32 autoneg;
5509 bool negotiation;
5510
5511 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5512 return;
5513
5514 /* someone else is in init, wait until next service event */
5515 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5516 return;
5517
5518 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5519
5520 autoneg = hw->phy.autoneg_advertised;
5521 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5522 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5523 if (hw->mac.ops.setup_link)
5524 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5525
5526 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5527 adapter->link_check_timeout = jiffies;
5528 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5529 }
5530
5531 #ifdef CONFIG_PCI_IOV
5532 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5533 {
5534 int vf;
5535 struct ixgbe_hw *hw = &adapter->hw;
5536 struct net_device *netdev = adapter->netdev;
5537 u32 gpc;
5538 u32 ciaa, ciad;
5539
5540 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5541 if (gpc) /* If incrementing then no need for the check below */
5542 return;
5543 /*
5544 * Check to see if a bad DMA write target from an errant or
5545 * malicious VF has caused a PCIe error. If so then we can
5546 * issue a VFLR to the offending VF(s) and then resume without
5547 * requesting a full slot reset.
5548 */
5549
5550 for (vf = 0; vf < adapter->num_vfs; vf++) {
5551 ciaa = (vf << 16) | 0x80000000;
5552 /* 32 bit read so align, we really want status at offset 6 */
5553 ciaa |= PCI_COMMAND;
5554 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5555 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5556 ciaa &= 0x7FFFFFFF;
5557 /* disable debug mode asap after reading data */
5558 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5559 /* Get the upper 16 bits which will be the PCI status reg */
5560 ciad >>= 16;
5561 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5562 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5563 /* Issue VFLR */
5564 ciaa = (vf << 16) | 0x80000000;
5565 ciaa |= 0xA8;
5566 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5567 ciad = 0x00008000; /* VFLR */
5568 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5569 ciaa &= 0x7FFFFFFF;
5570 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5571 }
5572 }
5573 }
5574
5575 #endif
5576 /**
5577 * ixgbe_service_timer - Timer Call-back
5578 * @data: pointer to adapter cast into an unsigned long
5579 **/
5580 static void ixgbe_service_timer(unsigned long data)
5581 {
5582 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5583 unsigned long next_event_offset;
5584 bool ready = true;
5585
5586 /* poll faster when waiting for link */
5587 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5588 next_event_offset = HZ / 10;
5589 else
5590 next_event_offset = HZ * 2;
5591
5592 #ifdef CONFIG_PCI_IOV
5593 /*
5594 * don't bother with SR-IOV VF DMA hang check if there are
5595 * no VFs or the link is down
5596 */
5597 if (!adapter->num_vfs ||
5598 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5599 goto normal_timer_service;
5600
5601 /* If we have VFs allocated then we must check for DMA hangs */
5602 ixgbe_check_for_bad_vf(adapter);
5603 next_event_offset = HZ / 50;
5604 adapter->timer_event_accumulator++;
5605
5606 if (adapter->timer_event_accumulator >= 100)
5607 adapter->timer_event_accumulator = 0;
5608 else
5609 ready = false;
5610
5611 normal_timer_service:
5612 #endif
5613 /* Reset the timer */
5614 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5615
5616 if (ready)
5617 ixgbe_service_event_schedule(adapter);
5618 }
5619
5620 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5621 {
5622 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5623 return;
5624
5625 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5626
5627 /* If we're already down or resetting, just bail */
5628 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5629 test_bit(__IXGBE_RESETTING, &adapter->state))
5630 return;
5631
5632 ixgbe_dump(adapter);
5633 netdev_err(adapter->netdev, "Reset adapter\n");
5634 adapter->tx_timeout_count++;
5635
5636 ixgbe_reinit_locked(adapter);
5637 }
5638
5639 /**
5640 * ixgbe_service_task - manages and runs subtasks
5641 * @work: pointer to work_struct containing our data
5642 **/
5643 static void ixgbe_service_task(struct work_struct *work)
5644 {
5645 struct ixgbe_adapter *adapter = container_of(work,
5646 struct ixgbe_adapter,
5647 service_task);
5648
5649 ixgbe_reset_subtask(adapter);
5650 ixgbe_sfp_detection_subtask(adapter);
5651 ixgbe_sfp_link_config_subtask(adapter);
5652 ixgbe_check_overtemp_subtask(adapter);
5653 ixgbe_watchdog_subtask(adapter);
5654 ixgbe_fdir_reinit_subtask(adapter);
5655 ixgbe_check_hang_subtask(adapter);
5656
5657 ixgbe_service_event_complete(adapter);
5658 }
5659
5660 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5661 struct ixgbe_tx_buffer *first,
5662 u8 *hdr_len)
5663 {
5664 struct sk_buff *skb = first->skb;
5665 u32 vlan_macip_lens, type_tucmd;
5666 u32 mss_l4len_idx, l4len;
5667
5668 if (!skb_is_gso(skb))
5669 return 0;
5670
5671 if (skb_header_cloned(skb)) {
5672 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5673 if (err)
5674 return err;
5675 }
5676
5677 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5678 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5679
5680 if (first->protocol == __constant_htons(ETH_P_IP)) {
5681 struct iphdr *iph = ip_hdr(skb);
5682 iph->tot_len = 0;
5683 iph->check = 0;
5684 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5685 iph->daddr, 0,
5686 IPPROTO_TCP,
5687 0);
5688 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5689 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5690 IXGBE_TX_FLAGS_CSUM |
5691 IXGBE_TX_FLAGS_IPV4;
5692 } else if (skb_is_gso_v6(skb)) {
5693 ipv6_hdr(skb)->payload_len = 0;
5694 tcp_hdr(skb)->check =
5695 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5696 &ipv6_hdr(skb)->daddr,
5697 0, IPPROTO_TCP, 0);
5698 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5699 IXGBE_TX_FLAGS_CSUM;
5700 }
5701
5702 /* compute header lengths */
5703 l4len = tcp_hdrlen(skb);
5704 *hdr_len = skb_transport_offset(skb) + l4len;
5705
5706 /* update gso size and bytecount with header size */
5707 first->gso_segs = skb_shinfo(skb)->gso_segs;
5708 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5709
5710 /* mss_l4len_id: use 1 as index for TSO */
5711 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5712 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5713 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5714
5715 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5716 vlan_macip_lens = skb_network_header_len(skb);
5717 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5718 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5719
5720 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5721 mss_l4len_idx);
5722
5723 return 1;
5724 }
5725
5726 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5727 struct ixgbe_tx_buffer *first)
5728 {
5729 struct sk_buff *skb = first->skb;
5730 u32 vlan_macip_lens = 0;
5731 u32 mss_l4len_idx = 0;
5732 u32 type_tucmd = 0;
5733
5734 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5735 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5736 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5737 return;
5738 } else {
5739 u8 l4_hdr = 0;
5740 switch (first->protocol) {
5741 case __constant_htons(ETH_P_IP):
5742 vlan_macip_lens |= skb_network_header_len(skb);
5743 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5744 l4_hdr = ip_hdr(skb)->protocol;
5745 break;
5746 case __constant_htons(ETH_P_IPV6):
5747 vlan_macip_lens |= skb_network_header_len(skb);
5748 l4_hdr = ipv6_hdr(skb)->nexthdr;
5749 break;
5750 default:
5751 if (unlikely(net_ratelimit())) {
5752 dev_warn(tx_ring->dev,
5753 "partial checksum but proto=%x!\n",
5754 first->protocol);
5755 }
5756 break;
5757 }
5758
5759 switch (l4_hdr) {
5760 case IPPROTO_TCP:
5761 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5762 mss_l4len_idx = tcp_hdrlen(skb) <<
5763 IXGBE_ADVTXD_L4LEN_SHIFT;
5764 break;
5765 case IPPROTO_SCTP:
5766 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5767 mss_l4len_idx = sizeof(struct sctphdr) <<
5768 IXGBE_ADVTXD_L4LEN_SHIFT;
5769 break;
5770 case IPPROTO_UDP:
5771 mss_l4len_idx = sizeof(struct udphdr) <<
5772 IXGBE_ADVTXD_L4LEN_SHIFT;
5773 break;
5774 default:
5775 if (unlikely(net_ratelimit())) {
5776 dev_warn(tx_ring->dev,
5777 "partial checksum but l4 proto=%x!\n",
5778 l4_hdr);
5779 }
5780 break;
5781 }
5782
5783 /* update TX checksum flag */
5784 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
5785 }
5786
5787 /* vlan_macip_lens: MACLEN, VLAN tag */
5788 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5789 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5790
5791 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5792 type_tucmd, mss_l4len_idx);
5793 }
5794
5795 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
5796 {
5797 /* set type for advanced descriptor with frame checksum insertion */
5798 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5799 IXGBE_ADVTXD_DCMD_IFCS |
5800 IXGBE_ADVTXD_DCMD_DEXT);
5801
5802 /* set HW vlan bit if vlan is present */
5803 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
5804 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
5805
5806 /* set segmentation enable bits for TSO/FSO */
5807 #ifdef IXGBE_FCOE
5808 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
5809 #else
5810 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5811 #endif
5812 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
5813
5814 return cmd_type;
5815 }
5816
5817 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5818 u32 tx_flags, unsigned int paylen)
5819 {
5820 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
5821
5822 /* enable L4 checksum for TSO and TX checksum offload */
5823 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5824 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
5825
5826 /* enble IPv4 checksum for TSO */
5827 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5828 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
5829
5830 /* use index 1 context for TSO/FSO/FCOE */
5831 #ifdef IXGBE_FCOE
5832 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5833 #else
5834 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5835 #endif
5836 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5837
5838 /*
5839 * Check Context must be set if Tx switch is enabled, which it
5840 * always is for case where virtual functions are running
5841 */
5842 #ifdef IXGBE_FCOE
5843 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5844 #else
5845 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
5846 #endif
5847 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5848
5849 tx_desc->read.olinfo_status = olinfo_status;
5850 }
5851
5852 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5853 IXGBE_TXD_CMD_RS)
5854
5855 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
5856 struct ixgbe_tx_buffer *first,
5857 const u8 hdr_len)
5858 {
5859 dma_addr_t dma;
5860 struct sk_buff *skb = first->skb;
5861 struct ixgbe_tx_buffer *tx_buffer;
5862 union ixgbe_adv_tx_desc *tx_desc;
5863 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
5864 unsigned int data_len = skb->data_len;
5865 unsigned int size = skb_headlen(skb);
5866 unsigned int paylen = skb->len - hdr_len;
5867 u32 tx_flags = first->tx_flags;
5868 __le32 cmd_type;
5869 u16 i = tx_ring->next_to_use;
5870
5871 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5872
5873 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5874 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5875
5876 #ifdef IXGBE_FCOE
5877 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5878 if (data_len < sizeof(struct fcoe_crc_eof)) {
5879 size -= sizeof(struct fcoe_crc_eof) - data_len;
5880 data_len = 0;
5881 } else {
5882 data_len -= sizeof(struct fcoe_crc_eof);
5883 }
5884 }
5885
5886 #endif
5887 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5888 if (dma_mapping_error(tx_ring->dev, dma))
5889 goto dma_error;
5890
5891 /* record length, and DMA address */
5892 dma_unmap_len_set(first, len, size);
5893 dma_unmap_addr_set(first, dma, dma);
5894
5895 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5896
5897 for (;;) {
5898 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
5899 tx_desc->read.cmd_type_len =
5900 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
5901
5902 i++;
5903 tx_desc++;
5904 if (i == tx_ring->count) {
5905 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5906 i = 0;
5907 }
5908
5909 dma += IXGBE_MAX_DATA_PER_TXD;
5910 size -= IXGBE_MAX_DATA_PER_TXD;
5911
5912 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5913 tx_desc->read.olinfo_status = 0;
5914 }
5915
5916 if (likely(!data_len))
5917 break;
5918
5919 if (unlikely(skb->no_fcs))
5920 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
5921 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
5922
5923 i++;
5924 tx_desc++;
5925 if (i == tx_ring->count) {
5926 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5927 i = 0;
5928 }
5929
5930 #ifdef IXGBE_FCOE
5931 size = min_t(unsigned int, data_len, skb_frag_size(frag));
5932 #else
5933 size = skb_frag_size(frag);
5934 #endif
5935 data_len -= size;
5936
5937 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
5938 DMA_TO_DEVICE);
5939 if (dma_mapping_error(tx_ring->dev, dma))
5940 goto dma_error;
5941
5942 tx_buffer = &tx_ring->tx_buffer_info[i];
5943 dma_unmap_len_set(tx_buffer, len, size);
5944 dma_unmap_addr_set(tx_buffer, dma, dma);
5945
5946 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5947 tx_desc->read.olinfo_status = 0;
5948
5949 frag++;
5950 }
5951
5952 /* write last descriptor with RS and EOP bits */
5953 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
5954 tx_desc->read.cmd_type_len = cmd_type;
5955
5956 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5957
5958 /* set the timestamp */
5959 first->time_stamp = jiffies;
5960
5961 /*
5962 * Force memory writes to complete before letting h/w know there
5963 * are new descriptors to fetch. (Only applicable for weak-ordered
5964 * memory model archs, such as IA-64).
5965 *
5966 * We also need this memory barrier to make certain all of the
5967 * status bits have been updated before next_to_watch is written.
5968 */
5969 wmb();
5970
5971 /* set next_to_watch value indicating a packet is present */
5972 first->next_to_watch = tx_desc;
5973
5974 i++;
5975 if (i == tx_ring->count)
5976 i = 0;
5977
5978 tx_ring->next_to_use = i;
5979
5980 /* notify HW of packet */
5981 writel(i, tx_ring->tail);
5982
5983 return;
5984 dma_error:
5985 dev_err(tx_ring->dev, "TX DMA map failed\n");
5986
5987 /* clear dma mappings for failed tx_buffer_info map */
5988 for (;;) {
5989 tx_buffer = &tx_ring->tx_buffer_info[i];
5990 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
5991 if (tx_buffer == first)
5992 break;
5993 if (i == 0)
5994 i = tx_ring->count;
5995 i--;
5996 }
5997
5998 tx_ring->next_to_use = i;
5999 }
6000
6001 static void ixgbe_atr(struct ixgbe_ring *ring,
6002 struct ixgbe_tx_buffer *first)
6003 {
6004 struct ixgbe_q_vector *q_vector = ring->q_vector;
6005 union ixgbe_atr_hash_dword input = { .dword = 0 };
6006 union ixgbe_atr_hash_dword common = { .dword = 0 };
6007 union {
6008 unsigned char *network;
6009 struct iphdr *ipv4;
6010 struct ipv6hdr *ipv6;
6011 } hdr;
6012 struct tcphdr *th;
6013 __be16 vlan_id;
6014
6015 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6016 if (!q_vector)
6017 return;
6018
6019 /* do nothing if sampling is disabled */
6020 if (!ring->atr_sample_rate)
6021 return;
6022
6023 ring->atr_count++;
6024
6025 /* snag network header to get L4 type and address */
6026 hdr.network = skb_network_header(first->skb);
6027
6028 /* Currently only IPv4/IPv6 with TCP is supported */
6029 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6030 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6031 (first->protocol != __constant_htons(ETH_P_IP) ||
6032 hdr.ipv4->protocol != IPPROTO_TCP))
6033 return;
6034
6035 th = tcp_hdr(first->skb);
6036
6037 /* skip this packet since it is invalid or the socket is closing */
6038 if (!th || th->fin)
6039 return;
6040
6041 /* sample on all syn packets or once every atr sample count */
6042 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6043 return;
6044
6045 /* reset sample count */
6046 ring->atr_count = 0;
6047
6048 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6049
6050 /*
6051 * src and dst are inverted, think how the receiver sees them
6052 *
6053 * The input is broken into two sections, a non-compressed section
6054 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6055 * is XORed together and stored in the compressed dword.
6056 */
6057 input.formatted.vlan_id = vlan_id;
6058
6059 /*
6060 * since src port and flex bytes occupy the same word XOR them together
6061 * and write the value to source port portion of compressed dword
6062 */
6063 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6064 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6065 else
6066 common.port.src ^= th->dest ^ first->protocol;
6067 common.port.dst ^= th->source;
6068
6069 if (first->protocol == __constant_htons(ETH_P_IP)) {
6070 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6071 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6072 } else {
6073 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6074 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6075 hdr.ipv6->saddr.s6_addr32[1] ^
6076 hdr.ipv6->saddr.s6_addr32[2] ^
6077 hdr.ipv6->saddr.s6_addr32[3] ^
6078 hdr.ipv6->daddr.s6_addr32[0] ^
6079 hdr.ipv6->daddr.s6_addr32[1] ^
6080 hdr.ipv6->daddr.s6_addr32[2] ^
6081 hdr.ipv6->daddr.s6_addr32[3];
6082 }
6083
6084 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6085 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6086 input, common, ring->queue_index);
6087 }
6088
6089 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6090 {
6091 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6092 /* Herbert's original patch had:
6093 * smp_mb__after_netif_stop_queue();
6094 * but since that doesn't exist yet, just open code it. */
6095 smp_mb();
6096
6097 /* We need to check again in a case another CPU has just
6098 * made room available. */
6099 if (likely(ixgbe_desc_unused(tx_ring) < size))
6100 return -EBUSY;
6101
6102 /* A reprieve! - use start_queue because it doesn't call schedule */
6103 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6104 ++tx_ring->tx_stats.restart_queue;
6105 return 0;
6106 }
6107
6108 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6109 {
6110 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6111 return 0;
6112 return __ixgbe_maybe_stop_tx(tx_ring, size);
6113 }
6114
6115 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6116 {
6117 struct ixgbe_adapter *adapter = netdev_priv(dev);
6118 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6119 smp_processor_id();
6120 #ifdef IXGBE_FCOE
6121 __be16 protocol = vlan_get_protocol(skb);
6122
6123 if (((protocol == htons(ETH_P_FCOE)) ||
6124 (protocol == htons(ETH_P_FIP))) &&
6125 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6126 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6127 txq += adapter->ring_feature[RING_F_FCOE].mask;
6128 return txq;
6129 }
6130 #endif
6131
6132 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6133 while (unlikely(txq >= dev->real_num_tx_queues))
6134 txq -= dev->real_num_tx_queues;
6135 return txq;
6136 }
6137
6138 return skb_tx_hash(dev, skb);
6139 }
6140
6141 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6142 struct ixgbe_adapter *adapter,
6143 struct ixgbe_ring *tx_ring)
6144 {
6145 struct ixgbe_tx_buffer *first;
6146 int tso;
6147 u32 tx_flags = 0;
6148 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6149 unsigned short f;
6150 #endif
6151 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6152 __be16 protocol = skb->protocol;
6153 u8 hdr_len = 0;
6154
6155 /*
6156 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6157 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6158 * + 2 desc gap to keep tail from touching head,
6159 * + 1 desc for context descriptor,
6160 * otherwise try next time
6161 */
6162 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6163 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6164 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6165 #else
6166 count += skb_shinfo(skb)->nr_frags;
6167 #endif
6168 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6169 tx_ring->tx_stats.tx_busy++;
6170 return NETDEV_TX_BUSY;
6171 }
6172
6173 /* record the location of the first descriptor for this packet */
6174 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6175 first->skb = skb;
6176 first->bytecount = skb->len;
6177 first->gso_segs = 1;
6178
6179 /* if we have a HW VLAN tag being added default to the HW one */
6180 if (vlan_tx_tag_present(skb)) {
6181 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6182 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6183 /* else if it is a SW VLAN check the next protocol and store the tag */
6184 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6185 struct vlan_hdr *vhdr, _vhdr;
6186 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6187 if (!vhdr)
6188 goto out_drop;
6189
6190 protocol = vhdr->h_vlan_encapsulated_proto;
6191 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6192 IXGBE_TX_FLAGS_VLAN_SHIFT;
6193 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6194 }
6195
6196 #ifdef CONFIG_PCI_IOV
6197 /*
6198 * Use the l2switch_enable flag - would be false if the DMA
6199 * Tx switch had been disabled.
6200 */
6201 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6202 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6203
6204 #endif
6205 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6206 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6207 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6208 (skb->priority != TC_PRIO_CONTROL))) {
6209 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6210 tx_flags |= (skb->priority & 0x7) <<
6211 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6212 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6213 struct vlan_ethhdr *vhdr;
6214 if (skb_header_cloned(skb) &&
6215 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6216 goto out_drop;
6217 vhdr = (struct vlan_ethhdr *)skb->data;
6218 vhdr->h_vlan_TCI = htons(tx_flags >>
6219 IXGBE_TX_FLAGS_VLAN_SHIFT);
6220 } else {
6221 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6222 }
6223 }
6224
6225 /* record initial flags and protocol */
6226 first->tx_flags = tx_flags;
6227 first->protocol = protocol;
6228
6229 #ifdef IXGBE_FCOE
6230 /* setup tx offload for FCoE */
6231 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6232 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6233 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6234 if (tso < 0)
6235 goto out_drop;
6236
6237 goto xmit_fcoe;
6238 }
6239
6240 #endif /* IXGBE_FCOE */
6241 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6242 if (tso < 0)
6243 goto out_drop;
6244 else if (!tso)
6245 ixgbe_tx_csum(tx_ring, first);
6246
6247 /* add the ATR filter if ATR is on */
6248 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6249 ixgbe_atr(tx_ring, first);
6250
6251 #ifdef IXGBE_FCOE
6252 xmit_fcoe:
6253 #endif /* IXGBE_FCOE */
6254 ixgbe_tx_map(tx_ring, first, hdr_len);
6255
6256 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6257
6258 return NETDEV_TX_OK;
6259
6260 out_drop:
6261 dev_kfree_skb_any(first->skb);
6262 first->skb = NULL;
6263
6264 return NETDEV_TX_OK;
6265 }
6266
6267 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6268 struct net_device *netdev)
6269 {
6270 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6271 struct ixgbe_ring *tx_ring;
6272
6273 if (skb->len <= 0) {
6274 dev_kfree_skb_any(skb);
6275 return NETDEV_TX_OK;
6276 }
6277
6278 /*
6279 * The minimum packet size for olinfo paylen is 17 so pad the skb
6280 * in order to meet this minimum size requirement.
6281 */
6282 if (skb->len < 17) {
6283 if (skb_padto(skb, 17))
6284 return NETDEV_TX_OK;
6285 skb->len = 17;
6286 }
6287
6288 tx_ring = adapter->tx_ring[skb->queue_mapping];
6289 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6290 }
6291
6292 /**
6293 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6294 * @netdev: network interface device structure
6295 * @p: pointer to an address structure
6296 *
6297 * Returns 0 on success, negative on failure
6298 **/
6299 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6300 {
6301 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6302 struct ixgbe_hw *hw = &adapter->hw;
6303 struct sockaddr *addr = p;
6304
6305 if (!is_valid_ether_addr(addr->sa_data))
6306 return -EADDRNOTAVAIL;
6307
6308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6309 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6310
6311 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6312 IXGBE_RAH_AV);
6313
6314 return 0;
6315 }
6316
6317 static int
6318 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6319 {
6320 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6321 struct ixgbe_hw *hw = &adapter->hw;
6322 u16 value;
6323 int rc;
6324
6325 if (prtad != hw->phy.mdio.prtad)
6326 return -EINVAL;
6327 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6328 if (!rc)
6329 rc = value;
6330 return rc;
6331 }
6332
6333 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6334 u16 addr, u16 value)
6335 {
6336 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6337 struct ixgbe_hw *hw = &adapter->hw;
6338
6339 if (prtad != hw->phy.mdio.prtad)
6340 return -EINVAL;
6341 return hw->phy.ops.write_reg(hw, addr, devad, value);
6342 }
6343
6344 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6345 {
6346 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6347
6348 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6349 }
6350
6351 /**
6352 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6353 * netdev->dev_addrs
6354 * @netdev: network interface device structure
6355 *
6356 * Returns non-zero on failure
6357 **/
6358 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6359 {
6360 int err = 0;
6361 struct ixgbe_adapter *adapter = netdev_priv(dev);
6362 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6363
6364 if (is_valid_ether_addr(mac->san_addr)) {
6365 rtnl_lock();
6366 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6367 rtnl_unlock();
6368 }
6369 return err;
6370 }
6371
6372 /**
6373 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6374 * netdev->dev_addrs
6375 * @netdev: network interface device structure
6376 *
6377 * Returns non-zero on failure
6378 **/
6379 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6380 {
6381 int err = 0;
6382 struct ixgbe_adapter *adapter = netdev_priv(dev);
6383 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6384
6385 if (is_valid_ether_addr(mac->san_addr)) {
6386 rtnl_lock();
6387 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6388 rtnl_unlock();
6389 }
6390 return err;
6391 }
6392
6393 #ifdef CONFIG_NET_POLL_CONTROLLER
6394 /*
6395 * Polling 'interrupt' - used by things like netconsole to send skbs
6396 * without having to re-enable interrupts. It's not called while
6397 * the interrupt routine is executing.
6398 */
6399 static void ixgbe_netpoll(struct net_device *netdev)
6400 {
6401 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6402 int i;
6403
6404 /* if interface is down do nothing */
6405 if (test_bit(__IXGBE_DOWN, &adapter->state))
6406 return;
6407
6408 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6409 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6410 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6411 for (i = 0; i < num_q_vectors; i++) {
6412 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6413 ixgbe_msix_clean_rings(0, q_vector);
6414 }
6415 } else {
6416 ixgbe_intr(adapter->pdev->irq, netdev);
6417 }
6418 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6419 }
6420
6421 #endif
6422 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6423 struct rtnl_link_stats64 *stats)
6424 {
6425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6426 int i;
6427
6428 rcu_read_lock();
6429 for (i = 0; i < adapter->num_rx_queues; i++) {
6430 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6431 u64 bytes, packets;
6432 unsigned int start;
6433
6434 if (ring) {
6435 do {
6436 start = u64_stats_fetch_begin_bh(&ring->syncp);
6437 packets = ring->stats.packets;
6438 bytes = ring->stats.bytes;
6439 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6440 stats->rx_packets += packets;
6441 stats->rx_bytes += bytes;
6442 }
6443 }
6444
6445 for (i = 0; i < adapter->num_tx_queues; i++) {
6446 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6447 u64 bytes, packets;
6448 unsigned int start;
6449
6450 if (ring) {
6451 do {
6452 start = u64_stats_fetch_begin_bh(&ring->syncp);
6453 packets = ring->stats.packets;
6454 bytes = ring->stats.bytes;
6455 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6456 stats->tx_packets += packets;
6457 stats->tx_bytes += bytes;
6458 }
6459 }
6460 rcu_read_unlock();
6461 /* following stats updated by ixgbe_watchdog_task() */
6462 stats->multicast = netdev->stats.multicast;
6463 stats->rx_errors = netdev->stats.rx_errors;
6464 stats->rx_length_errors = netdev->stats.rx_length_errors;
6465 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6466 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6467 return stats;
6468 }
6469
6470 #ifdef CONFIG_IXGBE_DCB
6471 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6472 * #adapter: pointer to ixgbe_adapter
6473 * @tc: number of traffic classes currently enabled
6474 *
6475 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6476 * 802.1Q priority maps to a packet buffer that exists.
6477 */
6478 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6479 {
6480 struct ixgbe_hw *hw = &adapter->hw;
6481 u32 reg, rsave;
6482 int i;
6483
6484 /* 82598 have a static priority to TC mapping that can not
6485 * be changed so no validation is needed.
6486 */
6487 if (hw->mac.type == ixgbe_mac_82598EB)
6488 return;
6489
6490 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6491 rsave = reg;
6492
6493 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6494 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6495
6496 /* If up2tc is out of bounds default to zero */
6497 if (up2tc > tc)
6498 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6499 }
6500
6501 if (reg != rsave)
6502 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6503
6504 return;
6505 }
6506
6507 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6508 * classes.
6509 *
6510 * @netdev: net device to configure
6511 * @tc: number of traffic classes to enable
6512 */
6513 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6514 {
6515 struct ixgbe_adapter *adapter = netdev_priv(dev);
6516 struct ixgbe_hw *hw = &adapter->hw;
6517
6518 /* Multiple traffic classes requires multiple queues */
6519 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6520 e_err(drv, "Enable failed, needs MSI-X\n");
6521 return -EINVAL;
6522 }
6523
6524 /* Hardware supports up to 8 traffic classes */
6525 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6526 (hw->mac.type == ixgbe_mac_82598EB &&
6527 tc < MAX_TRAFFIC_CLASS))
6528 return -EINVAL;
6529
6530 /* Hardware has to reinitialize queues and interrupts to
6531 * match packet buffer alignment. Unfortunately, the
6532 * hardware is not flexible enough to do this dynamically.
6533 */
6534 if (netif_running(dev))
6535 ixgbe_close(dev);
6536 ixgbe_clear_interrupt_scheme(adapter);
6537
6538 if (tc) {
6539 netdev_set_num_tc(dev, tc);
6540 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6541 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6542 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6543
6544 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6545 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6546 } else {
6547 netdev_reset_tc(dev);
6548 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6549
6550 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6551 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6552
6553 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6554 adapter->dcb_cfg.pfc_mode_enable = false;
6555 }
6556
6557 ixgbe_init_interrupt_scheme(adapter);
6558 ixgbe_validate_rtr(adapter, tc);
6559 if (netif_running(dev))
6560 ixgbe_open(dev);
6561
6562 return 0;
6563 }
6564
6565 #endif /* CONFIG_IXGBE_DCB */
6566 void ixgbe_do_reset(struct net_device *netdev)
6567 {
6568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6569
6570 if (netif_running(netdev))
6571 ixgbe_reinit_locked(adapter);
6572 else
6573 ixgbe_reset(adapter);
6574 }
6575
6576 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6577 netdev_features_t features)
6578 {
6579 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6580
6581 #ifdef CONFIG_DCB
6582 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6583 features &= ~NETIF_F_HW_VLAN_RX;
6584 #endif
6585
6586 /* return error if RXHASH is being enabled when RSS is not supported */
6587 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6588 features &= ~NETIF_F_RXHASH;
6589
6590 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6591 if (!(features & NETIF_F_RXCSUM))
6592 features &= ~NETIF_F_LRO;
6593
6594 /* Turn off LRO if not RSC capable */
6595 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6596 features &= ~NETIF_F_LRO;
6597
6598
6599 return features;
6600 }
6601
6602 static int ixgbe_set_features(struct net_device *netdev,
6603 netdev_features_t features)
6604 {
6605 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6606 netdev_features_t changed = netdev->features ^ features;
6607 bool need_reset = false;
6608
6609 /* Make sure RSC matches LRO, reset if change */
6610 if (!(features & NETIF_F_LRO)) {
6611 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6612 need_reset = true;
6613 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6614 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6615 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6616 if (adapter->rx_itr_setting == 1 ||
6617 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6618 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6619 need_reset = true;
6620 } else if ((changed ^ features) & NETIF_F_LRO) {
6621 e_info(probe, "rx-usecs set too low, "
6622 "disabling RSC\n");
6623 }
6624 }
6625
6626 /*
6627 * Check if Flow Director n-tuple support was enabled or disabled. If
6628 * the state changed, we need to reset.
6629 */
6630 if (!(features & NETIF_F_NTUPLE)) {
6631 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6632 /* turn off Flow Director, set ATR and reset */
6633 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6634 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6635 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6636 need_reset = true;
6637 }
6638 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6639 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6640 /* turn off ATR, enable perfect filters and reset */
6641 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6642 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6643 need_reset = true;
6644 }
6645
6646 if (changed & NETIF_F_RXALL)
6647 need_reset = true;
6648
6649 netdev->features = features;
6650 if (need_reset)
6651 ixgbe_do_reset(netdev);
6652
6653 return 0;
6654 }
6655
6656 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6657 struct net_device *dev,
6658 unsigned char *addr,
6659 u16 flags)
6660 {
6661 struct ixgbe_adapter *adapter = netdev_priv(dev);
6662 int err = -EOPNOTSUPP;
6663
6664 if (ndm->ndm_state & NUD_PERMANENT) {
6665 pr_info("%s: FDB only supports static addresses\n",
6666 ixgbe_driver_name);
6667 return -EINVAL;
6668 }
6669
6670 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6671 if (is_unicast_ether_addr(addr))
6672 err = dev_uc_add_excl(dev, addr);
6673 else if (is_multicast_ether_addr(addr))
6674 err = dev_mc_add_excl(dev, addr);
6675 else
6676 err = -EINVAL;
6677 }
6678
6679 /* Only return duplicate errors if NLM_F_EXCL is set */
6680 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6681 err = 0;
6682
6683 return err;
6684 }
6685
6686 static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6687 struct net_device *dev,
6688 unsigned char *addr)
6689 {
6690 struct ixgbe_adapter *adapter = netdev_priv(dev);
6691 int err = -EOPNOTSUPP;
6692
6693 if (ndm->ndm_state & NUD_PERMANENT) {
6694 pr_info("%s: FDB only supports static addresses\n",
6695 ixgbe_driver_name);
6696 return -EINVAL;
6697 }
6698
6699 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6700 if (is_unicast_ether_addr(addr))
6701 err = dev_uc_del(dev, addr);
6702 else if (is_multicast_ether_addr(addr))
6703 err = dev_mc_del(dev, addr);
6704 else
6705 err = -EINVAL;
6706 }
6707
6708 return err;
6709 }
6710
6711 static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6712 struct netlink_callback *cb,
6713 struct net_device *dev,
6714 int idx)
6715 {
6716 struct ixgbe_adapter *adapter = netdev_priv(dev);
6717
6718 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6719 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6720
6721 return idx;
6722 }
6723
6724 static const struct net_device_ops ixgbe_netdev_ops = {
6725 .ndo_open = ixgbe_open,
6726 .ndo_stop = ixgbe_close,
6727 .ndo_start_xmit = ixgbe_xmit_frame,
6728 .ndo_select_queue = ixgbe_select_queue,
6729 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6730 .ndo_validate_addr = eth_validate_addr,
6731 .ndo_set_mac_address = ixgbe_set_mac,
6732 .ndo_change_mtu = ixgbe_change_mtu,
6733 .ndo_tx_timeout = ixgbe_tx_timeout,
6734 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6735 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6736 .ndo_do_ioctl = ixgbe_ioctl,
6737 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6738 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6739 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6740 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
6741 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6742 .ndo_get_stats64 = ixgbe_get_stats64,
6743 #ifdef CONFIG_IXGBE_DCB
6744 .ndo_setup_tc = ixgbe_setup_tc,
6745 #endif
6746 #ifdef CONFIG_NET_POLL_CONTROLLER
6747 .ndo_poll_controller = ixgbe_netpoll,
6748 #endif
6749 #ifdef IXGBE_FCOE
6750 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6751 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6752 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6753 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6754 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6755 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6756 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
6757 #endif /* IXGBE_FCOE */
6758 .ndo_set_features = ixgbe_set_features,
6759 .ndo_fix_features = ixgbe_fix_features,
6760 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6761 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6762 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
6763 };
6764
6765 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6766 const struct ixgbe_info *ii)
6767 {
6768 #ifdef CONFIG_PCI_IOV
6769 struct ixgbe_hw *hw = &adapter->hw;
6770
6771 if (hw->mac.type == ixgbe_mac_82598EB)
6772 return;
6773
6774 /* The 82599 supports up to 64 VFs per physical function
6775 * but this implementation limits allocation to 63 so that
6776 * basic networking resources are still available to the
6777 * physical function
6778 */
6779 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6780 ixgbe_enable_sriov(adapter, ii);
6781 #endif /* CONFIG_PCI_IOV */
6782 }
6783
6784 /**
6785 * ixgbe_probe - Device Initialization Routine
6786 * @pdev: PCI device information struct
6787 * @ent: entry in ixgbe_pci_tbl
6788 *
6789 * Returns 0 on success, negative on failure
6790 *
6791 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6792 * The OS initialization, configuring of the adapter private structure,
6793 * and a hardware reset occur.
6794 **/
6795 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6796 const struct pci_device_id *ent)
6797 {
6798 struct net_device *netdev;
6799 struct ixgbe_adapter *adapter = NULL;
6800 struct ixgbe_hw *hw;
6801 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6802 static int cards_found;
6803 int i, err, pci_using_dac;
6804 u8 part_str[IXGBE_PBANUM_LENGTH];
6805 unsigned int indices = num_possible_cpus();
6806 #ifdef IXGBE_FCOE
6807 u16 device_caps;
6808 #endif
6809 u32 eec;
6810 u16 wol_cap;
6811
6812 /* Catch broken hardware that put the wrong VF device ID in
6813 * the PCIe SR-IOV capability.
6814 */
6815 if (pdev->is_virtfn) {
6816 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6817 pci_name(pdev), pdev->vendor, pdev->device);
6818 return -EINVAL;
6819 }
6820
6821 err = pci_enable_device_mem(pdev);
6822 if (err)
6823 return err;
6824
6825 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6826 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6827 pci_using_dac = 1;
6828 } else {
6829 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6830 if (err) {
6831 err = dma_set_coherent_mask(&pdev->dev,
6832 DMA_BIT_MASK(32));
6833 if (err) {
6834 dev_err(&pdev->dev,
6835 "No usable DMA configuration, aborting\n");
6836 goto err_dma;
6837 }
6838 }
6839 pci_using_dac = 0;
6840 }
6841
6842 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6843 IORESOURCE_MEM), ixgbe_driver_name);
6844 if (err) {
6845 dev_err(&pdev->dev,
6846 "pci_request_selected_regions failed 0x%x\n", err);
6847 goto err_pci_reg;
6848 }
6849
6850 pci_enable_pcie_error_reporting(pdev);
6851
6852 pci_set_master(pdev);
6853 pci_save_state(pdev);
6854
6855 #ifdef CONFIG_IXGBE_DCB
6856 indices *= MAX_TRAFFIC_CLASS;
6857 #endif
6858
6859 if (ii->mac == ixgbe_mac_82598EB)
6860 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6861 else
6862 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6863
6864 #ifdef IXGBE_FCOE
6865 indices += min_t(unsigned int, num_possible_cpus(),
6866 IXGBE_MAX_FCOE_INDICES);
6867 #endif
6868 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6869 if (!netdev) {
6870 err = -ENOMEM;
6871 goto err_alloc_etherdev;
6872 }
6873
6874 SET_NETDEV_DEV(netdev, &pdev->dev);
6875
6876 adapter = netdev_priv(netdev);
6877 pci_set_drvdata(pdev, adapter);
6878
6879 adapter->netdev = netdev;
6880 adapter->pdev = pdev;
6881 hw = &adapter->hw;
6882 hw->back = adapter;
6883 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
6884
6885 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6886 pci_resource_len(pdev, 0));
6887 if (!hw->hw_addr) {
6888 err = -EIO;
6889 goto err_ioremap;
6890 }
6891
6892 for (i = 1; i <= 5; i++) {
6893 if (pci_resource_len(pdev, i) == 0)
6894 continue;
6895 }
6896
6897 netdev->netdev_ops = &ixgbe_netdev_ops;
6898 ixgbe_set_ethtool_ops(netdev);
6899 netdev->watchdog_timeo = 5 * HZ;
6900 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6901
6902 adapter->bd_number = cards_found;
6903
6904 /* Setup hw api */
6905 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6906 hw->mac.type = ii->mac;
6907
6908 /* EEPROM */
6909 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6910 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6911 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6912 if (!(eec & (1 << 8)))
6913 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6914
6915 /* PHY */
6916 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6917 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6918 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6919 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6920 hw->phy.mdio.mmds = 0;
6921 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6922 hw->phy.mdio.dev = netdev;
6923 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6924 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6925
6926 ii->get_invariants(hw);
6927
6928 /* setup the private structure */
6929 err = ixgbe_sw_init(adapter);
6930 if (err)
6931 goto err_sw_init;
6932
6933 /* Make it possible the adapter to be woken up via WOL */
6934 switch (adapter->hw.mac.type) {
6935 case ixgbe_mac_82599EB:
6936 case ixgbe_mac_X540:
6937 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6938 break;
6939 default:
6940 break;
6941 }
6942
6943 /*
6944 * If there is a fan on this device and it has failed log the
6945 * failure.
6946 */
6947 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6948 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6949 if (esdp & IXGBE_ESDP_SDP1)
6950 e_crit(probe, "Fan has stopped, replace the adapter\n");
6951 }
6952
6953 if (allow_unsupported_sfp)
6954 hw->allow_unsupported_sfp = allow_unsupported_sfp;
6955
6956 /* reset_hw fills in the perm_addr as well */
6957 hw->phy.reset_if_overtemp = true;
6958 err = hw->mac.ops.reset_hw(hw);
6959 hw->phy.reset_if_overtemp = false;
6960 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6961 hw->mac.type == ixgbe_mac_82598EB) {
6962 err = 0;
6963 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6964 e_dev_err("failed to load because an unsupported SFP+ "
6965 "module type was detected.\n");
6966 e_dev_err("Reload the driver after installing a supported "
6967 "module.\n");
6968 goto err_sw_init;
6969 } else if (err) {
6970 e_dev_err("HW Init failed: %d\n", err);
6971 goto err_sw_init;
6972 }
6973
6974 ixgbe_probe_vf(adapter, ii);
6975
6976 netdev->features = NETIF_F_SG |
6977 NETIF_F_IP_CSUM |
6978 NETIF_F_IPV6_CSUM |
6979 NETIF_F_HW_VLAN_TX |
6980 NETIF_F_HW_VLAN_RX |
6981 NETIF_F_HW_VLAN_FILTER |
6982 NETIF_F_TSO |
6983 NETIF_F_TSO6 |
6984 NETIF_F_RXHASH |
6985 NETIF_F_RXCSUM;
6986
6987 netdev->hw_features = netdev->features;
6988
6989 switch (adapter->hw.mac.type) {
6990 case ixgbe_mac_82599EB:
6991 case ixgbe_mac_X540:
6992 netdev->features |= NETIF_F_SCTP_CSUM;
6993 netdev->hw_features |= NETIF_F_SCTP_CSUM |
6994 NETIF_F_NTUPLE;
6995 break;
6996 default:
6997 break;
6998 }
6999
7000 netdev->hw_features |= NETIF_F_RXALL;
7001
7002 netdev->vlan_features |= NETIF_F_TSO;
7003 netdev->vlan_features |= NETIF_F_TSO6;
7004 netdev->vlan_features |= NETIF_F_IP_CSUM;
7005 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7006 netdev->vlan_features |= NETIF_F_SG;
7007
7008 netdev->priv_flags |= IFF_UNICAST_FLT;
7009 netdev->priv_flags |= IFF_SUPP_NOFCS;
7010
7011 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7012 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7013 IXGBE_FLAG_DCB_ENABLED);
7014
7015 #ifdef CONFIG_IXGBE_DCB
7016 netdev->dcbnl_ops = &dcbnl_ops;
7017 #endif
7018
7019 #ifdef IXGBE_FCOE
7020 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7021 if (hw->mac.ops.get_device_caps) {
7022 hw->mac.ops.get_device_caps(hw, &device_caps);
7023 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7024 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7025 }
7026 }
7027 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7028 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7029 netdev->vlan_features |= NETIF_F_FSO;
7030 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7031 }
7032 #endif /* IXGBE_FCOE */
7033 if (pci_using_dac) {
7034 netdev->features |= NETIF_F_HIGHDMA;
7035 netdev->vlan_features |= NETIF_F_HIGHDMA;
7036 }
7037
7038 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7039 netdev->hw_features |= NETIF_F_LRO;
7040 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7041 netdev->features |= NETIF_F_LRO;
7042
7043 /* make sure the EEPROM is good */
7044 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7045 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7046 err = -EIO;
7047 goto err_sw_init;
7048 }
7049
7050 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7051 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7052
7053 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7054 e_dev_err("invalid MAC address\n");
7055 err = -EIO;
7056 goto err_sw_init;
7057 }
7058
7059 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7060 (unsigned long) adapter);
7061
7062 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7063 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7064
7065 err = ixgbe_init_interrupt_scheme(adapter);
7066 if (err)
7067 goto err_sw_init;
7068
7069 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7070 netdev->hw_features &= ~NETIF_F_RXHASH;
7071 netdev->features &= ~NETIF_F_RXHASH;
7072 }
7073
7074 /* WOL not supported for all but the following */
7075 adapter->wol = 0;
7076 switch (pdev->device) {
7077 case IXGBE_DEV_ID_82599_SFP:
7078 /* Only these subdevice supports WOL */
7079 switch (pdev->subsystem_device) {
7080 case IXGBE_SUBDEV_ID_82599_560FLR:
7081 /* only support first port */
7082 if (hw->bus.func != 0)
7083 break;
7084 case IXGBE_SUBDEV_ID_82599_SFP:
7085 adapter->wol = IXGBE_WUFC_MAG;
7086 break;
7087 }
7088 break;
7089 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7090 /* All except this subdevice support WOL */
7091 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7092 adapter->wol = IXGBE_WUFC_MAG;
7093 break;
7094 case IXGBE_DEV_ID_82599_KX4:
7095 adapter->wol = IXGBE_WUFC_MAG;
7096 break;
7097 case IXGBE_DEV_ID_X540T:
7098 /* Check eeprom to see if it is enabled */
7099 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7100 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7101
7102 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7103 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7104 (hw->bus.func == 0)))
7105 adapter->wol = IXGBE_WUFC_MAG;
7106 break;
7107 }
7108 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7109
7110 /* save off EEPROM version number */
7111 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7112 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7113
7114 /* pick up the PCI bus settings for reporting later */
7115 hw->mac.ops.get_bus_info(hw);
7116
7117 /* print bus type/speed/width info */
7118 e_dev_info("(PCI Express:%s:%s) %pM\n",
7119 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7120 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7121 "Unknown"),
7122 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7123 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7124 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7125 "Unknown"),
7126 netdev->dev_addr);
7127
7128 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7129 if (err)
7130 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7131 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7132 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7133 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7134 part_str);
7135 else
7136 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7137 hw->mac.type, hw->phy.type, part_str);
7138
7139 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7140 e_dev_warn("PCI-Express bandwidth available for this card is "
7141 "not sufficient for optimal performance.\n");
7142 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7143 "is required.\n");
7144 }
7145
7146 /* reset the hardware with the new settings */
7147 err = hw->mac.ops.start_hw(hw);
7148 if (err == IXGBE_ERR_EEPROM_VERSION) {
7149 /* We are running on a pre-production device, log a warning */
7150 e_dev_warn("This device is a pre-production adapter/LOM. "
7151 "Please be aware there may be issues associated "
7152 "with your hardware. If you are experiencing "
7153 "problems please contact your Intel or hardware "
7154 "representative who provided you with this "
7155 "hardware.\n");
7156 }
7157 strcpy(netdev->name, "eth%d");
7158 err = register_netdev(netdev);
7159 if (err)
7160 goto err_register;
7161
7162 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7163 if (hw->mac.ops.disable_tx_laser &&
7164 ((hw->phy.multispeed_fiber) ||
7165 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7166 (hw->mac.type == ixgbe_mac_82599EB))))
7167 hw->mac.ops.disable_tx_laser(hw);
7168
7169 /* carrier off reporting is important to ethtool even BEFORE open */
7170 netif_carrier_off(netdev);
7171
7172 #ifdef CONFIG_IXGBE_DCA
7173 if (dca_add_requester(&pdev->dev) == 0) {
7174 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7175 ixgbe_setup_dca(adapter);
7176 }
7177 #endif
7178 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7179 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7180 for (i = 0; i < adapter->num_vfs; i++)
7181 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7182 }
7183
7184 /* firmware requires driver version to be 0xFFFFFFFF
7185 * since os does not support feature
7186 */
7187 if (hw->mac.ops.set_fw_drv_ver)
7188 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7189 0xFF);
7190
7191 /* add san mac addr to netdev */
7192 ixgbe_add_sanmac_netdev(netdev);
7193
7194 e_dev_info("%s\n", ixgbe_default_device_descr);
7195 cards_found++;
7196 return 0;
7197
7198 err_register:
7199 ixgbe_release_hw_control(adapter);
7200 ixgbe_clear_interrupt_scheme(adapter);
7201 err_sw_init:
7202 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7203 ixgbe_disable_sriov(adapter);
7204 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7205 iounmap(hw->hw_addr);
7206 err_ioremap:
7207 free_netdev(netdev);
7208 err_alloc_etherdev:
7209 pci_release_selected_regions(pdev,
7210 pci_select_bars(pdev, IORESOURCE_MEM));
7211 err_pci_reg:
7212 err_dma:
7213 pci_disable_device(pdev);
7214 return err;
7215 }
7216
7217 /**
7218 * ixgbe_remove - Device Removal Routine
7219 * @pdev: PCI device information struct
7220 *
7221 * ixgbe_remove is called by the PCI subsystem to alert the driver
7222 * that it should release a PCI device. The could be caused by a
7223 * Hot-Plug event, or because the driver is going to be removed from
7224 * memory.
7225 **/
7226 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7227 {
7228 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7229 struct net_device *netdev = adapter->netdev;
7230
7231 set_bit(__IXGBE_DOWN, &adapter->state);
7232 cancel_work_sync(&adapter->service_task);
7233
7234 #ifdef CONFIG_IXGBE_DCA
7235 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7236 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7237 dca_remove_requester(&pdev->dev);
7238 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7239 }
7240
7241 #endif
7242 #ifdef IXGBE_FCOE
7243 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7244 ixgbe_cleanup_fcoe(adapter);
7245
7246 #endif /* IXGBE_FCOE */
7247
7248 /* remove the added san mac */
7249 ixgbe_del_sanmac_netdev(netdev);
7250
7251 if (netdev->reg_state == NETREG_REGISTERED)
7252 unregister_netdev(netdev);
7253
7254 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7255 if (!(ixgbe_check_vf_assignment(adapter)))
7256 ixgbe_disable_sriov(adapter);
7257 else
7258 e_dev_warn("Unloading driver while VFs are assigned "
7259 "- VFs will not be deallocated\n");
7260 }
7261
7262 ixgbe_clear_interrupt_scheme(adapter);
7263
7264 ixgbe_release_hw_control(adapter);
7265
7266 iounmap(adapter->hw.hw_addr);
7267 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7268 IORESOURCE_MEM));
7269
7270 e_dev_info("complete\n");
7271
7272 free_netdev(netdev);
7273
7274 pci_disable_pcie_error_reporting(pdev);
7275
7276 pci_disable_device(pdev);
7277 }
7278
7279 /**
7280 * ixgbe_io_error_detected - called when PCI error is detected
7281 * @pdev: Pointer to PCI device
7282 * @state: The current pci connection state
7283 *
7284 * This function is called after a PCI bus error affecting
7285 * this device has been detected.
7286 */
7287 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7288 pci_channel_state_t state)
7289 {
7290 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7291 struct net_device *netdev = adapter->netdev;
7292
7293 #ifdef CONFIG_PCI_IOV
7294 struct pci_dev *bdev, *vfdev;
7295 u32 dw0, dw1, dw2, dw3;
7296 int vf, pos;
7297 u16 req_id, pf_func;
7298
7299 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7300 adapter->num_vfs == 0)
7301 goto skip_bad_vf_detection;
7302
7303 bdev = pdev->bus->self;
7304 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7305 bdev = bdev->bus->self;
7306
7307 if (!bdev)
7308 goto skip_bad_vf_detection;
7309
7310 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7311 if (!pos)
7312 goto skip_bad_vf_detection;
7313
7314 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7315 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7316 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7317 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7318
7319 req_id = dw1 >> 16;
7320 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7321 if (!(req_id & 0x0080))
7322 goto skip_bad_vf_detection;
7323
7324 pf_func = req_id & 0x01;
7325 if ((pf_func & 1) == (pdev->devfn & 1)) {
7326 unsigned int device_id;
7327
7328 vf = (req_id & 0x7F) >> 1;
7329 e_dev_err("VF %d has caused a PCIe error\n", vf);
7330 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7331 "%8.8x\tdw3: %8.8x\n",
7332 dw0, dw1, dw2, dw3);
7333 switch (adapter->hw.mac.type) {
7334 case ixgbe_mac_82599EB:
7335 device_id = IXGBE_82599_VF_DEVICE_ID;
7336 break;
7337 case ixgbe_mac_X540:
7338 device_id = IXGBE_X540_VF_DEVICE_ID;
7339 break;
7340 default:
7341 device_id = 0;
7342 break;
7343 }
7344
7345 /* Find the pci device of the offending VF */
7346 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7347 while (vfdev) {
7348 if (vfdev->devfn == (req_id & 0xFF))
7349 break;
7350 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7351 device_id, vfdev);
7352 }
7353 /*
7354 * There's a slim chance the VF could have been hot plugged,
7355 * so if it is no longer present we don't need to issue the
7356 * VFLR. Just clean up the AER in that case.
7357 */
7358 if (vfdev) {
7359 e_dev_err("Issuing VFLR to VF %d\n", vf);
7360 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7361 }
7362
7363 pci_cleanup_aer_uncorrect_error_status(pdev);
7364 }
7365
7366 /*
7367 * Even though the error may have occurred on the other port
7368 * we still need to increment the vf error reference count for
7369 * both ports because the I/O resume function will be called
7370 * for both of them.
7371 */
7372 adapter->vferr_refcount++;
7373
7374 return PCI_ERS_RESULT_RECOVERED;
7375
7376 skip_bad_vf_detection:
7377 #endif /* CONFIG_PCI_IOV */
7378 netif_device_detach(netdev);
7379
7380 if (state == pci_channel_io_perm_failure)
7381 return PCI_ERS_RESULT_DISCONNECT;
7382
7383 if (netif_running(netdev))
7384 ixgbe_down(adapter);
7385 pci_disable_device(pdev);
7386
7387 /* Request a slot reset. */
7388 return PCI_ERS_RESULT_NEED_RESET;
7389 }
7390
7391 /**
7392 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7393 * @pdev: Pointer to PCI device
7394 *
7395 * Restart the card from scratch, as if from a cold-boot.
7396 */
7397 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7398 {
7399 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7400 pci_ers_result_t result;
7401 int err;
7402
7403 if (pci_enable_device_mem(pdev)) {
7404 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7405 result = PCI_ERS_RESULT_DISCONNECT;
7406 } else {
7407 pci_set_master(pdev);
7408 pci_restore_state(pdev);
7409 pci_save_state(pdev);
7410
7411 pci_wake_from_d3(pdev, false);
7412
7413 ixgbe_reset(adapter);
7414 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7415 result = PCI_ERS_RESULT_RECOVERED;
7416 }
7417
7418 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7419 if (err) {
7420 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7421 "failed 0x%0x\n", err);
7422 /* non-fatal, continue */
7423 }
7424
7425 return result;
7426 }
7427
7428 /**
7429 * ixgbe_io_resume - called when traffic can start flowing again.
7430 * @pdev: Pointer to PCI device
7431 *
7432 * This callback is called when the error recovery driver tells us that
7433 * its OK to resume normal operation.
7434 */
7435 static void ixgbe_io_resume(struct pci_dev *pdev)
7436 {
7437 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7438 struct net_device *netdev = adapter->netdev;
7439
7440 #ifdef CONFIG_PCI_IOV
7441 if (adapter->vferr_refcount) {
7442 e_info(drv, "Resuming after VF err\n");
7443 adapter->vferr_refcount--;
7444 return;
7445 }
7446
7447 #endif
7448 if (netif_running(netdev))
7449 ixgbe_up(adapter);
7450
7451 netif_device_attach(netdev);
7452 }
7453
7454 static struct pci_error_handlers ixgbe_err_handler = {
7455 .error_detected = ixgbe_io_error_detected,
7456 .slot_reset = ixgbe_io_slot_reset,
7457 .resume = ixgbe_io_resume,
7458 };
7459
7460 static struct pci_driver ixgbe_driver = {
7461 .name = ixgbe_driver_name,
7462 .id_table = ixgbe_pci_tbl,
7463 .probe = ixgbe_probe,
7464 .remove = __devexit_p(ixgbe_remove),
7465 #ifdef CONFIG_PM
7466 .suspend = ixgbe_suspend,
7467 .resume = ixgbe_resume,
7468 #endif
7469 .shutdown = ixgbe_shutdown,
7470 .err_handler = &ixgbe_err_handler
7471 };
7472
7473 /**
7474 * ixgbe_init_module - Driver Registration Routine
7475 *
7476 * ixgbe_init_module is the first routine called when the driver is
7477 * loaded. All it does is register with the PCI subsystem.
7478 **/
7479 static int __init ixgbe_init_module(void)
7480 {
7481 int ret;
7482 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7483 pr_info("%s\n", ixgbe_copyright);
7484
7485 #ifdef CONFIG_IXGBE_DCA
7486 dca_register_notify(&dca_notifier);
7487 #endif
7488
7489 ret = pci_register_driver(&ixgbe_driver);
7490 return ret;
7491 }
7492
7493 module_init(ixgbe_init_module);
7494
7495 /**
7496 * ixgbe_exit_module - Driver Exit Cleanup Routine
7497 *
7498 * ixgbe_exit_module is called just before the driver is removed
7499 * from memory.
7500 **/
7501 static void __exit ixgbe_exit_module(void)
7502 {
7503 #ifdef CONFIG_IXGBE_DCA
7504 dca_unregister_notify(&dca_notifier);
7505 #endif
7506 pci_unregister_driver(&ixgbe_driver);
7507 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7508 }
7509
7510 #ifdef CONFIG_IXGBE_DCA
7511 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7512 void *p)
7513 {
7514 int ret_val;
7515
7516 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7517 __ixgbe_notify_dca);
7518
7519 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7520 }
7521
7522 #endif /* CONFIG_IXGBE_DCA */
7523
7524 module_exit(ixgbe_exit_module);
7525
7526 /* ixgbe_main.c */
Linux kernel - Deliverables
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