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Merge branch 'for-next' of git://git.infradead.org/users/sameo/mfd-2.6
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #define MAJ 3
59 #define MIN 6
60 #define BUILD 7
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version[] = DRV_VERSION;
64 static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
66
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
71 };
72
73 /* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
109 /* required last entry */
110 {0, }
111 };
112 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
113
114 #ifdef CONFIG_IXGBE_DCA
115 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
116 void *p);
117 static struct notifier_block dca_notifier = {
118 .notifier_call = ixgbe_notify_dca,
119 .next = NULL,
120 .priority = 0
121 };
122 #endif
123
124 #ifdef CONFIG_PCI_IOV
125 static unsigned int max_vfs;
126 module_param(max_vfs, uint, 0);
127 MODULE_PARM_DESC(max_vfs,
128 "Maximum number of virtual functions to allocate per physical function");
129 #endif /* CONFIG_PCI_IOV */
130
131 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
132 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
133 MODULE_LICENSE("GPL");
134 MODULE_VERSION(DRV_VERSION);
135
136 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
137
138 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
139 {
140 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
141 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
142 schedule_work(&adapter->service_task);
143 }
144
145 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
146 {
147 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
148
149 /* flush memory to make sure state is correct before next watchog */
150 smp_mb__before_clear_bit();
151 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
152 }
153
154 struct ixgbe_reg_info {
155 u32 ofs;
156 char *name;
157 };
158
159 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
160
161 /* General Registers */
162 {IXGBE_CTRL, "CTRL"},
163 {IXGBE_STATUS, "STATUS"},
164 {IXGBE_CTRL_EXT, "CTRL_EXT"},
165
166 /* Interrupt Registers */
167 {IXGBE_EICR, "EICR"},
168
169 /* RX Registers */
170 {IXGBE_SRRCTL(0), "SRRCTL"},
171 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
172 {IXGBE_RDLEN(0), "RDLEN"},
173 {IXGBE_RDH(0), "RDH"},
174 {IXGBE_RDT(0), "RDT"},
175 {IXGBE_RXDCTL(0), "RXDCTL"},
176 {IXGBE_RDBAL(0), "RDBAL"},
177 {IXGBE_RDBAH(0), "RDBAH"},
178
179 /* TX Registers */
180 {IXGBE_TDBAL(0), "TDBAL"},
181 {IXGBE_TDBAH(0), "TDBAH"},
182 {IXGBE_TDLEN(0), "TDLEN"},
183 {IXGBE_TDH(0), "TDH"},
184 {IXGBE_TDT(0), "TDT"},
185 {IXGBE_TXDCTL(0), "TXDCTL"},
186
187 /* List Terminator */
188 {}
189 };
190
191
192 /*
193 * ixgbe_regdump - register printout routine
194 */
195 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
196 {
197 int i = 0, j = 0;
198 char rname[16];
199 u32 regs[64];
200
201 switch (reginfo->ofs) {
202 case IXGBE_SRRCTL(0):
203 for (i = 0; i < 64; i++)
204 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
205 break;
206 case IXGBE_DCA_RXCTRL(0):
207 for (i = 0; i < 64; i++)
208 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
209 break;
210 case IXGBE_RDLEN(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
213 break;
214 case IXGBE_RDH(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
217 break;
218 case IXGBE_RDT(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
221 break;
222 case IXGBE_RXDCTL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
225 break;
226 case IXGBE_RDBAL(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
229 break;
230 case IXGBE_RDBAH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
233 break;
234 case IXGBE_TDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
237 break;
238 case IXGBE_TDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
241 break;
242 case IXGBE_TDLEN(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
245 break;
246 case IXGBE_TDH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
249 break;
250 case IXGBE_TDT(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
253 break;
254 case IXGBE_TXDCTL(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
257 break;
258 default:
259 pr_info("%-15s %08x\n", reginfo->name,
260 IXGBE_READ_REG(hw, reginfo->ofs));
261 return;
262 }
263
264 for (i = 0; i < 8; i++) {
265 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
266 pr_err("%-15s", rname);
267 for (j = 0; j < 8; j++)
268 pr_cont(" %08x", regs[i*8+j]);
269 pr_cont("\n");
270 }
271
272 }
273
274 /*
275 * ixgbe_dump - Print registers, tx-rings and rx-rings
276 */
277 static void ixgbe_dump(struct ixgbe_adapter *adapter)
278 {
279 struct net_device *netdev = adapter->netdev;
280 struct ixgbe_hw *hw = &adapter->hw;
281 struct ixgbe_reg_info *reginfo;
282 int n = 0;
283 struct ixgbe_ring *tx_ring;
284 struct ixgbe_tx_buffer *tx_buffer_info;
285 union ixgbe_adv_tx_desc *tx_desc;
286 struct my_u0 { u64 a; u64 b; } *u0;
287 struct ixgbe_ring *rx_ring;
288 union ixgbe_adv_rx_desc *rx_desc;
289 struct ixgbe_rx_buffer *rx_buffer_info;
290 u32 staterr;
291 int i = 0;
292
293 if (!netif_msg_hw(adapter))
294 return;
295
296 /* Print netdevice Info */
297 if (netdev) {
298 dev_info(&adapter->pdev->dev, "Net device Info\n");
299 pr_info("Device Name state "
300 "trans_start last_rx\n");
301 pr_info("%-15s %016lX %016lX %016lX\n",
302 netdev->name,
303 netdev->state,
304 netdev->trans_start,
305 netdev->last_rx);
306 }
307
308 /* Print Registers */
309 dev_info(&adapter->pdev->dev, "Register Dump\n");
310 pr_info(" Register Name Value\n");
311 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
312 reginfo->name; reginfo++) {
313 ixgbe_regdump(hw, reginfo);
314 }
315
316 /* Print TX Ring Summary */
317 if (!netdev || !netif_running(netdev))
318 goto exit;
319
320 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
321 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
322 for (n = 0; n < adapter->num_tx_queues; n++) {
323 tx_ring = adapter->tx_ring[n];
324 tx_buffer_info =
325 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
326 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
327 n, tx_ring->next_to_use, tx_ring->next_to_clean,
328 (u64)tx_buffer_info->dma,
329 tx_buffer_info->length,
330 tx_buffer_info->next_to_watch,
331 (u64)tx_buffer_info->time_stamp);
332 }
333
334 /* Print TX Rings */
335 if (!netif_msg_tx_done(adapter))
336 goto rx_ring_summary;
337
338 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
339
340 /* Transmit Descriptor Formats
341 *
342 * Advanced Transmit Descriptor
343 * +--------------------------------------------------------------+
344 * 0 | Buffer Address [63:0] |
345 * +--------------------------------------------------------------+
346 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
347 * +--------------------------------------------------------------+
348 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
349 */
350
351 for (n = 0; n < adapter->num_tx_queues; n++) {
352 tx_ring = adapter->tx_ring[n];
353 pr_info("------------------------------------\n");
354 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
355 pr_info("------------------------------------\n");
356 pr_info("T [desc] [address 63:0 ] "
357 "[PlPOIdStDDt Ln] [bi->dma ] "
358 "leng ntw timestamp bi->skb\n");
359
360 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
361 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
362 tx_buffer_info = &tx_ring->tx_buffer_info[i];
363 u0 = (struct my_u0 *)tx_desc;
364 pr_info("T [0x%03X] %016llX %016llX %016llX"
365 " %04X %p %016llX %p", i,
366 le64_to_cpu(u0->a),
367 le64_to_cpu(u0->b),
368 (u64)tx_buffer_info->dma,
369 tx_buffer_info->length,
370 tx_buffer_info->next_to_watch,
371 (u64)tx_buffer_info->time_stamp,
372 tx_buffer_info->skb);
373 if (i == tx_ring->next_to_use &&
374 i == tx_ring->next_to_clean)
375 pr_cont(" NTC/U\n");
376 else if (i == tx_ring->next_to_use)
377 pr_cont(" NTU\n");
378 else if (i == tx_ring->next_to_clean)
379 pr_cont(" NTC\n");
380 else
381 pr_cont("\n");
382
383 if (netif_msg_pktdata(adapter) &&
384 tx_buffer_info->dma != 0)
385 print_hex_dump(KERN_INFO, "",
386 DUMP_PREFIX_ADDRESS, 16, 1,
387 phys_to_virt(tx_buffer_info->dma),
388 tx_buffer_info->length, true);
389 }
390 }
391
392 /* Print RX Rings Summary */
393 rx_ring_summary:
394 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
395 pr_info("Queue [NTU] [NTC]\n");
396 for (n = 0; n < adapter->num_rx_queues; n++) {
397 rx_ring = adapter->rx_ring[n];
398 pr_info("%5d %5X %5X\n",
399 n, rx_ring->next_to_use, rx_ring->next_to_clean);
400 }
401
402 /* Print RX Rings */
403 if (!netif_msg_rx_status(adapter))
404 goto exit;
405
406 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
407
408 /* Advanced Receive Descriptor (Read) Format
409 * 63 1 0
410 * +-----------------------------------------------------+
411 * 0 | Packet Buffer Address [63:1] |A0/NSE|
412 * +----------------------------------------------+------+
413 * 8 | Header Buffer Address [63:1] | DD |
414 * +-----------------------------------------------------+
415 *
416 *
417 * Advanced Receive Descriptor (Write-Back) Format
418 *
419 * 63 48 47 32 31 30 21 20 16 15 4 3 0
420 * +------------------------------------------------------+
421 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
422 * | Checksum Ident | | | | Type | Type |
423 * +------------------------------------------------------+
424 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
425 * +------------------------------------------------------+
426 * 63 48 47 32 31 20 19 0
427 */
428 for (n = 0; n < adapter->num_rx_queues; n++) {
429 rx_ring = adapter->rx_ring[n];
430 pr_info("------------------------------------\n");
431 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
432 pr_info("------------------------------------\n");
433 pr_info("R [desc] [ PktBuf A0] "
434 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
435 "<-- Adv Rx Read format\n");
436 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
437 "[vl er S cks ln] ---------------- [bi->skb] "
438 "<-- Adv Rx Write-Back format\n");
439
440 for (i = 0; i < rx_ring->count; i++) {
441 rx_buffer_info = &rx_ring->rx_buffer_info[i];
442 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
443 u0 = (struct my_u0 *)rx_desc;
444 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
445 if (staterr & IXGBE_RXD_STAT_DD) {
446 /* Descriptor Done */
447 pr_info("RWB[0x%03X] %016llX "
448 "%016llX ---------------- %p", i,
449 le64_to_cpu(u0->a),
450 le64_to_cpu(u0->b),
451 rx_buffer_info->skb);
452 } else {
453 pr_info("R [0x%03X] %016llX "
454 "%016llX %016llX %p", i,
455 le64_to_cpu(u0->a),
456 le64_to_cpu(u0->b),
457 (u64)rx_buffer_info->dma,
458 rx_buffer_info->skb);
459
460 if (netif_msg_pktdata(adapter)) {
461 print_hex_dump(KERN_INFO, "",
462 DUMP_PREFIX_ADDRESS, 16, 1,
463 phys_to_virt(rx_buffer_info->dma),
464 rx_ring->rx_buf_len, true);
465
466 if (rx_ring->rx_buf_len
467 < IXGBE_RXBUFFER_2K)
468 print_hex_dump(KERN_INFO, "",
469 DUMP_PREFIX_ADDRESS, 16, 1,
470 phys_to_virt(
471 rx_buffer_info->page_dma +
472 rx_buffer_info->page_offset
473 ),
474 PAGE_SIZE/2, true);
475 }
476 }
477
478 if (i == rx_ring->next_to_use)
479 pr_cont(" NTU\n");
480 else if (i == rx_ring->next_to_clean)
481 pr_cont(" NTC\n");
482 else
483 pr_cont("\n");
484
485 }
486 }
487
488 exit:
489 return;
490 }
491
492 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
493 {
494 u32 ctrl_ext;
495
496 /* Let firmware take over control of h/w */
497 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
498 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
499 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
500 }
501
502 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
503 {
504 u32 ctrl_ext;
505
506 /* Let firmware know the driver has taken over */
507 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
509 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
510 }
511
512 /*
513 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
514 * @adapter: pointer to adapter struct
515 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
516 * @queue: queue to map the corresponding interrupt to
517 * @msix_vector: the vector to map to the corresponding queue
518 *
519 */
520 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
521 u8 queue, u8 msix_vector)
522 {
523 u32 ivar, index;
524 struct ixgbe_hw *hw = &adapter->hw;
525 switch (hw->mac.type) {
526 case ixgbe_mac_82598EB:
527 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
528 if (direction == -1)
529 direction = 0;
530 index = (((direction * 64) + queue) >> 2) & 0x1F;
531 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
532 ivar &= ~(0xFF << (8 * (queue & 0x3)));
533 ivar |= (msix_vector << (8 * (queue & 0x3)));
534 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
535 break;
536 case ixgbe_mac_82599EB:
537 case ixgbe_mac_X540:
538 if (direction == -1) {
539 /* other causes */
540 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
541 index = ((queue & 1) * 8);
542 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
543 ivar &= ~(0xFF << index);
544 ivar |= (msix_vector << index);
545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
546 break;
547 } else {
548 /* tx or rx causes */
549 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
550 index = ((16 * (queue & 1)) + (8 * direction));
551 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
552 ivar &= ~(0xFF << index);
553 ivar |= (msix_vector << index);
554 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
555 break;
556 }
557 default:
558 break;
559 }
560 }
561
562 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
563 u64 qmask)
564 {
565 u32 mask;
566
567 switch (adapter->hw.mac.type) {
568 case ixgbe_mac_82598EB:
569 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
571 break;
572 case ixgbe_mac_82599EB:
573 case ixgbe_mac_X540:
574 mask = (qmask & 0xFFFFFFFF);
575 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
576 mask = (qmask >> 32);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
578 break;
579 default:
580 break;
581 }
582 }
583
584 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
585 struct ixgbe_tx_buffer *tx_buffer)
586 {
587 if (tx_buffer->dma) {
588 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
589 dma_unmap_page(ring->dev,
590 tx_buffer->dma,
591 tx_buffer->length,
592 DMA_TO_DEVICE);
593 else
594 dma_unmap_single(ring->dev,
595 tx_buffer->dma,
596 tx_buffer->length,
597 DMA_TO_DEVICE);
598 }
599 tx_buffer->dma = 0;
600 }
601
602 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
603 struct ixgbe_tx_buffer *tx_buffer_info)
604 {
605 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
606 if (tx_buffer_info->skb)
607 dev_kfree_skb_any(tx_buffer_info->skb);
608 tx_buffer_info->skb = NULL;
609 /* tx_buffer_info must be completely set up in the transmit path */
610 }
611
612 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
613 {
614 struct ixgbe_hw *hw = &adapter->hw;
615 struct ixgbe_hw_stats *hwstats = &adapter->stats;
616 u32 data = 0;
617 u32 xoff[8] = {0};
618 int i;
619
620 if ((hw->fc.current_mode == ixgbe_fc_full) ||
621 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
622 switch (hw->mac.type) {
623 case ixgbe_mac_82598EB:
624 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
625 break;
626 default:
627 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
628 }
629 hwstats->lxoffrxc += data;
630
631 /* refill credits (no tx hang) if we received xoff */
632 if (!data)
633 return;
634
635 for (i = 0; i < adapter->num_tx_queues; i++)
636 clear_bit(__IXGBE_HANG_CHECK_ARMED,
637 &adapter->tx_ring[i]->state);
638 return;
639 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
640 return;
641
642 /* update stats for each tc, only valid with PFC enabled */
643 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
644 switch (hw->mac.type) {
645 case ixgbe_mac_82598EB:
646 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
647 break;
648 default:
649 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
650 }
651 hwstats->pxoffrxc[i] += xoff[i];
652 }
653
654 /* disarm tx queues that have received xoff frames */
655 for (i = 0; i < adapter->num_tx_queues; i++) {
656 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
657 u8 tc = tx_ring->dcb_tc;
658
659 if (xoff[tc])
660 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
661 }
662 }
663
664 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
665 {
666 return ring->tx_stats.completed;
667 }
668
669 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
670 {
671 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
672 struct ixgbe_hw *hw = &adapter->hw;
673
674 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
675 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
676
677 if (head != tail)
678 return (head < tail) ?
679 tail - head : (tail + ring->count - head);
680
681 return 0;
682 }
683
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
685 {
686 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
687 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
688 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
689 bool ret = false;
690
691 clear_check_for_tx_hang(tx_ring);
692
693 /*
694 * Check for a hung queue, but be thorough. This verifies
695 * that a transmit has been completed since the previous
696 * check AND there is at least one packet pending. The
697 * ARMED bit is set to indicate a potential hang. The
698 * bit is cleared if a pause frame is received to remove
699 * false hang detection due to PFC or 802.3x frames. By
700 * requiring this to fail twice we avoid races with
701 * pfc clearing the ARMED bit and conditions where we
702 * run the check_tx_hang logic with a transmit completion
703 * pending but without time to complete it yet.
704 */
705 if ((tx_done_old == tx_done) && tx_pending) {
706 /* make sure it is true for two checks in a row */
707 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
708 &tx_ring->state);
709 } else {
710 /* update completed stats and continue */
711 tx_ring->tx_stats.tx_done_old = tx_done;
712 /* reset the countdown */
713 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
714 }
715
716 return ret;
717 }
718
719 /**
720 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
721 * @adapter: driver private struct
722 **/
723 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
724 {
725
726 /* Do the reset outside of interrupt context */
727 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
728 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
729 ixgbe_service_event_schedule(adapter);
730 }
731 }
732
733 /**
734 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
735 * @q_vector: structure containing interrupt and ring information
736 * @tx_ring: tx ring to clean
737 **/
738 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
739 struct ixgbe_ring *tx_ring)
740 {
741 struct ixgbe_adapter *adapter = q_vector->adapter;
742 struct ixgbe_tx_buffer *tx_buffer;
743 union ixgbe_adv_tx_desc *tx_desc;
744 unsigned int total_bytes = 0, total_packets = 0;
745 unsigned int budget = q_vector->tx.work_limit;
746 u16 i = tx_ring->next_to_clean;
747
748 tx_buffer = &tx_ring->tx_buffer_info[i];
749 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
750
751 for (; budget; budget--) {
752 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
753
754 /* if next_to_watch is not set then there is no work pending */
755 if (!eop_desc)
756 break;
757
758 /* if DD is not set pending work has not been completed */
759 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
760 break;
761
762 /* count the packet as being completed */
763 tx_ring->tx_stats.completed++;
764
765 /* clear next_to_watch to prevent false hangs */
766 tx_buffer->next_to_watch = NULL;
767
768 /* prevent any other reads prior to eop_desc being verified */
769 rmb();
770
771 do {
772 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
773 tx_desc->wb.status = 0;
774 if (likely(tx_desc == eop_desc)) {
775 eop_desc = NULL;
776 dev_kfree_skb_any(tx_buffer->skb);
777 tx_buffer->skb = NULL;
778
779 total_bytes += tx_buffer->bytecount;
780 total_packets += tx_buffer->gso_segs;
781 }
782
783 tx_buffer++;
784 tx_desc++;
785 i++;
786 if (unlikely(i == tx_ring->count)) {
787 i = 0;
788
789 tx_buffer = tx_ring->tx_buffer_info;
790 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
791 }
792
793 } while (eop_desc);
794 }
795
796 tx_ring->next_to_clean = i;
797 u64_stats_update_begin(&tx_ring->syncp);
798 tx_ring->stats.bytes += total_bytes;
799 tx_ring->stats.packets += total_packets;
800 u64_stats_update_end(&tx_ring->syncp);
801 q_vector->tx.total_bytes += total_bytes;
802 q_vector->tx.total_packets += total_packets;
803
804 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
805 /* schedule immediate reset if we believe we hung */
806 struct ixgbe_hw *hw = &adapter->hw;
807 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
808 e_err(drv, "Detected Tx Unit Hang\n"
809 " Tx Queue <%d>\n"
810 " TDH, TDT <%x>, <%x>\n"
811 " next_to_use <%x>\n"
812 " next_to_clean <%x>\n"
813 "tx_buffer_info[next_to_clean]\n"
814 " time_stamp <%lx>\n"
815 " jiffies <%lx>\n",
816 tx_ring->queue_index,
817 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
818 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
819 tx_ring->next_to_use, i,
820 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
821
822 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
823
824 e_info(probe,
825 "tx hang %d detected on queue %d, resetting adapter\n",
826 adapter->tx_timeout_count + 1, tx_ring->queue_index);
827
828 /* schedule immediate reset if we believe we hung */
829 ixgbe_tx_timeout_reset(adapter);
830
831 /* the adapter is about to reset, no point in enabling stuff */
832 return true;
833 }
834
835 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
836 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
837 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
838 /* Make sure that anybody stopping the queue after this
839 * sees the new next_to_clean.
840 */
841 smp_mb();
842 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
843 !test_bit(__IXGBE_DOWN, &adapter->state)) {
844 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
845 ++tx_ring->tx_stats.restart_queue;
846 }
847 }
848
849 return !!budget;
850 }
851
852 #ifdef CONFIG_IXGBE_DCA
853 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
854 struct ixgbe_ring *rx_ring,
855 int cpu)
856 {
857 struct ixgbe_hw *hw = &adapter->hw;
858 u32 rxctrl;
859 u8 reg_idx = rx_ring->reg_idx;
860
861 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
862 switch (hw->mac.type) {
863 case ixgbe_mac_82598EB:
864 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
865 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
866 break;
867 case ixgbe_mac_82599EB:
868 case ixgbe_mac_X540:
869 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
870 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
871 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
872 break;
873 default:
874 break;
875 }
876 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
877 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
878 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
879 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
880 }
881
882 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
883 struct ixgbe_ring *tx_ring,
884 int cpu)
885 {
886 struct ixgbe_hw *hw = &adapter->hw;
887 u32 txctrl;
888 u8 reg_idx = tx_ring->reg_idx;
889
890 switch (hw->mac.type) {
891 case ixgbe_mac_82598EB:
892 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
893 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
894 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
895 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
896 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
897 break;
898 case ixgbe_mac_82599EB:
899 case ixgbe_mac_X540:
900 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
901 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
902 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
903 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
904 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
905 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
906 break;
907 default:
908 break;
909 }
910 }
911
912 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
913 {
914 struct ixgbe_adapter *adapter = q_vector->adapter;
915 struct ixgbe_ring *ring;
916 int cpu = get_cpu();
917
918 if (q_vector->cpu == cpu)
919 goto out_no_update;
920
921 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
922 ixgbe_update_tx_dca(adapter, ring, cpu);
923
924 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
925 ixgbe_update_rx_dca(adapter, ring, cpu);
926
927 q_vector->cpu = cpu;
928 out_no_update:
929 put_cpu();
930 }
931
932 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
933 {
934 int num_q_vectors;
935 int i;
936
937 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
938 return;
939
940 /* always use CB2 mode, difference is masked in the CB driver */
941 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
942
943 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
944 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
945 else
946 num_q_vectors = 1;
947
948 for (i = 0; i < num_q_vectors; i++) {
949 adapter->q_vector[i]->cpu = -1;
950 ixgbe_update_dca(adapter->q_vector[i]);
951 }
952 }
953
954 static int __ixgbe_notify_dca(struct device *dev, void *data)
955 {
956 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
957 unsigned long event = *(unsigned long *)data;
958
959 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
960 return 0;
961
962 switch (event) {
963 case DCA_PROVIDER_ADD:
964 /* if we're already enabled, don't do it again */
965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
966 break;
967 if (dca_add_requester(dev) == 0) {
968 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
969 ixgbe_setup_dca(adapter);
970 break;
971 }
972 /* Fall Through since DCA is disabled. */
973 case DCA_PROVIDER_REMOVE:
974 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
975 dca_remove_requester(dev);
976 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
977 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
978 }
979 break;
980 }
981
982 return 0;
983 }
984 #endif /* CONFIG_IXGBE_DCA */
985
986 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
987 struct sk_buff *skb)
988 {
989 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
990 }
991
992 /**
993 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
994 * @adapter: address of board private structure
995 * @rx_desc: advanced rx descriptor
996 *
997 * Returns : true if it is FCoE pkt
998 */
999 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1000 union ixgbe_adv_rx_desc *rx_desc)
1001 {
1002 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1003
1004 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1005 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1006 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1007 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1008 }
1009
1010 /**
1011 * ixgbe_receive_skb - Send a completed packet up the stack
1012 * @adapter: board private structure
1013 * @skb: packet to send up
1014 * @status: hardware indication of status of receive
1015 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1016 * @rx_desc: rx descriptor
1017 **/
1018 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1019 struct sk_buff *skb, u8 status,
1020 struct ixgbe_ring *ring,
1021 union ixgbe_adv_rx_desc *rx_desc)
1022 {
1023 struct ixgbe_adapter *adapter = q_vector->adapter;
1024 struct napi_struct *napi = &q_vector->napi;
1025 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1026 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1027
1028 if (is_vlan && (tag & VLAN_VID_MASK))
1029 __vlan_hwaccel_put_tag(skb, tag);
1030
1031 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1032 napi_gro_receive(napi, skb);
1033 else
1034 netif_rx(skb);
1035 }
1036
1037 /**
1038 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1039 * @adapter: address of board private structure
1040 * @status_err: hardware indication of status of receive
1041 * @skb: skb currently being received and modified
1042 * @status_err: status error value of last descriptor in packet
1043 **/
1044 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1045 union ixgbe_adv_rx_desc *rx_desc,
1046 struct sk_buff *skb,
1047 u32 status_err)
1048 {
1049 skb->ip_summed = CHECKSUM_NONE;
1050
1051 /* Rx csum disabled */
1052 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1053 return;
1054
1055 /* if IP and error */
1056 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1057 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1058 adapter->hw_csum_rx_error++;
1059 return;
1060 }
1061
1062 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1063 return;
1064
1065 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1066 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1067
1068 /*
1069 * 82599 errata, UDP frames with a 0 checksum can be marked as
1070 * checksum errors.
1071 */
1072 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1073 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1074 return;
1075
1076 adapter->hw_csum_rx_error++;
1077 return;
1078 }
1079
1080 /* It must be a TCP or UDP packet with a valid checksum */
1081 skb->ip_summed = CHECKSUM_UNNECESSARY;
1082 }
1083
1084 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1085 {
1086 /*
1087 * Force memory writes to complete before letting h/w
1088 * know there are new descriptors to fetch. (Only
1089 * applicable for weak-ordered memory model archs,
1090 * such as IA-64).
1091 */
1092 wmb();
1093 writel(val, rx_ring->tail);
1094 }
1095
1096 /**
1097 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1098 * @rx_ring: ring to place buffers on
1099 * @cleaned_count: number of buffers to replace
1100 **/
1101 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1102 {
1103 union ixgbe_adv_rx_desc *rx_desc;
1104 struct ixgbe_rx_buffer *bi;
1105 struct sk_buff *skb;
1106 u16 i = rx_ring->next_to_use;
1107
1108 /* do nothing if no valid netdev defined */
1109 if (!rx_ring->netdev)
1110 return;
1111
1112 while (cleaned_count--) {
1113 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1114 bi = &rx_ring->rx_buffer_info[i];
1115 skb = bi->skb;
1116
1117 if (!skb) {
1118 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1119 rx_ring->rx_buf_len);
1120 if (!skb) {
1121 rx_ring->rx_stats.alloc_rx_buff_failed++;
1122 goto no_buffers;
1123 }
1124 /* initialize queue mapping */
1125 skb_record_rx_queue(skb, rx_ring->queue_index);
1126 bi->skb = skb;
1127 }
1128
1129 if (!bi->dma) {
1130 bi->dma = dma_map_single(rx_ring->dev,
1131 skb->data,
1132 rx_ring->rx_buf_len,
1133 DMA_FROM_DEVICE);
1134 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1135 rx_ring->rx_stats.alloc_rx_buff_failed++;
1136 bi->dma = 0;
1137 goto no_buffers;
1138 }
1139 }
1140
1141 if (ring_is_ps_enabled(rx_ring)) {
1142 if (!bi->page) {
1143 bi->page = netdev_alloc_page(rx_ring->netdev);
1144 if (!bi->page) {
1145 rx_ring->rx_stats.alloc_rx_page_failed++;
1146 goto no_buffers;
1147 }
1148 }
1149
1150 if (!bi->page_dma) {
1151 /* use a half page if we're re-using */
1152 bi->page_offset ^= PAGE_SIZE / 2;
1153 bi->page_dma = dma_map_page(rx_ring->dev,
1154 bi->page,
1155 bi->page_offset,
1156 PAGE_SIZE / 2,
1157 DMA_FROM_DEVICE);
1158 if (dma_mapping_error(rx_ring->dev,
1159 bi->page_dma)) {
1160 rx_ring->rx_stats.alloc_rx_page_failed++;
1161 bi->page_dma = 0;
1162 goto no_buffers;
1163 }
1164 }
1165
1166 /* Refresh the desc even if buffer_addrs didn't change
1167 * because each write-back erases this info. */
1168 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1169 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1170 } else {
1171 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1172 rx_desc->read.hdr_addr = 0;
1173 }
1174
1175 i++;
1176 if (i == rx_ring->count)
1177 i = 0;
1178 }
1179
1180 no_buffers:
1181 if (rx_ring->next_to_use != i) {
1182 rx_ring->next_to_use = i;
1183 ixgbe_release_rx_desc(rx_ring, i);
1184 }
1185 }
1186
1187 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1188 {
1189 /* HW will not DMA in data larger than the given buffer, even if it
1190 * parses the (NFS, of course) header to be larger. In that case, it
1191 * fills the header buffer and spills the rest into the page.
1192 */
1193 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1194 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1195 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1196 if (hlen > IXGBE_RX_HDR_SIZE)
1197 hlen = IXGBE_RX_HDR_SIZE;
1198 return hlen;
1199 }
1200
1201 /**
1202 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1203 * @skb: pointer to the last skb in the rsc queue
1204 *
1205 * This function changes a queue full of hw rsc buffers into a completed
1206 * packet. It uses the ->prev pointers to find the first packet and then
1207 * turns it into the frag list owner.
1208 **/
1209 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1210 {
1211 unsigned int frag_list_size = 0;
1212 unsigned int skb_cnt = 1;
1213
1214 while (skb->prev) {
1215 struct sk_buff *prev = skb->prev;
1216 frag_list_size += skb->len;
1217 skb->prev = NULL;
1218 skb = prev;
1219 skb_cnt++;
1220 }
1221
1222 skb_shinfo(skb)->frag_list = skb->next;
1223 skb->next = NULL;
1224 skb->len += frag_list_size;
1225 skb->data_len += frag_list_size;
1226 skb->truesize += frag_list_size;
1227 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1228
1229 return skb;
1230 }
1231
1232 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1233 {
1234 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1235 IXGBE_RXDADV_RSCCNT_MASK);
1236 }
1237
1238 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1239 struct ixgbe_ring *rx_ring,
1240 int budget)
1241 {
1242 struct ixgbe_adapter *adapter = q_vector->adapter;
1243 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1244 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1245 struct sk_buff *skb;
1246 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1247 const int current_node = numa_node_id();
1248 #ifdef IXGBE_FCOE
1249 int ddp_bytes = 0;
1250 #endif /* IXGBE_FCOE */
1251 u32 staterr;
1252 u16 i;
1253 u16 cleaned_count = 0;
1254 bool pkt_is_rsc = false;
1255
1256 i = rx_ring->next_to_clean;
1257 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1258 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1259
1260 while (staterr & IXGBE_RXD_STAT_DD) {
1261 u32 upper_len = 0;
1262
1263 rmb(); /* read descriptor and rx_buffer_info after status DD */
1264
1265 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1266
1267 skb = rx_buffer_info->skb;
1268 rx_buffer_info->skb = NULL;
1269 prefetch(skb->data);
1270
1271 if (ring_is_rsc_enabled(rx_ring))
1272 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1273
1274 /* linear means we are building an skb from multiple pages */
1275 if (!skb_is_nonlinear(skb)) {
1276 u16 hlen;
1277 if (pkt_is_rsc &&
1278 !(staterr & IXGBE_RXD_STAT_EOP) &&
1279 !skb->prev) {
1280 /*
1281 * When HWRSC is enabled, delay unmapping
1282 * of the first packet. It carries the
1283 * header information, HW may still
1284 * access the header after the writeback.
1285 * Only unmap it when EOP is reached
1286 */
1287 IXGBE_RSC_CB(skb)->delay_unmap = true;
1288 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1289 } else {
1290 dma_unmap_single(rx_ring->dev,
1291 rx_buffer_info->dma,
1292 rx_ring->rx_buf_len,
1293 DMA_FROM_DEVICE);
1294 }
1295 rx_buffer_info->dma = 0;
1296
1297 if (ring_is_ps_enabled(rx_ring)) {
1298 hlen = ixgbe_get_hlen(rx_desc);
1299 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1300 } else {
1301 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1302 }
1303
1304 skb_put(skb, hlen);
1305 } else {
1306 /* assume packet split since header is unmapped */
1307 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1308 }
1309
1310 if (upper_len) {
1311 dma_unmap_page(rx_ring->dev,
1312 rx_buffer_info->page_dma,
1313 PAGE_SIZE / 2,
1314 DMA_FROM_DEVICE);
1315 rx_buffer_info->page_dma = 0;
1316 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1317 rx_buffer_info->page,
1318 rx_buffer_info->page_offset,
1319 upper_len);
1320
1321 if ((page_count(rx_buffer_info->page) == 1) &&
1322 (page_to_nid(rx_buffer_info->page) == current_node))
1323 get_page(rx_buffer_info->page);
1324 else
1325 rx_buffer_info->page = NULL;
1326
1327 skb->len += upper_len;
1328 skb->data_len += upper_len;
1329 skb->truesize += PAGE_SIZE / 2;
1330 }
1331
1332 i++;
1333 if (i == rx_ring->count)
1334 i = 0;
1335
1336 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1337 prefetch(next_rxd);
1338 cleaned_count++;
1339
1340 if (pkt_is_rsc) {
1341 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1342 IXGBE_RXDADV_NEXTP_SHIFT;
1343 next_buffer = &rx_ring->rx_buffer_info[nextp];
1344 } else {
1345 next_buffer = &rx_ring->rx_buffer_info[i];
1346 }
1347
1348 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1349 if (ring_is_ps_enabled(rx_ring)) {
1350 rx_buffer_info->skb = next_buffer->skb;
1351 rx_buffer_info->dma = next_buffer->dma;
1352 next_buffer->skb = skb;
1353 next_buffer->dma = 0;
1354 } else {
1355 skb->next = next_buffer->skb;
1356 skb->next->prev = skb;
1357 }
1358 rx_ring->rx_stats.non_eop_descs++;
1359 goto next_desc;
1360 }
1361
1362 if (skb->prev) {
1363 skb = ixgbe_transform_rsc_queue(skb);
1364 /* if we got here without RSC the packet is invalid */
1365 if (!pkt_is_rsc) {
1366 __pskb_trim(skb, 0);
1367 rx_buffer_info->skb = skb;
1368 goto next_desc;
1369 }
1370 }
1371
1372 if (ring_is_rsc_enabled(rx_ring)) {
1373 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1374 dma_unmap_single(rx_ring->dev,
1375 IXGBE_RSC_CB(skb)->dma,
1376 rx_ring->rx_buf_len,
1377 DMA_FROM_DEVICE);
1378 IXGBE_RSC_CB(skb)->dma = 0;
1379 IXGBE_RSC_CB(skb)->delay_unmap = false;
1380 }
1381 }
1382 if (pkt_is_rsc) {
1383 if (ring_is_ps_enabled(rx_ring))
1384 rx_ring->rx_stats.rsc_count +=
1385 skb_shinfo(skb)->nr_frags;
1386 else
1387 rx_ring->rx_stats.rsc_count +=
1388 IXGBE_RSC_CB(skb)->skb_cnt;
1389 rx_ring->rx_stats.rsc_flush++;
1390 }
1391
1392 /* ERR_MASK will only have valid bits if EOP set */
1393 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1394 dev_kfree_skb_any(skb);
1395 goto next_desc;
1396 }
1397
1398 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1399 if (adapter->netdev->features & NETIF_F_RXHASH)
1400 ixgbe_rx_hash(rx_desc, skb);
1401
1402 /* probably a little skewed due to removing CRC */
1403 total_rx_bytes += skb->len;
1404 total_rx_packets++;
1405
1406 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1407 #ifdef IXGBE_FCOE
1408 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1409 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1410 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1411 staterr);
1412 if (!ddp_bytes) {
1413 dev_kfree_skb_any(skb);
1414 goto next_desc;
1415 }
1416 }
1417 #endif /* IXGBE_FCOE */
1418 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1419
1420 budget--;
1421 next_desc:
1422 rx_desc->wb.upper.status_error = 0;
1423
1424 if (!budget)
1425 break;
1426
1427 /* return some buffers to hardware, one at a time is too slow */
1428 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1429 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1430 cleaned_count = 0;
1431 }
1432
1433 /* use prefetched values */
1434 rx_desc = next_rxd;
1435 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1436 }
1437
1438 rx_ring->next_to_clean = i;
1439 cleaned_count = ixgbe_desc_unused(rx_ring);
1440
1441 if (cleaned_count)
1442 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1443
1444 #ifdef IXGBE_FCOE
1445 /* include DDPed FCoE data */
1446 if (ddp_bytes > 0) {
1447 unsigned int mss;
1448
1449 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1450 sizeof(struct fc_frame_header) -
1451 sizeof(struct fcoe_crc_eof);
1452 if (mss > 512)
1453 mss &= ~511;
1454 total_rx_bytes += ddp_bytes;
1455 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1456 }
1457 #endif /* IXGBE_FCOE */
1458
1459 u64_stats_update_begin(&rx_ring->syncp);
1460 rx_ring->stats.packets += total_rx_packets;
1461 rx_ring->stats.bytes += total_rx_bytes;
1462 u64_stats_update_end(&rx_ring->syncp);
1463 q_vector->rx.total_packets += total_rx_packets;
1464 q_vector->rx.total_bytes += total_rx_bytes;
1465
1466 return !!budget;
1467 }
1468
1469 /**
1470 * ixgbe_configure_msix - Configure MSI-X hardware
1471 * @adapter: board private structure
1472 *
1473 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1474 * interrupts.
1475 **/
1476 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1477 {
1478 struct ixgbe_q_vector *q_vector;
1479 int q_vectors, v_idx;
1480 u32 mask;
1481
1482 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1483
1484 /* Populate MSIX to EITR Select */
1485 if (adapter->num_vfs > 32) {
1486 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1487 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1488 }
1489
1490 /*
1491 * Populate the IVAR table and set the ITR values to the
1492 * corresponding register.
1493 */
1494 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1495 struct ixgbe_ring *ring;
1496 q_vector = adapter->q_vector[v_idx];
1497
1498 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1499 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1500
1501 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1502 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1503
1504 if (q_vector->tx.ring && !q_vector->rx.ring) {
1505 /* tx only vector */
1506 if (adapter->tx_itr_setting == 1)
1507 q_vector->itr = IXGBE_10K_ITR;
1508 else
1509 q_vector->itr = adapter->tx_itr_setting;
1510 } else {
1511 /* rx or rx/tx vector */
1512 if (adapter->rx_itr_setting == 1)
1513 q_vector->itr = IXGBE_20K_ITR;
1514 else
1515 q_vector->itr = adapter->rx_itr_setting;
1516 }
1517
1518 ixgbe_write_eitr(q_vector);
1519 }
1520
1521 switch (adapter->hw.mac.type) {
1522 case ixgbe_mac_82598EB:
1523 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1524 v_idx);
1525 break;
1526 case ixgbe_mac_82599EB:
1527 case ixgbe_mac_X540:
1528 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1529 break;
1530 default:
1531 break;
1532 }
1533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1534
1535 /* set up to autoclear timer, and the vectors */
1536 mask = IXGBE_EIMS_ENABLE_MASK;
1537 mask &= ~(IXGBE_EIMS_OTHER |
1538 IXGBE_EIMS_MAILBOX |
1539 IXGBE_EIMS_LSC);
1540
1541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1542 }
1543
1544 enum latency_range {
1545 lowest_latency = 0,
1546 low_latency = 1,
1547 bulk_latency = 2,
1548 latency_invalid = 255
1549 };
1550
1551 /**
1552 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1553 * @q_vector: structure containing interrupt and ring information
1554 * @ring_container: structure containing ring performance data
1555 *
1556 * Stores a new ITR value based on packets and byte
1557 * counts during the last interrupt. The advantage of per interrupt
1558 * computation is faster updates and more accurate ITR for the current
1559 * traffic pattern. Constants in this function were computed
1560 * based on theoretical maximum wire speed and thresholds were set based
1561 * on testing data as well as attempting to minimize response time
1562 * while increasing bulk throughput.
1563 * this functionality is controlled by the InterruptThrottleRate module
1564 * parameter (see ixgbe_param.c)
1565 **/
1566 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1567 struct ixgbe_ring_container *ring_container)
1568 {
1569 u64 bytes_perint;
1570 struct ixgbe_adapter *adapter = q_vector->adapter;
1571 int bytes = ring_container->total_bytes;
1572 int packets = ring_container->total_packets;
1573 u32 timepassed_us;
1574 u8 itr_setting = ring_container->itr;
1575
1576 if (packets == 0)
1577 return;
1578
1579 /* simple throttlerate management
1580 * 0-20MB/s lowest (100000 ints/s)
1581 * 20-100MB/s low (20000 ints/s)
1582 * 100-1249MB/s bulk (8000 ints/s)
1583 */
1584 /* what was last interrupt timeslice? */
1585 timepassed_us = q_vector->itr >> 2;
1586 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1587
1588 switch (itr_setting) {
1589 case lowest_latency:
1590 if (bytes_perint > adapter->eitr_low)
1591 itr_setting = low_latency;
1592 break;
1593 case low_latency:
1594 if (bytes_perint > adapter->eitr_high)
1595 itr_setting = bulk_latency;
1596 else if (bytes_perint <= adapter->eitr_low)
1597 itr_setting = lowest_latency;
1598 break;
1599 case bulk_latency:
1600 if (bytes_perint <= adapter->eitr_high)
1601 itr_setting = low_latency;
1602 break;
1603 }
1604
1605 /* clear work counters since we have the values we need */
1606 ring_container->total_bytes = 0;
1607 ring_container->total_packets = 0;
1608
1609 /* write updated itr to ring container */
1610 ring_container->itr = itr_setting;
1611 }
1612
1613 /**
1614 * ixgbe_write_eitr - write EITR register in hardware specific way
1615 * @q_vector: structure containing interrupt and ring information
1616 *
1617 * This function is made to be called by ethtool and by the driver
1618 * when it needs to update EITR registers at runtime. Hardware
1619 * specific quirks/differences are taken care of here.
1620 */
1621 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1622 {
1623 struct ixgbe_adapter *adapter = q_vector->adapter;
1624 struct ixgbe_hw *hw = &adapter->hw;
1625 int v_idx = q_vector->v_idx;
1626 u32 itr_reg = q_vector->itr;
1627
1628 switch (adapter->hw.mac.type) {
1629 case ixgbe_mac_82598EB:
1630 /* must write high and low 16 bits to reset counter */
1631 itr_reg |= (itr_reg << 16);
1632 break;
1633 case ixgbe_mac_82599EB:
1634 case ixgbe_mac_X540:
1635 /*
1636 * set the WDIS bit to not clear the timer bits and cause an
1637 * immediate assertion of the interrupt
1638 */
1639 itr_reg |= IXGBE_EITR_CNT_WDIS;
1640 break;
1641 default:
1642 break;
1643 }
1644 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1645 }
1646
1647 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1648 {
1649 u32 new_itr = q_vector->itr;
1650 u8 current_itr;
1651
1652 ixgbe_update_itr(q_vector, &q_vector->tx);
1653 ixgbe_update_itr(q_vector, &q_vector->rx);
1654
1655 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1656
1657 switch (current_itr) {
1658 /* counts and packets in update_itr are dependent on these numbers */
1659 case lowest_latency:
1660 new_itr = IXGBE_100K_ITR;
1661 break;
1662 case low_latency:
1663 new_itr = IXGBE_20K_ITR;
1664 break;
1665 case bulk_latency:
1666 new_itr = IXGBE_8K_ITR;
1667 break;
1668 default:
1669 break;
1670 }
1671
1672 if (new_itr != q_vector->itr) {
1673 /* do an exponential smoothing */
1674 new_itr = (10 * new_itr * q_vector->itr) /
1675 ((9 * new_itr) + q_vector->itr);
1676
1677 /* save the algorithm value here */
1678 q_vector->itr = new_itr & IXGBE_MAX_EITR;
1679
1680 ixgbe_write_eitr(q_vector);
1681 }
1682 }
1683
1684 /**
1685 * ixgbe_check_overtemp_subtask - check for over tempurature
1686 * @adapter: pointer to adapter
1687 **/
1688 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1689 {
1690 struct ixgbe_hw *hw = &adapter->hw;
1691 u32 eicr = adapter->interrupt_event;
1692
1693 if (test_bit(__IXGBE_DOWN, &adapter->state))
1694 return;
1695
1696 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1697 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1698 return;
1699
1700 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1701
1702 switch (hw->device_id) {
1703 case IXGBE_DEV_ID_82599_T3_LOM:
1704 /*
1705 * Since the warning interrupt is for both ports
1706 * we don't have to check if:
1707 * - This interrupt wasn't for our port.
1708 * - We may have missed the interrupt so always have to
1709 * check if we got a LSC
1710 */
1711 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1712 !(eicr & IXGBE_EICR_LSC))
1713 return;
1714
1715 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1716 u32 autoneg;
1717 bool link_up = false;
1718
1719 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1720
1721 if (link_up)
1722 return;
1723 }
1724
1725 /* Check if this is not due to overtemp */
1726 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1727 return;
1728
1729 break;
1730 default:
1731 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1732 return;
1733 break;
1734 }
1735 e_crit(drv,
1736 "Network adapter has been stopped because it has over heated. "
1737 "Restart the computer. If the problem persists, "
1738 "power off the system and replace the adapter\n");
1739
1740 adapter->interrupt_event = 0;
1741 }
1742
1743 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1744 {
1745 struct ixgbe_hw *hw = &adapter->hw;
1746
1747 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1748 (eicr & IXGBE_EICR_GPI_SDP1)) {
1749 e_crit(probe, "Fan has stopped, replace the adapter\n");
1750 /* write to clear the interrupt */
1751 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1752 }
1753 }
1754
1755 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1756 {
1757 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1758 return;
1759
1760 switch (adapter->hw.mac.type) {
1761 case ixgbe_mac_82599EB:
1762 /*
1763 * Need to check link state so complete overtemp check
1764 * on service task
1765 */
1766 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1767 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1768 adapter->interrupt_event = eicr;
1769 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1770 ixgbe_service_event_schedule(adapter);
1771 return;
1772 }
1773 return;
1774 case ixgbe_mac_X540:
1775 if (!(eicr & IXGBE_EICR_TS))
1776 return;
1777 break;
1778 default:
1779 return;
1780 }
1781
1782 e_crit(drv,
1783 "Network adapter has been stopped because it has over heated. "
1784 "Restart the computer. If the problem persists, "
1785 "power off the system and replace the adapter\n");
1786 }
1787
1788 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1789 {
1790 struct ixgbe_hw *hw = &adapter->hw;
1791
1792 if (eicr & IXGBE_EICR_GPI_SDP2) {
1793 /* Clear the interrupt */
1794 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1795 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1796 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1797 ixgbe_service_event_schedule(adapter);
1798 }
1799 }
1800
1801 if (eicr & IXGBE_EICR_GPI_SDP1) {
1802 /* Clear the interrupt */
1803 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1804 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1805 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1806 ixgbe_service_event_schedule(adapter);
1807 }
1808 }
1809 }
1810
1811 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1812 {
1813 struct ixgbe_hw *hw = &adapter->hw;
1814
1815 adapter->lsc_int++;
1816 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1817 adapter->link_check_timeout = jiffies;
1818 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1819 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1820 IXGBE_WRITE_FLUSH(hw);
1821 ixgbe_service_event_schedule(adapter);
1822 }
1823 }
1824
1825 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1826 u64 qmask)
1827 {
1828 u32 mask;
1829 struct ixgbe_hw *hw = &adapter->hw;
1830
1831 switch (hw->mac.type) {
1832 case ixgbe_mac_82598EB:
1833 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1834 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1835 break;
1836 case ixgbe_mac_82599EB:
1837 case ixgbe_mac_X540:
1838 mask = (qmask & 0xFFFFFFFF);
1839 if (mask)
1840 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1841 mask = (qmask >> 32);
1842 if (mask)
1843 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1844 break;
1845 default:
1846 break;
1847 }
1848 /* skip the flush */
1849 }
1850
1851 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1852 u64 qmask)
1853 {
1854 u32 mask;
1855 struct ixgbe_hw *hw = &adapter->hw;
1856
1857 switch (hw->mac.type) {
1858 case ixgbe_mac_82598EB:
1859 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1860 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1861 break;
1862 case ixgbe_mac_82599EB:
1863 case ixgbe_mac_X540:
1864 mask = (qmask & 0xFFFFFFFF);
1865 if (mask)
1866 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1867 mask = (qmask >> 32);
1868 if (mask)
1869 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1870 break;
1871 default:
1872 break;
1873 }
1874 /* skip the flush */
1875 }
1876
1877 /**
1878 * ixgbe_irq_enable - Enable default interrupt generation settings
1879 * @adapter: board private structure
1880 **/
1881 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1882 bool flush)
1883 {
1884 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1885
1886 /* don't reenable LSC while waiting for link */
1887 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1888 mask &= ~IXGBE_EIMS_LSC;
1889
1890 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
1891 switch (adapter->hw.mac.type) {
1892 case ixgbe_mac_82599EB:
1893 mask |= IXGBE_EIMS_GPI_SDP0;
1894 break;
1895 case ixgbe_mac_X540:
1896 mask |= IXGBE_EIMS_TS;
1897 break;
1898 default:
1899 break;
1900 }
1901 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1902 mask |= IXGBE_EIMS_GPI_SDP1;
1903 switch (adapter->hw.mac.type) {
1904 case ixgbe_mac_82599EB:
1905 mask |= IXGBE_EIMS_GPI_SDP1;
1906 mask |= IXGBE_EIMS_GPI_SDP2;
1907 case ixgbe_mac_X540:
1908 mask |= IXGBE_EIMS_ECC;
1909 mask |= IXGBE_EIMS_MAILBOX;
1910 break;
1911 default:
1912 break;
1913 }
1914 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1915 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1916 mask |= IXGBE_EIMS_FLOW_DIR;
1917
1918 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1919 if (queues)
1920 ixgbe_irq_enable_queues(adapter, ~0);
1921 if (flush)
1922 IXGBE_WRITE_FLUSH(&adapter->hw);
1923 }
1924
1925 static irqreturn_t ixgbe_msix_other(int irq, void *data)
1926 {
1927 struct ixgbe_adapter *adapter = data;
1928 struct ixgbe_hw *hw = &adapter->hw;
1929 u32 eicr;
1930
1931 /*
1932 * Workaround for Silicon errata. Use clear-by-write instead
1933 * of clear-by-read. Reading with EICS will return the
1934 * interrupt causes without clearing, which later be done
1935 * with the write to EICR.
1936 */
1937 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1938 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1939
1940 if (eicr & IXGBE_EICR_LSC)
1941 ixgbe_check_lsc(adapter);
1942
1943 if (eicr & IXGBE_EICR_MAILBOX)
1944 ixgbe_msg_task(adapter);
1945
1946 switch (hw->mac.type) {
1947 case ixgbe_mac_82599EB:
1948 case ixgbe_mac_X540:
1949 if (eicr & IXGBE_EICR_ECC)
1950 e_info(link, "Received unrecoverable ECC Err, please "
1951 "reboot\n");
1952 /* Handle Flow Director Full threshold interrupt */
1953 if (eicr & IXGBE_EICR_FLOW_DIR) {
1954 int reinit_count = 0;
1955 int i;
1956 for (i = 0; i < adapter->num_tx_queues; i++) {
1957 struct ixgbe_ring *ring = adapter->tx_ring[i];
1958 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1959 &ring->state))
1960 reinit_count++;
1961 }
1962 if (reinit_count) {
1963 /* no more flow director interrupts until after init */
1964 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1965 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1966 ixgbe_service_event_schedule(adapter);
1967 }
1968 }
1969 ixgbe_check_sfp_event(adapter, eicr);
1970 ixgbe_check_overtemp_event(adapter, eicr);
1971 break;
1972 default:
1973 break;
1974 }
1975
1976 ixgbe_check_fan_failure(adapter, eicr);
1977
1978 /* re-enable the original interrupt state, no lsc, no queues */
1979 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1980 ixgbe_irq_enable(adapter, false, false);
1981
1982 return IRQ_HANDLED;
1983 }
1984
1985 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
1986 {
1987 struct ixgbe_q_vector *q_vector = data;
1988
1989 /* EIAM disabled interrupts (on this vector) for us */
1990
1991 if (q_vector->rx.ring || q_vector->tx.ring)
1992 napi_schedule(&q_vector->napi);
1993
1994 return IRQ_HANDLED;
1995 }
1996
1997 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1998 int r_idx)
1999 {
2000 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2001 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2002
2003 rx_ring->q_vector = q_vector;
2004 rx_ring->next = q_vector->rx.ring;
2005 q_vector->rx.ring = rx_ring;
2006 q_vector->rx.count++;
2007 }
2008
2009 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2010 int t_idx)
2011 {
2012 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2013 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2014
2015 tx_ring->q_vector = q_vector;
2016 tx_ring->next = q_vector->tx.ring;
2017 q_vector->tx.ring = tx_ring;
2018 q_vector->tx.count++;
2019 q_vector->tx.work_limit = a->tx_work_limit;
2020 }
2021
2022 /**
2023 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2024 * @adapter: board private structure to initialize
2025 *
2026 * This function maps descriptor rings to the queue-specific vectors
2027 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2028 * one vector per ring/queue, but on a constrained vector budget, we
2029 * group the rings as "efficiently" as possible. You would add new
2030 * mapping configurations in here.
2031 **/
2032 static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2033 {
2034 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2035 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2036 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
2037 int v_start = 0;
2038
2039 /* only one q_vector if MSI-X is disabled. */
2040 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2041 q_vectors = 1;
2042
2043 /*
2044 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2045 * group them so there are multiple queues per vector.
2046 *
2047 * Re-adjusting *qpv takes care of the remainder.
2048 */
2049 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2050 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2051 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
2052 map_vector_to_rxq(adapter, v_start, rxr_idx);
2053 }
2054
2055 /*
2056 * If there are not enough q_vectors for each ring to have it's own
2057 * vector then we must pair up Rx/Tx on a each vector
2058 */
2059 if ((v_start + txr_remaining) > q_vectors)
2060 v_start = 0;
2061
2062 for (; v_start < q_vectors && txr_remaining; v_start++) {
2063 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2064 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2065 map_vector_to_txq(adapter, v_start, txr_idx);
2066 }
2067 }
2068
2069 /**
2070 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2071 * @adapter: board private structure
2072 *
2073 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2074 * interrupts from the kernel.
2075 **/
2076 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2077 {
2078 struct net_device *netdev = adapter->netdev;
2079 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2080 int vector, err;
2081 int ri = 0, ti = 0;
2082
2083 for (vector = 0; vector < q_vectors; vector++) {
2084 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2085 struct msix_entry *entry = &adapter->msix_entries[vector];
2086
2087 if (q_vector->tx.ring && q_vector->rx.ring) {
2088 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2089 "%s-%s-%d", netdev->name, "TxRx", ri++);
2090 ti++;
2091 } else if (q_vector->rx.ring) {
2092 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2093 "%s-%s-%d", netdev->name, "rx", ri++);
2094 } else if (q_vector->tx.ring) {
2095 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2096 "%s-%s-%d", netdev->name, "tx", ti++);
2097 } else {
2098 /* skip this unused q_vector */
2099 continue;
2100 }
2101 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2102 q_vector->name, q_vector);
2103 if (err) {
2104 e_err(probe, "request_irq failed for MSIX interrupt "
2105 "Error: %d\n", err);
2106 goto free_queue_irqs;
2107 }
2108 /* If Flow Director is enabled, set interrupt affinity */
2109 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2110 /* assign the mask for this irq */
2111 irq_set_affinity_hint(entry->vector,
2112 q_vector->affinity_mask);
2113 }
2114 }
2115
2116 err = request_irq(adapter->msix_entries[vector].vector,
2117 ixgbe_msix_other, 0, netdev->name, adapter);
2118 if (err) {
2119 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2120 goto free_queue_irqs;
2121 }
2122
2123 return 0;
2124
2125 free_queue_irqs:
2126 while (vector) {
2127 vector--;
2128 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2129 NULL);
2130 free_irq(adapter->msix_entries[vector].vector,
2131 adapter->q_vector[vector]);
2132 }
2133 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2134 pci_disable_msix(adapter->pdev);
2135 kfree(adapter->msix_entries);
2136 adapter->msix_entries = NULL;
2137 return err;
2138 }
2139
2140 /**
2141 * ixgbe_intr - legacy mode Interrupt Handler
2142 * @irq: interrupt number
2143 * @data: pointer to a network interface device structure
2144 **/
2145 static irqreturn_t ixgbe_intr(int irq, void *data)
2146 {
2147 struct ixgbe_adapter *adapter = data;
2148 struct ixgbe_hw *hw = &adapter->hw;
2149 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2150 u32 eicr;
2151
2152 /*
2153 * Workaround for silicon errata on 82598. Mask the interrupts
2154 * before the read of EICR.
2155 */
2156 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2157
2158 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2159 * therefore no explict interrupt disable is necessary */
2160 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2161 if (!eicr) {
2162 /*
2163 * shared interrupt alert!
2164 * make sure interrupts are enabled because the read will
2165 * have disabled interrupts due to EIAM
2166 * finish the workaround of silicon errata on 82598. Unmask
2167 * the interrupt that we masked before the EICR read.
2168 */
2169 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2170 ixgbe_irq_enable(adapter, true, true);
2171 return IRQ_NONE; /* Not our interrupt */
2172 }
2173
2174 if (eicr & IXGBE_EICR_LSC)
2175 ixgbe_check_lsc(adapter);
2176
2177 switch (hw->mac.type) {
2178 case ixgbe_mac_82599EB:
2179 ixgbe_check_sfp_event(adapter, eicr);
2180 /* Fall through */
2181 case ixgbe_mac_X540:
2182 if (eicr & IXGBE_EICR_ECC)
2183 e_info(link, "Received unrecoverable ECC err, please "
2184 "reboot\n");
2185 ixgbe_check_overtemp_event(adapter, eicr);
2186 break;
2187 default:
2188 break;
2189 }
2190
2191 ixgbe_check_fan_failure(adapter, eicr);
2192
2193 if (napi_schedule_prep(&(q_vector->napi))) {
2194 /* would disable interrupts here but EIAM disabled it */
2195 __napi_schedule(&(q_vector->napi));
2196 }
2197
2198 /*
2199 * re-enable link(maybe) and non-queue interrupts, no flush.
2200 * ixgbe_poll will re-enable the queue interrupts
2201 */
2202
2203 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2204 ixgbe_irq_enable(adapter, false, false);
2205
2206 return IRQ_HANDLED;
2207 }
2208
2209 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2210 {
2211 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2212 int i;
2213
2214 /* legacy and MSI only use one vector */
2215 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2216 q_vectors = 1;
2217
2218 for (i = 0; i < adapter->num_rx_queues; i++) {
2219 adapter->rx_ring[i]->q_vector = NULL;
2220 adapter->rx_ring[i]->next = NULL;
2221 }
2222 for (i = 0; i < adapter->num_tx_queues; i++) {
2223 adapter->tx_ring[i]->q_vector = NULL;
2224 adapter->tx_ring[i]->next = NULL;
2225 }
2226
2227 for (i = 0; i < q_vectors; i++) {
2228 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2229 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2230 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
2231 }
2232 }
2233
2234 /**
2235 * ixgbe_request_irq - initialize interrupts
2236 * @adapter: board private structure
2237 *
2238 * Attempts to configure interrupts using the best available
2239 * capabilities of the hardware and kernel.
2240 **/
2241 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2242 {
2243 struct net_device *netdev = adapter->netdev;
2244 int err;
2245
2246 /* map all of the rings to the q_vectors */
2247 ixgbe_map_rings_to_vectors(adapter);
2248
2249 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2250 err = ixgbe_request_msix_irqs(adapter);
2251 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2252 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2253 netdev->name, adapter);
2254 else
2255 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2256 netdev->name, adapter);
2257
2258 if (err) {
2259 e_err(probe, "request_irq failed, Error %d\n", err);
2260
2261 /* place q_vectors and rings back into a known good state */
2262 ixgbe_reset_q_vectors(adapter);
2263 }
2264
2265 return err;
2266 }
2267
2268 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2269 {
2270 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2271 int i, q_vectors;
2272
2273 q_vectors = adapter->num_msix_vectors;
2274 i = q_vectors - 1;
2275 free_irq(adapter->msix_entries[i].vector, adapter);
2276 i--;
2277
2278 for (; i >= 0; i--) {
2279 /* free only the irqs that were actually requested */
2280 if (!adapter->q_vector[i]->rx.ring &&
2281 !adapter->q_vector[i]->tx.ring)
2282 continue;
2283
2284 /* clear the affinity_mask in the IRQ descriptor */
2285 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2286 NULL);
2287
2288 free_irq(adapter->msix_entries[i].vector,
2289 adapter->q_vector[i]);
2290 }
2291 } else {
2292 free_irq(adapter->pdev->irq, adapter);
2293 }
2294
2295 /* clear q_vector state information */
2296 ixgbe_reset_q_vectors(adapter);
2297 }
2298
2299 /**
2300 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2301 * @adapter: board private structure
2302 **/
2303 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2304 {
2305 switch (adapter->hw.mac.type) {
2306 case ixgbe_mac_82598EB:
2307 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2308 break;
2309 case ixgbe_mac_82599EB:
2310 case ixgbe_mac_X540:
2311 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2312 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2314 break;
2315 default:
2316 break;
2317 }
2318 IXGBE_WRITE_FLUSH(&adapter->hw);
2319 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2320 int i;
2321 for (i = 0; i < adapter->num_msix_vectors; i++)
2322 synchronize_irq(adapter->msix_entries[i].vector);
2323 } else {
2324 synchronize_irq(adapter->pdev->irq);
2325 }
2326 }
2327
2328 /**
2329 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2330 *
2331 **/
2332 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2333 {
2334 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2335
2336 /* rx/tx vector */
2337 if (adapter->rx_itr_setting == 1)
2338 q_vector->itr = IXGBE_20K_ITR;
2339 else
2340 q_vector->itr = adapter->rx_itr_setting;
2341
2342 ixgbe_write_eitr(q_vector);
2343
2344 ixgbe_set_ivar(adapter, 0, 0, 0);
2345 ixgbe_set_ivar(adapter, 1, 0, 0);
2346
2347 e_info(hw, "Legacy interrupt IVAR setup done\n");
2348 }
2349
2350 /**
2351 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2352 * @adapter: board private structure
2353 * @ring: structure containing ring specific data
2354 *
2355 * Configure the Tx descriptor ring after a reset.
2356 **/
2357 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2358 struct ixgbe_ring *ring)
2359 {
2360 struct ixgbe_hw *hw = &adapter->hw;
2361 u64 tdba = ring->dma;
2362 int wait_loop = 10;
2363 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2364 u8 reg_idx = ring->reg_idx;
2365
2366 /* disable queue to avoid issues while updating state */
2367 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2368 IXGBE_WRITE_FLUSH(hw);
2369
2370 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2371 (tdba & DMA_BIT_MASK(32)));
2372 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2373 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2374 ring->count * sizeof(union ixgbe_adv_tx_desc));
2375 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2376 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2377 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2378
2379 /*
2380 * set WTHRESH to encourage burst writeback, it should not be set
2381 * higher than 1 when ITR is 0 as it could cause false TX hangs
2382 *
2383 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2384 * to or less than the number of on chip descriptors, which is
2385 * currently 40.
2386 */
2387 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2388 txdctl |= (1 << 16); /* WTHRESH = 1 */
2389 else
2390 txdctl |= (8 << 16); /* WTHRESH = 8 */
2391
2392 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2393 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2394 32; /* PTHRESH = 32 */
2395
2396 /* reinitialize flowdirector state */
2397 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2398 adapter->atr_sample_rate) {
2399 ring->atr_sample_rate = adapter->atr_sample_rate;
2400 ring->atr_count = 0;
2401 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2402 } else {
2403 ring->atr_sample_rate = 0;
2404 }
2405
2406 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2407
2408 /* enable queue */
2409 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2410
2411 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2412 if (hw->mac.type == ixgbe_mac_82598EB &&
2413 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2414 return;
2415
2416 /* poll to verify queue is enabled */
2417 do {
2418 usleep_range(1000, 2000);
2419 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2420 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2421 if (!wait_loop)
2422 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2423 }
2424
2425 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2426 {
2427 struct ixgbe_hw *hw = &adapter->hw;
2428 u32 rttdcs;
2429 u32 reg;
2430 u8 tcs = netdev_get_num_tc(adapter->netdev);
2431
2432 if (hw->mac.type == ixgbe_mac_82598EB)
2433 return;
2434
2435 /* disable the arbiter while setting MTQC */
2436 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2437 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2438 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2439
2440 /* set transmit pool layout */
2441 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2442 case (IXGBE_FLAG_SRIOV_ENABLED):
2443 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2444 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2445 break;
2446 default:
2447 if (!tcs)
2448 reg = IXGBE_MTQC_64Q_1PB;
2449 else if (tcs <= 4)
2450 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2451 else
2452 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2453
2454 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2455
2456 /* Enable Security TX Buffer IFG for multiple pb */
2457 if (tcs) {
2458 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2459 reg |= IXGBE_SECTX_DCB;
2460 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2461 }
2462 break;
2463 }
2464
2465 /* re-enable the arbiter */
2466 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2467 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2468 }
2469
2470 /**
2471 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2472 * @adapter: board private structure
2473 *
2474 * Configure the Tx unit of the MAC after a reset.
2475 **/
2476 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2477 {
2478 struct ixgbe_hw *hw = &adapter->hw;
2479 u32 dmatxctl;
2480 u32 i;
2481
2482 ixgbe_setup_mtqc(adapter);
2483
2484 if (hw->mac.type != ixgbe_mac_82598EB) {
2485 /* DMATXCTL.EN must be before Tx queues are enabled */
2486 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2487 dmatxctl |= IXGBE_DMATXCTL_TE;
2488 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2489 }
2490
2491 /* Setup the HW Tx Head and Tail descriptor pointers */
2492 for (i = 0; i < adapter->num_tx_queues; i++)
2493 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2494 }
2495
2496 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2497
2498 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2499 struct ixgbe_ring *rx_ring)
2500 {
2501 u32 srrctl;
2502 u8 reg_idx = rx_ring->reg_idx;
2503
2504 switch (adapter->hw.mac.type) {
2505 case ixgbe_mac_82598EB: {
2506 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2507 const int mask = feature[RING_F_RSS].mask;
2508 reg_idx = reg_idx & mask;
2509 }
2510 break;
2511 case ixgbe_mac_82599EB:
2512 case ixgbe_mac_X540:
2513 default:
2514 break;
2515 }
2516
2517 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2518
2519 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2520 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2521 if (adapter->num_vfs)
2522 srrctl |= IXGBE_SRRCTL_DROP_EN;
2523
2524 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2525 IXGBE_SRRCTL_BSIZEHDR_MASK;
2526
2527 if (ring_is_ps_enabled(rx_ring)) {
2528 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2529 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2530 #else
2531 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2532 #endif
2533 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2534 } else {
2535 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2536 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2537 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2538 }
2539
2540 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2541 }
2542
2543 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2544 {
2545 struct ixgbe_hw *hw = &adapter->hw;
2546 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2547 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2548 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2549 u32 mrqc = 0, reta = 0;
2550 u32 rxcsum;
2551 int i, j;
2552 u8 tcs = netdev_get_num_tc(adapter->netdev);
2553 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2554
2555 if (tcs)
2556 maxq = min(maxq, adapter->num_tx_queues / tcs);
2557
2558 /* Fill out hash function seeds */
2559 for (i = 0; i < 10; i++)
2560 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2561
2562 /* Fill out redirection table */
2563 for (i = 0, j = 0; i < 128; i++, j++) {
2564 if (j == maxq)
2565 j = 0;
2566 /* reta = 4-byte sliding window of
2567 * 0x00..(indices-1)(indices-1)00..etc. */
2568 reta = (reta << 8) | (j * 0x11);
2569 if ((i & 3) == 3)
2570 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2571 }
2572
2573 /* Disable indicating checksum in descriptor, enables RSS hash */
2574 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2575 rxcsum |= IXGBE_RXCSUM_PCSD;
2576 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2577
2578 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2579 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2580 mrqc = IXGBE_MRQC_RSSEN;
2581 } else {
2582 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2583 | IXGBE_FLAG_SRIOV_ENABLED);
2584
2585 switch (mask) {
2586 case (IXGBE_FLAG_RSS_ENABLED):
2587 if (!tcs)
2588 mrqc = IXGBE_MRQC_RSSEN;
2589 else if (tcs <= 4)
2590 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2591 else
2592 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2593 break;
2594 case (IXGBE_FLAG_SRIOV_ENABLED):
2595 mrqc = IXGBE_MRQC_VMDQEN;
2596 break;
2597 default:
2598 break;
2599 }
2600 }
2601
2602 /* Perform hash on these packet types */
2603 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2604 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2605 | IXGBE_MRQC_RSS_FIELD_IPV6
2606 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2607
2608 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2609 }
2610
2611 /**
2612 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2613 * @adapter: address of board private structure
2614 * @index: index of ring to set
2615 **/
2616 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2617 struct ixgbe_ring *ring)
2618 {
2619 struct ixgbe_hw *hw = &adapter->hw;
2620 u32 rscctrl;
2621 int rx_buf_len;
2622 u8 reg_idx = ring->reg_idx;
2623
2624 if (!ring_is_rsc_enabled(ring))
2625 return;
2626
2627 rx_buf_len = ring->rx_buf_len;
2628 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2629 rscctrl |= IXGBE_RSCCTL_RSCEN;
2630 /*
2631 * we must limit the number of descriptors so that the
2632 * total size of max desc * buf_len is not greater
2633 * than 65535
2634 */
2635 if (ring_is_ps_enabled(ring)) {
2636 #if (MAX_SKB_FRAGS > 16)
2637 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2638 #elif (MAX_SKB_FRAGS > 8)
2639 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2640 #elif (MAX_SKB_FRAGS > 4)
2641 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2642 #else
2643 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2644 #endif
2645 } else {
2646 if (rx_buf_len < IXGBE_RXBUFFER_4K)
2647 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2648 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
2649 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2650 else
2651 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2652 }
2653 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2654 }
2655
2656 /**
2657 * ixgbe_set_uta - Set unicast filter table address
2658 * @adapter: board private structure
2659 *
2660 * The unicast table address is a register array of 32-bit registers.
2661 * The table is meant to be used in a way similar to how the MTA is used
2662 * however due to certain limitations in the hardware it is necessary to
2663 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2664 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2665 **/
2666 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2667 {
2668 struct ixgbe_hw *hw = &adapter->hw;
2669 int i;
2670
2671 /* The UTA table only exists on 82599 hardware and newer */
2672 if (hw->mac.type < ixgbe_mac_82599EB)
2673 return;
2674
2675 /* we only need to do this if VMDq is enabled */
2676 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2677 return;
2678
2679 for (i = 0; i < 128; i++)
2680 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2681 }
2682
2683 #define IXGBE_MAX_RX_DESC_POLL 10
2684 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2685 struct ixgbe_ring *ring)
2686 {
2687 struct ixgbe_hw *hw = &adapter->hw;
2688 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2689 u32 rxdctl;
2690 u8 reg_idx = ring->reg_idx;
2691
2692 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2693 if (hw->mac.type == ixgbe_mac_82598EB &&
2694 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2695 return;
2696
2697 do {
2698 usleep_range(1000, 2000);
2699 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2700 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2701
2702 if (!wait_loop) {
2703 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2704 "the polling period\n", reg_idx);
2705 }
2706 }
2707
2708 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2709 struct ixgbe_ring *ring)
2710 {
2711 struct ixgbe_hw *hw = &adapter->hw;
2712 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2713 u32 rxdctl;
2714 u8 reg_idx = ring->reg_idx;
2715
2716 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2717 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2718
2719 /* write value back with RXDCTL.ENABLE bit cleared */
2720 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2721
2722 if (hw->mac.type == ixgbe_mac_82598EB &&
2723 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2724 return;
2725
2726 /* the hardware may take up to 100us to really disable the rx queue */
2727 do {
2728 udelay(10);
2729 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2730 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2731
2732 if (!wait_loop) {
2733 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2734 "the polling period\n", reg_idx);
2735 }
2736 }
2737
2738 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2739 struct ixgbe_ring *ring)
2740 {
2741 struct ixgbe_hw *hw = &adapter->hw;
2742 u64 rdba = ring->dma;
2743 u32 rxdctl;
2744 u8 reg_idx = ring->reg_idx;
2745
2746 /* disable queue to avoid issues while updating state */
2747 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2748 ixgbe_disable_rx_queue(adapter, ring);
2749
2750 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2751 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2752 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2753 ring->count * sizeof(union ixgbe_adv_rx_desc));
2754 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2755 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2756 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2757
2758 ixgbe_configure_srrctl(adapter, ring);
2759 ixgbe_configure_rscctl(adapter, ring);
2760
2761 /* If operating in IOV mode set RLPML for X540 */
2762 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2763 hw->mac.type == ixgbe_mac_X540) {
2764 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2765 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2766 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2767 }
2768
2769 if (hw->mac.type == ixgbe_mac_82598EB) {
2770 /*
2771 * enable cache line friendly hardware writes:
2772 * PTHRESH=32 descriptors (half the internal cache),
2773 * this also removes ugly rx_no_buffer_count increment
2774 * HTHRESH=4 descriptors (to minimize latency on fetch)
2775 * WTHRESH=8 burst writeback up to two cache lines
2776 */
2777 rxdctl &= ~0x3FFFFF;
2778 rxdctl |= 0x080420;
2779 }
2780
2781 /* enable receive descriptor ring */
2782 rxdctl |= IXGBE_RXDCTL_ENABLE;
2783 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2784
2785 ixgbe_rx_desc_queue_enable(adapter, ring);
2786 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
2787 }
2788
2789 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2790 {
2791 struct ixgbe_hw *hw = &adapter->hw;
2792 int p;
2793
2794 /* PSRTYPE must be initialized in non 82598 adapters */
2795 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2796 IXGBE_PSRTYPE_UDPHDR |
2797 IXGBE_PSRTYPE_IPV4HDR |
2798 IXGBE_PSRTYPE_L2HDR |
2799 IXGBE_PSRTYPE_IPV6HDR;
2800
2801 if (hw->mac.type == ixgbe_mac_82598EB)
2802 return;
2803
2804 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2805 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2806
2807 for (p = 0; p < adapter->num_rx_pools; p++)
2808 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2809 psrtype);
2810 }
2811
2812 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2813 {
2814 struct ixgbe_hw *hw = &adapter->hw;
2815 u32 gcr_ext;
2816 u32 vt_reg_bits;
2817 u32 reg_offset, vf_shift;
2818 u32 vmdctl;
2819 int i;
2820
2821 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2822 return;
2823
2824 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2825 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2826 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2827 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2828
2829 vf_shift = adapter->num_vfs % 32;
2830 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2831
2832 /* Enable only the PF's pool for Tx/Rx */
2833 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2834 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2835 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2836 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2837 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2838
2839 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2840 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2841
2842 /*
2843 * Set up VF register offsets for selected VT Mode,
2844 * i.e. 32 or 64 VFs for SR-IOV
2845 */
2846 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2847 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2848 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2849 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2850
2851 /* enable Tx loopback for VF/PF communication */
2852 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2853 /* Enable MAC Anti-Spoofing */
2854 hw->mac.ops.set_mac_anti_spoofing(hw,
2855 (adapter->num_vfs != 0),
2856 adapter->num_vfs);
2857 /* For VFs that have spoof checking turned off */
2858 for (i = 0; i < adapter->num_vfs; i++) {
2859 if (!adapter->vfinfo[i].spoofchk_enabled)
2860 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2861 }
2862 }
2863
2864 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2865 {
2866 struct ixgbe_hw *hw = &adapter->hw;
2867 struct net_device *netdev = adapter->netdev;
2868 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2869 int rx_buf_len;
2870 struct ixgbe_ring *rx_ring;
2871 int i;
2872 u32 mhadd, hlreg0;
2873
2874 /* Decide whether to use packet split mode or not */
2875 /* On by default */
2876 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2877
2878 /* Do not use packet split if we're in SR-IOV Mode */
2879 if (adapter->num_vfs)
2880 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2881
2882 /* Disable packet split due to 82599 erratum #45 */
2883 if (hw->mac.type == ixgbe_mac_82599EB)
2884 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2885
2886 #ifdef IXGBE_FCOE
2887 /* adjust max frame to be able to do baby jumbo for FCoE */
2888 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2889 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2890 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2891
2892 #endif /* IXGBE_FCOE */
2893 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2894 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2895 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2896 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2897
2898 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2899 }
2900
2901 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2902 max_frame += VLAN_HLEN;
2903
2904 /* Set the RX buffer length according to the mode */
2905 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2906 rx_buf_len = IXGBE_RX_HDR_SIZE;
2907 } else {
2908 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2909 (netdev->mtu <= ETH_DATA_LEN))
2910 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2911 /*
2912 * Make best use of allocation by using all but 1K of a
2913 * power of 2 allocation that will be used for skb->head.
2914 */
2915 else if (max_frame <= IXGBE_RXBUFFER_3K)
2916 rx_buf_len = IXGBE_RXBUFFER_3K;
2917 else if (max_frame <= IXGBE_RXBUFFER_7K)
2918 rx_buf_len = IXGBE_RXBUFFER_7K;
2919 else if (max_frame <= IXGBE_RXBUFFER_15K)
2920 rx_buf_len = IXGBE_RXBUFFER_15K;
2921 else
2922 rx_buf_len = IXGBE_MAX_RXBUFFER;
2923 }
2924
2925 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2926 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2927 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2928 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2929
2930 /*
2931 * Setup the HW Rx Head and Tail Descriptor Pointers and
2932 * the Base and Length of the Rx Descriptor Ring
2933 */
2934 for (i = 0; i < adapter->num_rx_queues; i++) {
2935 rx_ring = adapter->rx_ring[i];
2936 rx_ring->rx_buf_len = rx_buf_len;
2937
2938 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2939 set_ring_ps_enabled(rx_ring);
2940 else
2941 clear_ring_ps_enabled(rx_ring);
2942
2943 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2944 set_ring_rsc_enabled(rx_ring);
2945 else
2946 clear_ring_rsc_enabled(rx_ring);
2947
2948 #ifdef IXGBE_FCOE
2949 if (netdev->features & NETIF_F_FCOE_MTU) {
2950 struct ixgbe_ring_feature *f;
2951 f = &adapter->ring_feature[RING_F_FCOE];
2952 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2953 clear_ring_ps_enabled(rx_ring);
2954 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2955 rx_ring->rx_buf_len =
2956 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2957 } else if (!ring_is_rsc_enabled(rx_ring) &&
2958 !ring_is_ps_enabled(rx_ring)) {
2959 rx_ring->rx_buf_len =
2960 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2961 }
2962 }
2963 #endif /* IXGBE_FCOE */
2964 }
2965 }
2966
2967 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2968 {
2969 struct ixgbe_hw *hw = &adapter->hw;
2970 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2971
2972 switch (hw->mac.type) {
2973 case ixgbe_mac_82598EB:
2974 /*
2975 * For VMDq support of different descriptor types or
2976 * buffer sizes through the use of multiple SRRCTL
2977 * registers, RDRXCTL.MVMEN must be set to 1
2978 *
2979 * also, the manual doesn't mention it clearly but DCA hints
2980 * will only use queue 0's tags unless this bit is set. Side
2981 * effects of setting this bit are only that SRRCTL must be
2982 * fully programmed [0..15]
2983 */
2984 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2985 break;
2986 case ixgbe_mac_82599EB:
2987 case ixgbe_mac_X540:
2988 /* Disable RSC for ACK packets */
2989 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2990 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2991 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2992 /* hardware requires some bits to be set by default */
2993 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2994 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2995 break;
2996 default:
2997 /* We should do nothing since we don't know this hardware */
2998 return;
2999 }
3000
3001 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3002 }
3003
3004 /**
3005 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3006 * @adapter: board private structure
3007 *
3008 * Configure the Rx unit of the MAC after a reset.
3009 **/
3010 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3011 {
3012 struct ixgbe_hw *hw = &adapter->hw;
3013 int i;
3014 u32 rxctrl;
3015
3016 /* disable receives while setting up the descriptors */
3017 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3018 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3019
3020 ixgbe_setup_psrtype(adapter);
3021 ixgbe_setup_rdrxctl(adapter);
3022
3023 /* Program registers for the distribution of queues */
3024 ixgbe_setup_mrqc(adapter);
3025
3026 ixgbe_set_uta(adapter);
3027
3028 /* set_rx_buffer_len must be called before ring initialization */
3029 ixgbe_set_rx_buffer_len(adapter);
3030
3031 /*
3032 * Setup the HW Rx Head and Tail Descriptor Pointers and
3033 * the Base and Length of the Rx Descriptor Ring
3034 */
3035 for (i = 0; i < adapter->num_rx_queues; i++)
3036 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3037
3038 /* disable drop enable for 82598 parts */
3039 if (hw->mac.type == ixgbe_mac_82598EB)
3040 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3041
3042 /* enable all receives */
3043 rxctrl |= IXGBE_RXCTRL_RXEN;
3044 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3045 }
3046
3047 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3048 {
3049 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3050 struct ixgbe_hw *hw = &adapter->hw;
3051 int pool_ndx = adapter->num_vfs;
3052
3053 /* add VID to filter table */
3054 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3055 set_bit(vid, adapter->active_vlans);
3056 }
3057
3058 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3059 {
3060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3061 struct ixgbe_hw *hw = &adapter->hw;
3062 int pool_ndx = adapter->num_vfs;
3063
3064 /* remove VID from filter table */
3065 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3066 clear_bit(vid, adapter->active_vlans);
3067 }
3068
3069 /**
3070 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3071 * @adapter: driver data
3072 */
3073 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3074 {
3075 struct ixgbe_hw *hw = &adapter->hw;
3076 u32 vlnctrl;
3077
3078 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3079 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3080 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3081 }
3082
3083 /**
3084 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3085 * @adapter: driver data
3086 */
3087 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3088 {
3089 struct ixgbe_hw *hw = &adapter->hw;
3090 u32 vlnctrl;
3091
3092 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3093 vlnctrl |= IXGBE_VLNCTRL_VFE;
3094 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3095 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3096 }
3097
3098 /**
3099 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3100 * @adapter: driver data
3101 */
3102 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3103 {
3104 struct ixgbe_hw *hw = &adapter->hw;
3105 u32 vlnctrl;
3106 int i, j;
3107
3108 switch (hw->mac.type) {
3109 case ixgbe_mac_82598EB:
3110 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3111 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3112 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3113 break;
3114 case ixgbe_mac_82599EB:
3115 case ixgbe_mac_X540:
3116 for (i = 0; i < adapter->num_rx_queues; i++) {
3117 j = adapter->rx_ring[i]->reg_idx;
3118 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3119 vlnctrl &= ~IXGBE_RXDCTL_VME;
3120 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3121 }
3122 break;
3123 default:
3124 break;
3125 }
3126 }
3127
3128 /**
3129 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3130 * @adapter: driver data
3131 */
3132 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3133 {
3134 struct ixgbe_hw *hw = &adapter->hw;
3135 u32 vlnctrl;
3136 int i, j;
3137
3138 switch (hw->mac.type) {
3139 case ixgbe_mac_82598EB:
3140 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3141 vlnctrl |= IXGBE_VLNCTRL_VME;
3142 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3143 break;
3144 case ixgbe_mac_82599EB:
3145 case ixgbe_mac_X540:
3146 for (i = 0; i < adapter->num_rx_queues; i++) {
3147 j = adapter->rx_ring[i]->reg_idx;
3148 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3149 vlnctrl |= IXGBE_RXDCTL_VME;
3150 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3151 }
3152 break;
3153 default:
3154 break;
3155 }
3156 }
3157
3158 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3159 {
3160 u16 vid;
3161
3162 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3163
3164 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3165 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3166 }
3167
3168 /**
3169 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3170 * @netdev: network interface device structure
3171 *
3172 * Writes unicast address list to the RAR table.
3173 * Returns: -ENOMEM on failure/insufficient address space
3174 * 0 on no addresses written
3175 * X on writing X addresses to the RAR table
3176 **/
3177 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3178 {
3179 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3180 struct ixgbe_hw *hw = &adapter->hw;
3181 unsigned int vfn = adapter->num_vfs;
3182 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3183 int count = 0;
3184
3185 /* return ENOMEM indicating insufficient memory for addresses */
3186 if (netdev_uc_count(netdev) > rar_entries)
3187 return -ENOMEM;
3188
3189 if (!netdev_uc_empty(netdev) && rar_entries) {
3190 struct netdev_hw_addr *ha;
3191 /* return error if we do not support writing to RAR table */
3192 if (!hw->mac.ops.set_rar)
3193 return -ENOMEM;
3194
3195 netdev_for_each_uc_addr(ha, netdev) {
3196 if (!rar_entries)
3197 break;
3198 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3199 vfn, IXGBE_RAH_AV);
3200 count++;
3201 }
3202 }
3203 /* write the addresses in reverse order to avoid write combining */
3204 for (; rar_entries > 0 ; rar_entries--)
3205 hw->mac.ops.clear_rar(hw, rar_entries);
3206
3207 return count;
3208 }
3209
3210 /**
3211 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3212 * @netdev: network interface device structure
3213 *
3214 * The set_rx_method entry point is called whenever the unicast/multicast
3215 * address list or the network interface flags are updated. This routine is
3216 * responsible for configuring the hardware for proper unicast, multicast and
3217 * promiscuous mode.
3218 **/
3219 void ixgbe_set_rx_mode(struct net_device *netdev)
3220 {
3221 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3222 struct ixgbe_hw *hw = &adapter->hw;
3223 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3224 int count;
3225
3226 /* Check for Promiscuous and All Multicast modes */
3227
3228 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3229
3230 /* set all bits that we expect to always be set */
3231 fctrl |= IXGBE_FCTRL_BAM;
3232 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3233 fctrl |= IXGBE_FCTRL_PMCF;
3234
3235 /* clear the bits we are changing the status of */
3236 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3237
3238 if (netdev->flags & IFF_PROMISC) {
3239 hw->addr_ctrl.user_set_promisc = true;
3240 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3241 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3242 /* don't hardware filter vlans in promisc mode */
3243 ixgbe_vlan_filter_disable(adapter);
3244 } else {
3245 if (netdev->flags & IFF_ALLMULTI) {
3246 fctrl |= IXGBE_FCTRL_MPE;
3247 vmolr |= IXGBE_VMOLR_MPE;
3248 } else {
3249 /*
3250 * Write addresses to the MTA, if the attempt fails
3251 * then we should just turn on promiscuous mode so
3252 * that we can at least receive multicast traffic
3253 */
3254 hw->mac.ops.update_mc_addr_list(hw, netdev);
3255 vmolr |= IXGBE_VMOLR_ROMPE;
3256 }
3257 ixgbe_vlan_filter_enable(adapter);
3258 hw->addr_ctrl.user_set_promisc = false;
3259 /*
3260 * Write addresses to available RAR registers, if there is not
3261 * sufficient space to store all the addresses then enable
3262 * unicast promiscuous mode
3263 */
3264 count = ixgbe_write_uc_addr_list(netdev);
3265 if (count < 0) {
3266 fctrl |= IXGBE_FCTRL_UPE;
3267 vmolr |= IXGBE_VMOLR_ROPE;
3268 }
3269 }
3270
3271 if (adapter->num_vfs) {
3272 ixgbe_restore_vf_multicasts(adapter);
3273 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3274 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3275 IXGBE_VMOLR_ROPE);
3276 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3277 }
3278
3279 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3280
3281 if (netdev->features & NETIF_F_HW_VLAN_RX)
3282 ixgbe_vlan_strip_enable(adapter);
3283 else
3284 ixgbe_vlan_strip_disable(adapter);
3285 }
3286
3287 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3288 {
3289 int q_idx;
3290 struct ixgbe_q_vector *q_vector;
3291 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3292
3293 /* legacy and MSI only use one vector */
3294 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3295 q_vectors = 1;
3296
3297 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3298 q_vector = adapter->q_vector[q_idx];
3299 napi_enable(&q_vector->napi);
3300 }
3301 }
3302
3303 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3304 {
3305 int q_idx;
3306 struct ixgbe_q_vector *q_vector;
3307 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3308
3309 /* legacy and MSI only use one vector */
3310 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3311 q_vectors = 1;
3312
3313 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3314 q_vector = adapter->q_vector[q_idx];
3315 napi_disable(&q_vector->napi);
3316 }
3317 }
3318
3319 #ifdef CONFIG_IXGBE_DCB
3320 /*
3321 * ixgbe_configure_dcb - Configure DCB hardware
3322 * @adapter: ixgbe adapter struct
3323 *
3324 * This is called by the driver on open to configure the DCB hardware.
3325 * This is also called by the gennetlink interface when reconfiguring
3326 * the DCB state.
3327 */
3328 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3329 {
3330 struct ixgbe_hw *hw = &adapter->hw;
3331 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3332
3333 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3334 if (hw->mac.type == ixgbe_mac_82598EB)
3335 netif_set_gso_max_size(adapter->netdev, 65536);
3336 return;
3337 }
3338
3339 if (hw->mac.type == ixgbe_mac_82598EB)
3340 netif_set_gso_max_size(adapter->netdev, 32768);
3341
3342
3343 /* Enable VLAN tag insert/strip */
3344 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3345
3346 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3347
3348 /* reconfigure the hardware */
3349 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3350 #ifdef IXGBE_FCOE
3351 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3352 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3353 #endif
3354 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3355 DCB_TX_CONFIG);
3356 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3357 DCB_RX_CONFIG);
3358 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3359 } else {
3360 struct net_device *dev = adapter->netdev;
3361
3362 if (adapter->ixgbe_ieee_ets) {
3363 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
3364 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3365
3366 ixgbe_dcb_hw_ets(&adapter->hw, ets, max_frame);
3367 }
3368
3369 if (adapter->ixgbe_ieee_pfc) {
3370 struct ieee_pfc *pfc = adapter->ixgbe_ieee_pfc;
3371 u8 *prio_tc = adapter->ixgbe_ieee_ets->prio_tc;
3372
3373 ixgbe_dcb_hw_pfc_config(&adapter->hw, pfc->pfc_en,
3374 prio_tc);
3375 }
3376 }
3377
3378 /* Enable RSS Hash per TC */
3379 if (hw->mac.type != ixgbe_mac_82598EB) {
3380 int i;
3381 u32 reg = 0;
3382
3383 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3384 u8 msb = 0;
3385 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3386
3387 while (cnt >>= 1)
3388 msb++;
3389
3390 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3391 }
3392 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3393 }
3394 }
3395 #endif
3396
3397 /* Additional bittime to account for IXGBE framing */
3398 #define IXGBE_ETH_FRAMING 20
3399
3400 /*
3401 * ixgbe_hpbthresh - calculate high water mark for flow control
3402 *
3403 * @adapter: board private structure to calculate for
3404 * @pb - packet buffer to calculate
3405 */
3406 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3407 {
3408 struct ixgbe_hw *hw = &adapter->hw;
3409 struct net_device *dev = adapter->netdev;
3410 int link, tc, kb, marker;
3411 u32 dv_id, rx_pba;
3412
3413 /* Calculate max LAN frame size */
3414 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3415
3416 #ifdef IXGBE_FCOE
3417 /* FCoE traffic class uses FCOE jumbo frames */
3418 if (dev->features & NETIF_F_FCOE_MTU) {
3419 int fcoe_pb = 0;
3420
3421 #ifdef CONFIG_IXGBE_DCB
3422 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3423
3424 #endif
3425 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3426 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3427 }
3428 #endif
3429
3430 /* Calculate delay value for device */
3431 switch (hw->mac.type) {
3432 case ixgbe_mac_X540:
3433 dv_id = IXGBE_DV_X540(link, tc);
3434 break;
3435 default:
3436 dv_id = IXGBE_DV(link, tc);
3437 break;
3438 }
3439
3440 /* Loopback switch introduces additional latency */
3441 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3442 dv_id += IXGBE_B2BT(tc);
3443
3444 /* Delay value is calculated in bit times convert to KB */
3445 kb = IXGBE_BT2KB(dv_id);
3446 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3447
3448 marker = rx_pba - kb;
3449
3450 /* It is possible that the packet buffer is not large enough
3451 * to provide required headroom. In this case throw an error
3452 * to user and a do the best we can.
3453 */
3454 if (marker < 0) {
3455 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3456 "headroom to support flow control."
3457 "Decrease MTU or number of traffic classes\n", pb);
3458 marker = tc + 1;
3459 }
3460
3461 return marker;
3462 }
3463
3464 /*
3465 * ixgbe_lpbthresh - calculate low water mark for for flow control
3466 *
3467 * @adapter: board private structure to calculate for
3468 * @pb - packet buffer to calculate
3469 */
3470 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3471 {
3472 struct ixgbe_hw *hw = &adapter->hw;
3473 struct net_device *dev = adapter->netdev;
3474 int tc;
3475 u32 dv_id;
3476
3477 /* Calculate max LAN frame size */
3478 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3479
3480 /* Calculate delay value for device */
3481 switch (hw->mac.type) {
3482 case ixgbe_mac_X540:
3483 dv_id = IXGBE_LOW_DV_X540(tc);
3484 break;
3485 default:
3486 dv_id = IXGBE_LOW_DV(tc);
3487 break;
3488 }
3489
3490 /* Delay value is calculated in bit times convert to KB */
3491 return IXGBE_BT2KB(dv_id);
3492 }
3493
3494 /*
3495 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3496 */
3497 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3498 {
3499 struct ixgbe_hw *hw = &adapter->hw;
3500 int num_tc = netdev_get_num_tc(adapter->netdev);
3501 int i;
3502
3503 if (!num_tc)
3504 num_tc = 1;
3505
3506 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3507
3508 for (i = 0; i < num_tc; i++) {
3509 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3510
3511 /* Low water marks must not be larger than high water marks */
3512 if (hw->fc.low_water > hw->fc.high_water[i])
3513 hw->fc.low_water = 0;
3514 }
3515 }
3516
3517 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3518 {
3519 struct ixgbe_hw *hw = &adapter->hw;
3520 int hdrm;
3521 u8 tc = netdev_get_num_tc(adapter->netdev);
3522
3523 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3524 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3525 hdrm = 32 << adapter->fdir_pballoc;
3526 else
3527 hdrm = 0;
3528
3529 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3530 ixgbe_pbthresh_setup(adapter);
3531 }
3532
3533 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3534 {
3535 struct ixgbe_hw *hw = &adapter->hw;
3536 struct hlist_node *node, *node2;
3537 struct ixgbe_fdir_filter *filter;
3538
3539 spin_lock(&adapter->fdir_perfect_lock);
3540
3541 if (!hlist_empty(&adapter->fdir_filter_list))
3542 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3543
3544 hlist_for_each_entry_safe(filter, node, node2,
3545 &adapter->fdir_filter_list, fdir_node) {
3546 ixgbe_fdir_write_perfect_filter_82599(hw,
3547 &filter->filter,
3548 filter->sw_idx,
3549 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3550 IXGBE_FDIR_DROP_QUEUE :
3551 adapter->rx_ring[filter->action]->reg_idx);
3552 }
3553
3554 spin_unlock(&adapter->fdir_perfect_lock);
3555 }
3556
3557 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3558 {
3559 ixgbe_configure_pb(adapter);
3560 #ifdef CONFIG_IXGBE_DCB
3561 ixgbe_configure_dcb(adapter);
3562 #endif
3563
3564 ixgbe_set_rx_mode(adapter->netdev);
3565 ixgbe_restore_vlan(adapter);
3566
3567 #ifdef IXGBE_FCOE
3568 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3569 ixgbe_configure_fcoe(adapter);
3570
3571 #endif /* IXGBE_FCOE */
3572 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3573 ixgbe_init_fdir_signature_82599(&adapter->hw,
3574 adapter->fdir_pballoc);
3575 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3576 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3577 adapter->fdir_pballoc);
3578 ixgbe_fdir_filter_restore(adapter);
3579 }
3580
3581 ixgbe_configure_virtualization(adapter);
3582
3583 ixgbe_configure_tx(adapter);
3584 ixgbe_configure_rx(adapter);
3585 }
3586
3587 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3588 {
3589 switch (hw->phy.type) {
3590 case ixgbe_phy_sfp_avago:
3591 case ixgbe_phy_sfp_ftl:
3592 case ixgbe_phy_sfp_intel:
3593 case ixgbe_phy_sfp_unknown:
3594 case ixgbe_phy_sfp_passive_tyco:
3595 case ixgbe_phy_sfp_passive_unknown:
3596 case ixgbe_phy_sfp_active_unknown:
3597 case ixgbe_phy_sfp_ftl_active:
3598 return true;
3599 case ixgbe_phy_nl:
3600 if (hw->mac.type == ixgbe_mac_82598EB)
3601 return true;
3602 default:
3603 return false;
3604 }
3605 }
3606
3607 /**
3608 * ixgbe_sfp_link_config - set up SFP+ link
3609 * @adapter: pointer to private adapter struct
3610 **/
3611 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3612 {
3613 /*
3614 * We are assuming the worst case scenerio here, and that
3615 * is that an SFP was inserted/removed after the reset
3616 * but before SFP detection was enabled. As such the best
3617 * solution is to just start searching as soon as we start
3618 */
3619 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3620 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3621
3622 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3623 }
3624
3625 /**
3626 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3627 * @hw: pointer to private hardware struct
3628 *
3629 * Returns 0 on success, negative on failure
3630 **/
3631 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3632 {
3633 u32 autoneg;
3634 bool negotiation, link_up = false;
3635 u32 ret = IXGBE_ERR_LINK_SETUP;
3636
3637 if (hw->mac.ops.check_link)
3638 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3639
3640 if (ret)
3641 goto link_cfg_out;
3642
3643 autoneg = hw->phy.autoneg_advertised;
3644 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3645 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3646 &negotiation);
3647 if (ret)
3648 goto link_cfg_out;
3649
3650 if (hw->mac.ops.setup_link)
3651 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3652 link_cfg_out:
3653 return ret;
3654 }
3655
3656 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3657 {
3658 struct ixgbe_hw *hw = &adapter->hw;
3659 u32 gpie = 0;
3660
3661 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3662 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3663 IXGBE_GPIE_OCD;
3664 gpie |= IXGBE_GPIE_EIAME;
3665 /*
3666 * use EIAM to auto-mask when MSI-X interrupt is asserted
3667 * this saves a register write for every interrupt
3668 */
3669 switch (hw->mac.type) {
3670 case ixgbe_mac_82598EB:
3671 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3672 break;
3673 case ixgbe_mac_82599EB:
3674 case ixgbe_mac_X540:
3675 default:
3676 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3677 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3678 break;
3679 }
3680 } else {
3681 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3682 * specifically only auto mask tx and rx interrupts */
3683 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3684 }
3685
3686 /* XXX: to interrupt immediately for EICS writes, enable this */
3687 /* gpie |= IXGBE_GPIE_EIMEN; */
3688
3689 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3690 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3691 gpie |= IXGBE_GPIE_VTMODE_64;
3692 }
3693
3694 /* Enable Thermal over heat sensor interrupt */
3695 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3696 switch (adapter->hw.mac.type) {
3697 case ixgbe_mac_82599EB:
3698 gpie |= IXGBE_SDP0_GPIEN;
3699 break;
3700 case ixgbe_mac_X540:
3701 gpie |= IXGBE_EIMS_TS;
3702 break;
3703 default:
3704 break;
3705 }
3706 }
3707
3708 /* Enable fan failure interrupt */
3709 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3710 gpie |= IXGBE_SDP1_GPIEN;
3711
3712 if (hw->mac.type == ixgbe_mac_82599EB) {
3713 gpie |= IXGBE_SDP1_GPIEN;
3714 gpie |= IXGBE_SDP2_GPIEN;
3715 }
3716
3717 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3718 }
3719
3720 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3721 {
3722 struct ixgbe_hw *hw = &adapter->hw;
3723 int err;
3724 u32 ctrl_ext;
3725
3726 ixgbe_get_hw_control(adapter);
3727 ixgbe_setup_gpie(adapter);
3728
3729 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3730 ixgbe_configure_msix(adapter);
3731 else
3732 ixgbe_configure_msi_and_legacy(adapter);
3733
3734 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3735 if (hw->mac.ops.enable_tx_laser &&
3736 ((hw->phy.multispeed_fiber) ||
3737 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3738 (hw->mac.type == ixgbe_mac_82599EB))))
3739 hw->mac.ops.enable_tx_laser(hw);
3740
3741 clear_bit(__IXGBE_DOWN, &adapter->state);
3742 ixgbe_napi_enable_all(adapter);
3743
3744 if (ixgbe_is_sfp(hw)) {
3745 ixgbe_sfp_link_config(adapter);
3746 } else {
3747 err = ixgbe_non_sfp_link_config(hw);
3748 if (err)
3749 e_err(probe, "link_config FAILED %d\n", err);
3750 }
3751
3752 /* clear any pending interrupts, may auto mask */
3753 IXGBE_READ_REG(hw, IXGBE_EICR);
3754 ixgbe_irq_enable(adapter, true, true);
3755
3756 /*
3757 * If this adapter has a fan, check to see if we had a failure
3758 * before we enabled the interrupt.
3759 */
3760 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3761 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3762 if (esdp & IXGBE_ESDP_SDP1)
3763 e_crit(drv, "Fan has stopped, replace the adapter\n");
3764 }
3765
3766 /* enable transmits */
3767 netif_tx_start_all_queues(adapter->netdev);
3768
3769 /* bring the link up in the watchdog, this could race with our first
3770 * link up interrupt but shouldn't be a problem */
3771 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3772 adapter->link_check_timeout = jiffies;
3773 mod_timer(&adapter->service_timer, jiffies);
3774
3775 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3776 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3777 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3778 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3779 }
3780
3781 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3782 {
3783 WARN_ON(in_interrupt());
3784 /* put off any impending NetWatchDogTimeout */
3785 adapter->netdev->trans_start = jiffies;
3786
3787 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3788 usleep_range(1000, 2000);
3789 ixgbe_down(adapter);
3790 /*
3791 * If SR-IOV enabled then wait a bit before bringing the adapter
3792 * back up to give the VFs time to respond to the reset. The
3793 * two second wait is based upon the watchdog timer cycle in
3794 * the VF driver.
3795 */
3796 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3797 msleep(2000);
3798 ixgbe_up(adapter);
3799 clear_bit(__IXGBE_RESETTING, &adapter->state);
3800 }
3801
3802 void ixgbe_up(struct ixgbe_adapter *adapter)
3803 {
3804 /* hardware has been reset, we need to reload some things */
3805 ixgbe_configure(adapter);
3806
3807 ixgbe_up_complete(adapter);
3808 }
3809
3810 void ixgbe_reset(struct ixgbe_adapter *adapter)
3811 {
3812 struct ixgbe_hw *hw = &adapter->hw;
3813 int err;
3814
3815 /* lock SFP init bit to prevent race conditions with the watchdog */
3816 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3817 usleep_range(1000, 2000);
3818
3819 /* clear all SFP and link config related flags while holding SFP_INIT */
3820 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3821 IXGBE_FLAG2_SFP_NEEDS_RESET);
3822 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3823
3824 err = hw->mac.ops.init_hw(hw);
3825 switch (err) {
3826 case 0:
3827 case IXGBE_ERR_SFP_NOT_PRESENT:
3828 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3829 break;
3830 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3831 e_dev_err("master disable timed out\n");
3832 break;
3833 case IXGBE_ERR_EEPROM_VERSION:
3834 /* We are running on a pre-production device, log a warning */
3835 e_dev_warn("This device is a pre-production adapter/LOM. "
3836 "Please be aware there may be issuesassociated with "
3837 "your hardware. If you are experiencing problems "
3838 "please contact your Intel or hardware "
3839 "representative who provided you with this "
3840 "hardware.\n");
3841 break;
3842 default:
3843 e_dev_err("Hardware Error: %d\n", err);
3844 }
3845
3846 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3847
3848 /* reprogram the RAR[0] in case user changed it. */
3849 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3850 IXGBE_RAH_AV);
3851 }
3852
3853 /**
3854 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3855 * @rx_ring: ring to free buffers from
3856 **/
3857 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3858 {
3859 struct device *dev = rx_ring->dev;
3860 unsigned long size;
3861 u16 i;
3862
3863 /* ring already cleared, nothing to do */
3864 if (!rx_ring->rx_buffer_info)
3865 return;
3866
3867 /* Free all the Rx ring sk_buffs */
3868 for (i = 0; i < rx_ring->count; i++) {
3869 struct ixgbe_rx_buffer *rx_buffer_info;
3870
3871 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3872 if (rx_buffer_info->dma) {
3873 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3874 rx_ring->rx_buf_len,
3875 DMA_FROM_DEVICE);
3876 rx_buffer_info->dma = 0;
3877 }
3878 if (rx_buffer_info->skb) {
3879 struct sk_buff *skb = rx_buffer_info->skb;
3880 rx_buffer_info->skb = NULL;
3881 do {
3882 struct sk_buff *this = skb;
3883 if (IXGBE_RSC_CB(this)->delay_unmap) {
3884 dma_unmap_single(dev,
3885 IXGBE_RSC_CB(this)->dma,
3886 rx_ring->rx_buf_len,
3887 DMA_FROM_DEVICE);
3888 IXGBE_RSC_CB(this)->dma = 0;
3889 IXGBE_RSC_CB(skb)->delay_unmap = false;
3890 }
3891 skb = skb->prev;
3892 dev_kfree_skb(this);
3893 } while (skb);
3894 }
3895 if (!rx_buffer_info->page)
3896 continue;
3897 if (rx_buffer_info->page_dma) {
3898 dma_unmap_page(dev, rx_buffer_info->page_dma,
3899 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3900 rx_buffer_info->page_dma = 0;
3901 }
3902 put_page(rx_buffer_info->page);
3903 rx_buffer_info->page = NULL;
3904 rx_buffer_info->page_offset = 0;
3905 }
3906
3907 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3908 memset(rx_ring->rx_buffer_info, 0, size);
3909
3910 /* Zero out the descriptor ring */
3911 memset(rx_ring->desc, 0, rx_ring->size);
3912
3913 rx_ring->next_to_clean = 0;
3914 rx_ring->next_to_use = 0;
3915 }
3916
3917 /**
3918 * ixgbe_clean_tx_ring - Free Tx Buffers
3919 * @tx_ring: ring to be cleaned
3920 **/
3921 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3922 {
3923 struct ixgbe_tx_buffer *tx_buffer_info;
3924 unsigned long size;
3925 u16 i;
3926
3927 /* ring already cleared, nothing to do */
3928 if (!tx_ring->tx_buffer_info)
3929 return;
3930
3931 /* Free all the Tx ring sk_buffs */
3932 for (i = 0; i < tx_ring->count; i++) {
3933 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3934 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3935 }
3936
3937 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3938 memset(tx_ring->tx_buffer_info, 0, size);
3939
3940 /* Zero out the descriptor ring */
3941 memset(tx_ring->desc, 0, tx_ring->size);
3942
3943 tx_ring->next_to_use = 0;
3944 tx_ring->next_to_clean = 0;
3945 }
3946
3947 /**
3948 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3949 * @adapter: board private structure
3950 **/
3951 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3952 {
3953 int i;
3954
3955 for (i = 0; i < adapter->num_rx_queues; i++)
3956 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3957 }
3958
3959 /**
3960 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3961 * @adapter: board private structure
3962 **/
3963 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3964 {
3965 int i;
3966
3967 for (i = 0; i < adapter->num_tx_queues; i++)
3968 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3969 }
3970
3971 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3972 {
3973 struct hlist_node *node, *node2;
3974 struct ixgbe_fdir_filter *filter;
3975
3976 spin_lock(&adapter->fdir_perfect_lock);
3977
3978 hlist_for_each_entry_safe(filter, node, node2,
3979 &adapter->fdir_filter_list, fdir_node) {
3980 hlist_del(&filter->fdir_node);
3981 kfree(filter);
3982 }
3983 adapter->fdir_filter_count = 0;
3984
3985 spin_unlock(&adapter->fdir_perfect_lock);
3986 }
3987
3988 void ixgbe_down(struct ixgbe_adapter *adapter)
3989 {
3990 struct net_device *netdev = adapter->netdev;
3991 struct ixgbe_hw *hw = &adapter->hw;
3992 u32 rxctrl;
3993 int i;
3994
3995 /* signal that we are down to the interrupt handler */
3996 set_bit(__IXGBE_DOWN, &adapter->state);
3997
3998 /* disable receives */
3999 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4000 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4001
4002 /* disable all enabled rx queues */
4003 for (i = 0; i < adapter->num_rx_queues; i++)
4004 /* this call also flushes the previous write */
4005 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4006
4007 usleep_range(10000, 20000);
4008
4009 netif_tx_stop_all_queues(netdev);
4010
4011 /* call carrier off first to avoid false dev_watchdog timeouts */
4012 netif_carrier_off(netdev);
4013 netif_tx_disable(netdev);
4014
4015 ixgbe_irq_disable(adapter);
4016
4017 ixgbe_napi_disable_all(adapter);
4018
4019 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4020 IXGBE_FLAG2_RESET_REQUESTED);
4021 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4022
4023 del_timer_sync(&adapter->service_timer);
4024
4025 if (adapter->num_vfs) {
4026 /* Clear EITR Select mapping */
4027 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4028
4029 /* Mark all the VFs as inactive */
4030 for (i = 0 ; i < adapter->num_vfs; i++)
4031 adapter->vfinfo[i].clear_to_send = 0;
4032
4033 /* ping all the active vfs to let them know we are going down */
4034 ixgbe_ping_all_vfs(adapter);
4035
4036 /* Disable all VFTE/VFRE TX/RX */
4037 ixgbe_disable_tx_rx(adapter);
4038 }
4039
4040 /* disable transmits in the hardware now that interrupts are off */
4041 for (i = 0; i < adapter->num_tx_queues; i++) {
4042 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4043 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4044 }
4045
4046 /* Disable the Tx DMA engine on 82599 and X540 */
4047 switch (hw->mac.type) {
4048 case ixgbe_mac_82599EB:
4049 case ixgbe_mac_X540:
4050 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4051 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4052 ~IXGBE_DMATXCTL_TE));
4053 break;
4054 default:
4055 break;
4056 }
4057
4058 if (!pci_channel_offline(adapter->pdev))
4059 ixgbe_reset(adapter);
4060
4061 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4062 if (hw->mac.ops.disable_tx_laser &&
4063 ((hw->phy.multispeed_fiber) ||
4064 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4065 (hw->mac.type == ixgbe_mac_82599EB))))
4066 hw->mac.ops.disable_tx_laser(hw);
4067
4068 ixgbe_clean_all_tx_rings(adapter);
4069 ixgbe_clean_all_rx_rings(adapter);
4070
4071 #ifdef CONFIG_IXGBE_DCA
4072 /* since we reset the hardware DCA settings were cleared */
4073 ixgbe_setup_dca(adapter);
4074 #endif
4075 }
4076
4077 /**
4078 * ixgbe_poll - NAPI Rx polling callback
4079 * @napi: structure for representing this polling device
4080 * @budget: how many packets driver is allowed to clean
4081 *
4082 * This function is used for legacy and MSI, NAPI mode
4083 **/
4084 static int ixgbe_poll(struct napi_struct *napi, int budget)
4085 {
4086 struct ixgbe_q_vector *q_vector =
4087 container_of(napi, struct ixgbe_q_vector, napi);
4088 struct ixgbe_adapter *adapter = q_vector->adapter;
4089 struct ixgbe_ring *ring;
4090 int per_ring_budget;
4091 bool clean_complete = true;
4092
4093 #ifdef CONFIG_IXGBE_DCA
4094 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4095 ixgbe_update_dca(q_vector);
4096 #endif
4097
4098 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4099 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
4100
4101 /* attempt to distribute budget to each queue fairly, but don't allow
4102 * the budget to go below 1 because we'll exit polling */
4103 if (q_vector->rx.count > 1)
4104 per_ring_budget = max(budget/q_vector->rx.count, 1);
4105 else
4106 per_ring_budget = budget;
4107
4108 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4109 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4110 per_ring_budget);
4111
4112 /* If all work not completed, return budget and keep polling */
4113 if (!clean_complete)
4114 return budget;
4115
4116 /* all work done, exit the polling mode */
4117 napi_complete(napi);
4118 if (adapter->rx_itr_setting & 1)
4119 ixgbe_set_itr(q_vector);
4120 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4121 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4122
4123 return 0;
4124 }
4125
4126 /**
4127 * ixgbe_tx_timeout - Respond to a Tx Hang
4128 * @netdev: network interface device structure
4129 **/
4130 static void ixgbe_tx_timeout(struct net_device *netdev)
4131 {
4132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4133
4134 /* Do the reset outside of interrupt context */
4135 ixgbe_tx_timeout_reset(adapter);
4136 }
4137
4138 /**
4139 * ixgbe_set_rss_queues: Allocate queues for RSS
4140 * @adapter: board private structure to initialize
4141 *
4142 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4143 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4144 *
4145 **/
4146 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4147 {
4148 bool ret = false;
4149 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4150
4151 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4152 f->mask = 0xF;
4153 adapter->num_rx_queues = f->indices;
4154 adapter->num_tx_queues = f->indices;
4155 ret = true;
4156 } else {
4157 ret = false;
4158 }
4159
4160 return ret;
4161 }
4162
4163 /**
4164 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4165 * @adapter: board private structure to initialize
4166 *
4167 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4168 * to the original CPU that initiated the Tx session. This runs in addition
4169 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4170 * Rx load across CPUs using RSS.
4171 *
4172 **/
4173 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4174 {
4175 bool ret = false;
4176 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4177
4178 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4179 f_fdir->mask = 0;
4180
4181 /* Flow Director must have RSS enabled */
4182 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4183 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4184 adapter->num_tx_queues = f_fdir->indices;
4185 adapter->num_rx_queues = f_fdir->indices;
4186 ret = true;
4187 } else {
4188 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4189 }
4190 return ret;
4191 }
4192
4193 #ifdef IXGBE_FCOE
4194 /**
4195 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4196 * @adapter: board private structure to initialize
4197 *
4198 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4199 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4200 * rx queues out of the max number of rx queues, instead, it is used as the
4201 * index of the first rx queue used by FCoE.
4202 *
4203 **/
4204 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4205 {
4206 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4207
4208 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4209 return false;
4210
4211 f->indices = min((int)num_online_cpus(), f->indices);
4212
4213 adapter->num_rx_queues = 1;
4214 adapter->num_tx_queues = 1;
4215
4216 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4217 e_info(probe, "FCoE enabled with RSS\n");
4218 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4219 ixgbe_set_fdir_queues(adapter);
4220 else
4221 ixgbe_set_rss_queues(adapter);
4222 }
4223
4224 /* adding FCoE rx rings to the end */
4225 f->mask = adapter->num_rx_queues;
4226 adapter->num_rx_queues += f->indices;
4227 adapter->num_tx_queues += f->indices;
4228
4229 return true;
4230 }
4231 #endif /* IXGBE_FCOE */
4232
4233 /* Artificial max queue cap per traffic class in DCB mode */
4234 #define DCB_QUEUE_CAP 8
4235
4236 #ifdef CONFIG_IXGBE_DCB
4237 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4238 {
4239 int per_tc_q, q, i, offset = 0;
4240 struct net_device *dev = adapter->netdev;
4241 int tcs = netdev_get_num_tc(dev);
4242
4243 if (!tcs)
4244 return false;
4245
4246 /* Map queue offset and counts onto allocated tx queues */
4247 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4248 q = min((int)num_online_cpus(), per_tc_q);
4249
4250 for (i = 0; i < tcs; i++) {
4251 netdev_set_tc_queue(dev, i, q, offset);
4252 offset += q;
4253 }
4254
4255 adapter->num_tx_queues = q * tcs;
4256 adapter->num_rx_queues = q * tcs;
4257
4258 #ifdef IXGBE_FCOE
4259 /* FCoE enabled queues require special configuration indexed
4260 * by feature specific indices and mask. Here we map FCoE
4261 * indices onto the DCB queue pairs allowing FCoE to own
4262 * configuration later.
4263 */
4264 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4265 int tc;
4266 struct ixgbe_ring_feature *f =
4267 &adapter->ring_feature[RING_F_FCOE];
4268
4269 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4270 f->indices = dev->tc_to_txq[tc].count;
4271 f->mask = dev->tc_to_txq[tc].offset;
4272 }
4273 #endif
4274
4275 return true;
4276 }
4277 #endif
4278
4279 /**
4280 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4281 * @adapter: board private structure to initialize
4282 *
4283 * IOV doesn't actually use anything, so just NAK the
4284 * request for now and let the other queue routines
4285 * figure out what to do.
4286 */
4287 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4288 {
4289 return false;
4290 }
4291
4292 /*
4293 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4294 * @adapter: board private structure to initialize
4295 *
4296 * This is the top level queue allocation routine. The order here is very
4297 * important, starting with the "most" number of features turned on at once,
4298 * and ending with the smallest set of features. This way large combinations
4299 * can be allocated if they're turned on, and smaller combinations are the
4300 * fallthrough conditions.
4301 *
4302 **/
4303 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4304 {
4305 /* Start with base case */
4306 adapter->num_rx_queues = 1;
4307 adapter->num_tx_queues = 1;
4308 adapter->num_rx_pools = adapter->num_rx_queues;
4309 adapter->num_rx_queues_per_pool = 1;
4310
4311 if (ixgbe_set_sriov_queues(adapter))
4312 goto done;
4313
4314 #ifdef CONFIG_IXGBE_DCB
4315 if (ixgbe_set_dcb_queues(adapter))
4316 goto done;
4317
4318 #endif
4319 #ifdef IXGBE_FCOE
4320 if (ixgbe_set_fcoe_queues(adapter))
4321 goto done;
4322
4323 #endif /* IXGBE_FCOE */
4324 if (ixgbe_set_fdir_queues(adapter))
4325 goto done;
4326
4327 if (ixgbe_set_rss_queues(adapter))
4328 goto done;
4329
4330 /* fallback to base case */
4331 adapter->num_rx_queues = 1;
4332 adapter->num_tx_queues = 1;
4333
4334 done:
4335 /* Notify the stack of the (possibly) reduced queue counts. */
4336 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4337 return netif_set_real_num_rx_queues(adapter->netdev,
4338 adapter->num_rx_queues);
4339 }
4340
4341 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4342 int vectors)
4343 {
4344 int err, vector_threshold;
4345
4346 /* We'll want at least 3 (vector_threshold):
4347 * 1) TxQ[0] Cleanup
4348 * 2) RxQ[0] Cleanup
4349 * 3) Other (Link Status Change, etc.)
4350 * 4) TCP Timer (optional)
4351 */
4352 vector_threshold = MIN_MSIX_COUNT;
4353
4354 /* The more we get, the more we will assign to Tx/Rx Cleanup
4355 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4356 * Right now, we simply care about how many we'll get; we'll
4357 * set them up later while requesting irq's.
4358 */
4359 while (vectors >= vector_threshold) {
4360 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4361 vectors);
4362 if (!err) /* Success in acquiring all requested vectors. */
4363 break;
4364 else if (err < 0)
4365 vectors = 0; /* Nasty failure, quit now */
4366 else /* err == number of vectors we should try again with */
4367 vectors = err;
4368 }
4369
4370 if (vectors < vector_threshold) {
4371 /* Can't allocate enough MSI-X interrupts? Oh well.
4372 * This just means we'll go with either a single MSI
4373 * vector or fall back to legacy interrupts.
4374 */
4375 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4376 "Unable to allocate MSI-X interrupts\n");
4377 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4378 kfree(adapter->msix_entries);
4379 adapter->msix_entries = NULL;
4380 } else {
4381 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4382 /*
4383 * Adjust for only the vectors we'll use, which is minimum
4384 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4385 * vectors we were allocated.
4386 */
4387 adapter->num_msix_vectors = min(vectors,
4388 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4389 }
4390 }
4391
4392 /**
4393 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4394 * @adapter: board private structure to initialize
4395 *
4396 * Cache the descriptor ring offsets for RSS to the assigned rings.
4397 *
4398 **/
4399 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4400 {
4401 int i;
4402
4403 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4404 return false;
4405
4406 for (i = 0; i < adapter->num_rx_queues; i++)
4407 adapter->rx_ring[i]->reg_idx = i;
4408 for (i = 0; i < adapter->num_tx_queues; i++)
4409 adapter->tx_ring[i]->reg_idx = i;
4410
4411 return true;
4412 }
4413
4414 #ifdef CONFIG_IXGBE_DCB
4415
4416 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4417 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4418 unsigned int *tx, unsigned int *rx)
4419 {
4420 struct net_device *dev = adapter->netdev;
4421 struct ixgbe_hw *hw = &adapter->hw;
4422 u8 num_tcs = netdev_get_num_tc(dev);
4423
4424 *tx = 0;
4425 *rx = 0;
4426
4427 switch (hw->mac.type) {
4428 case ixgbe_mac_82598EB:
4429 *tx = tc << 2;
4430 *rx = tc << 3;
4431 break;
4432 case ixgbe_mac_82599EB:
4433 case ixgbe_mac_X540:
4434 if (num_tcs > 4) {
4435 if (tc < 3) {
4436 *tx = tc << 5;
4437 *rx = tc << 4;
4438 } else if (tc < 5) {
4439 *tx = ((tc + 2) << 4);
4440 *rx = tc << 4;
4441 } else if (tc < num_tcs) {
4442 *tx = ((tc + 8) << 3);
4443 *rx = tc << 4;
4444 }
4445 } else {
4446 *rx = tc << 5;
4447 switch (tc) {
4448 case 0:
4449 *tx = 0;
4450 break;
4451 case 1:
4452 *tx = 64;
4453 break;
4454 case 2:
4455 *tx = 96;
4456 break;
4457 case 3:
4458 *tx = 112;
4459 break;
4460 default:
4461 break;
4462 }
4463 }
4464 break;
4465 default:
4466 break;
4467 }
4468 }
4469
4470 /**
4471 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4472 * @adapter: board private structure to initialize
4473 *
4474 * Cache the descriptor ring offsets for DCB to the assigned rings.
4475 *
4476 **/
4477 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4478 {
4479 struct net_device *dev = adapter->netdev;
4480 int i, j, k;
4481 u8 num_tcs = netdev_get_num_tc(dev);
4482
4483 if (!num_tcs)
4484 return false;
4485
4486 for (i = 0, k = 0; i < num_tcs; i++) {
4487 unsigned int tx_s, rx_s;
4488 u16 count = dev->tc_to_txq[i].count;
4489
4490 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4491 for (j = 0; j < count; j++, k++) {
4492 adapter->tx_ring[k]->reg_idx = tx_s + j;
4493 adapter->rx_ring[k]->reg_idx = rx_s + j;
4494 adapter->tx_ring[k]->dcb_tc = i;
4495 adapter->rx_ring[k]->dcb_tc = i;
4496 }
4497 }
4498
4499 return true;
4500 }
4501 #endif
4502
4503 /**
4504 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4505 * @adapter: board private structure to initialize
4506 *
4507 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4508 *
4509 **/
4510 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4511 {
4512 int i;
4513 bool ret = false;
4514
4515 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4516 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4517 for (i = 0; i < adapter->num_rx_queues; i++)
4518 adapter->rx_ring[i]->reg_idx = i;
4519 for (i = 0; i < adapter->num_tx_queues; i++)
4520 adapter->tx_ring[i]->reg_idx = i;
4521 ret = true;
4522 }
4523
4524 return ret;
4525 }
4526
4527 #ifdef IXGBE_FCOE
4528 /**
4529 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4530 * @adapter: board private structure to initialize
4531 *
4532 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4533 *
4534 */
4535 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4536 {
4537 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4538 int i;
4539 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4540
4541 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4542 return false;
4543
4544 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4545 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4546 ixgbe_cache_ring_fdir(adapter);
4547 else
4548 ixgbe_cache_ring_rss(adapter);
4549
4550 fcoe_rx_i = f->mask;
4551 fcoe_tx_i = f->mask;
4552 }
4553 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4554 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4555 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4556 }
4557 return true;
4558 }
4559
4560 #endif /* IXGBE_FCOE */
4561 /**
4562 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4563 * @adapter: board private structure to initialize
4564 *
4565 * SR-IOV doesn't use any descriptor rings but changes the default if
4566 * no other mapping is used.
4567 *
4568 */
4569 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4570 {
4571 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4572 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4573 if (adapter->num_vfs)
4574 return true;
4575 else
4576 return false;
4577 }
4578
4579 /**
4580 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4581 * @adapter: board private structure to initialize
4582 *
4583 * Once we know the feature-set enabled for the device, we'll cache
4584 * the register offset the descriptor ring is assigned to.
4585 *
4586 * Note, the order the various feature calls is important. It must start with
4587 * the "most" features enabled at the same time, then trickle down to the
4588 * least amount of features turned on at once.
4589 **/
4590 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4591 {
4592 /* start with default case */
4593 adapter->rx_ring[0]->reg_idx = 0;
4594 adapter->tx_ring[0]->reg_idx = 0;
4595
4596 if (ixgbe_cache_ring_sriov(adapter))
4597 return;
4598
4599 #ifdef CONFIG_IXGBE_DCB
4600 if (ixgbe_cache_ring_dcb(adapter))
4601 return;
4602 #endif
4603
4604 #ifdef IXGBE_FCOE
4605 if (ixgbe_cache_ring_fcoe(adapter))
4606 return;
4607 #endif /* IXGBE_FCOE */
4608
4609 if (ixgbe_cache_ring_fdir(adapter))
4610 return;
4611
4612 if (ixgbe_cache_ring_rss(adapter))
4613 return;
4614 }
4615
4616 /**
4617 * ixgbe_alloc_queues - Allocate memory for all rings
4618 * @adapter: board private structure to initialize
4619 *
4620 * We allocate one ring per queue at run-time since we don't know the
4621 * number of queues at compile-time. The polling_netdev array is
4622 * intended for Multiqueue, but should work fine with a single queue.
4623 **/
4624 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4625 {
4626 int rx = 0, tx = 0, nid = adapter->node;
4627
4628 if (nid < 0 || !node_online(nid))
4629 nid = first_online_node;
4630
4631 for (; tx < adapter->num_tx_queues; tx++) {
4632 struct ixgbe_ring *ring;
4633
4634 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4635 if (!ring)
4636 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4637 if (!ring)
4638 goto err_allocation;
4639 ring->count = adapter->tx_ring_count;
4640 ring->queue_index = tx;
4641 ring->numa_node = nid;
4642 ring->dev = &adapter->pdev->dev;
4643 ring->netdev = adapter->netdev;
4644
4645 adapter->tx_ring[tx] = ring;
4646 }
4647
4648 for (; rx < adapter->num_rx_queues; rx++) {
4649 struct ixgbe_ring *ring;
4650
4651 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4652 if (!ring)
4653 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4654 if (!ring)
4655 goto err_allocation;
4656 ring->count = adapter->rx_ring_count;
4657 ring->queue_index = rx;
4658 ring->numa_node = nid;
4659 ring->dev = &adapter->pdev->dev;
4660 ring->netdev = adapter->netdev;
4661
4662 adapter->rx_ring[rx] = ring;
4663 }
4664
4665 ixgbe_cache_ring_register(adapter);
4666
4667 return 0;
4668
4669 err_allocation:
4670 while (tx)
4671 kfree(adapter->tx_ring[--tx]);
4672
4673 while (rx)
4674 kfree(adapter->rx_ring[--rx]);
4675 return -ENOMEM;
4676 }
4677
4678 /**
4679 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4680 * @adapter: board private structure to initialize
4681 *
4682 * Attempt to configure the interrupts using the best available
4683 * capabilities of the hardware and the kernel.
4684 **/
4685 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4686 {
4687 struct ixgbe_hw *hw = &adapter->hw;
4688 int err = 0;
4689 int vector, v_budget;
4690
4691 /*
4692 * It's easy to be greedy for MSI-X vectors, but it really
4693 * doesn't do us much good if we have a lot more vectors
4694 * than CPU's. So let's be conservative and only ask for
4695 * (roughly) the same number of vectors as there are CPU's.
4696 */
4697 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4698 (int)num_online_cpus()) + NON_Q_VECTORS;
4699
4700 /*
4701 * At the same time, hardware can only support a maximum of
4702 * hw.mac->max_msix_vectors vectors. With features
4703 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4704 * descriptor queues supported by our device. Thus, we cap it off in
4705 * those rare cases where the cpu count also exceeds our vector limit.
4706 */
4707 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4708
4709 /* A failure in MSI-X entry allocation isn't fatal, but it does
4710 * mean we disable MSI-X capabilities of the adapter. */
4711 adapter->msix_entries = kcalloc(v_budget,
4712 sizeof(struct msix_entry), GFP_KERNEL);
4713 if (adapter->msix_entries) {
4714 for (vector = 0; vector < v_budget; vector++)
4715 adapter->msix_entries[vector].entry = vector;
4716
4717 ixgbe_acquire_msix_vectors(adapter, v_budget);
4718
4719 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4720 goto out;
4721 }
4722
4723 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4724 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4725 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4726 e_err(probe,
4727 "ATR is not supported while multiple "
4728 "queues are disabled. Disabling Flow Director\n");
4729 }
4730 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4731 adapter->atr_sample_rate = 0;
4732 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4733 ixgbe_disable_sriov(adapter);
4734
4735 err = ixgbe_set_num_queues(adapter);
4736 if (err)
4737 return err;
4738
4739 err = pci_enable_msi(adapter->pdev);
4740 if (!err) {
4741 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4742 } else {
4743 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4744 "Unable to allocate MSI interrupt, "
4745 "falling back to legacy. Error: %d\n", err);
4746 /* reset err */
4747 err = 0;
4748 }
4749
4750 out:
4751 return err;
4752 }
4753
4754 /**
4755 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4756 * @adapter: board private structure to initialize
4757 *
4758 * We allocate one q_vector per queue interrupt. If allocation fails we
4759 * return -ENOMEM.
4760 **/
4761 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4762 {
4763 int v_idx, num_q_vectors;
4764 struct ixgbe_q_vector *q_vector;
4765
4766 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4767 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4768 else
4769 num_q_vectors = 1;
4770
4771 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4772 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4773 GFP_KERNEL, adapter->node);
4774 if (!q_vector)
4775 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4776 GFP_KERNEL);
4777 if (!q_vector)
4778 goto err_out;
4779
4780 q_vector->adapter = adapter;
4781 q_vector->v_idx = v_idx;
4782
4783 /* Allocate the affinity_hint cpumask, configure the mask */
4784 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4785 goto err_out;
4786 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4787 netif_napi_add(adapter->netdev, &q_vector->napi,
4788 ixgbe_poll, 64);
4789 adapter->q_vector[v_idx] = q_vector;
4790 }
4791
4792 return 0;
4793
4794 err_out:
4795 while (v_idx) {
4796 v_idx--;
4797 q_vector = adapter->q_vector[v_idx];
4798 netif_napi_del(&q_vector->napi);
4799 free_cpumask_var(q_vector->affinity_mask);
4800 kfree(q_vector);
4801 adapter->q_vector[v_idx] = NULL;
4802 }
4803 return -ENOMEM;
4804 }
4805
4806 /**
4807 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4808 * @adapter: board private structure to initialize
4809 *
4810 * This function frees the memory allocated to the q_vectors. In addition if
4811 * NAPI is enabled it will delete any references to the NAPI struct prior
4812 * to freeing the q_vector.
4813 **/
4814 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4815 {
4816 int v_idx, num_q_vectors;
4817
4818 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4819 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4820 else
4821 num_q_vectors = 1;
4822
4823 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4824 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4825 adapter->q_vector[v_idx] = NULL;
4826 netif_napi_del(&q_vector->napi);
4827 free_cpumask_var(q_vector->affinity_mask);
4828 kfree(q_vector);
4829 }
4830 }
4831
4832 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4833 {
4834 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4835 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4836 pci_disable_msix(adapter->pdev);
4837 kfree(adapter->msix_entries);
4838 adapter->msix_entries = NULL;
4839 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4840 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4841 pci_disable_msi(adapter->pdev);
4842 }
4843 }
4844
4845 /**
4846 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4847 * @adapter: board private structure to initialize
4848 *
4849 * We determine which interrupt scheme to use based on...
4850 * - Kernel support (MSI, MSI-X)
4851 * - which can be user-defined (via MODULE_PARAM)
4852 * - Hardware queue count (num_*_queues)
4853 * - defined by miscellaneous hardware support/features (RSS, etc.)
4854 **/
4855 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4856 {
4857 int err;
4858
4859 /* Number of supported queues */
4860 err = ixgbe_set_num_queues(adapter);
4861 if (err)
4862 return err;
4863
4864 err = ixgbe_set_interrupt_capability(adapter);
4865 if (err) {
4866 e_dev_err("Unable to setup interrupt capabilities\n");
4867 goto err_set_interrupt;
4868 }
4869
4870 err = ixgbe_alloc_q_vectors(adapter);
4871 if (err) {
4872 e_dev_err("Unable to allocate memory for queue vectors\n");
4873 goto err_alloc_q_vectors;
4874 }
4875
4876 err = ixgbe_alloc_queues(adapter);
4877 if (err) {
4878 e_dev_err("Unable to allocate memory for queues\n");
4879 goto err_alloc_queues;
4880 }
4881
4882 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4883 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4884 adapter->num_rx_queues, adapter->num_tx_queues);
4885
4886 set_bit(__IXGBE_DOWN, &adapter->state);
4887
4888 return 0;
4889
4890 err_alloc_queues:
4891 ixgbe_free_q_vectors(adapter);
4892 err_alloc_q_vectors:
4893 ixgbe_reset_interrupt_capability(adapter);
4894 err_set_interrupt:
4895 return err;
4896 }
4897
4898 /**
4899 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4900 * @adapter: board private structure to clear interrupt scheme on
4901 *
4902 * We go through and clear interrupt specific resources and reset the structure
4903 * to pre-load conditions
4904 **/
4905 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4906 {
4907 int i;
4908
4909 for (i = 0; i < adapter->num_tx_queues; i++) {
4910 kfree(adapter->tx_ring[i]);
4911 adapter->tx_ring[i] = NULL;
4912 }
4913 for (i = 0; i < adapter->num_rx_queues; i++) {
4914 struct ixgbe_ring *ring = adapter->rx_ring[i];
4915
4916 /* ixgbe_get_stats64() might access this ring, we must wait
4917 * a grace period before freeing it.
4918 */
4919 kfree_rcu(ring, rcu);
4920 adapter->rx_ring[i] = NULL;
4921 }
4922
4923 adapter->num_tx_queues = 0;
4924 adapter->num_rx_queues = 0;
4925
4926 ixgbe_free_q_vectors(adapter);
4927 ixgbe_reset_interrupt_capability(adapter);
4928 }
4929
4930 /**
4931 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4932 * @adapter: board private structure to initialize
4933 *
4934 * ixgbe_sw_init initializes the Adapter private data structure.
4935 * Fields are initialized based on PCI device information and
4936 * OS network device settings (MTU size).
4937 **/
4938 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4939 {
4940 struct ixgbe_hw *hw = &adapter->hw;
4941 struct pci_dev *pdev = adapter->pdev;
4942 unsigned int rss;
4943 #ifdef CONFIG_IXGBE_DCB
4944 int j;
4945 struct tc_configuration *tc;
4946 #endif
4947
4948 /* PCI config space info */
4949
4950 hw->vendor_id = pdev->vendor;
4951 hw->device_id = pdev->device;
4952 hw->revision_id = pdev->revision;
4953 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4954 hw->subsystem_device_id = pdev->subsystem_device;
4955
4956 /* Set capability flags */
4957 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4958 adapter->ring_feature[RING_F_RSS].indices = rss;
4959 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4960 switch (hw->mac.type) {
4961 case ixgbe_mac_82598EB:
4962 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4963 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4964 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4965 break;
4966 case ixgbe_mac_X540:
4967 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4968 case ixgbe_mac_82599EB:
4969 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4970 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4971 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4972 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4973 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4974 /* Flow Director hash filters enabled */
4975 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4976 adapter->atr_sample_rate = 20;
4977 adapter->ring_feature[RING_F_FDIR].indices =
4978 IXGBE_MAX_FDIR_INDICES;
4979 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4980 #ifdef IXGBE_FCOE
4981 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4982 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4983 adapter->ring_feature[RING_F_FCOE].indices = 0;
4984 #ifdef CONFIG_IXGBE_DCB
4985 /* Default traffic class to use for FCoE */
4986 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4987 #endif
4988 #endif /* IXGBE_FCOE */
4989 break;
4990 default:
4991 break;
4992 }
4993
4994 /* n-tuple support exists, always init our spinlock */
4995 spin_lock_init(&adapter->fdir_perfect_lock);
4996
4997 #ifdef CONFIG_IXGBE_DCB
4998 switch (hw->mac.type) {
4999 case ixgbe_mac_X540:
5000 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5001 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5002 break;
5003 default:
5004 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5005 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5006 break;
5007 }
5008
5009 /* Configure DCB traffic classes */
5010 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5011 tc = &adapter->dcb_cfg.tc_config[j];
5012 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5013 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5014 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5015 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5016 tc->dcb_pfc = pfc_disabled;
5017 }
5018
5019 /* Initialize default user to priority mapping, UPx->TC0 */
5020 tc = &adapter->dcb_cfg.tc_config[0];
5021 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5022 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5023
5024 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5025 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5026 adapter->dcb_cfg.pfc_mode_enable = false;
5027 adapter->dcb_set_bitmap = 0x00;
5028 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5029 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5030 MAX_TRAFFIC_CLASS);
5031
5032 #endif
5033
5034 /* default flow control settings */
5035 hw->fc.requested_mode = ixgbe_fc_full;
5036 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5037 #ifdef CONFIG_DCB
5038 adapter->last_lfc_mode = hw->fc.current_mode;
5039 #endif
5040 ixgbe_pbthresh_setup(adapter);
5041 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5042 hw->fc.send_xon = true;
5043 hw->fc.disable_fc_autoneg = false;
5044
5045 /* enable itr by default in dynamic mode */
5046 adapter->rx_itr_setting = 1;
5047 adapter->tx_itr_setting = 1;
5048
5049 /* set defaults for eitr in MegaBytes */
5050 adapter->eitr_low = 10;
5051 adapter->eitr_high = 20;
5052
5053 /* set default ring sizes */
5054 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5055 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5056
5057 /* set default work limits */
5058 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5059
5060 /* initialize eeprom parameters */
5061 if (ixgbe_init_eeprom_params_generic(hw)) {
5062 e_dev_err("EEPROM initialization failed\n");
5063 return -EIO;
5064 }
5065
5066 /* enable rx csum by default */
5067 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5068
5069 /* get assigned NUMA node */
5070 adapter->node = dev_to_node(&pdev->dev);
5071
5072 set_bit(__IXGBE_DOWN, &adapter->state);
5073
5074 return 0;
5075 }
5076
5077 /**
5078 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5079 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5080 *
5081 * Return 0 on success, negative on failure
5082 **/
5083 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5084 {
5085 struct device *dev = tx_ring->dev;
5086 int size;
5087
5088 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5089 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5090 if (!tx_ring->tx_buffer_info)
5091 tx_ring->tx_buffer_info = vzalloc(size);
5092 if (!tx_ring->tx_buffer_info)
5093 goto err;
5094
5095 /* round up to nearest 4K */
5096 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5097 tx_ring->size = ALIGN(tx_ring->size, 4096);
5098
5099 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5100 &tx_ring->dma, GFP_KERNEL);
5101 if (!tx_ring->desc)
5102 goto err;
5103
5104 tx_ring->next_to_use = 0;
5105 tx_ring->next_to_clean = 0;
5106 return 0;
5107
5108 err:
5109 vfree(tx_ring->tx_buffer_info);
5110 tx_ring->tx_buffer_info = NULL;
5111 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5112 return -ENOMEM;
5113 }
5114
5115 /**
5116 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5117 * @adapter: board private structure
5118 *
5119 * If this function returns with an error, then it's possible one or
5120 * more of the rings is populated (while the rest are not). It is the
5121 * callers duty to clean those orphaned rings.
5122 *
5123 * Return 0 on success, negative on failure
5124 **/
5125 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5126 {
5127 int i, err = 0;
5128
5129 for (i = 0; i < adapter->num_tx_queues; i++) {
5130 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5131 if (!err)
5132 continue;
5133 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5134 break;
5135 }
5136
5137 return err;
5138 }
5139
5140 /**
5141 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5142 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5143 *
5144 * Returns 0 on success, negative on failure
5145 **/
5146 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5147 {
5148 struct device *dev = rx_ring->dev;
5149 int size;
5150
5151 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5152 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5153 if (!rx_ring->rx_buffer_info)
5154 rx_ring->rx_buffer_info = vzalloc(size);
5155 if (!rx_ring->rx_buffer_info)
5156 goto err;
5157
5158 /* Round up to nearest 4K */
5159 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5160 rx_ring->size = ALIGN(rx_ring->size, 4096);
5161
5162 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5163 &rx_ring->dma, GFP_KERNEL);
5164
5165 if (!rx_ring->desc)
5166 goto err;
5167
5168 rx_ring->next_to_clean = 0;
5169 rx_ring->next_to_use = 0;
5170
5171 return 0;
5172 err:
5173 vfree(rx_ring->rx_buffer_info);
5174 rx_ring->rx_buffer_info = NULL;
5175 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5176 return -ENOMEM;
5177 }
5178
5179 /**
5180 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5181 * @adapter: board private structure
5182 *
5183 * If this function returns with an error, then it's possible one or
5184 * more of the rings is populated (while the rest are not). It is the
5185 * callers duty to clean those orphaned rings.
5186 *
5187 * Return 0 on success, negative on failure
5188 **/
5189 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5190 {
5191 int i, err = 0;
5192
5193 for (i = 0; i < adapter->num_rx_queues; i++) {
5194 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5195 if (!err)
5196 continue;
5197 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5198 break;
5199 }
5200
5201 return err;
5202 }
5203
5204 /**
5205 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5206 * @tx_ring: Tx descriptor ring for a specific queue
5207 *
5208 * Free all transmit software resources
5209 **/
5210 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5211 {
5212 ixgbe_clean_tx_ring(tx_ring);
5213
5214 vfree(tx_ring->tx_buffer_info);
5215 tx_ring->tx_buffer_info = NULL;
5216
5217 /* if not set, then don't free */
5218 if (!tx_ring->desc)
5219 return;
5220
5221 dma_free_coherent(tx_ring->dev, tx_ring->size,
5222 tx_ring->desc, tx_ring->dma);
5223
5224 tx_ring->desc = NULL;
5225 }
5226
5227 /**
5228 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5229 * @adapter: board private structure
5230 *
5231 * Free all transmit software resources
5232 **/
5233 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5234 {
5235 int i;
5236
5237 for (i = 0; i < adapter->num_tx_queues; i++)
5238 if (adapter->tx_ring[i]->desc)
5239 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5240 }
5241
5242 /**
5243 * ixgbe_free_rx_resources - Free Rx Resources
5244 * @rx_ring: ring to clean the resources from
5245 *
5246 * Free all receive software resources
5247 **/
5248 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5249 {
5250 ixgbe_clean_rx_ring(rx_ring);
5251
5252 vfree(rx_ring->rx_buffer_info);
5253 rx_ring->rx_buffer_info = NULL;
5254
5255 /* if not set, then don't free */
5256 if (!rx_ring->desc)
5257 return;
5258
5259 dma_free_coherent(rx_ring->dev, rx_ring->size,
5260 rx_ring->desc, rx_ring->dma);
5261
5262 rx_ring->desc = NULL;
5263 }
5264
5265 /**
5266 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5267 * @adapter: board private structure
5268 *
5269 * Free all receive software resources
5270 **/
5271 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5272 {
5273 int i;
5274
5275 for (i = 0; i < adapter->num_rx_queues; i++)
5276 if (adapter->rx_ring[i]->desc)
5277 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5278 }
5279
5280 /**
5281 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5282 * @netdev: network interface device structure
5283 * @new_mtu: new value for maximum frame size
5284 *
5285 * Returns 0 on success, negative on failure
5286 **/
5287 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5288 {
5289 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5290 struct ixgbe_hw *hw = &adapter->hw;
5291 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5292
5293 /* MTU < 68 is an error and causes problems on some kernels */
5294 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5295 hw->mac.type != ixgbe_mac_X540) {
5296 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5297 return -EINVAL;
5298 } else {
5299 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5300 return -EINVAL;
5301 }
5302
5303 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5304 /* must set new MTU before calling down or up */
5305 netdev->mtu = new_mtu;
5306
5307 if (netif_running(netdev))
5308 ixgbe_reinit_locked(adapter);
5309
5310 return 0;
5311 }
5312
5313 /**
5314 * ixgbe_open - Called when a network interface is made active
5315 * @netdev: network interface device structure
5316 *
5317 * Returns 0 on success, negative value on failure
5318 *
5319 * The open entry point is called when a network interface is made
5320 * active by the system (IFF_UP). At this point all resources needed
5321 * for transmit and receive operations are allocated, the interrupt
5322 * handler is registered with the OS, the watchdog timer is started,
5323 * and the stack is notified that the interface is ready.
5324 **/
5325 static int ixgbe_open(struct net_device *netdev)
5326 {
5327 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5328 int err;
5329
5330 /* disallow open during test */
5331 if (test_bit(__IXGBE_TESTING, &adapter->state))
5332 return -EBUSY;
5333
5334 netif_carrier_off(netdev);
5335
5336 /* allocate transmit descriptors */
5337 err = ixgbe_setup_all_tx_resources(adapter);
5338 if (err)
5339 goto err_setup_tx;
5340
5341 /* allocate receive descriptors */
5342 err = ixgbe_setup_all_rx_resources(adapter);
5343 if (err)
5344 goto err_setup_rx;
5345
5346 ixgbe_configure(adapter);
5347
5348 err = ixgbe_request_irq(adapter);
5349 if (err)
5350 goto err_req_irq;
5351
5352 ixgbe_up_complete(adapter);
5353
5354 return 0;
5355
5356 err_req_irq:
5357 err_setup_rx:
5358 ixgbe_free_all_rx_resources(adapter);
5359 err_setup_tx:
5360 ixgbe_free_all_tx_resources(adapter);
5361 ixgbe_reset(adapter);
5362
5363 return err;
5364 }
5365
5366 /**
5367 * ixgbe_close - Disables a network interface
5368 * @netdev: network interface device structure
5369 *
5370 * Returns 0, this is not allowed to fail
5371 *
5372 * The close entry point is called when an interface is de-activated
5373 * by the OS. The hardware is still under the drivers control, but
5374 * needs to be disabled. A global MAC reset is issued to stop the
5375 * hardware, and all transmit and receive resources are freed.
5376 **/
5377 static int ixgbe_close(struct net_device *netdev)
5378 {
5379 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5380
5381 ixgbe_down(adapter);
5382 ixgbe_free_irq(adapter);
5383
5384 ixgbe_fdir_filter_exit(adapter);
5385
5386 ixgbe_free_all_tx_resources(adapter);
5387 ixgbe_free_all_rx_resources(adapter);
5388
5389 ixgbe_release_hw_control(adapter);
5390
5391 return 0;
5392 }
5393
5394 #ifdef CONFIG_PM
5395 static int ixgbe_resume(struct pci_dev *pdev)
5396 {
5397 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5398 struct net_device *netdev = adapter->netdev;
5399 u32 err;
5400
5401 pci_set_power_state(pdev, PCI_D0);
5402 pci_restore_state(pdev);
5403 /*
5404 * pci_restore_state clears dev->state_saved so call
5405 * pci_save_state to restore it.
5406 */
5407 pci_save_state(pdev);
5408
5409 err = pci_enable_device_mem(pdev);
5410 if (err) {
5411 e_dev_err("Cannot enable PCI device from suspend\n");
5412 return err;
5413 }
5414 pci_set_master(pdev);
5415
5416 pci_wake_from_d3(pdev, false);
5417
5418 err = ixgbe_init_interrupt_scheme(adapter);
5419 if (err) {
5420 e_dev_err("Cannot initialize interrupts for device\n");
5421 return err;
5422 }
5423
5424 ixgbe_reset(adapter);
5425
5426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5427
5428 if (netif_running(netdev)) {
5429 err = ixgbe_open(netdev);
5430 if (err)
5431 return err;
5432 }
5433
5434 netif_device_attach(netdev);
5435
5436 return 0;
5437 }
5438 #endif /* CONFIG_PM */
5439
5440 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5441 {
5442 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5443 struct net_device *netdev = adapter->netdev;
5444 struct ixgbe_hw *hw = &adapter->hw;
5445 u32 ctrl, fctrl;
5446 u32 wufc = adapter->wol;
5447 #ifdef CONFIG_PM
5448 int retval = 0;
5449 #endif
5450
5451 netif_device_detach(netdev);
5452
5453 if (netif_running(netdev)) {
5454 ixgbe_down(adapter);
5455 ixgbe_free_irq(adapter);
5456 ixgbe_free_all_tx_resources(adapter);
5457 ixgbe_free_all_rx_resources(adapter);
5458 }
5459
5460 ixgbe_clear_interrupt_scheme(adapter);
5461 #ifdef CONFIG_DCB
5462 kfree(adapter->ixgbe_ieee_pfc);
5463 kfree(adapter->ixgbe_ieee_ets);
5464 #endif
5465
5466 #ifdef CONFIG_PM
5467 retval = pci_save_state(pdev);
5468 if (retval)
5469 return retval;
5470
5471 #endif
5472 if (wufc) {
5473 ixgbe_set_rx_mode(netdev);
5474
5475 /* turn on all-multi mode if wake on multicast is enabled */
5476 if (wufc & IXGBE_WUFC_MC) {
5477 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5478 fctrl |= IXGBE_FCTRL_MPE;
5479 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5480 }
5481
5482 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5483 ctrl |= IXGBE_CTRL_GIO_DIS;
5484 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5485
5486 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5487 } else {
5488 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5489 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5490 }
5491
5492 switch (hw->mac.type) {
5493 case ixgbe_mac_82598EB:
5494 pci_wake_from_d3(pdev, false);
5495 break;
5496 case ixgbe_mac_82599EB:
5497 case ixgbe_mac_X540:
5498 pci_wake_from_d3(pdev, !!wufc);
5499 break;
5500 default:
5501 break;
5502 }
5503
5504 *enable_wake = !!wufc;
5505
5506 ixgbe_release_hw_control(adapter);
5507
5508 pci_disable_device(pdev);
5509
5510 return 0;
5511 }
5512
5513 #ifdef CONFIG_PM
5514 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5515 {
5516 int retval;
5517 bool wake;
5518
5519 retval = __ixgbe_shutdown(pdev, &wake);
5520 if (retval)
5521 return retval;
5522
5523 if (wake) {
5524 pci_prepare_to_sleep(pdev);
5525 } else {
5526 pci_wake_from_d3(pdev, false);
5527 pci_set_power_state(pdev, PCI_D3hot);
5528 }
5529
5530 return 0;
5531 }
5532 #endif /* CONFIG_PM */
5533
5534 static void ixgbe_shutdown(struct pci_dev *pdev)
5535 {
5536 bool wake;
5537
5538 __ixgbe_shutdown(pdev, &wake);
5539
5540 if (system_state == SYSTEM_POWER_OFF) {
5541 pci_wake_from_d3(pdev, wake);
5542 pci_set_power_state(pdev, PCI_D3hot);
5543 }
5544 }
5545
5546 /**
5547 * ixgbe_update_stats - Update the board statistics counters.
5548 * @adapter: board private structure
5549 **/
5550 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5551 {
5552 struct net_device *netdev = adapter->netdev;
5553 struct ixgbe_hw *hw = &adapter->hw;
5554 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5555 u64 total_mpc = 0;
5556 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5557 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5558 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5559 u64 bytes = 0, packets = 0;
5560 #ifdef IXGBE_FCOE
5561 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5562 unsigned int cpu;
5563 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5564 #endif /* IXGBE_FCOE */
5565
5566 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5567 test_bit(__IXGBE_RESETTING, &adapter->state))
5568 return;
5569
5570 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5571 u64 rsc_count = 0;
5572 u64 rsc_flush = 0;
5573 for (i = 0; i < 16; i++)
5574 adapter->hw_rx_no_dma_resources +=
5575 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5576 for (i = 0; i < adapter->num_rx_queues; i++) {
5577 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5578 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5579 }
5580 adapter->rsc_total_count = rsc_count;
5581 adapter->rsc_total_flush = rsc_flush;
5582 }
5583
5584 for (i = 0; i < adapter->num_rx_queues; i++) {
5585 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5586 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5587 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5588 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5589 bytes += rx_ring->stats.bytes;
5590 packets += rx_ring->stats.packets;
5591 }
5592 adapter->non_eop_descs = non_eop_descs;
5593 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5594 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5595 netdev->stats.rx_bytes = bytes;
5596 netdev->stats.rx_packets = packets;
5597
5598 bytes = 0;
5599 packets = 0;
5600 /* gather some stats to the adapter struct that are per queue */
5601 for (i = 0; i < adapter->num_tx_queues; i++) {
5602 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5603 restart_queue += tx_ring->tx_stats.restart_queue;
5604 tx_busy += tx_ring->tx_stats.tx_busy;
5605 bytes += tx_ring->stats.bytes;
5606 packets += tx_ring->stats.packets;
5607 }
5608 adapter->restart_queue = restart_queue;
5609 adapter->tx_busy = tx_busy;
5610 netdev->stats.tx_bytes = bytes;
5611 netdev->stats.tx_packets = packets;
5612
5613 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5614
5615 /* 8 register reads */
5616 for (i = 0; i < 8; i++) {
5617 /* for packet buffers not used, the register should read 0 */
5618 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5619 missed_rx += mpc;
5620 hwstats->mpc[i] += mpc;
5621 total_mpc += hwstats->mpc[i];
5622 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5623 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5624 switch (hw->mac.type) {
5625 case ixgbe_mac_82598EB:
5626 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5627 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5628 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5629 hwstats->pxonrxc[i] +=
5630 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5631 break;
5632 case ixgbe_mac_82599EB:
5633 case ixgbe_mac_X540:
5634 hwstats->pxonrxc[i] +=
5635 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5636 break;
5637 default:
5638 break;
5639 }
5640 }
5641
5642 /*16 register reads */
5643 for (i = 0; i < 16; i++) {
5644 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5645 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5646 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5647 (hw->mac.type == ixgbe_mac_X540)) {
5648 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5649 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5650 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5651 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5652 }
5653 }
5654
5655 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5656 /* work around hardware counting issue */
5657 hwstats->gprc -= missed_rx;
5658
5659 ixgbe_update_xoff_received(adapter);
5660
5661 /* 82598 hardware only has a 32 bit counter in the high register */
5662 switch (hw->mac.type) {
5663 case ixgbe_mac_82598EB:
5664 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5665 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5666 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5667 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5668 break;
5669 case ixgbe_mac_X540:
5670 /* OS2BMC stats are X540 only*/
5671 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5672 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5673 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5674 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5675 case ixgbe_mac_82599EB:
5676 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5677 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5678 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5679 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5680 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5681 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5682 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5683 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5684 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5685 #ifdef IXGBE_FCOE
5686 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5687 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5688 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5689 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5690 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5691 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5692 /* Add up per cpu counters for total ddp aloc fail */
5693 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5694 for_each_possible_cpu(cpu) {
5695 fcoe_noddp_counts_sum +=
5696 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5697 fcoe_noddp_ext_buff_counts_sum +=
5698 *per_cpu_ptr(fcoe->
5699 pcpu_noddp_ext_buff, cpu);
5700 }
5701 }
5702 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5703 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5704 #endif /* IXGBE_FCOE */
5705 break;
5706 default:
5707 break;
5708 }
5709 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5710 hwstats->bprc += bprc;
5711 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5712 if (hw->mac.type == ixgbe_mac_82598EB)
5713 hwstats->mprc -= bprc;
5714 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5715 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5716 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5717 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5718 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5719 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5720 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5721 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5722 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5723 hwstats->lxontxc += lxon;
5724 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5725 hwstats->lxofftxc += lxoff;
5726 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5727 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5728 /*
5729 * 82598 errata - tx of flow control packets is included in tx counters
5730 */
5731 xon_off_tot = lxon + lxoff;
5732 hwstats->gptc -= xon_off_tot;
5733 hwstats->mptc -= xon_off_tot;
5734 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5735 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5736 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5737 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5738 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5739 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5740 hwstats->ptc64 -= xon_off_tot;
5741 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5742 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5743 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5744 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5745 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5746 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5747
5748 /* Fill out the OS statistics structure */
5749 netdev->stats.multicast = hwstats->mprc;
5750
5751 /* Rx Errors */
5752 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5753 netdev->stats.rx_dropped = 0;
5754 netdev->stats.rx_length_errors = hwstats->rlec;
5755 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5756 netdev->stats.rx_missed_errors = total_mpc;
5757 }
5758
5759 /**
5760 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5761 * @adapter - pointer to the device adapter structure
5762 **/
5763 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5764 {
5765 struct ixgbe_hw *hw = &adapter->hw;
5766 int i;
5767
5768 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5769 return;
5770
5771 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5772
5773 /* if interface is down do nothing */
5774 if (test_bit(__IXGBE_DOWN, &adapter->state))
5775 return;
5776
5777 /* do nothing if we are not using signature filters */
5778 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5779 return;
5780
5781 adapter->fdir_overflow++;
5782
5783 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5784 for (i = 0; i < adapter->num_tx_queues; i++)
5785 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5786 &(adapter->tx_ring[i]->state));
5787 /* re-enable flow director interrupts */
5788 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5789 } else {
5790 e_err(probe, "failed to finish FDIR re-initialization, "
5791 "ignored adding FDIR ATR filters\n");
5792 }
5793 }
5794
5795 /**
5796 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5797 * @adapter - pointer to the device adapter structure
5798 *
5799 * This function serves two purposes. First it strobes the interrupt lines
5800 * in order to make certain interrupts are occuring. Secondly it sets the
5801 * bits needed to check for TX hangs. As a result we should immediately
5802 * determine if a hang has occured.
5803 */
5804 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5805 {
5806 struct ixgbe_hw *hw = &adapter->hw;
5807 u64 eics = 0;
5808 int i;
5809
5810 /* If we're down or resetting, just bail */
5811 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5812 test_bit(__IXGBE_RESETTING, &adapter->state))
5813 return;
5814
5815 /* Force detection of hung controller */
5816 if (netif_carrier_ok(adapter->netdev)) {
5817 for (i = 0; i < adapter->num_tx_queues; i++)
5818 set_check_for_tx_hang(adapter->tx_ring[i]);
5819 }
5820
5821 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5822 /*
5823 * for legacy and MSI interrupts don't set any bits
5824 * that are enabled for EIAM, because this operation
5825 * would set *both* EIMS and EICS for any bit in EIAM
5826 */
5827 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5828 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5829 } else {
5830 /* get one bit for every active tx/rx interrupt vector */
5831 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5832 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5833 if (qv->rx.ring || qv->tx.ring)
5834 eics |= ((u64)1 << i);
5835 }
5836 }
5837
5838 /* Cause software interrupt to ensure rings are cleaned */
5839 ixgbe_irq_rearm_queues(adapter, eics);
5840
5841 }
5842
5843 /**
5844 * ixgbe_watchdog_update_link - update the link status
5845 * @adapter - pointer to the device adapter structure
5846 * @link_speed - pointer to a u32 to store the link_speed
5847 **/
5848 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5849 {
5850 struct ixgbe_hw *hw = &adapter->hw;
5851 u32 link_speed = adapter->link_speed;
5852 bool link_up = adapter->link_up;
5853 int i;
5854
5855 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5856 return;
5857
5858 if (hw->mac.ops.check_link) {
5859 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5860 } else {
5861 /* always assume link is up, if no check link function */
5862 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5863 link_up = true;
5864 }
5865 if (link_up) {
5866 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5867 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5868 hw->mac.ops.fc_enable(hw, i);
5869 } else {
5870 hw->mac.ops.fc_enable(hw, 0);
5871 }
5872 }
5873
5874 if (link_up ||
5875 time_after(jiffies, (adapter->link_check_timeout +
5876 IXGBE_TRY_LINK_TIMEOUT))) {
5877 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5878 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5879 IXGBE_WRITE_FLUSH(hw);
5880 }
5881
5882 adapter->link_up = link_up;
5883 adapter->link_speed = link_speed;
5884 }
5885
5886 /**
5887 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5888 * print link up message
5889 * @adapter - pointer to the device adapter structure
5890 **/
5891 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5892 {
5893 struct net_device *netdev = adapter->netdev;
5894 struct ixgbe_hw *hw = &adapter->hw;
5895 u32 link_speed = adapter->link_speed;
5896 bool flow_rx, flow_tx;
5897
5898 /* only continue if link was previously down */
5899 if (netif_carrier_ok(netdev))
5900 return;
5901
5902 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5903
5904 switch (hw->mac.type) {
5905 case ixgbe_mac_82598EB: {
5906 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5907 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5908 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5909 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5910 }
5911 break;
5912 case ixgbe_mac_X540:
5913 case ixgbe_mac_82599EB: {
5914 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5915 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5916 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5917 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5918 }
5919 break;
5920 default:
5921 flow_tx = false;
5922 flow_rx = false;
5923 break;
5924 }
5925 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5926 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5927 "10 Gbps" :
5928 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5929 "1 Gbps" :
5930 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5931 "100 Mbps" :
5932 "unknown speed"))),
5933 ((flow_rx && flow_tx) ? "RX/TX" :
5934 (flow_rx ? "RX" :
5935 (flow_tx ? "TX" : "None"))));
5936
5937 netif_carrier_on(netdev);
5938 ixgbe_check_vf_rate_limit(adapter);
5939 }
5940
5941 /**
5942 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5943 * print link down message
5944 * @adapter - pointer to the adapter structure
5945 **/
5946 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
5947 {
5948 struct net_device *netdev = adapter->netdev;
5949 struct ixgbe_hw *hw = &adapter->hw;
5950
5951 adapter->link_up = false;
5952 adapter->link_speed = 0;
5953
5954 /* only continue if link was up previously */
5955 if (!netif_carrier_ok(netdev))
5956 return;
5957
5958 /* poll for SFP+ cable when link is down */
5959 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5960 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5961
5962 e_info(drv, "NIC Link is Down\n");
5963 netif_carrier_off(netdev);
5964 }
5965
5966 /**
5967 * ixgbe_watchdog_flush_tx - flush queues on link down
5968 * @adapter - pointer to the device adapter structure
5969 **/
5970 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5971 {
5972 int i;
5973 int some_tx_pending = 0;
5974
5975 if (!netif_carrier_ok(adapter->netdev)) {
5976 for (i = 0; i < adapter->num_tx_queues; i++) {
5977 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5978 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5979 some_tx_pending = 1;
5980 break;
5981 }
5982 }
5983
5984 if (some_tx_pending) {
5985 /* We've lost link, so the controller stops DMA,
5986 * but we've got queued Tx work that's never going
5987 * to get done, so reset controller to flush Tx.
5988 * (Do the reset outside of interrupt context).
5989 */
5990 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5991 }
5992 }
5993 }
5994
5995 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5996 {
5997 u32 ssvpc;
5998
5999 /* Do not perform spoof check for 82598 */
6000 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6001 return;
6002
6003 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6004
6005 /*
6006 * ssvpc register is cleared on read, if zero then no
6007 * spoofed packets in the last interval.
6008 */
6009 if (!ssvpc)
6010 return;
6011
6012 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6013 }
6014
6015 /**
6016 * ixgbe_watchdog_subtask - check and bring link up
6017 * @adapter - pointer to the device adapter structure
6018 **/
6019 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6020 {
6021 /* if interface is down do nothing */
6022 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6023 test_bit(__IXGBE_RESETTING, &adapter->state))
6024 return;
6025
6026 ixgbe_watchdog_update_link(adapter);
6027
6028 if (adapter->link_up)
6029 ixgbe_watchdog_link_is_up(adapter);
6030 else
6031 ixgbe_watchdog_link_is_down(adapter);
6032
6033 ixgbe_spoof_check(adapter);
6034 ixgbe_update_stats(adapter);
6035
6036 ixgbe_watchdog_flush_tx(adapter);
6037 }
6038
6039 /**
6040 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6041 * @adapter - the ixgbe adapter structure
6042 **/
6043 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6044 {
6045 struct ixgbe_hw *hw = &adapter->hw;
6046 s32 err;
6047
6048 /* not searching for SFP so there is nothing to do here */
6049 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6050 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6051 return;
6052
6053 /* someone else is in init, wait until next service event */
6054 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6055 return;
6056
6057 err = hw->phy.ops.identify_sfp(hw);
6058 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6059 goto sfp_out;
6060
6061 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6062 /* If no cable is present, then we need to reset
6063 * the next time we find a good cable. */
6064 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6065 }
6066
6067 /* exit on error */
6068 if (err)
6069 goto sfp_out;
6070
6071 /* exit if reset not needed */
6072 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6073 goto sfp_out;
6074
6075 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6076
6077 /*
6078 * A module may be identified correctly, but the EEPROM may not have
6079 * support for that module. setup_sfp() will fail in that case, so
6080 * we should not allow that module to load.
6081 */
6082 if (hw->mac.type == ixgbe_mac_82598EB)
6083 err = hw->phy.ops.reset(hw);
6084 else
6085 err = hw->mac.ops.setup_sfp(hw);
6086
6087 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6088 goto sfp_out;
6089
6090 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6091 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6092
6093 sfp_out:
6094 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6095
6096 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6097 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6098 e_dev_err("failed to initialize because an unsupported "
6099 "SFP+ module type was detected.\n");
6100 e_dev_err("Reload the driver after installing a "
6101 "supported module.\n");
6102 unregister_netdev(adapter->netdev);
6103 }
6104 }
6105
6106 /**
6107 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6108 * @adapter - the ixgbe adapter structure
6109 **/
6110 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6111 {
6112 struct ixgbe_hw *hw = &adapter->hw;
6113 u32 autoneg;
6114 bool negotiation;
6115
6116 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6117 return;
6118
6119 /* someone else is in init, wait until next service event */
6120 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6121 return;
6122
6123 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6124
6125 autoneg = hw->phy.autoneg_advertised;
6126 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6127 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6128 hw->mac.autotry_restart = false;
6129 if (hw->mac.ops.setup_link)
6130 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6131
6132 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6133 adapter->link_check_timeout = jiffies;
6134 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6135 }
6136
6137 #ifdef CONFIG_PCI_IOV
6138 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6139 {
6140 int vf;
6141 struct ixgbe_hw *hw = &adapter->hw;
6142 struct net_device *netdev = adapter->netdev;
6143 u32 gpc;
6144 u32 ciaa, ciad;
6145
6146 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6147 if (gpc) /* If incrementing then no need for the check below */
6148 return;
6149 /*
6150 * Check to see if a bad DMA write target from an errant or
6151 * malicious VF has caused a PCIe error. If so then we can
6152 * issue a VFLR to the offending VF(s) and then resume without
6153 * requesting a full slot reset.
6154 */
6155
6156 for (vf = 0; vf < adapter->num_vfs; vf++) {
6157 ciaa = (vf << 16) | 0x80000000;
6158 /* 32 bit read so align, we really want status at offset 6 */
6159 ciaa |= PCI_COMMAND;
6160 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6161 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6162 ciaa &= 0x7FFFFFFF;
6163 /* disable debug mode asap after reading data */
6164 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6165 /* Get the upper 16 bits which will be the PCI status reg */
6166 ciad >>= 16;
6167 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6168 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6169 /* Issue VFLR */
6170 ciaa = (vf << 16) | 0x80000000;
6171 ciaa |= 0xA8;
6172 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6173 ciad = 0x00008000; /* VFLR */
6174 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6175 ciaa &= 0x7FFFFFFF;
6176 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6177 }
6178 }
6179 }
6180
6181 #endif
6182 /**
6183 * ixgbe_service_timer - Timer Call-back
6184 * @data: pointer to adapter cast into an unsigned long
6185 **/
6186 static void ixgbe_service_timer(unsigned long data)
6187 {
6188 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6189 unsigned long next_event_offset;
6190 bool ready = true;
6191
6192 #ifdef CONFIG_PCI_IOV
6193 ready = false;
6194
6195 /*
6196 * don't bother with SR-IOV VF DMA hang check if there are
6197 * no VFs or the link is down
6198 */
6199 if (!adapter->num_vfs ||
6200 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6201 ready = true;
6202 goto normal_timer_service;
6203 }
6204
6205 /* If we have VFs allocated then we must check for DMA hangs */
6206 ixgbe_check_for_bad_vf(adapter);
6207 next_event_offset = HZ / 50;
6208 adapter->timer_event_accumulator++;
6209
6210 if (adapter->timer_event_accumulator >= 100) {
6211 ready = true;
6212 adapter->timer_event_accumulator = 0;
6213 }
6214
6215 goto schedule_event;
6216
6217 normal_timer_service:
6218 #endif
6219 /* poll faster when waiting for link */
6220 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6221 next_event_offset = HZ / 10;
6222 else
6223 next_event_offset = HZ * 2;
6224
6225 #ifdef CONFIG_PCI_IOV
6226 schedule_event:
6227 #endif
6228 /* Reset the timer */
6229 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6230
6231 if (ready)
6232 ixgbe_service_event_schedule(adapter);
6233 }
6234
6235 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6236 {
6237 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6238 return;
6239
6240 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6241
6242 /* If we're already down or resetting, just bail */
6243 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6244 test_bit(__IXGBE_RESETTING, &adapter->state))
6245 return;
6246
6247 ixgbe_dump(adapter);
6248 netdev_err(adapter->netdev, "Reset adapter\n");
6249 adapter->tx_timeout_count++;
6250
6251 ixgbe_reinit_locked(adapter);
6252 }
6253
6254 /**
6255 * ixgbe_service_task - manages and runs subtasks
6256 * @work: pointer to work_struct containing our data
6257 **/
6258 static void ixgbe_service_task(struct work_struct *work)
6259 {
6260 struct ixgbe_adapter *adapter = container_of(work,
6261 struct ixgbe_adapter,
6262 service_task);
6263
6264 ixgbe_reset_subtask(adapter);
6265 ixgbe_sfp_detection_subtask(adapter);
6266 ixgbe_sfp_link_config_subtask(adapter);
6267 ixgbe_check_overtemp_subtask(adapter);
6268 ixgbe_watchdog_subtask(adapter);
6269 ixgbe_fdir_reinit_subtask(adapter);
6270 ixgbe_check_hang_subtask(adapter);
6271
6272 ixgbe_service_event_complete(adapter);
6273 }
6274
6275 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6276 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6277 {
6278 struct ixgbe_adv_tx_context_desc *context_desc;
6279 u16 i = tx_ring->next_to_use;
6280
6281 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6282
6283 i++;
6284 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6285
6286 /* set bits to identify this as an advanced context descriptor */
6287 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6288
6289 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6290 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6291 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6292 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6293 }
6294
6295 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6296 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6297 {
6298 int err;
6299 u32 vlan_macip_lens, type_tucmd;
6300 u32 mss_l4len_idx, l4len;
6301
6302 if (!skb_is_gso(skb))
6303 return 0;
6304
6305 if (skb_header_cloned(skb)) {
6306 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6307 if (err)
6308 return err;
6309 }
6310
6311 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6312 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6313
6314 if (protocol == __constant_htons(ETH_P_IP)) {
6315 struct iphdr *iph = ip_hdr(skb);
6316 iph->tot_len = 0;
6317 iph->check = 0;
6318 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6319 iph->daddr, 0,
6320 IPPROTO_TCP,
6321 0);
6322 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6323 } else if (skb_is_gso_v6(skb)) {
6324 ipv6_hdr(skb)->payload_len = 0;
6325 tcp_hdr(skb)->check =
6326 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6327 &ipv6_hdr(skb)->daddr,
6328 0, IPPROTO_TCP, 0);
6329 }
6330
6331 l4len = tcp_hdrlen(skb);
6332 *hdr_len = skb_transport_offset(skb) + l4len;
6333
6334 /* mss_l4len_id: use 1 as index for TSO */
6335 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6336 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6337 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6338
6339 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6340 vlan_macip_lens = skb_network_header_len(skb);
6341 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6342 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6343
6344 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6345 mss_l4len_idx);
6346
6347 return 1;
6348 }
6349
6350 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6351 struct sk_buff *skb, u32 tx_flags,
6352 __be16 protocol)
6353 {
6354 u32 vlan_macip_lens = 0;
6355 u32 mss_l4len_idx = 0;
6356 u32 type_tucmd = 0;
6357
6358 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6359 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6360 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
6361 return false;
6362 } else {
6363 u8 l4_hdr = 0;
6364 switch (protocol) {
6365 case __constant_htons(ETH_P_IP):
6366 vlan_macip_lens |= skb_network_header_len(skb);
6367 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6368 l4_hdr = ip_hdr(skb)->protocol;
6369 break;
6370 case __constant_htons(ETH_P_IPV6):
6371 vlan_macip_lens |= skb_network_header_len(skb);
6372 l4_hdr = ipv6_hdr(skb)->nexthdr;
6373 break;
6374 default:
6375 if (unlikely(net_ratelimit())) {
6376 dev_warn(tx_ring->dev,
6377 "partial checksum but proto=%x!\n",
6378 skb->protocol);
6379 }
6380 break;
6381 }
6382
6383 switch (l4_hdr) {
6384 case IPPROTO_TCP:
6385 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6386 mss_l4len_idx = tcp_hdrlen(skb) <<
6387 IXGBE_ADVTXD_L4LEN_SHIFT;
6388 break;
6389 case IPPROTO_SCTP:
6390 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6391 mss_l4len_idx = sizeof(struct sctphdr) <<
6392 IXGBE_ADVTXD_L4LEN_SHIFT;
6393 break;
6394 case IPPROTO_UDP:
6395 mss_l4len_idx = sizeof(struct udphdr) <<
6396 IXGBE_ADVTXD_L4LEN_SHIFT;
6397 break;
6398 default:
6399 if (unlikely(net_ratelimit())) {
6400 dev_warn(tx_ring->dev,
6401 "partial checksum but l4 proto=%x!\n",
6402 skb->protocol);
6403 }
6404 break;
6405 }
6406 }
6407
6408 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6409 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6410
6411 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6412 type_tucmd, mss_l4len_idx);
6413
6414 return (skb->ip_summed == CHECKSUM_PARTIAL);
6415 }
6416
6417 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6418 {
6419 /* set type for advanced descriptor with frame checksum insertion */
6420 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6421 IXGBE_ADVTXD_DCMD_IFCS |
6422 IXGBE_ADVTXD_DCMD_DEXT);
6423
6424 /* set HW vlan bit if vlan is present */
6425 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6426 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6427
6428 /* set segmentation enable bits for TSO/FSO */
6429 #ifdef IXGBE_FCOE
6430 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6431 #else
6432 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6433 #endif
6434 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6435
6436 return cmd_type;
6437 }
6438
6439 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6440 {
6441 __le32 olinfo_status =
6442 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6443
6444 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6445 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6446 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6447 /* enble IPv4 checksum for TSO */
6448 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6449 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6450 }
6451
6452 /* enable L4 checksum for TSO and TX checksum offload */
6453 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6454 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6455
6456 #ifdef IXGBE_FCOE
6457 /* use index 1 context for FCOE/FSO */
6458 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6459 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6460 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6461
6462 #endif
6463 /*
6464 * Check Context must be set if Tx switch is enabled, which it
6465 * always is for case where virtual functions are running
6466 */
6467 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6468 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6469
6470 return olinfo_status;
6471 }
6472
6473 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6474 IXGBE_TXD_CMD_RS)
6475
6476 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6477 struct sk_buff *skb,
6478 struct ixgbe_tx_buffer *first,
6479 u32 tx_flags,
6480 const u8 hdr_len)
6481 {
6482 struct device *dev = tx_ring->dev;
6483 struct ixgbe_tx_buffer *tx_buffer_info;
6484 union ixgbe_adv_tx_desc *tx_desc;
6485 dma_addr_t dma;
6486 __le32 cmd_type, olinfo_status;
6487 struct skb_frag_struct *frag;
6488 unsigned int f = 0;
6489 unsigned int data_len = skb->data_len;
6490 unsigned int size = skb_headlen(skb);
6491 u32 offset = 0;
6492 u32 paylen = skb->len - hdr_len;
6493 u16 i = tx_ring->next_to_use;
6494 u16 gso_segs;
6495
6496 #ifdef IXGBE_FCOE
6497 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6498 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6499 data_len -= sizeof(struct fcoe_crc_eof);
6500 } else {
6501 size -= sizeof(struct fcoe_crc_eof) - data_len;
6502 data_len = 0;
6503 }
6504 }
6505
6506 #endif
6507 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6508 if (dma_mapping_error(dev, dma))
6509 goto dma_error;
6510
6511 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6512 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6513
6514 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6515
6516 for (;;) {
6517 while (size > IXGBE_MAX_DATA_PER_TXD) {
6518 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6519 tx_desc->read.cmd_type_len =
6520 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6521 tx_desc->read.olinfo_status = olinfo_status;
6522
6523 offset += IXGBE_MAX_DATA_PER_TXD;
6524 size -= IXGBE_MAX_DATA_PER_TXD;
6525
6526 tx_desc++;
6527 i++;
6528 if (i == tx_ring->count) {
6529 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6530 i = 0;
6531 }
6532 }
6533
6534 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6535 tx_buffer_info->length = offset + size;
6536 tx_buffer_info->tx_flags = tx_flags;
6537 tx_buffer_info->dma = dma;
6538
6539 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6540 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6541 tx_desc->read.olinfo_status = olinfo_status;
6542
6543 if (!data_len)
6544 break;
6545
6546 frag = &skb_shinfo(skb)->frags[f];
6547 #ifdef IXGBE_FCOE
6548 size = min_t(unsigned int, data_len, skb_frag_size(frag));
6549 #else
6550 size = skb_frag_size(frag);
6551 #endif
6552 data_len -= size;
6553 f++;
6554
6555 offset = 0;
6556 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6557
6558 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
6559 if (dma_mapping_error(dev, dma))
6560 goto dma_error;
6561
6562 tx_desc++;
6563 i++;
6564 if (i == tx_ring->count) {
6565 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6566 i = 0;
6567 }
6568 }
6569
6570 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6571
6572 i++;
6573 if (i == tx_ring->count)
6574 i = 0;
6575
6576 tx_ring->next_to_use = i;
6577
6578 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6579 gso_segs = skb_shinfo(skb)->gso_segs;
6580 #ifdef IXGBE_FCOE
6581 /* adjust for FCoE Sequence Offload */
6582 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6583 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6584 skb_shinfo(skb)->gso_size);
6585 #endif /* IXGBE_FCOE */
6586 else
6587 gso_segs = 1;
6588
6589 /* multiply data chunks by size of headers */
6590 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6591 tx_buffer_info->gso_segs = gso_segs;
6592 tx_buffer_info->skb = skb;
6593
6594 /* set the timestamp */
6595 first->time_stamp = jiffies;
6596
6597 /*
6598 * Force memory writes to complete before letting h/w
6599 * know there are new descriptors to fetch. (Only
6600 * applicable for weak-ordered memory model archs,
6601 * such as IA-64).
6602 */
6603 wmb();
6604
6605 /* set next_to_watch value indicating a packet is present */
6606 first->next_to_watch = tx_desc;
6607
6608 /* notify HW of packet */
6609 writel(i, tx_ring->tail);
6610
6611 return;
6612 dma_error:
6613 dev_err(dev, "TX DMA map failed\n");
6614
6615 /* clear dma mappings for failed tx_buffer_info map */
6616 for (;;) {
6617 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6618 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6619 if (tx_buffer_info == first)
6620 break;
6621 if (i == 0)
6622 i = tx_ring->count;
6623 i--;
6624 }
6625
6626 dev_kfree_skb_any(skb);
6627
6628 tx_ring->next_to_use = i;
6629 }
6630
6631 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6632 u32 tx_flags, __be16 protocol)
6633 {
6634 struct ixgbe_q_vector *q_vector = ring->q_vector;
6635 union ixgbe_atr_hash_dword input = { .dword = 0 };
6636 union ixgbe_atr_hash_dword common = { .dword = 0 };
6637 union {
6638 unsigned char *network;
6639 struct iphdr *ipv4;
6640 struct ipv6hdr *ipv6;
6641 } hdr;
6642 struct tcphdr *th;
6643 __be16 vlan_id;
6644
6645 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6646 if (!q_vector)
6647 return;
6648
6649 /* do nothing if sampling is disabled */
6650 if (!ring->atr_sample_rate)
6651 return;
6652
6653 ring->atr_count++;
6654
6655 /* snag network header to get L4 type and address */
6656 hdr.network = skb_network_header(skb);
6657
6658 /* Currently only IPv4/IPv6 with TCP is supported */
6659 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6660 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6661 (protocol != __constant_htons(ETH_P_IP) ||
6662 hdr.ipv4->protocol != IPPROTO_TCP))
6663 return;
6664
6665 th = tcp_hdr(skb);
6666
6667 /* skip this packet since it is invalid or the socket is closing */
6668 if (!th || th->fin)
6669 return;
6670
6671 /* sample on all syn packets or once every atr sample count */
6672 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6673 return;
6674
6675 /* reset sample count */
6676 ring->atr_count = 0;
6677
6678 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6679
6680 /*
6681 * src and dst are inverted, think how the receiver sees them
6682 *
6683 * The input is broken into two sections, a non-compressed section
6684 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6685 * is XORed together and stored in the compressed dword.
6686 */
6687 input.formatted.vlan_id = vlan_id;
6688
6689 /*
6690 * since src port and flex bytes occupy the same word XOR them together
6691 * and write the value to source port portion of compressed dword
6692 */
6693 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6694 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6695 else
6696 common.port.src ^= th->dest ^ protocol;
6697 common.port.dst ^= th->source;
6698
6699 if (protocol == __constant_htons(ETH_P_IP)) {
6700 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6701 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6702 } else {
6703 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6704 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6705 hdr.ipv6->saddr.s6_addr32[1] ^
6706 hdr.ipv6->saddr.s6_addr32[2] ^
6707 hdr.ipv6->saddr.s6_addr32[3] ^
6708 hdr.ipv6->daddr.s6_addr32[0] ^
6709 hdr.ipv6->daddr.s6_addr32[1] ^
6710 hdr.ipv6->daddr.s6_addr32[2] ^
6711 hdr.ipv6->daddr.s6_addr32[3];
6712 }
6713
6714 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6715 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6716 input, common, ring->queue_index);
6717 }
6718
6719 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6720 {
6721 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6722 /* Herbert's original patch had:
6723 * smp_mb__after_netif_stop_queue();
6724 * but since that doesn't exist yet, just open code it. */
6725 smp_mb();
6726
6727 /* We need to check again in a case another CPU has just
6728 * made room available. */
6729 if (likely(ixgbe_desc_unused(tx_ring) < size))
6730 return -EBUSY;
6731
6732 /* A reprieve! - use start_queue because it doesn't call schedule */
6733 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6734 ++tx_ring->tx_stats.restart_queue;
6735 return 0;
6736 }
6737
6738 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6739 {
6740 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6741 return 0;
6742 return __ixgbe_maybe_stop_tx(tx_ring, size);
6743 }
6744
6745 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6746 {
6747 struct ixgbe_adapter *adapter = netdev_priv(dev);
6748 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6749 smp_processor_id();
6750 #ifdef IXGBE_FCOE
6751 __be16 protocol = vlan_get_protocol(skb);
6752
6753 if (((protocol == htons(ETH_P_FCOE)) ||
6754 (protocol == htons(ETH_P_FIP))) &&
6755 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6756 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6757 txq += adapter->ring_feature[RING_F_FCOE].mask;
6758 return txq;
6759 }
6760 #endif
6761
6762 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6763 while (unlikely(txq >= dev->real_num_tx_queues))
6764 txq -= dev->real_num_tx_queues;
6765 return txq;
6766 }
6767
6768 return skb_tx_hash(dev, skb);
6769 }
6770
6771 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6772 struct ixgbe_adapter *adapter,
6773 struct ixgbe_ring *tx_ring)
6774 {
6775 struct ixgbe_tx_buffer *first;
6776 int tso;
6777 u32 tx_flags = 0;
6778 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6779 unsigned short f;
6780 #endif
6781 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6782 __be16 protocol = skb->protocol;
6783 u8 hdr_len = 0;
6784
6785 /*
6786 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6787 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6788 * + 2 desc gap to keep tail from touching head,
6789 * + 1 desc for context descriptor,
6790 * otherwise try next time
6791 */
6792 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6793 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6794 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6795 #else
6796 count += skb_shinfo(skb)->nr_frags;
6797 #endif
6798 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6799 tx_ring->tx_stats.tx_busy++;
6800 return NETDEV_TX_BUSY;
6801 }
6802
6803 #ifdef CONFIG_PCI_IOV
6804 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6805 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6806
6807 #endif
6808 /* if we have a HW VLAN tag being added default to the HW one */
6809 if (vlan_tx_tag_present(skb)) {
6810 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6811 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6812 /* else if it is a SW VLAN check the next protocol and store the tag */
6813 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6814 struct vlan_hdr *vhdr, _vhdr;
6815 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6816 if (!vhdr)
6817 goto out_drop;
6818
6819 protocol = vhdr->h_vlan_encapsulated_proto;
6820 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6821 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6822 }
6823
6824 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6825 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6826 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6827 (skb->priority != TC_PRIO_CONTROL))) {
6828 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6829 tx_flags |= (skb->priority & 0x7) <<
6830 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6831 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6832 struct vlan_ethhdr *vhdr;
6833 if (skb_header_cloned(skb) &&
6834 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6835 goto out_drop;
6836 vhdr = (struct vlan_ethhdr *)skb->data;
6837 vhdr->h_vlan_TCI = htons(tx_flags >>
6838 IXGBE_TX_FLAGS_VLAN_SHIFT);
6839 } else {
6840 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6841 }
6842 }
6843
6844 /* record the location of the first descriptor for this packet */
6845 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6846
6847 #ifdef IXGBE_FCOE
6848 /* setup tx offload for FCoE */
6849 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6850 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6851 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6852 if (tso < 0)
6853 goto out_drop;
6854 else if (tso)
6855 tx_flags |= IXGBE_TX_FLAGS_FSO |
6856 IXGBE_TX_FLAGS_FCOE;
6857 else
6858 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6859
6860 goto xmit_fcoe;
6861 }
6862
6863 #endif /* IXGBE_FCOE */
6864 /* setup IPv4/IPv6 offloads */
6865 if (protocol == __constant_htons(ETH_P_IP))
6866 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6867
6868 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6869 if (tso < 0)
6870 goto out_drop;
6871 else if (tso)
6872 tx_flags |= IXGBE_TX_FLAGS_TSO;
6873 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6874 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6875
6876 /* add the ATR filter if ATR is on */
6877 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6878 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6879
6880 #ifdef IXGBE_FCOE
6881 xmit_fcoe:
6882 #endif /* IXGBE_FCOE */
6883 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6884
6885 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6886
6887 return NETDEV_TX_OK;
6888
6889 out_drop:
6890 dev_kfree_skb_any(skb);
6891 return NETDEV_TX_OK;
6892 }
6893
6894 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6895 {
6896 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6897 struct ixgbe_ring *tx_ring;
6898
6899 tx_ring = adapter->tx_ring[skb->queue_mapping];
6900 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6901 }
6902
6903 /**
6904 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6905 * @netdev: network interface device structure
6906 * @p: pointer to an address structure
6907 *
6908 * Returns 0 on success, negative on failure
6909 **/
6910 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6911 {
6912 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6913 struct ixgbe_hw *hw = &adapter->hw;
6914 struct sockaddr *addr = p;
6915
6916 if (!is_valid_ether_addr(addr->sa_data))
6917 return -EADDRNOTAVAIL;
6918
6919 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6920 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6921
6922 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6923 IXGBE_RAH_AV);
6924
6925 return 0;
6926 }
6927
6928 static int
6929 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6930 {
6931 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6932 struct ixgbe_hw *hw = &adapter->hw;
6933 u16 value;
6934 int rc;
6935
6936 if (prtad != hw->phy.mdio.prtad)
6937 return -EINVAL;
6938 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6939 if (!rc)
6940 rc = value;
6941 return rc;
6942 }
6943
6944 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6945 u16 addr, u16 value)
6946 {
6947 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6948 struct ixgbe_hw *hw = &adapter->hw;
6949
6950 if (prtad != hw->phy.mdio.prtad)
6951 return -EINVAL;
6952 return hw->phy.ops.write_reg(hw, addr, devad, value);
6953 }
6954
6955 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6956 {
6957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6958
6959 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6960 }
6961
6962 /**
6963 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6964 * netdev->dev_addrs
6965 * @netdev: network interface device structure
6966 *
6967 * Returns non-zero on failure
6968 **/
6969 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6970 {
6971 int err = 0;
6972 struct ixgbe_adapter *adapter = netdev_priv(dev);
6973 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6974
6975 if (is_valid_ether_addr(mac->san_addr)) {
6976 rtnl_lock();
6977 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6978 rtnl_unlock();
6979 }
6980 return err;
6981 }
6982
6983 /**
6984 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6985 * netdev->dev_addrs
6986 * @netdev: network interface device structure
6987 *
6988 * Returns non-zero on failure
6989 **/
6990 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6991 {
6992 int err = 0;
6993 struct ixgbe_adapter *adapter = netdev_priv(dev);
6994 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6995
6996 if (is_valid_ether_addr(mac->san_addr)) {
6997 rtnl_lock();
6998 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6999 rtnl_unlock();
7000 }
7001 return err;
7002 }
7003
7004 #ifdef CONFIG_NET_POLL_CONTROLLER
7005 /*
7006 * Polling 'interrupt' - used by things like netconsole to send skbs
7007 * without having to re-enable interrupts. It's not called while
7008 * the interrupt routine is executing.
7009 */
7010 static void ixgbe_netpoll(struct net_device *netdev)
7011 {
7012 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7013 int i;
7014
7015 /* if interface is down do nothing */
7016 if (test_bit(__IXGBE_DOWN, &adapter->state))
7017 return;
7018
7019 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7020 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7021 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7022 for (i = 0; i < num_q_vectors; i++) {
7023 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7024 ixgbe_msix_clean_rings(0, q_vector);
7025 }
7026 } else {
7027 ixgbe_intr(adapter->pdev->irq, netdev);
7028 }
7029 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7030 }
7031 #endif
7032
7033 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7034 struct rtnl_link_stats64 *stats)
7035 {
7036 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7037 int i;
7038
7039 rcu_read_lock();
7040 for (i = 0; i < adapter->num_rx_queues; i++) {
7041 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7042 u64 bytes, packets;
7043 unsigned int start;
7044
7045 if (ring) {
7046 do {
7047 start = u64_stats_fetch_begin_bh(&ring->syncp);
7048 packets = ring->stats.packets;
7049 bytes = ring->stats.bytes;
7050 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7051 stats->rx_packets += packets;
7052 stats->rx_bytes += bytes;
7053 }
7054 }
7055
7056 for (i = 0; i < adapter->num_tx_queues; i++) {
7057 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7058 u64 bytes, packets;
7059 unsigned int start;
7060
7061 if (ring) {
7062 do {
7063 start = u64_stats_fetch_begin_bh(&ring->syncp);
7064 packets = ring->stats.packets;
7065 bytes = ring->stats.bytes;
7066 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7067 stats->tx_packets += packets;
7068 stats->tx_bytes += bytes;
7069 }
7070 }
7071 rcu_read_unlock();
7072 /* following stats updated by ixgbe_watchdog_task() */
7073 stats->multicast = netdev->stats.multicast;
7074 stats->rx_errors = netdev->stats.rx_errors;
7075 stats->rx_length_errors = netdev->stats.rx_length_errors;
7076 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7077 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7078 return stats;
7079 }
7080
7081 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7082 * #adapter: pointer to ixgbe_adapter
7083 * @tc: number of traffic classes currently enabled
7084 *
7085 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7086 * 802.1Q priority maps to a packet buffer that exists.
7087 */
7088 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7089 {
7090 struct ixgbe_hw *hw = &adapter->hw;
7091 u32 reg, rsave;
7092 int i;
7093
7094 /* 82598 have a static priority to TC mapping that can not
7095 * be changed so no validation is needed.
7096 */
7097 if (hw->mac.type == ixgbe_mac_82598EB)
7098 return;
7099
7100 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7101 rsave = reg;
7102
7103 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7104 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7105
7106 /* If up2tc is out of bounds default to zero */
7107 if (up2tc > tc)
7108 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7109 }
7110
7111 if (reg != rsave)
7112 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7113
7114 return;
7115 }
7116
7117
7118 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7119 * classes.
7120 *
7121 * @netdev: net device to configure
7122 * @tc: number of traffic classes to enable
7123 */
7124 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7125 {
7126 struct ixgbe_adapter *adapter = netdev_priv(dev);
7127 struct ixgbe_hw *hw = &adapter->hw;
7128
7129 /* Multiple traffic classes requires multiple queues */
7130 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7131 e_err(drv, "Enable failed, needs MSI-X\n");
7132 return -EINVAL;
7133 }
7134
7135 /* Hardware supports up to 8 traffic classes */
7136 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
7137 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7138 return -EINVAL;
7139
7140 /* Hardware has to reinitialize queues and interrupts to
7141 * match packet buffer alignment. Unfortunantly, the
7142 * hardware is not flexible enough to do this dynamically.
7143 */
7144 if (netif_running(dev))
7145 ixgbe_close(dev);
7146 ixgbe_clear_interrupt_scheme(adapter);
7147
7148 if (tc) {
7149 netdev_set_num_tc(dev, tc);
7150 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7151
7152 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7153 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7154
7155 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7156 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7157 } else {
7158 netdev_reset_tc(dev);
7159
7160 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7161
7162 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7163 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7164
7165 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7166 adapter->dcb_cfg.pfc_mode_enable = false;
7167 }
7168
7169 ixgbe_init_interrupt_scheme(adapter);
7170 ixgbe_validate_rtr(adapter, tc);
7171 if (netif_running(dev))
7172 ixgbe_open(dev);
7173
7174 return 0;
7175 }
7176
7177 void ixgbe_do_reset(struct net_device *netdev)
7178 {
7179 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7180
7181 if (netif_running(netdev))
7182 ixgbe_reinit_locked(adapter);
7183 else
7184 ixgbe_reset(adapter);
7185 }
7186
7187 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7188 {
7189 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7190
7191 #ifdef CONFIG_DCB
7192 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7193 data &= ~NETIF_F_HW_VLAN_RX;
7194 #endif
7195
7196 /* return error if RXHASH is being enabled when RSS is not supported */
7197 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7198 data &= ~NETIF_F_RXHASH;
7199
7200 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7201 if (!(data & NETIF_F_RXCSUM))
7202 data &= ~NETIF_F_LRO;
7203
7204 /* Turn off LRO if not RSC capable or invalid ITR settings */
7205 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7206 data &= ~NETIF_F_LRO;
7207 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7208 (adapter->rx_itr_setting != 1 &&
7209 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7210 data &= ~NETIF_F_LRO;
7211 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7212 }
7213
7214 return data;
7215 }
7216
7217 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7218 {
7219 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7220 bool need_reset = false;
7221
7222 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7223 if (!(data & NETIF_F_RXCSUM))
7224 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7225 else
7226 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7227
7228 /* Make sure RSC matches LRO, reset if change */
7229 if (!!(data & NETIF_F_LRO) !=
7230 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7231 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7232 switch (adapter->hw.mac.type) {
7233 case ixgbe_mac_X540:
7234 case ixgbe_mac_82599EB:
7235 need_reset = true;
7236 break;
7237 default:
7238 break;
7239 }
7240 }
7241
7242 /*
7243 * Check if Flow Director n-tuple support was enabled or disabled. If
7244 * the state changed, we need to reset.
7245 */
7246 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7247 /* turn off ATR, enable perfect filters and reset */
7248 if (data & NETIF_F_NTUPLE) {
7249 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7250 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7251 need_reset = true;
7252 }
7253 } else if (!(data & NETIF_F_NTUPLE)) {
7254 /* turn off Flow Director, set ATR and reset */
7255 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7256 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7257 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7258 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7259 need_reset = true;
7260 }
7261
7262 if (need_reset)
7263 ixgbe_do_reset(netdev);
7264
7265 return 0;
7266
7267 }
7268
7269 static const struct net_device_ops ixgbe_netdev_ops = {
7270 .ndo_open = ixgbe_open,
7271 .ndo_stop = ixgbe_close,
7272 .ndo_start_xmit = ixgbe_xmit_frame,
7273 .ndo_select_queue = ixgbe_select_queue,
7274 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7275 .ndo_validate_addr = eth_validate_addr,
7276 .ndo_set_mac_address = ixgbe_set_mac,
7277 .ndo_change_mtu = ixgbe_change_mtu,
7278 .ndo_tx_timeout = ixgbe_tx_timeout,
7279 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7280 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7281 .ndo_do_ioctl = ixgbe_ioctl,
7282 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7283 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7284 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7285 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7286 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7287 .ndo_get_stats64 = ixgbe_get_stats64,
7288 .ndo_setup_tc = ixgbe_setup_tc,
7289 #ifdef CONFIG_NET_POLL_CONTROLLER
7290 .ndo_poll_controller = ixgbe_netpoll,
7291 #endif
7292 #ifdef IXGBE_FCOE
7293 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7294 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7295 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7296 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7297 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7298 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7299 #endif /* IXGBE_FCOE */
7300 .ndo_set_features = ixgbe_set_features,
7301 .ndo_fix_features = ixgbe_fix_features,
7302 };
7303
7304 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7305 const struct ixgbe_info *ii)
7306 {
7307 #ifdef CONFIG_PCI_IOV
7308 struct ixgbe_hw *hw = &adapter->hw;
7309
7310 if (hw->mac.type == ixgbe_mac_82598EB)
7311 return;
7312
7313 /* The 82599 supports up to 64 VFs per physical function
7314 * but this implementation limits allocation to 63 so that
7315 * basic networking resources are still available to the
7316 * physical function
7317 */
7318 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7319 ixgbe_enable_sriov(adapter, ii);
7320 #endif /* CONFIG_PCI_IOV */
7321 }
7322
7323 /**
7324 * ixgbe_probe - Device Initialization Routine
7325 * @pdev: PCI device information struct
7326 * @ent: entry in ixgbe_pci_tbl
7327 *
7328 * Returns 0 on success, negative on failure
7329 *
7330 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7331 * The OS initialization, configuring of the adapter private structure,
7332 * and a hardware reset occur.
7333 **/
7334 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7335 const struct pci_device_id *ent)
7336 {
7337 struct net_device *netdev;
7338 struct ixgbe_adapter *adapter = NULL;
7339 struct ixgbe_hw *hw;
7340 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7341 static int cards_found;
7342 int i, err, pci_using_dac;
7343 u8 part_str[IXGBE_PBANUM_LENGTH];
7344 unsigned int indices = num_possible_cpus();
7345 #ifdef IXGBE_FCOE
7346 u16 device_caps;
7347 #endif
7348 u32 eec;
7349 u16 wol_cap;
7350
7351 /* Catch broken hardware that put the wrong VF device ID in
7352 * the PCIe SR-IOV capability.
7353 */
7354 if (pdev->is_virtfn) {
7355 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7356 pci_name(pdev), pdev->vendor, pdev->device);
7357 return -EINVAL;
7358 }
7359
7360 err = pci_enable_device_mem(pdev);
7361 if (err)
7362 return err;
7363
7364 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7365 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7366 pci_using_dac = 1;
7367 } else {
7368 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7369 if (err) {
7370 err = dma_set_coherent_mask(&pdev->dev,
7371 DMA_BIT_MASK(32));
7372 if (err) {
7373 dev_err(&pdev->dev,
7374 "No usable DMA configuration, aborting\n");
7375 goto err_dma;
7376 }
7377 }
7378 pci_using_dac = 0;
7379 }
7380
7381 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7382 IORESOURCE_MEM), ixgbe_driver_name);
7383 if (err) {
7384 dev_err(&pdev->dev,
7385 "pci_request_selected_regions failed 0x%x\n", err);
7386 goto err_pci_reg;
7387 }
7388
7389 pci_enable_pcie_error_reporting(pdev);
7390
7391 pci_set_master(pdev);
7392 pci_save_state(pdev);
7393
7394 #ifdef CONFIG_IXGBE_DCB
7395 indices *= MAX_TRAFFIC_CLASS;
7396 #endif
7397
7398 if (ii->mac == ixgbe_mac_82598EB)
7399 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7400 else
7401 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7402
7403 #ifdef IXGBE_FCOE
7404 indices += min_t(unsigned int, num_possible_cpus(),
7405 IXGBE_MAX_FCOE_INDICES);
7406 #endif
7407 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7408 if (!netdev) {
7409 err = -ENOMEM;
7410 goto err_alloc_etherdev;
7411 }
7412
7413 SET_NETDEV_DEV(netdev, &pdev->dev);
7414
7415 adapter = netdev_priv(netdev);
7416 pci_set_drvdata(pdev, adapter);
7417
7418 adapter->netdev = netdev;
7419 adapter->pdev = pdev;
7420 hw = &adapter->hw;
7421 hw->back = adapter;
7422 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7423
7424 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7425 pci_resource_len(pdev, 0));
7426 if (!hw->hw_addr) {
7427 err = -EIO;
7428 goto err_ioremap;
7429 }
7430
7431 for (i = 1; i <= 5; i++) {
7432 if (pci_resource_len(pdev, i) == 0)
7433 continue;
7434 }
7435
7436 netdev->netdev_ops = &ixgbe_netdev_ops;
7437 ixgbe_set_ethtool_ops(netdev);
7438 netdev->watchdog_timeo = 5 * HZ;
7439 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7440
7441 adapter->bd_number = cards_found;
7442
7443 /* Setup hw api */
7444 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7445 hw->mac.type = ii->mac;
7446
7447 /* EEPROM */
7448 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7449 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7450 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7451 if (!(eec & (1 << 8)))
7452 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7453
7454 /* PHY */
7455 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7456 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7457 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7458 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7459 hw->phy.mdio.mmds = 0;
7460 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7461 hw->phy.mdio.dev = netdev;
7462 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7463 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7464
7465 ii->get_invariants(hw);
7466
7467 /* setup the private structure */
7468 err = ixgbe_sw_init(adapter);
7469 if (err)
7470 goto err_sw_init;
7471
7472 /* Make it possible the adapter to be woken up via WOL */
7473 switch (adapter->hw.mac.type) {
7474 case ixgbe_mac_82599EB:
7475 case ixgbe_mac_X540:
7476 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7477 break;
7478 default:
7479 break;
7480 }
7481
7482 /*
7483 * If there is a fan on this device and it has failed log the
7484 * failure.
7485 */
7486 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7487 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7488 if (esdp & IXGBE_ESDP_SDP1)
7489 e_crit(probe, "Fan has stopped, replace the adapter\n");
7490 }
7491
7492 /* reset_hw fills in the perm_addr as well */
7493 hw->phy.reset_if_overtemp = true;
7494 err = hw->mac.ops.reset_hw(hw);
7495 hw->phy.reset_if_overtemp = false;
7496 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7497 hw->mac.type == ixgbe_mac_82598EB) {
7498 err = 0;
7499 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7500 e_dev_err("failed to load because an unsupported SFP+ "
7501 "module type was detected.\n");
7502 e_dev_err("Reload the driver after installing a supported "
7503 "module.\n");
7504 goto err_sw_init;
7505 } else if (err) {
7506 e_dev_err("HW Init failed: %d\n", err);
7507 goto err_sw_init;
7508 }
7509
7510 ixgbe_probe_vf(adapter, ii);
7511
7512 netdev->features = NETIF_F_SG |
7513 NETIF_F_IP_CSUM |
7514 NETIF_F_IPV6_CSUM |
7515 NETIF_F_HW_VLAN_TX |
7516 NETIF_F_HW_VLAN_RX |
7517 NETIF_F_HW_VLAN_FILTER |
7518 NETIF_F_TSO |
7519 NETIF_F_TSO6 |
7520 NETIF_F_RXHASH |
7521 NETIF_F_RXCSUM;
7522
7523 netdev->hw_features = netdev->features;
7524
7525 switch (adapter->hw.mac.type) {
7526 case ixgbe_mac_82599EB:
7527 case ixgbe_mac_X540:
7528 netdev->features |= NETIF_F_SCTP_CSUM;
7529 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7530 NETIF_F_NTUPLE;
7531 break;
7532 default:
7533 break;
7534 }
7535
7536 netdev->vlan_features |= NETIF_F_TSO;
7537 netdev->vlan_features |= NETIF_F_TSO6;
7538 netdev->vlan_features |= NETIF_F_IP_CSUM;
7539 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7540 netdev->vlan_features |= NETIF_F_SG;
7541
7542 netdev->priv_flags |= IFF_UNICAST_FLT;
7543
7544 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7545 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7546 IXGBE_FLAG_DCB_ENABLED);
7547
7548 #ifdef CONFIG_IXGBE_DCB
7549 netdev->dcbnl_ops = &dcbnl_ops;
7550 #endif
7551
7552 #ifdef IXGBE_FCOE
7553 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7554 if (hw->mac.ops.get_device_caps) {
7555 hw->mac.ops.get_device_caps(hw, &device_caps);
7556 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7557 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7558 }
7559 }
7560 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7561 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7562 netdev->vlan_features |= NETIF_F_FSO;
7563 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7564 }
7565 #endif /* IXGBE_FCOE */
7566 if (pci_using_dac) {
7567 netdev->features |= NETIF_F_HIGHDMA;
7568 netdev->vlan_features |= NETIF_F_HIGHDMA;
7569 }
7570
7571 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7572 netdev->hw_features |= NETIF_F_LRO;
7573 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7574 netdev->features |= NETIF_F_LRO;
7575
7576 /* make sure the EEPROM is good */
7577 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7578 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7579 err = -EIO;
7580 goto err_eeprom;
7581 }
7582
7583 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7584 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7585
7586 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7587 e_dev_err("invalid MAC address\n");
7588 err = -EIO;
7589 goto err_eeprom;
7590 }
7591
7592 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7593 if (hw->mac.ops.disable_tx_laser &&
7594 ((hw->phy.multispeed_fiber) ||
7595 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7596 (hw->mac.type == ixgbe_mac_82599EB))))
7597 hw->mac.ops.disable_tx_laser(hw);
7598
7599 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7600 (unsigned long) adapter);
7601
7602 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7603 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7604
7605 err = ixgbe_init_interrupt_scheme(adapter);
7606 if (err)
7607 goto err_sw_init;
7608
7609 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7610 netdev->hw_features &= ~NETIF_F_RXHASH;
7611 netdev->features &= ~NETIF_F_RXHASH;
7612 }
7613
7614 /* WOL not supported for all but the following */
7615 adapter->wol = 0;
7616 switch (pdev->device) {
7617 case IXGBE_DEV_ID_82599_SFP:
7618 /* Only this subdevice supports WOL */
7619 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7620 adapter->wol = IXGBE_WUFC_MAG;
7621 break;
7622 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7623 /* All except this subdevice support WOL */
7624 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7625 adapter->wol = IXGBE_WUFC_MAG;
7626 break;
7627 case IXGBE_DEV_ID_82599_KX4:
7628 adapter->wol = IXGBE_WUFC_MAG;
7629 break;
7630 case IXGBE_DEV_ID_X540T:
7631 /* Check eeprom to see if it is enabled */
7632 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7633 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7634
7635 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7636 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7637 (hw->bus.func == 0)))
7638 adapter->wol = IXGBE_WUFC_MAG;
7639 break;
7640 }
7641 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7642
7643 /* save off EEPROM version number */
7644 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7645 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7646
7647 /* pick up the PCI bus settings for reporting later */
7648 hw->mac.ops.get_bus_info(hw);
7649
7650 /* print bus type/speed/width info */
7651 e_dev_info("(PCI Express:%s:%s) %pM\n",
7652 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7653 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7654 "Unknown"),
7655 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7656 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7657 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7658 "Unknown"),
7659 netdev->dev_addr);
7660
7661 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7662 if (err)
7663 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7664 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7665 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7666 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7667 part_str);
7668 else
7669 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7670 hw->mac.type, hw->phy.type, part_str);
7671
7672 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7673 e_dev_warn("PCI-Express bandwidth available for this card is "
7674 "not sufficient for optimal performance.\n");
7675 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7676 "is required.\n");
7677 }
7678
7679 /* reset the hardware with the new settings */
7680 err = hw->mac.ops.start_hw(hw);
7681
7682 if (err == IXGBE_ERR_EEPROM_VERSION) {
7683 /* We are running on a pre-production device, log a warning */
7684 e_dev_warn("This device is a pre-production adapter/LOM. "
7685 "Please be aware there may be issues associated "
7686 "with your hardware. If you are experiencing "
7687 "problems please contact your Intel or hardware "
7688 "representative who provided you with this "
7689 "hardware.\n");
7690 }
7691 strcpy(netdev->name, "eth%d");
7692 err = register_netdev(netdev);
7693 if (err)
7694 goto err_register;
7695
7696 /* carrier off reporting is important to ethtool even BEFORE open */
7697 netif_carrier_off(netdev);
7698
7699 #ifdef CONFIG_IXGBE_DCA
7700 if (dca_add_requester(&pdev->dev) == 0) {
7701 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7702 ixgbe_setup_dca(adapter);
7703 }
7704 #endif
7705 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7706 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7707 for (i = 0; i < adapter->num_vfs; i++)
7708 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7709 }
7710
7711 /* firmware requires driver version to be 0xFFFFFFFF
7712 * since os does not support feature
7713 */
7714 if (hw->mac.ops.set_fw_drv_ver)
7715 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7716 0xFF);
7717
7718 /* add san mac addr to netdev */
7719 ixgbe_add_sanmac_netdev(netdev);
7720
7721 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7722 cards_found++;
7723 return 0;
7724
7725 err_register:
7726 ixgbe_release_hw_control(adapter);
7727 ixgbe_clear_interrupt_scheme(adapter);
7728 err_sw_init:
7729 err_eeprom:
7730 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7731 ixgbe_disable_sriov(adapter);
7732 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7733 iounmap(hw->hw_addr);
7734 err_ioremap:
7735 free_netdev(netdev);
7736 err_alloc_etherdev:
7737 pci_release_selected_regions(pdev,
7738 pci_select_bars(pdev, IORESOURCE_MEM));
7739 err_pci_reg:
7740 err_dma:
7741 pci_disable_device(pdev);
7742 return err;
7743 }
7744
7745 /**
7746 * ixgbe_remove - Device Removal Routine
7747 * @pdev: PCI device information struct
7748 *
7749 * ixgbe_remove is called by the PCI subsystem to alert the driver
7750 * that it should release a PCI device. The could be caused by a
7751 * Hot-Plug event, or because the driver is going to be removed from
7752 * memory.
7753 **/
7754 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7755 {
7756 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7757 struct net_device *netdev = adapter->netdev;
7758
7759 set_bit(__IXGBE_DOWN, &adapter->state);
7760 cancel_work_sync(&adapter->service_task);
7761
7762 #ifdef CONFIG_IXGBE_DCA
7763 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7764 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7765 dca_remove_requester(&pdev->dev);
7766 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7767 }
7768
7769 #endif
7770 #ifdef IXGBE_FCOE
7771 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7772 ixgbe_cleanup_fcoe(adapter);
7773
7774 #endif /* IXGBE_FCOE */
7775
7776 /* remove the added san mac */
7777 ixgbe_del_sanmac_netdev(netdev);
7778
7779 if (netdev->reg_state == NETREG_REGISTERED)
7780 unregister_netdev(netdev);
7781
7782 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7783 if (!(ixgbe_check_vf_assignment(adapter)))
7784 ixgbe_disable_sriov(adapter);
7785 else
7786 e_dev_warn("Unloading driver while VFs are assigned "
7787 "- VFs will not be deallocated\n");
7788 }
7789
7790 ixgbe_clear_interrupt_scheme(adapter);
7791
7792 ixgbe_release_hw_control(adapter);
7793
7794 iounmap(adapter->hw.hw_addr);
7795 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7796 IORESOURCE_MEM));
7797
7798 e_dev_info("complete\n");
7799
7800 free_netdev(netdev);
7801
7802 pci_disable_pcie_error_reporting(pdev);
7803
7804 pci_disable_device(pdev);
7805 }
7806
7807 /**
7808 * ixgbe_io_error_detected - called when PCI error is detected
7809 * @pdev: Pointer to PCI device
7810 * @state: The current pci connection state
7811 *
7812 * This function is called after a PCI bus error affecting
7813 * this device has been detected.
7814 */
7815 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7816 pci_channel_state_t state)
7817 {
7818 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7819 struct net_device *netdev = adapter->netdev;
7820
7821 #ifdef CONFIG_PCI_IOV
7822 struct pci_dev *bdev, *vfdev;
7823 u32 dw0, dw1, dw2, dw3;
7824 int vf, pos;
7825 u16 req_id, pf_func;
7826
7827 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7828 adapter->num_vfs == 0)
7829 goto skip_bad_vf_detection;
7830
7831 bdev = pdev->bus->self;
7832 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7833 bdev = bdev->bus->self;
7834
7835 if (!bdev)
7836 goto skip_bad_vf_detection;
7837
7838 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7839 if (!pos)
7840 goto skip_bad_vf_detection;
7841
7842 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7843 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7844 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7845 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7846
7847 req_id = dw1 >> 16;
7848 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7849 if (!(req_id & 0x0080))
7850 goto skip_bad_vf_detection;
7851
7852 pf_func = req_id & 0x01;
7853 if ((pf_func & 1) == (pdev->devfn & 1)) {
7854 unsigned int device_id;
7855
7856 vf = (req_id & 0x7F) >> 1;
7857 e_dev_err("VF %d has caused a PCIe error\n", vf);
7858 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7859 "%8.8x\tdw3: %8.8x\n",
7860 dw0, dw1, dw2, dw3);
7861 switch (adapter->hw.mac.type) {
7862 case ixgbe_mac_82599EB:
7863 device_id = IXGBE_82599_VF_DEVICE_ID;
7864 break;
7865 case ixgbe_mac_X540:
7866 device_id = IXGBE_X540_VF_DEVICE_ID;
7867 break;
7868 default:
7869 device_id = 0;
7870 break;
7871 }
7872
7873 /* Find the pci device of the offending VF */
7874 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7875 while (vfdev) {
7876 if (vfdev->devfn == (req_id & 0xFF))
7877 break;
7878 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7879 device_id, vfdev);
7880 }
7881 /*
7882 * There's a slim chance the VF could have been hot plugged,
7883 * so if it is no longer present we don't need to issue the
7884 * VFLR. Just clean up the AER in that case.
7885 */
7886 if (vfdev) {
7887 e_dev_err("Issuing VFLR to VF %d\n", vf);
7888 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7889 }
7890
7891 pci_cleanup_aer_uncorrect_error_status(pdev);
7892 }
7893
7894 /*
7895 * Even though the error may have occurred on the other port
7896 * we still need to increment the vf error reference count for
7897 * both ports because the I/O resume function will be called
7898 * for both of them.
7899 */
7900 adapter->vferr_refcount++;
7901
7902 return PCI_ERS_RESULT_RECOVERED;
7903
7904 skip_bad_vf_detection:
7905 #endif /* CONFIG_PCI_IOV */
7906 netif_device_detach(netdev);
7907
7908 if (state == pci_channel_io_perm_failure)
7909 return PCI_ERS_RESULT_DISCONNECT;
7910
7911 if (netif_running(netdev))
7912 ixgbe_down(adapter);
7913 pci_disable_device(pdev);
7914
7915 /* Request a slot reset. */
7916 return PCI_ERS_RESULT_NEED_RESET;
7917 }
7918
7919 /**
7920 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7921 * @pdev: Pointer to PCI device
7922 *
7923 * Restart the card from scratch, as if from a cold-boot.
7924 */
7925 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7926 {
7927 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7928 pci_ers_result_t result;
7929 int err;
7930
7931 if (pci_enable_device_mem(pdev)) {
7932 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7933 result = PCI_ERS_RESULT_DISCONNECT;
7934 } else {
7935 pci_set_master(pdev);
7936 pci_restore_state(pdev);
7937 pci_save_state(pdev);
7938
7939 pci_wake_from_d3(pdev, false);
7940
7941 ixgbe_reset(adapter);
7942 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7943 result = PCI_ERS_RESULT_RECOVERED;
7944 }
7945
7946 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7947 if (err) {
7948 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7949 "failed 0x%0x\n", err);
7950 /* non-fatal, continue */
7951 }
7952
7953 return result;
7954 }
7955
7956 /**
7957 * ixgbe_io_resume - called when traffic can start flowing again.
7958 * @pdev: Pointer to PCI device
7959 *
7960 * This callback is called when the error recovery driver tells us that
7961 * its OK to resume normal operation.
7962 */
7963 static void ixgbe_io_resume(struct pci_dev *pdev)
7964 {
7965 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7966 struct net_device *netdev = adapter->netdev;
7967
7968 #ifdef CONFIG_PCI_IOV
7969 if (adapter->vferr_refcount) {
7970 e_info(drv, "Resuming after VF err\n");
7971 adapter->vferr_refcount--;
7972 return;
7973 }
7974
7975 #endif
7976 if (netif_running(netdev))
7977 ixgbe_up(adapter);
7978
7979 netif_device_attach(netdev);
7980 }
7981
7982 static struct pci_error_handlers ixgbe_err_handler = {
7983 .error_detected = ixgbe_io_error_detected,
7984 .slot_reset = ixgbe_io_slot_reset,
7985 .resume = ixgbe_io_resume,
7986 };
7987
7988 static struct pci_driver ixgbe_driver = {
7989 .name = ixgbe_driver_name,
7990 .id_table = ixgbe_pci_tbl,
7991 .probe = ixgbe_probe,
7992 .remove = __devexit_p(ixgbe_remove),
7993 #ifdef CONFIG_PM
7994 .suspend = ixgbe_suspend,
7995 .resume = ixgbe_resume,
7996 #endif
7997 .shutdown = ixgbe_shutdown,
7998 .err_handler = &ixgbe_err_handler
7999 };
8000
8001 /**
8002 * ixgbe_init_module - Driver Registration Routine
8003 *
8004 * ixgbe_init_module is the first routine called when the driver is
8005 * loaded. All it does is register with the PCI subsystem.
8006 **/
8007 static int __init ixgbe_init_module(void)
8008 {
8009 int ret;
8010 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
8011 pr_info("%s\n", ixgbe_copyright);
8012
8013 #ifdef CONFIG_IXGBE_DCA
8014 dca_register_notify(&dca_notifier);
8015 #endif
8016
8017 ret = pci_register_driver(&ixgbe_driver);
8018 return ret;
8019 }
8020
8021 module_init(ixgbe_init_module);
8022
8023 /**
8024 * ixgbe_exit_module - Driver Exit Cleanup Routine
8025 *
8026 * ixgbe_exit_module is called just before the driver is removed
8027 * from memory.
8028 **/
8029 static void __exit ixgbe_exit_module(void)
8030 {
8031 #ifdef CONFIG_IXGBE_DCA
8032 dca_unregister_notify(&dca_notifier);
8033 #endif
8034 pci_unregister_driver(&ixgbe_driver);
8035 rcu_barrier(); /* Wait for completion of call_rcu()'s */
8036 }
8037
8038 #ifdef CONFIG_IXGBE_DCA
8039 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
8040 void *p)
8041 {
8042 int ret_val;
8043
8044 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
8045 __ixgbe_notify_dca);
8046
8047 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8048 }
8049
8050 #endif /* CONFIG_IXGBE_DCA */
8051
8052 module_exit(ixgbe_exit_module);
8053
8054 /* ixgbe_main.c */
Linux kernel - Deliverables
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