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ixgbe: Identify FCoE rings earlier to resolve memory corruption w/ FCoE
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
49
50 #include "ixgbe.h"
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
54
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
58 #ifdef IXGBE_FCOE
59 char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
61 #else
62 static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64 #endif
65 #define MAJ 3
66 #define MIN 8
67 #define BUILD 21
68 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
69 __stringify(BUILD) "-k"
70 const char ixgbe_driver_version[] = DRV_VERSION;
71 static const char ixgbe_copyright[] =
72 "Copyright (c) 1999-2012 Intel Corporation.";
73
74 static const struct ixgbe_info *ixgbe_info_tbl[] = {
75 [board_82598] = &ixgbe_82598_info,
76 [board_82599] = &ixgbe_82599_info,
77 [board_X540] = &ixgbe_X540_info,
78 };
79
80 /* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
88 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
117 /* required last entry */
118 {0, }
119 };
120 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
122 #ifdef CONFIG_IXGBE_DCA
123 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
124 void *p);
125 static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129 };
130 #endif
131
132 #ifdef CONFIG_PCI_IOV
133 static unsigned int max_vfs;
134 module_param(max_vfs, uint, 0);
135 MODULE_PARM_DESC(max_vfs,
136 "Maximum number of virtual functions to allocate per physical function");
137 #endif /* CONFIG_PCI_IOV */
138
139 static unsigned int allow_unsupported_sfp;
140 module_param(allow_unsupported_sfp, uint, 0);
141 MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
144 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145 static int debug = -1;
146 module_param(debug, int, 0);
147 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
149 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151 MODULE_LICENSE("GPL");
152 MODULE_VERSION(DRV_VERSION);
153
154 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155 {
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159 }
160
161 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162 {
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
165 /* flush memory to make sure state is correct before next watchdog */
166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168 }
169
170 struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173 };
174
175 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205 };
206
207
208 /*
209 * ixgbe_regdump - register printout routine
210 */
211 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212 {
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
275 pr_info("%-15s %08x\n", reginfo->name,
276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
282 pr_err("%-15s", rname);
283 for (j = 0; j < 8; j++)
284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
286 }
287
288 }
289
290 /*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293 static void ixgbe_dump(struct ixgbe_adapter *adapter)
294 {
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
300 struct ixgbe_tx_buffer *tx_buffer;
301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
315 pr_info("Device Name state "
316 "trans_start last_rx\n");
317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
326 pr_info(" Register Name Value\n");
327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
377 tx_buffer = &tx_ring->tx_buffer_info[i];
378 u0 = (struct my_u0 *)tx_desc;
379 pr_info("T [0x%03X] %016llX %016llX %016llX"
380 " %04X %p %016llX %p", i,
381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
390 pr_cont(" NTC/U\n");
391 else if (i == tx_ring->next_to_use)
392 pr_cont(" NTU\n");
393 else if (i == tx_ring->next_to_clean)
394 pr_cont(" NTC\n");
395 else
396 pr_cont("\n");
397
398 if (netif_msg_pktdata(adapter) &&
399 dma_unmap_len(tx_buffer, len) != 0)
400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
402 phys_to_virt(dma_unmap_addr(tx_buffer,
403 dma)),
404 dma_unmap_len(tx_buffer, len),
405 true);
406 }
407 }
408
409 /* Print RX Rings Summary */
410 rx_ring_summary:
411 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
412 pr_info("Queue [NTU] [NTC]\n");
413 for (n = 0; n < adapter->num_rx_queues; n++) {
414 rx_ring = adapter->rx_ring[n];
415 pr_info("%5d %5X %5X\n",
416 n, rx_ring->next_to_use, rx_ring->next_to_clean);
417 }
418
419 /* Print RX Rings */
420 if (!netif_msg_rx_status(adapter))
421 goto exit;
422
423 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
424
425 /* Advanced Receive Descriptor (Read) Format
426 * 63 1 0
427 * +-----------------------------------------------------+
428 * 0 | Packet Buffer Address [63:1] |A0/NSE|
429 * +----------------------------------------------+------+
430 * 8 | Header Buffer Address [63:1] | DD |
431 * +-----------------------------------------------------+
432 *
433 *
434 * Advanced Receive Descriptor (Write-Back) Format
435 *
436 * 63 48 47 32 31 30 21 20 16 15 4 3 0
437 * +------------------------------------------------------+
438 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
439 * | Checksum Ident | | | | Type | Type |
440 * +------------------------------------------------------+
441 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
442 * +------------------------------------------------------+
443 * 63 48 47 32 31 20 19 0
444 */
445 for (n = 0; n < adapter->num_rx_queues; n++) {
446 rx_ring = adapter->rx_ring[n];
447 pr_info("------------------------------------\n");
448 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
449 pr_info("------------------------------------\n");
450 pr_info("R [desc] [ PktBuf A0] "
451 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
452 "<-- Adv Rx Read format\n");
453 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
454 "[vl er S cks ln] ---------------- [bi->skb] "
455 "<-- Adv Rx Write-Back format\n");
456
457 for (i = 0; i < rx_ring->count; i++) {
458 rx_buffer_info = &rx_ring->rx_buffer_info[i];
459 rx_desc = IXGBE_RX_DESC(rx_ring, i);
460 u0 = (struct my_u0 *)rx_desc;
461 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
462 if (staterr & IXGBE_RXD_STAT_DD) {
463 /* Descriptor Done */
464 pr_info("RWB[0x%03X] %016llX "
465 "%016llX ---------------- %p", i,
466 le64_to_cpu(u0->a),
467 le64_to_cpu(u0->b),
468 rx_buffer_info->skb);
469 } else {
470 pr_info("R [0x%03X] %016llX "
471 "%016llX %016llX %p", i,
472 le64_to_cpu(u0->a),
473 le64_to_cpu(u0->b),
474 (u64)rx_buffer_info->dma,
475 rx_buffer_info->skb);
476
477 if (netif_msg_pktdata(adapter)) {
478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
480 phys_to_virt(rx_buffer_info->dma),
481 ixgbe_rx_bufsz(rx_ring), true);
482 }
483 }
484
485 if (i == rx_ring->next_to_use)
486 pr_cont(" NTU\n");
487 else if (i == rx_ring->next_to_clean)
488 pr_cont(" NTC\n");
489 else
490 pr_cont("\n");
491
492 }
493 }
494
495 exit:
496 return;
497 }
498
499 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
500 {
501 u32 ctrl_ext;
502
503 /* Let firmware take over control of h/w */
504 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
505 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
506 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
507 }
508
509 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
510 {
511 u32 ctrl_ext;
512
513 /* Let firmware know the driver has taken over */
514 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
516 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
517 }
518
519 /*
520 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
521 * @adapter: pointer to adapter struct
522 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
523 * @queue: queue to map the corresponding interrupt to
524 * @msix_vector: the vector to map to the corresponding queue
525 *
526 */
527 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
528 u8 queue, u8 msix_vector)
529 {
530 u32 ivar, index;
531 struct ixgbe_hw *hw = &adapter->hw;
532 switch (hw->mac.type) {
533 case ixgbe_mac_82598EB:
534 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
535 if (direction == -1)
536 direction = 0;
537 index = (((direction * 64) + queue) >> 2) & 0x1F;
538 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
539 ivar &= ~(0xFF << (8 * (queue & 0x3)));
540 ivar |= (msix_vector << (8 * (queue & 0x3)));
541 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
542 break;
543 case ixgbe_mac_82599EB:
544 case ixgbe_mac_X540:
545 if (direction == -1) {
546 /* other causes */
547 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
548 index = ((queue & 1) * 8);
549 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
550 ivar &= ~(0xFF << index);
551 ivar |= (msix_vector << index);
552 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
553 break;
554 } else {
555 /* tx or rx causes */
556 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
557 index = ((16 * (queue & 1)) + (8 * direction));
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
559 ivar &= ~(0xFF << index);
560 ivar |= (msix_vector << index);
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
562 break;
563 }
564 default:
565 break;
566 }
567 }
568
569 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
570 u64 qmask)
571 {
572 u32 mask;
573
574 switch (adapter->hw.mac.type) {
575 case ixgbe_mac_82598EB:
576 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
577 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
578 break;
579 case ixgbe_mac_82599EB:
580 case ixgbe_mac_X540:
581 mask = (qmask & 0xFFFFFFFF);
582 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
583 mask = (qmask >> 32);
584 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
585 break;
586 default:
587 break;
588 }
589 }
590
591 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
592 struct ixgbe_tx_buffer *tx_buffer)
593 {
594 if (tx_buffer->skb) {
595 dev_kfree_skb_any(tx_buffer->skb);
596 if (dma_unmap_len(tx_buffer, len))
597 dma_unmap_single(ring->dev,
598 dma_unmap_addr(tx_buffer, dma),
599 dma_unmap_len(tx_buffer, len),
600 DMA_TO_DEVICE);
601 } else if (dma_unmap_len(tx_buffer, len)) {
602 dma_unmap_page(ring->dev,
603 dma_unmap_addr(tx_buffer, dma),
604 dma_unmap_len(tx_buffer, len),
605 DMA_TO_DEVICE);
606 }
607 tx_buffer->next_to_watch = NULL;
608 tx_buffer->skb = NULL;
609 dma_unmap_len_set(tx_buffer, len, 0);
610 /* tx_buffer must be completely set up in the transmit path */
611 }
612
613 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
614 {
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
617 u32 data = 0;
618 u32 xoff[8] = {0};
619 int i;
620
621 if ((hw->fc.current_mode == ixgbe_fc_full) ||
622 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
623 switch (hw->mac.type) {
624 case ixgbe_mac_82598EB:
625 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
626 break;
627 default:
628 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
629 }
630 hwstats->lxoffrxc += data;
631
632 /* refill credits (no tx hang) if we received xoff */
633 if (!data)
634 return;
635
636 for (i = 0; i < adapter->num_tx_queues; i++)
637 clear_bit(__IXGBE_HANG_CHECK_ARMED,
638 &adapter->tx_ring[i]->state);
639 return;
640 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
641 return;
642
643 /* update stats for each tc, only valid with PFC enabled */
644 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
645 switch (hw->mac.type) {
646 case ixgbe_mac_82598EB:
647 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
648 break;
649 default:
650 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
651 }
652 hwstats->pxoffrxc[i] += xoff[i];
653 }
654
655 /* disarm tx queues that have received xoff frames */
656 for (i = 0; i < adapter->num_tx_queues; i++) {
657 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
658 u8 tc = tx_ring->dcb_tc;
659
660 if (xoff[tc])
661 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
662 }
663 }
664
665 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
666 {
667 return ring->stats.packets;
668 }
669
670 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
671 {
672 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
673 struct ixgbe_hw *hw = &adapter->hw;
674
675 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
676 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
677
678 if (head != tail)
679 return (head < tail) ?
680 tail - head : (tail + ring->count - head);
681
682 return 0;
683 }
684
685 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
686 {
687 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
688 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
689 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
690 bool ret = false;
691
692 clear_check_for_tx_hang(tx_ring);
693
694 /*
695 * Check for a hung queue, but be thorough. This verifies
696 * that a transmit has been completed since the previous
697 * check AND there is at least one packet pending. The
698 * ARMED bit is set to indicate a potential hang. The
699 * bit is cleared if a pause frame is received to remove
700 * false hang detection due to PFC or 802.3x frames. By
701 * requiring this to fail twice we avoid races with
702 * pfc clearing the ARMED bit and conditions where we
703 * run the check_tx_hang logic with a transmit completion
704 * pending but without time to complete it yet.
705 */
706 if ((tx_done_old == tx_done) && tx_pending) {
707 /* make sure it is true for two checks in a row */
708 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
709 &tx_ring->state);
710 } else {
711 /* update completed stats and continue */
712 tx_ring->tx_stats.tx_done_old = tx_done;
713 /* reset the countdown */
714 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
715 }
716
717 return ret;
718 }
719
720 /**
721 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
722 * @adapter: driver private struct
723 **/
724 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
725 {
726
727 /* Do the reset outside of interrupt context */
728 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
729 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
730 ixgbe_service_event_schedule(adapter);
731 }
732 }
733
734 /**
735 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
736 * @q_vector: structure containing interrupt and ring information
737 * @tx_ring: tx ring to clean
738 **/
739 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
740 struct ixgbe_ring *tx_ring)
741 {
742 struct ixgbe_adapter *adapter = q_vector->adapter;
743 struct ixgbe_tx_buffer *tx_buffer;
744 union ixgbe_adv_tx_desc *tx_desc;
745 unsigned int total_bytes = 0, total_packets = 0;
746 unsigned int budget = q_vector->tx.work_limit;
747 unsigned int i = tx_ring->next_to_clean;
748
749 if (test_bit(__IXGBE_DOWN, &adapter->state))
750 return true;
751
752 tx_buffer = &tx_ring->tx_buffer_info[i];
753 tx_desc = IXGBE_TX_DESC(tx_ring, i);
754 i -= tx_ring->count;
755
756 do {
757 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
758
759 /* if next_to_watch is not set then there is no work pending */
760 if (!eop_desc)
761 break;
762
763 /* prevent any other reads prior to eop_desc */
764 rmb();
765
766 /* if DD is not set pending work has not been completed */
767 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
768 break;
769
770 /* clear next_to_watch to prevent false hangs */
771 tx_buffer->next_to_watch = NULL;
772
773 /* update the statistics for this packet */
774 total_bytes += tx_buffer->bytecount;
775 total_packets += tx_buffer->gso_segs;
776
777 /* free the skb */
778 dev_kfree_skb_any(tx_buffer->skb);
779
780 /* unmap skb header data */
781 dma_unmap_single(tx_ring->dev,
782 dma_unmap_addr(tx_buffer, dma),
783 dma_unmap_len(tx_buffer, len),
784 DMA_TO_DEVICE);
785
786 /* clear tx_buffer data */
787 tx_buffer->skb = NULL;
788 dma_unmap_len_set(tx_buffer, len, 0);
789
790 /* unmap remaining buffers */
791 while (tx_desc != eop_desc) {
792 tx_buffer++;
793 tx_desc++;
794 i++;
795 if (unlikely(!i)) {
796 i -= tx_ring->count;
797 tx_buffer = tx_ring->tx_buffer_info;
798 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
799 }
800
801 /* unmap any remaining paged data */
802 if (dma_unmap_len(tx_buffer, len)) {
803 dma_unmap_page(tx_ring->dev,
804 dma_unmap_addr(tx_buffer, dma),
805 dma_unmap_len(tx_buffer, len),
806 DMA_TO_DEVICE);
807 dma_unmap_len_set(tx_buffer, len, 0);
808 }
809 }
810
811 /* move us one more past the eop_desc for start of next pkt */
812 tx_buffer++;
813 tx_desc++;
814 i++;
815 if (unlikely(!i)) {
816 i -= tx_ring->count;
817 tx_buffer = tx_ring->tx_buffer_info;
818 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
819 }
820
821 /* issue prefetch for next Tx descriptor */
822 prefetch(tx_desc);
823
824 /* update budget accounting */
825 budget--;
826 } while (likely(budget));
827
828 i += tx_ring->count;
829 tx_ring->next_to_clean = i;
830 u64_stats_update_begin(&tx_ring->syncp);
831 tx_ring->stats.bytes += total_bytes;
832 tx_ring->stats.packets += total_packets;
833 u64_stats_update_end(&tx_ring->syncp);
834 q_vector->tx.total_bytes += total_bytes;
835 q_vector->tx.total_packets += total_packets;
836
837 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
838 /* schedule immediate reset if we believe we hung */
839 struct ixgbe_hw *hw = &adapter->hw;
840 e_err(drv, "Detected Tx Unit Hang\n"
841 " Tx Queue <%d>\n"
842 " TDH, TDT <%x>, <%x>\n"
843 " next_to_use <%x>\n"
844 " next_to_clean <%x>\n"
845 "tx_buffer_info[next_to_clean]\n"
846 " time_stamp <%lx>\n"
847 " jiffies <%lx>\n",
848 tx_ring->queue_index,
849 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
850 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
851 tx_ring->next_to_use, i,
852 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
853
854 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
855
856 e_info(probe,
857 "tx hang %d detected on queue %d, resetting adapter\n",
858 adapter->tx_timeout_count + 1, tx_ring->queue_index);
859
860 /* schedule immediate reset if we believe we hung */
861 ixgbe_tx_timeout_reset(adapter);
862
863 /* the adapter is about to reset, no point in enabling stuff */
864 return true;
865 }
866
867 netdev_tx_completed_queue(txring_txq(tx_ring),
868 total_packets, total_bytes);
869
870 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
871 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
872 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
873 /* Make sure that anybody stopping the queue after this
874 * sees the new next_to_clean.
875 */
876 smp_mb();
877 if (__netif_subqueue_stopped(tx_ring->netdev,
878 tx_ring->queue_index)
879 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
880 netif_wake_subqueue(tx_ring->netdev,
881 tx_ring->queue_index);
882 ++tx_ring->tx_stats.restart_queue;
883 }
884 }
885
886 return !!budget;
887 }
888
889 #ifdef CONFIG_IXGBE_DCA
890 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
891 struct ixgbe_ring *tx_ring,
892 int cpu)
893 {
894 struct ixgbe_hw *hw = &adapter->hw;
895 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
896 u16 reg_offset;
897
898 switch (hw->mac.type) {
899 case ixgbe_mac_82598EB:
900 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
901 break;
902 case ixgbe_mac_82599EB:
903 case ixgbe_mac_X540:
904 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
905 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
906 break;
907 default:
908 /* for unknown hardware do not write register */
909 return;
910 }
911
912 /*
913 * We can enable relaxed ordering for reads, but not writes when
914 * DCA is enabled. This is due to a known issue in some chipsets
915 * which will cause the DCA tag to be cleared.
916 */
917 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
918 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
919 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
920
921 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
922 }
923
924 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
925 struct ixgbe_ring *rx_ring,
926 int cpu)
927 {
928 struct ixgbe_hw *hw = &adapter->hw;
929 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
930 u8 reg_idx = rx_ring->reg_idx;
931
932
933 switch (hw->mac.type) {
934 case ixgbe_mac_82599EB:
935 case ixgbe_mac_X540:
936 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
937 break;
938 default:
939 break;
940 }
941
942 /*
943 * We can enable relaxed ordering for reads, but not writes when
944 * DCA is enabled. This is due to a known issue in some chipsets
945 * which will cause the DCA tag to be cleared.
946 */
947 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
948 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
949 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
950
951 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
952 }
953
954 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
955 {
956 struct ixgbe_adapter *adapter = q_vector->adapter;
957 struct ixgbe_ring *ring;
958 int cpu = get_cpu();
959
960 if (q_vector->cpu == cpu)
961 goto out_no_update;
962
963 ixgbe_for_each_ring(ring, q_vector->tx)
964 ixgbe_update_tx_dca(adapter, ring, cpu);
965
966 ixgbe_for_each_ring(ring, q_vector->rx)
967 ixgbe_update_rx_dca(adapter, ring, cpu);
968
969 q_vector->cpu = cpu;
970 out_no_update:
971 put_cpu();
972 }
973
974 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
975 {
976 int num_q_vectors;
977 int i;
978
979 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
980 return;
981
982 /* always use CB2 mode, difference is masked in the CB driver */
983 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
984
985 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
986 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
987 else
988 num_q_vectors = 1;
989
990 for (i = 0; i < num_q_vectors; i++) {
991 adapter->q_vector[i]->cpu = -1;
992 ixgbe_update_dca(adapter->q_vector[i]);
993 }
994 }
995
996 static int __ixgbe_notify_dca(struct device *dev, void *data)
997 {
998 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
999 unsigned long event = *(unsigned long *)data;
1000
1001 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1002 return 0;
1003
1004 switch (event) {
1005 case DCA_PROVIDER_ADD:
1006 /* if we're already enabled, don't do it again */
1007 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1008 break;
1009 if (dca_add_requester(dev) == 0) {
1010 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1011 ixgbe_setup_dca(adapter);
1012 break;
1013 }
1014 /* Fall Through since DCA is disabled. */
1015 case DCA_PROVIDER_REMOVE:
1016 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1017 dca_remove_requester(dev);
1018 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1019 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1020 }
1021 break;
1022 }
1023
1024 return 0;
1025 }
1026
1027 #endif /* CONFIG_IXGBE_DCA */
1028 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1029 union ixgbe_adv_rx_desc *rx_desc,
1030 struct sk_buff *skb)
1031 {
1032 if (ring->netdev->features & NETIF_F_RXHASH)
1033 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1034 }
1035
1036 #ifdef IXGBE_FCOE
1037 /**
1038 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1039 * @adapter: address of board private structure
1040 * @rx_desc: advanced rx descriptor
1041 *
1042 * Returns : true if it is FCoE pkt
1043 */
1044 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1045 union ixgbe_adv_rx_desc *rx_desc)
1046 {
1047 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1048
1049 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1050 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1051 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1052 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1053 }
1054
1055 #endif /* IXGBE_FCOE */
1056 /**
1057 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1058 * @ring: structure containing ring specific data
1059 * @rx_desc: current Rx descriptor being processed
1060 * @skb: skb currently being received and modified
1061 **/
1062 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1063 union ixgbe_adv_rx_desc *rx_desc,
1064 struct sk_buff *skb)
1065 {
1066 skb_checksum_none_assert(skb);
1067
1068 /* Rx csum disabled */
1069 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1070 return;
1071
1072 /* if IP and error */
1073 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1074 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1075 ring->rx_stats.csum_err++;
1076 return;
1077 }
1078
1079 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1080 return;
1081
1082 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1083 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1084
1085 /*
1086 * 82599 errata, UDP frames with a 0 checksum can be marked as
1087 * checksum errors.
1088 */
1089 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1090 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1091 return;
1092
1093 ring->rx_stats.csum_err++;
1094 return;
1095 }
1096
1097 /* It must be a TCP or UDP packet with a valid checksum */
1098 skb->ip_summed = CHECKSUM_UNNECESSARY;
1099 }
1100
1101 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1102 {
1103 rx_ring->next_to_use = val;
1104
1105 /* update next to alloc since we have filled the ring */
1106 rx_ring->next_to_alloc = val;
1107 /*
1108 * Force memory writes to complete before letting h/w
1109 * know there are new descriptors to fetch. (Only
1110 * applicable for weak-ordered memory model archs,
1111 * such as IA-64).
1112 */
1113 wmb();
1114 writel(val, rx_ring->tail);
1115 }
1116
1117 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1118 struct ixgbe_rx_buffer *bi)
1119 {
1120 struct page *page = bi->page;
1121 dma_addr_t dma = bi->dma;
1122
1123 /* since we are recycling buffers we should seldom need to alloc */
1124 if (likely(dma))
1125 return true;
1126
1127 /* alloc new page for storage */
1128 if (likely(!page)) {
1129 page = alloc_pages(GFP_ATOMIC | __GFP_COLD,
1130 ixgbe_rx_pg_order(rx_ring));
1131 if (unlikely(!page)) {
1132 rx_ring->rx_stats.alloc_rx_page_failed++;
1133 return false;
1134 }
1135 bi->page = page;
1136 }
1137
1138 /* map page for use */
1139 dma = dma_map_page(rx_ring->dev, page, 0,
1140 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1141
1142 /*
1143 * if mapping failed free memory back to system since
1144 * there isn't much point in holding memory we can't use
1145 */
1146 if (dma_mapping_error(rx_ring->dev, dma)) {
1147 put_page(page);
1148 bi->page = NULL;
1149
1150 rx_ring->rx_stats.alloc_rx_page_failed++;
1151 return false;
1152 }
1153
1154 bi->dma = dma;
1155 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1156
1157 return true;
1158 }
1159
1160 /**
1161 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1162 * @rx_ring: ring to place buffers on
1163 * @cleaned_count: number of buffers to replace
1164 **/
1165 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1166 {
1167 union ixgbe_adv_rx_desc *rx_desc;
1168 struct ixgbe_rx_buffer *bi;
1169 u16 i = rx_ring->next_to_use;
1170
1171 /* nothing to do */
1172 if (!cleaned_count)
1173 return;
1174
1175 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1176 bi = &rx_ring->rx_buffer_info[i];
1177 i -= rx_ring->count;
1178
1179 do {
1180 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1181 break;
1182
1183 /*
1184 * Refresh the desc even if buffer_addrs didn't change
1185 * because each write-back erases this info.
1186 */
1187 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1188
1189 rx_desc++;
1190 bi++;
1191 i++;
1192 if (unlikely(!i)) {
1193 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1194 bi = rx_ring->rx_buffer_info;
1195 i -= rx_ring->count;
1196 }
1197
1198 /* clear the hdr_addr for the next_to_use descriptor */
1199 rx_desc->read.hdr_addr = 0;
1200
1201 cleaned_count--;
1202 } while (cleaned_count);
1203
1204 i += rx_ring->count;
1205
1206 if (rx_ring->next_to_use != i)
1207 ixgbe_release_rx_desc(rx_ring, i);
1208 }
1209
1210 /**
1211 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1212 * @data: pointer to the start of the headers
1213 * @max_len: total length of section to find headers in
1214 *
1215 * This function is meant to determine the length of headers that will
1216 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1217 * motivation of doing this is to only perform one pull for IPv4 TCP
1218 * packets so that we can do basic things like calculating the gso_size
1219 * based on the average data per packet.
1220 **/
1221 static unsigned int ixgbe_get_headlen(unsigned char *data,
1222 unsigned int max_len)
1223 {
1224 union {
1225 unsigned char *network;
1226 /* l2 headers */
1227 struct ethhdr *eth;
1228 struct vlan_hdr *vlan;
1229 /* l3 headers */
1230 struct iphdr *ipv4;
1231 } hdr;
1232 __be16 protocol;
1233 u8 nexthdr = 0; /* default to not TCP */
1234 u8 hlen;
1235
1236 /* this should never happen, but better safe than sorry */
1237 if (max_len < ETH_HLEN)
1238 return max_len;
1239
1240 /* initialize network frame pointer */
1241 hdr.network = data;
1242
1243 /* set first protocol and move network header forward */
1244 protocol = hdr.eth->h_proto;
1245 hdr.network += ETH_HLEN;
1246
1247 /* handle any vlan tag if present */
1248 if (protocol == __constant_htons(ETH_P_8021Q)) {
1249 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1250 return max_len;
1251
1252 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1253 hdr.network += VLAN_HLEN;
1254 }
1255
1256 /* handle L3 protocols */
1257 if (protocol == __constant_htons(ETH_P_IP)) {
1258 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1259 return max_len;
1260
1261 /* access ihl as a u8 to avoid unaligned access on ia64 */
1262 hlen = (hdr.network[0] & 0x0F) << 2;
1263
1264 /* verify hlen meets minimum size requirements */
1265 if (hlen < sizeof(struct iphdr))
1266 return hdr.network - data;
1267
1268 /* record next protocol */
1269 nexthdr = hdr.ipv4->protocol;
1270 hdr.network += hlen;
1271 #ifdef IXGBE_FCOE
1272 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1273 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1274 return max_len;
1275 hdr.network += FCOE_HEADER_LEN;
1276 #endif
1277 } else {
1278 return hdr.network - data;
1279 }
1280
1281 /* finally sort out TCP */
1282 if (nexthdr == IPPROTO_TCP) {
1283 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1284 return max_len;
1285
1286 /* access doff as a u8 to avoid unaligned access on ia64 */
1287 hlen = (hdr.network[12] & 0xF0) >> 2;
1288
1289 /* verify hlen meets minimum size requirements */
1290 if (hlen < sizeof(struct tcphdr))
1291 return hdr.network - data;
1292
1293 hdr.network += hlen;
1294 }
1295
1296 /*
1297 * If everything has gone correctly hdr.network should be the
1298 * data section of the packet and will be the end of the header.
1299 * If not then it probably represents the end of the last recognized
1300 * header.
1301 */
1302 if ((hdr.network - data) < max_len)
1303 return hdr.network - data;
1304 else
1305 return max_len;
1306 }
1307
1308 static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1309 union ixgbe_adv_rx_desc *rx_desc,
1310 struct sk_buff *skb)
1311 {
1312 __le32 rsc_enabled;
1313 u32 rsc_cnt;
1314
1315 if (!ring_is_rsc_enabled(rx_ring))
1316 return;
1317
1318 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1319 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1320
1321 /* If this is an RSC frame rsc_cnt should be non-zero */
1322 if (!rsc_enabled)
1323 return;
1324
1325 rsc_cnt = le32_to_cpu(rsc_enabled);
1326 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1327
1328 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1329 }
1330
1331 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1332 struct sk_buff *skb)
1333 {
1334 u16 hdr_len = skb_headlen(skb);
1335
1336 /* set gso_size to avoid messing up TCP MSS */
1337 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1338 IXGBE_CB(skb)->append_cnt);
1339 }
1340
1341 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1342 struct sk_buff *skb)
1343 {
1344 /* if append_cnt is 0 then frame is not RSC */
1345 if (!IXGBE_CB(skb)->append_cnt)
1346 return;
1347
1348 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1349 rx_ring->rx_stats.rsc_flush++;
1350
1351 ixgbe_set_rsc_gso_size(rx_ring, skb);
1352
1353 /* gso_size is computed using append_cnt so always clear it last */
1354 IXGBE_CB(skb)->append_cnt = 0;
1355 }
1356
1357 /**
1358 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1359 * @rx_ring: rx descriptor ring packet is being transacted on
1360 * @rx_desc: pointer to the EOP Rx descriptor
1361 * @skb: pointer to current skb being populated
1362 *
1363 * This function checks the ring, descriptor, and packet information in
1364 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1365 * other fields within the skb.
1366 **/
1367 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1368 union ixgbe_adv_rx_desc *rx_desc,
1369 struct sk_buff *skb)
1370 {
1371 ixgbe_update_rsc_stats(rx_ring, skb);
1372
1373 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1374
1375 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1376
1377 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1378 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1379 __vlan_hwaccel_put_tag(skb, vid);
1380 }
1381
1382 skb_record_rx_queue(skb, rx_ring->queue_index);
1383
1384 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1385 }
1386
1387 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1388 struct sk_buff *skb)
1389 {
1390 struct ixgbe_adapter *adapter = q_vector->adapter;
1391
1392 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1393 napi_gro_receive(&q_vector->napi, skb);
1394 else
1395 netif_rx(skb);
1396 }
1397
1398 /**
1399 * ixgbe_is_non_eop - process handling of non-EOP buffers
1400 * @rx_ring: Rx ring being processed
1401 * @rx_desc: Rx descriptor for current buffer
1402 * @skb: Current socket buffer containing buffer in progress
1403 *
1404 * This function updates next to clean. If the buffer is an EOP buffer
1405 * this function exits returning false, otherwise it will place the
1406 * sk_buff in the next buffer to be chained and return true indicating
1407 * that this is in fact a non-EOP buffer.
1408 **/
1409 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1410 union ixgbe_adv_rx_desc *rx_desc,
1411 struct sk_buff *skb)
1412 {
1413 u32 ntc = rx_ring->next_to_clean + 1;
1414
1415 /* fetch, update, and store next to clean */
1416 ntc = (ntc < rx_ring->count) ? ntc : 0;
1417 rx_ring->next_to_clean = ntc;
1418
1419 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1420
1421 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1422 return false;
1423
1424 /* append_cnt indicates packet is RSC, if so fetch nextp */
1425 if (IXGBE_CB(skb)->append_cnt) {
1426 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1427 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1428 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1429 }
1430
1431 /* place skb in next buffer to be received */
1432 rx_ring->rx_buffer_info[ntc].skb = skb;
1433 rx_ring->rx_stats.non_eop_descs++;
1434
1435 return true;
1436 }
1437
1438 /**
1439 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1440 * @rx_ring: rx descriptor ring packet is being transacted on
1441 * @rx_desc: pointer to the EOP Rx descriptor
1442 * @skb: pointer to current skb being fixed
1443 *
1444 * Check for corrupted packet headers caused by senders on the local L2
1445 * embedded NIC switch not setting up their Tx Descriptors right. These
1446 * should be very rare.
1447 *
1448 * Also address the case where we are pulling data in on pages only
1449 * and as such no data is present in the skb header.
1450 *
1451 * In addition if skb is not at least 60 bytes we need to pad it so that
1452 * it is large enough to qualify as a valid Ethernet frame.
1453 *
1454 * Returns true if an error was encountered and skb was freed.
1455 **/
1456 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1457 union ixgbe_adv_rx_desc *rx_desc,
1458 struct sk_buff *skb)
1459 {
1460 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1461 struct net_device *netdev = rx_ring->netdev;
1462 unsigned char *va;
1463 unsigned int pull_len;
1464
1465 /* if the page was released unmap it, else just sync our portion */
1466 if (unlikely(IXGBE_CB(skb)->page_released)) {
1467 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1468 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1469 IXGBE_CB(skb)->page_released = false;
1470 } else {
1471 dma_sync_single_range_for_cpu(rx_ring->dev,
1472 IXGBE_CB(skb)->dma,
1473 frag->page_offset,
1474 ixgbe_rx_bufsz(rx_ring),
1475 DMA_FROM_DEVICE);
1476 }
1477 IXGBE_CB(skb)->dma = 0;
1478
1479 /* verify that the packet does not have any known errors */
1480 if (unlikely(ixgbe_test_staterr(rx_desc,
1481 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1482 !(netdev->features & NETIF_F_RXALL))) {
1483 dev_kfree_skb_any(skb);
1484 return true;
1485 }
1486
1487 /*
1488 * it is valid to use page_address instead of kmap since we are
1489 * working with pages allocated out of the lomem pool per
1490 * alloc_page(GFP_ATOMIC)
1491 */
1492 va = skb_frag_address(frag);
1493
1494 /*
1495 * we need the header to contain the greater of either ETH_HLEN or
1496 * 60 bytes if the skb->len is less than 60 for skb_pad.
1497 */
1498 pull_len = skb_frag_size(frag);
1499 if (pull_len > 256)
1500 pull_len = ixgbe_get_headlen(va, pull_len);
1501
1502 /* align pull length to size of long to optimize memcpy performance */
1503 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1504
1505 /* update all of the pointers */
1506 skb_frag_size_sub(frag, pull_len);
1507 frag->page_offset += pull_len;
1508 skb->data_len -= pull_len;
1509 skb->tail += pull_len;
1510
1511 /*
1512 * if we sucked the frag empty then we should free it,
1513 * if there are other frags here something is screwed up in hardware
1514 */
1515 if (skb_frag_size(frag) == 0) {
1516 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1517 skb_shinfo(skb)->nr_frags = 0;
1518 __skb_frag_unref(frag);
1519 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1520 }
1521
1522 /* if skb_pad returns an error the skb was freed */
1523 if (unlikely(skb->len < 60)) {
1524 int pad_len = 60 - skb->len;
1525
1526 if (skb_pad(skb, pad_len))
1527 return true;
1528 __skb_put(skb, pad_len);
1529 }
1530
1531 return false;
1532 }
1533
1534 /**
1535 * ixgbe_can_reuse_page - determine if we can reuse a page
1536 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1537 *
1538 * Returns true if page can be reused in another Rx buffer
1539 **/
1540 static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1541 {
1542 struct page *page = rx_buffer->page;
1543
1544 /* if we are only owner of page and it is local we can reuse it */
1545 return likely(page_count(page) == 1) &&
1546 likely(page_to_nid(page) == numa_node_id());
1547 }
1548
1549 /**
1550 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1551 * @rx_ring: rx descriptor ring to store buffers on
1552 * @old_buff: donor buffer to have page reused
1553 *
1554 * Syncronizes page for reuse by the adapter
1555 **/
1556 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1557 struct ixgbe_rx_buffer *old_buff)
1558 {
1559 struct ixgbe_rx_buffer *new_buff;
1560 u16 nta = rx_ring->next_to_alloc;
1561 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1562
1563 new_buff = &rx_ring->rx_buffer_info[nta];
1564
1565 /* update, and store next to alloc */
1566 nta++;
1567 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1568
1569 /* transfer page from old buffer to new buffer */
1570 new_buff->page = old_buff->page;
1571 new_buff->dma = old_buff->dma;
1572
1573 /* flip page offset to other buffer and store to new_buff */
1574 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1575
1576 /* sync the buffer for use by the device */
1577 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1578 new_buff->page_offset, bufsz,
1579 DMA_FROM_DEVICE);
1580
1581 /* bump ref count on page before it is given to the stack */
1582 get_page(new_buff->page);
1583 }
1584
1585 /**
1586 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1587 * @rx_ring: rx descriptor ring to transact packets on
1588 * @rx_buffer: buffer containing page to add
1589 * @rx_desc: descriptor containing length of buffer written by hardware
1590 * @skb: sk_buff to place the data into
1591 *
1592 * This function is based on skb_add_rx_frag. I would have used that
1593 * function however it doesn't handle the truesize case correctly since we
1594 * are allocating more memory than might be used for a single receive.
1595 **/
1596 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1597 struct ixgbe_rx_buffer *rx_buffer,
1598 struct sk_buff *skb, int size)
1599 {
1600 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1601 rx_buffer->page, rx_buffer->page_offset,
1602 size);
1603 skb->len += size;
1604 skb->data_len += size;
1605 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1606 }
1607
1608 /**
1609 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1610 * @q_vector: structure containing interrupt and ring information
1611 * @rx_ring: rx descriptor ring to transact packets on
1612 * @budget: Total limit on number of packets to process
1613 *
1614 * This function provides a "bounce buffer" approach to Rx interrupt
1615 * processing. The advantage to this is that on systems that have
1616 * expensive overhead for IOMMU access this provides a means of avoiding
1617 * it by maintaining the mapping of the page to the syste.
1618 *
1619 * Returns true if all work is completed without reaching budget
1620 **/
1621 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1622 struct ixgbe_ring *rx_ring,
1623 int budget)
1624 {
1625 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1626 #ifdef IXGBE_FCOE
1627 struct ixgbe_adapter *adapter = q_vector->adapter;
1628 int ddp_bytes = 0;
1629 #endif /* IXGBE_FCOE */
1630 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
1631
1632 do {
1633 struct ixgbe_rx_buffer *rx_buffer;
1634 union ixgbe_adv_rx_desc *rx_desc;
1635 struct sk_buff *skb;
1636 struct page *page;
1637 u16 ntc;
1638
1639 /* return some buffers to hardware, one at a time is too slow */
1640 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1641 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1642 cleaned_count = 0;
1643 }
1644
1645 ntc = rx_ring->next_to_clean;
1646 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1647 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1648
1649 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1650 break;
1651
1652 /*
1653 * This memory barrier is needed to keep us from reading
1654 * any other fields out of the rx_desc until we know the
1655 * RXD_STAT_DD bit is set
1656 */
1657 rmb();
1658
1659 page = rx_buffer->page;
1660 prefetchw(page);
1661
1662 skb = rx_buffer->skb;
1663
1664 if (likely(!skb)) {
1665 void *page_addr = page_address(page) +
1666 rx_buffer->page_offset;
1667
1668 /* prefetch first cache line of first page */
1669 prefetch(page_addr);
1670 #if L1_CACHE_BYTES < 128
1671 prefetch(page_addr + L1_CACHE_BYTES);
1672 #endif
1673
1674 /* allocate a skb to store the frags */
1675 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1676 IXGBE_RX_HDR_SIZE);
1677 if (unlikely(!skb)) {
1678 rx_ring->rx_stats.alloc_rx_buff_failed++;
1679 break;
1680 }
1681
1682 /*
1683 * we will be copying header into skb->data in
1684 * pskb_may_pull so it is in our interest to prefetch
1685 * it now to avoid a possible cache miss
1686 */
1687 prefetchw(skb->data);
1688
1689 /*
1690 * Delay unmapping of the first packet. It carries the
1691 * header information, HW may still access the header
1692 * after the writeback. Only unmap it when EOP is
1693 * reached
1694 */
1695 IXGBE_CB(skb)->dma = rx_buffer->dma;
1696 } else {
1697 /* we are reusing so sync this buffer for CPU use */
1698 dma_sync_single_range_for_cpu(rx_ring->dev,
1699 rx_buffer->dma,
1700 rx_buffer->page_offset,
1701 ixgbe_rx_bufsz(rx_ring),
1702 DMA_FROM_DEVICE);
1703 }
1704
1705 /* pull page into skb */
1706 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1707 le16_to_cpu(rx_desc->wb.upper.length));
1708
1709 if (ixgbe_can_reuse_page(rx_buffer)) {
1710 /* hand second half of page back to the ring */
1711 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1712 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1713 /* the page has been released from the ring */
1714 IXGBE_CB(skb)->page_released = true;
1715 } else {
1716 /* we are not reusing the buffer so unmap it */
1717 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1718 ixgbe_rx_pg_size(rx_ring),
1719 DMA_FROM_DEVICE);
1720 }
1721
1722 /* clear contents of buffer_info */
1723 rx_buffer->skb = NULL;
1724 rx_buffer->dma = 0;
1725 rx_buffer->page = NULL;
1726
1727 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1728
1729 cleaned_count++;
1730
1731 /* place incomplete frames back on ring for completion */
1732 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1733 continue;
1734
1735 /* verify the packet layout is correct */
1736 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1737 continue;
1738
1739 /* probably a little skewed due to removing CRC */
1740 total_rx_bytes += skb->len;
1741 total_rx_packets++;
1742
1743 /* populate checksum, timestamp, VLAN, and protocol */
1744 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1745
1746 #ifdef IXGBE_FCOE
1747 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1748 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1749 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1750 if (!ddp_bytes) {
1751 dev_kfree_skb_any(skb);
1752 continue;
1753 }
1754 }
1755
1756 #endif /* IXGBE_FCOE */
1757 ixgbe_rx_skb(q_vector, skb);
1758
1759 /* update budget accounting */
1760 budget--;
1761 } while (likely(budget));
1762
1763 #ifdef IXGBE_FCOE
1764 /* include DDPed FCoE data */
1765 if (ddp_bytes > 0) {
1766 unsigned int mss;
1767
1768 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1769 sizeof(struct fc_frame_header) -
1770 sizeof(struct fcoe_crc_eof);
1771 if (mss > 512)
1772 mss &= ~511;
1773 total_rx_bytes += ddp_bytes;
1774 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1775 }
1776
1777 #endif /* IXGBE_FCOE */
1778 u64_stats_update_begin(&rx_ring->syncp);
1779 rx_ring->stats.packets += total_rx_packets;
1780 rx_ring->stats.bytes += total_rx_bytes;
1781 u64_stats_update_end(&rx_ring->syncp);
1782 q_vector->rx.total_packets += total_rx_packets;
1783 q_vector->rx.total_bytes += total_rx_bytes;
1784
1785 if (cleaned_count)
1786 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1787
1788 return !!budget;
1789 }
1790
1791 /**
1792 * ixgbe_configure_msix - Configure MSI-X hardware
1793 * @adapter: board private structure
1794 *
1795 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1796 * interrupts.
1797 **/
1798 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1799 {
1800 struct ixgbe_q_vector *q_vector;
1801 int q_vectors, v_idx;
1802 u32 mask;
1803
1804 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1805
1806 /* Populate MSIX to EITR Select */
1807 if (adapter->num_vfs > 32) {
1808 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1809 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1810 }
1811
1812 /*
1813 * Populate the IVAR table and set the ITR values to the
1814 * corresponding register.
1815 */
1816 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1817 struct ixgbe_ring *ring;
1818 q_vector = adapter->q_vector[v_idx];
1819
1820 ixgbe_for_each_ring(ring, q_vector->rx)
1821 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1822
1823 ixgbe_for_each_ring(ring, q_vector->tx)
1824 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1825
1826 if (q_vector->tx.ring && !q_vector->rx.ring) {
1827 /* tx only vector */
1828 if (adapter->tx_itr_setting == 1)
1829 q_vector->itr = IXGBE_10K_ITR;
1830 else
1831 q_vector->itr = adapter->tx_itr_setting;
1832 } else {
1833 /* rx or rx/tx vector */
1834 if (adapter->rx_itr_setting == 1)
1835 q_vector->itr = IXGBE_20K_ITR;
1836 else
1837 q_vector->itr = adapter->rx_itr_setting;
1838 }
1839
1840 ixgbe_write_eitr(q_vector);
1841 }
1842
1843 switch (adapter->hw.mac.type) {
1844 case ixgbe_mac_82598EB:
1845 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1846 v_idx);
1847 break;
1848 case ixgbe_mac_82599EB:
1849 case ixgbe_mac_X540:
1850 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1851 break;
1852 default:
1853 break;
1854 }
1855 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1856
1857 /* set up to autoclear timer, and the vectors */
1858 mask = IXGBE_EIMS_ENABLE_MASK;
1859 mask &= ~(IXGBE_EIMS_OTHER |
1860 IXGBE_EIMS_MAILBOX |
1861 IXGBE_EIMS_LSC);
1862
1863 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1864 }
1865
1866 enum latency_range {
1867 lowest_latency = 0,
1868 low_latency = 1,
1869 bulk_latency = 2,
1870 latency_invalid = 255
1871 };
1872
1873 /**
1874 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1875 * @q_vector: structure containing interrupt and ring information
1876 * @ring_container: structure containing ring performance data
1877 *
1878 * Stores a new ITR value based on packets and byte
1879 * counts during the last interrupt. The advantage of per interrupt
1880 * computation is faster updates and more accurate ITR for the current
1881 * traffic pattern. Constants in this function were computed
1882 * based on theoretical maximum wire speed and thresholds were set based
1883 * on testing data as well as attempting to minimize response time
1884 * while increasing bulk throughput.
1885 * this functionality is controlled by the InterruptThrottleRate module
1886 * parameter (see ixgbe_param.c)
1887 **/
1888 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1889 struct ixgbe_ring_container *ring_container)
1890 {
1891 int bytes = ring_container->total_bytes;
1892 int packets = ring_container->total_packets;
1893 u32 timepassed_us;
1894 u64 bytes_perint;
1895 u8 itr_setting = ring_container->itr;
1896
1897 if (packets == 0)
1898 return;
1899
1900 /* simple throttlerate management
1901 * 0-10MB/s lowest (100000 ints/s)
1902 * 10-20MB/s low (20000 ints/s)
1903 * 20-1249MB/s bulk (8000 ints/s)
1904 */
1905 /* what was last interrupt timeslice? */
1906 timepassed_us = q_vector->itr >> 2;
1907 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1908
1909 switch (itr_setting) {
1910 case lowest_latency:
1911 if (bytes_perint > 10)
1912 itr_setting = low_latency;
1913 break;
1914 case low_latency:
1915 if (bytes_perint > 20)
1916 itr_setting = bulk_latency;
1917 else if (bytes_perint <= 10)
1918 itr_setting = lowest_latency;
1919 break;
1920 case bulk_latency:
1921 if (bytes_perint <= 20)
1922 itr_setting = low_latency;
1923 break;
1924 }
1925
1926 /* clear work counters since we have the values we need */
1927 ring_container->total_bytes = 0;
1928 ring_container->total_packets = 0;
1929
1930 /* write updated itr to ring container */
1931 ring_container->itr = itr_setting;
1932 }
1933
1934 /**
1935 * ixgbe_write_eitr - write EITR register in hardware specific way
1936 * @q_vector: structure containing interrupt and ring information
1937 *
1938 * This function is made to be called by ethtool and by the driver
1939 * when it needs to update EITR registers at runtime. Hardware
1940 * specific quirks/differences are taken care of here.
1941 */
1942 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1943 {
1944 struct ixgbe_adapter *adapter = q_vector->adapter;
1945 struct ixgbe_hw *hw = &adapter->hw;
1946 int v_idx = q_vector->v_idx;
1947 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
1948
1949 switch (adapter->hw.mac.type) {
1950 case ixgbe_mac_82598EB:
1951 /* must write high and low 16 bits to reset counter */
1952 itr_reg |= (itr_reg << 16);
1953 break;
1954 case ixgbe_mac_82599EB:
1955 case ixgbe_mac_X540:
1956 /*
1957 * set the WDIS bit to not clear the timer bits and cause an
1958 * immediate assertion of the interrupt
1959 */
1960 itr_reg |= IXGBE_EITR_CNT_WDIS;
1961 break;
1962 default:
1963 break;
1964 }
1965 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1966 }
1967
1968 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1969 {
1970 u32 new_itr = q_vector->itr;
1971 u8 current_itr;
1972
1973 ixgbe_update_itr(q_vector, &q_vector->tx);
1974 ixgbe_update_itr(q_vector, &q_vector->rx);
1975
1976 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1977
1978 switch (current_itr) {
1979 /* counts and packets in update_itr are dependent on these numbers */
1980 case lowest_latency:
1981 new_itr = IXGBE_100K_ITR;
1982 break;
1983 case low_latency:
1984 new_itr = IXGBE_20K_ITR;
1985 break;
1986 case bulk_latency:
1987 new_itr = IXGBE_8K_ITR;
1988 break;
1989 default:
1990 break;
1991 }
1992
1993 if (new_itr != q_vector->itr) {
1994 /* do an exponential smoothing */
1995 new_itr = (10 * new_itr * q_vector->itr) /
1996 ((9 * new_itr) + q_vector->itr);
1997
1998 /* save the algorithm value here */
1999 q_vector->itr = new_itr;
2000
2001 ixgbe_write_eitr(q_vector);
2002 }
2003 }
2004
2005 /**
2006 * ixgbe_check_overtemp_subtask - check for over temperature
2007 * @adapter: pointer to adapter
2008 **/
2009 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2010 {
2011 struct ixgbe_hw *hw = &adapter->hw;
2012 u32 eicr = adapter->interrupt_event;
2013
2014 if (test_bit(__IXGBE_DOWN, &adapter->state))
2015 return;
2016
2017 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2018 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2019 return;
2020
2021 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2022
2023 switch (hw->device_id) {
2024 case IXGBE_DEV_ID_82599_T3_LOM:
2025 /*
2026 * Since the warning interrupt is for both ports
2027 * we don't have to check if:
2028 * - This interrupt wasn't for our port.
2029 * - We may have missed the interrupt so always have to
2030 * check if we got a LSC
2031 */
2032 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2033 !(eicr & IXGBE_EICR_LSC))
2034 return;
2035
2036 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2037 u32 autoneg;
2038 bool link_up = false;
2039
2040 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2041
2042 if (link_up)
2043 return;
2044 }
2045
2046 /* Check if this is not due to overtemp */
2047 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2048 return;
2049
2050 break;
2051 default:
2052 if (!(eicr & IXGBE_EICR_GPI_SDP0))
2053 return;
2054 break;
2055 }
2056 e_crit(drv,
2057 "Network adapter has been stopped because it has over heated. "
2058 "Restart the computer. If the problem persists, "
2059 "power off the system and replace the adapter\n");
2060
2061 adapter->interrupt_event = 0;
2062 }
2063
2064 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2065 {
2066 struct ixgbe_hw *hw = &adapter->hw;
2067
2068 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2069 (eicr & IXGBE_EICR_GPI_SDP1)) {
2070 e_crit(probe, "Fan has stopped, replace the adapter\n");
2071 /* write to clear the interrupt */
2072 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2073 }
2074 }
2075
2076 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2077 {
2078 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2079 return;
2080
2081 switch (adapter->hw.mac.type) {
2082 case ixgbe_mac_82599EB:
2083 /*
2084 * Need to check link state so complete overtemp check
2085 * on service task
2086 */
2087 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2088 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2089 adapter->interrupt_event = eicr;
2090 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2091 ixgbe_service_event_schedule(adapter);
2092 return;
2093 }
2094 return;
2095 case ixgbe_mac_X540:
2096 if (!(eicr & IXGBE_EICR_TS))
2097 return;
2098 break;
2099 default:
2100 return;
2101 }
2102
2103 e_crit(drv,
2104 "Network adapter has been stopped because it has over heated. "
2105 "Restart the computer. If the problem persists, "
2106 "power off the system and replace the adapter\n");
2107 }
2108
2109 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2110 {
2111 struct ixgbe_hw *hw = &adapter->hw;
2112
2113 if (eicr & IXGBE_EICR_GPI_SDP2) {
2114 /* Clear the interrupt */
2115 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
2116 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2117 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2118 ixgbe_service_event_schedule(adapter);
2119 }
2120 }
2121
2122 if (eicr & IXGBE_EICR_GPI_SDP1) {
2123 /* Clear the interrupt */
2124 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2125 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2126 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2127 ixgbe_service_event_schedule(adapter);
2128 }
2129 }
2130 }
2131
2132 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2133 {
2134 struct ixgbe_hw *hw = &adapter->hw;
2135
2136 adapter->lsc_int++;
2137 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2138 adapter->link_check_timeout = jiffies;
2139 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2140 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2141 IXGBE_WRITE_FLUSH(hw);
2142 ixgbe_service_event_schedule(adapter);
2143 }
2144 }
2145
2146 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2147 u64 qmask)
2148 {
2149 u32 mask;
2150 struct ixgbe_hw *hw = &adapter->hw;
2151
2152 switch (hw->mac.type) {
2153 case ixgbe_mac_82598EB:
2154 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2155 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2156 break;
2157 case ixgbe_mac_82599EB:
2158 case ixgbe_mac_X540:
2159 mask = (qmask & 0xFFFFFFFF);
2160 if (mask)
2161 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2162 mask = (qmask >> 32);
2163 if (mask)
2164 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2165 break;
2166 default:
2167 break;
2168 }
2169 /* skip the flush */
2170 }
2171
2172 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2173 u64 qmask)
2174 {
2175 u32 mask;
2176 struct ixgbe_hw *hw = &adapter->hw;
2177
2178 switch (hw->mac.type) {
2179 case ixgbe_mac_82598EB:
2180 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2181 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2182 break;
2183 case ixgbe_mac_82599EB:
2184 case ixgbe_mac_X540:
2185 mask = (qmask & 0xFFFFFFFF);
2186 if (mask)
2187 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2188 mask = (qmask >> 32);
2189 if (mask)
2190 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2191 break;
2192 default:
2193 break;
2194 }
2195 /* skip the flush */
2196 }
2197
2198 /**
2199 * ixgbe_irq_enable - Enable default interrupt generation settings
2200 * @adapter: board private structure
2201 **/
2202 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2203 bool flush)
2204 {
2205 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2206
2207 /* don't reenable LSC while waiting for link */
2208 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2209 mask &= ~IXGBE_EIMS_LSC;
2210
2211 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2212 switch (adapter->hw.mac.type) {
2213 case ixgbe_mac_82599EB:
2214 mask |= IXGBE_EIMS_GPI_SDP0;
2215 break;
2216 case ixgbe_mac_X540:
2217 mask |= IXGBE_EIMS_TS;
2218 break;
2219 default:
2220 break;
2221 }
2222 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2223 mask |= IXGBE_EIMS_GPI_SDP1;
2224 switch (adapter->hw.mac.type) {
2225 case ixgbe_mac_82599EB:
2226 mask |= IXGBE_EIMS_GPI_SDP1;
2227 mask |= IXGBE_EIMS_GPI_SDP2;
2228 case ixgbe_mac_X540:
2229 mask |= IXGBE_EIMS_ECC;
2230 mask |= IXGBE_EIMS_MAILBOX;
2231 break;
2232 default:
2233 break;
2234 }
2235 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2236 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2237 mask |= IXGBE_EIMS_FLOW_DIR;
2238
2239 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2240 if (queues)
2241 ixgbe_irq_enable_queues(adapter, ~0);
2242 if (flush)
2243 IXGBE_WRITE_FLUSH(&adapter->hw);
2244 }
2245
2246 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2247 {
2248 struct ixgbe_adapter *adapter = data;
2249 struct ixgbe_hw *hw = &adapter->hw;
2250 u32 eicr;
2251
2252 /*
2253 * Workaround for Silicon errata. Use clear-by-write instead
2254 * of clear-by-read. Reading with EICS will return the
2255 * interrupt causes without clearing, which later be done
2256 * with the write to EICR.
2257 */
2258 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2259 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2260
2261 if (eicr & IXGBE_EICR_LSC)
2262 ixgbe_check_lsc(adapter);
2263
2264 if (eicr & IXGBE_EICR_MAILBOX)
2265 ixgbe_msg_task(adapter);
2266
2267 switch (hw->mac.type) {
2268 case ixgbe_mac_82599EB:
2269 case ixgbe_mac_X540:
2270 if (eicr & IXGBE_EICR_ECC)
2271 e_info(link, "Received unrecoverable ECC Err, please "
2272 "reboot\n");
2273 /* Handle Flow Director Full threshold interrupt */
2274 if (eicr & IXGBE_EICR_FLOW_DIR) {
2275 int reinit_count = 0;
2276 int i;
2277 for (i = 0; i < adapter->num_tx_queues; i++) {
2278 struct ixgbe_ring *ring = adapter->tx_ring[i];
2279 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2280 &ring->state))
2281 reinit_count++;
2282 }
2283 if (reinit_count) {
2284 /* no more flow director interrupts until after init */
2285 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2286 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2287 ixgbe_service_event_schedule(adapter);
2288 }
2289 }
2290 ixgbe_check_sfp_event(adapter, eicr);
2291 ixgbe_check_overtemp_event(adapter, eicr);
2292 break;
2293 default:
2294 break;
2295 }
2296
2297 ixgbe_check_fan_failure(adapter, eicr);
2298
2299 /* re-enable the original interrupt state, no lsc, no queues */
2300 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2301 ixgbe_irq_enable(adapter, false, false);
2302
2303 return IRQ_HANDLED;
2304 }
2305
2306 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2307 {
2308 struct ixgbe_q_vector *q_vector = data;
2309
2310 /* EIAM disabled interrupts (on this vector) for us */
2311
2312 if (q_vector->rx.ring || q_vector->tx.ring)
2313 napi_schedule(&q_vector->napi);
2314
2315 return IRQ_HANDLED;
2316 }
2317
2318 /**
2319 * ixgbe_poll - NAPI Rx polling callback
2320 * @napi: structure for representing this polling device
2321 * @budget: how many packets driver is allowed to clean
2322 *
2323 * This function is used for legacy and MSI, NAPI mode
2324 **/
2325 int ixgbe_poll(struct napi_struct *napi, int budget)
2326 {
2327 struct ixgbe_q_vector *q_vector =
2328 container_of(napi, struct ixgbe_q_vector, napi);
2329 struct ixgbe_adapter *adapter = q_vector->adapter;
2330 struct ixgbe_ring *ring;
2331 int per_ring_budget;
2332 bool clean_complete = true;
2333
2334 #ifdef CONFIG_IXGBE_DCA
2335 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2336 ixgbe_update_dca(q_vector);
2337 #endif
2338
2339 ixgbe_for_each_ring(ring, q_vector->tx)
2340 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2341
2342 /* attempt to distribute budget to each queue fairly, but don't allow
2343 * the budget to go below 1 because we'll exit polling */
2344 if (q_vector->rx.count > 1)
2345 per_ring_budget = max(budget/q_vector->rx.count, 1);
2346 else
2347 per_ring_budget = budget;
2348
2349 ixgbe_for_each_ring(ring, q_vector->rx)
2350 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2351 per_ring_budget);
2352
2353 /* If all work not completed, return budget and keep polling */
2354 if (!clean_complete)
2355 return budget;
2356
2357 /* all work done, exit the polling mode */
2358 napi_complete(napi);
2359 if (adapter->rx_itr_setting & 1)
2360 ixgbe_set_itr(q_vector);
2361 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2362 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2363
2364 return 0;
2365 }
2366
2367 /**
2368 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2369 * @adapter: board private structure
2370 *
2371 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2372 * interrupts from the kernel.
2373 **/
2374 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2375 {
2376 struct net_device *netdev = adapter->netdev;
2377 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2378 int vector, err;
2379 int ri = 0, ti = 0;
2380
2381 for (vector = 0; vector < q_vectors; vector++) {
2382 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2383 struct msix_entry *entry = &adapter->msix_entries[vector];
2384
2385 if (q_vector->tx.ring && q_vector->rx.ring) {
2386 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2387 "%s-%s-%d", netdev->name, "TxRx", ri++);
2388 ti++;
2389 } else if (q_vector->rx.ring) {
2390 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2391 "%s-%s-%d", netdev->name, "rx", ri++);
2392 } else if (q_vector->tx.ring) {
2393 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2394 "%s-%s-%d", netdev->name, "tx", ti++);
2395 } else {
2396 /* skip this unused q_vector */
2397 continue;
2398 }
2399 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2400 q_vector->name, q_vector);
2401 if (err) {
2402 e_err(probe, "request_irq failed for MSIX interrupt "
2403 "Error: %d\n", err);
2404 goto free_queue_irqs;
2405 }
2406 /* If Flow Director is enabled, set interrupt affinity */
2407 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2408 /* assign the mask for this irq */
2409 irq_set_affinity_hint(entry->vector,
2410 &q_vector->affinity_mask);
2411 }
2412 }
2413
2414 err = request_irq(adapter->msix_entries[vector].vector,
2415 ixgbe_msix_other, 0, netdev->name, adapter);
2416 if (err) {
2417 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2418 goto free_queue_irqs;
2419 }
2420
2421 return 0;
2422
2423 free_queue_irqs:
2424 while (vector) {
2425 vector--;
2426 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2427 NULL);
2428 free_irq(adapter->msix_entries[vector].vector,
2429 adapter->q_vector[vector]);
2430 }
2431 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2432 pci_disable_msix(adapter->pdev);
2433 kfree(adapter->msix_entries);
2434 adapter->msix_entries = NULL;
2435 return err;
2436 }
2437
2438 /**
2439 * ixgbe_intr - legacy mode Interrupt Handler
2440 * @irq: interrupt number
2441 * @data: pointer to a network interface device structure
2442 **/
2443 static irqreturn_t ixgbe_intr(int irq, void *data)
2444 {
2445 struct ixgbe_adapter *adapter = data;
2446 struct ixgbe_hw *hw = &adapter->hw;
2447 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2448 u32 eicr;
2449
2450 /*
2451 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2452 * before the read of EICR.
2453 */
2454 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2455
2456 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2457 * therefore no explicit interrupt disable is necessary */
2458 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2459 if (!eicr) {
2460 /*
2461 * shared interrupt alert!
2462 * make sure interrupts are enabled because the read will
2463 * have disabled interrupts due to EIAM
2464 * finish the workaround of silicon errata on 82598. Unmask
2465 * the interrupt that we masked before the EICR read.
2466 */
2467 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2468 ixgbe_irq_enable(adapter, true, true);
2469 return IRQ_NONE; /* Not our interrupt */
2470 }
2471
2472 if (eicr & IXGBE_EICR_LSC)
2473 ixgbe_check_lsc(adapter);
2474
2475 switch (hw->mac.type) {
2476 case ixgbe_mac_82599EB:
2477 ixgbe_check_sfp_event(adapter, eicr);
2478 /* Fall through */
2479 case ixgbe_mac_X540:
2480 if (eicr & IXGBE_EICR_ECC)
2481 e_info(link, "Received unrecoverable ECC err, please "
2482 "reboot\n");
2483 ixgbe_check_overtemp_event(adapter, eicr);
2484 break;
2485 default:
2486 break;
2487 }
2488
2489 ixgbe_check_fan_failure(adapter, eicr);
2490
2491 /* would disable interrupts here but EIAM disabled it */
2492 napi_schedule(&q_vector->napi);
2493
2494 /*
2495 * re-enable link(maybe) and non-queue interrupts, no flush.
2496 * ixgbe_poll will re-enable the queue interrupts
2497 */
2498 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2499 ixgbe_irq_enable(adapter, false, false);
2500
2501 return IRQ_HANDLED;
2502 }
2503
2504 /**
2505 * ixgbe_request_irq - initialize interrupts
2506 * @adapter: board private structure
2507 *
2508 * Attempts to configure interrupts using the best available
2509 * capabilities of the hardware and kernel.
2510 **/
2511 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2512 {
2513 struct net_device *netdev = adapter->netdev;
2514 int err;
2515
2516 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2517 err = ixgbe_request_msix_irqs(adapter);
2518 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2519 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2520 netdev->name, adapter);
2521 else
2522 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2523 netdev->name, adapter);
2524
2525 if (err)
2526 e_err(probe, "request_irq failed, Error %d\n", err);
2527
2528 return err;
2529 }
2530
2531 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2532 {
2533 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2534 int i, q_vectors;
2535
2536 q_vectors = adapter->num_msix_vectors;
2537 i = q_vectors - 1;
2538 free_irq(adapter->msix_entries[i].vector, adapter);
2539 i--;
2540
2541 for (; i >= 0; i--) {
2542 /* free only the irqs that were actually requested */
2543 if (!adapter->q_vector[i]->rx.ring &&
2544 !adapter->q_vector[i]->tx.ring)
2545 continue;
2546
2547 /* clear the affinity_mask in the IRQ descriptor */
2548 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2549 NULL);
2550
2551 free_irq(adapter->msix_entries[i].vector,
2552 adapter->q_vector[i]);
2553 }
2554 } else {
2555 free_irq(adapter->pdev->irq, adapter);
2556 }
2557 }
2558
2559 /**
2560 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2561 * @adapter: board private structure
2562 **/
2563 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2564 {
2565 switch (adapter->hw.mac.type) {
2566 case ixgbe_mac_82598EB:
2567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2568 break;
2569 case ixgbe_mac_82599EB:
2570 case ixgbe_mac_X540:
2571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2572 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2573 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2574 break;
2575 default:
2576 break;
2577 }
2578 IXGBE_WRITE_FLUSH(&adapter->hw);
2579 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2580 int i;
2581 for (i = 0; i < adapter->num_msix_vectors; i++)
2582 synchronize_irq(adapter->msix_entries[i].vector);
2583 } else {
2584 synchronize_irq(adapter->pdev->irq);
2585 }
2586 }
2587
2588 /**
2589 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2590 *
2591 **/
2592 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2593 {
2594 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2595
2596 /* rx/tx vector */
2597 if (adapter->rx_itr_setting == 1)
2598 q_vector->itr = IXGBE_20K_ITR;
2599 else
2600 q_vector->itr = adapter->rx_itr_setting;
2601
2602 ixgbe_write_eitr(q_vector);
2603
2604 ixgbe_set_ivar(adapter, 0, 0, 0);
2605 ixgbe_set_ivar(adapter, 1, 0, 0);
2606
2607 e_info(hw, "Legacy interrupt IVAR setup done\n");
2608 }
2609
2610 /**
2611 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2612 * @adapter: board private structure
2613 * @ring: structure containing ring specific data
2614 *
2615 * Configure the Tx descriptor ring after a reset.
2616 **/
2617 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2618 struct ixgbe_ring *ring)
2619 {
2620 struct ixgbe_hw *hw = &adapter->hw;
2621 u64 tdba = ring->dma;
2622 int wait_loop = 10;
2623 u32 txdctl = IXGBE_TXDCTL_ENABLE;
2624 u8 reg_idx = ring->reg_idx;
2625
2626 /* disable queue to avoid issues while updating state */
2627 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2628 IXGBE_WRITE_FLUSH(hw);
2629
2630 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2631 (tdba & DMA_BIT_MASK(32)));
2632 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2633 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2634 ring->count * sizeof(union ixgbe_adv_tx_desc));
2635 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2636 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2637 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2638
2639 /*
2640 * set WTHRESH to encourage burst writeback, it should not be set
2641 * higher than 1 when ITR is 0 as it could cause false TX hangs
2642 *
2643 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2644 * to or less than the number of on chip descriptors, which is
2645 * currently 40.
2646 */
2647 if (!ring->q_vector || (ring->q_vector->itr < 8))
2648 txdctl |= (1 << 16); /* WTHRESH = 1 */
2649 else
2650 txdctl |= (8 << 16); /* WTHRESH = 8 */
2651
2652 /*
2653 * Setting PTHRESH to 32 both improves performance
2654 * and avoids a TX hang with DFP enabled
2655 */
2656 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2657 32; /* PTHRESH = 32 */
2658
2659 /* reinitialize flowdirector state */
2660 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2661 adapter->atr_sample_rate) {
2662 ring->atr_sample_rate = adapter->atr_sample_rate;
2663 ring->atr_count = 0;
2664 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2665 } else {
2666 ring->atr_sample_rate = 0;
2667 }
2668
2669 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2670
2671 /* enable queue */
2672 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2673
2674 netdev_tx_reset_queue(txring_txq(ring));
2675
2676 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2677 if (hw->mac.type == ixgbe_mac_82598EB &&
2678 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2679 return;
2680
2681 /* poll to verify queue is enabled */
2682 do {
2683 usleep_range(1000, 2000);
2684 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2685 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2686 if (!wait_loop)
2687 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2688 }
2689
2690 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2691 {
2692 struct ixgbe_hw *hw = &adapter->hw;
2693 u32 rttdcs;
2694 u32 reg;
2695 u8 tcs = netdev_get_num_tc(adapter->netdev);
2696
2697 if (hw->mac.type == ixgbe_mac_82598EB)
2698 return;
2699
2700 /* disable the arbiter while setting MTQC */
2701 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2702 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2703 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2704
2705 /* set transmit pool layout */
2706 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2707 case (IXGBE_FLAG_SRIOV_ENABLED):
2708 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2709 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2710 break;
2711 default:
2712 if (!tcs)
2713 reg = IXGBE_MTQC_64Q_1PB;
2714 else if (tcs <= 4)
2715 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2716 else
2717 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2718
2719 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2720
2721 /* Enable Security TX Buffer IFG for multiple pb */
2722 if (tcs) {
2723 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2724 reg |= IXGBE_SECTX_DCB;
2725 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2726 }
2727 break;
2728 }
2729
2730 /* re-enable the arbiter */
2731 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2732 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2733 }
2734
2735 /**
2736 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2737 * @adapter: board private structure
2738 *
2739 * Configure the Tx unit of the MAC after a reset.
2740 **/
2741 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2742 {
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 u32 dmatxctl;
2745 u32 i;
2746
2747 ixgbe_setup_mtqc(adapter);
2748
2749 if (hw->mac.type != ixgbe_mac_82598EB) {
2750 /* DMATXCTL.EN must be before Tx queues are enabled */
2751 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2752 dmatxctl |= IXGBE_DMATXCTL_TE;
2753 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2754 }
2755
2756 /* Setup the HW Tx Head and Tail descriptor pointers */
2757 for (i = 0; i < adapter->num_tx_queues; i++)
2758 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2759 }
2760
2761 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2762
2763 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2764 struct ixgbe_ring *rx_ring)
2765 {
2766 u32 srrctl;
2767 u8 reg_idx = rx_ring->reg_idx;
2768
2769 switch (adapter->hw.mac.type) {
2770 case ixgbe_mac_82598EB: {
2771 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2772 const int mask = feature[RING_F_RSS].mask;
2773 reg_idx = reg_idx & mask;
2774 }
2775 break;
2776 case ixgbe_mac_82599EB:
2777 case ixgbe_mac_X540:
2778 default:
2779 break;
2780 }
2781
2782 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2783
2784 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2785 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2786 if (adapter->num_vfs)
2787 srrctl |= IXGBE_SRRCTL_DROP_EN;
2788
2789 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2790 IXGBE_SRRCTL_BSIZEHDR_MASK;
2791
2792 #if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2793 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2794 #else
2795 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2796 #endif
2797 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2798
2799 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2800 }
2801
2802 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2803 {
2804 struct ixgbe_hw *hw = &adapter->hw;
2805 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2806 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2807 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2808 u32 mrqc = 0, reta = 0;
2809 u32 rxcsum;
2810 int i, j;
2811 u8 tcs = netdev_get_num_tc(adapter->netdev);
2812 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2813
2814 if (tcs)
2815 maxq = min(maxq, adapter->num_tx_queues / tcs);
2816
2817 /* Fill out hash function seeds */
2818 for (i = 0; i < 10; i++)
2819 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2820
2821 /* Fill out redirection table */
2822 for (i = 0, j = 0; i < 128; i++, j++) {
2823 if (j == maxq)
2824 j = 0;
2825 /* reta = 4-byte sliding window of
2826 * 0x00..(indices-1)(indices-1)00..etc. */
2827 reta = (reta << 8) | (j * 0x11);
2828 if ((i & 3) == 3)
2829 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2830 }
2831
2832 /* Disable indicating checksum in descriptor, enables RSS hash */
2833 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2834 rxcsum |= IXGBE_RXCSUM_PCSD;
2835 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2836
2837 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2838 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2839 mrqc = IXGBE_MRQC_RSSEN;
2840 } else {
2841 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2842 | IXGBE_FLAG_SRIOV_ENABLED);
2843
2844 switch (mask) {
2845 case (IXGBE_FLAG_RSS_ENABLED):
2846 if (!tcs)
2847 mrqc = IXGBE_MRQC_RSSEN;
2848 else if (tcs <= 4)
2849 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2850 else
2851 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2852 break;
2853 case (IXGBE_FLAG_SRIOV_ENABLED):
2854 mrqc = IXGBE_MRQC_VMDQEN;
2855 break;
2856 default:
2857 break;
2858 }
2859 }
2860
2861 /* Perform hash on these packet types */
2862 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2863 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2864 | IXGBE_MRQC_RSS_FIELD_IPV6
2865 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2866
2867 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2868 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2869 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2870 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2871
2872 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2873 }
2874
2875 /**
2876 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2877 * @adapter: address of board private structure
2878 * @index: index of ring to set
2879 **/
2880 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2881 struct ixgbe_ring *ring)
2882 {
2883 struct ixgbe_hw *hw = &adapter->hw;
2884 u32 rscctrl;
2885 u8 reg_idx = ring->reg_idx;
2886
2887 if (!ring_is_rsc_enabled(ring))
2888 return;
2889
2890 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2891 rscctrl |= IXGBE_RSCCTL_RSCEN;
2892 /*
2893 * we must limit the number of descriptors so that the
2894 * total size of max desc * buf_len is not greater
2895 * than 65536
2896 */
2897 #if (PAGE_SIZE <= 8192)
2898 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2899 #elif (PAGE_SIZE <= 16384)
2900 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2901 #else
2902 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2903 #endif
2904 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2905 }
2906
2907 /**
2908 * ixgbe_set_uta - Set unicast filter table address
2909 * @adapter: board private structure
2910 *
2911 * The unicast table address is a register array of 32-bit registers.
2912 * The table is meant to be used in a way similar to how the MTA is used
2913 * however due to certain limitations in the hardware it is necessary to
2914 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2915 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2916 **/
2917 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2918 {
2919 struct ixgbe_hw *hw = &adapter->hw;
2920 int i;
2921
2922 /* The UTA table only exists on 82599 hardware and newer */
2923 if (hw->mac.type < ixgbe_mac_82599EB)
2924 return;
2925
2926 /* we only need to do this if VMDq is enabled */
2927 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2928 return;
2929
2930 for (i = 0; i < 128; i++)
2931 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2932 }
2933
2934 #define IXGBE_MAX_RX_DESC_POLL 10
2935 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2936 struct ixgbe_ring *ring)
2937 {
2938 struct ixgbe_hw *hw = &adapter->hw;
2939 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2940 u32 rxdctl;
2941 u8 reg_idx = ring->reg_idx;
2942
2943 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2944 if (hw->mac.type == ixgbe_mac_82598EB &&
2945 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2946 return;
2947
2948 do {
2949 usleep_range(1000, 2000);
2950 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2951 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2952
2953 if (!wait_loop) {
2954 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2955 "the polling period\n", reg_idx);
2956 }
2957 }
2958
2959 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2960 struct ixgbe_ring *ring)
2961 {
2962 struct ixgbe_hw *hw = &adapter->hw;
2963 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2964 u32 rxdctl;
2965 u8 reg_idx = ring->reg_idx;
2966
2967 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2968 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2969
2970 /* write value back with RXDCTL.ENABLE bit cleared */
2971 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2972
2973 if (hw->mac.type == ixgbe_mac_82598EB &&
2974 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2975 return;
2976
2977 /* the hardware may take up to 100us to really disable the rx queue */
2978 do {
2979 udelay(10);
2980 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2981 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2982
2983 if (!wait_loop) {
2984 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2985 "the polling period\n", reg_idx);
2986 }
2987 }
2988
2989 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2990 struct ixgbe_ring *ring)
2991 {
2992 struct ixgbe_hw *hw = &adapter->hw;
2993 u64 rdba = ring->dma;
2994 u32 rxdctl;
2995 u8 reg_idx = ring->reg_idx;
2996
2997 /* disable queue to avoid issues while updating state */
2998 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2999 ixgbe_disable_rx_queue(adapter, ring);
3000
3001 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3002 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3003 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3004 ring->count * sizeof(union ixgbe_adv_rx_desc));
3005 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3006 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3007 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3008
3009 ixgbe_configure_srrctl(adapter, ring);
3010 ixgbe_configure_rscctl(adapter, ring);
3011
3012 /* If operating in IOV mode set RLPML for X540 */
3013 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3014 hw->mac.type == ixgbe_mac_X540) {
3015 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3016 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3017 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3018 }
3019
3020 if (hw->mac.type == ixgbe_mac_82598EB) {
3021 /*
3022 * enable cache line friendly hardware writes:
3023 * PTHRESH=32 descriptors (half the internal cache),
3024 * this also removes ugly rx_no_buffer_count increment
3025 * HTHRESH=4 descriptors (to minimize latency on fetch)
3026 * WTHRESH=8 burst writeback up to two cache lines
3027 */
3028 rxdctl &= ~0x3FFFFF;
3029 rxdctl |= 0x080420;
3030 }
3031
3032 /* enable receive descriptor ring */
3033 rxdctl |= IXGBE_RXDCTL_ENABLE;
3034 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3035
3036 ixgbe_rx_desc_queue_enable(adapter, ring);
3037 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3038 }
3039
3040 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3041 {
3042 struct ixgbe_hw *hw = &adapter->hw;
3043 int p;
3044
3045 /* PSRTYPE must be initialized in non 82598 adapters */
3046 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3047 IXGBE_PSRTYPE_UDPHDR |
3048 IXGBE_PSRTYPE_IPV4HDR |
3049 IXGBE_PSRTYPE_L2HDR |
3050 IXGBE_PSRTYPE_IPV6HDR;
3051
3052 if (hw->mac.type == ixgbe_mac_82598EB)
3053 return;
3054
3055 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3056 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3057
3058 for (p = 0; p < adapter->num_rx_pools; p++)
3059 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3060 psrtype);
3061 }
3062
3063 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3064 {
3065 struct ixgbe_hw *hw = &adapter->hw;
3066 u32 gcr_ext;
3067 u32 vt_reg_bits;
3068 u32 reg_offset, vf_shift;
3069 u32 vmdctl;
3070 int i;
3071
3072 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3073 return;
3074
3075 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3076 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3077 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3078 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3079
3080 vf_shift = adapter->num_vfs % 32;
3081 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
3082
3083 /* Enable only the PF's pool for Tx/Rx */
3084 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3085 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3086 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3087 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3088 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3089
3090 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3091 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3092
3093 /*
3094 * Set up VF register offsets for selected VT Mode,
3095 * i.e. 32 or 64 VFs for SR-IOV
3096 */
3097 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3098 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3099 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3100 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3101
3102 /* enable Tx loopback for VF/PF communication */
3103 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3104 /* Enable MAC Anti-Spoofing */
3105 hw->mac.ops.set_mac_anti_spoofing(hw,
3106 (adapter->num_vfs != 0),
3107 adapter->num_vfs);
3108 /* For VFs that have spoof checking turned off */
3109 for (i = 0; i < adapter->num_vfs; i++) {
3110 if (!adapter->vfinfo[i].spoofchk_enabled)
3111 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3112 }
3113 }
3114
3115 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3116 {
3117 struct ixgbe_hw *hw = &adapter->hw;
3118 struct net_device *netdev = adapter->netdev;
3119 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3120 struct ixgbe_ring *rx_ring;
3121 int i;
3122 u32 mhadd, hlreg0;
3123
3124 #ifdef IXGBE_FCOE
3125 /* adjust max frame to be able to do baby jumbo for FCoE */
3126 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3127 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3128 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3129
3130 #endif /* IXGBE_FCOE */
3131 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3132 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3133 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3134 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3135
3136 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3137 }
3138
3139 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3140 max_frame += VLAN_HLEN;
3141
3142 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3143 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3144 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3145 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3146
3147 /*
3148 * Setup the HW Rx Head and Tail Descriptor Pointers and
3149 * the Base and Length of the Rx Descriptor Ring
3150 */
3151 for (i = 0; i < adapter->num_rx_queues; i++) {
3152 rx_ring = adapter->rx_ring[i];
3153 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3154 set_ring_rsc_enabled(rx_ring);
3155 else
3156 clear_ring_rsc_enabled(rx_ring);
3157 }
3158 }
3159
3160 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3161 {
3162 struct ixgbe_hw *hw = &adapter->hw;
3163 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3164
3165 switch (hw->mac.type) {
3166 case ixgbe_mac_82598EB:
3167 /*
3168 * For VMDq support of different descriptor types or
3169 * buffer sizes through the use of multiple SRRCTL
3170 * registers, RDRXCTL.MVMEN must be set to 1
3171 *
3172 * also, the manual doesn't mention it clearly but DCA hints
3173 * will only use queue 0's tags unless this bit is set. Side
3174 * effects of setting this bit are only that SRRCTL must be
3175 * fully programmed [0..15]
3176 */
3177 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3178 break;
3179 case ixgbe_mac_82599EB:
3180 case ixgbe_mac_X540:
3181 /* Disable RSC for ACK packets */
3182 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3183 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3184 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3185 /* hardware requires some bits to be set by default */
3186 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3187 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3188 break;
3189 default:
3190 /* We should do nothing since we don't know this hardware */
3191 return;
3192 }
3193
3194 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3195 }
3196
3197 /**
3198 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3199 * @adapter: board private structure
3200 *
3201 * Configure the Rx unit of the MAC after a reset.
3202 **/
3203 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3204 {
3205 struct ixgbe_hw *hw = &adapter->hw;
3206 int i;
3207 u32 rxctrl;
3208
3209 /* disable receives while setting up the descriptors */
3210 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3211 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3212
3213 ixgbe_setup_psrtype(adapter);
3214 ixgbe_setup_rdrxctl(adapter);
3215
3216 /* Program registers for the distribution of queues */
3217 ixgbe_setup_mrqc(adapter);
3218
3219 ixgbe_set_uta(adapter);
3220
3221 /* set_rx_buffer_len must be called before ring initialization */
3222 ixgbe_set_rx_buffer_len(adapter);
3223
3224 /*
3225 * Setup the HW Rx Head and Tail Descriptor Pointers and
3226 * the Base and Length of the Rx Descriptor Ring
3227 */
3228 for (i = 0; i < adapter->num_rx_queues; i++)
3229 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3230
3231 /* disable drop enable for 82598 parts */
3232 if (hw->mac.type == ixgbe_mac_82598EB)
3233 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3234
3235 /* enable all receives */
3236 rxctrl |= IXGBE_RXCTRL_RXEN;
3237 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3238 }
3239
3240 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3241 {
3242 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3243 struct ixgbe_hw *hw = &adapter->hw;
3244 int pool_ndx = adapter->num_vfs;
3245
3246 /* add VID to filter table */
3247 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3248 set_bit(vid, adapter->active_vlans);
3249
3250 return 0;
3251 }
3252
3253 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3254 {
3255 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3256 struct ixgbe_hw *hw = &adapter->hw;
3257 int pool_ndx = adapter->num_vfs;
3258
3259 /* remove VID from filter table */
3260 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3261 clear_bit(vid, adapter->active_vlans);
3262
3263 return 0;
3264 }
3265
3266 /**
3267 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3268 * @adapter: driver data
3269 */
3270 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3271 {
3272 struct ixgbe_hw *hw = &adapter->hw;
3273 u32 vlnctrl;
3274
3275 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3276 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3277 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3278 }
3279
3280 /**
3281 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3282 * @adapter: driver data
3283 */
3284 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3285 {
3286 struct ixgbe_hw *hw = &adapter->hw;
3287 u32 vlnctrl;
3288
3289 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3290 vlnctrl |= IXGBE_VLNCTRL_VFE;
3291 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3292 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3293 }
3294
3295 /**
3296 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3297 * @adapter: driver data
3298 */
3299 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3300 {
3301 struct ixgbe_hw *hw = &adapter->hw;
3302 u32 vlnctrl;
3303 int i, j;
3304
3305 switch (hw->mac.type) {
3306 case ixgbe_mac_82598EB:
3307 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3308 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3309 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3310 break;
3311 case ixgbe_mac_82599EB:
3312 case ixgbe_mac_X540:
3313 for (i = 0; i < adapter->num_rx_queues; i++) {
3314 j = adapter->rx_ring[i]->reg_idx;
3315 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3316 vlnctrl &= ~IXGBE_RXDCTL_VME;
3317 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3318 }
3319 break;
3320 default:
3321 break;
3322 }
3323 }
3324
3325 /**
3326 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3327 * @adapter: driver data
3328 */
3329 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3330 {
3331 struct ixgbe_hw *hw = &adapter->hw;
3332 u32 vlnctrl;
3333 int i, j;
3334
3335 switch (hw->mac.type) {
3336 case ixgbe_mac_82598EB:
3337 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3338 vlnctrl |= IXGBE_VLNCTRL_VME;
3339 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3340 break;
3341 case ixgbe_mac_82599EB:
3342 case ixgbe_mac_X540:
3343 for (i = 0; i < adapter->num_rx_queues; i++) {
3344 j = adapter->rx_ring[i]->reg_idx;
3345 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3346 vlnctrl |= IXGBE_RXDCTL_VME;
3347 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3348 }
3349 break;
3350 default:
3351 break;
3352 }
3353 }
3354
3355 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3356 {
3357 u16 vid;
3358
3359 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3360
3361 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3362 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3363 }
3364
3365 /**
3366 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3367 * @netdev: network interface device structure
3368 *
3369 * Writes unicast address list to the RAR table.
3370 * Returns: -ENOMEM on failure/insufficient address space
3371 * 0 on no addresses written
3372 * X on writing X addresses to the RAR table
3373 **/
3374 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3375 {
3376 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3377 struct ixgbe_hw *hw = &adapter->hw;
3378 unsigned int vfn = adapter->num_vfs;
3379 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3380 int count = 0;
3381
3382 /* return ENOMEM indicating insufficient memory for addresses */
3383 if (netdev_uc_count(netdev) > rar_entries)
3384 return -ENOMEM;
3385
3386 if (!netdev_uc_empty(netdev) && rar_entries) {
3387 struct netdev_hw_addr *ha;
3388 /* return error if we do not support writing to RAR table */
3389 if (!hw->mac.ops.set_rar)
3390 return -ENOMEM;
3391
3392 netdev_for_each_uc_addr(ha, netdev) {
3393 if (!rar_entries)
3394 break;
3395 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3396 vfn, IXGBE_RAH_AV);
3397 count++;
3398 }
3399 }
3400 /* write the addresses in reverse order to avoid write combining */
3401 for (; rar_entries > 0 ; rar_entries--)
3402 hw->mac.ops.clear_rar(hw, rar_entries);
3403
3404 return count;
3405 }
3406
3407 /**
3408 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3409 * @netdev: network interface device structure
3410 *
3411 * The set_rx_method entry point is called whenever the unicast/multicast
3412 * address list or the network interface flags are updated. This routine is
3413 * responsible for configuring the hardware for proper unicast, multicast and
3414 * promiscuous mode.
3415 **/
3416 void ixgbe_set_rx_mode(struct net_device *netdev)
3417 {
3418 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3419 struct ixgbe_hw *hw = &adapter->hw;
3420 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3421 int count;
3422
3423 /* Check for Promiscuous and All Multicast modes */
3424
3425 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3426
3427 /* set all bits that we expect to always be set */
3428 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
3429 fctrl |= IXGBE_FCTRL_BAM;
3430 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3431 fctrl |= IXGBE_FCTRL_PMCF;
3432
3433 /* clear the bits we are changing the status of */
3434 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3435
3436 if (netdev->flags & IFF_PROMISC) {
3437 hw->addr_ctrl.user_set_promisc = true;
3438 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3439 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3440 /* don't hardware filter vlans in promisc mode */
3441 ixgbe_vlan_filter_disable(adapter);
3442 } else {
3443 if (netdev->flags & IFF_ALLMULTI) {
3444 fctrl |= IXGBE_FCTRL_MPE;
3445 vmolr |= IXGBE_VMOLR_MPE;
3446 } else {
3447 /*
3448 * Write addresses to the MTA, if the attempt fails
3449 * then we should just turn on promiscuous mode so
3450 * that we can at least receive multicast traffic
3451 */
3452 hw->mac.ops.update_mc_addr_list(hw, netdev);
3453 vmolr |= IXGBE_VMOLR_ROMPE;
3454 }
3455 ixgbe_vlan_filter_enable(adapter);
3456 hw->addr_ctrl.user_set_promisc = false;
3457 /*
3458 * Write addresses to available RAR registers, if there is not
3459 * sufficient space to store all the addresses then enable
3460 * unicast promiscuous mode
3461 */
3462 count = ixgbe_write_uc_addr_list(netdev);
3463 if (count < 0) {
3464 fctrl |= IXGBE_FCTRL_UPE;
3465 vmolr |= IXGBE_VMOLR_ROPE;
3466 }
3467 }
3468
3469 if (adapter->num_vfs) {
3470 ixgbe_restore_vf_multicasts(adapter);
3471 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3472 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3473 IXGBE_VMOLR_ROPE);
3474 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3475 }
3476
3477 /* This is useful for sniffing bad packets. */
3478 if (adapter->netdev->features & NETIF_F_RXALL) {
3479 /* UPE and MPE will be handled by normal PROMISC logic
3480 * in e1000e_set_rx_mode */
3481 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3482 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3483 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3484
3485 fctrl &= ~(IXGBE_FCTRL_DPF);
3486 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3487 }
3488
3489 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3490
3491 if (netdev->features & NETIF_F_HW_VLAN_RX)
3492 ixgbe_vlan_strip_enable(adapter);
3493 else
3494 ixgbe_vlan_strip_disable(adapter);
3495 }
3496
3497 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3498 {
3499 int q_idx;
3500 struct ixgbe_q_vector *q_vector;
3501 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3502
3503 /* legacy and MSI only use one vector */
3504 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3505 q_vectors = 1;
3506
3507 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3508 q_vector = adapter->q_vector[q_idx];
3509 napi_enable(&q_vector->napi);
3510 }
3511 }
3512
3513 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3514 {
3515 int q_idx;
3516 struct ixgbe_q_vector *q_vector;
3517 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3518
3519 /* legacy and MSI only use one vector */
3520 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3521 q_vectors = 1;
3522
3523 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3524 q_vector = adapter->q_vector[q_idx];
3525 napi_disable(&q_vector->napi);
3526 }
3527 }
3528
3529 #ifdef CONFIG_IXGBE_DCB
3530 /*
3531 * ixgbe_configure_dcb - Configure DCB hardware
3532 * @adapter: ixgbe adapter struct
3533 *
3534 * This is called by the driver on open to configure the DCB hardware.
3535 * This is also called by the gennetlink interface when reconfiguring
3536 * the DCB state.
3537 */
3538 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3539 {
3540 struct ixgbe_hw *hw = &adapter->hw;
3541 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3542
3543 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3544 if (hw->mac.type == ixgbe_mac_82598EB)
3545 netif_set_gso_max_size(adapter->netdev, 65536);
3546 return;
3547 }
3548
3549 if (hw->mac.type == ixgbe_mac_82598EB)
3550 netif_set_gso_max_size(adapter->netdev, 32768);
3551
3552
3553 /* Enable VLAN tag insert/strip */
3554 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3555
3556 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3557
3558 #ifdef IXGBE_FCOE
3559 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3560 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3561 #endif
3562
3563 /* reconfigure the hardware */
3564 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3565 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3566 DCB_TX_CONFIG);
3567 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3568 DCB_RX_CONFIG);
3569 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3570 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3571 ixgbe_dcb_hw_ets(&adapter->hw,
3572 adapter->ixgbe_ieee_ets,
3573 max_frame);
3574 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3575 adapter->ixgbe_ieee_pfc->pfc_en,
3576 adapter->ixgbe_ieee_ets->prio_tc);
3577 }
3578
3579 /* Enable RSS Hash per TC */
3580 if (hw->mac.type != ixgbe_mac_82598EB) {
3581 int i;
3582 u32 reg = 0;
3583
3584 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3585 u8 msb = 0;
3586 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3587
3588 while (cnt >>= 1)
3589 msb++;
3590
3591 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3592 }
3593 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3594 }
3595 }
3596 #endif
3597
3598 /* Additional bittime to account for IXGBE framing */
3599 #define IXGBE_ETH_FRAMING 20
3600
3601 /*
3602 * ixgbe_hpbthresh - calculate high water mark for flow control
3603 *
3604 * @adapter: board private structure to calculate for
3605 * @pb - packet buffer to calculate
3606 */
3607 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3608 {
3609 struct ixgbe_hw *hw = &adapter->hw;
3610 struct net_device *dev = adapter->netdev;
3611 int link, tc, kb, marker;
3612 u32 dv_id, rx_pba;
3613
3614 /* Calculate max LAN frame size */
3615 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3616
3617 #ifdef IXGBE_FCOE
3618 /* FCoE traffic class uses FCOE jumbo frames */
3619 if (dev->features & NETIF_F_FCOE_MTU) {
3620 int fcoe_pb = 0;
3621
3622 #ifdef CONFIG_IXGBE_DCB
3623 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3624
3625 #endif
3626 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3627 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3628 }
3629 #endif
3630
3631 /* Calculate delay value for device */
3632 switch (hw->mac.type) {
3633 case ixgbe_mac_X540:
3634 dv_id = IXGBE_DV_X540(link, tc);
3635 break;
3636 default:
3637 dv_id = IXGBE_DV(link, tc);
3638 break;
3639 }
3640
3641 /* Loopback switch introduces additional latency */
3642 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3643 dv_id += IXGBE_B2BT(tc);
3644
3645 /* Delay value is calculated in bit times convert to KB */
3646 kb = IXGBE_BT2KB(dv_id);
3647 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3648
3649 marker = rx_pba - kb;
3650
3651 /* It is possible that the packet buffer is not large enough
3652 * to provide required headroom. In this case throw an error
3653 * to user and a do the best we can.
3654 */
3655 if (marker < 0) {
3656 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3657 "headroom to support flow control."
3658 "Decrease MTU or number of traffic classes\n", pb);
3659 marker = tc + 1;
3660 }
3661
3662 return marker;
3663 }
3664
3665 /*
3666 * ixgbe_lpbthresh - calculate low water mark for for flow control
3667 *
3668 * @adapter: board private structure to calculate for
3669 * @pb - packet buffer to calculate
3670 */
3671 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3672 {
3673 struct ixgbe_hw *hw = &adapter->hw;
3674 struct net_device *dev = adapter->netdev;
3675 int tc;
3676 u32 dv_id;
3677
3678 /* Calculate max LAN frame size */
3679 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3680
3681 /* Calculate delay value for device */
3682 switch (hw->mac.type) {
3683 case ixgbe_mac_X540:
3684 dv_id = IXGBE_LOW_DV_X540(tc);
3685 break;
3686 default:
3687 dv_id = IXGBE_LOW_DV(tc);
3688 break;
3689 }
3690
3691 /* Delay value is calculated in bit times convert to KB */
3692 return IXGBE_BT2KB(dv_id);
3693 }
3694
3695 /*
3696 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3697 */
3698 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3699 {
3700 struct ixgbe_hw *hw = &adapter->hw;
3701 int num_tc = netdev_get_num_tc(adapter->netdev);
3702 int i;
3703
3704 if (!num_tc)
3705 num_tc = 1;
3706
3707 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3708
3709 for (i = 0; i < num_tc; i++) {
3710 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3711
3712 /* Low water marks must not be larger than high water marks */
3713 if (hw->fc.low_water > hw->fc.high_water[i])
3714 hw->fc.low_water = 0;
3715 }
3716 }
3717
3718 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3719 {
3720 struct ixgbe_hw *hw = &adapter->hw;
3721 int hdrm;
3722 u8 tc = netdev_get_num_tc(adapter->netdev);
3723
3724 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3725 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3726 hdrm = 32 << adapter->fdir_pballoc;
3727 else
3728 hdrm = 0;
3729
3730 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
3731 ixgbe_pbthresh_setup(adapter);
3732 }
3733
3734 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3735 {
3736 struct ixgbe_hw *hw = &adapter->hw;
3737 struct hlist_node *node, *node2;
3738 struct ixgbe_fdir_filter *filter;
3739
3740 spin_lock(&adapter->fdir_perfect_lock);
3741
3742 if (!hlist_empty(&adapter->fdir_filter_list))
3743 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3744
3745 hlist_for_each_entry_safe(filter, node, node2,
3746 &adapter->fdir_filter_list, fdir_node) {
3747 ixgbe_fdir_write_perfect_filter_82599(hw,
3748 &filter->filter,
3749 filter->sw_idx,
3750 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3751 IXGBE_FDIR_DROP_QUEUE :
3752 adapter->rx_ring[filter->action]->reg_idx);
3753 }
3754
3755 spin_unlock(&adapter->fdir_perfect_lock);
3756 }
3757
3758 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3759 {
3760 struct ixgbe_hw *hw = &adapter->hw;
3761
3762 ixgbe_configure_pb(adapter);
3763 #ifdef CONFIG_IXGBE_DCB
3764 ixgbe_configure_dcb(adapter);
3765 #endif
3766
3767 ixgbe_set_rx_mode(adapter->netdev);
3768 ixgbe_restore_vlan(adapter);
3769
3770 #ifdef IXGBE_FCOE
3771 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3772 ixgbe_configure_fcoe(adapter);
3773
3774 #endif /* IXGBE_FCOE */
3775
3776 switch (hw->mac.type) {
3777 case ixgbe_mac_82599EB:
3778 case ixgbe_mac_X540:
3779 hw->mac.ops.disable_rx_buff(hw);
3780 break;
3781 default:
3782 break;
3783 }
3784
3785 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3786 ixgbe_init_fdir_signature_82599(&adapter->hw,
3787 adapter->fdir_pballoc);
3788 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3789 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3790 adapter->fdir_pballoc);
3791 ixgbe_fdir_filter_restore(adapter);
3792 }
3793
3794 switch (hw->mac.type) {
3795 case ixgbe_mac_82599EB:
3796 case ixgbe_mac_X540:
3797 hw->mac.ops.enable_rx_buff(hw);
3798 break;
3799 default:
3800 break;
3801 }
3802
3803 ixgbe_configure_virtualization(adapter);
3804
3805 ixgbe_configure_tx(adapter);
3806 ixgbe_configure_rx(adapter);
3807 }
3808
3809 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3810 {
3811 switch (hw->phy.type) {
3812 case ixgbe_phy_sfp_avago:
3813 case ixgbe_phy_sfp_ftl:
3814 case ixgbe_phy_sfp_intel:
3815 case ixgbe_phy_sfp_unknown:
3816 case ixgbe_phy_sfp_passive_tyco:
3817 case ixgbe_phy_sfp_passive_unknown:
3818 case ixgbe_phy_sfp_active_unknown:
3819 case ixgbe_phy_sfp_ftl_active:
3820 return true;
3821 case ixgbe_phy_nl:
3822 if (hw->mac.type == ixgbe_mac_82598EB)
3823 return true;
3824 default:
3825 return false;
3826 }
3827 }
3828
3829 /**
3830 * ixgbe_sfp_link_config - set up SFP+ link
3831 * @adapter: pointer to private adapter struct
3832 **/
3833 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3834 {
3835 /*
3836 * We are assuming the worst case scenario here, and that
3837 * is that an SFP was inserted/removed after the reset
3838 * but before SFP detection was enabled. As such the best
3839 * solution is to just start searching as soon as we start
3840 */
3841 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3842 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3843
3844 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3845 }
3846
3847 /**
3848 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3849 * @hw: pointer to private hardware struct
3850 *
3851 * Returns 0 on success, negative on failure
3852 **/
3853 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3854 {
3855 u32 autoneg;
3856 bool negotiation, link_up = false;
3857 u32 ret = IXGBE_ERR_LINK_SETUP;
3858
3859 if (hw->mac.ops.check_link)
3860 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3861
3862 if (ret)
3863 goto link_cfg_out;
3864
3865 autoneg = hw->phy.autoneg_advertised;
3866 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3867 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3868 &negotiation);
3869 if (ret)
3870 goto link_cfg_out;
3871
3872 if (hw->mac.ops.setup_link)
3873 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3874 link_cfg_out:
3875 return ret;
3876 }
3877
3878 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3879 {
3880 struct ixgbe_hw *hw = &adapter->hw;
3881 u32 gpie = 0;
3882
3883 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3884 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3885 IXGBE_GPIE_OCD;
3886 gpie |= IXGBE_GPIE_EIAME;
3887 /*
3888 * use EIAM to auto-mask when MSI-X interrupt is asserted
3889 * this saves a register write for every interrupt
3890 */
3891 switch (hw->mac.type) {
3892 case ixgbe_mac_82598EB:
3893 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3894 break;
3895 case ixgbe_mac_82599EB:
3896 case ixgbe_mac_X540:
3897 default:
3898 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3899 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3900 break;
3901 }
3902 } else {
3903 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3904 * specifically only auto mask tx and rx interrupts */
3905 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3906 }
3907
3908 /* XXX: to interrupt immediately for EICS writes, enable this */
3909 /* gpie |= IXGBE_GPIE_EIMEN; */
3910
3911 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3912 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3913 gpie |= IXGBE_GPIE_VTMODE_64;
3914 }
3915
3916 /* Enable Thermal over heat sensor interrupt */
3917 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3918 switch (adapter->hw.mac.type) {
3919 case ixgbe_mac_82599EB:
3920 gpie |= IXGBE_SDP0_GPIEN;
3921 break;
3922 case ixgbe_mac_X540:
3923 gpie |= IXGBE_EIMS_TS;
3924 break;
3925 default:
3926 break;
3927 }
3928 }
3929
3930 /* Enable fan failure interrupt */
3931 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3932 gpie |= IXGBE_SDP1_GPIEN;
3933
3934 if (hw->mac.type == ixgbe_mac_82599EB) {
3935 gpie |= IXGBE_SDP1_GPIEN;
3936 gpie |= IXGBE_SDP2_GPIEN;
3937 }
3938
3939 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3940 }
3941
3942 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
3943 {
3944 struct ixgbe_hw *hw = &adapter->hw;
3945 int err;
3946 u32 ctrl_ext;
3947
3948 ixgbe_get_hw_control(adapter);
3949 ixgbe_setup_gpie(adapter);
3950
3951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3952 ixgbe_configure_msix(adapter);
3953 else
3954 ixgbe_configure_msi_and_legacy(adapter);
3955
3956 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3957 if (hw->mac.ops.enable_tx_laser &&
3958 ((hw->phy.multispeed_fiber) ||
3959 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3960 (hw->mac.type == ixgbe_mac_82599EB))))
3961 hw->mac.ops.enable_tx_laser(hw);
3962
3963 clear_bit(__IXGBE_DOWN, &adapter->state);
3964 ixgbe_napi_enable_all(adapter);
3965
3966 if (ixgbe_is_sfp(hw)) {
3967 ixgbe_sfp_link_config(adapter);
3968 } else {
3969 err = ixgbe_non_sfp_link_config(hw);
3970 if (err)
3971 e_err(probe, "link_config FAILED %d\n", err);
3972 }
3973
3974 /* clear any pending interrupts, may auto mask */
3975 IXGBE_READ_REG(hw, IXGBE_EICR);
3976 ixgbe_irq_enable(adapter, true, true);
3977
3978 /*
3979 * If this adapter has a fan, check to see if we had a failure
3980 * before we enabled the interrupt.
3981 */
3982 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3983 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3984 if (esdp & IXGBE_ESDP_SDP1)
3985 e_crit(drv, "Fan has stopped, replace the adapter\n");
3986 }
3987
3988 /* enable transmits */
3989 netif_tx_start_all_queues(adapter->netdev);
3990
3991 /* bring the link up in the watchdog, this could race with our first
3992 * link up interrupt but shouldn't be a problem */
3993 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3994 adapter->link_check_timeout = jiffies;
3995 mod_timer(&adapter->service_timer, jiffies);
3996
3997 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3998 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3999 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4000 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
4001 }
4002
4003 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4004 {
4005 WARN_ON(in_interrupt());
4006 /* put off any impending NetWatchDogTimeout */
4007 adapter->netdev->trans_start = jiffies;
4008
4009 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4010 usleep_range(1000, 2000);
4011 ixgbe_down(adapter);
4012 /*
4013 * If SR-IOV enabled then wait a bit before bringing the adapter
4014 * back up to give the VFs time to respond to the reset. The
4015 * two second wait is based upon the watchdog timer cycle in
4016 * the VF driver.
4017 */
4018 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4019 msleep(2000);
4020 ixgbe_up(adapter);
4021 clear_bit(__IXGBE_RESETTING, &adapter->state);
4022 }
4023
4024 void ixgbe_up(struct ixgbe_adapter *adapter)
4025 {
4026 /* hardware has been reset, we need to reload some things */
4027 ixgbe_configure(adapter);
4028
4029 ixgbe_up_complete(adapter);
4030 }
4031
4032 void ixgbe_reset(struct ixgbe_adapter *adapter)
4033 {
4034 struct ixgbe_hw *hw = &adapter->hw;
4035 int err;
4036
4037 /* lock SFP init bit to prevent race conditions with the watchdog */
4038 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4039 usleep_range(1000, 2000);
4040
4041 /* clear all SFP and link config related flags while holding SFP_INIT */
4042 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4043 IXGBE_FLAG2_SFP_NEEDS_RESET);
4044 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4045
4046 err = hw->mac.ops.init_hw(hw);
4047 switch (err) {
4048 case 0:
4049 case IXGBE_ERR_SFP_NOT_PRESENT:
4050 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4051 break;
4052 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4053 e_dev_err("master disable timed out\n");
4054 break;
4055 case IXGBE_ERR_EEPROM_VERSION:
4056 /* We are running on a pre-production device, log a warning */
4057 e_dev_warn("This device is a pre-production adapter/LOM. "
4058 "Please be aware there may be issues associated with "
4059 "your hardware. If you are experiencing problems "
4060 "please contact your Intel or hardware "
4061 "representative who provided you with this "
4062 "hardware.\n");
4063 break;
4064 default:
4065 e_dev_err("Hardware Error: %d\n", err);
4066 }
4067
4068 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4069
4070 /* reprogram the RAR[0] in case user changed it. */
4071 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4072 IXGBE_RAH_AV);
4073 }
4074
4075 /**
4076 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4077 * @rx_ring: ring to setup
4078 *
4079 * On many IA platforms the L1 cache has a critical stride of 4K, this
4080 * results in each receive buffer starting in the same cache set. To help
4081 * reduce the pressure on this cache set we can interleave the offsets so
4082 * that only every other buffer will be in the same cache set.
4083 **/
4084 static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4085 {
4086 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4087 u16 i;
4088
4089 for (i = 0; i < rx_ring->count; i += 2) {
4090 rx_buffer[0].page_offset = 0;
4091 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4092 rx_buffer = &rx_buffer[2];
4093 }
4094 }
4095
4096 /**
4097 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4098 * @rx_ring: ring to free buffers from
4099 **/
4100 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4101 {
4102 struct device *dev = rx_ring->dev;
4103 unsigned long size;
4104 u16 i;
4105
4106 /* ring already cleared, nothing to do */
4107 if (!rx_ring->rx_buffer_info)
4108 return;
4109
4110 /* Free all the Rx ring sk_buffs */
4111 for (i = 0; i < rx_ring->count; i++) {
4112 struct ixgbe_rx_buffer *rx_buffer;
4113
4114 rx_buffer = &rx_ring->rx_buffer_info[i];
4115 if (rx_buffer->skb) {
4116 struct sk_buff *skb = rx_buffer->skb;
4117 if (IXGBE_CB(skb)->page_released) {
4118 dma_unmap_page(dev,
4119 IXGBE_CB(skb)->dma,
4120 ixgbe_rx_bufsz(rx_ring),
4121 DMA_FROM_DEVICE);
4122 IXGBE_CB(skb)->page_released = false;
4123 }
4124 dev_kfree_skb(skb);
4125 }
4126 rx_buffer->skb = NULL;
4127 if (rx_buffer->dma)
4128 dma_unmap_page(dev, rx_buffer->dma,
4129 ixgbe_rx_pg_size(rx_ring),
4130 DMA_FROM_DEVICE);
4131 rx_buffer->dma = 0;
4132 if (rx_buffer->page)
4133 put_page(rx_buffer->page);
4134 rx_buffer->page = NULL;
4135 }
4136
4137 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4138 memset(rx_ring->rx_buffer_info, 0, size);
4139
4140 ixgbe_init_rx_page_offset(rx_ring);
4141
4142 /* Zero out the descriptor ring */
4143 memset(rx_ring->desc, 0, rx_ring->size);
4144
4145 rx_ring->next_to_alloc = 0;
4146 rx_ring->next_to_clean = 0;
4147 rx_ring->next_to_use = 0;
4148 }
4149
4150 /**
4151 * ixgbe_clean_tx_ring - Free Tx Buffers
4152 * @tx_ring: ring to be cleaned
4153 **/
4154 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4155 {
4156 struct ixgbe_tx_buffer *tx_buffer_info;
4157 unsigned long size;
4158 u16 i;
4159
4160 /* ring already cleared, nothing to do */
4161 if (!tx_ring->tx_buffer_info)
4162 return;
4163
4164 /* Free all the Tx ring sk_buffs */
4165 for (i = 0; i < tx_ring->count; i++) {
4166 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4167 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4168 }
4169
4170 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4171 memset(tx_ring->tx_buffer_info, 0, size);
4172
4173 /* Zero out the descriptor ring */
4174 memset(tx_ring->desc, 0, tx_ring->size);
4175
4176 tx_ring->next_to_use = 0;
4177 tx_ring->next_to_clean = 0;
4178 }
4179
4180 /**
4181 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4182 * @adapter: board private structure
4183 **/
4184 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4185 {
4186 int i;
4187
4188 for (i = 0; i < adapter->num_rx_queues; i++)
4189 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4190 }
4191
4192 /**
4193 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4194 * @adapter: board private structure
4195 **/
4196 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4197 {
4198 int i;
4199
4200 for (i = 0; i < adapter->num_tx_queues; i++)
4201 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4202 }
4203
4204 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4205 {
4206 struct hlist_node *node, *node2;
4207 struct ixgbe_fdir_filter *filter;
4208
4209 spin_lock(&adapter->fdir_perfect_lock);
4210
4211 hlist_for_each_entry_safe(filter, node, node2,
4212 &adapter->fdir_filter_list, fdir_node) {
4213 hlist_del(&filter->fdir_node);
4214 kfree(filter);
4215 }
4216 adapter->fdir_filter_count = 0;
4217
4218 spin_unlock(&adapter->fdir_perfect_lock);
4219 }
4220
4221 void ixgbe_down(struct ixgbe_adapter *adapter)
4222 {
4223 struct net_device *netdev = adapter->netdev;
4224 struct ixgbe_hw *hw = &adapter->hw;
4225 u32 rxctrl;
4226 int i;
4227
4228 /* signal that we are down to the interrupt handler */
4229 set_bit(__IXGBE_DOWN, &adapter->state);
4230
4231 /* disable receives */
4232 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4233 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4234
4235 /* disable all enabled rx queues */
4236 for (i = 0; i < adapter->num_rx_queues; i++)
4237 /* this call also flushes the previous write */
4238 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4239
4240 usleep_range(10000, 20000);
4241
4242 netif_tx_stop_all_queues(netdev);
4243
4244 /* call carrier off first to avoid false dev_watchdog timeouts */
4245 netif_carrier_off(netdev);
4246 netif_tx_disable(netdev);
4247
4248 ixgbe_irq_disable(adapter);
4249
4250 ixgbe_napi_disable_all(adapter);
4251
4252 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4253 IXGBE_FLAG2_RESET_REQUESTED);
4254 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4255
4256 del_timer_sync(&adapter->service_timer);
4257
4258 if (adapter->num_vfs) {
4259 /* Clear EITR Select mapping */
4260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
4261
4262 /* Mark all the VFs as inactive */
4263 for (i = 0 ; i < adapter->num_vfs; i++)
4264 adapter->vfinfo[i].clear_to_send = false;
4265
4266 /* ping all the active vfs to let them know we are going down */
4267 ixgbe_ping_all_vfs(adapter);
4268
4269 /* Disable all VFTE/VFRE TX/RX */
4270 ixgbe_disable_tx_rx(adapter);
4271 }
4272
4273 /* disable transmits in the hardware now that interrupts are off */
4274 for (i = 0; i < adapter->num_tx_queues; i++) {
4275 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4276 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4277 }
4278
4279 /* Disable the Tx DMA engine on 82599 and X540 */
4280 switch (hw->mac.type) {
4281 case ixgbe_mac_82599EB:
4282 case ixgbe_mac_X540:
4283 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4284 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4285 ~IXGBE_DMATXCTL_TE));
4286 break;
4287 default:
4288 break;
4289 }
4290
4291 if (!pci_channel_offline(adapter->pdev))
4292 ixgbe_reset(adapter);
4293
4294 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4295 if (hw->mac.ops.disable_tx_laser &&
4296 ((hw->phy.multispeed_fiber) ||
4297 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4298 (hw->mac.type == ixgbe_mac_82599EB))))
4299 hw->mac.ops.disable_tx_laser(hw);
4300
4301 ixgbe_clean_all_tx_rings(adapter);
4302 ixgbe_clean_all_rx_rings(adapter);
4303
4304 #ifdef CONFIG_IXGBE_DCA
4305 /* since we reset the hardware DCA settings were cleared */
4306 ixgbe_setup_dca(adapter);
4307 #endif
4308 }
4309
4310 /**
4311 * ixgbe_tx_timeout - Respond to a Tx Hang
4312 * @netdev: network interface device structure
4313 **/
4314 static void ixgbe_tx_timeout(struct net_device *netdev)
4315 {
4316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4317
4318 /* Do the reset outside of interrupt context */
4319 ixgbe_tx_timeout_reset(adapter);
4320 }
4321
4322 /**
4323 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4324 * @adapter: board private structure to initialize
4325 *
4326 * ixgbe_sw_init initializes the Adapter private data structure.
4327 * Fields are initialized based on PCI device information and
4328 * OS network device settings (MTU size).
4329 **/
4330 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4331 {
4332 struct ixgbe_hw *hw = &adapter->hw;
4333 struct pci_dev *pdev = adapter->pdev;
4334 unsigned int rss;
4335 #ifdef CONFIG_IXGBE_DCB
4336 int j;
4337 struct tc_configuration *tc;
4338 #endif
4339
4340 /* PCI config space info */
4341
4342 hw->vendor_id = pdev->vendor;
4343 hw->device_id = pdev->device;
4344 hw->revision_id = pdev->revision;
4345 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4346 hw->subsystem_device_id = pdev->subsystem_device;
4347
4348 /* Set capability flags */
4349 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
4350 adapter->ring_feature[RING_F_RSS].indices = rss;
4351 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4352 switch (hw->mac.type) {
4353 case ixgbe_mac_82598EB:
4354 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4355 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4356 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4357 break;
4358 case ixgbe_mac_X540:
4359 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4360 case ixgbe_mac_82599EB:
4361 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4362 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4363 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4364 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4365 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4366 /* Flow Director hash filters enabled */
4367 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4368 adapter->atr_sample_rate = 20;
4369 adapter->ring_feature[RING_F_FDIR].indices =
4370 IXGBE_MAX_FDIR_INDICES;
4371 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4372 #ifdef IXGBE_FCOE
4373 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4374 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4375 adapter->ring_feature[RING_F_FCOE].indices = 0;
4376 #ifdef CONFIG_IXGBE_DCB
4377 /* Default traffic class to use for FCoE */
4378 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4379 #endif
4380 #endif /* IXGBE_FCOE */
4381 break;
4382 default:
4383 break;
4384 }
4385
4386 /* n-tuple support exists, always init our spinlock */
4387 spin_lock_init(&adapter->fdir_perfect_lock);
4388
4389 #ifdef CONFIG_IXGBE_DCB
4390 switch (hw->mac.type) {
4391 case ixgbe_mac_X540:
4392 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4393 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4394 break;
4395 default:
4396 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4397 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4398 break;
4399 }
4400
4401 /* Configure DCB traffic classes */
4402 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4403 tc = &adapter->dcb_cfg.tc_config[j];
4404 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4405 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4406 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4407 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4408 tc->dcb_pfc = pfc_disabled;
4409 }
4410
4411 /* Initialize default user to priority mapping, UPx->TC0 */
4412 tc = &adapter->dcb_cfg.tc_config[0];
4413 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4414 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4415
4416 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4417 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4418 adapter->dcb_cfg.pfc_mode_enable = false;
4419 adapter->dcb_set_bitmap = 0x00;
4420 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
4421 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4422 MAX_TRAFFIC_CLASS);
4423
4424 #endif
4425
4426 /* default flow control settings */
4427 hw->fc.requested_mode = ixgbe_fc_full;
4428 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4429 #ifdef CONFIG_DCB
4430 adapter->last_lfc_mode = hw->fc.current_mode;
4431 #endif
4432 ixgbe_pbthresh_setup(adapter);
4433 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4434 hw->fc.send_xon = true;
4435 hw->fc.disable_fc_autoneg = false;
4436
4437 /* enable itr by default in dynamic mode */
4438 adapter->rx_itr_setting = 1;
4439 adapter->tx_itr_setting = 1;
4440
4441 /* set default ring sizes */
4442 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4443 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4444
4445 /* set default work limits */
4446 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
4447
4448 /* initialize eeprom parameters */
4449 if (ixgbe_init_eeprom_params_generic(hw)) {
4450 e_dev_err("EEPROM initialization failed\n");
4451 return -EIO;
4452 }
4453
4454 set_bit(__IXGBE_DOWN, &adapter->state);
4455
4456 return 0;
4457 }
4458
4459 /**
4460 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4461 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4462 *
4463 * Return 0 on success, negative on failure
4464 **/
4465 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4466 {
4467 struct device *dev = tx_ring->dev;
4468 int orig_node = dev_to_node(dev);
4469 int numa_node = -1;
4470 int size;
4471
4472 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4473
4474 if (tx_ring->q_vector)
4475 numa_node = tx_ring->q_vector->numa_node;
4476
4477 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
4478 if (!tx_ring->tx_buffer_info)
4479 tx_ring->tx_buffer_info = vzalloc(size);
4480 if (!tx_ring->tx_buffer_info)
4481 goto err;
4482
4483 /* round up to nearest 4K */
4484 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4485 tx_ring->size = ALIGN(tx_ring->size, 4096);
4486
4487 set_dev_node(dev, numa_node);
4488 tx_ring->desc = dma_alloc_coherent(dev,
4489 tx_ring->size,
4490 &tx_ring->dma,
4491 GFP_KERNEL);
4492 set_dev_node(dev, orig_node);
4493 if (!tx_ring->desc)
4494 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4495 &tx_ring->dma, GFP_KERNEL);
4496 if (!tx_ring->desc)
4497 goto err;
4498
4499 tx_ring->next_to_use = 0;
4500 tx_ring->next_to_clean = 0;
4501 return 0;
4502
4503 err:
4504 vfree(tx_ring->tx_buffer_info);
4505 tx_ring->tx_buffer_info = NULL;
4506 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4507 return -ENOMEM;
4508 }
4509
4510 /**
4511 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4512 * @adapter: board private structure
4513 *
4514 * If this function returns with an error, then it's possible one or
4515 * more of the rings is populated (while the rest are not). It is the
4516 * callers duty to clean those orphaned rings.
4517 *
4518 * Return 0 on success, negative on failure
4519 **/
4520 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4521 {
4522 int i, err = 0;
4523
4524 for (i = 0; i < adapter->num_tx_queues; i++) {
4525 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4526 if (!err)
4527 continue;
4528 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4529 break;
4530 }
4531
4532 return err;
4533 }
4534
4535 /**
4536 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4537 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4538 *
4539 * Returns 0 on success, negative on failure
4540 **/
4541 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
4542 {
4543 struct device *dev = rx_ring->dev;
4544 int orig_node = dev_to_node(dev);
4545 int numa_node = -1;
4546 int size;
4547
4548 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4549
4550 if (rx_ring->q_vector)
4551 numa_node = rx_ring->q_vector->numa_node;
4552
4553 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
4554 if (!rx_ring->rx_buffer_info)
4555 rx_ring->rx_buffer_info = vzalloc(size);
4556 if (!rx_ring->rx_buffer_info)
4557 goto err;
4558
4559 /* Round up to nearest 4K */
4560 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4561 rx_ring->size = ALIGN(rx_ring->size, 4096);
4562
4563 set_dev_node(dev, numa_node);
4564 rx_ring->desc = dma_alloc_coherent(dev,
4565 rx_ring->size,
4566 &rx_ring->dma,
4567 GFP_KERNEL);
4568 set_dev_node(dev, orig_node);
4569 if (!rx_ring->desc)
4570 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4571 &rx_ring->dma, GFP_KERNEL);
4572 if (!rx_ring->desc)
4573 goto err;
4574
4575 rx_ring->next_to_clean = 0;
4576 rx_ring->next_to_use = 0;
4577
4578 ixgbe_init_rx_page_offset(rx_ring);
4579
4580 return 0;
4581 err:
4582 vfree(rx_ring->rx_buffer_info);
4583 rx_ring->rx_buffer_info = NULL;
4584 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4585 return -ENOMEM;
4586 }
4587
4588 /**
4589 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4590 * @adapter: board private structure
4591 *
4592 * If this function returns with an error, then it's possible one or
4593 * more of the rings is populated (while the rest are not). It is the
4594 * callers duty to clean those orphaned rings.
4595 *
4596 * Return 0 on success, negative on failure
4597 **/
4598 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4599 {
4600 int i, err = 0;
4601
4602 for (i = 0; i < adapter->num_rx_queues; i++) {
4603 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
4604 if (!err)
4605 continue;
4606 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4607 break;
4608 }
4609
4610 return err;
4611 }
4612
4613 /**
4614 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4615 * @tx_ring: Tx descriptor ring for a specific queue
4616 *
4617 * Free all transmit software resources
4618 **/
4619 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
4620 {
4621 ixgbe_clean_tx_ring(tx_ring);
4622
4623 vfree(tx_ring->tx_buffer_info);
4624 tx_ring->tx_buffer_info = NULL;
4625
4626 /* if not set, then don't free */
4627 if (!tx_ring->desc)
4628 return;
4629
4630 dma_free_coherent(tx_ring->dev, tx_ring->size,
4631 tx_ring->desc, tx_ring->dma);
4632
4633 tx_ring->desc = NULL;
4634 }
4635
4636 /**
4637 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4638 * @adapter: board private structure
4639 *
4640 * Free all transmit software resources
4641 **/
4642 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4643 {
4644 int i;
4645
4646 for (i = 0; i < adapter->num_tx_queues; i++)
4647 if (adapter->tx_ring[i]->desc)
4648 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4649 }
4650
4651 /**
4652 * ixgbe_free_rx_resources - Free Rx Resources
4653 * @rx_ring: ring to clean the resources from
4654 *
4655 * Free all receive software resources
4656 **/
4657 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
4658 {
4659 ixgbe_clean_rx_ring(rx_ring);
4660
4661 vfree(rx_ring->rx_buffer_info);
4662 rx_ring->rx_buffer_info = NULL;
4663
4664 /* if not set, then don't free */
4665 if (!rx_ring->desc)
4666 return;
4667
4668 dma_free_coherent(rx_ring->dev, rx_ring->size,
4669 rx_ring->desc, rx_ring->dma);
4670
4671 rx_ring->desc = NULL;
4672 }
4673
4674 /**
4675 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4676 * @adapter: board private structure
4677 *
4678 * Free all receive software resources
4679 **/
4680 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4681 {
4682 int i;
4683
4684 for (i = 0; i < adapter->num_rx_queues; i++)
4685 if (adapter->rx_ring[i]->desc)
4686 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4687 }
4688
4689 /**
4690 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4691 * @netdev: network interface device structure
4692 * @new_mtu: new value for maximum frame size
4693 *
4694 * Returns 0 on success, negative on failure
4695 **/
4696 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4697 {
4698 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4699 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4700
4701 /* MTU < 68 is an error and causes problems on some kernels */
4702 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4703 return -EINVAL;
4704
4705 /*
4706 * For 82599EB we cannot allow PF to change MTU greater than 1500
4707 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4708 * don't allocate and chain buffers correctly.
4709 */
4710 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4711 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4712 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
4713 return -EINVAL;
4714
4715 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
4716
4717 /* must set new MTU before calling down or up */
4718 netdev->mtu = new_mtu;
4719
4720 if (netif_running(netdev))
4721 ixgbe_reinit_locked(adapter);
4722
4723 return 0;
4724 }
4725
4726 /**
4727 * ixgbe_open - Called when a network interface is made active
4728 * @netdev: network interface device structure
4729 *
4730 * Returns 0 on success, negative value on failure
4731 *
4732 * The open entry point is called when a network interface is made
4733 * active by the system (IFF_UP). At this point all resources needed
4734 * for transmit and receive operations are allocated, the interrupt
4735 * handler is registered with the OS, the watchdog timer is started,
4736 * and the stack is notified that the interface is ready.
4737 **/
4738 static int ixgbe_open(struct net_device *netdev)
4739 {
4740 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4741 int err;
4742
4743 /* disallow open during test */
4744 if (test_bit(__IXGBE_TESTING, &adapter->state))
4745 return -EBUSY;
4746
4747 netif_carrier_off(netdev);
4748
4749 /* allocate transmit descriptors */
4750 err = ixgbe_setup_all_tx_resources(adapter);
4751 if (err)
4752 goto err_setup_tx;
4753
4754 /* allocate receive descriptors */
4755 err = ixgbe_setup_all_rx_resources(adapter);
4756 if (err)
4757 goto err_setup_rx;
4758
4759 ixgbe_configure(adapter);
4760
4761 err = ixgbe_request_irq(adapter);
4762 if (err)
4763 goto err_req_irq;
4764
4765 ixgbe_up_complete(adapter);
4766
4767 return 0;
4768
4769 err_req_irq:
4770 err_setup_rx:
4771 ixgbe_free_all_rx_resources(adapter);
4772 err_setup_tx:
4773 ixgbe_free_all_tx_resources(adapter);
4774 ixgbe_reset(adapter);
4775
4776 return err;
4777 }
4778
4779 /**
4780 * ixgbe_close - Disables a network interface
4781 * @netdev: network interface device structure
4782 *
4783 * Returns 0, this is not allowed to fail
4784 *
4785 * The close entry point is called when an interface is de-activated
4786 * by the OS. The hardware is still under the drivers control, but
4787 * needs to be disabled. A global MAC reset is issued to stop the
4788 * hardware, and all transmit and receive resources are freed.
4789 **/
4790 static int ixgbe_close(struct net_device *netdev)
4791 {
4792 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4793
4794 ixgbe_down(adapter);
4795 ixgbe_free_irq(adapter);
4796
4797 ixgbe_fdir_filter_exit(adapter);
4798
4799 ixgbe_free_all_tx_resources(adapter);
4800 ixgbe_free_all_rx_resources(adapter);
4801
4802 ixgbe_release_hw_control(adapter);
4803
4804 return 0;
4805 }
4806
4807 #ifdef CONFIG_PM
4808 static int ixgbe_resume(struct pci_dev *pdev)
4809 {
4810 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4811 struct net_device *netdev = adapter->netdev;
4812 u32 err;
4813
4814 pci_set_power_state(pdev, PCI_D0);
4815 pci_restore_state(pdev);
4816 /*
4817 * pci_restore_state clears dev->state_saved so call
4818 * pci_save_state to restore it.
4819 */
4820 pci_save_state(pdev);
4821
4822 err = pci_enable_device_mem(pdev);
4823 if (err) {
4824 e_dev_err("Cannot enable PCI device from suspend\n");
4825 return err;
4826 }
4827 pci_set_master(pdev);
4828
4829 pci_wake_from_d3(pdev, false);
4830
4831 rtnl_lock();
4832 err = ixgbe_init_interrupt_scheme(adapter);
4833 rtnl_unlock();
4834 if (err) {
4835 e_dev_err("Cannot initialize interrupts for device\n");
4836 return err;
4837 }
4838
4839 ixgbe_reset(adapter);
4840
4841 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4842
4843 if (netif_running(netdev)) {
4844 err = ixgbe_open(netdev);
4845 if (err)
4846 return err;
4847 }
4848
4849 netif_device_attach(netdev);
4850
4851 return 0;
4852 }
4853 #endif /* CONFIG_PM */
4854
4855 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4856 {
4857 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4858 struct net_device *netdev = adapter->netdev;
4859 struct ixgbe_hw *hw = &adapter->hw;
4860 u32 ctrl, fctrl;
4861 u32 wufc = adapter->wol;
4862 #ifdef CONFIG_PM
4863 int retval = 0;
4864 #endif
4865
4866 netif_device_detach(netdev);
4867
4868 if (netif_running(netdev)) {
4869 ixgbe_down(adapter);
4870 ixgbe_free_irq(adapter);
4871 ixgbe_free_all_tx_resources(adapter);
4872 ixgbe_free_all_rx_resources(adapter);
4873 }
4874
4875 ixgbe_clear_interrupt_scheme(adapter);
4876 #ifdef CONFIG_DCB
4877 kfree(adapter->ixgbe_ieee_pfc);
4878 kfree(adapter->ixgbe_ieee_ets);
4879 #endif
4880
4881 #ifdef CONFIG_PM
4882 retval = pci_save_state(pdev);
4883 if (retval)
4884 return retval;
4885
4886 #endif
4887 if (wufc) {
4888 ixgbe_set_rx_mode(netdev);
4889
4890 /*
4891 * enable the optics for both mult-speed fiber and
4892 * 82599 SFP+ fiber as we can WoL.
4893 */
4894 if (hw->mac.ops.enable_tx_laser &&
4895 (hw->phy.multispeed_fiber ||
4896 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4897 hw->mac.type == ixgbe_mac_82599EB)))
4898 hw->mac.ops.enable_tx_laser(hw);
4899
4900 /* turn on all-multi mode if wake on multicast is enabled */
4901 if (wufc & IXGBE_WUFC_MC) {
4902 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4903 fctrl |= IXGBE_FCTRL_MPE;
4904 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4905 }
4906
4907 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4908 ctrl |= IXGBE_CTRL_GIO_DIS;
4909 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4910
4911 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4912 } else {
4913 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4914 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4915 }
4916
4917 switch (hw->mac.type) {
4918 case ixgbe_mac_82598EB:
4919 pci_wake_from_d3(pdev, false);
4920 break;
4921 case ixgbe_mac_82599EB:
4922 case ixgbe_mac_X540:
4923 pci_wake_from_d3(pdev, !!wufc);
4924 break;
4925 default:
4926 break;
4927 }
4928
4929 *enable_wake = !!wufc;
4930
4931 ixgbe_release_hw_control(adapter);
4932
4933 pci_disable_device(pdev);
4934
4935 return 0;
4936 }
4937
4938 #ifdef CONFIG_PM
4939 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4940 {
4941 int retval;
4942 bool wake;
4943
4944 retval = __ixgbe_shutdown(pdev, &wake);
4945 if (retval)
4946 return retval;
4947
4948 if (wake) {
4949 pci_prepare_to_sleep(pdev);
4950 } else {
4951 pci_wake_from_d3(pdev, false);
4952 pci_set_power_state(pdev, PCI_D3hot);
4953 }
4954
4955 return 0;
4956 }
4957 #endif /* CONFIG_PM */
4958
4959 static void ixgbe_shutdown(struct pci_dev *pdev)
4960 {
4961 bool wake;
4962
4963 __ixgbe_shutdown(pdev, &wake);
4964
4965 if (system_state == SYSTEM_POWER_OFF) {
4966 pci_wake_from_d3(pdev, wake);
4967 pci_set_power_state(pdev, PCI_D3hot);
4968 }
4969 }
4970
4971 /**
4972 * ixgbe_update_stats - Update the board statistics counters.
4973 * @adapter: board private structure
4974 **/
4975 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4976 {
4977 struct net_device *netdev = adapter->netdev;
4978 struct ixgbe_hw *hw = &adapter->hw;
4979 struct ixgbe_hw_stats *hwstats = &adapter->stats;
4980 u64 total_mpc = 0;
4981 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4982 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
4983 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
4984 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
4985 #ifdef IXGBE_FCOE
4986 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4987 unsigned int cpu;
4988 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
4989 #endif /* IXGBE_FCOE */
4990
4991 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4992 test_bit(__IXGBE_RESETTING, &adapter->state))
4993 return;
4994
4995 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
4996 u64 rsc_count = 0;
4997 u64 rsc_flush = 0;
4998 for (i = 0; i < 16; i++)
4999 adapter->hw_rx_no_dma_resources +=
5000 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5001 for (i = 0; i < adapter->num_rx_queues; i++) {
5002 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5003 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5004 }
5005 adapter->rsc_total_count = rsc_count;
5006 adapter->rsc_total_flush = rsc_flush;
5007 }
5008
5009 for (i = 0; i < adapter->num_rx_queues; i++) {
5010 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5011 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5012 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5013 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5014 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5015 bytes += rx_ring->stats.bytes;
5016 packets += rx_ring->stats.packets;
5017 }
5018 adapter->non_eop_descs = non_eop_descs;
5019 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5020 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5021 adapter->hw_csum_rx_error = hw_csum_rx_error;
5022 netdev->stats.rx_bytes = bytes;
5023 netdev->stats.rx_packets = packets;
5024
5025 bytes = 0;
5026 packets = 0;
5027 /* gather some stats to the adapter struct that are per queue */
5028 for (i = 0; i < adapter->num_tx_queues; i++) {
5029 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5030 restart_queue += tx_ring->tx_stats.restart_queue;
5031 tx_busy += tx_ring->tx_stats.tx_busy;
5032 bytes += tx_ring->stats.bytes;
5033 packets += tx_ring->stats.packets;
5034 }
5035 adapter->restart_queue = restart_queue;
5036 adapter->tx_busy = tx_busy;
5037 netdev->stats.tx_bytes = bytes;
5038 netdev->stats.tx_packets = packets;
5039
5040 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5041
5042 /* 8 register reads */
5043 for (i = 0; i < 8; i++) {
5044 /* for packet buffers not used, the register should read 0 */
5045 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5046 missed_rx += mpc;
5047 hwstats->mpc[i] += mpc;
5048 total_mpc += hwstats->mpc[i];
5049 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5050 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5051 switch (hw->mac.type) {
5052 case ixgbe_mac_82598EB:
5053 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5054 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5055 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5056 hwstats->pxonrxc[i] +=
5057 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5058 break;
5059 case ixgbe_mac_82599EB:
5060 case ixgbe_mac_X540:
5061 hwstats->pxonrxc[i] +=
5062 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5063 break;
5064 default:
5065 break;
5066 }
5067 }
5068
5069 /*16 register reads */
5070 for (i = 0; i < 16; i++) {
5071 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5072 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5073 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5074 (hw->mac.type == ixgbe_mac_X540)) {
5075 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5076 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5077 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5078 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5079 }
5080 }
5081
5082 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5083 /* work around hardware counting issue */
5084 hwstats->gprc -= missed_rx;
5085
5086 ixgbe_update_xoff_received(adapter);
5087
5088 /* 82598 hardware only has a 32 bit counter in the high register */
5089 switch (hw->mac.type) {
5090 case ixgbe_mac_82598EB:
5091 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5092 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5093 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5094 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5095 break;
5096 case ixgbe_mac_X540:
5097 /* OS2BMC stats are X540 only*/
5098 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5099 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5100 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5101 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5102 case ixgbe_mac_82599EB:
5103 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5104 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5105 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5106 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5107 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5108 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5109 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5110 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5111 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5112 #ifdef IXGBE_FCOE
5113 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5114 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5115 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5116 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5117 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5118 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5119 /* Add up per cpu counters for total ddp aloc fail */
5120 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5121 for_each_possible_cpu(cpu) {
5122 fcoe_noddp_counts_sum +=
5123 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5124 fcoe_noddp_ext_buff_counts_sum +=
5125 *per_cpu_ptr(fcoe->
5126 pcpu_noddp_ext_buff, cpu);
5127 }
5128 }
5129 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5130 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
5131 #endif /* IXGBE_FCOE */
5132 break;
5133 default:
5134 break;
5135 }
5136 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5137 hwstats->bprc += bprc;
5138 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5139 if (hw->mac.type == ixgbe_mac_82598EB)
5140 hwstats->mprc -= bprc;
5141 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5142 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5143 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5144 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5145 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5146 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5147 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5148 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5149 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5150 hwstats->lxontxc += lxon;
5151 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5152 hwstats->lxofftxc += lxoff;
5153 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5154 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5155 /*
5156 * 82598 errata - tx of flow control packets is included in tx counters
5157 */
5158 xon_off_tot = lxon + lxoff;
5159 hwstats->gptc -= xon_off_tot;
5160 hwstats->mptc -= xon_off_tot;
5161 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5162 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5163 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5164 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5165 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5166 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5167 hwstats->ptc64 -= xon_off_tot;
5168 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5169 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5170 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5171 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5172 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5173 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5174
5175 /* Fill out the OS statistics structure */
5176 netdev->stats.multicast = hwstats->mprc;
5177
5178 /* Rx Errors */
5179 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5180 netdev->stats.rx_dropped = 0;
5181 netdev->stats.rx_length_errors = hwstats->rlec;
5182 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5183 netdev->stats.rx_missed_errors = total_mpc;
5184 }
5185
5186 /**
5187 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5188 * @adapter - pointer to the device adapter structure
5189 **/
5190 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5191 {
5192 struct ixgbe_hw *hw = &adapter->hw;
5193 int i;
5194
5195 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5196 return;
5197
5198 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5199
5200 /* if interface is down do nothing */
5201 if (test_bit(__IXGBE_DOWN, &adapter->state))
5202 return;
5203
5204 /* do nothing if we are not using signature filters */
5205 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5206 return;
5207
5208 adapter->fdir_overflow++;
5209
5210 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5211 for (i = 0; i < adapter->num_tx_queues; i++)
5212 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5213 &(adapter->tx_ring[i]->state));
5214 /* re-enable flow director interrupts */
5215 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5216 } else {
5217 e_err(probe, "failed to finish FDIR re-initialization, "
5218 "ignored adding FDIR ATR filters\n");
5219 }
5220 }
5221
5222 /**
5223 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5224 * @adapter - pointer to the device adapter structure
5225 *
5226 * This function serves two purposes. First it strobes the interrupt lines
5227 * in order to make certain interrupts are occurring. Secondly it sets the
5228 * bits needed to check for TX hangs. As a result we should immediately
5229 * determine if a hang has occurred.
5230 */
5231 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5232 {
5233 struct ixgbe_hw *hw = &adapter->hw;
5234 u64 eics = 0;
5235 int i;
5236
5237 /* If we're down or resetting, just bail */
5238 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5239 test_bit(__IXGBE_RESETTING, &adapter->state))
5240 return;
5241
5242 /* Force detection of hung controller */
5243 if (netif_carrier_ok(adapter->netdev)) {
5244 for (i = 0; i < adapter->num_tx_queues; i++)
5245 set_check_for_tx_hang(adapter->tx_ring[i]);
5246 }
5247
5248 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5249 /*
5250 * for legacy and MSI interrupts don't set any bits
5251 * that are enabled for EIAM, because this operation
5252 * would set *both* EIMS and EICS for any bit in EIAM
5253 */
5254 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5255 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5256 } else {
5257 /* get one bit for every active tx/rx interrupt vector */
5258 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5259 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5260 if (qv->rx.ring || qv->tx.ring)
5261 eics |= ((u64)1 << i);
5262 }
5263 }
5264
5265 /* Cause software interrupt to ensure rings are cleaned */
5266 ixgbe_irq_rearm_queues(adapter, eics);
5267
5268 }
5269
5270 /**
5271 * ixgbe_watchdog_update_link - update the link status
5272 * @adapter - pointer to the device adapter structure
5273 * @link_speed - pointer to a u32 to store the link_speed
5274 **/
5275 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5276 {
5277 struct ixgbe_hw *hw = &adapter->hw;
5278 u32 link_speed = adapter->link_speed;
5279 bool link_up = adapter->link_up;
5280 int i;
5281
5282 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5283 return;
5284
5285 if (hw->mac.ops.check_link) {
5286 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5287 } else {
5288 /* always assume link is up, if no check link function */
5289 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5290 link_up = true;
5291 }
5292 if (link_up) {
5293 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5294 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5295 hw->mac.ops.fc_enable(hw, i);
5296 } else {
5297 hw->mac.ops.fc_enable(hw, 0);
5298 }
5299 }
5300
5301 if (link_up ||
5302 time_after(jiffies, (adapter->link_check_timeout +
5303 IXGBE_TRY_LINK_TIMEOUT))) {
5304 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5305 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5306 IXGBE_WRITE_FLUSH(hw);
5307 }
5308
5309 adapter->link_up = link_up;
5310 adapter->link_speed = link_speed;
5311 }
5312
5313 /**
5314 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5315 * print link up message
5316 * @adapter - pointer to the device adapter structure
5317 **/
5318 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5319 {
5320 struct net_device *netdev = adapter->netdev;
5321 struct ixgbe_hw *hw = &adapter->hw;
5322 u32 link_speed = adapter->link_speed;
5323 bool flow_rx, flow_tx;
5324
5325 /* only continue if link was previously down */
5326 if (netif_carrier_ok(netdev))
5327 return;
5328
5329 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5330
5331 switch (hw->mac.type) {
5332 case ixgbe_mac_82598EB: {
5333 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5334 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5335 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5336 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5337 }
5338 break;
5339 case ixgbe_mac_X540:
5340 case ixgbe_mac_82599EB: {
5341 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5342 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5343 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5344 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5345 }
5346 break;
5347 default:
5348 flow_tx = false;
5349 flow_rx = false;
5350 break;
5351 }
5352 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5353 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5354 "10 Gbps" :
5355 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5356 "1 Gbps" :
5357 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5358 "100 Mbps" :
5359 "unknown speed"))),
5360 ((flow_rx && flow_tx) ? "RX/TX" :
5361 (flow_rx ? "RX" :
5362 (flow_tx ? "TX" : "None"))));
5363
5364 netif_carrier_on(netdev);
5365 ixgbe_check_vf_rate_limit(adapter);
5366 }
5367
5368 /**
5369 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5370 * print link down message
5371 * @adapter - pointer to the adapter structure
5372 **/
5373 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
5374 {
5375 struct net_device *netdev = adapter->netdev;
5376 struct ixgbe_hw *hw = &adapter->hw;
5377
5378 adapter->link_up = false;
5379 adapter->link_speed = 0;
5380
5381 /* only continue if link was up previously */
5382 if (!netif_carrier_ok(netdev))
5383 return;
5384
5385 /* poll for SFP+ cable when link is down */
5386 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5387 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5388
5389 e_info(drv, "NIC Link is Down\n");
5390 netif_carrier_off(netdev);
5391 }
5392
5393 /**
5394 * ixgbe_watchdog_flush_tx - flush queues on link down
5395 * @adapter - pointer to the device adapter structure
5396 **/
5397 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5398 {
5399 int i;
5400 int some_tx_pending = 0;
5401
5402 if (!netif_carrier_ok(adapter->netdev)) {
5403 for (i = 0; i < adapter->num_tx_queues; i++) {
5404 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5405 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5406 some_tx_pending = 1;
5407 break;
5408 }
5409 }
5410
5411 if (some_tx_pending) {
5412 /* We've lost link, so the controller stops DMA,
5413 * but we've got queued Tx work that's never going
5414 * to get done, so reset controller to flush Tx.
5415 * (Do the reset outside of interrupt context).
5416 */
5417 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
5418 }
5419 }
5420 }
5421
5422 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5423 {
5424 u32 ssvpc;
5425
5426 /* Do not perform spoof check for 82598 */
5427 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5428 return;
5429
5430 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5431
5432 /*
5433 * ssvpc register is cleared on read, if zero then no
5434 * spoofed packets in the last interval.
5435 */
5436 if (!ssvpc)
5437 return;
5438
5439 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5440 }
5441
5442 /**
5443 * ixgbe_watchdog_subtask - check and bring link up
5444 * @adapter - pointer to the device adapter structure
5445 **/
5446 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5447 {
5448 /* if interface is down do nothing */
5449 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5450 test_bit(__IXGBE_RESETTING, &adapter->state))
5451 return;
5452
5453 ixgbe_watchdog_update_link(adapter);
5454
5455 if (adapter->link_up)
5456 ixgbe_watchdog_link_is_up(adapter);
5457 else
5458 ixgbe_watchdog_link_is_down(adapter);
5459
5460 ixgbe_spoof_check(adapter);
5461 ixgbe_update_stats(adapter);
5462
5463 ixgbe_watchdog_flush_tx(adapter);
5464 }
5465
5466 /**
5467 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
5468 * @adapter - the ixgbe adapter structure
5469 **/
5470 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
5471 {
5472 struct ixgbe_hw *hw = &adapter->hw;
5473 s32 err;
5474
5475 /* not searching for SFP so there is nothing to do here */
5476 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5477 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5478 return;
5479
5480 /* someone else is in init, wait until next service event */
5481 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5482 return;
5483
5484 err = hw->phy.ops.identify_sfp(hw);
5485 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5486 goto sfp_out;
5487
5488 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5489 /* If no cable is present, then we need to reset
5490 * the next time we find a good cable. */
5491 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5492 }
5493
5494 /* exit on error */
5495 if (err)
5496 goto sfp_out;
5497
5498 /* exit if reset not needed */
5499 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5500 goto sfp_out;
5501
5502 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
5503
5504 /*
5505 * A module may be identified correctly, but the EEPROM may not have
5506 * support for that module. setup_sfp() will fail in that case, so
5507 * we should not allow that module to load.
5508 */
5509 if (hw->mac.type == ixgbe_mac_82598EB)
5510 err = hw->phy.ops.reset(hw);
5511 else
5512 err = hw->mac.ops.setup_sfp(hw);
5513
5514 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5515 goto sfp_out;
5516
5517 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5518 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5519
5520 sfp_out:
5521 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5522
5523 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5524 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5525 e_dev_err("failed to initialize because an unsupported "
5526 "SFP+ module type was detected.\n");
5527 e_dev_err("Reload the driver after installing a "
5528 "supported module.\n");
5529 unregister_netdev(adapter->netdev);
5530 }
5531 }
5532
5533 /**
5534 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
5535 * @adapter - the ixgbe adapter structure
5536 **/
5537 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5538 {
5539 struct ixgbe_hw *hw = &adapter->hw;
5540 u32 autoneg;
5541 bool negotiation;
5542
5543 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5544 return;
5545
5546 /* someone else is in init, wait until next service event */
5547 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5548 return;
5549
5550 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5551
5552 autoneg = hw->phy.autoneg_advertised;
5553 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5554 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5555 if (hw->mac.ops.setup_link)
5556 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5557
5558 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5559 adapter->link_check_timeout = jiffies;
5560 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5561 }
5562
5563 #ifdef CONFIG_PCI_IOV
5564 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5565 {
5566 int vf;
5567 struct ixgbe_hw *hw = &adapter->hw;
5568 struct net_device *netdev = adapter->netdev;
5569 u32 gpc;
5570 u32 ciaa, ciad;
5571
5572 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5573 if (gpc) /* If incrementing then no need for the check below */
5574 return;
5575 /*
5576 * Check to see if a bad DMA write target from an errant or
5577 * malicious VF has caused a PCIe error. If so then we can
5578 * issue a VFLR to the offending VF(s) and then resume without
5579 * requesting a full slot reset.
5580 */
5581
5582 for (vf = 0; vf < adapter->num_vfs; vf++) {
5583 ciaa = (vf << 16) | 0x80000000;
5584 /* 32 bit read so align, we really want status at offset 6 */
5585 ciaa |= PCI_COMMAND;
5586 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5587 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5588 ciaa &= 0x7FFFFFFF;
5589 /* disable debug mode asap after reading data */
5590 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5591 /* Get the upper 16 bits which will be the PCI status reg */
5592 ciad >>= 16;
5593 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5594 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5595 /* Issue VFLR */
5596 ciaa = (vf << 16) | 0x80000000;
5597 ciaa |= 0xA8;
5598 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5599 ciad = 0x00008000; /* VFLR */
5600 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5601 ciaa &= 0x7FFFFFFF;
5602 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5603 }
5604 }
5605 }
5606
5607 #endif
5608 /**
5609 * ixgbe_service_timer - Timer Call-back
5610 * @data: pointer to adapter cast into an unsigned long
5611 **/
5612 static void ixgbe_service_timer(unsigned long data)
5613 {
5614 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5615 unsigned long next_event_offset;
5616 bool ready = true;
5617
5618 /* poll faster when waiting for link */
5619 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5620 next_event_offset = HZ / 10;
5621 else
5622 next_event_offset = HZ * 2;
5623
5624 #ifdef CONFIG_PCI_IOV
5625 /*
5626 * don't bother with SR-IOV VF DMA hang check if there are
5627 * no VFs or the link is down
5628 */
5629 if (!adapter->num_vfs ||
5630 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5631 goto normal_timer_service;
5632
5633 /* If we have VFs allocated then we must check for DMA hangs */
5634 ixgbe_check_for_bad_vf(adapter);
5635 next_event_offset = HZ / 50;
5636 adapter->timer_event_accumulator++;
5637
5638 if (adapter->timer_event_accumulator >= 100)
5639 adapter->timer_event_accumulator = 0;
5640 else
5641 ready = false;
5642
5643 normal_timer_service:
5644 #endif
5645 /* Reset the timer */
5646 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5647
5648 if (ready)
5649 ixgbe_service_event_schedule(adapter);
5650 }
5651
5652 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5653 {
5654 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5655 return;
5656
5657 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5658
5659 /* If we're already down or resetting, just bail */
5660 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5661 test_bit(__IXGBE_RESETTING, &adapter->state))
5662 return;
5663
5664 ixgbe_dump(adapter);
5665 netdev_err(adapter->netdev, "Reset adapter\n");
5666 adapter->tx_timeout_count++;
5667
5668 ixgbe_reinit_locked(adapter);
5669 }
5670
5671 /**
5672 * ixgbe_service_task - manages and runs subtasks
5673 * @work: pointer to work_struct containing our data
5674 **/
5675 static void ixgbe_service_task(struct work_struct *work)
5676 {
5677 struct ixgbe_adapter *adapter = container_of(work,
5678 struct ixgbe_adapter,
5679 service_task);
5680
5681 ixgbe_reset_subtask(adapter);
5682 ixgbe_sfp_detection_subtask(adapter);
5683 ixgbe_sfp_link_config_subtask(adapter);
5684 ixgbe_check_overtemp_subtask(adapter);
5685 ixgbe_watchdog_subtask(adapter);
5686 ixgbe_fdir_reinit_subtask(adapter);
5687 ixgbe_check_hang_subtask(adapter);
5688
5689 ixgbe_service_event_complete(adapter);
5690 }
5691
5692 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5693 struct ixgbe_tx_buffer *first,
5694 u8 *hdr_len)
5695 {
5696 struct sk_buff *skb = first->skb;
5697 u32 vlan_macip_lens, type_tucmd;
5698 u32 mss_l4len_idx, l4len;
5699
5700 if (!skb_is_gso(skb))
5701 return 0;
5702
5703 if (skb_header_cloned(skb)) {
5704 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5705 if (err)
5706 return err;
5707 }
5708
5709 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5710 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5711
5712 if (first->protocol == __constant_htons(ETH_P_IP)) {
5713 struct iphdr *iph = ip_hdr(skb);
5714 iph->tot_len = 0;
5715 iph->check = 0;
5716 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5717 iph->daddr, 0,
5718 IPPROTO_TCP,
5719 0);
5720 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5721 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5722 IXGBE_TX_FLAGS_CSUM |
5723 IXGBE_TX_FLAGS_IPV4;
5724 } else if (skb_is_gso_v6(skb)) {
5725 ipv6_hdr(skb)->payload_len = 0;
5726 tcp_hdr(skb)->check =
5727 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5728 &ipv6_hdr(skb)->daddr,
5729 0, IPPROTO_TCP, 0);
5730 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5731 IXGBE_TX_FLAGS_CSUM;
5732 }
5733
5734 /* compute header lengths */
5735 l4len = tcp_hdrlen(skb);
5736 *hdr_len = skb_transport_offset(skb) + l4len;
5737
5738 /* update gso size and bytecount with header size */
5739 first->gso_segs = skb_shinfo(skb)->gso_segs;
5740 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5741
5742 /* mss_l4len_id: use 1 as index for TSO */
5743 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5744 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5745 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5746
5747 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5748 vlan_macip_lens = skb_network_header_len(skb);
5749 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5750 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5751
5752 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
5753 mss_l4len_idx);
5754
5755 return 1;
5756 }
5757
5758 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5759 struct ixgbe_tx_buffer *first)
5760 {
5761 struct sk_buff *skb = first->skb;
5762 u32 vlan_macip_lens = 0;
5763 u32 mss_l4len_idx = 0;
5764 u32 type_tucmd = 0;
5765
5766 if (skb->ip_summed != CHECKSUM_PARTIAL) {
5767 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5768 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5769 return;
5770 } else {
5771 u8 l4_hdr = 0;
5772 switch (first->protocol) {
5773 case __constant_htons(ETH_P_IP):
5774 vlan_macip_lens |= skb_network_header_len(skb);
5775 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5776 l4_hdr = ip_hdr(skb)->protocol;
5777 break;
5778 case __constant_htons(ETH_P_IPV6):
5779 vlan_macip_lens |= skb_network_header_len(skb);
5780 l4_hdr = ipv6_hdr(skb)->nexthdr;
5781 break;
5782 default:
5783 if (unlikely(net_ratelimit())) {
5784 dev_warn(tx_ring->dev,
5785 "partial checksum but proto=%x!\n",
5786 first->protocol);
5787 }
5788 break;
5789 }
5790
5791 switch (l4_hdr) {
5792 case IPPROTO_TCP:
5793 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5794 mss_l4len_idx = tcp_hdrlen(skb) <<
5795 IXGBE_ADVTXD_L4LEN_SHIFT;
5796 break;
5797 case IPPROTO_SCTP:
5798 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5799 mss_l4len_idx = sizeof(struct sctphdr) <<
5800 IXGBE_ADVTXD_L4LEN_SHIFT;
5801 break;
5802 case IPPROTO_UDP:
5803 mss_l4len_idx = sizeof(struct udphdr) <<
5804 IXGBE_ADVTXD_L4LEN_SHIFT;
5805 break;
5806 default:
5807 if (unlikely(net_ratelimit())) {
5808 dev_warn(tx_ring->dev,
5809 "partial checksum but l4 proto=%x!\n",
5810 l4_hdr);
5811 }
5812 break;
5813 }
5814
5815 /* update TX checksum flag */
5816 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
5817 }
5818
5819 /* vlan_macip_lens: MACLEN, VLAN tag */
5820 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
5821 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
5822
5823 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5824 type_tucmd, mss_l4len_idx);
5825 }
5826
5827 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
5828 {
5829 /* set type for advanced descriptor with frame checksum insertion */
5830 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5831 IXGBE_ADVTXD_DCMD_IFCS |
5832 IXGBE_ADVTXD_DCMD_DEXT);
5833
5834 /* set HW vlan bit if vlan is present */
5835 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
5836 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
5837
5838 /* set segmentation enable bits for TSO/FSO */
5839 #ifdef IXGBE_FCOE
5840 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
5841 #else
5842 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5843 #endif
5844 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
5845
5846 return cmd_type;
5847 }
5848
5849 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5850 u32 tx_flags, unsigned int paylen)
5851 {
5852 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
5853
5854 /* enable L4 checksum for TSO and TX checksum offload */
5855 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5856 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
5857
5858 /* enble IPv4 checksum for TSO */
5859 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5860 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
5861
5862 /* use index 1 context for TSO/FSO/FCOE */
5863 #ifdef IXGBE_FCOE
5864 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5865 #else
5866 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5867 #endif
5868 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5869
5870 /*
5871 * Check Context must be set if Tx switch is enabled, which it
5872 * always is for case where virtual functions are running
5873 */
5874 #ifdef IXGBE_FCOE
5875 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5876 #else
5877 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
5878 #endif
5879 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5880
5881 tx_desc->read.olinfo_status = olinfo_status;
5882 }
5883
5884 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
5885 IXGBE_TXD_CMD_RS)
5886
5887 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
5888 struct ixgbe_tx_buffer *first,
5889 const u8 hdr_len)
5890 {
5891 dma_addr_t dma;
5892 struct sk_buff *skb = first->skb;
5893 struct ixgbe_tx_buffer *tx_buffer;
5894 union ixgbe_adv_tx_desc *tx_desc;
5895 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
5896 unsigned int data_len = skb->data_len;
5897 unsigned int size = skb_headlen(skb);
5898 unsigned int paylen = skb->len - hdr_len;
5899 u32 tx_flags = first->tx_flags;
5900 __le32 cmd_type;
5901 u16 i = tx_ring->next_to_use;
5902
5903 tx_desc = IXGBE_TX_DESC(tx_ring, i);
5904
5905 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
5906 cmd_type = ixgbe_tx_cmd_type(tx_flags);
5907
5908 #ifdef IXGBE_FCOE
5909 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5910 if (data_len < sizeof(struct fcoe_crc_eof)) {
5911 size -= sizeof(struct fcoe_crc_eof) - data_len;
5912 data_len = 0;
5913 } else {
5914 data_len -= sizeof(struct fcoe_crc_eof);
5915 }
5916 }
5917
5918 #endif
5919 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5920 if (dma_mapping_error(tx_ring->dev, dma))
5921 goto dma_error;
5922
5923 /* record length, and DMA address */
5924 dma_unmap_len_set(first, len, size);
5925 dma_unmap_addr_set(first, dma, dma);
5926
5927 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5928
5929 for (;;) {
5930 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
5931 tx_desc->read.cmd_type_len =
5932 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
5933
5934 i++;
5935 tx_desc++;
5936 if (i == tx_ring->count) {
5937 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5938 i = 0;
5939 }
5940
5941 dma += IXGBE_MAX_DATA_PER_TXD;
5942 size -= IXGBE_MAX_DATA_PER_TXD;
5943
5944 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5945 tx_desc->read.olinfo_status = 0;
5946 }
5947
5948 if (likely(!data_len))
5949 break;
5950
5951 if (unlikely(skb->no_fcs))
5952 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
5953 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
5954
5955 i++;
5956 tx_desc++;
5957 if (i == tx_ring->count) {
5958 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
5959 i = 0;
5960 }
5961
5962 #ifdef IXGBE_FCOE
5963 size = min_t(unsigned int, data_len, skb_frag_size(frag));
5964 #else
5965 size = skb_frag_size(frag);
5966 #endif
5967 data_len -= size;
5968
5969 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
5970 DMA_TO_DEVICE);
5971 if (dma_mapping_error(tx_ring->dev, dma))
5972 goto dma_error;
5973
5974 tx_buffer = &tx_ring->tx_buffer_info[i];
5975 dma_unmap_len_set(tx_buffer, len, size);
5976 dma_unmap_addr_set(tx_buffer, dma, dma);
5977
5978 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5979 tx_desc->read.olinfo_status = 0;
5980
5981 frag++;
5982 }
5983
5984 /* write last descriptor with RS and EOP bits */
5985 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
5986 tx_desc->read.cmd_type_len = cmd_type;
5987
5988 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
5989
5990 /* set the timestamp */
5991 first->time_stamp = jiffies;
5992
5993 /*
5994 * Force memory writes to complete before letting h/w know there
5995 * are new descriptors to fetch. (Only applicable for weak-ordered
5996 * memory model archs, such as IA-64).
5997 *
5998 * We also need this memory barrier to make certain all of the
5999 * status bits have been updated before next_to_watch is written.
6000 */
6001 wmb();
6002
6003 /* set next_to_watch value indicating a packet is present */
6004 first->next_to_watch = tx_desc;
6005
6006 i++;
6007 if (i == tx_ring->count)
6008 i = 0;
6009
6010 tx_ring->next_to_use = i;
6011
6012 /* notify HW of packet */
6013 writel(i, tx_ring->tail);
6014
6015 return;
6016 dma_error:
6017 dev_err(tx_ring->dev, "TX DMA map failed\n");
6018
6019 /* clear dma mappings for failed tx_buffer_info map */
6020 for (;;) {
6021 tx_buffer = &tx_ring->tx_buffer_info[i];
6022 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6023 if (tx_buffer == first)
6024 break;
6025 if (i == 0)
6026 i = tx_ring->count;
6027 i--;
6028 }
6029
6030 tx_ring->next_to_use = i;
6031 }
6032
6033 static void ixgbe_atr(struct ixgbe_ring *ring,
6034 struct ixgbe_tx_buffer *first)
6035 {
6036 struct ixgbe_q_vector *q_vector = ring->q_vector;
6037 union ixgbe_atr_hash_dword input = { .dword = 0 };
6038 union ixgbe_atr_hash_dword common = { .dword = 0 };
6039 union {
6040 unsigned char *network;
6041 struct iphdr *ipv4;
6042 struct ipv6hdr *ipv6;
6043 } hdr;
6044 struct tcphdr *th;
6045 __be16 vlan_id;
6046
6047 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6048 if (!q_vector)
6049 return;
6050
6051 /* do nothing if sampling is disabled */
6052 if (!ring->atr_sample_rate)
6053 return;
6054
6055 ring->atr_count++;
6056
6057 /* snag network header to get L4 type and address */
6058 hdr.network = skb_network_header(first->skb);
6059
6060 /* Currently only IPv4/IPv6 with TCP is supported */
6061 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
6062 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6063 (first->protocol != __constant_htons(ETH_P_IP) ||
6064 hdr.ipv4->protocol != IPPROTO_TCP))
6065 return;
6066
6067 th = tcp_hdr(first->skb);
6068
6069 /* skip this packet since it is invalid or the socket is closing */
6070 if (!th || th->fin)
6071 return;
6072
6073 /* sample on all syn packets or once every atr sample count */
6074 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6075 return;
6076
6077 /* reset sample count */
6078 ring->atr_count = 0;
6079
6080 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6081
6082 /*
6083 * src and dst are inverted, think how the receiver sees them
6084 *
6085 * The input is broken into two sections, a non-compressed section
6086 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6087 * is XORed together and stored in the compressed dword.
6088 */
6089 input.formatted.vlan_id = vlan_id;
6090
6091 /*
6092 * since src port and flex bytes occupy the same word XOR them together
6093 * and write the value to source port portion of compressed dword
6094 */
6095 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6096 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6097 else
6098 common.port.src ^= th->dest ^ first->protocol;
6099 common.port.dst ^= th->source;
6100
6101 if (first->protocol == __constant_htons(ETH_P_IP)) {
6102 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6103 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6104 } else {
6105 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6106 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6107 hdr.ipv6->saddr.s6_addr32[1] ^
6108 hdr.ipv6->saddr.s6_addr32[2] ^
6109 hdr.ipv6->saddr.s6_addr32[3] ^
6110 hdr.ipv6->daddr.s6_addr32[0] ^
6111 hdr.ipv6->daddr.s6_addr32[1] ^
6112 hdr.ipv6->daddr.s6_addr32[2] ^
6113 hdr.ipv6->daddr.s6_addr32[3];
6114 }
6115
6116 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6117 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6118 input, common, ring->queue_index);
6119 }
6120
6121 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6122 {
6123 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6124 /* Herbert's original patch had:
6125 * smp_mb__after_netif_stop_queue();
6126 * but since that doesn't exist yet, just open code it. */
6127 smp_mb();
6128
6129 /* We need to check again in a case another CPU has just
6130 * made room available. */
6131 if (likely(ixgbe_desc_unused(tx_ring) < size))
6132 return -EBUSY;
6133
6134 /* A reprieve! - use start_queue because it doesn't call schedule */
6135 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6136 ++tx_ring->tx_stats.restart_queue;
6137 return 0;
6138 }
6139
6140 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6141 {
6142 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6143 return 0;
6144 return __ixgbe_maybe_stop_tx(tx_ring, size);
6145 }
6146
6147 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6148 {
6149 struct ixgbe_adapter *adapter = netdev_priv(dev);
6150 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6151 smp_processor_id();
6152 #ifdef IXGBE_FCOE
6153 __be16 protocol = vlan_get_protocol(skb);
6154
6155 if (((protocol == htons(ETH_P_FCOE)) ||
6156 (protocol == htons(ETH_P_FIP))) &&
6157 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6158 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6159 txq += adapter->ring_feature[RING_F_FCOE].mask;
6160 return txq;
6161 }
6162 #endif
6163
6164 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6165 while (unlikely(txq >= dev->real_num_tx_queues))
6166 txq -= dev->real_num_tx_queues;
6167 return txq;
6168 }
6169
6170 return skb_tx_hash(dev, skb);
6171 }
6172
6173 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6174 struct ixgbe_adapter *adapter,
6175 struct ixgbe_ring *tx_ring)
6176 {
6177 struct ixgbe_tx_buffer *first;
6178 int tso;
6179 u32 tx_flags = 0;
6180 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6181 unsigned short f;
6182 #endif
6183 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6184 __be16 protocol = skb->protocol;
6185 u8 hdr_len = 0;
6186
6187 /*
6188 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6189 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
6190 * + 2 desc gap to keep tail from touching head,
6191 * + 1 desc for context descriptor,
6192 * otherwise try next time
6193 */
6194 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6195 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6196 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6197 #else
6198 count += skb_shinfo(skb)->nr_frags;
6199 #endif
6200 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6201 tx_ring->tx_stats.tx_busy++;
6202 return NETDEV_TX_BUSY;
6203 }
6204
6205 /* record the location of the first descriptor for this packet */
6206 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6207 first->skb = skb;
6208 first->bytecount = skb->len;
6209 first->gso_segs = 1;
6210
6211 /* if we have a HW VLAN tag being added default to the HW one */
6212 if (vlan_tx_tag_present(skb)) {
6213 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6214 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6215 /* else if it is a SW VLAN check the next protocol and store the tag */
6216 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6217 struct vlan_hdr *vhdr, _vhdr;
6218 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6219 if (!vhdr)
6220 goto out_drop;
6221
6222 protocol = vhdr->h_vlan_encapsulated_proto;
6223 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6224 IXGBE_TX_FLAGS_VLAN_SHIFT;
6225 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6226 }
6227
6228 #ifdef CONFIG_PCI_IOV
6229 /*
6230 * Use the l2switch_enable flag - would be false if the DMA
6231 * Tx switch had been disabled.
6232 */
6233 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6234 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6235
6236 #endif
6237 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
6238 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6239 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6240 (skb->priority != TC_PRIO_CONTROL))) {
6241 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6242 tx_flags |= (skb->priority & 0x7) <<
6243 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6244 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6245 struct vlan_ethhdr *vhdr;
6246 if (skb_header_cloned(skb) &&
6247 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6248 goto out_drop;
6249 vhdr = (struct vlan_ethhdr *)skb->data;
6250 vhdr->h_vlan_TCI = htons(tx_flags >>
6251 IXGBE_TX_FLAGS_VLAN_SHIFT);
6252 } else {
6253 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6254 }
6255 }
6256
6257 /* record initial flags and protocol */
6258 first->tx_flags = tx_flags;
6259 first->protocol = protocol;
6260
6261 #ifdef IXGBE_FCOE
6262 /* setup tx offload for FCoE */
6263 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6264 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6265 tso = ixgbe_fso(tx_ring, first, &hdr_len);
6266 if (tso < 0)
6267 goto out_drop;
6268
6269 goto xmit_fcoe;
6270 }
6271
6272 #endif /* IXGBE_FCOE */
6273 tso = ixgbe_tso(tx_ring, first, &hdr_len);
6274 if (tso < 0)
6275 goto out_drop;
6276 else if (!tso)
6277 ixgbe_tx_csum(tx_ring, first);
6278
6279 /* add the ATR filter if ATR is on */
6280 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6281 ixgbe_atr(tx_ring, first);
6282
6283 #ifdef IXGBE_FCOE
6284 xmit_fcoe:
6285 #endif /* IXGBE_FCOE */
6286 ixgbe_tx_map(tx_ring, first, hdr_len);
6287
6288 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6289
6290 return NETDEV_TX_OK;
6291
6292 out_drop:
6293 dev_kfree_skb_any(first->skb);
6294 first->skb = NULL;
6295
6296 return NETDEV_TX_OK;
6297 }
6298
6299 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6300 struct net_device *netdev)
6301 {
6302 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6303 struct ixgbe_ring *tx_ring;
6304
6305 if (skb->len <= 0) {
6306 dev_kfree_skb_any(skb);
6307 return NETDEV_TX_OK;
6308 }
6309
6310 /*
6311 * The minimum packet size for olinfo paylen is 17 so pad the skb
6312 * in order to meet this minimum size requirement.
6313 */
6314 if (skb->len < 17) {
6315 if (skb_padto(skb, 17))
6316 return NETDEV_TX_OK;
6317 skb->len = 17;
6318 }
6319
6320 tx_ring = adapter->tx_ring[skb->queue_mapping];
6321 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6322 }
6323
6324 /**
6325 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6326 * @netdev: network interface device structure
6327 * @p: pointer to an address structure
6328 *
6329 * Returns 0 on success, negative on failure
6330 **/
6331 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6332 {
6333 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6334 struct ixgbe_hw *hw = &adapter->hw;
6335 struct sockaddr *addr = p;
6336
6337 if (!is_valid_ether_addr(addr->sa_data))
6338 return -EADDRNOTAVAIL;
6339
6340 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6341 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6342
6343 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6344 IXGBE_RAH_AV);
6345
6346 return 0;
6347 }
6348
6349 static int
6350 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6351 {
6352 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6353 struct ixgbe_hw *hw = &adapter->hw;
6354 u16 value;
6355 int rc;
6356
6357 if (prtad != hw->phy.mdio.prtad)
6358 return -EINVAL;
6359 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6360 if (!rc)
6361 rc = value;
6362 return rc;
6363 }
6364
6365 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6366 u16 addr, u16 value)
6367 {
6368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6369 struct ixgbe_hw *hw = &adapter->hw;
6370
6371 if (prtad != hw->phy.mdio.prtad)
6372 return -EINVAL;
6373 return hw->phy.ops.write_reg(hw, addr, devad, value);
6374 }
6375
6376 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6377 {
6378 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6379
6380 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6381 }
6382
6383 /**
6384 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6385 * netdev->dev_addrs
6386 * @netdev: network interface device structure
6387 *
6388 * Returns non-zero on failure
6389 **/
6390 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6391 {
6392 int err = 0;
6393 struct ixgbe_adapter *adapter = netdev_priv(dev);
6394 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6395
6396 if (is_valid_ether_addr(mac->san_addr)) {
6397 rtnl_lock();
6398 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6399 rtnl_unlock();
6400 }
6401 return err;
6402 }
6403
6404 /**
6405 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6406 * netdev->dev_addrs
6407 * @netdev: network interface device structure
6408 *
6409 * Returns non-zero on failure
6410 **/
6411 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6412 {
6413 int err = 0;
6414 struct ixgbe_adapter *adapter = netdev_priv(dev);
6415 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6416
6417 if (is_valid_ether_addr(mac->san_addr)) {
6418 rtnl_lock();
6419 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6420 rtnl_unlock();
6421 }
6422 return err;
6423 }
6424
6425 #ifdef CONFIG_NET_POLL_CONTROLLER
6426 /*
6427 * Polling 'interrupt' - used by things like netconsole to send skbs
6428 * without having to re-enable interrupts. It's not called while
6429 * the interrupt routine is executing.
6430 */
6431 static void ixgbe_netpoll(struct net_device *netdev)
6432 {
6433 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6434 int i;
6435
6436 /* if interface is down do nothing */
6437 if (test_bit(__IXGBE_DOWN, &adapter->state))
6438 return;
6439
6440 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6441 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6442 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6443 for (i = 0; i < num_q_vectors; i++) {
6444 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6445 ixgbe_msix_clean_rings(0, q_vector);
6446 }
6447 } else {
6448 ixgbe_intr(adapter->pdev->irq, netdev);
6449 }
6450 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6451 }
6452
6453 #endif
6454 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6455 struct rtnl_link_stats64 *stats)
6456 {
6457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6458 int i;
6459
6460 rcu_read_lock();
6461 for (i = 0; i < adapter->num_rx_queues; i++) {
6462 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6463 u64 bytes, packets;
6464 unsigned int start;
6465
6466 if (ring) {
6467 do {
6468 start = u64_stats_fetch_begin_bh(&ring->syncp);
6469 packets = ring->stats.packets;
6470 bytes = ring->stats.bytes;
6471 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6472 stats->rx_packets += packets;
6473 stats->rx_bytes += bytes;
6474 }
6475 }
6476
6477 for (i = 0; i < adapter->num_tx_queues; i++) {
6478 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6479 u64 bytes, packets;
6480 unsigned int start;
6481
6482 if (ring) {
6483 do {
6484 start = u64_stats_fetch_begin_bh(&ring->syncp);
6485 packets = ring->stats.packets;
6486 bytes = ring->stats.bytes;
6487 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6488 stats->tx_packets += packets;
6489 stats->tx_bytes += bytes;
6490 }
6491 }
6492 rcu_read_unlock();
6493 /* following stats updated by ixgbe_watchdog_task() */
6494 stats->multicast = netdev->stats.multicast;
6495 stats->rx_errors = netdev->stats.rx_errors;
6496 stats->rx_length_errors = netdev->stats.rx_length_errors;
6497 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6498 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6499 return stats;
6500 }
6501
6502 #ifdef CONFIG_IXGBE_DCB
6503 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6504 * #adapter: pointer to ixgbe_adapter
6505 * @tc: number of traffic classes currently enabled
6506 *
6507 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6508 * 802.1Q priority maps to a packet buffer that exists.
6509 */
6510 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6511 {
6512 struct ixgbe_hw *hw = &adapter->hw;
6513 u32 reg, rsave;
6514 int i;
6515
6516 /* 82598 have a static priority to TC mapping that can not
6517 * be changed so no validation is needed.
6518 */
6519 if (hw->mac.type == ixgbe_mac_82598EB)
6520 return;
6521
6522 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6523 rsave = reg;
6524
6525 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6526 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6527
6528 /* If up2tc is out of bounds default to zero */
6529 if (up2tc > tc)
6530 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6531 }
6532
6533 if (reg != rsave)
6534 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6535
6536 return;
6537 }
6538
6539 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
6540 * classes.
6541 *
6542 * @netdev: net device to configure
6543 * @tc: number of traffic classes to enable
6544 */
6545 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6546 {
6547 struct ixgbe_adapter *adapter = netdev_priv(dev);
6548 struct ixgbe_hw *hw = &adapter->hw;
6549
6550 /* Multiple traffic classes requires multiple queues */
6551 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6552 e_err(drv, "Enable failed, needs MSI-X\n");
6553 return -EINVAL;
6554 }
6555
6556 /* Hardware supports up to 8 traffic classes */
6557 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
6558 (hw->mac.type == ixgbe_mac_82598EB &&
6559 tc < MAX_TRAFFIC_CLASS))
6560 return -EINVAL;
6561
6562 /* Hardware has to reinitialize queues and interrupts to
6563 * match packet buffer alignment. Unfortunately, the
6564 * hardware is not flexible enough to do this dynamically.
6565 */
6566 if (netif_running(dev))
6567 ixgbe_close(dev);
6568 ixgbe_clear_interrupt_scheme(adapter);
6569
6570 if (tc) {
6571 netdev_set_num_tc(dev, tc);
6572 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
6573 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
6574 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6575
6576 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6577 adapter->hw.fc.requested_mode = ixgbe_fc_none;
6578 } else {
6579 netdev_reset_tc(dev);
6580 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
6581
6582 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6583 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6584
6585 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6586 adapter->dcb_cfg.pfc_mode_enable = false;
6587 }
6588
6589 ixgbe_init_interrupt_scheme(adapter);
6590 ixgbe_validate_rtr(adapter, tc);
6591 if (netif_running(dev))
6592 ixgbe_open(dev);
6593
6594 return 0;
6595 }
6596
6597 #endif /* CONFIG_IXGBE_DCB */
6598 void ixgbe_do_reset(struct net_device *netdev)
6599 {
6600 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6601
6602 if (netif_running(netdev))
6603 ixgbe_reinit_locked(adapter);
6604 else
6605 ixgbe_reset(adapter);
6606 }
6607
6608 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
6609 netdev_features_t features)
6610 {
6611 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6612
6613 #ifdef CONFIG_DCB
6614 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6615 features &= ~NETIF_F_HW_VLAN_RX;
6616 #endif
6617
6618 /* return error if RXHASH is being enabled when RSS is not supported */
6619 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
6620 features &= ~NETIF_F_RXHASH;
6621
6622 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
6623 if (!(features & NETIF_F_RXCSUM))
6624 features &= ~NETIF_F_LRO;
6625
6626 /* Turn off LRO if not RSC capable */
6627 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6628 features &= ~NETIF_F_LRO;
6629
6630
6631 return features;
6632 }
6633
6634 static int ixgbe_set_features(struct net_device *netdev,
6635 netdev_features_t features)
6636 {
6637 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6638 netdev_features_t changed = netdev->features ^ features;
6639 bool need_reset = false;
6640
6641 /* Make sure RSC matches LRO, reset if change */
6642 if (!(features & NETIF_F_LRO)) {
6643 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6644 need_reset = true;
6645 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6646 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6647 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6648 if (adapter->rx_itr_setting == 1 ||
6649 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6650 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6651 need_reset = true;
6652 } else if ((changed ^ features) & NETIF_F_LRO) {
6653 e_info(probe, "rx-usecs set too low, "
6654 "disabling RSC\n");
6655 }
6656 }
6657
6658 /*
6659 * Check if Flow Director n-tuple support was enabled or disabled. If
6660 * the state changed, we need to reset.
6661 */
6662 if (!(features & NETIF_F_NTUPLE)) {
6663 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
6664 /* turn off Flow Director, set ATR and reset */
6665 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
6666 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
6667 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6668 need_reset = true;
6669 }
6670 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6671 } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
6672 /* turn off ATR, enable perfect filters and reset */
6673 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6674 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6675 need_reset = true;
6676 }
6677
6678 if (changed & NETIF_F_RXALL)
6679 need_reset = true;
6680
6681 netdev->features = features;
6682 if (need_reset)
6683 ixgbe_do_reset(netdev);
6684
6685 return 0;
6686 }
6687
6688 static const struct net_device_ops ixgbe_netdev_ops = {
6689 .ndo_open = ixgbe_open,
6690 .ndo_stop = ixgbe_close,
6691 .ndo_start_xmit = ixgbe_xmit_frame,
6692 .ndo_select_queue = ixgbe_select_queue,
6693 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6694 .ndo_validate_addr = eth_validate_addr,
6695 .ndo_set_mac_address = ixgbe_set_mac,
6696 .ndo_change_mtu = ixgbe_change_mtu,
6697 .ndo_tx_timeout = ixgbe_tx_timeout,
6698 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6699 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6700 .ndo_do_ioctl = ixgbe_ioctl,
6701 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6702 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6703 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6704 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
6705 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6706 .ndo_get_stats64 = ixgbe_get_stats64,
6707 #ifdef CONFIG_IXGBE_DCB
6708 .ndo_setup_tc = ixgbe_setup_tc,
6709 #endif
6710 #ifdef CONFIG_NET_POLL_CONTROLLER
6711 .ndo_poll_controller = ixgbe_netpoll,
6712 #endif
6713 #ifdef IXGBE_FCOE
6714 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6715 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
6716 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6717 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6718 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6719 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6720 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
6721 #endif /* IXGBE_FCOE */
6722 .ndo_set_features = ixgbe_set_features,
6723 .ndo_fix_features = ixgbe_fix_features,
6724 };
6725
6726 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6727 const struct ixgbe_info *ii)
6728 {
6729 #ifdef CONFIG_PCI_IOV
6730 struct ixgbe_hw *hw = &adapter->hw;
6731
6732 if (hw->mac.type == ixgbe_mac_82598EB)
6733 return;
6734
6735 /* The 82599 supports up to 64 VFs per physical function
6736 * but this implementation limits allocation to 63 so that
6737 * basic networking resources are still available to the
6738 * physical function
6739 */
6740 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6741 ixgbe_enable_sriov(adapter, ii);
6742 #endif /* CONFIG_PCI_IOV */
6743 }
6744
6745 /**
6746 * ixgbe_probe - Device Initialization Routine
6747 * @pdev: PCI device information struct
6748 * @ent: entry in ixgbe_pci_tbl
6749 *
6750 * Returns 0 on success, negative on failure
6751 *
6752 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6753 * The OS initialization, configuring of the adapter private structure,
6754 * and a hardware reset occur.
6755 **/
6756 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6757 const struct pci_device_id *ent)
6758 {
6759 struct net_device *netdev;
6760 struct ixgbe_adapter *adapter = NULL;
6761 struct ixgbe_hw *hw;
6762 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6763 static int cards_found;
6764 int i, err, pci_using_dac;
6765 u8 part_str[IXGBE_PBANUM_LENGTH];
6766 unsigned int indices = num_possible_cpus();
6767 #ifdef IXGBE_FCOE
6768 u16 device_caps;
6769 #endif
6770 u32 eec;
6771 u16 wol_cap;
6772
6773 /* Catch broken hardware that put the wrong VF device ID in
6774 * the PCIe SR-IOV capability.
6775 */
6776 if (pdev->is_virtfn) {
6777 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6778 pci_name(pdev), pdev->vendor, pdev->device);
6779 return -EINVAL;
6780 }
6781
6782 err = pci_enable_device_mem(pdev);
6783 if (err)
6784 return err;
6785
6786 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6787 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6788 pci_using_dac = 1;
6789 } else {
6790 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6791 if (err) {
6792 err = dma_set_coherent_mask(&pdev->dev,
6793 DMA_BIT_MASK(32));
6794 if (err) {
6795 dev_err(&pdev->dev,
6796 "No usable DMA configuration, aborting\n");
6797 goto err_dma;
6798 }
6799 }
6800 pci_using_dac = 0;
6801 }
6802
6803 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6804 IORESOURCE_MEM), ixgbe_driver_name);
6805 if (err) {
6806 dev_err(&pdev->dev,
6807 "pci_request_selected_regions failed 0x%x\n", err);
6808 goto err_pci_reg;
6809 }
6810
6811 pci_enable_pcie_error_reporting(pdev);
6812
6813 pci_set_master(pdev);
6814 pci_save_state(pdev);
6815
6816 #ifdef CONFIG_IXGBE_DCB
6817 indices *= MAX_TRAFFIC_CLASS;
6818 #endif
6819
6820 if (ii->mac == ixgbe_mac_82598EB)
6821 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6822 else
6823 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6824
6825 #ifdef IXGBE_FCOE
6826 indices += min_t(unsigned int, num_possible_cpus(),
6827 IXGBE_MAX_FCOE_INDICES);
6828 #endif
6829 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6830 if (!netdev) {
6831 err = -ENOMEM;
6832 goto err_alloc_etherdev;
6833 }
6834
6835 SET_NETDEV_DEV(netdev, &pdev->dev);
6836
6837 adapter = netdev_priv(netdev);
6838 pci_set_drvdata(pdev, adapter);
6839
6840 adapter->netdev = netdev;
6841 adapter->pdev = pdev;
6842 hw = &adapter->hw;
6843 hw->back = adapter;
6844 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
6845
6846 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6847 pci_resource_len(pdev, 0));
6848 if (!hw->hw_addr) {
6849 err = -EIO;
6850 goto err_ioremap;
6851 }
6852
6853 for (i = 1; i <= 5; i++) {
6854 if (pci_resource_len(pdev, i) == 0)
6855 continue;
6856 }
6857
6858 netdev->netdev_ops = &ixgbe_netdev_ops;
6859 ixgbe_set_ethtool_ops(netdev);
6860 netdev->watchdog_timeo = 5 * HZ;
6861 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6862
6863 adapter->bd_number = cards_found;
6864
6865 /* Setup hw api */
6866 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6867 hw->mac.type = ii->mac;
6868
6869 /* EEPROM */
6870 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6871 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6872 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6873 if (!(eec & (1 << 8)))
6874 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6875
6876 /* PHY */
6877 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6878 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6879 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6880 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6881 hw->phy.mdio.mmds = 0;
6882 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6883 hw->phy.mdio.dev = netdev;
6884 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6885 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6886
6887 ii->get_invariants(hw);
6888
6889 /* setup the private structure */
6890 err = ixgbe_sw_init(adapter);
6891 if (err)
6892 goto err_sw_init;
6893
6894 /* Make it possible the adapter to be woken up via WOL */
6895 switch (adapter->hw.mac.type) {
6896 case ixgbe_mac_82599EB:
6897 case ixgbe_mac_X540:
6898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6899 break;
6900 default:
6901 break;
6902 }
6903
6904 /*
6905 * If there is a fan on this device and it has failed log the
6906 * failure.
6907 */
6908 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6909 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6910 if (esdp & IXGBE_ESDP_SDP1)
6911 e_crit(probe, "Fan has stopped, replace the adapter\n");
6912 }
6913
6914 if (allow_unsupported_sfp)
6915 hw->allow_unsupported_sfp = allow_unsupported_sfp;
6916
6917 /* reset_hw fills in the perm_addr as well */
6918 hw->phy.reset_if_overtemp = true;
6919 err = hw->mac.ops.reset_hw(hw);
6920 hw->phy.reset_if_overtemp = false;
6921 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6922 hw->mac.type == ixgbe_mac_82598EB) {
6923 err = 0;
6924 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6925 e_dev_err("failed to load because an unsupported SFP+ "
6926 "module type was detected.\n");
6927 e_dev_err("Reload the driver after installing a supported "
6928 "module.\n");
6929 goto err_sw_init;
6930 } else if (err) {
6931 e_dev_err("HW Init failed: %d\n", err);
6932 goto err_sw_init;
6933 }
6934
6935 ixgbe_probe_vf(adapter, ii);
6936
6937 netdev->features = NETIF_F_SG |
6938 NETIF_F_IP_CSUM |
6939 NETIF_F_IPV6_CSUM |
6940 NETIF_F_HW_VLAN_TX |
6941 NETIF_F_HW_VLAN_RX |
6942 NETIF_F_HW_VLAN_FILTER |
6943 NETIF_F_TSO |
6944 NETIF_F_TSO6 |
6945 NETIF_F_RXHASH |
6946 NETIF_F_RXCSUM;
6947
6948 netdev->hw_features = netdev->features;
6949
6950 switch (adapter->hw.mac.type) {
6951 case ixgbe_mac_82599EB:
6952 case ixgbe_mac_X540:
6953 netdev->features |= NETIF_F_SCTP_CSUM;
6954 netdev->hw_features |= NETIF_F_SCTP_CSUM |
6955 NETIF_F_NTUPLE;
6956 break;
6957 default:
6958 break;
6959 }
6960
6961 netdev->hw_features |= NETIF_F_RXALL;
6962
6963 netdev->vlan_features |= NETIF_F_TSO;
6964 netdev->vlan_features |= NETIF_F_TSO6;
6965 netdev->vlan_features |= NETIF_F_IP_CSUM;
6966 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6967 netdev->vlan_features |= NETIF_F_SG;
6968
6969 netdev->priv_flags |= IFF_UNICAST_FLT;
6970 netdev->priv_flags |= IFF_SUPP_NOFCS;
6971
6972 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6973 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6974 IXGBE_FLAG_DCB_ENABLED);
6975
6976 #ifdef CONFIG_IXGBE_DCB
6977 netdev->dcbnl_ops = &dcbnl_ops;
6978 #endif
6979
6980 #ifdef IXGBE_FCOE
6981 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6982 if (hw->mac.ops.get_device_caps) {
6983 hw->mac.ops.get_device_caps(hw, &device_caps);
6984 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6985 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6986 }
6987 }
6988 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6989 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6990 netdev->vlan_features |= NETIF_F_FSO;
6991 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6992 }
6993 #endif /* IXGBE_FCOE */
6994 if (pci_using_dac) {
6995 netdev->features |= NETIF_F_HIGHDMA;
6996 netdev->vlan_features |= NETIF_F_HIGHDMA;
6997 }
6998
6999 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7000 netdev->hw_features |= NETIF_F_LRO;
7001 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7002 netdev->features |= NETIF_F_LRO;
7003
7004 /* make sure the EEPROM is good */
7005 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7006 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7007 err = -EIO;
7008 goto err_sw_init;
7009 }
7010
7011 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7012 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7013
7014 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7015 e_dev_err("invalid MAC address\n");
7016 err = -EIO;
7017 goto err_sw_init;
7018 }
7019
7020 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7021 (unsigned long) adapter);
7022
7023 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7024 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7025
7026 err = ixgbe_init_interrupt_scheme(adapter);
7027 if (err)
7028 goto err_sw_init;
7029
7030 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7031 netdev->hw_features &= ~NETIF_F_RXHASH;
7032 netdev->features &= ~NETIF_F_RXHASH;
7033 }
7034
7035 /* WOL not supported for all but the following */
7036 adapter->wol = 0;
7037 switch (pdev->device) {
7038 case IXGBE_DEV_ID_82599_SFP:
7039 /* Only these subdevice supports WOL */
7040 switch (pdev->subsystem_device) {
7041 case IXGBE_SUBDEV_ID_82599_560FLR:
7042 /* only support first port */
7043 if (hw->bus.func != 0)
7044 break;
7045 case IXGBE_SUBDEV_ID_82599_SFP:
7046 adapter->wol = IXGBE_WUFC_MAG;
7047 break;
7048 }
7049 break;
7050 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7051 /* All except this subdevice support WOL */
7052 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7053 adapter->wol = IXGBE_WUFC_MAG;
7054 break;
7055 case IXGBE_DEV_ID_82599_KX4:
7056 adapter->wol = IXGBE_WUFC_MAG;
7057 break;
7058 case IXGBE_DEV_ID_X540T:
7059 /* Check eeprom to see if it is enabled */
7060 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7061 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7062
7063 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7064 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7065 (hw->bus.func == 0)))
7066 adapter->wol = IXGBE_WUFC_MAG;
7067 break;
7068 }
7069 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7070
7071 /* save off EEPROM version number */
7072 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7073 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7074
7075 /* pick up the PCI bus settings for reporting later */
7076 hw->mac.ops.get_bus_info(hw);
7077
7078 /* print bus type/speed/width info */
7079 e_dev_info("(PCI Express:%s:%s) %pM\n",
7080 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7081 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7082 "Unknown"),
7083 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7084 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7085 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7086 "Unknown"),
7087 netdev->dev_addr);
7088
7089 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7090 if (err)
7091 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7092 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7093 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7094 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7095 part_str);
7096 else
7097 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7098 hw->mac.type, hw->phy.type, part_str);
7099
7100 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7101 e_dev_warn("PCI-Express bandwidth available for this card is "
7102 "not sufficient for optimal performance.\n");
7103 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7104 "is required.\n");
7105 }
7106
7107 /* reset the hardware with the new settings */
7108 err = hw->mac.ops.start_hw(hw);
7109 if (err == IXGBE_ERR_EEPROM_VERSION) {
7110 /* We are running on a pre-production device, log a warning */
7111 e_dev_warn("This device is a pre-production adapter/LOM. "
7112 "Please be aware there may be issues associated "
7113 "with your hardware. If you are experiencing "
7114 "problems please contact your Intel or hardware "
7115 "representative who provided you with this "
7116 "hardware.\n");
7117 }
7118 strcpy(netdev->name, "eth%d");
7119 err = register_netdev(netdev);
7120 if (err)
7121 goto err_register;
7122
7123 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7124 if (hw->mac.ops.disable_tx_laser &&
7125 ((hw->phy.multispeed_fiber) ||
7126 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7127 (hw->mac.type == ixgbe_mac_82599EB))))
7128 hw->mac.ops.disable_tx_laser(hw);
7129
7130 /* carrier off reporting is important to ethtool even BEFORE open */
7131 netif_carrier_off(netdev);
7132
7133 #ifdef CONFIG_IXGBE_DCA
7134 if (dca_add_requester(&pdev->dev) == 0) {
7135 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7136 ixgbe_setup_dca(adapter);
7137 }
7138 #endif
7139 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7140 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7141 for (i = 0; i < adapter->num_vfs; i++)
7142 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7143 }
7144
7145 /* firmware requires driver version to be 0xFFFFFFFF
7146 * since os does not support feature
7147 */
7148 if (hw->mac.ops.set_fw_drv_ver)
7149 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7150 0xFF);
7151
7152 /* add san mac addr to netdev */
7153 ixgbe_add_sanmac_netdev(netdev);
7154
7155 e_dev_info("%s\n", ixgbe_default_device_descr);
7156 cards_found++;
7157 return 0;
7158
7159 err_register:
7160 ixgbe_release_hw_control(adapter);
7161 ixgbe_clear_interrupt_scheme(adapter);
7162 err_sw_init:
7163 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7164 ixgbe_disable_sriov(adapter);
7165 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7166 iounmap(hw->hw_addr);
7167 err_ioremap:
7168 free_netdev(netdev);
7169 err_alloc_etherdev:
7170 pci_release_selected_regions(pdev,
7171 pci_select_bars(pdev, IORESOURCE_MEM));
7172 err_pci_reg:
7173 err_dma:
7174 pci_disable_device(pdev);
7175 return err;
7176 }
7177
7178 /**
7179 * ixgbe_remove - Device Removal Routine
7180 * @pdev: PCI device information struct
7181 *
7182 * ixgbe_remove is called by the PCI subsystem to alert the driver
7183 * that it should release a PCI device. The could be caused by a
7184 * Hot-Plug event, or because the driver is going to be removed from
7185 * memory.
7186 **/
7187 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7188 {
7189 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7190 struct net_device *netdev = adapter->netdev;
7191
7192 set_bit(__IXGBE_DOWN, &adapter->state);
7193 cancel_work_sync(&adapter->service_task);
7194
7195 #ifdef CONFIG_IXGBE_DCA
7196 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7197 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7198 dca_remove_requester(&pdev->dev);
7199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7200 }
7201
7202 #endif
7203 #ifdef IXGBE_FCOE
7204 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7205 ixgbe_cleanup_fcoe(adapter);
7206
7207 #endif /* IXGBE_FCOE */
7208
7209 /* remove the added san mac */
7210 ixgbe_del_sanmac_netdev(netdev);
7211
7212 if (netdev->reg_state == NETREG_REGISTERED)
7213 unregister_netdev(netdev);
7214
7215 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7216 if (!(ixgbe_check_vf_assignment(adapter)))
7217 ixgbe_disable_sriov(adapter);
7218 else
7219 e_dev_warn("Unloading driver while VFs are assigned "
7220 "- VFs will not be deallocated\n");
7221 }
7222
7223 ixgbe_clear_interrupt_scheme(adapter);
7224
7225 ixgbe_release_hw_control(adapter);
7226
7227 iounmap(adapter->hw.hw_addr);
7228 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7229 IORESOURCE_MEM));
7230
7231 e_dev_info("complete\n");
7232
7233 free_netdev(netdev);
7234
7235 pci_disable_pcie_error_reporting(pdev);
7236
7237 pci_disable_device(pdev);
7238 }
7239
7240 /**
7241 * ixgbe_io_error_detected - called when PCI error is detected
7242 * @pdev: Pointer to PCI device
7243 * @state: The current pci connection state
7244 *
7245 * This function is called after a PCI bus error affecting
7246 * this device has been detected.
7247 */
7248 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7249 pci_channel_state_t state)
7250 {
7251 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7252 struct net_device *netdev = adapter->netdev;
7253
7254 #ifdef CONFIG_PCI_IOV
7255 struct pci_dev *bdev, *vfdev;
7256 u32 dw0, dw1, dw2, dw3;
7257 int vf, pos;
7258 u16 req_id, pf_func;
7259
7260 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7261 adapter->num_vfs == 0)
7262 goto skip_bad_vf_detection;
7263
7264 bdev = pdev->bus->self;
7265 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7266 bdev = bdev->bus->self;
7267
7268 if (!bdev)
7269 goto skip_bad_vf_detection;
7270
7271 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7272 if (!pos)
7273 goto skip_bad_vf_detection;
7274
7275 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7276 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7277 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7278 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7279
7280 req_id = dw1 >> 16;
7281 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7282 if (!(req_id & 0x0080))
7283 goto skip_bad_vf_detection;
7284
7285 pf_func = req_id & 0x01;
7286 if ((pf_func & 1) == (pdev->devfn & 1)) {
7287 unsigned int device_id;
7288
7289 vf = (req_id & 0x7F) >> 1;
7290 e_dev_err("VF %d has caused a PCIe error\n", vf);
7291 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7292 "%8.8x\tdw3: %8.8x\n",
7293 dw0, dw1, dw2, dw3);
7294 switch (adapter->hw.mac.type) {
7295 case ixgbe_mac_82599EB:
7296 device_id = IXGBE_82599_VF_DEVICE_ID;
7297 break;
7298 case ixgbe_mac_X540:
7299 device_id = IXGBE_X540_VF_DEVICE_ID;
7300 break;
7301 default:
7302 device_id = 0;
7303 break;
7304 }
7305
7306 /* Find the pci device of the offending VF */
7307 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7308 while (vfdev) {
7309 if (vfdev->devfn == (req_id & 0xFF))
7310 break;
7311 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7312 device_id, vfdev);
7313 }
7314 /*
7315 * There's a slim chance the VF could have been hot plugged,
7316 * so if it is no longer present we don't need to issue the
7317 * VFLR. Just clean up the AER in that case.
7318 */
7319 if (vfdev) {
7320 e_dev_err("Issuing VFLR to VF %d\n", vf);
7321 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7322 }
7323
7324 pci_cleanup_aer_uncorrect_error_status(pdev);
7325 }
7326
7327 /*
7328 * Even though the error may have occurred on the other port
7329 * we still need to increment the vf error reference count for
7330 * both ports because the I/O resume function will be called
7331 * for both of them.
7332 */
7333 adapter->vferr_refcount++;
7334
7335 return PCI_ERS_RESULT_RECOVERED;
7336
7337 skip_bad_vf_detection:
7338 #endif /* CONFIG_PCI_IOV */
7339 netif_device_detach(netdev);
7340
7341 if (state == pci_channel_io_perm_failure)
7342 return PCI_ERS_RESULT_DISCONNECT;
7343
7344 if (netif_running(netdev))
7345 ixgbe_down(adapter);
7346 pci_disable_device(pdev);
7347
7348 /* Request a slot reset. */
7349 return PCI_ERS_RESULT_NEED_RESET;
7350 }
7351
7352 /**
7353 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7354 * @pdev: Pointer to PCI device
7355 *
7356 * Restart the card from scratch, as if from a cold-boot.
7357 */
7358 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7359 {
7360 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7361 pci_ers_result_t result;
7362 int err;
7363
7364 if (pci_enable_device_mem(pdev)) {
7365 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7366 result = PCI_ERS_RESULT_DISCONNECT;
7367 } else {
7368 pci_set_master(pdev);
7369 pci_restore_state(pdev);
7370 pci_save_state(pdev);
7371
7372 pci_wake_from_d3(pdev, false);
7373
7374 ixgbe_reset(adapter);
7375 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7376 result = PCI_ERS_RESULT_RECOVERED;
7377 }
7378
7379 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7380 if (err) {
7381 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7382 "failed 0x%0x\n", err);
7383 /* non-fatal, continue */
7384 }
7385
7386 return result;
7387 }
7388
7389 /**
7390 * ixgbe_io_resume - called when traffic can start flowing again.
7391 * @pdev: Pointer to PCI device
7392 *
7393 * This callback is called when the error recovery driver tells us that
7394 * its OK to resume normal operation.
7395 */
7396 static void ixgbe_io_resume(struct pci_dev *pdev)
7397 {
7398 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7399 struct net_device *netdev = adapter->netdev;
7400
7401 #ifdef CONFIG_PCI_IOV
7402 if (adapter->vferr_refcount) {
7403 e_info(drv, "Resuming after VF err\n");
7404 adapter->vferr_refcount--;
7405 return;
7406 }
7407
7408 #endif
7409 if (netif_running(netdev))
7410 ixgbe_up(adapter);
7411
7412 netif_device_attach(netdev);
7413 }
7414
7415 static struct pci_error_handlers ixgbe_err_handler = {
7416 .error_detected = ixgbe_io_error_detected,
7417 .slot_reset = ixgbe_io_slot_reset,
7418 .resume = ixgbe_io_resume,
7419 };
7420
7421 static struct pci_driver ixgbe_driver = {
7422 .name = ixgbe_driver_name,
7423 .id_table = ixgbe_pci_tbl,
7424 .probe = ixgbe_probe,
7425 .remove = __devexit_p(ixgbe_remove),
7426 #ifdef CONFIG_PM
7427 .suspend = ixgbe_suspend,
7428 .resume = ixgbe_resume,
7429 #endif
7430 .shutdown = ixgbe_shutdown,
7431 .err_handler = &ixgbe_err_handler
7432 };
7433
7434 /**
7435 * ixgbe_init_module - Driver Registration Routine
7436 *
7437 * ixgbe_init_module is the first routine called when the driver is
7438 * loaded. All it does is register with the PCI subsystem.
7439 **/
7440 static int __init ixgbe_init_module(void)
7441 {
7442 int ret;
7443 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7444 pr_info("%s\n", ixgbe_copyright);
7445
7446 #ifdef CONFIG_IXGBE_DCA
7447 dca_register_notify(&dca_notifier);
7448 #endif
7449
7450 ret = pci_register_driver(&ixgbe_driver);
7451 return ret;
7452 }
7453
7454 module_init(ixgbe_init_module);
7455
7456 /**
7457 * ixgbe_exit_module - Driver Exit Cleanup Routine
7458 *
7459 * ixgbe_exit_module is called just before the driver is removed
7460 * from memory.
7461 **/
7462 static void __exit ixgbe_exit_module(void)
7463 {
7464 #ifdef CONFIG_IXGBE_DCA
7465 dca_unregister_notify(&dca_notifier);
7466 #endif
7467 pci_unregister_driver(&ixgbe_driver);
7468 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7469 }
7470
7471 #ifdef CONFIG_IXGBE_DCA
7472 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7473 void *p)
7474 {
7475 int ret_val;
7476
7477 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7478 __ixgbe_notify_dca);
7479
7480 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7481 }
7482
7483 #endif /* CONFIG_IXGBE_DCA */
7484
7485 module_exit(ixgbe_exit_module);
7486
7487 /* ixgbe_main.c */
Linux kernel - Deliverables
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