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ixgbe: Delete redundant include file
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2015 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/types.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/vmalloc.h>
34 #include <linux/string.h>
35 #include <linux/in.h>
36 #include <linux/interrupt.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/sctp.h>
40 #include <linux/pkt_sched.h>
41 #include <linux/ipv6.h>
42 #include <linux/slab.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/etherdevice.h>
46 #include <linux/ethtool.h>
47 #include <linux/if.h>
48 #include <linux/if_vlan.h>
49 #include <linux/if_macvlan.h>
50 #include <linux/if_bridge.h>
51 #include <linux/prefetch.h>
52 #include <scsi/fc/fc_fcoe.h>
53 #include <net/vxlan.h>
54
55 #ifdef CONFIG_OF
56 #include <linux/of_net.h>
57 #endif
58
59 #ifdef CONFIG_SPARC
60 #include <asm/idprom.h>
61 #include <asm/prom.h>
62 #endif
63
64 #include "ixgbe.h"
65 #include "ixgbe_common.h"
66 #include "ixgbe_dcb_82599.h"
67 #include "ixgbe_sriov.h"
68
69 char ixgbe_driver_name[] = "ixgbe";
70 static const char ixgbe_driver_string[] =
71 "Intel(R) 10 Gigabit PCI Express Network Driver";
72 #ifdef IXGBE_FCOE
73 char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
75 #else
76 static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78 #endif
79 #define DRV_VERSION "4.2.1-k"
80 const char ixgbe_driver_version[] = DRV_VERSION;
81 static const char ixgbe_copyright[] =
82 "Copyright (c) 1999-2015 Intel Corporation.";
83
84 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
85
86 static const struct ixgbe_info *ixgbe_info_tbl[] = {
87 [board_82598] = &ixgbe_82598_info,
88 [board_82599] = &ixgbe_82599_info,
89 [board_X540] = &ixgbe_X540_info,
90 [board_X550] = &ixgbe_X550_info,
91 [board_X550EM_x] = &ixgbe_X550EM_x_info,
92 };
93
94 /* ixgbe_pci_tbl - PCI Device ID Table
95 *
96 * Wildcard entries (PCI_ANY_ID) should come last
97 * Last entry must be all 0s
98 *
99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
100 * Class, Class Mask, private data (not used) }
101 */
102 static const struct pci_device_id ixgbe_pci_tbl[] = {
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
138 /* required last entry */
139 {0, }
140 };
141 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
142
143 #ifdef CONFIG_IXGBE_DCA
144 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
145 void *p);
146 static struct notifier_block dca_notifier = {
147 .notifier_call = ixgbe_notify_dca,
148 .next = NULL,
149 .priority = 0
150 };
151 #endif
152
153 #ifdef CONFIG_PCI_IOV
154 static unsigned int max_vfs;
155 module_param(max_vfs, uint, 0);
156 MODULE_PARM_DESC(max_vfs,
157 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
158 #endif /* CONFIG_PCI_IOV */
159
160 static unsigned int allow_unsupported_sfp;
161 module_param(allow_unsupported_sfp, uint, 0);
162 MODULE_PARM_DESC(allow_unsupported_sfp,
163 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
164
165 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
166 static int debug = -1;
167 module_param(debug, int, 0);
168 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
169
170 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
171 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
172 MODULE_LICENSE("GPL");
173 MODULE_VERSION(DRV_VERSION);
174
175 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
176
177 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
178 u32 reg, u16 *value)
179 {
180 struct pci_dev *parent_dev;
181 struct pci_bus *parent_bus;
182
183 parent_bus = adapter->pdev->bus->parent;
184 if (!parent_bus)
185 return -1;
186
187 parent_dev = parent_bus->self;
188 if (!parent_dev)
189 return -1;
190
191 if (!pci_is_pcie(parent_dev))
192 return -1;
193
194 pcie_capability_read_word(parent_dev, reg, value);
195 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
196 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
197 return -1;
198 return 0;
199 }
200
201 static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
202 {
203 struct ixgbe_hw *hw = &adapter->hw;
204 u16 link_status = 0;
205 int err;
206
207 hw->bus.type = ixgbe_bus_type_pci_express;
208
209 /* Get the negotiated link width and speed from PCI config space of the
210 * parent, as this device is behind a switch
211 */
212 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
213
214 /* assume caller will handle error case */
215 if (err)
216 return err;
217
218 hw->bus.width = ixgbe_convert_bus_width(link_status);
219 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
220
221 return 0;
222 }
223
224 /**
225 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
226 * @hw: hw specific details
227 *
228 * This function is used by probe to determine whether a device's PCI-Express
229 * bandwidth details should be gathered from the parent bus instead of from the
230 * device. Used to ensure that various locations all have the correct device ID
231 * checks.
232 */
233 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
234 {
235 switch (hw->device_id) {
236 case IXGBE_DEV_ID_82599_SFP_SF_QP:
237 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
238 return true;
239 default:
240 return false;
241 }
242 }
243
244 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
245 int expected_gts)
246 {
247 struct ixgbe_hw *hw = &adapter->hw;
248 int max_gts = 0;
249 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
250 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
251 struct pci_dev *pdev;
252
253 /* Some devices are not connected over PCIe and thus do not negotiate
254 * speed. These devices do not have valid bus info, and thus any report
255 * we generate may not be correct.
256 */
257 if (hw->bus.type == ixgbe_bus_type_internal)
258 return;
259
260 /* determine whether to use the parent device */
261 if (ixgbe_pcie_from_parent(&adapter->hw))
262 pdev = adapter->pdev->bus->parent->self;
263 else
264 pdev = adapter->pdev;
265
266 if (pcie_get_minimum_link(pdev, &speed, &width) ||
267 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
268 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
269 return;
270 }
271
272 switch (speed) {
273 case PCIE_SPEED_2_5GT:
274 /* 8b/10b encoding reduces max throughput by 20% */
275 max_gts = 2 * width;
276 break;
277 case PCIE_SPEED_5_0GT:
278 /* 8b/10b encoding reduces max throughput by 20% */
279 max_gts = 4 * width;
280 break;
281 case PCIE_SPEED_8_0GT:
282 /* 128b/130b encoding reduces throughput by less than 2% */
283 max_gts = 8 * width;
284 break;
285 default:
286 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
287 return;
288 }
289
290 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
291 max_gts);
292 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
293 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
294 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
295 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
296 "Unknown"),
297 width,
298 (speed == PCIE_SPEED_2_5GT ? "20%" :
299 speed == PCIE_SPEED_5_0GT ? "20%" :
300 speed == PCIE_SPEED_8_0GT ? "<2%" :
301 "Unknown"));
302
303 if (max_gts < expected_gts) {
304 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
305 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
306 expected_gts);
307 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
308 }
309 }
310
311 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
312 {
313 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
314 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
315 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
316 schedule_work(&adapter->service_task);
317 }
318
319 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
320 {
321 struct ixgbe_adapter *adapter = hw->back;
322
323 if (!hw->hw_addr)
324 return;
325 hw->hw_addr = NULL;
326 e_dev_err("Adapter removed\n");
327 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
328 ixgbe_service_event_schedule(adapter);
329 }
330
331 static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
332 {
333 u32 value;
334
335 /* The following check not only optimizes a bit by not
336 * performing a read on the status register when the
337 * register just read was a status register read that
338 * returned IXGBE_FAILED_READ_REG. It also blocks any
339 * potential recursion.
340 */
341 if (reg == IXGBE_STATUS) {
342 ixgbe_remove_adapter(hw);
343 return;
344 }
345 value = ixgbe_read_reg(hw, IXGBE_STATUS);
346 if (value == IXGBE_FAILED_READ_REG)
347 ixgbe_remove_adapter(hw);
348 }
349
350 /**
351 * ixgbe_read_reg - Read from device register
352 * @hw: hw specific details
353 * @reg: offset of register to read
354 *
355 * Returns : value read or IXGBE_FAILED_READ_REG if removed
356 *
357 * This function is used to read device registers. It checks for device
358 * removal by confirming any read that returns all ones by checking the
359 * status register value for all ones. This function avoids reading from
360 * the hardware if a removal was previously detected in which case it
361 * returns IXGBE_FAILED_READ_REG (all ones).
362 */
363 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
364 {
365 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
366 u32 value;
367
368 if (ixgbe_removed(reg_addr))
369 return IXGBE_FAILED_READ_REG;
370 value = readl(reg_addr + reg);
371 if (unlikely(value == IXGBE_FAILED_READ_REG))
372 ixgbe_check_remove(hw, reg);
373 return value;
374 }
375
376 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
377 {
378 u16 value;
379
380 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
381 if (value == IXGBE_FAILED_READ_CFG_WORD) {
382 ixgbe_remove_adapter(hw);
383 return true;
384 }
385 return false;
386 }
387
388 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
389 {
390 struct ixgbe_adapter *adapter = hw->back;
391 u16 value;
392
393 if (ixgbe_removed(hw->hw_addr))
394 return IXGBE_FAILED_READ_CFG_WORD;
395 pci_read_config_word(adapter->pdev, reg, &value);
396 if (value == IXGBE_FAILED_READ_CFG_WORD &&
397 ixgbe_check_cfg_remove(hw, adapter->pdev))
398 return IXGBE_FAILED_READ_CFG_WORD;
399 return value;
400 }
401
402 #ifdef CONFIG_PCI_IOV
403 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
404 {
405 struct ixgbe_adapter *adapter = hw->back;
406 u32 value;
407
408 if (ixgbe_removed(hw->hw_addr))
409 return IXGBE_FAILED_READ_CFG_DWORD;
410 pci_read_config_dword(adapter->pdev, reg, &value);
411 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
412 ixgbe_check_cfg_remove(hw, adapter->pdev))
413 return IXGBE_FAILED_READ_CFG_DWORD;
414 return value;
415 }
416 #endif /* CONFIG_PCI_IOV */
417
418 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
419 {
420 struct ixgbe_adapter *adapter = hw->back;
421
422 if (ixgbe_removed(hw->hw_addr))
423 return;
424 pci_write_config_word(adapter->pdev, reg, value);
425 }
426
427 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
428 {
429 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
430
431 /* flush memory to make sure state is correct before next watchdog */
432 smp_mb__before_atomic();
433 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
434 }
435
436 struct ixgbe_reg_info {
437 u32 ofs;
438 char *name;
439 };
440
441 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
442
443 /* General Registers */
444 {IXGBE_CTRL, "CTRL"},
445 {IXGBE_STATUS, "STATUS"},
446 {IXGBE_CTRL_EXT, "CTRL_EXT"},
447
448 /* Interrupt Registers */
449 {IXGBE_EICR, "EICR"},
450
451 /* RX Registers */
452 {IXGBE_SRRCTL(0), "SRRCTL"},
453 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
454 {IXGBE_RDLEN(0), "RDLEN"},
455 {IXGBE_RDH(0), "RDH"},
456 {IXGBE_RDT(0), "RDT"},
457 {IXGBE_RXDCTL(0), "RXDCTL"},
458 {IXGBE_RDBAL(0), "RDBAL"},
459 {IXGBE_RDBAH(0), "RDBAH"},
460
461 /* TX Registers */
462 {IXGBE_TDBAL(0), "TDBAL"},
463 {IXGBE_TDBAH(0), "TDBAH"},
464 {IXGBE_TDLEN(0), "TDLEN"},
465 {IXGBE_TDH(0), "TDH"},
466 {IXGBE_TDT(0), "TDT"},
467 {IXGBE_TXDCTL(0), "TXDCTL"},
468
469 /* List Terminator */
470 { .name = NULL }
471 };
472
473
474 /*
475 * ixgbe_regdump - register printout routine
476 */
477 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
478 {
479 int i = 0, j = 0;
480 char rname[16];
481 u32 regs[64];
482
483 switch (reginfo->ofs) {
484 case IXGBE_SRRCTL(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
487 break;
488 case IXGBE_DCA_RXCTRL(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
491 break;
492 case IXGBE_RDLEN(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
495 break;
496 case IXGBE_RDH(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
499 break;
500 case IXGBE_RDT(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
503 break;
504 case IXGBE_RXDCTL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
507 break;
508 case IXGBE_RDBAL(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
511 break;
512 case IXGBE_RDBAH(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
515 break;
516 case IXGBE_TDBAL(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
519 break;
520 case IXGBE_TDBAH(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
523 break;
524 case IXGBE_TDLEN(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
527 break;
528 case IXGBE_TDH(0):
529 for (i = 0; i < 64; i++)
530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
531 break;
532 case IXGBE_TDT(0):
533 for (i = 0; i < 64; i++)
534 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
535 break;
536 case IXGBE_TXDCTL(0):
537 for (i = 0; i < 64; i++)
538 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
539 break;
540 default:
541 pr_info("%-15s %08x\n", reginfo->name,
542 IXGBE_READ_REG(hw, reginfo->ofs));
543 return;
544 }
545
546 for (i = 0; i < 8; i++) {
547 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
548 pr_err("%-15s", rname);
549 for (j = 0; j < 8; j++)
550 pr_cont(" %08x", regs[i*8+j]);
551 pr_cont("\n");
552 }
553
554 }
555
556 /*
557 * ixgbe_dump - Print registers, tx-rings and rx-rings
558 */
559 static void ixgbe_dump(struct ixgbe_adapter *adapter)
560 {
561 struct net_device *netdev = adapter->netdev;
562 struct ixgbe_hw *hw = &adapter->hw;
563 struct ixgbe_reg_info *reginfo;
564 int n = 0;
565 struct ixgbe_ring *tx_ring;
566 struct ixgbe_tx_buffer *tx_buffer;
567 union ixgbe_adv_tx_desc *tx_desc;
568 struct my_u0 { u64 a; u64 b; } *u0;
569 struct ixgbe_ring *rx_ring;
570 union ixgbe_adv_rx_desc *rx_desc;
571 struct ixgbe_rx_buffer *rx_buffer_info;
572 u32 staterr;
573 int i = 0;
574
575 if (!netif_msg_hw(adapter))
576 return;
577
578 /* Print netdevice Info */
579 if (netdev) {
580 dev_info(&adapter->pdev->dev, "Net device Info\n");
581 pr_info("Device Name state "
582 "trans_start last_rx\n");
583 pr_info("%-15s %016lX %016lX %016lX\n",
584 netdev->name,
585 netdev->state,
586 netdev->trans_start,
587 netdev->last_rx);
588 }
589
590 /* Print Registers */
591 dev_info(&adapter->pdev->dev, "Register Dump\n");
592 pr_info(" Register Name Value\n");
593 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
594 reginfo->name; reginfo++) {
595 ixgbe_regdump(hw, reginfo);
596 }
597
598 /* Print TX Ring Summary */
599 if (!netdev || !netif_running(netdev))
600 return;
601
602 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
603 pr_info(" %s %s %s %s\n",
604 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
605 "leng", "ntw", "timestamp");
606 for (n = 0; n < adapter->num_tx_queues; n++) {
607 tx_ring = adapter->tx_ring[n];
608 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
609 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
610 n, tx_ring->next_to_use, tx_ring->next_to_clean,
611 (u64)dma_unmap_addr(tx_buffer, dma),
612 dma_unmap_len(tx_buffer, len),
613 tx_buffer->next_to_watch,
614 (u64)tx_buffer->time_stamp);
615 }
616
617 /* Print TX Rings */
618 if (!netif_msg_tx_done(adapter))
619 goto rx_ring_summary;
620
621 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
622
623 /* Transmit Descriptor Formats
624 *
625 * 82598 Advanced Transmit Descriptor
626 * +--------------------------------------------------------------+
627 * 0 | Buffer Address [63:0] |
628 * +--------------------------------------------------------------+
629 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
630 * +--------------------------------------------------------------+
631 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
632 *
633 * 82598 Advanced Transmit Descriptor (Write-Back Format)
634 * +--------------------------------------------------------------+
635 * 0 | RSV [63:0] |
636 * +--------------------------------------------------------------+
637 * 8 | RSV | STA | NXTSEQ |
638 * +--------------------------------------------------------------+
639 * 63 36 35 32 31 0
640 *
641 * 82599+ Advanced Transmit Descriptor
642 * +--------------------------------------------------------------+
643 * 0 | Buffer Address [63:0] |
644 * +--------------------------------------------------------------+
645 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
646 * +--------------------------------------------------------------+
647 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
648 *
649 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
650 * +--------------------------------------------------------------+
651 * 0 | RSV [63:0] |
652 * +--------------------------------------------------------------+
653 * 8 | RSV | STA | RSV |
654 * +--------------------------------------------------------------+
655 * 63 36 35 32 31 0
656 */
657
658 for (n = 0; n < adapter->num_tx_queues; n++) {
659 tx_ring = adapter->tx_ring[n];
660 pr_info("------------------------------------\n");
661 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
662 pr_info("------------------------------------\n");
663 pr_info("%s%s %s %s %s %s\n",
664 "T [desc] [address 63:0 ] ",
665 "[PlPOIdStDDt Ln] [bi->dma ] ",
666 "leng", "ntw", "timestamp", "bi->skb");
667
668 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
669 tx_desc = IXGBE_TX_DESC(tx_ring, i);
670 tx_buffer = &tx_ring->tx_buffer_info[i];
671 u0 = (struct my_u0 *)tx_desc;
672 if (dma_unmap_len(tx_buffer, len) > 0) {
673 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
674 i,
675 le64_to_cpu(u0->a),
676 le64_to_cpu(u0->b),
677 (u64)dma_unmap_addr(tx_buffer, dma),
678 dma_unmap_len(tx_buffer, len),
679 tx_buffer->next_to_watch,
680 (u64)tx_buffer->time_stamp,
681 tx_buffer->skb);
682 if (i == tx_ring->next_to_use &&
683 i == tx_ring->next_to_clean)
684 pr_cont(" NTC/U\n");
685 else if (i == tx_ring->next_to_use)
686 pr_cont(" NTU\n");
687 else if (i == tx_ring->next_to_clean)
688 pr_cont(" NTC\n");
689 else
690 pr_cont("\n");
691
692 if (netif_msg_pktdata(adapter) &&
693 tx_buffer->skb)
694 print_hex_dump(KERN_INFO, "",
695 DUMP_PREFIX_ADDRESS, 16, 1,
696 tx_buffer->skb->data,
697 dma_unmap_len(tx_buffer, len),
698 true);
699 }
700 }
701 }
702
703 /* Print RX Rings Summary */
704 rx_ring_summary:
705 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
706 pr_info("Queue [NTU] [NTC]\n");
707 for (n = 0; n < adapter->num_rx_queues; n++) {
708 rx_ring = adapter->rx_ring[n];
709 pr_info("%5d %5X %5X\n",
710 n, rx_ring->next_to_use, rx_ring->next_to_clean);
711 }
712
713 /* Print RX Rings */
714 if (!netif_msg_rx_status(adapter))
715 return;
716
717 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
718
719 /* Receive Descriptor Formats
720 *
721 * 82598 Advanced Receive Descriptor (Read) Format
722 * 63 1 0
723 * +-----------------------------------------------------+
724 * 0 | Packet Buffer Address [63:1] |A0/NSE|
725 * +----------------------------------------------+------+
726 * 8 | Header Buffer Address [63:1] | DD |
727 * +-----------------------------------------------------+
728 *
729 *
730 * 82598 Advanced Receive Descriptor (Write-Back) Format
731 *
732 * 63 48 47 32 31 30 21 20 16 15 4 3 0
733 * +------------------------------------------------------+
734 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
735 * | Packet | IP | | | | Type | Type |
736 * | Checksum | Ident | | | | | |
737 * +------------------------------------------------------+
738 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
739 * +------------------------------------------------------+
740 * 63 48 47 32 31 20 19 0
741 *
742 * 82599+ Advanced Receive Descriptor (Read) Format
743 * 63 1 0
744 * +-----------------------------------------------------+
745 * 0 | Packet Buffer Address [63:1] |A0/NSE|
746 * +----------------------------------------------+------+
747 * 8 | Header Buffer Address [63:1] | DD |
748 * +-----------------------------------------------------+
749 *
750 *
751 * 82599+ Advanced Receive Descriptor (Write-Back) Format
752 *
753 * 63 48 47 32 31 30 21 20 17 16 4 3 0
754 * +------------------------------------------------------+
755 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
756 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
757 * |/ Flow Dir Flt ID | | | | | |
758 * +------------------------------------------------------+
759 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
760 * +------------------------------------------------------+
761 * 63 48 47 32 31 20 19 0
762 */
763
764 for (n = 0; n < adapter->num_rx_queues; n++) {
765 rx_ring = adapter->rx_ring[n];
766 pr_info("------------------------------------\n");
767 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
768 pr_info("------------------------------------\n");
769 pr_info("%s%s%s",
770 "R [desc] [ PktBuf A0] ",
771 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
772 "<-- Adv Rx Read format\n");
773 pr_info("%s%s%s",
774 "RWB[desc] [PcsmIpSHl PtRs] ",
775 "[vl er S cks ln] ---------------- [bi->skb ] ",
776 "<-- Adv Rx Write-Back format\n");
777
778 for (i = 0; i < rx_ring->count; i++) {
779 rx_buffer_info = &rx_ring->rx_buffer_info[i];
780 rx_desc = IXGBE_RX_DESC(rx_ring, i);
781 u0 = (struct my_u0 *)rx_desc;
782 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
783 if (staterr & IXGBE_RXD_STAT_DD) {
784 /* Descriptor Done */
785 pr_info("RWB[0x%03X] %016llX "
786 "%016llX ---------------- %p", i,
787 le64_to_cpu(u0->a),
788 le64_to_cpu(u0->b),
789 rx_buffer_info->skb);
790 } else {
791 pr_info("R [0x%03X] %016llX "
792 "%016llX %016llX %p", i,
793 le64_to_cpu(u0->a),
794 le64_to_cpu(u0->b),
795 (u64)rx_buffer_info->dma,
796 rx_buffer_info->skb);
797
798 if (netif_msg_pktdata(adapter) &&
799 rx_buffer_info->dma) {
800 print_hex_dump(KERN_INFO, "",
801 DUMP_PREFIX_ADDRESS, 16, 1,
802 page_address(rx_buffer_info->page) +
803 rx_buffer_info->page_offset,
804 ixgbe_rx_bufsz(rx_ring), true);
805 }
806 }
807
808 if (i == rx_ring->next_to_use)
809 pr_cont(" NTU\n");
810 else if (i == rx_ring->next_to_clean)
811 pr_cont(" NTC\n");
812 else
813 pr_cont("\n");
814
815 }
816 }
817 }
818
819 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
820 {
821 u32 ctrl_ext;
822
823 /* Let firmware take over control of h/w */
824 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
826 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
827 }
828
829 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
830 {
831 u32 ctrl_ext;
832
833 /* Let firmware know the driver has taken over */
834 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
836 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
837 }
838
839 /**
840 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
841 * @adapter: pointer to adapter struct
842 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
843 * @queue: queue to map the corresponding interrupt to
844 * @msix_vector: the vector to map to the corresponding queue
845 *
846 */
847 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
848 u8 queue, u8 msix_vector)
849 {
850 u32 ivar, index;
851 struct ixgbe_hw *hw = &adapter->hw;
852 switch (hw->mac.type) {
853 case ixgbe_mac_82598EB:
854 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
855 if (direction == -1)
856 direction = 0;
857 index = (((direction * 64) + queue) >> 2) & 0x1F;
858 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
859 ivar &= ~(0xFF << (8 * (queue & 0x3)));
860 ivar |= (msix_vector << (8 * (queue & 0x3)));
861 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
862 break;
863 case ixgbe_mac_82599EB:
864 case ixgbe_mac_X540:
865 case ixgbe_mac_X550:
866 case ixgbe_mac_X550EM_x:
867 if (direction == -1) {
868 /* other causes */
869 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
870 index = ((queue & 1) * 8);
871 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
872 ivar &= ~(0xFF << index);
873 ivar |= (msix_vector << index);
874 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
875 break;
876 } else {
877 /* tx or rx causes */
878 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
879 index = ((16 * (queue & 1)) + (8 * direction));
880 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
881 ivar &= ~(0xFF << index);
882 ivar |= (msix_vector << index);
883 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
884 break;
885 }
886 default:
887 break;
888 }
889 }
890
891 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
892 u64 qmask)
893 {
894 u32 mask;
895
896 switch (adapter->hw.mac.type) {
897 case ixgbe_mac_82598EB:
898 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
900 break;
901 case ixgbe_mac_82599EB:
902 case ixgbe_mac_X540:
903 case ixgbe_mac_X550:
904 case ixgbe_mac_X550EM_x:
905 mask = (qmask & 0xFFFFFFFF);
906 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
907 mask = (qmask >> 32);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
909 break;
910 default:
911 break;
912 }
913 }
914
915 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
916 struct ixgbe_tx_buffer *tx_buffer)
917 {
918 if (tx_buffer->skb) {
919 dev_kfree_skb_any(tx_buffer->skb);
920 if (dma_unmap_len(tx_buffer, len))
921 dma_unmap_single(ring->dev,
922 dma_unmap_addr(tx_buffer, dma),
923 dma_unmap_len(tx_buffer, len),
924 DMA_TO_DEVICE);
925 } else if (dma_unmap_len(tx_buffer, len)) {
926 dma_unmap_page(ring->dev,
927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
929 DMA_TO_DEVICE);
930 }
931 tx_buffer->next_to_watch = NULL;
932 tx_buffer->skb = NULL;
933 dma_unmap_len_set(tx_buffer, len, 0);
934 /* tx_buffer must be completely set up in the transmit path */
935 }
936
937 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
938 {
939 struct ixgbe_hw *hw = &adapter->hw;
940 struct ixgbe_hw_stats *hwstats = &adapter->stats;
941 int i;
942 u32 data;
943
944 if ((hw->fc.current_mode != ixgbe_fc_full) &&
945 (hw->fc.current_mode != ixgbe_fc_rx_pause))
946 return;
947
948 switch (hw->mac.type) {
949 case ixgbe_mac_82598EB:
950 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
951 break;
952 default:
953 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
954 }
955 hwstats->lxoffrxc += data;
956
957 /* refill credits (no tx hang) if we received xoff */
958 if (!data)
959 return;
960
961 for (i = 0; i < adapter->num_tx_queues; i++)
962 clear_bit(__IXGBE_HANG_CHECK_ARMED,
963 &adapter->tx_ring[i]->state);
964 }
965
966 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
967 {
968 struct ixgbe_hw *hw = &adapter->hw;
969 struct ixgbe_hw_stats *hwstats = &adapter->stats;
970 u32 xoff[8] = {0};
971 u8 tc;
972 int i;
973 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
974
975 if (adapter->ixgbe_ieee_pfc)
976 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
977
978 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
979 ixgbe_update_xoff_rx_lfc(adapter);
980 return;
981 }
982
983 /* update stats for each tc, only valid with PFC enabled */
984 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
985 u32 pxoffrxc;
986
987 switch (hw->mac.type) {
988 case ixgbe_mac_82598EB:
989 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
990 break;
991 default:
992 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
993 }
994 hwstats->pxoffrxc[i] += pxoffrxc;
995 /* Get the TC for given UP */
996 tc = netdev_get_prio_tc_map(adapter->netdev, i);
997 xoff[tc] += pxoffrxc;
998 }
999
1000 /* disarm tx queues that have received xoff frames */
1001 for (i = 0; i < adapter->num_tx_queues; i++) {
1002 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
1003
1004 tc = tx_ring->dcb_tc;
1005 if (xoff[tc])
1006 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1007 }
1008 }
1009
1010 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1011 {
1012 return ring->stats.packets;
1013 }
1014
1015 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1016 {
1017 struct ixgbe_adapter *adapter;
1018 struct ixgbe_hw *hw;
1019 u32 head, tail;
1020
1021 if (ring->l2_accel_priv)
1022 adapter = ring->l2_accel_priv->real_adapter;
1023 else
1024 adapter = netdev_priv(ring->netdev);
1025
1026 hw = &adapter->hw;
1027 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1028 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
1029
1030 if (head != tail)
1031 return (head < tail) ?
1032 tail - head : (tail + ring->count - head);
1033
1034 return 0;
1035 }
1036
1037 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1038 {
1039 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1040 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1041 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1042
1043 clear_check_for_tx_hang(tx_ring);
1044
1045 /*
1046 * Check for a hung queue, but be thorough. This verifies
1047 * that a transmit has been completed since the previous
1048 * check AND there is at least one packet pending. The
1049 * ARMED bit is set to indicate a potential hang. The
1050 * bit is cleared if a pause frame is received to remove
1051 * false hang detection due to PFC or 802.3x frames. By
1052 * requiring this to fail twice we avoid races with
1053 * pfc clearing the ARMED bit and conditions where we
1054 * run the check_tx_hang logic with a transmit completion
1055 * pending but without time to complete it yet.
1056 */
1057 if (tx_done_old == tx_done && tx_pending)
1058 /* make sure it is true for two checks in a row */
1059 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1060 &tx_ring->state);
1061 /* update completed stats and continue */
1062 tx_ring->tx_stats.tx_done_old = tx_done;
1063 /* reset the countdown */
1064 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1065
1066 return false;
1067 }
1068
1069 /**
1070 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1071 * @adapter: driver private struct
1072 **/
1073 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1074 {
1075
1076 /* Do the reset outside of interrupt context */
1077 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1078 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
1079 e_warn(drv, "initiating reset due to tx timeout\n");
1080 ixgbe_service_event_schedule(adapter);
1081 }
1082 }
1083
1084 /**
1085 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1086 * @q_vector: structure containing interrupt and ring information
1087 * @tx_ring: tx ring to clean
1088 **/
1089 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1090 struct ixgbe_ring *tx_ring)
1091 {
1092 struct ixgbe_adapter *adapter = q_vector->adapter;
1093 struct ixgbe_tx_buffer *tx_buffer;
1094 union ixgbe_adv_tx_desc *tx_desc;
1095 unsigned int total_bytes = 0, total_packets = 0;
1096 unsigned int budget = q_vector->tx.work_limit;
1097 unsigned int i = tx_ring->next_to_clean;
1098
1099 if (test_bit(__IXGBE_DOWN, &adapter->state))
1100 return true;
1101
1102 tx_buffer = &tx_ring->tx_buffer_info[i];
1103 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1104 i -= tx_ring->count;
1105
1106 do {
1107 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1108
1109 /* if next_to_watch is not set then there is no work pending */
1110 if (!eop_desc)
1111 break;
1112
1113 /* prevent any other reads prior to eop_desc */
1114 read_barrier_depends();
1115
1116 /* if DD is not set pending work has not been completed */
1117 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1118 break;
1119
1120 /* clear next_to_watch to prevent false hangs */
1121 tx_buffer->next_to_watch = NULL;
1122
1123 /* update the statistics for this packet */
1124 total_bytes += tx_buffer->bytecount;
1125 total_packets += tx_buffer->gso_segs;
1126
1127 /* free the skb */
1128 dev_consume_skb_any(tx_buffer->skb);
1129
1130 /* unmap skb header data */
1131 dma_unmap_single(tx_ring->dev,
1132 dma_unmap_addr(tx_buffer, dma),
1133 dma_unmap_len(tx_buffer, len),
1134 DMA_TO_DEVICE);
1135
1136 /* clear tx_buffer data */
1137 tx_buffer->skb = NULL;
1138 dma_unmap_len_set(tx_buffer, len, 0);
1139
1140 /* unmap remaining buffers */
1141 while (tx_desc != eop_desc) {
1142 tx_buffer++;
1143 tx_desc++;
1144 i++;
1145 if (unlikely(!i)) {
1146 i -= tx_ring->count;
1147 tx_buffer = tx_ring->tx_buffer_info;
1148 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1149 }
1150
1151 /* unmap any remaining paged data */
1152 if (dma_unmap_len(tx_buffer, len)) {
1153 dma_unmap_page(tx_ring->dev,
1154 dma_unmap_addr(tx_buffer, dma),
1155 dma_unmap_len(tx_buffer, len),
1156 DMA_TO_DEVICE);
1157 dma_unmap_len_set(tx_buffer, len, 0);
1158 }
1159 }
1160
1161 /* move us one more past the eop_desc for start of next pkt */
1162 tx_buffer++;
1163 tx_desc++;
1164 i++;
1165 if (unlikely(!i)) {
1166 i -= tx_ring->count;
1167 tx_buffer = tx_ring->tx_buffer_info;
1168 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1169 }
1170
1171 /* issue prefetch for next Tx descriptor */
1172 prefetch(tx_desc);
1173
1174 /* update budget accounting */
1175 budget--;
1176 } while (likely(budget));
1177
1178 i += tx_ring->count;
1179 tx_ring->next_to_clean = i;
1180 u64_stats_update_begin(&tx_ring->syncp);
1181 tx_ring->stats.bytes += total_bytes;
1182 tx_ring->stats.packets += total_packets;
1183 u64_stats_update_end(&tx_ring->syncp);
1184 q_vector->tx.total_bytes += total_bytes;
1185 q_vector->tx.total_packets += total_packets;
1186
1187 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1188 /* schedule immediate reset if we believe we hung */
1189 struct ixgbe_hw *hw = &adapter->hw;
1190 e_err(drv, "Detected Tx Unit Hang\n"
1191 " Tx Queue <%d>\n"
1192 " TDH, TDT <%x>, <%x>\n"
1193 " next_to_use <%x>\n"
1194 " next_to_clean <%x>\n"
1195 "tx_buffer_info[next_to_clean]\n"
1196 " time_stamp <%lx>\n"
1197 " jiffies <%lx>\n",
1198 tx_ring->queue_index,
1199 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1200 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1201 tx_ring->next_to_use, i,
1202 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1203
1204 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1205
1206 e_info(probe,
1207 "tx hang %d detected on queue %d, resetting adapter\n",
1208 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1209
1210 /* schedule immediate reset if we believe we hung */
1211 ixgbe_tx_timeout_reset(adapter);
1212
1213 /* the adapter is about to reset, no point in enabling stuff */
1214 return true;
1215 }
1216
1217 netdev_tx_completed_queue(txring_txq(tx_ring),
1218 total_packets, total_bytes);
1219
1220 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1221 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
1222 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
1223 /* Make sure that anybody stopping the queue after this
1224 * sees the new next_to_clean.
1225 */
1226 smp_mb();
1227 if (__netif_subqueue_stopped(tx_ring->netdev,
1228 tx_ring->queue_index)
1229 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1230 netif_wake_subqueue(tx_ring->netdev,
1231 tx_ring->queue_index);
1232 ++tx_ring->tx_stats.restart_queue;
1233 }
1234 }
1235
1236 return !!budget;
1237 }
1238
1239 #ifdef CONFIG_IXGBE_DCA
1240 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1241 struct ixgbe_ring *tx_ring,
1242 int cpu)
1243 {
1244 struct ixgbe_hw *hw = &adapter->hw;
1245 u32 txctrl = 0;
1246 u16 reg_offset;
1247
1248 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1249 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1250
1251 switch (hw->mac.type) {
1252 case ixgbe_mac_82598EB:
1253 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1254 break;
1255 case ixgbe_mac_82599EB:
1256 case ixgbe_mac_X540:
1257 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1258 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1259 break;
1260 default:
1261 /* for unknown hardware do not write register */
1262 return;
1263 }
1264
1265 /*
1266 * We can enable relaxed ordering for reads, but not writes when
1267 * DCA is enabled. This is due to a known issue in some chipsets
1268 * which will cause the DCA tag to be cleared.
1269 */
1270 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1271 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1272 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1273
1274 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1275 }
1276
1277 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1278 struct ixgbe_ring *rx_ring,
1279 int cpu)
1280 {
1281 struct ixgbe_hw *hw = &adapter->hw;
1282 u32 rxctrl = 0;
1283 u8 reg_idx = rx_ring->reg_idx;
1284
1285 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1286 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1287
1288 switch (hw->mac.type) {
1289 case ixgbe_mac_82599EB:
1290 case ixgbe_mac_X540:
1291 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1292 break;
1293 default:
1294 break;
1295 }
1296
1297 /*
1298 * We can enable relaxed ordering for reads, but not writes when
1299 * DCA is enabled. This is due to a known issue in some chipsets
1300 * which will cause the DCA tag to be cleared.
1301 */
1302 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1303 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1304 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1305
1306 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1307 }
1308
1309 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1310 {
1311 struct ixgbe_adapter *adapter = q_vector->adapter;
1312 struct ixgbe_ring *ring;
1313 int cpu = get_cpu();
1314
1315 if (q_vector->cpu == cpu)
1316 goto out_no_update;
1317
1318 ixgbe_for_each_ring(ring, q_vector->tx)
1319 ixgbe_update_tx_dca(adapter, ring, cpu);
1320
1321 ixgbe_for_each_ring(ring, q_vector->rx)
1322 ixgbe_update_rx_dca(adapter, ring, cpu);
1323
1324 q_vector->cpu = cpu;
1325 out_no_update:
1326 put_cpu();
1327 }
1328
1329 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1330 {
1331 int i;
1332
1333 /* always use CB2 mode, difference is masked in the CB driver */
1334 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1336 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1337 else
1338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1339 IXGBE_DCA_CTRL_DCA_DISABLE);
1340
1341 for (i = 0; i < adapter->num_q_vectors; i++) {
1342 adapter->q_vector[i]->cpu = -1;
1343 ixgbe_update_dca(adapter->q_vector[i]);
1344 }
1345 }
1346
1347 static int __ixgbe_notify_dca(struct device *dev, void *data)
1348 {
1349 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1350 unsigned long event = *(unsigned long *)data;
1351
1352 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1353 return 0;
1354
1355 switch (event) {
1356 case DCA_PROVIDER_ADD:
1357 /* if we're already enabled, don't do it again */
1358 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1359 break;
1360 if (dca_add_requester(dev) == 0) {
1361 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1363 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1364 break;
1365 }
1366 /* Fall Through since DCA is disabled. */
1367 case DCA_PROVIDER_REMOVE:
1368 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1369 dca_remove_requester(dev);
1370 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1371 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1372 IXGBE_DCA_CTRL_DCA_DISABLE);
1373 }
1374 break;
1375 }
1376
1377 return 0;
1378 }
1379
1380 #endif /* CONFIG_IXGBE_DCA */
1381
1382 #define IXGBE_RSS_L4_TYPES_MASK \
1383 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1384 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1385 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1386 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1387
1388 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1389 union ixgbe_adv_rx_desc *rx_desc,
1390 struct sk_buff *skb)
1391 {
1392 u16 rss_type;
1393
1394 if (!(ring->netdev->features & NETIF_F_RXHASH))
1395 return;
1396
1397 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1398 IXGBE_RXDADV_RSSTYPE_MASK;
1399
1400 if (!rss_type)
1401 return;
1402
1403 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1404 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1405 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1406 }
1407
1408 #ifdef IXGBE_FCOE
1409 /**
1410 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1411 * @ring: structure containing ring specific data
1412 * @rx_desc: advanced rx descriptor
1413 *
1414 * Returns : true if it is FCoE pkt
1415 */
1416 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1417 union ixgbe_adv_rx_desc *rx_desc)
1418 {
1419 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1420
1421 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1422 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1423 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1424 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1425 }
1426
1427 #endif /* IXGBE_FCOE */
1428 /**
1429 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1430 * @ring: structure containing ring specific data
1431 * @rx_desc: current Rx descriptor being processed
1432 * @skb: skb currently being received and modified
1433 **/
1434 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1435 union ixgbe_adv_rx_desc *rx_desc,
1436 struct sk_buff *skb)
1437 {
1438 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1439 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1440 bool encap_pkt = false;
1441
1442 skb_checksum_none_assert(skb);
1443
1444 /* Rx csum disabled */
1445 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1446 return;
1447
1448 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1449 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1450 encap_pkt = true;
1451 skb->encapsulation = 1;
1452 }
1453
1454 /* if IP and error */
1455 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1456 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1457 ring->rx_stats.csum_err++;
1458 return;
1459 }
1460
1461 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1462 return;
1463
1464 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1465 /*
1466 * 82599 errata, UDP frames with a 0 checksum can be marked as
1467 * checksum errors.
1468 */
1469 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1470 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1471 return;
1472
1473 ring->rx_stats.csum_err++;
1474 return;
1475 }
1476
1477 /* It must be a TCP or UDP packet with a valid checksum */
1478 skb->ip_summed = CHECKSUM_UNNECESSARY;
1479 if (encap_pkt) {
1480 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1481 return;
1482
1483 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1484 ring->rx_stats.csum_err++;
1485 return;
1486 }
1487 /* If we checked the outer header let the stack know */
1488 skb->csum_level = 1;
1489 }
1490 }
1491
1492 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1493 struct ixgbe_rx_buffer *bi)
1494 {
1495 struct page *page = bi->page;
1496 dma_addr_t dma;
1497
1498 /* since we are recycling buffers we should seldom need to alloc */
1499 if (likely(page))
1500 return true;
1501
1502 /* alloc new page for storage */
1503 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1504 if (unlikely(!page)) {
1505 rx_ring->rx_stats.alloc_rx_page_failed++;
1506 return false;
1507 }
1508
1509 /* map page for use */
1510 dma = dma_map_page(rx_ring->dev, page, 0,
1511 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1512
1513 /*
1514 * if mapping failed free memory back to system since
1515 * there isn't much point in holding memory we can't use
1516 */
1517 if (dma_mapping_error(rx_ring->dev, dma)) {
1518 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1519
1520 rx_ring->rx_stats.alloc_rx_page_failed++;
1521 return false;
1522 }
1523
1524 bi->dma = dma;
1525 bi->page = page;
1526 bi->page_offset = 0;
1527
1528 return true;
1529 }
1530
1531 /**
1532 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1533 * @rx_ring: ring to place buffers on
1534 * @cleaned_count: number of buffers to replace
1535 **/
1536 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1537 {
1538 union ixgbe_adv_rx_desc *rx_desc;
1539 struct ixgbe_rx_buffer *bi;
1540 u16 i = rx_ring->next_to_use;
1541
1542 /* nothing to do */
1543 if (!cleaned_count)
1544 return;
1545
1546 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1547 bi = &rx_ring->rx_buffer_info[i];
1548 i -= rx_ring->count;
1549
1550 do {
1551 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1552 break;
1553
1554 /*
1555 * Refresh the desc even if buffer_addrs didn't change
1556 * because each write-back erases this info.
1557 */
1558 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1559
1560 rx_desc++;
1561 bi++;
1562 i++;
1563 if (unlikely(!i)) {
1564 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1565 bi = rx_ring->rx_buffer_info;
1566 i -= rx_ring->count;
1567 }
1568
1569 /* clear the status bits for the next_to_use descriptor */
1570 rx_desc->wb.upper.status_error = 0;
1571
1572 cleaned_count--;
1573 } while (cleaned_count);
1574
1575 i += rx_ring->count;
1576
1577 if (rx_ring->next_to_use != i) {
1578 rx_ring->next_to_use = i;
1579
1580 /* update next to alloc since we have filled the ring */
1581 rx_ring->next_to_alloc = i;
1582
1583 /* Force memory writes to complete before letting h/w
1584 * know there are new descriptors to fetch. (Only
1585 * applicable for weak-ordered memory model archs,
1586 * such as IA-64).
1587 */
1588 wmb();
1589 writel(i, rx_ring->tail);
1590 }
1591 }
1592
1593 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1594 struct sk_buff *skb)
1595 {
1596 u16 hdr_len = skb_headlen(skb);
1597
1598 /* set gso_size to avoid messing up TCP MSS */
1599 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1600 IXGBE_CB(skb)->append_cnt);
1601 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1602 }
1603
1604 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1605 struct sk_buff *skb)
1606 {
1607 /* if append_cnt is 0 then frame is not RSC */
1608 if (!IXGBE_CB(skb)->append_cnt)
1609 return;
1610
1611 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1612 rx_ring->rx_stats.rsc_flush++;
1613
1614 ixgbe_set_rsc_gso_size(rx_ring, skb);
1615
1616 /* gso_size is computed using append_cnt so always clear it last */
1617 IXGBE_CB(skb)->append_cnt = 0;
1618 }
1619
1620 /**
1621 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1622 * @rx_ring: rx descriptor ring packet is being transacted on
1623 * @rx_desc: pointer to the EOP Rx descriptor
1624 * @skb: pointer to current skb being populated
1625 *
1626 * This function checks the ring, descriptor, and packet information in
1627 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1628 * other fields within the skb.
1629 **/
1630 static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1631 union ixgbe_adv_rx_desc *rx_desc,
1632 struct sk_buff *skb)
1633 {
1634 struct net_device *dev = rx_ring->netdev;
1635
1636 ixgbe_update_rsc_stats(rx_ring, skb);
1637
1638 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1639
1640 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1641
1642 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1643 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
1644
1645 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1646 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1647 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1648 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1649 }
1650
1651 skb_record_rx_queue(skb, rx_ring->queue_index);
1652
1653 skb->protocol = eth_type_trans(skb, dev);
1654 }
1655
1656 static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1657 struct sk_buff *skb)
1658 {
1659 skb_mark_napi_id(skb, &q_vector->napi);
1660 if (ixgbe_qv_busy_polling(q_vector))
1661 netif_receive_skb(skb);
1662 else
1663 napi_gro_receive(&q_vector->napi, skb);
1664 }
1665
1666 /**
1667 * ixgbe_is_non_eop - process handling of non-EOP buffers
1668 * @rx_ring: Rx ring being processed
1669 * @rx_desc: Rx descriptor for current buffer
1670 * @skb: Current socket buffer containing buffer in progress
1671 *
1672 * This function updates next to clean. If the buffer is an EOP buffer
1673 * this function exits returning false, otherwise it will place the
1674 * sk_buff in the next buffer to be chained and return true indicating
1675 * that this is in fact a non-EOP buffer.
1676 **/
1677 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1678 union ixgbe_adv_rx_desc *rx_desc,
1679 struct sk_buff *skb)
1680 {
1681 u32 ntc = rx_ring->next_to_clean + 1;
1682
1683 /* fetch, update, and store next to clean */
1684 ntc = (ntc < rx_ring->count) ? ntc : 0;
1685 rx_ring->next_to_clean = ntc;
1686
1687 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1688
1689 /* update RSC append count if present */
1690 if (ring_is_rsc_enabled(rx_ring)) {
1691 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1692 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1693
1694 if (unlikely(rsc_enabled)) {
1695 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1696
1697 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1698 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1699
1700 /* update ntc based on RSC value */
1701 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1702 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1703 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1704 }
1705 }
1706
1707 /* if we are the last buffer then there is nothing else to do */
1708 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1709 return false;
1710
1711 /* place skb in next buffer to be received */
1712 rx_ring->rx_buffer_info[ntc].skb = skb;
1713 rx_ring->rx_stats.non_eop_descs++;
1714
1715 return true;
1716 }
1717
1718 /**
1719 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1720 * @rx_ring: rx descriptor ring packet is being transacted on
1721 * @skb: pointer to current skb being adjusted
1722 *
1723 * This function is an ixgbe specific version of __pskb_pull_tail. The
1724 * main difference between this version and the original function is that
1725 * this function can make several assumptions about the state of things
1726 * that allow for significant optimizations versus the standard function.
1727 * As a result we can do things like drop a frag and maintain an accurate
1728 * truesize for the skb.
1729 */
1730 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1731 struct sk_buff *skb)
1732 {
1733 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1734 unsigned char *va;
1735 unsigned int pull_len;
1736
1737 /*
1738 * it is valid to use page_address instead of kmap since we are
1739 * working with pages allocated out of the lomem pool per
1740 * alloc_page(GFP_ATOMIC)
1741 */
1742 va = skb_frag_address(frag);
1743
1744 /*
1745 * we need the header to contain the greater of either ETH_HLEN or
1746 * 60 bytes if the skb->len is less than 60 for skb_pad.
1747 */
1748 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
1749
1750 /* align pull length to size of long to optimize memcpy performance */
1751 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1752
1753 /* update all of the pointers */
1754 skb_frag_size_sub(frag, pull_len);
1755 frag->page_offset += pull_len;
1756 skb->data_len -= pull_len;
1757 skb->tail += pull_len;
1758 }
1759
1760 /**
1761 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1762 * @rx_ring: rx descriptor ring packet is being transacted on
1763 * @skb: pointer to current skb being updated
1764 *
1765 * This function provides a basic DMA sync up for the first fragment of an
1766 * skb. The reason for doing this is that the first fragment cannot be
1767 * unmapped until we have reached the end of packet descriptor for a buffer
1768 * chain.
1769 */
1770 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1771 struct sk_buff *skb)
1772 {
1773 /* if the page was released unmap it, else just sync our portion */
1774 if (unlikely(IXGBE_CB(skb)->page_released)) {
1775 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1776 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1777 IXGBE_CB(skb)->page_released = false;
1778 } else {
1779 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1780
1781 dma_sync_single_range_for_cpu(rx_ring->dev,
1782 IXGBE_CB(skb)->dma,
1783 frag->page_offset,
1784 ixgbe_rx_bufsz(rx_ring),
1785 DMA_FROM_DEVICE);
1786 }
1787 IXGBE_CB(skb)->dma = 0;
1788 }
1789
1790 /**
1791 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1792 * @rx_ring: rx descriptor ring packet is being transacted on
1793 * @rx_desc: pointer to the EOP Rx descriptor
1794 * @skb: pointer to current skb being fixed
1795 *
1796 * Check for corrupted packet headers caused by senders on the local L2
1797 * embedded NIC switch not setting up their Tx Descriptors right. These
1798 * should be very rare.
1799 *
1800 * Also address the case where we are pulling data in on pages only
1801 * and as such no data is present in the skb header.
1802 *
1803 * In addition if skb is not at least 60 bytes we need to pad it so that
1804 * it is large enough to qualify as a valid Ethernet frame.
1805 *
1806 * Returns true if an error was encountered and skb was freed.
1807 **/
1808 static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1809 union ixgbe_adv_rx_desc *rx_desc,
1810 struct sk_buff *skb)
1811 {
1812 struct net_device *netdev = rx_ring->netdev;
1813
1814 /* verify that the packet does not have any known errors */
1815 if (unlikely(ixgbe_test_staterr(rx_desc,
1816 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1817 !(netdev->features & NETIF_F_RXALL))) {
1818 dev_kfree_skb_any(skb);
1819 return true;
1820 }
1821
1822 /* place header in linear portion of buffer */
1823 if (skb_is_nonlinear(skb))
1824 ixgbe_pull_tail(rx_ring, skb);
1825
1826 #ifdef IXGBE_FCOE
1827 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1828 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1829 return false;
1830
1831 #endif
1832 /* if eth_skb_pad returns an error the skb was freed */
1833 if (eth_skb_pad(skb))
1834 return true;
1835
1836 return false;
1837 }
1838
1839 /**
1840 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1841 * @rx_ring: rx descriptor ring to store buffers on
1842 * @old_buff: donor buffer to have page reused
1843 *
1844 * Synchronizes page for reuse by the adapter
1845 **/
1846 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1847 struct ixgbe_rx_buffer *old_buff)
1848 {
1849 struct ixgbe_rx_buffer *new_buff;
1850 u16 nta = rx_ring->next_to_alloc;
1851
1852 new_buff = &rx_ring->rx_buffer_info[nta];
1853
1854 /* update, and store next to alloc */
1855 nta++;
1856 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1857
1858 /* transfer page from old buffer to new buffer */
1859 *new_buff = *old_buff;
1860
1861 /* sync the buffer for use by the device */
1862 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1863 new_buff->page_offset,
1864 ixgbe_rx_bufsz(rx_ring),
1865 DMA_FROM_DEVICE);
1866 }
1867
1868 static inline bool ixgbe_page_is_reserved(struct page *page)
1869 {
1870 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1871 }
1872
1873 /**
1874 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1875 * @rx_ring: rx descriptor ring to transact packets on
1876 * @rx_buffer: buffer containing page to add
1877 * @rx_desc: descriptor containing length of buffer written by hardware
1878 * @skb: sk_buff to place the data into
1879 *
1880 * This function will add the data contained in rx_buffer->page to the skb.
1881 * This is done either through a direct copy if the data in the buffer is
1882 * less than the skb header size, otherwise it will just attach the page as
1883 * a frag to the skb.
1884 *
1885 * The function will then update the page offset if necessary and return
1886 * true if the buffer can be reused by the adapter.
1887 **/
1888 static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1889 struct ixgbe_rx_buffer *rx_buffer,
1890 union ixgbe_adv_rx_desc *rx_desc,
1891 struct sk_buff *skb)
1892 {
1893 struct page *page = rx_buffer->page;
1894 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
1895 #if (PAGE_SIZE < 8192)
1896 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
1897 #else
1898 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1899 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1900 ixgbe_rx_bufsz(rx_ring);
1901 #endif
1902
1903 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1904 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1905
1906 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1907
1908 /* page is not reserved, we can reuse buffer as-is */
1909 if (likely(!ixgbe_page_is_reserved(page)))
1910 return true;
1911
1912 /* this page cannot be reused so discard it */
1913 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1914 return false;
1915 }
1916
1917 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1918 rx_buffer->page_offset, size, truesize);
1919
1920 /* avoid re-using remote pages */
1921 if (unlikely(ixgbe_page_is_reserved(page)))
1922 return false;
1923
1924 #if (PAGE_SIZE < 8192)
1925 /* if we are only owner of page we can reuse it */
1926 if (unlikely(page_count(page) != 1))
1927 return false;
1928
1929 /* flip page offset to other buffer */
1930 rx_buffer->page_offset ^= truesize;
1931 #else
1932 /* move offset up to the next cache line */
1933 rx_buffer->page_offset += truesize;
1934
1935 if (rx_buffer->page_offset > last_offset)
1936 return false;
1937 #endif
1938
1939 /* Even if we own the page, we are not allowed to use atomic_set()
1940 * This would break get_page_unless_zero() users.
1941 */
1942 atomic_inc(&page->_count);
1943
1944 return true;
1945 }
1946
1947 static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1948 union ixgbe_adv_rx_desc *rx_desc)
1949 {
1950 struct ixgbe_rx_buffer *rx_buffer;
1951 struct sk_buff *skb;
1952 struct page *page;
1953
1954 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1955 page = rx_buffer->page;
1956 prefetchw(page);
1957
1958 skb = rx_buffer->skb;
1959
1960 if (likely(!skb)) {
1961 void *page_addr = page_address(page) +
1962 rx_buffer->page_offset;
1963
1964 /* prefetch first cache line of first page */
1965 prefetch(page_addr);
1966 #if L1_CACHE_BYTES < 128
1967 prefetch(page_addr + L1_CACHE_BYTES);
1968 #endif
1969
1970 /* allocate a skb to store the frags */
1971 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1972 IXGBE_RX_HDR_SIZE);
1973 if (unlikely(!skb)) {
1974 rx_ring->rx_stats.alloc_rx_buff_failed++;
1975 return NULL;
1976 }
1977
1978 /*
1979 * we will be copying header into skb->data in
1980 * pskb_may_pull so it is in our interest to prefetch
1981 * it now to avoid a possible cache miss
1982 */
1983 prefetchw(skb->data);
1984
1985 /*
1986 * Delay unmapping of the first packet. It carries the
1987 * header information, HW may still access the header
1988 * after the writeback. Only unmap it when EOP is
1989 * reached
1990 */
1991 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1992 goto dma_sync;
1993
1994 IXGBE_CB(skb)->dma = rx_buffer->dma;
1995 } else {
1996 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1997 ixgbe_dma_sync_frag(rx_ring, skb);
1998
1999 dma_sync:
2000 /* we are reusing so sync this buffer for CPU use */
2001 dma_sync_single_range_for_cpu(rx_ring->dev,
2002 rx_buffer->dma,
2003 rx_buffer->page_offset,
2004 ixgbe_rx_bufsz(rx_ring),
2005 DMA_FROM_DEVICE);
2006
2007 rx_buffer->skb = NULL;
2008 }
2009
2010 /* pull page into skb */
2011 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2012 /* hand second half of page back to the ring */
2013 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2014 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2015 /* the page has been released from the ring */
2016 IXGBE_CB(skb)->page_released = true;
2017 } else {
2018 /* we are not reusing the buffer so unmap it */
2019 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2020 ixgbe_rx_pg_size(rx_ring),
2021 DMA_FROM_DEVICE);
2022 }
2023
2024 /* clear contents of buffer_info */
2025 rx_buffer->page = NULL;
2026
2027 return skb;
2028 }
2029
2030 /**
2031 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2032 * @q_vector: structure containing interrupt and ring information
2033 * @rx_ring: rx descriptor ring to transact packets on
2034 * @budget: Total limit on number of packets to process
2035 *
2036 * This function provides a "bounce buffer" approach to Rx interrupt
2037 * processing. The advantage to this is that on systems that have
2038 * expensive overhead for IOMMU access this provides a means of avoiding
2039 * it by maintaining the mapping of the page to the syste.
2040 *
2041 * Returns amount of work completed
2042 **/
2043 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2044 struct ixgbe_ring *rx_ring,
2045 const int budget)
2046 {
2047 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2048 #ifdef IXGBE_FCOE
2049 struct ixgbe_adapter *adapter = q_vector->adapter;
2050 int ddp_bytes;
2051 unsigned int mss = 0;
2052 #endif /* IXGBE_FCOE */
2053 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2054
2055 while (likely(total_rx_packets < budget)) {
2056 union ixgbe_adv_rx_desc *rx_desc;
2057 struct sk_buff *skb;
2058
2059 /* return some buffers to hardware, one at a time is too slow */
2060 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2061 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2062 cleaned_count = 0;
2063 }
2064
2065 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2066
2067 if (!rx_desc->wb.upper.status_error)
2068 break;
2069
2070 /* This memory barrier is needed to keep us from reading
2071 * any other fields out of the rx_desc until we know the
2072 * descriptor has been written back
2073 */
2074 dma_rmb();
2075
2076 /* retrieve a buffer from the ring */
2077 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
2078
2079 /* exit if we failed to retrieve a buffer */
2080 if (!skb)
2081 break;
2082
2083 cleaned_count++;
2084
2085 /* place incomplete frames back on ring for completion */
2086 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2087 continue;
2088
2089 /* verify the packet layout is correct */
2090 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2091 continue;
2092
2093 /* probably a little skewed due to removing CRC */
2094 total_rx_bytes += skb->len;
2095
2096 /* populate checksum, timestamp, VLAN, and protocol */
2097 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2098
2099 #ifdef IXGBE_FCOE
2100 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2101 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2102 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2103 /* include DDPed FCoE data */
2104 if (ddp_bytes > 0) {
2105 if (!mss) {
2106 mss = rx_ring->netdev->mtu -
2107 sizeof(struct fcoe_hdr) -
2108 sizeof(struct fc_frame_header) -
2109 sizeof(struct fcoe_crc_eof);
2110 if (mss > 512)
2111 mss &= ~511;
2112 }
2113 total_rx_bytes += ddp_bytes;
2114 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2115 mss);
2116 }
2117 if (!ddp_bytes) {
2118 dev_kfree_skb_any(skb);
2119 continue;
2120 }
2121 }
2122
2123 #endif /* IXGBE_FCOE */
2124 ixgbe_rx_skb(q_vector, skb);
2125
2126 /* update budget accounting */
2127 total_rx_packets++;
2128 }
2129
2130 u64_stats_update_begin(&rx_ring->syncp);
2131 rx_ring->stats.packets += total_rx_packets;
2132 rx_ring->stats.bytes += total_rx_bytes;
2133 u64_stats_update_end(&rx_ring->syncp);
2134 q_vector->rx.total_packets += total_rx_packets;
2135 q_vector->rx.total_bytes += total_rx_bytes;
2136
2137 return total_rx_packets;
2138 }
2139
2140 #ifdef CONFIG_NET_RX_BUSY_POLL
2141 /* must be called with local_bh_disable()d */
2142 static int ixgbe_low_latency_recv(struct napi_struct *napi)
2143 {
2144 struct ixgbe_q_vector *q_vector =
2145 container_of(napi, struct ixgbe_q_vector, napi);
2146 struct ixgbe_adapter *adapter = q_vector->adapter;
2147 struct ixgbe_ring *ring;
2148 int found = 0;
2149
2150 if (test_bit(__IXGBE_DOWN, &adapter->state))
2151 return LL_FLUSH_FAILED;
2152
2153 if (!ixgbe_qv_lock_poll(q_vector))
2154 return LL_FLUSH_BUSY;
2155
2156 ixgbe_for_each_ring(ring, q_vector->rx) {
2157 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
2158 #ifdef BP_EXTENDED_STATS
2159 if (found)
2160 ring->stats.cleaned += found;
2161 else
2162 ring->stats.misses++;
2163 #endif
2164 if (found)
2165 break;
2166 }
2167
2168 ixgbe_qv_unlock_poll(q_vector);
2169
2170 return found;
2171 }
2172 #endif /* CONFIG_NET_RX_BUSY_POLL */
2173
2174 /**
2175 * ixgbe_configure_msix - Configure MSI-X hardware
2176 * @adapter: board private structure
2177 *
2178 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2179 * interrupts.
2180 **/
2181 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2182 {
2183 struct ixgbe_q_vector *q_vector;
2184 int v_idx;
2185 u32 mask;
2186
2187 /* Populate MSIX to EITR Select */
2188 if (adapter->num_vfs > 32) {
2189 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2190 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2191 }
2192
2193 /*
2194 * Populate the IVAR table and set the ITR values to the
2195 * corresponding register.
2196 */
2197 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2198 struct ixgbe_ring *ring;
2199 q_vector = adapter->q_vector[v_idx];
2200
2201 ixgbe_for_each_ring(ring, q_vector->rx)
2202 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2203
2204 ixgbe_for_each_ring(ring, q_vector->tx)
2205 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2206
2207 ixgbe_write_eitr(q_vector);
2208 }
2209
2210 switch (adapter->hw.mac.type) {
2211 case ixgbe_mac_82598EB:
2212 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2213 v_idx);
2214 break;
2215 case ixgbe_mac_82599EB:
2216 case ixgbe_mac_X540:
2217 case ixgbe_mac_X550:
2218 case ixgbe_mac_X550EM_x:
2219 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2220 break;
2221 default:
2222 break;
2223 }
2224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2225
2226 /* set up to autoclear timer, and the vectors */
2227 mask = IXGBE_EIMS_ENABLE_MASK;
2228 mask &= ~(IXGBE_EIMS_OTHER |
2229 IXGBE_EIMS_MAILBOX |
2230 IXGBE_EIMS_LSC);
2231
2232 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2233 }
2234
2235 enum latency_range {
2236 lowest_latency = 0,
2237 low_latency = 1,
2238 bulk_latency = 2,
2239 latency_invalid = 255
2240 };
2241
2242 /**
2243 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2244 * @q_vector: structure containing interrupt and ring information
2245 * @ring_container: structure containing ring performance data
2246 *
2247 * Stores a new ITR value based on packets and byte
2248 * counts during the last interrupt. The advantage of per interrupt
2249 * computation is faster updates and more accurate ITR for the current
2250 * traffic pattern. Constants in this function were computed
2251 * based on theoretical maximum wire speed and thresholds were set based
2252 * on testing data as well as attempting to minimize response time
2253 * while increasing bulk throughput.
2254 * this functionality is controlled by the InterruptThrottleRate module
2255 * parameter (see ixgbe_param.c)
2256 **/
2257 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2258 struct ixgbe_ring_container *ring_container)
2259 {
2260 int bytes = ring_container->total_bytes;
2261 int packets = ring_container->total_packets;
2262 u32 timepassed_us;
2263 u64 bytes_perint;
2264 u8 itr_setting = ring_container->itr;
2265
2266 if (packets == 0)
2267 return;
2268
2269 /* simple throttlerate management
2270 * 0-10MB/s lowest (100000 ints/s)
2271 * 10-20MB/s low (20000 ints/s)
2272 * 20-1249MB/s bulk (12000 ints/s)
2273 */
2274 /* what was last interrupt timeslice? */
2275 timepassed_us = q_vector->itr >> 2;
2276 if (timepassed_us == 0)
2277 return;
2278
2279 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2280
2281 switch (itr_setting) {
2282 case lowest_latency:
2283 if (bytes_perint > 10)
2284 itr_setting = low_latency;
2285 break;
2286 case low_latency:
2287 if (bytes_perint > 20)
2288 itr_setting = bulk_latency;
2289 else if (bytes_perint <= 10)
2290 itr_setting = lowest_latency;
2291 break;
2292 case bulk_latency:
2293 if (bytes_perint <= 20)
2294 itr_setting = low_latency;
2295 break;
2296 }
2297
2298 /* clear work counters since we have the values we need */
2299 ring_container->total_bytes = 0;
2300 ring_container->total_packets = 0;
2301
2302 /* write updated itr to ring container */
2303 ring_container->itr = itr_setting;
2304 }
2305
2306 /**
2307 * ixgbe_write_eitr - write EITR register in hardware specific way
2308 * @q_vector: structure containing interrupt and ring information
2309 *
2310 * This function is made to be called by ethtool and by the driver
2311 * when it needs to update EITR registers at runtime. Hardware
2312 * specific quirks/differences are taken care of here.
2313 */
2314 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2315 {
2316 struct ixgbe_adapter *adapter = q_vector->adapter;
2317 struct ixgbe_hw *hw = &adapter->hw;
2318 int v_idx = q_vector->v_idx;
2319 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2320
2321 switch (adapter->hw.mac.type) {
2322 case ixgbe_mac_82598EB:
2323 /* must write high and low 16 bits to reset counter */
2324 itr_reg |= (itr_reg << 16);
2325 break;
2326 case ixgbe_mac_82599EB:
2327 case ixgbe_mac_X540:
2328 case ixgbe_mac_X550:
2329 case ixgbe_mac_X550EM_x:
2330 /*
2331 * set the WDIS bit to not clear the timer bits and cause an
2332 * immediate assertion of the interrupt
2333 */
2334 itr_reg |= IXGBE_EITR_CNT_WDIS;
2335 break;
2336 default:
2337 break;
2338 }
2339 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2340 }
2341
2342 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2343 {
2344 u32 new_itr = q_vector->itr;
2345 u8 current_itr;
2346
2347 ixgbe_update_itr(q_vector, &q_vector->tx);
2348 ixgbe_update_itr(q_vector, &q_vector->rx);
2349
2350 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2351
2352 switch (current_itr) {
2353 /* counts and packets in update_itr are dependent on these numbers */
2354 case lowest_latency:
2355 new_itr = IXGBE_100K_ITR;
2356 break;
2357 case low_latency:
2358 new_itr = IXGBE_20K_ITR;
2359 break;
2360 case bulk_latency:
2361 new_itr = IXGBE_12K_ITR;
2362 break;
2363 default:
2364 break;
2365 }
2366
2367 if (new_itr != q_vector->itr) {
2368 /* do an exponential smoothing */
2369 new_itr = (10 * new_itr * q_vector->itr) /
2370 ((9 * new_itr) + q_vector->itr);
2371
2372 /* save the algorithm value here */
2373 q_vector->itr = new_itr;
2374
2375 ixgbe_write_eitr(q_vector);
2376 }
2377 }
2378
2379 /**
2380 * ixgbe_check_overtemp_subtask - check for over temperature
2381 * @adapter: pointer to adapter
2382 **/
2383 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2384 {
2385 struct ixgbe_hw *hw = &adapter->hw;
2386 u32 eicr = adapter->interrupt_event;
2387
2388 if (test_bit(__IXGBE_DOWN, &adapter->state))
2389 return;
2390
2391 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2392 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2393 return;
2394
2395 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2396
2397 switch (hw->device_id) {
2398 case IXGBE_DEV_ID_82599_T3_LOM:
2399 /*
2400 * Since the warning interrupt is for both ports
2401 * we don't have to check if:
2402 * - This interrupt wasn't for our port.
2403 * - We may have missed the interrupt so always have to
2404 * check if we got a LSC
2405 */
2406 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2407 !(eicr & IXGBE_EICR_LSC))
2408 return;
2409
2410 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2411 u32 speed;
2412 bool link_up = false;
2413
2414 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2415
2416 if (link_up)
2417 return;
2418 }
2419
2420 /* Check if this is not due to overtemp */
2421 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2422 return;
2423
2424 break;
2425 default:
2426 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2427 return;
2428 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2429 return;
2430 break;
2431 }
2432 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2433
2434 adapter->interrupt_event = 0;
2435 }
2436
2437 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2438 {
2439 struct ixgbe_hw *hw = &adapter->hw;
2440
2441 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2442 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2443 e_crit(probe, "Fan has stopped, replace the adapter\n");
2444 /* write to clear the interrupt */
2445 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2446 }
2447 }
2448
2449 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2450 {
2451 struct ixgbe_hw *hw = &adapter->hw;
2452
2453 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2454 return;
2455
2456 switch (adapter->hw.mac.type) {
2457 case ixgbe_mac_82599EB:
2458 /*
2459 * Need to check link state so complete overtemp check
2460 * on service task
2461 */
2462 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2463 (eicr & IXGBE_EICR_LSC)) &&
2464 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2465 adapter->interrupt_event = eicr;
2466 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2467 ixgbe_service_event_schedule(adapter);
2468 return;
2469 }
2470 return;
2471 case ixgbe_mac_X540:
2472 if (!(eicr & IXGBE_EICR_TS))
2473 return;
2474 break;
2475 default:
2476 return;
2477 }
2478
2479 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2480 }
2481
2482 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2483 {
2484 switch (hw->mac.type) {
2485 case ixgbe_mac_82598EB:
2486 if (hw->phy.type == ixgbe_phy_nl)
2487 return true;
2488 return false;
2489 case ixgbe_mac_82599EB:
2490 case ixgbe_mac_X550EM_x:
2491 switch (hw->mac.ops.get_media_type(hw)) {
2492 case ixgbe_media_type_fiber:
2493 case ixgbe_media_type_fiber_qsfp:
2494 return true;
2495 default:
2496 return false;
2497 }
2498 default:
2499 return false;
2500 }
2501 }
2502
2503 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2504 {
2505 struct ixgbe_hw *hw = &adapter->hw;
2506 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2507
2508 if (!ixgbe_is_sfp(hw))
2509 return;
2510
2511 /* Later MAC's use different SDP */
2512 if (hw->mac.type >= ixgbe_mac_X540)
2513 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2514
2515 if (eicr & eicr_mask) {
2516 /* Clear the interrupt */
2517 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2518 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2519 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2520 adapter->sfp_poll_time = 0;
2521 ixgbe_service_event_schedule(adapter);
2522 }
2523 }
2524
2525 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2526 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2527 /* Clear the interrupt */
2528 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2529 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2530 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2531 ixgbe_service_event_schedule(adapter);
2532 }
2533 }
2534 }
2535
2536 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2537 {
2538 struct ixgbe_hw *hw = &adapter->hw;
2539
2540 adapter->lsc_int++;
2541 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2542 adapter->link_check_timeout = jiffies;
2543 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2544 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2545 IXGBE_WRITE_FLUSH(hw);
2546 ixgbe_service_event_schedule(adapter);
2547 }
2548 }
2549
2550 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2551 u64 qmask)
2552 {
2553 u32 mask;
2554 struct ixgbe_hw *hw = &adapter->hw;
2555
2556 switch (hw->mac.type) {
2557 case ixgbe_mac_82598EB:
2558 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2559 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2560 break;
2561 case ixgbe_mac_82599EB:
2562 case ixgbe_mac_X540:
2563 case ixgbe_mac_X550:
2564 case ixgbe_mac_X550EM_x:
2565 mask = (qmask & 0xFFFFFFFF);
2566 if (mask)
2567 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2568 mask = (qmask >> 32);
2569 if (mask)
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2571 break;
2572 default:
2573 break;
2574 }
2575 /* skip the flush */
2576 }
2577
2578 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2579 u64 qmask)
2580 {
2581 u32 mask;
2582 struct ixgbe_hw *hw = &adapter->hw;
2583
2584 switch (hw->mac.type) {
2585 case ixgbe_mac_82598EB:
2586 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2587 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2588 break;
2589 case ixgbe_mac_82599EB:
2590 case ixgbe_mac_X540:
2591 case ixgbe_mac_X550:
2592 case ixgbe_mac_X550EM_x:
2593 mask = (qmask & 0xFFFFFFFF);
2594 if (mask)
2595 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2596 mask = (qmask >> 32);
2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2599 break;
2600 default:
2601 break;
2602 }
2603 /* skip the flush */
2604 }
2605
2606 /**
2607 * ixgbe_irq_enable - Enable default interrupt generation settings
2608 * @adapter: board private structure
2609 **/
2610 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2611 bool flush)
2612 {
2613 struct ixgbe_hw *hw = &adapter->hw;
2614 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2615
2616 /* don't reenable LSC while waiting for link */
2617 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2618 mask &= ~IXGBE_EIMS_LSC;
2619
2620 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2621 switch (adapter->hw.mac.type) {
2622 case ixgbe_mac_82599EB:
2623 mask |= IXGBE_EIMS_GPI_SDP0(hw);
2624 break;
2625 case ixgbe_mac_X540:
2626 case ixgbe_mac_X550:
2627 case ixgbe_mac_X550EM_x:
2628 mask |= IXGBE_EIMS_TS;
2629 break;
2630 default:
2631 break;
2632 }
2633 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2634 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2635 switch (adapter->hw.mac.type) {
2636 case ixgbe_mac_82599EB:
2637 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2638 mask |= IXGBE_EIMS_GPI_SDP2(hw);
2639 /* fall through */
2640 case ixgbe_mac_X540:
2641 case ixgbe_mac_X550:
2642 case ixgbe_mac_X550EM_x:
2643 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2644 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
2645 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2646 mask |= IXGBE_EICR_GPI_SDP0_X540;
2647 mask |= IXGBE_EIMS_ECC;
2648 mask |= IXGBE_EIMS_MAILBOX;
2649 break;
2650 default:
2651 break;
2652 }
2653
2654 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2655 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2656 mask |= IXGBE_EIMS_FLOW_DIR;
2657
2658 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2659 if (queues)
2660 ixgbe_irq_enable_queues(adapter, ~0);
2661 if (flush)
2662 IXGBE_WRITE_FLUSH(&adapter->hw);
2663 }
2664
2665 static irqreturn_t ixgbe_msix_other(int irq, void *data)
2666 {
2667 struct ixgbe_adapter *adapter = data;
2668 struct ixgbe_hw *hw = &adapter->hw;
2669 u32 eicr;
2670
2671 /*
2672 * Workaround for Silicon errata. Use clear-by-write instead
2673 * of clear-by-read. Reading with EICS will return the
2674 * interrupt causes without clearing, which later be done
2675 * with the write to EICR.
2676 */
2677 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2678
2679 /* The lower 16bits of the EICR register are for the queue interrupts
2680 * which should be masked here in order to not accidentally clear them if
2681 * the bits are high when ixgbe_msix_other is called. There is a race
2682 * condition otherwise which results in possible performance loss
2683 * especially if the ixgbe_msix_other interrupt is triggering
2684 * consistently (as it would when PPS is turned on for the X540 device)
2685 */
2686 eicr &= 0xFFFF0000;
2687
2688 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
2689
2690 if (eicr & IXGBE_EICR_LSC)
2691 ixgbe_check_lsc(adapter);
2692
2693 if (eicr & IXGBE_EICR_MAILBOX)
2694 ixgbe_msg_task(adapter);
2695
2696 switch (hw->mac.type) {
2697 case ixgbe_mac_82599EB:
2698 case ixgbe_mac_X540:
2699 case ixgbe_mac_X550:
2700 case ixgbe_mac_X550EM_x:
2701 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2702 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2703 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2704 ixgbe_service_event_schedule(adapter);
2705 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2706 IXGBE_EICR_GPI_SDP0_X540);
2707 }
2708 if (eicr & IXGBE_EICR_ECC) {
2709 e_info(link, "Received ECC Err, initiating reset\n");
2710 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2711 ixgbe_service_event_schedule(adapter);
2712 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2713 }
2714 /* Handle Flow Director Full threshold interrupt */
2715 if (eicr & IXGBE_EICR_FLOW_DIR) {
2716 int reinit_count = 0;
2717 int i;
2718 for (i = 0; i < adapter->num_tx_queues; i++) {
2719 struct ixgbe_ring *ring = adapter->tx_ring[i];
2720 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
2721 &ring->state))
2722 reinit_count++;
2723 }
2724 if (reinit_count) {
2725 /* no more flow director interrupts until after init */
2726 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
2727 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2728 ixgbe_service_event_schedule(adapter);
2729 }
2730 }
2731 ixgbe_check_sfp_event(adapter, eicr);
2732 ixgbe_check_overtemp_event(adapter, eicr);
2733 break;
2734 default:
2735 break;
2736 }
2737
2738 ixgbe_check_fan_failure(adapter, eicr);
2739
2740 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2741 ixgbe_ptp_check_pps_event(adapter, eicr);
2742
2743 /* re-enable the original interrupt state, no lsc, no queues */
2744 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2745 ixgbe_irq_enable(adapter, false, false);
2746
2747 return IRQ_HANDLED;
2748 }
2749
2750 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
2751 {
2752 struct ixgbe_q_vector *q_vector = data;
2753
2754 /* EIAM disabled interrupts (on this vector) for us */
2755
2756 if (q_vector->rx.ring || q_vector->tx.ring)
2757 napi_schedule(&q_vector->napi);
2758
2759 return IRQ_HANDLED;
2760 }
2761
2762 /**
2763 * ixgbe_poll - NAPI Rx polling callback
2764 * @napi: structure for representing this polling device
2765 * @budget: how many packets driver is allowed to clean
2766 *
2767 * This function is used for legacy and MSI, NAPI mode
2768 **/
2769 int ixgbe_poll(struct napi_struct *napi, int budget)
2770 {
2771 struct ixgbe_q_vector *q_vector =
2772 container_of(napi, struct ixgbe_q_vector, napi);
2773 struct ixgbe_adapter *adapter = q_vector->adapter;
2774 struct ixgbe_ring *ring;
2775 int per_ring_budget, work_done = 0;
2776 bool clean_complete = true;
2777
2778 #ifdef CONFIG_IXGBE_DCA
2779 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2780 ixgbe_update_dca(q_vector);
2781 #endif
2782
2783 ixgbe_for_each_ring(ring, q_vector->tx)
2784 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2785
2786 if (!ixgbe_qv_lock_napi(q_vector))
2787 return budget;
2788
2789 /* attempt to distribute budget to each queue fairly, but don't allow
2790 * the budget to go below 1 because we'll exit polling */
2791 if (q_vector->rx.count > 1)
2792 per_ring_budget = max(budget/q_vector->rx.count, 1);
2793 else
2794 per_ring_budget = budget;
2795
2796 ixgbe_for_each_ring(ring, q_vector->rx) {
2797 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2798 per_ring_budget);
2799
2800 work_done += cleaned;
2801 clean_complete &= (cleaned < per_ring_budget);
2802 }
2803
2804 ixgbe_qv_unlock_napi(q_vector);
2805 /* If all work not completed, return budget and keep polling */
2806 if (!clean_complete)
2807 return budget;
2808
2809 /* all work done, exit the polling mode */
2810 napi_complete_done(napi, work_done);
2811 if (adapter->rx_itr_setting & 1)
2812 ixgbe_set_itr(q_vector);
2813 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2814 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2815
2816 return 0;
2817 }
2818
2819 /**
2820 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2821 * @adapter: board private structure
2822 *
2823 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2824 * interrupts from the kernel.
2825 **/
2826 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2827 {
2828 struct net_device *netdev = adapter->netdev;
2829 int vector, err;
2830 int ri = 0, ti = 0;
2831
2832 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2833 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2834 struct msix_entry *entry = &adapter->msix_entries[vector];
2835
2836 if (q_vector->tx.ring && q_vector->rx.ring) {
2837 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2838 "%s-%s-%d", netdev->name, "TxRx", ri++);
2839 ti++;
2840 } else if (q_vector->rx.ring) {
2841 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2842 "%s-%s-%d", netdev->name, "rx", ri++);
2843 } else if (q_vector->tx.ring) {
2844 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2845 "%s-%s-%d", netdev->name, "tx", ti++);
2846 } else {
2847 /* skip this unused q_vector */
2848 continue;
2849 }
2850 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2851 q_vector->name, q_vector);
2852 if (err) {
2853 e_err(probe, "request_irq failed for MSIX interrupt "
2854 "Error: %d\n", err);
2855 goto free_queue_irqs;
2856 }
2857 /* If Flow Director is enabled, set interrupt affinity */
2858 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2859 /* assign the mask for this irq */
2860 irq_set_affinity_hint(entry->vector,
2861 &q_vector->affinity_mask);
2862 }
2863 }
2864
2865 err = request_irq(adapter->msix_entries[vector].vector,
2866 ixgbe_msix_other, 0, netdev->name, adapter);
2867 if (err) {
2868 e_err(probe, "request_irq for msix_other failed: %d\n", err);
2869 goto free_queue_irqs;
2870 }
2871
2872 return 0;
2873
2874 free_queue_irqs:
2875 while (vector) {
2876 vector--;
2877 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2878 NULL);
2879 free_irq(adapter->msix_entries[vector].vector,
2880 adapter->q_vector[vector]);
2881 }
2882 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2883 pci_disable_msix(adapter->pdev);
2884 kfree(adapter->msix_entries);
2885 adapter->msix_entries = NULL;
2886 return err;
2887 }
2888
2889 /**
2890 * ixgbe_intr - legacy mode Interrupt Handler
2891 * @irq: interrupt number
2892 * @data: pointer to a network interface device structure
2893 **/
2894 static irqreturn_t ixgbe_intr(int irq, void *data)
2895 {
2896 struct ixgbe_adapter *adapter = data;
2897 struct ixgbe_hw *hw = &adapter->hw;
2898 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2899 u32 eicr;
2900
2901 /*
2902 * Workaround for silicon errata #26 on 82598. Mask the interrupt
2903 * before the read of EICR.
2904 */
2905 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2906
2907 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2908 * therefore no explicit interrupt disable is necessary */
2909 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2910 if (!eicr) {
2911 /*
2912 * shared interrupt alert!
2913 * make sure interrupts are enabled because the read will
2914 * have disabled interrupts due to EIAM
2915 * finish the workaround of silicon errata on 82598. Unmask
2916 * the interrupt that we masked before the EICR read.
2917 */
2918 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2919 ixgbe_irq_enable(adapter, true, true);
2920 return IRQ_NONE; /* Not our interrupt */
2921 }
2922
2923 if (eicr & IXGBE_EICR_LSC)
2924 ixgbe_check_lsc(adapter);
2925
2926 switch (hw->mac.type) {
2927 case ixgbe_mac_82599EB:
2928 ixgbe_check_sfp_event(adapter, eicr);
2929 /* Fall through */
2930 case ixgbe_mac_X540:
2931 case ixgbe_mac_X550:
2932 case ixgbe_mac_X550EM_x:
2933 if (eicr & IXGBE_EICR_ECC) {
2934 e_info(link, "Received ECC Err, initiating reset\n");
2935 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2936 ixgbe_service_event_schedule(adapter);
2937 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2938 }
2939 ixgbe_check_overtemp_event(adapter, eicr);
2940 break;
2941 default:
2942 break;
2943 }
2944
2945 ixgbe_check_fan_failure(adapter, eicr);
2946 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2947 ixgbe_ptp_check_pps_event(adapter, eicr);
2948
2949 /* would disable interrupts here but EIAM disabled it */
2950 napi_schedule(&q_vector->napi);
2951
2952 /*
2953 * re-enable link(maybe) and non-queue interrupts, no flush.
2954 * ixgbe_poll will re-enable the queue interrupts
2955 */
2956 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2957 ixgbe_irq_enable(adapter, false, false);
2958
2959 return IRQ_HANDLED;
2960 }
2961
2962 /**
2963 * ixgbe_request_irq - initialize interrupts
2964 * @adapter: board private structure
2965 *
2966 * Attempts to configure interrupts using the best available
2967 * capabilities of the hardware and kernel.
2968 **/
2969 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2970 {
2971 struct net_device *netdev = adapter->netdev;
2972 int err;
2973
2974 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2975 err = ixgbe_request_msix_irqs(adapter);
2976 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
2977 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2978 netdev->name, adapter);
2979 else
2980 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2981 netdev->name, adapter);
2982
2983 if (err)
2984 e_err(probe, "request_irq failed, Error %d\n", err);
2985
2986 return err;
2987 }
2988
2989 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2990 {
2991 int vector;
2992
2993 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2994 free_irq(adapter->pdev->irq, adapter);
2995 return;
2996 }
2997
2998 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2999 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3000 struct msix_entry *entry = &adapter->msix_entries[vector];
3001
3002 /* free only the irqs that were actually requested */
3003 if (!q_vector->rx.ring && !q_vector->tx.ring)
3004 continue;
3005
3006 /* clear the affinity_mask in the IRQ descriptor */
3007 irq_set_affinity_hint(entry->vector, NULL);
3008
3009 free_irq(entry->vector, q_vector);
3010 }
3011
3012 free_irq(adapter->msix_entries[vector++].vector, adapter);
3013 }
3014
3015 /**
3016 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3017 * @adapter: board private structure
3018 **/
3019 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3020 {
3021 switch (adapter->hw.mac.type) {
3022 case ixgbe_mac_82598EB:
3023 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3024 break;
3025 case ixgbe_mac_82599EB:
3026 case ixgbe_mac_X540:
3027 case ixgbe_mac_X550:
3028 case ixgbe_mac_X550EM_x:
3029 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3030 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3031 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3032 break;
3033 default:
3034 break;
3035 }
3036 IXGBE_WRITE_FLUSH(&adapter->hw);
3037 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3038 int vector;
3039
3040 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3041 synchronize_irq(adapter->msix_entries[vector].vector);
3042
3043 synchronize_irq(adapter->msix_entries[vector++].vector);
3044 } else {
3045 synchronize_irq(adapter->pdev->irq);
3046 }
3047 }
3048
3049 /**
3050 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3051 *
3052 **/
3053 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3054 {
3055 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3056
3057 ixgbe_write_eitr(q_vector);
3058
3059 ixgbe_set_ivar(adapter, 0, 0, 0);
3060 ixgbe_set_ivar(adapter, 1, 0, 0);
3061
3062 e_info(hw, "Legacy interrupt IVAR setup done\n");
3063 }
3064
3065 /**
3066 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3067 * @adapter: board private structure
3068 * @ring: structure containing ring specific data
3069 *
3070 * Configure the Tx descriptor ring after a reset.
3071 **/
3072 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3073 struct ixgbe_ring *ring)
3074 {
3075 struct ixgbe_hw *hw = &adapter->hw;
3076 u64 tdba = ring->dma;
3077 int wait_loop = 10;
3078 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3079 u8 reg_idx = ring->reg_idx;
3080
3081 /* disable queue to avoid issues while updating state */
3082 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3083 IXGBE_WRITE_FLUSH(hw);
3084
3085 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3086 (tdba & DMA_BIT_MASK(32)));
3087 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3088 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3089 ring->count * sizeof(union ixgbe_adv_tx_desc));
3090 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3091 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3092 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3093
3094 /*
3095 * set WTHRESH to encourage burst writeback, it should not be set
3096 * higher than 1 when:
3097 * - ITR is 0 as it could cause false TX hangs
3098 * - ITR is set to > 100k int/sec and BQL is enabled
3099 *
3100 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3101 * to or less than the number of on chip descriptors, which is
3102 * currently 40.
3103 */
3104 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3105 txdctl |= (1 << 16); /* WTHRESH = 1 */
3106 else
3107 txdctl |= (8 << 16); /* WTHRESH = 8 */
3108
3109 /*
3110 * Setting PTHRESH to 32 both improves performance
3111 * and avoids a TX hang with DFP enabled
3112 */
3113 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3114 32; /* PTHRESH = 32 */
3115
3116 /* reinitialize flowdirector state */
3117 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3118 ring->atr_sample_rate = adapter->atr_sample_rate;
3119 ring->atr_count = 0;
3120 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3121 } else {
3122 ring->atr_sample_rate = 0;
3123 }
3124
3125 /* initialize XPS */
3126 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3127 struct ixgbe_q_vector *q_vector = ring->q_vector;
3128
3129 if (q_vector)
3130 netif_set_xps_queue(ring->netdev,
3131 &q_vector->affinity_mask,
3132 ring->queue_index);
3133 }
3134
3135 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3136
3137 /* enable queue */
3138 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3139
3140 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3141 if (hw->mac.type == ixgbe_mac_82598EB &&
3142 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3143 return;
3144
3145 /* poll to verify queue is enabled */
3146 do {
3147 usleep_range(1000, 2000);
3148 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3149 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3150 if (!wait_loop)
3151 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
3152 }
3153
3154 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3155 {
3156 struct ixgbe_hw *hw = &adapter->hw;
3157 u32 rttdcs, mtqc;
3158 u8 tcs = netdev_get_num_tc(adapter->netdev);
3159
3160 if (hw->mac.type == ixgbe_mac_82598EB)
3161 return;
3162
3163 /* disable the arbiter while setting MTQC */
3164 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3165 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3166 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3167
3168 /* set transmit pool layout */
3169 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3170 mtqc = IXGBE_MTQC_VT_ENA;
3171 if (tcs > 4)
3172 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3173 else if (tcs > 1)
3174 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3175 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3176 mtqc |= IXGBE_MTQC_32VF;
3177 else
3178 mtqc |= IXGBE_MTQC_64VF;
3179 } else {
3180 if (tcs > 4)
3181 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3182 else if (tcs > 1)
3183 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3184 else
3185 mtqc = IXGBE_MTQC_64Q_1PB;
3186 }
3187
3188 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3189
3190 /* Enable Security TX Buffer IFG for multiple pb */
3191 if (tcs) {
3192 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3193 sectx |= IXGBE_SECTX_DCB;
3194 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3195 }
3196
3197 /* re-enable the arbiter */
3198 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3199 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3200 }
3201
3202 /**
3203 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3204 * @adapter: board private structure
3205 *
3206 * Configure the Tx unit of the MAC after a reset.
3207 **/
3208 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3209 {
3210 struct ixgbe_hw *hw = &adapter->hw;
3211 u32 dmatxctl;
3212 u32 i;
3213
3214 ixgbe_setup_mtqc(adapter);
3215
3216 if (hw->mac.type != ixgbe_mac_82598EB) {
3217 /* DMATXCTL.EN must be before Tx queues are enabled */
3218 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3219 dmatxctl |= IXGBE_DMATXCTL_TE;
3220 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3221 }
3222
3223 /* Setup the HW Tx Head and Tail descriptor pointers */
3224 for (i = 0; i < adapter->num_tx_queues; i++)
3225 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3226 }
3227
3228 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3229 struct ixgbe_ring *ring)
3230 {
3231 struct ixgbe_hw *hw = &adapter->hw;
3232 u8 reg_idx = ring->reg_idx;
3233 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3234
3235 srrctl |= IXGBE_SRRCTL_DROP_EN;
3236
3237 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3238 }
3239
3240 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3241 struct ixgbe_ring *ring)
3242 {
3243 struct ixgbe_hw *hw = &adapter->hw;
3244 u8 reg_idx = ring->reg_idx;
3245 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3246
3247 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3248
3249 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3250 }
3251
3252 #ifdef CONFIG_IXGBE_DCB
3253 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3254 #else
3255 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3256 #endif
3257 {
3258 int i;
3259 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3260
3261 if (adapter->ixgbe_ieee_pfc)
3262 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3263
3264 /*
3265 * We should set the drop enable bit if:
3266 * SR-IOV is enabled
3267 * or
3268 * Number of Rx queues > 1 and flow control is disabled
3269 *
3270 * This allows us to avoid head of line blocking for security
3271 * and performance reasons.
3272 */
3273 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3274 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3275 for (i = 0; i < adapter->num_rx_queues; i++)
3276 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3277 } else {
3278 for (i = 0; i < adapter->num_rx_queues; i++)
3279 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3280 }
3281 }
3282
3283 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3284
3285 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3286 struct ixgbe_ring *rx_ring)
3287 {
3288 struct ixgbe_hw *hw = &adapter->hw;
3289 u32 srrctl;
3290 u8 reg_idx = rx_ring->reg_idx;
3291
3292 if (hw->mac.type == ixgbe_mac_82598EB) {
3293 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3294
3295 /*
3296 * if VMDq is not active we must program one srrctl register
3297 * per RSS queue since we have enabled RDRXCTL.MVMEN
3298 */
3299 reg_idx &= mask;
3300 }
3301
3302 /* configure header buffer length, needed for RSC */
3303 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3304
3305 /* configure the packet buffer length */
3306 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3307
3308 /* configure descriptor type */
3309 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3310
3311 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3312 }
3313
3314 /**
3315 * Return a number of entries in the RSS indirection table
3316 *
3317 * @adapter: device handle
3318 *
3319 * - 82598/82599/X540: 128
3320 * - X550(non-SRIOV mode): 512
3321 * - X550(SRIOV mode): 64
3322 */
3323 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3324 {
3325 if (adapter->hw.mac.type < ixgbe_mac_X550)
3326 return 128;
3327 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3328 return 64;
3329 else
3330 return 512;
3331 }
3332
3333 /**
3334 * Write the RETA table to HW
3335 *
3336 * @adapter: device handle
3337 *
3338 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3339 */
3340 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3341 {
3342 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3343 struct ixgbe_hw *hw = &adapter->hw;
3344 u32 reta = 0;
3345 u32 indices_multi;
3346 u8 *indir_tbl = adapter->rss_indir_tbl;
3347
3348 /* Fill out the redirection table as follows:
3349 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3350 * indices.
3351 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3352 * - X550: 8 bit wide entries containing 6 bit RSS index
3353 */
3354 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3355 indices_multi = 0x11;
3356 else
3357 indices_multi = 0x1;
3358
3359 /* Write redirection table to HW */
3360 for (i = 0; i < reta_entries; i++) {
3361 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3362 if ((i & 3) == 3) {
3363 if (i < 128)
3364 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3365 else
3366 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3367 reta);
3368 reta = 0;
3369 }
3370 }
3371 }
3372
3373 /**
3374 * Write the RETA table to HW (for x550 devices in SRIOV mode)
3375 *
3376 * @adapter: device handle
3377 *
3378 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3379 */
3380 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3381 {
3382 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3383 struct ixgbe_hw *hw = &adapter->hw;
3384 u32 vfreta = 0;
3385 unsigned int pf_pool = adapter->num_vfs;
3386
3387 /* Write redirection table to HW */
3388 for (i = 0; i < reta_entries; i++) {
3389 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3390 if ((i & 3) == 3) {
3391 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3392 vfreta);
3393 vfreta = 0;
3394 }
3395 }
3396 }
3397
3398 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3399 {
3400 struct ixgbe_hw *hw = &adapter->hw;
3401 u32 i, j;
3402 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3403 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3404
3405 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3406 * make full use of any rings they may have. We will use the
3407 * PSRTYPE register to control how many rings we use within the PF.
3408 */
3409 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3410 rss_i = 2;
3411
3412 /* Fill out hash function seeds */
3413 for (i = 0; i < 10; i++)
3414 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3415
3416 /* Fill out redirection table */
3417 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3418
3419 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3420 if (j == rss_i)
3421 j = 0;
3422
3423 adapter->rss_indir_tbl[i] = j;
3424 }
3425
3426 ixgbe_store_reta(adapter);
3427 }
3428
3429 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3430 {
3431 struct ixgbe_hw *hw = &adapter->hw;
3432 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3433 unsigned int pf_pool = adapter->num_vfs;
3434 int i, j;
3435
3436 /* Fill out hash function seeds */
3437 for (i = 0; i < 10; i++)
3438 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3439 adapter->rss_key[i]);
3440
3441 /* Fill out the redirection table */
3442 for (i = 0, j = 0; i < 64; i++, j++) {
3443 if (j == rss_i)
3444 j = 0;
3445
3446 adapter->rss_indir_tbl[i] = j;
3447 }
3448
3449 ixgbe_store_vfreta(adapter);
3450 }
3451
3452 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3453 {
3454 struct ixgbe_hw *hw = &adapter->hw;
3455 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3456 u32 rxcsum;
3457
3458 /* Disable indicating checksum in descriptor, enables RSS hash */
3459 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3460 rxcsum |= IXGBE_RXCSUM_PCSD;
3461 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3462
3463 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3464 if (adapter->ring_feature[RING_F_RSS].mask)
3465 mrqc = IXGBE_MRQC_RSSEN;
3466 } else {
3467 u8 tcs = netdev_get_num_tc(adapter->netdev);
3468
3469 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3470 if (tcs > 4)
3471 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3472 else if (tcs > 1)
3473 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3474 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3475 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3476 else
3477 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3478 } else {
3479 if (tcs > 4)
3480 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3481 else if (tcs > 1)
3482 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3483 else
3484 mrqc = IXGBE_MRQC_RSSEN;
3485 }
3486 }
3487
3488 /* Perform hash on these packet types */
3489 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3490 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3491 IXGBE_MRQC_RSS_FIELD_IPV6 |
3492 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3493
3494 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3495 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3496 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3497 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3498
3499 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
3500 if ((hw->mac.type >= ixgbe_mac_X550) &&
3501 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3502 unsigned int pf_pool = adapter->num_vfs;
3503
3504 /* Enable VF RSS mode */
3505 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3506 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3507
3508 /* Setup RSS through the VF registers */
3509 ixgbe_setup_vfreta(adapter);
3510 vfmrqc = IXGBE_MRQC_RSSEN;
3511 vfmrqc |= rss_field;
3512 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3513 } else {
3514 ixgbe_setup_reta(adapter);
3515 mrqc |= rss_field;
3516 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3517 }
3518 }
3519
3520 /**
3521 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3522 * @adapter: address of board private structure
3523 * @index: index of ring to set
3524 **/
3525 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3526 struct ixgbe_ring *ring)
3527 {
3528 struct ixgbe_hw *hw = &adapter->hw;
3529 u32 rscctrl;
3530 u8 reg_idx = ring->reg_idx;
3531
3532 if (!ring_is_rsc_enabled(ring))
3533 return;
3534
3535 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3536 rscctrl |= IXGBE_RSCCTL_RSCEN;
3537 /*
3538 * we must limit the number of descriptors so that the
3539 * total size of max desc * buf_len is not greater
3540 * than 65536
3541 */
3542 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3543 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3544 }
3545
3546 #define IXGBE_MAX_RX_DESC_POLL 10
3547 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3548 struct ixgbe_ring *ring)
3549 {
3550 struct ixgbe_hw *hw = &adapter->hw;
3551 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3552 u32 rxdctl;
3553 u8 reg_idx = ring->reg_idx;
3554
3555 if (ixgbe_removed(hw->hw_addr))
3556 return;
3557 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3558 if (hw->mac.type == ixgbe_mac_82598EB &&
3559 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3560 return;
3561
3562 do {
3563 usleep_range(1000, 2000);
3564 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3565 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3566
3567 if (!wait_loop) {
3568 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3569 "the polling period\n", reg_idx);
3570 }
3571 }
3572
3573 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3574 struct ixgbe_ring *ring)
3575 {
3576 struct ixgbe_hw *hw = &adapter->hw;
3577 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3578 u32 rxdctl;
3579 u8 reg_idx = ring->reg_idx;
3580
3581 if (ixgbe_removed(hw->hw_addr))
3582 return;
3583 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3584 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3585
3586 /* write value back with RXDCTL.ENABLE bit cleared */
3587 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3588
3589 if (hw->mac.type == ixgbe_mac_82598EB &&
3590 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3591 return;
3592
3593 /* the hardware may take up to 100us to really disable the rx queue */
3594 do {
3595 udelay(10);
3596 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3597 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3598
3599 if (!wait_loop) {
3600 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3601 "the polling period\n", reg_idx);
3602 }
3603 }
3604
3605 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3606 struct ixgbe_ring *ring)
3607 {
3608 struct ixgbe_hw *hw = &adapter->hw;
3609 u64 rdba = ring->dma;
3610 u32 rxdctl;
3611 u8 reg_idx = ring->reg_idx;
3612
3613 /* disable queue to avoid issues while updating state */
3614 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3615 ixgbe_disable_rx_queue(adapter, ring);
3616
3617 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3618 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3619 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3620 ring->count * sizeof(union ixgbe_adv_rx_desc));
3621 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3622 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3623 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
3624
3625 ixgbe_configure_srrctl(adapter, ring);
3626 ixgbe_configure_rscctl(adapter, ring);
3627
3628 if (hw->mac.type == ixgbe_mac_82598EB) {
3629 /*
3630 * enable cache line friendly hardware writes:
3631 * PTHRESH=32 descriptors (half the internal cache),
3632 * this also removes ugly rx_no_buffer_count increment
3633 * HTHRESH=4 descriptors (to minimize latency on fetch)
3634 * WTHRESH=8 burst writeback up to two cache lines
3635 */
3636 rxdctl &= ~0x3FFFFF;
3637 rxdctl |= 0x080420;
3638 }
3639
3640 /* enable receive descriptor ring */
3641 rxdctl |= IXGBE_RXDCTL_ENABLE;
3642 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3643
3644 ixgbe_rx_desc_queue_enable(adapter, ring);
3645 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3646 }
3647
3648 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3649 {
3650 struct ixgbe_hw *hw = &adapter->hw;
3651 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
3652 u16 pool;
3653
3654 /* PSRTYPE must be initialized in non 82598 adapters */
3655 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3656 IXGBE_PSRTYPE_UDPHDR |
3657 IXGBE_PSRTYPE_IPV4HDR |
3658 IXGBE_PSRTYPE_L2HDR |
3659 IXGBE_PSRTYPE_IPV6HDR;
3660
3661 if (hw->mac.type == ixgbe_mac_82598EB)
3662 return;
3663
3664 if (rss_i > 3)
3665 psrtype |= 2 << 29;
3666 else if (rss_i > 1)
3667 psrtype |= 1 << 29;
3668
3669 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3670 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
3671 }
3672
3673 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3674 {
3675 struct ixgbe_hw *hw = &adapter->hw;
3676 u32 reg_offset, vf_shift;
3677 u32 gcr_ext, vmdctl;
3678 int i;
3679
3680 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3681 return;
3682
3683 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3684 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3685 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
3686 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
3687 vmdctl |= IXGBE_VT_CTL_REPLEN;
3688 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
3689
3690 vf_shift = VMDQ_P(0) % 32;
3691 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
3692
3693 /* Enable only the PF's pool for Tx/Rx */
3694 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3695 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3696 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3697 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
3698 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
3699 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3700
3701 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3702 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
3703
3704 /*
3705 * Set up VF register offsets for selected VT Mode,
3706 * i.e. 32 or 64 VFs for SR-IOV
3707 */
3708 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3709 case IXGBE_82599_VMDQ_8Q_MASK:
3710 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3711 break;
3712 case IXGBE_82599_VMDQ_4Q_MASK:
3713 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3714 break;
3715 default:
3716 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3717 break;
3718 }
3719
3720 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3721
3722
3723 /* Enable MAC Anti-Spoofing */
3724 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3725 adapter->num_vfs);
3726
3727 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
3728 * calling set_ethertype_anti_spoofing for each VF in loop below
3729 */
3730 if (hw->mac.ops.set_ethertype_anti_spoofing) {
3731 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3732 (IXGBE_ETQF_FILTER_EN |
3733 IXGBE_ETQF_TX_ANTISPOOF |
3734 IXGBE_ETH_P_LLDP));
3735
3736 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3737 (IXGBE_ETQF_FILTER_EN |
3738 IXGBE_ETQF_TX_ANTISPOOF |
3739 ETH_P_PAUSE));
3740 }
3741
3742 /* For VFs that have spoof checking turned off */
3743 for (i = 0; i < adapter->num_vfs; i++) {
3744 if (!adapter->vfinfo[i].spoofchk_enabled)
3745 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3746
3747 /* enable ethertype anti spoofing if hw supports it */
3748 if (hw->mac.ops.set_ethertype_anti_spoofing)
3749 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
3750
3751 /* Enable/Disable RSS query feature */
3752 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3753 adapter->vfinfo[i].rss_query_enabled);
3754 }
3755 }
3756
3757 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3758 {
3759 struct ixgbe_hw *hw = &adapter->hw;
3760 struct net_device *netdev = adapter->netdev;
3761 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3762 struct ixgbe_ring *rx_ring;
3763 int i;
3764 u32 mhadd, hlreg0;
3765
3766 #ifdef IXGBE_FCOE
3767 /* adjust max frame to be able to do baby jumbo for FCoE */
3768 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3769 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3770 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3771
3772 #endif /* IXGBE_FCOE */
3773
3774 /* adjust max frame to be at least the size of a standard frame */
3775 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3776 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3777
3778 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3779 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3780 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3781 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3782
3783 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3784 }
3785
3786 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3787 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3788 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3789 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3790
3791 /*
3792 * Setup the HW Rx Head and Tail Descriptor Pointers and
3793 * the Base and Length of the Rx Descriptor Ring
3794 */
3795 for (i = 0; i < adapter->num_rx_queues; i++) {
3796 rx_ring = adapter->rx_ring[i];
3797 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3798 set_ring_rsc_enabled(rx_ring);
3799 else
3800 clear_ring_rsc_enabled(rx_ring);
3801 }
3802 }
3803
3804 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3805 {
3806 struct ixgbe_hw *hw = &adapter->hw;
3807 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3808
3809 switch (hw->mac.type) {
3810 case ixgbe_mac_82598EB:
3811 /*
3812 * For VMDq support of different descriptor types or
3813 * buffer sizes through the use of multiple SRRCTL
3814 * registers, RDRXCTL.MVMEN must be set to 1
3815 *
3816 * also, the manual doesn't mention it clearly but DCA hints
3817 * will only use queue 0's tags unless this bit is set. Side
3818 * effects of setting this bit are only that SRRCTL must be
3819 * fully programmed [0..15]
3820 */
3821 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3822 break;
3823 case ixgbe_mac_X550:
3824 case ixgbe_mac_X550EM_x:
3825 if (adapter->num_vfs)
3826 rdrxctl |= IXGBE_RDRXCTL_PSP;
3827 /* fall through for older HW */
3828 case ixgbe_mac_82599EB:
3829 case ixgbe_mac_X540:
3830 /* Disable RSC for ACK packets */
3831 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3832 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3833 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3834 /* hardware requires some bits to be set by default */
3835 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3836 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3837 break;
3838 default:
3839 /* We should do nothing since we don't know this hardware */
3840 return;
3841 }
3842
3843 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3844 }
3845
3846 /**
3847 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3848 * @adapter: board private structure
3849 *
3850 * Configure the Rx unit of the MAC after a reset.
3851 **/
3852 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3853 {
3854 struct ixgbe_hw *hw = &adapter->hw;
3855 int i;
3856 u32 rxctrl, rfctl;
3857
3858 /* disable receives while setting up the descriptors */
3859 hw->mac.ops.disable_rx(hw);
3860
3861 ixgbe_setup_psrtype(adapter);
3862 ixgbe_setup_rdrxctl(adapter);
3863
3864 /* RSC Setup */
3865 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3866 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3867 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3868 rfctl |= IXGBE_RFCTL_RSC_DIS;
3869 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3870
3871 /* Program registers for the distribution of queues */
3872 ixgbe_setup_mrqc(adapter);
3873
3874 /* set_rx_buffer_len must be called before ring initialization */
3875 ixgbe_set_rx_buffer_len(adapter);
3876
3877 /*
3878 * Setup the HW Rx Head and Tail Descriptor Pointers and
3879 * the Base and Length of the Rx Descriptor Ring
3880 */
3881 for (i = 0; i < adapter->num_rx_queues; i++)
3882 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3883
3884 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3885 /* disable drop enable for 82598 parts */
3886 if (hw->mac.type == ixgbe_mac_82598EB)
3887 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3888
3889 /* enable all receives */
3890 rxctrl |= IXGBE_RXCTRL_RXEN;
3891 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3892 }
3893
3894 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3895 __be16 proto, u16 vid)
3896 {
3897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3898 struct ixgbe_hw *hw = &adapter->hw;
3899
3900 /* add VID to filter table */
3901 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
3902 set_bit(vid, adapter->active_vlans);
3903
3904 return 0;
3905 }
3906
3907 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3908 __be16 proto, u16 vid)
3909 {
3910 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3911 struct ixgbe_hw *hw = &adapter->hw;
3912
3913 /* remove VID from filter table */
3914 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
3915 clear_bit(vid, adapter->active_vlans);
3916
3917 return 0;
3918 }
3919
3920 /**
3921 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3922 * @adapter: driver data
3923 */
3924 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3925 {
3926 struct ixgbe_hw *hw = &adapter->hw;
3927 u32 vlnctrl;
3928 int i, j;
3929
3930 switch (hw->mac.type) {
3931 case ixgbe_mac_82598EB:
3932 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3933 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3934 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3935 break;
3936 case ixgbe_mac_82599EB:
3937 case ixgbe_mac_X540:
3938 case ixgbe_mac_X550:
3939 case ixgbe_mac_X550EM_x:
3940 for (i = 0; i < adapter->num_rx_queues; i++) {
3941 struct ixgbe_ring *ring = adapter->rx_ring[i];
3942
3943 if (ring->l2_accel_priv)
3944 continue;
3945 j = ring->reg_idx;
3946 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3947 vlnctrl &= ~IXGBE_RXDCTL_VME;
3948 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3949 }
3950 break;
3951 default:
3952 break;
3953 }
3954 }
3955
3956 /**
3957 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3958 * @adapter: driver data
3959 */
3960 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3961 {
3962 struct ixgbe_hw *hw = &adapter->hw;
3963 u32 vlnctrl;
3964 int i, j;
3965
3966 switch (hw->mac.type) {
3967 case ixgbe_mac_82598EB:
3968 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3969 vlnctrl |= IXGBE_VLNCTRL_VME;
3970 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3971 break;
3972 case ixgbe_mac_82599EB:
3973 case ixgbe_mac_X540:
3974 case ixgbe_mac_X550:
3975 case ixgbe_mac_X550EM_x:
3976 for (i = 0; i < adapter->num_rx_queues; i++) {
3977 struct ixgbe_ring *ring = adapter->rx_ring[i];
3978
3979 if (ring->l2_accel_priv)
3980 continue;
3981 j = ring->reg_idx;
3982 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3983 vlnctrl |= IXGBE_RXDCTL_VME;
3984 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3985 }
3986 break;
3987 default:
3988 break;
3989 }
3990 }
3991
3992 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3993 {
3994 u16 vid;
3995
3996 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
3997
3998 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3999 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4000 }
4001
4002 /**
4003 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4004 * @netdev: network interface device structure
4005 *
4006 * Writes multicast address list to the MTA hash table.
4007 * Returns: -ENOMEM on failure
4008 * 0 on no addresses written
4009 * X on writing X addresses to MTA
4010 **/
4011 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4012 {
4013 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4014 struct ixgbe_hw *hw = &adapter->hw;
4015
4016 if (!netif_running(netdev))
4017 return 0;
4018
4019 if (hw->mac.ops.update_mc_addr_list)
4020 hw->mac.ops.update_mc_addr_list(hw, netdev);
4021 else
4022 return -ENOMEM;
4023
4024 #ifdef CONFIG_PCI_IOV
4025 ixgbe_restore_vf_multicasts(adapter);
4026 #endif
4027
4028 return netdev_mc_count(netdev);
4029 }
4030
4031 #ifdef CONFIG_PCI_IOV
4032 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4033 {
4034 struct ixgbe_hw *hw = &adapter->hw;
4035 int i;
4036 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4037 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4038 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
4039 adapter->mac_table[i].queue,
4040 IXGBE_RAH_AV);
4041 else
4042 hw->mac.ops.clear_rar(hw, i);
4043
4044 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
4045 }
4046 }
4047 #endif
4048
4049 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4050 {
4051 struct ixgbe_hw *hw = &adapter->hw;
4052 int i;
4053 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4054 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
4055 if (adapter->mac_table[i].state &
4056 IXGBE_MAC_STATE_IN_USE)
4057 hw->mac.ops.set_rar(hw, i,
4058 adapter->mac_table[i].addr,
4059 adapter->mac_table[i].queue,
4060 IXGBE_RAH_AV);
4061 else
4062 hw->mac.ops.clear_rar(hw, i);
4063
4064 adapter->mac_table[i].state &=
4065 ~(IXGBE_MAC_STATE_MODIFIED);
4066 }
4067 }
4068 }
4069
4070 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4071 {
4072 int i;
4073 struct ixgbe_hw *hw = &adapter->hw;
4074
4075 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4076 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4077 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
4078 eth_zero_addr(adapter->mac_table[i].addr);
4079 adapter->mac_table[i].queue = 0;
4080 }
4081 ixgbe_sync_mac_table(adapter);
4082 }
4083
4084 static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
4085 {
4086 struct ixgbe_hw *hw = &adapter->hw;
4087 int i, count = 0;
4088
4089 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4090 if (adapter->mac_table[i].state == 0)
4091 count++;
4092 }
4093 return count;
4094 }
4095
4096 /* this function destroys the first RAR entry */
4097 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4098 u8 *addr)
4099 {
4100 struct ixgbe_hw *hw = &adapter->hw;
4101
4102 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4103 adapter->mac_table[0].queue = VMDQ_P(0);
4104 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4105 IXGBE_MAC_STATE_IN_USE);
4106 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4107 adapter->mac_table[0].queue,
4108 IXGBE_RAH_AV);
4109 }
4110
4111 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4112 {
4113 struct ixgbe_hw *hw = &adapter->hw;
4114 int i;
4115
4116 if (is_zero_ether_addr(addr))
4117 return -EINVAL;
4118
4119 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4120 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4121 continue;
4122 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4123 IXGBE_MAC_STATE_IN_USE);
4124 ether_addr_copy(adapter->mac_table[i].addr, addr);
4125 adapter->mac_table[i].queue = queue;
4126 ixgbe_sync_mac_table(adapter);
4127 return i;
4128 }
4129 return -ENOMEM;
4130 }
4131
4132 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4133 {
4134 /* search table for addr, if found, set to 0 and sync */
4135 int i;
4136 struct ixgbe_hw *hw = &adapter->hw;
4137
4138 if (is_zero_ether_addr(addr))
4139 return -EINVAL;
4140
4141 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4142 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4143 adapter->mac_table[i].queue == queue) {
4144 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4145 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
4146 eth_zero_addr(adapter->mac_table[i].addr);
4147 adapter->mac_table[i].queue = 0;
4148 ixgbe_sync_mac_table(adapter);
4149 return 0;
4150 }
4151 }
4152 return -ENOMEM;
4153 }
4154 /**
4155 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4156 * @netdev: network interface device structure
4157 *
4158 * Writes unicast address list to the RAR table.
4159 * Returns: -ENOMEM on failure/insufficient address space
4160 * 0 on no addresses written
4161 * X on writing X addresses to the RAR table
4162 **/
4163 static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
4164 {
4165 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4166 int count = 0;
4167
4168 /* return ENOMEM indicating insufficient memory for addresses */
4169 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
4170 return -ENOMEM;
4171
4172 if (!netdev_uc_empty(netdev)) {
4173 struct netdev_hw_addr *ha;
4174 netdev_for_each_uc_addr(ha, netdev) {
4175 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4176 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
4177 count++;
4178 }
4179 }
4180 return count;
4181 }
4182
4183 /**
4184 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4185 * @netdev: network interface device structure
4186 *
4187 * The set_rx_method entry point is called whenever the unicast/multicast
4188 * address list or the network interface flags are updated. This routine is
4189 * responsible for configuring the hardware for proper unicast, multicast and
4190 * promiscuous mode.
4191 **/
4192 void ixgbe_set_rx_mode(struct net_device *netdev)
4193 {
4194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4195 struct ixgbe_hw *hw = &adapter->hw;
4196 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4197 u32 vlnctrl;
4198 int count;
4199
4200 /* Check for Promiscuous and All Multicast modes */
4201 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4202 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4203
4204 /* set all bits that we expect to always be set */
4205 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4206 fctrl |= IXGBE_FCTRL_BAM;
4207 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4208 fctrl |= IXGBE_FCTRL_PMCF;
4209
4210 /* clear the bits we are changing the status of */
4211 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4212 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4213 if (netdev->flags & IFF_PROMISC) {
4214 hw->addr_ctrl.user_set_promisc = true;
4215 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4216 vmolr |= IXGBE_VMOLR_MPE;
4217 /* Only disable hardware filter vlans in promiscuous mode
4218 * if SR-IOV and VMDQ are disabled - otherwise ensure
4219 * that hardware VLAN filters remain enabled.
4220 */
4221 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4222 IXGBE_FLAG_SRIOV_ENABLED))
4223 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4224 } else {
4225 if (netdev->flags & IFF_ALLMULTI) {
4226 fctrl |= IXGBE_FCTRL_MPE;
4227 vmolr |= IXGBE_VMOLR_MPE;
4228 }
4229 vlnctrl |= IXGBE_VLNCTRL_VFE;
4230 hw->addr_ctrl.user_set_promisc = false;
4231 }
4232
4233 /*
4234 * Write addresses to available RAR registers, if there is not
4235 * sufficient space to store all the addresses then enable
4236 * unicast promiscuous mode
4237 */
4238 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
4239 if (count < 0) {
4240 fctrl |= IXGBE_FCTRL_UPE;
4241 vmolr |= IXGBE_VMOLR_ROPE;
4242 }
4243
4244 /* Write addresses to the MTA, if the attempt fails
4245 * then we should just turn on promiscuous mode so
4246 * that we can at least receive multicast traffic
4247 */
4248 count = ixgbe_write_mc_addr_list(netdev);
4249 if (count < 0) {
4250 fctrl |= IXGBE_FCTRL_MPE;
4251 vmolr |= IXGBE_VMOLR_MPE;
4252 } else if (count) {
4253 vmolr |= IXGBE_VMOLR_ROMPE;
4254 }
4255
4256 if (hw->mac.type != ixgbe_mac_82598EB) {
4257 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4258 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4259 IXGBE_VMOLR_ROPE);
4260 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4261 }
4262
4263 /* This is useful for sniffing bad packets. */
4264 if (adapter->netdev->features & NETIF_F_RXALL) {
4265 /* UPE and MPE will be handled by normal PROMISC logic
4266 * in e1000e_set_rx_mode */
4267 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4268 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4269 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4270
4271 fctrl &= ~(IXGBE_FCTRL_DPF);
4272 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4273 }
4274
4275 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4276 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4277
4278 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
4279 ixgbe_vlan_strip_enable(adapter);
4280 else
4281 ixgbe_vlan_strip_disable(adapter);
4282 }
4283
4284 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4285 {
4286 int q_idx;
4287
4288 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4289 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
4290 napi_enable(&adapter->q_vector[q_idx]->napi);
4291 }
4292 }
4293
4294 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4295 {
4296 int q_idx;
4297
4298 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4299 napi_disable(&adapter->q_vector[q_idx]->napi);
4300 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
4301 pr_info("QV %d locked\n", q_idx);
4302 usleep_range(1000, 20000);
4303 }
4304 }
4305 }
4306
4307 static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4308 {
4309 switch (adapter->hw.mac.type) {
4310 case ixgbe_mac_X550:
4311 case ixgbe_mac_X550EM_x:
4312 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4313 #ifdef CONFIG_IXGBE_VXLAN
4314 adapter->vxlan_port = 0;
4315 #endif
4316 break;
4317 default:
4318 break;
4319 }
4320 }
4321
4322 #ifdef CONFIG_IXGBE_DCB
4323 /**
4324 * ixgbe_configure_dcb - Configure DCB hardware
4325 * @adapter: ixgbe adapter struct
4326 *
4327 * This is called by the driver on open to configure the DCB hardware.
4328 * This is also called by the gennetlink interface when reconfiguring
4329 * the DCB state.
4330 */
4331 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4332 {
4333 struct ixgbe_hw *hw = &adapter->hw;
4334 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4335
4336 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4337 if (hw->mac.type == ixgbe_mac_82598EB)
4338 netif_set_gso_max_size(adapter->netdev, 65536);
4339 return;
4340 }
4341
4342 if (hw->mac.type == ixgbe_mac_82598EB)
4343 netif_set_gso_max_size(adapter->netdev, 32768);
4344
4345 #ifdef IXGBE_FCOE
4346 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4347 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
4348 #endif
4349
4350 /* reconfigure the hardware */
4351 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
4352 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4353 DCB_TX_CONFIG);
4354 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4355 DCB_RX_CONFIG);
4356 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
4357 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4358 ixgbe_dcb_hw_ets(&adapter->hw,
4359 adapter->ixgbe_ieee_ets,
4360 max_frame);
4361 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4362 adapter->ixgbe_ieee_pfc->pfc_en,
4363 adapter->ixgbe_ieee_ets->prio_tc);
4364 }
4365
4366 /* Enable RSS Hash per TC */
4367 if (hw->mac.type != ixgbe_mac_82598EB) {
4368 u32 msb = 0;
4369 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
4370
4371 while (rss_i) {
4372 msb++;
4373 rss_i >>= 1;
4374 }
4375
4376 /* write msb to all 8 TCs in one write */
4377 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
4378 }
4379 }
4380 #endif
4381
4382 /* Additional bittime to account for IXGBE framing */
4383 #define IXGBE_ETH_FRAMING 20
4384
4385 /**
4386 * ixgbe_hpbthresh - calculate high water mark for flow control
4387 *
4388 * @adapter: board private structure to calculate for
4389 * @pb: packet buffer to calculate
4390 */
4391 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4392 {
4393 struct ixgbe_hw *hw = &adapter->hw;
4394 struct net_device *dev = adapter->netdev;
4395 int link, tc, kb, marker;
4396 u32 dv_id, rx_pba;
4397
4398 /* Calculate max LAN frame size */
4399 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4400
4401 #ifdef IXGBE_FCOE
4402 /* FCoE traffic class uses FCOE jumbo frames */
4403 if ((dev->features & NETIF_F_FCOE_MTU) &&
4404 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4405 (pb == ixgbe_fcoe_get_tc(adapter)))
4406 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4407 #endif
4408
4409 /* Calculate delay value for device */
4410 switch (hw->mac.type) {
4411 case ixgbe_mac_X540:
4412 case ixgbe_mac_X550:
4413 case ixgbe_mac_X550EM_x:
4414 dv_id = IXGBE_DV_X540(link, tc);
4415 break;
4416 default:
4417 dv_id = IXGBE_DV(link, tc);
4418 break;
4419 }
4420
4421 /* Loopback switch introduces additional latency */
4422 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4423 dv_id += IXGBE_B2BT(tc);
4424
4425 /* Delay value is calculated in bit times convert to KB */
4426 kb = IXGBE_BT2KB(dv_id);
4427 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4428
4429 marker = rx_pba - kb;
4430
4431 /* It is possible that the packet buffer is not large enough
4432 * to provide required headroom. In this case throw an error
4433 * to user and a do the best we can.
4434 */
4435 if (marker < 0) {
4436 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4437 "headroom to support flow control."
4438 "Decrease MTU or number of traffic classes\n", pb);
4439 marker = tc + 1;
4440 }
4441
4442 return marker;
4443 }
4444
4445 /**
4446 * ixgbe_lpbthresh - calculate low water mark for for flow control
4447 *
4448 * @adapter: board private structure to calculate for
4449 * @pb: packet buffer to calculate
4450 */
4451 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
4452 {
4453 struct ixgbe_hw *hw = &adapter->hw;
4454 struct net_device *dev = adapter->netdev;
4455 int tc;
4456 u32 dv_id;
4457
4458 /* Calculate max LAN frame size */
4459 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4460
4461 #ifdef IXGBE_FCOE
4462 /* FCoE traffic class uses FCOE jumbo frames */
4463 if ((dev->features & NETIF_F_FCOE_MTU) &&
4464 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4465 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4466 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4467 #endif
4468
4469 /* Calculate delay value for device */
4470 switch (hw->mac.type) {
4471 case ixgbe_mac_X540:
4472 case ixgbe_mac_X550:
4473 case ixgbe_mac_X550EM_x:
4474 dv_id = IXGBE_LOW_DV_X540(tc);
4475 break;
4476 default:
4477 dv_id = IXGBE_LOW_DV(tc);
4478 break;
4479 }
4480
4481 /* Delay value is calculated in bit times convert to KB */
4482 return IXGBE_BT2KB(dv_id);
4483 }
4484
4485 /*
4486 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4487 */
4488 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4489 {
4490 struct ixgbe_hw *hw = &adapter->hw;
4491 int num_tc = netdev_get_num_tc(adapter->netdev);
4492 int i;
4493
4494 if (!num_tc)
4495 num_tc = 1;
4496
4497 for (i = 0; i < num_tc; i++) {
4498 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4499 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
4500
4501 /* Low water marks must not be larger than high water marks */
4502 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4503 hw->fc.low_water[i] = 0;
4504 }
4505
4506 for (; i < MAX_TRAFFIC_CLASS; i++)
4507 hw->fc.high_water[i] = 0;
4508 }
4509
4510 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4511 {
4512 struct ixgbe_hw *hw = &adapter->hw;
4513 int hdrm;
4514 u8 tc = netdev_get_num_tc(adapter->netdev);
4515
4516 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4517 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4518 hdrm = 32 << adapter->fdir_pballoc;
4519 else
4520 hdrm = 0;
4521
4522 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
4523 ixgbe_pbthresh_setup(adapter);
4524 }
4525
4526 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4527 {
4528 struct ixgbe_hw *hw = &adapter->hw;
4529 struct hlist_node *node2;
4530 struct ixgbe_fdir_filter *filter;
4531
4532 spin_lock(&adapter->fdir_perfect_lock);
4533
4534 if (!hlist_empty(&adapter->fdir_filter_list))
4535 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4536
4537 hlist_for_each_entry_safe(filter, node2,
4538 &adapter->fdir_filter_list, fdir_node) {
4539 ixgbe_fdir_write_perfect_filter_82599(hw,
4540 &filter->filter,
4541 filter->sw_idx,
4542 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4543 IXGBE_FDIR_DROP_QUEUE :
4544 adapter->rx_ring[filter->action]->reg_idx);
4545 }
4546
4547 spin_unlock(&adapter->fdir_perfect_lock);
4548 }
4549
4550 static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4551 struct ixgbe_adapter *adapter)
4552 {
4553 struct ixgbe_hw *hw = &adapter->hw;
4554 u32 vmolr;
4555
4556 /* No unicast promiscuous support for VMDQ devices. */
4557 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4558 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4559
4560 /* clear the affected bit */
4561 vmolr &= ~IXGBE_VMOLR_MPE;
4562
4563 if (dev->flags & IFF_ALLMULTI) {
4564 vmolr |= IXGBE_VMOLR_MPE;
4565 } else {
4566 vmolr |= IXGBE_VMOLR_ROMPE;
4567 hw->mac.ops.update_mc_addr_list(hw, dev);
4568 }
4569 ixgbe_write_uc_addr_list(adapter->netdev, pool);
4570 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4571 }
4572
4573 static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4574 {
4575 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4576 int rss_i = adapter->num_rx_queues_per_pool;
4577 struct ixgbe_hw *hw = &adapter->hw;
4578 u16 pool = vadapter->pool;
4579 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4580 IXGBE_PSRTYPE_UDPHDR |
4581 IXGBE_PSRTYPE_IPV4HDR |
4582 IXGBE_PSRTYPE_L2HDR |
4583 IXGBE_PSRTYPE_IPV6HDR;
4584
4585 if (hw->mac.type == ixgbe_mac_82598EB)
4586 return;
4587
4588 if (rss_i > 3)
4589 psrtype |= 2 << 29;
4590 else if (rss_i > 1)
4591 psrtype |= 1 << 29;
4592
4593 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4594 }
4595
4596 /**
4597 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4598 * @rx_ring: ring to free buffers from
4599 **/
4600 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4601 {
4602 struct device *dev = rx_ring->dev;
4603 unsigned long size;
4604 u16 i;
4605
4606 /* ring already cleared, nothing to do */
4607 if (!rx_ring->rx_buffer_info)
4608 return;
4609
4610 /* Free all the Rx ring sk_buffs */
4611 for (i = 0; i < rx_ring->count; i++) {
4612 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
4613
4614 if (rx_buffer->skb) {
4615 struct sk_buff *skb = rx_buffer->skb;
4616 if (IXGBE_CB(skb)->page_released)
4617 dma_unmap_page(dev,
4618 IXGBE_CB(skb)->dma,
4619 ixgbe_rx_bufsz(rx_ring),
4620 DMA_FROM_DEVICE);
4621 dev_kfree_skb(skb);
4622 rx_buffer->skb = NULL;
4623 }
4624
4625 if (!rx_buffer->page)
4626 continue;
4627
4628 dma_unmap_page(dev, rx_buffer->dma,
4629 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4630 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4631
4632 rx_buffer->page = NULL;
4633 }
4634
4635 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4636 memset(rx_ring->rx_buffer_info, 0, size);
4637
4638 /* Zero out the descriptor ring */
4639 memset(rx_ring->desc, 0, rx_ring->size);
4640
4641 rx_ring->next_to_alloc = 0;
4642 rx_ring->next_to_clean = 0;
4643 rx_ring->next_to_use = 0;
4644 }
4645
4646 static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4647 struct ixgbe_ring *rx_ring)
4648 {
4649 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4650 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4651
4652 /* shutdown specific queue receive and wait for dma to settle */
4653 ixgbe_disable_rx_queue(adapter, rx_ring);
4654 usleep_range(10000, 20000);
4655 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4656 ixgbe_clean_rx_ring(rx_ring);
4657 rx_ring->l2_accel_priv = NULL;
4658 }
4659
4660 static int ixgbe_fwd_ring_down(struct net_device *vdev,
4661 struct ixgbe_fwd_adapter *accel)
4662 {
4663 struct ixgbe_adapter *adapter = accel->real_adapter;
4664 unsigned int rxbase = accel->rx_base_queue;
4665 unsigned int txbase = accel->tx_base_queue;
4666 int i;
4667
4668 netif_tx_stop_all_queues(vdev);
4669
4670 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4671 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4672 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4673 }
4674
4675 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4676 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4677 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4678 }
4679
4680
4681 return 0;
4682 }
4683
4684 static int ixgbe_fwd_ring_up(struct net_device *vdev,
4685 struct ixgbe_fwd_adapter *accel)
4686 {
4687 struct ixgbe_adapter *adapter = accel->real_adapter;
4688 unsigned int rxbase, txbase, queues;
4689 int i, baseq, err = 0;
4690
4691 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4692 return 0;
4693
4694 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4695 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4696 accel->pool, adapter->num_rx_pools,
4697 baseq, baseq + adapter->num_rx_queues_per_pool,
4698 adapter->fwd_bitmask);
4699
4700 accel->netdev = vdev;
4701 accel->rx_base_queue = rxbase = baseq;
4702 accel->tx_base_queue = txbase = baseq;
4703
4704 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4705 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4706
4707 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4708 adapter->rx_ring[rxbase + i]->netdev = vdev;
4709 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4710 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4711 }
4712
4713 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4714 adapter->tx_ring[txbase + i]->netdev = vdev;
4715 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4716 }
4717
4718 queues = min_t(unsigned int,
4719 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4720 err = netif_set_real_num_tx_queues(vdev, queues);
4721 if (err)
4722 goto fwd_queue_err;
4723
4724 err = netif_set_real_num_rx_queues(vdev, queues);
4725 if (err)
4726 goto fwd_queue_err;
4727
4728 if (is_valid_ether_addr(vdev->dev_addr))
4729 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4730
4731 ixgbe_fwd_psrtype(accel);
4732 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4733 return err;
4734 fwd_queue_err:
4735 ixgbe_fwd_ring_down(vdev, accel);
4736 return err;
4737 }
4738
4739 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4740 {
4741 struct net_device *upper;
4742 struct list_head *iter;
4743 int err;
4744
4745 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4746 if (netif_is_macvlan(upper)) {
4747 struct macvlan_dev *dfwd = netdev_priv(upper);
4748 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4749
4750 if (dfwd->fwd_priv) {
4751 err = ixgbe_fwd_ring_up(upper, vadapter);
4752 if (err)
4753 continue;
4754 }
4755 }
4756 }
4757 }
4758
4759 static void ixgbe_configure(struct ixgbe_adapter *adapter)
4760 {
4761 struct ixgbe_hw *hw = &adapter->hw;
4762
4763 ixgbe_configure_pb(adapter);
4764 #ifdef CONFIG_IXGBE_DCB
4765 ixgbe_configure_dcb(adapter);
4766 #endif
4767 /*
4768 * We must restore virtualization before VLANs or else
4769 * the VLVF registers will not be populated
4770 */
4771 ixgbe_configure_virtualization(adapter);
4772
4773 ixgbe_set_rx_mode(adapter->netdev);
4774 ixgbe_restore_vlan(adapter);
4775
4776 switch (hw->mac.type) {
4777 case ixgbe_mac_82599EB:
4778 case ixgbe_mac_X540:
4779 hw->mac.ops.disable_rx_buff(hw);
4780 break;
4781 default:
4782 break;
4783 }
4784
4785 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4786 ixgbe_init_fdir_signature_82599(&adapter->hw,
4787 adapter->fdir_pballoc);
4788 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4789 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4790 adapter->fdir_pballoc);
4791 ixgbe_fdir_filter_restore(adapter);
4792 }
4793
4794 switch (hw->mac.type) {
4795 case ixgbe_mac_82599EB:
4796 case ixgbe_mac_X540:
4797 hw->mac.ops.enable_rx_buff(hw);
4798 break;
4799 default:
4800 break;
4801 }
4802
4803 #ifdef CONFIG_IXGBE_DCA
4804 /* configure DCA */
4805 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
4806 ixgbe_setup_dca(adapter);
4807 #endif /* CONFIG_IXGBE_DCA */
4808
4809 #ifdef IXGBE_FCOE
4810 /* configure FCoE L2 filters, redirection table, and Rx control */
4811 ixgbe_configure_fcoe(adapter);
4812
4813 #endif /* IXGBE_FCOE */
4814 ixgbe_configure_tx(adapter);
4815 ixgbe_configure_rx(adapter);
4816 ixgbe_configure_dfwd(adapter);
4817 }
4818
4819 /**
4820 * ixgbe_sfp_link_config - set up SFP+ link
4821 * @adapter: pointer to private adapter struct
4822 **/
4823 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4824 {
4825 /*
4826 * We are assuming the worst case scenario here, and that
4827 * is that an SFP was inserted/removed after the reset
4828 * but before SFP detection was enabled. As such the best
4829 * solution is to just start searching as soon as we start
4830 */
4831 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4832 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
4833
4834 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
4835 adapter->sfp_poll_time = 0;
4836 }
4837
4838 /**
4839 * ixgbe_non_sfp_link_config - set up non-SFP+ link
4840 * @hw: pointer to private hardware struct
4841 *
4842 * Returns 0 on success, negative on failure
4843 **/
4844 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
4845 {
4846 u32 speed;
4847 bool autoneg, link_up = false;
4848 int ret = IXGBE_ERR_LINK_SETUP;
4849
4850 if (hw->mac.ops.check_link)
4851 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
4852
4853 if (ret)
4854 return ret;
4855
4856 speed = hw->phy.autoneg_advertised;
4857 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4858 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4859 &autoneg);
4860 if (ret)
4861 return ret;
4862
4863 if (hw->mac.ops.setup_link)
4864 ret = hw->mac.ops.setup_link(hw, speed, link_up);
4865
4866 return ret;
4867 }
4868
4869 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
4870 {
4871 struct ixgbe_hw *hw = &adapter->hw;
4872 u32 gpie = 0;
4873
4874 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4875 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4876 IXGBE_GPIE_OCD;
4877 gpie |= IXGBE_GPIE_EIAME;
4878 /*
4879 * use EIAM to auto-mask when MSI-X interrupt is asserted
4880 * this saves a register write for every interrupt
4881 */
4882 switch (hw->mac.type) {
4883 case ixgbe_mac_82598EB:
4884 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4885 break;
4886 case ixgbe_mac_82599EB:
4887 case ixgbe_mac_X540:
4888 case ixgbe_mac_X550:
4889 case ixgbe_mac_X550EM_x:
4890 default:
4891 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4892 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4893 break;
4894 }
4895 } else {
4896 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4897 * specifically only auto mask tx and rx interrupts */
4898 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4899 }
4900
4901 /* XXX: to interrupt immediately for EICS writes, enable this */
4902 /* gpie |= IXGBE_GPIE_EIMEN; */
4903
4904 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4905 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
4906
4907 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4908 case IXGBE_82599_VMDQ_8Q_MASK:
4909 gpie |= IXGBE_GPIE_VTMODE_16;
4910 break;
4911 case IXGBE_82599_VMDQ_4Q_MASK:
4912 gpie |= IXGBE_GPIE_VTMODE_32;
4913 break;
4914 default:
4915 gpie |= IXGBE_GPIE_VTMODE_64;
4916 break;
4917 }
4918 }
4919
4920 /* Enable Thermal over heat sensor interrupt */
4921 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4922 switch (adapter->hw.mac.type) {
4923 case ixgbe_mac_82599EB:
4924 gpie |= IXGBE_SDP0_GPIEN_8259X;
4925 break;
4926 default:
4927 break;
4928 }
4929 }
4930
4931 /* Enable fan failure interrupt */
4932 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
4933 gpie |= IXGBE_SDP1_GPIEN(hw);
4934
4935 switch (hw->mac.type) {
4936 case ixgbe_mac_82599EB:
4937 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
4938 break;
4939 case ixgbe_mac_X550EM_x:
4940 gpie |= IXGBE_SDP0_GPIEN_X540;
4941 break;
4942 default:
4943 break;
4944 }
4945
4946 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4947 }
4948
4949 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
4950 {
4951 struct ixgbe_hw *hw = &adapter->hw;
4952 int err;
4953 u32 ctrl_ext;
4954
4955 ixgbe_get_hw_control(adapter);
4956 ixgbe_setup_gpie(adapter);
4957
4958 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4959 ixgbe_configure_msix(adapter);
4960 else
4961 ixgbe_configure_msi_and_legacy(adapter);
4962
4963 /* enable the optics for 82599 SFP+ fiber */
4964 if (hw->mac.ops.enable_tx_laser)
4965 hw->mac.ops.enable_tx_laser(hw);
4966
4967 if (hw->phy.ops.set_phy_power)
4968 hw->phy.ops.set_phy_power(hw, true);
4969
4970 smp_mb__before_atomic();
4971 clear_bit(__IXGBE_DOWN, &adapter->state);
4972 ixgbe_napi_enable_all(adapter);
4973
4974 if (ixgbe_is_sfp(hw)) {
4975 ixgbe_sfp_link_config(adapter);
4976 } else {
4977 err = ixgbe_non_sfp_link_config(hw);
4978 if (err)
4979 e_err(probe, "link_config FAILED %d\n", err);
4980 }
4981
4982 /* clear any pending interrupts, may auto mask */
4983 IXGBE_READ_REG(hw, IXGBE_EICR);
4984 ixgbe_irq_enable(adapter, true, true);
4985
4986 /*
4987 * If this adapter has a fan, check to see if we had a failure
4988 * before we enabled the interrupt.
4989 */
4990 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4991 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4992 if (esdp & IXGBE_ESDP_SDP1)
4993 e_crit(drv, "Fan has stopped, replace the adapter\n");
4994 }
4995
4996 /* bring the link up in the watchdog, this could race with our first
4997 * link up interrupt but shouldn't be a problem */
4998 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4999 adapter->link_check_timeout = jiffies;
5000 mod_timer(&adapter->service_timer, jiffies);
5001
5002 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5003 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5004 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5005 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5006 }
5007
5008 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5009 {
5010 WARN_ON(in_interrupt());
5011 /* put off any impending NetWatchDogTimeout */
5012 adapter->netdev->trans_start = jiffies;
5013
5014 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5015 usleep_range(1000, 2000);
5016 ixgbe_down(adapter);
5017 /*
5018 * If SR-IOV enabled then wait a bit before bringing the adapter
5019 * back up to give the VFs time to respond to the reset. The
5020 * two second wait is based upon the watchdog timer cycle in
5021 * the VF driver.
5022 */
5023 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5024 msleep(2000);
5025 ixgbe_up(adapter);
5026 clear_bit(__IXGBE_RESETTING, &adapter->state);
5027 }
5028
5029 void ixgbe_up(struct ixgbe_adapter *adapter)
5030 {
5031 /* hardware has been reset, we need to reload some things */
5032 ixgbe_configure(adapter);
5033
5034 ixgbe_up_complete(adapter);
5035 }
5036
5037 void ixgbe_reset(struct ixgbe_adapter *adapter)
5038 {
5039 struct ixgbe_hw *hw = &adapter->hw;
5040 struct net_device *netdev = adapter->netdev;
5041 int err;
5042 u8 old_addr[ETH_ALEN];
5043
5044 if (ixgbe_removed(hw->hw_addr))
5045 return;
5046 /* lock SFP init bit to prevent race conditions with the watchdog */
5047 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5048 usleep_range(1000, 2000);
5049
5050 /* clear all SFP and link config related flags while holding SFP_INIT */
5051 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5052 IXGBE_FLAG2_SFP_NEEDS_RESET);
5053 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5054
5055 err = hw->mac.ops.init_hw(hw);
5056 switch (err) {
5057 case 0:
5058 case IXGBE_ERR_SFP_NOT_PRESENT:
5059 case IXGBE_ERR_SFP_NOT_SUPPORTED:
5060 break;
5061 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
5062 e_dev_err("master disable timed out\n");
5063 break;
5064 case IXGBE_ERR_EEPROM_VERSION:
5065 /* We are running on a pre-production device, log a warning */
5066 e_dev_warn("This device is a pre-production adapter/LOM. "
5067 "Please be aware there may be issues associated with "
5068 "your hardware. If you are experiencing problems "
5069 "please contact your Intel or hardware "
5070 "representative who provided you with this "
5071 "hardware.\n");
5072 break;
5073 default:
5074 e_dev_err("Hardware Error: %d\n", err);
5075 }
5076
5077 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5078 /* do not flush user set addresses */
5079 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
5080 ixgbe_flush_sw_mac_table(adapter);
5081 ixgbe_mac_set_default_filter(adapter, old_addr);
5082
5083 /* update SAN MAC vmdq pool selection */
5084 if (hw->mac.san_mac_rar_index)
5085 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
5086
5087 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
5088 ixgbe_ptp_reset(adapter);
5089
5090 if (hw->phy.ops.set_phy_power) {
5091 if (!netif_running(adapter->netdev) && !adapter->wol)
5092 hw->phy.ops.set_phy_power(hw, false);
5093 else
5094 hw->phy.ops.set_phy_power(hw, true);
5095 }
5096 }
5097
5098 /**
5099 * ixgbe_clean_tx_ring - Free Tx Buffers
5100 * @tx_ring: ring to be cleaned
5101 **/
5102 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
5103 {
5104 struct ixgbe_tx_buffer *tx_buffer_info;
5105 unsigned long size;
5106 u16 i;
5107
5108 /* ring already cleared, nothing to do */
5109 if (!tx_ring->tx_buffer_info)
5110 return;
5111
5112 /* Free all the Tx ring sk_buffs */
5113 for (i = 0; i < tx_ring->count; i++) {
5114 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5115 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
5116 }
5117
5118 netdev_tx_reset_queue(txring_txq(tx_ring));
5119
5120 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5121 memset(tx_ring->tx_buffer_info, 0, size);
5122
5123 /* Zero out the descriptor ring */
5124 memset(tx_ring->desc, 0, tx_ring->size);
5125
5126 tx_ring->next_to_use = 0;
5127 tx_ring->next_to_clean = 0;
5128 }
5129
5130 /**
5131 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
5132 * @adapter: board private structure
5133 **/
5134 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
5135 {
5136 int i;
5137
5138 for (i = 0; i < adapter->num_rx_queues; i++)
5139 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
5140 }
5141
5142 /**
5143 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
5144 * @adapter: board private structure
5145 **/
5146 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
5147 {
5148 int i;
5149
5150 for (i = 0; i < adapter->num_tx_queues; i++)
5151 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
5152 }
5153
5154 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5155 {
5156 struct hlist_node *node2;
5157 struct ixgbe_fdir_filter *filter;
5158
5159 spin_lock(&adapter->fdir_perfect_lock);
5160
5161 hlist_for_each_entry_safe(filter, node2,
5162 &adapter->fdir_filter_list, fdir_node) {
5163 hlist_del(&filter->fdir_node);
5164 kfree(filter);
5165 }
5166 adapter->fdir_filter_count = 0;
5167
5168 spin_unlock(&adapter->fdir_perfect_lock);
5169 }
5170
5171 void ixgbe_down(struct ixgbe_adapter *adapter)
5172 {
5173 struct net_device *netdev = adapter->netdev;
5174 struct ixgbe_hw *hw = &adapter->hw;
5175 struct net_device *upper;
5176 struct list_head *iter;
5177 int i;
5178
5179 /* signal that we are down to the interrupt handler */
5180 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5181 return; /* do nothing if already down */
5182
5183 /* disable receives */
5184 hw->mac.ops.disable_rx(hw);
5185
5186 /* disable all enabled rx queues */
5187 for (i = 0; i < adapter->num_rx_queues; i++)
5188 /* this call also flushes the previous write */
5189 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5190
5191 usleep_range(10000, 20000);
5192
5193 netif_tx_stop_all_queues(netdev);
5194
5195 /* call carrier off first to avoid false dev_watchdog timeouts */
5196 netif_carrier_off(netdev);
5197 netif_tx_disable(netdev);
5198
5199 /* disable any upper devices */
5200 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5201 if (netif_is_macvlan(upper)) {
5202 struct macvlan_dev *vlan = netdev_priv(upper);
5203
5204 if (vlan->fwd_priv) {
5205 netif_tx_stop_all_queues(upper);
5206 netif_carrier_off(upper);
5207 netif_tx_disable(upper);
5208 }
5209 }
5210 }
5211
5212 ixgbe_irq_disable(adapter);
5213
5214 ixgbe_napi_disable_all(adapter);
5215
5216 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5217 IXGBE_FLAG2_RESET_REQUESTED);
5218 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5219
5220 del_timer_sync(&adapter->service_timer);
5221
5222 if (adapter->num_vfs) {
5223 /* Clear EITR Select mapping */
5224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
5225
5226 /* Mark all the VFs as inactive */
5227 for (i = 0 ; i < adapter->num_vfs; i++)
5228 adapter->vfinfo[i].clear_to_send = false;
5229
5230 /* ping all the active vfs to let them know we are going down */
5231 ixgbe_ping_all_vfs(adapter);
5232
5233 /* Disable all VFTE/VFRE TX/RX */
5234 ixgbe_disable_tx_rx(adapter);
5235 }
5236
5237 /* disable transmits in the hardware now that interrupts are off */
5238 for (i = 0; i < adapter->num_tx_queues; i++) {
5239 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
5240 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5241 }
5242
5243 /* Disable the Tx DMA engine on 82599 and later MAC */
5244 switch (hw->mac.type) {
5245 case ixgbe_mac_82599EB:
5246 case ixgbe_mac_X540:
5247 case ixgbe_mac_X550:
5248 case ixgbe_mac_X550EM_x:
5249 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5250 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5251 ~IXGBE_DMATXCTL_TE));
5252 break;
5253 default:
5254 break;
5255 }
5256
5257 if (!pci_channel_offline(adapter->pdev))
5258 ixgbe_reset(adapter);
5259
5260 /* power down the optics for 82599 SFP+ fiber */
5261 if (hw->mac.ops.disable_tx_laser)
5262 hw->mac.ops.disable_tx_laser(hw);
5263
5264 ixgbe_clean_all_tx_rings(adapter);
5265 ixgbe_clean_all_rx_rings(adapter);
5266 }
5267
5268 /**
5269 * ixgbe_tx_timeout - Respond to a Tx Hang
5270 * @netdev: network interface device structure
5271 **/
5272 static void ixgbe_tx_timeout(struct net_device *netdev)
5273 {
5274 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5275
5276 /* Do the reset outside of interrupt context */
5277 ixgbe_tx_timeout_reset(adapter);
5278 }
5279
5280 /**
5281 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5282 * @adapter: board private structure to initialize
5283 *
5284 * ixgbe_sw_init initializes the Adapter private data structure.
5285 * Fields are initialized based on PCI device information and
5286 * OS network device settings (MTU size).
5287 **/
5288 static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
5289 {
5290 struct ixgbe_hw *hw = &adapter->hw;
5291 struct pci_dev *pdev = adapter->pdev;
5292 unsigned int rss, fdir;
5293 u32 fwsm;
5294 #ifdef CONFIG_IXGBE_DCB
5295 int j;
5296 struct tc_configuration *tc;
5297 #endif
5298
5299 /* PCI config space info */
5300
5301 hw->vendor_id = pdev->vendor;
5302 hw->device_id = pdev->device;
5303 hw->revision_id = pdev->revision;
5304 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5305 hw->subsystem_device_id = pdev->subsystem_device;
5306
5307 /* Set common capability flags and settings */
5308 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
5309 adapter->ring_feature[RING_F_RSS].limit = rss;
5310 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5311 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5312 adapter->atr_sample_rate = 20;
5313 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5314 adapter->ring_feature[RING_F_FDIR].limit = fdir;
5315 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5316 #ifdef CONFIG_IXGBE_DCA
5317 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5318 #endif
5319 #ifdef IXGBE_FCOE
5320 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5321 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5322 #ifdef CONFIG_IXGBE_DCB
5323 /* Default traffic class to use for FCoE */
5324 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5325 #endif /* CONFIG_IXGBE_DCB */
5326 #endif /* IXGBE_FCOE */
5327
5328 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5329 hw->mac.num_rar_entries,
5330 GFP_ATOMIC);
5331
5332 /* Set MAC specific capability flags and exceptions */
5333 switch (hw->mac.type) {
5334 case ixgbe_mac_82598EB:
5335 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5336
5337 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5338 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5339
5340 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
5341 adapter->ring_feature[RING_F_FDIR].limit = 0;
5342 adapter->atr_sample_rate = 0;
5343 adapter->fdir_pballoc = 0;
5344 #ifdef IXGBE_FCOE
5345 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5346 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5347 #ifdef CONFIG_IXGBE_DCB
5348 adapter->fcoe.up = 0;
5349 #endif /* IXGBE_DCB */
5350 #endif /* IXGBE_FCOE */
5351 break;
5352 case ixgbe_mac_82599EB:
5353 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5354 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5355 break;
5356 case ixgbe_mac_X540:
5357 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
5358 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5359 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5360 break;
5361 case ixgbe_mac_X550EM_x:
5362 case ixgbe_mac_X550:
5363 #ifdef CONFIG_IXGBE_DCA
5364 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
5365 #endif
5366 #ifdef CONFIG_IXGBE_VXLAN
5367 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
5368 #endif
5369 break;
5370 default:
5371 break;
5372 }
5373
5374 #ifdef IXGBE_FCOE
5375 /* FCoE support exists, always init the FCoE lock */
5376 spin_lock_init(&adapter->fcoe.lock);
5377
5378 #endif
5379 /* n-tuple support exists, always init our spinlock */
5380 spin_lock_init(&adapter->fdir_perfect_lock);
5381
5382 #ifdef CONFIG_IXGBE_DCB
5383 switch (hw->mac.type) {
5384 case ixgbe_mac_X540:
5385 case ixgbe_mac_X550:
5386 case ixgbe_mac_X550EM_x:
5387 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5388 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5389 break;
5390 default:
5391 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5392 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5393 break;
5394 }
5395
5396 /* Configure DCB traffic classes */
5397 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5398 tc = &adapter->dcb_cfg.tc_config[j];
5399 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5400 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5401 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5402 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5403 tc->dcb_pfc = pfc_disabled;
5404 }
5405
5406 /* Initialize default user to priority mapping, UPx->TC0 */
5407 tc = &adapter->dcb_cfg.tc_config[0];
5408 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5409 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5410
5411 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5412 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5413 adapter->dcb_cfg.pfc_mode_enable = false;
5414 adapter->dcb_set_bitmap = 0x00;
5415 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5416 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5417 sizeof(adapter->temp_dcb_cfg));
5418
5419 #endif
5420
5421 /* default flow control settings */
5422 hw->fc.requested_mode = ixgbe_fc_full;
5423 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5424 ixgbe_pbthresh_setup(adapter);
5425 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5426 hw->fc.send_xon = true;
5427 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
5428
5429 #ifdef CONFIG_PCI_IOV
5430 if (max_vfs > 0)
5431 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5432
5433 /* assign number of SR-IOV VFs */
5434 if (hw->mac.type != ixgbe_mac_82598EB) {
5435 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
5436 adapter->num_vfs = 0;
5437 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5438 } else {
5439 adapter->num_vfs = max_vfs;
5440 }
5441 }
5442 #endif /* CONFIG_PCI_IOV */
5443
5444 /* enable itr by default in dynamic mode */
5445 adapter->rx_itr_setting = 1;
5446 adapter->tx_itr_setting = 1;
5447
5448 /* set default ring sizes */
5449 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5450 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5451
5452 /* set default work limits */
5453 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
5454
5455 /* initialize eeprom parameters */
5456 if (ixgbe_init_eeprom_params_generic(hw)) {
5457 e_dev_err("EEPROM initialization failed\n");
5458 return -EIO;
5459 }
5460
5461 /* PF holds first pool slot */
5462 set_bit(0, &adapter->fwd_bitmask);
5463 set_bit(__IXGBE_DOWN, &adapter->state);
5464
5465 return 0;
5466 }
5467
5468 /**
5469 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5470 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5471 *
5472 * Return 0 on success, negative on failure
5473 **/
5474 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5475 {
5476 struct device *dev = tx_ring->dev;
5477 int orig_node = dev_to_node(dev);
5478 int ring_node = -1;
5479 int size;
5480
5481 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5482
5483 if (tx_ring->q_vector)
5484 ring_node = tx_ring->q_vector->numa_node;
5485
5486 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
5487 if (!tx_ring->tx_buffer_info)
5488 tx_ring->tx_buffer_info = vzalloc(size);
5489 if (!tx_ring->tx_buffer_info)
5490 goto err;
5491
5492 u64_stats_init(&tx_ring->syncp);
5493
5494 /* round up to nearest 4K */
5495 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5496 tx_ring->size = ALIGN(tx_ring->size, 4096);
5497
5498 set_dev_node(dev, ring_node);
5499 tx_ring->desc = dma_alloc_coherent(dev,
5500 tx_ring->size,
5501 &tx_ring->dma,
5502 GFP_KERNEL);
5503 set_dev_node(dev, orig_node);
5504 if (!tx_ring->desc)
5505 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5506 &tx_ring->dma, GFP_KERNEL);
5507 if (!tx_ring->desc)
5508 goto err;
5509
5510 tx_ring->next_to_use = 0;
5511 tx_ring->next_to_clean = 0;
5512 return 0;
5513
5514 err:
5515 vfree(tx_ring->tx_buffer_info);
5516 tx_ring->tx_buffer_info = NULL;
5517 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5518 return -ENOMEM;
5519 }
5520
5521 /**
5522 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5523 * @adapter: board private structure
5524 *
5525 * If this function returns with an error, then it's possible one or
5526 * more of the rings is populated (while the rest are not). It is the
5527 * callers duty to clean those orphaned rings.
5528 *
5529 * Return 0 on success, negative on failure
5530 **/
5531 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5532 {
5533 int i, err = 0;
5534
5535 for (i = 0; i < adapter->num_tx_queues; i++) {
5536 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5537 if (!err)
5538 continue;
5539
5540 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5541 goto err_setup_tx;
5542 }
5543
5544 return 0;
5545 err_setup_tx:
5546 /* rewind the index freeing the rings as we go */
5547 while (i--)
5548 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5549 return err;
5550 }
5551
5552 /**
5553 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5554 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5555 *
5556 * Returns 0 on success, negative on failure
5557 **/
5558 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5559 {
5560 struct device *dev = rx_ring->dev;
5561 int orig_node = dev_to_node(dev);
5562 int ring_node = -1;
5563 int size;
5564
5565 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5566
5567 if (rx_ring->q_vector)
5568 ring_node = rx_ring->q_vector->numa_node;
5569
5570 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
5571 if (!rx_ring->rx_buffer_info)
5572 rx_ring->rx_buffer_info = vzalloc(size);
5573 if (!rx_ring->rx_buffer_info)
5574 goto err;
5575
5576 u64_stats_init(&rx_ring->syncp);
5577
5578 /* Round up to nearest 4K */
5579 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5580 rx_ring->size = ALIGN(rx_ring->size, 4096);
5581
5582 set_dev_node(dev, ring_node);
5583 rx_ring->desc = dma_alloc_coherent(dev,
5584 rx_ring->size,
5585 &rx_ring->dma,
5586 GFP_KERNEL);
5587 set_dev_node(dev, orig_node);
5588 if (!rx_ring->desc)
5589 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5590 &rx_ring->dma, GFP_KERNEL);
5591 if (!rx_ring->desc)
5592 goto err;
5593
5594 rx_ring->next_to_clean = 0;
5595 rx_ring->next_to_use = 0;
5596
5597 return 0;
5598 err:
5599 vfree(rx_ring->rx_buffer_info);
5600 rx_ring->rx_buffer_info = NULL;
5601 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5602 return -ENOMEM;
5603 }
5604
5605 /**
5606 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5607 * @adapter: board private structure
5608 *
5609 * If this function returns with an error, then it's possible one or
5610 * more of the rings is populated (while the rest are not). It is the
5611 * callers duty to clean those orphaned rings.
5612 *
5613 * Return 0 on success, negative on failure
5614 **/
5615 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5616 {
5617 int i, err = 0;
5618
5619 for (i = 0; i < adapter->num_rx_queues; i++) {
5620 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5621 if (!err)
5622 continue;
5623
5624 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5625 goto err_setup_rx;
5626 }
5627
5628 #ifdef IXGBE_FCOE
5629 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5630 if (!err)
5631 #endif
5632 return 0;
5633 err_setup_rx:
5634 /* rewind the index freeing the rings as we go */
5635 while (i--)
5636 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5637 return err;
5638 }
5639
5640 /**
5641 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5642 * @tx_ring: Tx descriptor ring for a specific queue
5643 *
5644 * Free all transmit software resources
5645 **/
5646 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5647 {
5648 ixgbe_clean_tx_ring(tx_ring);
5649
5650 vfree(tx_ring->tx_buffer_info);
5651 tx_ring->tx_buffer_info = NULL;
5652
5653 /* if not set, then don't free */
5654 if (!tx_ring->desc)
5655 return;
5656
5657 dma_free_coherent(tx_ring->dev, tx_ring->size,
5658 tx_ring->desc, tx_ring->dma);
5659
5660 tx_ring->desc = NULL;
5661 }
5662
5663 /**
5664 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5665 * @adapter: board private structure
5666 *
5667 * Free all transmit software resources
5668 **/
5669 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5670 {
5671 int i;
5672
5673 for (i = 0; i < adapter->num_tx_queues; i++)
5674 if (adapter->tx_ring[i]->desc)
5675 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5676 }
5677
5678 /**
5679 * ixgbe_free_rx_resources - Free Rx Resources
5680 * @rx_ring: ring to clean the resources from
5681 *
5682 * Free all receive software resources
5683 **/
5684 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5685 {
5686 ixgbe_clean_rx_ring(rx_ring);
5687
5688 vfree(rx_ring->rx_buffer_info);
5689 rx_ring->rx_buffer_info = NULL;
5690
5691 /* if not set, then don't free */
5692 if (!rx_ring->desc)
5693 return;
5694
5695 dma_free_coherent(rx_ring->dev, rx_ring->size,
5696 rx_ring->desc, rx_ring->dma);
5697
5698 rx_ring->desc = NULL;
5699 }
5700
5701 /**
5702 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5703 * @adapter: board private structure
5704 *
5705 * Free all receive software resources
5706 **/
5707 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5708 {
5709 int i;
5710
5711 #ifdef IXGBE_FCOE
5712 ixgbe_free_fcoe_ddp_resources(adapter);
5713
5714 #endif
5715 for (i = 0; i < adapter->num_rx_queues; i++)
5716 if (adapter->rx_ring[i]->desc)
5717 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5718 }
5719
5720 /**
5721 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5722 * @netdev: network interface device structure
5723 * @new_mtu: new value for maximum frame size
5724 *
5725 * Returns 0 on success, negative on failure
5726 **/
5727 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5728 {
5729 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5730 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5731
5732 /* MTU < 68 is an error and causes problems on some kernels */
5733 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5734 return -EINVAL;
5735
5736 /*
5737 * For 82599EB we cannot allow legacy VFs to enable their receive
5738 * paths when MTU greater than 1500 is configured. So display a
5739 * warning that legacy VFs will be disabled.
5740 */
5741 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5742 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
5743 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
5744 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
5745
5746 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5747
5748 /* must set new MTU before calling down or up */
5749 netdev->mtu = new_mtu;
5750
5751 if (netif_running(netdev))
5752 ixgbe_reinit_locked(adapter);
5753
5754 return 0;
5755 }
5756
5757 /**
5758 * ixgbe_open - Called when a network interface is made active
5759 * @netdev: network interface device structure
5760 *
5761 * Returns 0 on success, negative value on failure
5762 *
5763 * The open entry point is called when a network interface is made
5764 * active by the system (IFF_UP). At this point all resources needed
5765 * for transmit and receive operations are allocated, the interrupt
5766 * handler is registered with the OS, the watchdog timer is started,
5767 * and the stack is notified that the interface is ready.
5768 **/
5769 static int ixgbe_open(struct net_device *netdev)
5770 {
5771 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5772 struct ixgbe_hw *hw = &adapter->hw;
5773 int err, queues;
5774
5775 /* disallow open during test */
5776 if (test_bit(__IXGBE_TESTING, &adapter->state))
5777 return -EBUSY;
5778
5779 netif_carrier_off(netdev);
5780
5781 /* allocate transmit descriptors */
5782 err = ixgbe_setup_all_tx_resources(adapter);
5783 if (err)
5784 goto err_setup_tx;
5785
5786 /* allocate receive descriptors */
5787 err = ixgbe_setup_all_rx_resources(adapter);
5788 if (err)
5789 goto err_setup_rx;
5790
5791 ixgbe_configure(adapter);
5792
5793 err = ixgbe_request_irq(adapter);
5794 if (err)
5795 goto err_req_irq;
5796
5797 /* Notify the stack of the actual queue counts. */
5798 if (adapter->num_rx_pools > 1)
5799 queues = adapter->num_rx_queues_per_pool;
5800 else
5801 queues = adapter->num_tx_queues;
5802
5803 err = netif_set_real_num_tx_queues(netdev, queues);
5804 if (err)
5805 goto err_set_queues;
5806
5807 if (adapter->num_rx_pools > 1 &&
5808 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5809 queues = IXGBE_MAX_L2A_QUEUES;
5810 else
5811 queues = adapter->num_rx_queues;
5812 err = netif_set_real_num_rx_queues(netdev, queues);
5813 if (err)
5814 goto err_set_queues;
5815
5816 ixgbe_ptp_init(adapter);
5817
5818 ixgbe_up_complete(adapter);
5819
5820 ixgbe_clear_vxlan_port(adapter);
5821 #ifdef CONFIG_IXGBE_VXLAN
5822 vxlan_get_rx_port(netdev);
5823 #endif
5824
5825 return 0;
5826
5827 err_set_queues:
5828 ixgbe_free_irq(adapter);
5829 err_req_irq:
5830 ixgbe_free_all_rx_resources(adapter);
5831 if (hw->phy.ops.set_phy_power && !adapter->wol)
5832 hw->phy.ops.set_phy_power(&adapter->hw, false);
5833 err_setup_rx:
5834 ixgbe_free_all_tx_resources(adapter);
5835 err_setup_tx:
5836 ixgbe_reset(adapter);
5837
5838 return err;
5839 }
5840
5841 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5842 {
5843 ixgbe_ptp_suspend(adapter);
5844
5845 if (adapter->hw.phy.ops.enter_lplu) {
5846 adapter->hw.phy.reset_disable = true;
5847 ixgbe_down(adapter);
5848 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5849 adapter->hw.phy.reset_disable = false;
5850 } else {
5851 ixgbe_down(adapter);
5852 }
5853
5854 ixgbe_free_irq(adapter);
5855
5856 ixgbe_free_all_tx_resources(adapter);
5857 ixgbe_free_all_rx_resources(adapter);
5858 }
5859
5860 /**
5861 * ixgbe_close - Disables a network interface
5862 * @netdev: network interface device structure
5863 *
5864 * Returns 0, this is not allowed to fail
5865 *
5866 * The close entry point is called when an interface is de-activated
5867 * by the OS. The hardware is still under the drivers control, but
5868 * needs to be disabled. A global MAC reset is issued to stop the
5869 * hardware, and all transmit and receive resources are freed.
5870 **/
5871 static int ixgbe_close(struct net_device *netdev)
5872 {
5873 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5874
5875 ixgbe_ptp_stop(adapter);
5876
5877 ixgbe_close_suspend(adapter);
5878
5879 ixgbe_fdir_filter_exit(adapter);
5880
5881 ixgbe_release_hw_control(adapter);
5882
5883 return 0;
5884 }
5885
5886 #ifdef CONFIG_PM
5887 static int ixgbe_resume(struct pci_dev *pdev)
5888 {
5889 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5890 struct net_device *netdev = adapter->netdev;
5891 u32 err;
5892
5893 adapter->hw.hw_addr = adapter->io_addr;
5894 pci_set_power_state(pdev, PCI_D0);
5895 pci_restore_state(pdev);
5896 /*
5897 * pci_restore_state clears dev->state_saved so call
5898 * pci_save_state to restore it.
5899 */
5900 pci_save_state(pdev);
5901
5902 err = pci_enable_device_mem(pdev);
5903 if (err) {
5904 e_dev_err("Cannot enable PCI device from suspend\n");
5905 return err;
5906 }
5907 smp_mb__before_atomic();
5908 clear_bit(__IXGBE_DISABLED, &adapter->state);
5909 pci_set_master(pdev);
5910
5911 pci_wake_from_d3(pdev, false);
5912
5913 ixgbe_reset(adapter);
5914
5915 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5916
5917 rtnl_lock();
5918 err = ixgbe_init_interrupt_scheme(adapter);
5919 if (!err && netif_running(netdev))
5920 err = ixgbe_open(netdev);
5921
5922 rtnl_unlock();
5923
5924 if (err)
5925 return err;
5926
5927 netif_device_attach(netdev);
5928
5929 return 0;
5930 }
5931 #endif /* CONFIG_PM */
5932
5933 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5934 {
5935 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5936 struct net_device *netdev = adapter->netdev;
5937 struct ixgbe_hw *hw = &adapter->hw;
5938 u32 ctrl, fctrl;
5939 u32 wufc = adapter->wol;
5940 #ifdef CONFIG_PM
5941 int retval = 0;
5942 #endif
5943
5944 netif_device_detach(netdev);
5945
5946 rtnl_lock();
5947 if (netif_running(netdev))
5948 ixgbe_close_suspend(adapter);
5949 rtnl_unlock();
5950
5951 ixgbe_clear_interrupt_scheme(adapter);
5952
5953 #ifdef CONFIG_PM
5954 retval = pci_save_state(pdev);
5955 if (retval)
5956 return retval;
5957
5958 #endif
5959 if (hw->mac.ops.stop_link_on_d3)
5960 hw->mac.ops.stop_link_on_d3(hw);
5961
5962 if (wufc) {
5963 ixgbe_set_rx_mode(netdev);
5964
5965 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5966 if (hw->mac.ops.enable_tx_laser)
5967 hw->mac.ops.enable_tx_laser(hw);
5968
5969 /* turn on all-multi mode if wake on multicast is enabled */
5970 if (wufc & IXGBE_WUFC_MC) {
5971 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5972 fctrl |= IXGBE_FCTRL_MPE;
5973 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5974 }
5975
5976 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5977 ctrl |= IXGBE_CTRL_GIO_DIS;
5978 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5979
5980 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5981 } else {
5982 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5983 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5984 }
5985
5986 switch (hw->mac.type) {
5987 case ixgbe_mac_82598EB:
5988 pci_wake_from_d3(pdev, false);
5989 break;
5990 case ixgbe_mac_82599EB:
5991 case ixgbe_mac_X540:
5992 case ixgbe_mac_X550:
5993 case ixgbe_mac_X550EM_x:
5994 pci_wake_from_d3(pdev, !!wufc);
5995 break;
5996 default:
5997 break;
5998 }
5999
6000 *enable_wake = !!wufc;
6001 if (hw->phy.ops.set_phy_power && !*enable_wake)
6002 hw->phy.ops.set_phy_power(hw, false);
6003
6004 ixgbe_release_hw_control(adapter);
6005
6006 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6007 pci_disable_device(pdev);
6008
6009 return 0;
6010 }
6011
6012 #ifdef CONFIG_PM
6013 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6014 {
6015 int retval;
6016 bool wake;
6017
6018 retval = __ixgbe_shutdown(pdev, &wake);
6019 if (retval)
6020 return retval;
6021
6022 if (wake) {
6023 pci_prepare_to_sleep(pdev);
6024 } else {
6025 pci_wake_from_d3(pdev, false);
6026 pci_set_power_state(pdev, PCI_D3hot);
6027 }
6028
6029 return 0;
6030 }
6031 #endif /* CONFIG_PM */
6032
6033 static void ixgbe_shutdown(struct pci_dev *pdev)
6034 {
6035 bool wake;
6036
6037 __ixgbe_shutdown(pdev, &wake);
6038
6039 if (system_state == SYSTEM_POWER_OFF) {
6040 pci_wake_from_d3(pdev, wake);
6041 pci_set_power_state(pdev, PCI_D3hot);
6042 }
6043 }
6044
6045 /**
6046 * ixgbe_update_stats - Update the board statistics counters.
6047 * @adapter: board private structure
6048 **/
6049 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6050 {
6051 struct net_device *netdev = adapter->netdev;
6052 struct ixgbe_hw *hw = &adapter->hw;
6053 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6054 u64 total_mpc = 0;
6055 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
6056 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6057 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
6058 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
6059
6060 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6061 test_bit(__IXGBE_RESETTING, &adapter->state))
6062 return;
6063
6064 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
6065 u64 rsc_count = 0;
6066 u64 rsc_flush = 0;
6067 for (i = 0; i < adapter->num_rx_queues; i++) {
6068 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6069 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
6070 }
6071 adapter->rsc_total_count = rsc_count;
6072 adapter->rsc_total_flush = rsc_flush;
6073 }
6074
6075 for (i = 0; i < adapter->num_rx_queues; i++) {
6076 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6077 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6078 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6079 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
6080 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
6081 bytes += rx_ring->stats.bytes;
6082 packets += rx_ring->stats.packets;
6083 }
6084 adapter->non_eop_descs = non_eop_descs;
6085 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6086 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
6087 adapter->hw_csum_rx_error = hw_csum_rx_error;
6088 netdev->stats.rx_bytes = bytes;
6089 netdev->stats.rx_packets = packets;
6090
6091 bytes = 0;
6092 packets = 0;
6093 /* gather some stats to the adapter struct that are per queue */
6094 for (i = 0; i < adapter->num_tx_queues; i++) {
6095 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6096 restart_queue += tx_ring->tx_stats.restart_queue;
6097 tx_busy += tx_ring->tx_stats.tx_busy;
6098 bytes += tx_ring->stats.bytes;
6099 packets += tx_ring->stats.packets;
6100 }
6101 adapter->restart_queue = restart_queue;
6102 adapter->tx_busy = tx_busy;
6103 netdev->stats.tx_bytes = bytes;
6104 netdev->stats.tx_packets = packets;
6105
6106 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
6107
6108 /* 8 register reads */
6109 for (i = 0; i < 8; i++) {
6110 /* for packet buffers not used, the register should read 0 */
6111 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6112 missed_rx += mpc;
6113 hwstats->mpc[i] += mpc;
6114 total_mpc += hwstats->mpc[i];
6115 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6116 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
6117 switch (hw->mac.type) {
6118 case ixgbe_mac_82598EB:
6119 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6120 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6121 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
6122 hwstats->pxonrxc[i] +=
6123 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
6124 break;
6125 case ixgbe_mac_82599EB:
6126 case ixgbe_mac_X540:
6127 case ixgbe_mac_X550:
6128 case ixgbe_mac_X550EM_x:
6129 hwstats->pxonrxc[i] +=
6130 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
6131 break;
6132 default:
6133 break;
6134 }
6135 }
6136
6137 /*16 register reads */
6138 for (i = 0; i < 16; i++) {
6139 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6140 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6141 if ((hw->mac.type == ixgbe_mac_82599EB) ||
6142 (hw->mac.type == ixgbe_mac_X540) ||
6143 (hw->mac.type == ixgbe_mac_X550) ||
6144 (hw->mac.type == ixgbe_mac_X550EM_x)) {
6145 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6146 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6147 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6148 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6149 }
6150 }
6151
6152 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6153 /* work around hardware counting issue */
6154 hwstats->gprc -= missed_rx;
6155
6156 ixgbe_update_xoff_received(adapter);
6157
6158 /* 82598 hardware only has a 32 bit counter in the high register */
6159 switch (hw->mac.type) {
6160 case ixgbe_mac_82598EB:
6161 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
6162 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6163 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6164 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6165 break;
6166 case ixgbe_mac_X540:
6167 case ixgbe_mac_X550:
6168 case ixgbe_mac_X550EM_x:
6169 /* OS2BMC stats are X540 and later */
6170 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6171 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6172 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6173 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6174 case ixgbe_mac_82599EB:
6175 for (i = 0; i < 16; i++)
6176 adapter->hw_rx_no_dma_resources +=
6177 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
6178 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
6179 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
6180 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
6181 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
6182 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
6183 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
6184 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
6185 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6186 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6187 #ifdef IXGBE_FCOE
6188 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6189 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6190 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6191 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6192 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6193 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
6194 /* Add up per cpu counters for total ddp aloc fail */
6195 if (adapter->fcoe.ddp_pool) {
6196 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6197 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6198 unsigned int cpu;
6199 u64 noddp = 0, noddp_ext_buff = 0;
6200 for_each_possible_cpu(cpu) {
6201 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6202 noddp += ddp_pool->noddp;
6203 noddp_ext_buff += ddp_pool->noddp_ext_buff;
6204 }
6205 hwstats->fcoe_noddp = noddp;
6206 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
6207 }
6208 #endif /* IXGBE_FCOE */
6209 break;
6210 default:
6211 break;
6212 }
6213 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
6214 hwstats->bprc += bprc;
6215 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
6216 if (hw->mac.type == ixgbe_mac_82598EB)
6217 hwstats->mprc -= bprc;
6218 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6219 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6220 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6221 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6222 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6223 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6224 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6225 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6226 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
6227 hwstats->lxontxc += lxon;
6228 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
6229 hwstats->lxofftxc += lxoff;
6230 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6231 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6232 /*
6233 * 82598 errata - tx of flow control packets is included in tx counters
6234 */
6235 xon_off_tot = lxon + lxoff;
6236 hwstats->gptc -= xon_off_tot;
6237 hwstats->mptc -= xon_off_tot;
6238 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6239 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6240 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6241 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6242 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6243 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6244 hwstats->ptc64 -= xon_off_tot;
6245 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6246 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6247 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6248 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6249 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6250 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
6251
6252 /* Fill out the OS statistics structure */
6253 netdev->stats.multicast = hwstats->mprc;
6254
6255 /* Rx Errors */
6256 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
6257 netdev->stats.rx_dropped = 0;
6258 netdev->stats.rx_length_errors = hwstats->rlec;
6259 netdev->stats.rx_crc_errors = hwstats->crcerrs;
6260 netdev->stats.rx_missed_errors = total_mpc;
6261 }
6262
6263 /**
6264 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
6265 * @adapter: pointer to the device adapter structure
6266 **/
6267 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
6268 {
6269 struct ixgbe_hw *hw = &adapter->hw;
6270 int i;
6271
6272 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6273 return;
6274
6275 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6276
6277 /* if interface is down do nothing */
6278 if (test_bit(__IXGBE_DOWN, &adapter->state))
6279 return;
6280
6281 /* do nothing if we are not using signature filters */
6282 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6283 return;
6284
6285 adapter->fdir_overflow++;
6286
6287 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6288 for (i = 0; i < adapter->num_tx_queues; i++)
6289 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6290 &(adapter->tx_ring[i]->state));
6291 /* re-enable flow director interrupts */
6292 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
6293 } else {
6294 e_err(probe, "failed to finish FDIR re-initialization, "
6295 "ignored adding FDIR ATR filters\n");
6296 }
6297 }
6298
6299 /**
6300 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6301 * @adapter: pointer to the device adapter structure
6302 *
6303 * This function serves two purposes. First it strobes the interrupt lines
6304 * in order to make certain interrupts are occurring. Secondly it sets the
6305 * bits needed to check for TX hangs. As a result we should immediately
6306 * determine if a hang has occurred.
6307 */
6308 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6309 {
6310 struct ixgbe_hw *hw = &adapter->hw;
6311 u64 eics = 0;
6312 int i;
6313
6314 /* If we're down, removing or resetting, just bail */
6315 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6316 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6317 test_bit(__IXGBE_RESETTING, &adapter->state))
6318 return;
6319
6320 /* Force detection of hung controller */
6321 if (netif_carrier_ok(adapter->netdev)) {
6322 for (i = 0; i < adapter->num_tx_queues; i++)
6323 set_check_for_tx_hang(adapter->tx_ring[i]);
6324 }
6325
6326 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6327 /*
6328 * for legacy and MSI interrupts don't set any bits
6329 * that are enabled for EIAM, because this operation
6330 * would set *both* EIMS and EICS for any bit in EIAM
6331 */
6332 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6333 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6334 } else {
6335 /* get one bit for every active tx/rx interrupt vector */
6336 for (i = 0; i < adapter->num_q_vectors; i++) {
6337 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6338 if (qv->rx.ring || qv->tx.ring)
6339 eics |= ((u64)1 << i);
6340 }
6341 }
6342
6343 /* Cause software interrupt to ensure rings are cleaned */
6344 ixgbe_irq_rearm_queues(adapter, eics);
6345 }
6346
6347 /**
6348 * ixgbe_watchdog_update_link - update the link status
6349 * @adapter: pointer to the device adapter structure
6350 * @link_speed: pointer to a u32 to store the link_speed
6351 **/
6352 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6353 {
6354 struct ixgbe_hw *hw = &adapter->hw;
6355 u32 link_speed = adapter->link_speed;
6356 bool link_up = adapter->link_up;
6357 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
6358
6359 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6360 return;
6361
6362 if (hw->mac.ops.check_link) {
6363 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6364 } else {
6365 /* always assume link is up, if no check link function */
6366 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6367 link_up = true;
6368 }
6369
6370 if (adapter->ixgbe_ieee_pfc)
6371 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6372
6373 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
6374 hw->mac.ops.fc_enable(hw);
6375 ixgbe_set_rx_drop_en(adapter);
6376 }
6377
6378 if (link_up ||
6379 time_after(jiffies, (adapter->link_check_timeout +
6380 IXGBE_TRY_LINK_TIMEOUT))) {
6381 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6382 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6383 IXGBE_WRITE_FLUSH(hw);
6384 }
6385
6386 adapter->link_up = link_up;
6387 adapter->link_speed = link_speed;
6388 }
6389
6390 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6391 {
6392 #ifdef CONFIG_IXGBE_DCB
6393 struct net_device *netdev = adapter->netdev;
6394 struct dcb_app app = {
6395 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6396 .protocol = 0,
6397 };
6398 u8 up = 0;
6399
6400 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6401 up = dcb_ieee_getapp_mask(netdev, &app);
6402
6403 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6404 #endif
6405 }
6406
6407 /**
6408 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6409 * print link up message
6410 * @adapter: pointer to the device adapter structure
6411 **/
6412 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6413 {
6414 struct net_device *netdev = adapter->netdev;
6415 struct ixgbe_hw *hw = &adapter->hw;
6416 struct net_device *upper;
6417 struct list_head *iter;
6418 u32 link_speed = adapter->link_speed;
6419 const char *speed_str;
6420 bool flow_rx, flow_tx;
6421
6422 /* only continue if link was previously down */
6423 if (netif_carrier_ok(netdev))
6424 return;
6425
6426 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6427
6428 switch (hw->mac.type) {
6429 case ixgbe_mac_82598EB: {
6430 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6431 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6432 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6433 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6434 }
6435 break;
6436 case ixgbe_mac_X540:
6437 case ixgbe_mac_X550:
6438 case ixgbe_mac_X550EM_x:
6439 case ixgbe_mac_82599EB: {
6440 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6441 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6442 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6443 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6444 }
6445 break;
6446 default:
6447 flow_tx = false;
6448 flow_rx = false;
6449 break;
6450 }
6451
6452 adapter->last_rx_ptp_check = jiffies;
6453
6454 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6455 ixgbe_ptp_start_cyclecounter(adapter);
6456
6457 switch (link_speed) {
6458 case IXGBE_LINK_SPEED_10GB_FULL:
6459 speed_str = "10 Gbps";
6460 break;
6461 case IXGBE_LINK_SPEED_2_5GB_FULL:
6462 speed_str = "2.5 Gbps";
6463 break;
6464 case IXGBE_LINK_SPEED_1GB_FULL:
6465 speed_str = "1 Gbps";
6466 break;
6467 case IXGBE_LINK_SPEED_100_FULL:
6468 speed_str = "100 Mbps";
6469 break;
6470 default:
6471 speed_str = "unknown speed";
6472 break;
6473 }
6474 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
6475 ((flow_rx && flow_tx) ? "RX/TX" :
6476 (flow_rx ? "RX" :
6477 (flow_tx ? "TX" : "None"))));
6478
6479 netif_carrier_on(netdev);
6480 ixgbe_check_vf_rate_limit(adapter);
6481
6482 /* enable transmits */
6483 netif_tx_wake_all_queues(adapter->netdev);
6484
6485 /* enable any upper devices */
6486 rtnl_lock();
6487 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6488 if (netif_is_macvlan(upper)) {
6489 struct macvlan_dev *vlan = netdev_priv(upper);
6490
6491 if (vlan->fwd_priv)
6492 netif_tx_wake_all_queues(upper);
6493 }
6494 }
6495 rtnl_unlock();
6496
6497 /* update the default user priority for VFs */
6498 ixgbe_update_default_up(adapter);
6499
6500 /* ping all the active vfs to let them know link has changed */
6501 ixgbe_ping_all_vfs(adapter);
6502 }
6503
6504 /**
6505 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6506 * print link down message
6507 * @adapter: pointer to the adapter structure
6508 **/
6509 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
6510 {
6511 struct net_device *netdev = adapter->netdev;
6512 struct ixgbe_hw *hw = &adapter->hw;
6513
6514 adapter->link_up = false;
6515 adapter->link_speed = 0;
6516
6517 /* only continue if link was up previously */
6518 if (!netif_carrier_ok(netdev))
6519 return;
6520
6521 /* poll for SFP+ cable when link is down */
6522 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6523 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6524
6525 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6526 ixgbe_ptp_start_cyclecounter(adapter);
6527
6528 e_info(drv, "NIC Link is Down\n");
6529 netif_carrier_off(netdev);
6530
6531 /* ping all the active vfs to let them know link has changed */
6532 ixgbe_ping_all_vfs(adapter);
6533 }
6534
6535 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6536 {
6537 int i;
6538
6539 for (i = 0; i < adapter->num_tx_queues; i++) {
6540 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6541
6542 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6543 return true;
6544 }
6545
6546 return false;
6547 }
6548
6549 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6550 {
6551 struct ixgbe_hw *hw = &adapter->hw;
6552 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6553 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6554
6555 int i, j;
6556
6557 if (!adapter->num_vfs)
6558 return false;
6559
6560 /* resetting the PF is only needed for MAC before X550 */
6561 if (hw->mac.type >= ixgbe_mac_X550)
6562 return false;
6563
6564 for (i = 0; i < adapter->num_vfs; i++) {
6565 for (j = 0; j < q_per_pool; j++) {
6566 u32 h, t;
6567
6568 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6569 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6570
6571 if (h != t)
6572 return true;
6573 }
6574 }
6575
6576 return false;
6577 }
6578
6579 /**
6580 * ixgbe_watchdog_flush_tx - flush queues on link down
6581 * @adapter: pointer to the device adapter structure
6582 **/
6583 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6584 {
6585 if (!netif_carrier_ok(adapter->netdev)) {
6586 if (ixgbe_ring_tx_pending(adapter) ||
6587 ixgbe_vf_tx_pending(adapter)) {
6588 /* We've lost link, so the controller stops DMA,
6589 * but we've got queued Tx work that's never going
6590 * to get done, so reset controller to flush Tx.
6591 * (Do the reset outside of interrupt context).
6592 */
6593 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
6594 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6595 }
6596 }
6597 }
6598
6599 #ifdef CONFIG_PCI_IOV
6600 static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6601 struct pci_dev *vfdev)
6602 {
6603 if (!pci_wait_for_pending_transaction(vfdev))
6604 e_dev_warn("Issuing VFLR with pending transactions\n");
6605
6606 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6607 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6608
6609 msleep(100);
6610 }
6611
6612 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6613 {
6614 struct ixgbe_hw *hw = &adapter->hw;
6615 struct pci_dev *pdev = adapter->pdev;
6616 struct pci_dev *vfdev;
6617 u32 gpc;
6618 int pos;
6619 unsigned short vf_id;
6620
6621 if (!(netif_carrier_ok(adapter->netdev)))
6622 return;
6623
6624 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6625 if (gpc) /* If incrementing then no need for the check below */
6626 return;
6627 /* Check to see if a bad DMA write target from an errant or
6628 * malicious VF has caused a PCIe error. If so then we can
6629 * issue a VFLR to the offending VF(s) and then resume without
6630 * requesting a full slot reset.
6631 */
6632
6633 if (!pdev)
6634 return;
6635
6636 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6637 if (!pos)
6638 return;
6639
6640 /* get the device ID for the VF */
6641 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6642
6643 /* check status reg for all VFs owned by this PF */
6644 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6645 while (vfdev) {
6646 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6647 u16 status_reg;
6648
6649 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6650 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6651 /* issue VFLR */
6652 ixgbe_issue_vf_flr(adapter, vfdev);
6653 }
6654
6655 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6656 }
6657 }
6658
6659 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6660 {
6661 u32 ssvpc;
6662
6663 /* Do not perform spoof check for 82598 or if not in IOV mode */
6664 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6665 adapter->num_vfs == 0)
6666 return;
6667
6668 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6669
6670 /*
6671 * ssvpc register is cleared on read, if zero then no
6672 * spoofed packets in the last interval.
6673 */
6674 if (!ssvpc)
6675 return;
6676
6677 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
6678 }
6679 #else
6680 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6681 {
6682 }
6683
6684 static void
6685 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6686 {
6687 }
6688 #endif /* CONFIG_PCI_IOV */
6689
6690
6691 /**
6692 * ixgbe_watchdog_subtask - check and bring link up
6693 * @adapter: pointer to the device adapter structure
6694 **/
6695 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6696 {
6697 /* if interface is down, removing or resetting, do nothing */
6698 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6699 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6700 test_bit(__IXGBE_RESETTING, &adapter->state))
6701 return;
6702
6703 ixgbe_watchdog_update_link(adapter);
6704
6705 if (adapter->link_up)
6706 ixgbe_watchdog_link_is_up(adapter);
6707 else
6708 ixgbe_watchdog_link_is_down(adapter);
6709
6710 ixgbe_check_for_bad_vf(adapter);
6711 ixgbe_spoof_check(adapter);
6712 ixgbe_update_stats(adapter);
6713
6714 ixgbe_watchdog_flush_tx(adapter);
6715 }
6716
6717 /**
6718 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6719 * @adapter: the ixgbe adapter structure
6720 **/
6721 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6722 {
6723 struct ixgbe_hw *hw = &adapter->hw;
6724 s32 err;
6725
6726 /* not searching for SFP so there is nothing to do here */
6727 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6728 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6729 return;
6730
6731 if (adapter->sfp_poll_time &&
6732 time_after(adapter->sfp_poll_time, jiffies))
6733 return; /* If not yet time to poll for SFP */
6734
6735 /* someone else is in init, wait until next service event */
6736 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6737 return;
6738
6739 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6740
6741 err = hw->phy.ops.identify_sfp(hw);
6742 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6743 goto sfp_out;
6744
6745 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6746 /* If no cable is present, then we need to reset
6747 * the next time we find a good cable. */
6748 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6749 }
6750
6751 /* exit on error */
6752 if (err)
6753 goto sfp_out;
6754
6755 /* exit if reset not needed */
6756 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6757 goto sfp_out;
6758
6759 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6760
6761 /*
6762 * A module may be identified correctly, but the EEPROM may not have
6763 * support for that module. setup_sfp() will fail in that case, so
6764 * we should not allow that module to load.
6765 */
6766 if (hw->mac.type == ixgbe_mac_82598EB)
6767 err = hw->phy.ops.reset(hw);
6768 else
6769 err = hw->mac.ops.setup_sfp(hw);
6770
6771 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6772 goto sfp_out;
6773
6774 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6775 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6776
6777 sfp_out:
6778 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6779
6780 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6781 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6782 e_dev_err("failed to initialize because an unsupported "
6783 "SFP+ module type was detected.\n");
6784 e_dev_err("Reload the driver after installing a "
6785 "supported module.\n");
6786 unregister_netdev(adapter->netdev);
6787 }
6788 }
6789
6790 /**
6791 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6792 * @adapter: the ixgbe adapter structure
6793 **/
6794 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6795 {
6796 struct ixgbe_hw *hw = &adapter->hw;
6797 u32 speed;
6798 bool autoneg = false;
6799
6800 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6801 return;
6802
6803 /* someone else is in init, wait until next service event */
6804 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6805 return;
6806
6807 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6808
6809 speed = hw->phy.autoneg_advertised;
6810 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
6811 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
6812
6813 /* setup the highest link when no autoneg */
6814 if (!autoneg) {
6815 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6816 speed = IXGBE_LINK_SPEED_10GB_FULL;
6817 }
6818 }
6819
6820 if (hw->mac.ops.setup_link)
6821 hw->mac.ops.setup_link(hw, speed, true);
6822
6823 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6824 adapter->link_check_timeout = jiffies;
6825 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6826 }
6827
6828 /**
6829 * ixgbe_service_timer - Timer Call-back
6830 * @data: pointer to adapter cast into an unsigned long
6831 **/
6832 static void ixgbe_service_timer(unsigned long data)
6833 {
6834 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6835 unsigned long next_event_offset;
6836
6837 /* poll faster when waiting for link */
6838 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6839 next_event_offset = HZ / 10;
6840 else
6841 next_event_offset = HZ * 2;
6842
6843 /* Reset the timer */
6844 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6845
6846 ixgbe_service_event_schedule(adapter);
6847 }
6848
6849 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6850 {
6851 struct ixgbe_hw *hw = &adapter->hw;
6852 u32 status;
6853
6854 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6855 return;
6856
6857 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6858
6859 if (!hw->phy.ops.handle_lasi)
6860 return;
6861
6862 status = hw->phy.ops.handle_lasi(&adapter->hw);
6863 if (status != IXGBE_ERR_OVERTEMP)
6864 return;
6865
6866 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6867 }
6868
6869 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6870 {
6871 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6872 return;
6873
6874 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6875
6876 /* If we're already down, removing or resetting, just bail */
6877 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6878 test_bit(__IXGBE_REMOVING, &adapter->state) ||
6879 test_bit(__IXGBE_RESETTING, &adapter->state))
6880 return;
6881
6882 ixgbe_dump(adapter);
6883 netdev_err(adapter->netdev, "Reset adapter\n");
6884 adapter->tx_timeout_count++;
6885
6886 rtnl_lock();
6887 ixgbe_reinit_locked(adapter);
6888 rtnl_unlock();
6889 }
6890
6891 /**
6892 * ixgbe_service_task - manages and runs subtasks
6893 * @work: pointer to work_struct containing our data
6894 **/
6895 static void ixgbe_service_task(struct work_struct *work)
6896 {
6897 struct ixgbe_adapter *adapter = container_of(work,
6898 struct ixgbe_adapter,
6899 service_task);
6900 if (ixgbe_removed(adapter->hw.hw_addr)) {
6901 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6902 rtnl_lock();
6903 ixgbe_down(adapter);
6904 rtnl_unlock();
6905 }
6906 ixgbe_service_event_complete(adapter);
6907 return;
6908 }
6909 #ifdef CONFIG_IXGBE_VXLAN
6910 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6911 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6912 vxlan_get_rx_port(adapter->netdev);
6913 }
6914 #endif /* CONFIG_IXGBE_VXLAN */
6915 ixgbe_reset_subtask(adapter);
6916 ixgbe_phy_interrupt_subtask(adapter);
6917 ixgbe_sfp_detection_subtask(adapter);
6918 ixgbe_sfp_link_config_subtask(adapter);
6919 ixgbe_check_overtemp_subtask(adapter);
6920 ixgbe_watchdog_subtask(adapter);
6921 ixgbe_fdir_reinit_subtask(adapter);
6922 ixgbe_check_hang_subtask(adapter);
6923
6924 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
6925 ixgbe_ptp_overflow_check(adapter);
6926 ixgbe_ptp_rx_hang(adapter);
6927 }
6928
6929 ixgbe_service_event_complete(adapter);
6930 }
6931
6932 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6933 struct ixgbe_tx_buffer *first,
6934 u8 *hdr_len)
6935 {
6936 struct sk_buff *skb = first->skb;
6937 u32 vlan_macip_lens, type_tucmd;
6938 u32 mss_l4len_idx, l4len;
6939 int err;
6940
6941 if (skb->ip_summed != CHECKSUM_PARTIAL)
6942 return 0;
6943
6944 if (!skb_is_gso(skb))
6945 return 0;
6946
6947 err = skb_cow_head(skb, 0);
6948 if (err < 0)
6949 return err;
6950
6951 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6952 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6953
6954 if (first->protocol == htons(ETH_P_IP)) {
6955 struct iphdr *iph = ip_hdr(skb);
6956 iph->tot_len = 0;
6957 iph->check = 0;
6958 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6959 iph->daddr, 0,
6960 IPPROTO_TCP,
6961 0);
6962 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6963 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6964 IXGBE_TX_FLAGS_CSUM |
6965 IXGBE_TX_FLAGS_IPV4;
6966 } else if (skb_is_gso_v6(skb)) {
6967 ipv6_hdr(skb)->payload_len = 0;
6968 tcp_hdr(skb)->check =
6969 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6970 &ipv6_hdr(skb)->daddr,
6971 0, IPPROTO_TCP, 0);
6972 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6973 IXGBE_TX_FLAGS_CSUM;
6974 }
6975
6976 /* compute header lengths */
6977 l4len = tcp_hdrlen(skb);
6978 *hdr_len = skb_transport_offset(skb) + l4len;
6979
6980 /* update gso size and bytecount with header size */
6981 first->gso_segs = skb_shinfo(skb)->gso_segs;
6982 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6983
6984 /* mss_l4len_id: use 0 as index for TSO */
6985 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6986 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6987
6988 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6989 vlan_macip_lens = skb_network_header_len(skb);
6990 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6991 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6992
6993 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6994 mss_l4len_idx);
6995
6996 return 1;
6997 }
6998
6999 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7000 struct ixgbe_tx_buffer *first)
7001 {
7002 struct sk_buff *skb = first->skb;
7003 u32 vlan_macip_lens = 0;
7004 u32 mss_l4len_idx = 0;
7005 u32 type_tucmd = 0;
7006
7007 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7008 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7009 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7010 return;
7011 vlan_macip_lens = skb_network_offset(skb) <<
7012 IXGBE_ADVTXD_MACLEN_SHIFT;
7013 } else {
7014 u8 l4_hdr = 0;
7015 union {
7016 struct iphdr *ipv4;
7017 struct ipv6hdr *ipv6;
7018 u8 *raw;
7019 } network_hdr;
7020 union {
7021 struct tcphdr *tcphdr;
7022 u8 *raw;
7023 } transport_hdr;
7024
7025 if (skb->encapsulation) {
7026 network_hdr.raw = skb_inner_network_header(skb);
7027 transport_hdr.raw = skb_inner_transport_header(skb);
7028 vlan_macip_lens = skb_inner_network_offset(skb) <<
7029 IXGBE_ADVTXD_MACLEN_SHIFT;
7030 } else {
7031 network_hdr.raw = skb_network_header(skb);
7032 transport_hdr.raw = skb_transport_header(skb);
7033 vlan_macip_lens = skb_network_offset(skb) <<
7034 IXGBE_ADVTXD_MACLEN_SHIFT;
7035 }
7036
7037 /* use first 4 bits to determine IP version */
7038 switch (network_hdr.ipv4->version) {
7039 case IPVERSION:
7040 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7041 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
7042 l4_hdr = network_hdr.ipv4->protocol;
7043 break;
7044 case 6:
7045 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7046 l4_hdr = network_hdr.ipv6->nexthdr;
7047 break;
7048 default:
7049 if (unlikely(net_ratelimit())) {
7050 dev_warn(tx_ring->dev,
7051 "partial checksum but version=%d\n",
7052 network_hdr.ipv4->version);
7053 }
7054 }
7055
7056 switch (l4_hdr) {
7057 case IPPROTO_TCP:
7058 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
7059 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
7060 IXGBE_ADVTXD_L4LEN_SHIFT;
7061 break;
7062 case IPPROTO_SCTP:
7063 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7064 mss_l4len_idx = sizeof(struct sctphdr) <<
7065 IXGBE_ADVTXD_L4LEN_SHIFT;
7066 break;
7067 case IPPROTO_UDP:
7068 mss_l4len_idx = sizeof(struct udphdr) <<
7069 IXGBE_ADVTXD_L4LEN_SHIFT;
7070 break;
7071 default:
7072 if (unlikely(net_ratelimit())) {
7073 dev_warn(tx_ring->dev,
7074 "partial checksum but l4 proto=%x!\n",
7075 l4_hdr);
7076 }
7077 break;
7078 }
7079
7080 /* update TX checksum flag */
7081 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7082 }
7083
7084 /* vlan_macip_lens: MACLEN, VLAN tag */
7085 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
7086
7087 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7088 type_tucmd, mss_l4len_idx);
7089 }
7090
7091 #define IXGBE_SET_FLAG(_input, _flag, _result) \
7092 ((_flag <= _result) ? \
7093 ((u32)(_input & _flag) * (_result / _flag)) : \
7094 ((u32)(_input & _flag) / (_flag / _result)))
7095
7096 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
7097 {
7098 /* set type for advanced descriptor with frame checksum insertion */
7099 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7100 IXGBE_ADVTXD_DCMD_DEXT |
7101 IXGBE_ADVTXD_DCMD_IFCS;
7102
7103 /* set HW vlan bit if vlan is present */
7104 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7105 IXGBE_ADVTXD_DCMD_VLE);
7106
7107 /* set segmentation enable bits for TSO/FSO */
7108 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7109 IXGBE_ADVTXD_DCMD_TSE);
7110
7111 /* set timestamp bit if present */
7112 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7113 IXGBE_ADVTXD_MAC_TSTAMP);
7114
7115 /* insert frame checksum */
7116 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
7117
7118 return cmd_type;
7119 }
7120
7121 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7122 u32 tx_flags, unsigned int paylen)
7123 {
7124 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
7125
7126 /* enable L4 checksum for TSO and TX checksum offload */
7127 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7128 IXGBE_TX_FLAGS_CSUM,
7129 IXGBE_ADVTXD_POPTS_TXSM);
7130
7131 /* enble IPv4 checksum for TSO */
7132 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7133 IXGBE_TX_FLAGS_IPV4,
7134 IXGBE_ADVTXD_POPTS_IXSM);
7135
7136 /*
7137 * Check Context must be set if Tx switch is enabled, which it
7138 * always is for case where virtual functions are running
7139 */
7140 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7141 IXGBE_TX_FLAGS_CC,
7142 IXGBE_ADVTXD_CC);
7143
7144 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
7145 }
7146
7147 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7148 {
7149 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7150
7151 /* Herbert's original patch had:
7152 * smp_mb__after_netif_stop_queue();
7153 * but since that doesn't exist yet, just open code it.
7154 */
7155 smp_mb();
7156
7157 /* We need to check again in a case another CPU has just
7158 * made room available.
7159 */
7160 if (likely(ixgbe_desc_unused(tx_ring) < size))
7161 return -EBUSY;
7162
7163 /* A reprieve! - use start_queue because it doesn't call schedule */
7164 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7165 ++tx_ring->tx_stats.restart_queue;
7166 return 0;
7167 }
7168
7169 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7170 {
7171 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7172 return 0;
7173
7174 return __ixgbe_maybe_stop_tx(tx_ring, size);
7175 }
7176
7177 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7178 IXGBE_TXD_CMD_RS)
7179
7180 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
7181 struct ixgbe_tx_buffer *first,
7182 const u8 hdr_len)
7183 {
7184 struct sk_buff *skb = first->skb;
7185 struct ixgbe_tx_buffer *tx_buffer;
7186 union ixgbe_adv_tx_desc *tx_desc;
7187 struct skb_frag_struct *frag;
7188 dma_addr_t dma;
7189 unsigned int data_len, size;
7190 u32 tx_flags = first->tx_flags;
7191 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
7192 u16 i = tx_ring->next_to_use;
7193
7194 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7195
7196 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7197
7198 size = skb_headlen(skb);
7199 data_len = skb->data_len;
7200
7201 #ifdef IXGBE_FCOE
7202 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
7203 if (data_len < sizeof(struct fcoe_crc_eof)) {
7204 size -= sizeof(struct fcoe_crc_eof) - data_len;
7205 data_len = 0;
7206 } else {
7207 data_len -= sizeof(struct fcoe_crc_eof);
7208 }
7209 }
7210
7211 #endif
7212 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
7213
7214 tx_buffer = first;
7215
7216 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7217 if (dma_mapping_error(tx_ring->dev, dma))
7218 goto dma_error;
7219
7220 /* record length, and DMA address */
7221 dma_unmap_len_set(tx_buffer, len, size);
7222 dma_unmap_addr_set(tx_buffer, dma, dma);
7223
7224 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7225
7226 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
7227 tx_desc->read.cmd_type_len =
7228 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
7229
7230 i++;
7231 tx_desc++;
7232 if (i == tx_ring->count) {
7233 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7234 i = 0;
7235 }
7236 tx_desc->read.olinfo_status = 0;
7237
7238 dma += IXGBE_MAX_DATA_PER_TXD;
7239 size -= IXGBE_MAX_DATA_PER_TXD;
7240
7241 tx_desc->read.buffer_addr = cpu_to_le64(dma);
7242 }
7243
7244 if (likely(!data_len))
7245 break;
7246
7247 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
7248
7249 i++;
7250 tx_desc++;
7251 if (i == tx_ring->count) {
7252 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7253 i = 0;
7254 }
7255 tx_desc->read.olinfo_status = 0;
7256
7257 #ifdef IXGBE_FCOE
7258 size = min_t(unsigned int, data_len, skb_frag_size(frag));
7259 #else
7260 size = skb_frag_size(frag);
7261 #endif
7262 data_len -= size;
7263
7264 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7265 DMA_TO_DEVICE);
7266
7267 tx_buffer = &tx_ring->tx_buffer_info[i];
7268 }
7269
7270 /* write last descriptor with RS and EOP bits */
7271 cmd_type |= size | IXGBE_TXD_CMD;
7272 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
7273
7274 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
7275
7276 /* set the timestamp */
7277 first->time_stamp = jiffies;
7278
7279 /*
7280 * Force memory writes to complete before letting h/w know there
7281 * are new descriptors to fetch. (Only applicable for weak-ordered
7282 * memory model archs, such as IA-64).
7283 *
7284 * We also need this memory barrier to make certain all of the
7285 * status bits have been updated before next_to_watch is written.
7286 */
7287 wmb();
7288
7289 /* set next_to_watch value indicating a packet is present */
7290 first->next_to_watch = tx_desc;
7291
7292 i++;
7293 if (i == tx_ring->count)
7294 i = 0;
7295
7296 tx_ring->next_to_use = i;
7297
7298 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7299
7300 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
7301 writel(i, tx_ring->tail);
7302
7303 /* we need this if more than one processor can write to our tail
7304 * at a time, it synchronizes IO on IA64/Altix systems
7305 */
7306 mmiowb();
7307 }
7308
7309 return;
7310 dma_error:
7311 dev_err(tx_ring->dev, "TX DMA map failed\n");
7312
7313 /* clear dma mappings for failed tx_buffer_info map */
7314 for (;;) {
7315 tx_buffer = &tx_ring->tx_buffer_info[i];
7316 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7317 if (tx_buffer == first)
7318 break;
7319 if (i == 0)
7320 i = tx_ring->count;
7321 i--;
7322 }
7323
7324 tx_ring->next_to_use = i;
7325 }
7326
7327 static void ixgbe_atr(struct ixgbe_ring *ring,
7328 struct ixgbe_tx_buffer *first)
7329 {
7330 struct ixgbe_q_vector *q_vector = ring->q_vector;
7331 union ixgbe_atr_hash_dword input = { .dword = 0 };
7332 union ixgbe_atr_hash_dword common = { .dword = 0 };
7333 union {
7334 unsigned char *network;
7335 struct iphdr *ipv4;
7336 struct ipv6hdr *ipv6;
7337 } hdr;
7338 struct tcphdr *th;
7339 struct sk_buff *skb;
7340 #ifdef CONFIG_IXGBE_VXLAN
7341 u8 encap = false;
7342 #endif /* CONFIG_IXGBE_VXLAN */
7343 __be16 vlan_id;
7344
7345 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7346 if (!q_vector)
7347 return;
7348
7349 /* do nothing if sampling is disabled */
7350 if (!ring->atr_sample_rate)
7351 return;
7352
7353 ring->atr_count++;
7354
7355 /* snag network header to get L4 type and address */
7356 skb = first->skb;
7357 hdr.network = skb_network_header(skb);
7358 if (skb->encapsulation) {
7359 #ifdef CONFIG_IXGBE_VXLAN
7360 struct ixgbe_adapter *adapter = q_vector->adapter;
7361
7362 if (!adapter->vxlan_port)
7363 return;
7364 if (first->protocol != htons(ETH_P_IP) ||
7365 hdr.ipv4->version != IPVERSION ||
7366 hdr.ipv4->protocol != IPPROTO_UDP) {
7367 return;
7368 }
7369 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7370 return;
7371 encap = true;
7372 hdr.network = skb_inner_network_header(skb);
7373 th = inner_tcp_hdr(skb);
7374 #else
7375 return;
7376 #endif /* CONFIG_IXGBE_VXLAN */
7377 } else {
7378 /* Currently only IPv4/IPv6 with TCP is supported */
7379 if ((first->protocol != htons(ETH_P_IPV6) ||
7380 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7381 (first->protocol != htons(ETH_P_IP) ||
7382 hdr.ipv4->protocol != IPPROTO_TCP))
7383 return;
7384 th = tcp_hdr(skb);
7385 }
7386
7387 /* skip this packet since it is invalid or the socket is closing */
7388 if (!th || th->fin)
7389 return;
7390
7391 /* sample on all syn packets or once every atr sample count */
7392 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7393 return;
7394
7395 /* reset sample count */
7396 ring->atr_count = 0;
7397
7398 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
7399
7400 /*
7401 * src and dst are inverted, think how the receiver sees them
7402 *
7403 * The input is broken into two sections, a non-compressed section
7404 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7405 * is XORed together and stored in the compressed dword.
7406 */
7407 input.formatted.vlan_id = vlan_id;
7408
7409 /*
7410 * since src port and flex bytes occupy the same word XOR them together
7411 * and write the value to source port portion of compressed dword
7412 */
7413 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
7414 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
7415 else
7416 common.port.src ^= th->dest ^ first->protocol;
7417 common.port.dst ^= th->source;
7418
7419 if (first->protocol == htons(ETH_P_IP)) {
7420 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7421 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7422 } else {
7423 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7424 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7425 hdr.ipv6->saddr.s6_addr32[1] ^
7426 hdr.ipv6->saddr.s6_addr32[2] ^
7427 hdr.ipv6->saddr.s6_addr32[3] ^
7428 hdr.ipv6->daddr.s6_addr32[0] ^
7429 hdr.ipv6->daddr.s6_addr32[1] ^
7430 hdr.ipv6->daddr.s6_addr32[2] ^
7431 hdr.ipv6->daddr.s6_addr32[3];
7432 }
7433
7434 #ifdef CONFIG_IXGBE_VXLAN
7435 if (encap)
7436 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7437 #endif /* CONFIG_IXGBE_VXLAN */
7438
7439 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
7440 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7441 input, common, ring->queue_index);
7442 }
7443
7444 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
7445 void *accel_priv, select_queue_fallback_t fallback)
7446 {
7447 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7448 #ifdef IXGBE_FCOE
7449 struct ixgbe_adapter *adapter;
7450 struct ixgbe_ring_feature *f;
7451 int txq;
7452 #endif
7453
7454 if (fwd_adapter)
7455 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7456
7457 #ifdef IXGBE_FCOE
7458
7459 /*
7460 * only execute the code below if protocol is FCoE
7461 * or FIP and we have FCoE enabled on the adapter
7462 */
7463 switch (vlan_get_protocol(skb)) {
7464 case htons(ETH_P_FCOE):
7465 case htons(ETH_P_FIP):
7466 adapter = netdev_priv(dev);
7467
7468 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7469 break;
7470 default:
7471 return fallback(dev, skb);
7472 }
7473
7474 f = &adapter->ring_feature[RING_F_FCOE];
7475
7476 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7477 smp_processor_id();
7478
7479 while (txq >= f->indices)
7480 txq -= f->indices;
7481
7482 return txq + f->offset;
7483 #else
7484 return fallback(dev, skb);
7485 #endif
7486 }
7487
7488 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
7489 struct ixgbe_adapter *adapter,
7490 struct ixgbe_ring *tx_ring)
7491 {
7492 struct ixgbe_tx_buffer *first;
7493 int tso;
7494 u32 tx_flags = 0;
7495 unsigned short f;
7496 u16 count = TXD_USE_COUNT(skb_headlen(skb));
7497 __be16 protocol = skb->protocol;
7498 u8 hdr_len = 0;
7499
7500 /*
7501 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
7502 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
7503 * + 2 desc gap to keep tail from touching head,
7504 * + 1 desc for context descriptor,
7505 * otherwise try next time
7506 */
7507 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7508 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7509
7510 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7511 tx_ring->tx_stats.tx_busy++;
7512 return NETDEV_TX_BUSY;
7513 }
7514
7515 /* record the location of the first descriptor for this packet */
7516 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7517 first->skb = skb;
7518 first->bytecount = skb->len;
7519 first->gso_segs = 1;
7520
7521 /* if we have a HW VLAN tag being added default to the HW one */
7522 if (skb_vlan_tag_present(skb)) {
7523 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7524 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7525 /* else if it is a SW VLAN check the next protocol and store the tag */
7526 } else if (protocol == htons(ETH_P_8021Q)) {
7527 struct vlan_hdr *vhdr, _vhdr;
7528 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7529 if (!vhdr)
7530 goto out_drop;
7531
7532 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7533 IXGBE_TX_FLAGS_VLAN_SHIFT;
7534 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7535 }
7536 protocol = vlan_get_protocol(skb);
7537
7538 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7539 adapter->ptp_clock &&
7540 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7541 &adapter->state)) {
7542 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7543 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
7544
7545 /* schedule check for Tx timestamp */
7546 adapter->ptp_tx_skb = skb_get(skb);
7547 adapter->ptp_tx_start = jiffies;
7548 schedule_work(&adapter->ptp_tx_work);
7549 }
7550
7551 skb_tx_timestamp(skb);
7552
7553 #ifdef CONFIG_PCI_IOV
7554 /*
7555 * Use the l2switch_enable flag - would be false if the DMA
7556 * Tx switch had been disabled.
7557 */
7558 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7559 tx_flags |= IXGBE_TX_FLAGS_CC;
7560
7561 #endif
7562 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
7563 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7564 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7565 (skb->priority != TC_PRIO_CONTROL))) {
7566 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
7567 tx_flags |= (skb->priority & 0x7) <<
7568 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
7569 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7570 struct vlan_ethhdr *vhdr;
7571
7572 if (skb_cow_head(skb, 0))
7573 goto out_drop;
7574 vhdr = (struct vlan_ethhdr *)skb->data;
7575 vhdr->h_vlan_TCI = htons(tx_flags >>
7576 IXGBE_TX_FLAGS_VLAN_SHIFT);
7577 } else {
7578 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7579 }
7580 }
7581
7582 /* record initial flags and protocol */
7583 first->tx_flags = tx_flags;
7584 first->protocol = protocol;
7585
7586 #ifdef IXGBE_FCOE
7587 /* setup tx offload for FCoE */
7588 if ((protocol == htons(ETH_P_FCOE)) &&
7589 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
7590 tso = ixgbe_fso(tx_ring, first, &hdr_len);
7591 if (tso < 0)
7592 goto out_drop;
7593
7594 goto xmit_fcoe;
7595 }
7596
7597 #endif /* IXGBE_FCOE */
7598 tso = ixgbe_tso(tx_ring, first, &hdr_len);
7599 if (tso < 0)
7600 goto out_drop;
7601 else if (!tso)
7602 ixgbe_tx_csum(tx_ring, first);
7603
7604 /* add the ATR filter if ATR is on */
7605 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7606 ixgbe_atr(tx_ring, first);
7607
7608 #ifdef IXGBE_FCOE
7609 xmit_fcoe:
7610 #endif /* IXGBE_FCOE */
7611 ixgbe_tx_map(tx_ring, first, hdr_len);
7612
7613 return NETDEV_TX_OK;
7614
7615 out_drop:
7616 dev_kfree_skb_any(first->skb);
7617 first->skb = NULL;
7618
7619 return NETDEV_TX_OK;
7620 }
7621
7622 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7623 struct net_device *netdev,
7624 struct ixgbe_ring *ring)
7625 {
7626 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7627 struct ixgbe_ring *tx_ring;
7628
7629 /*
7630 * The minimum packet size for olinfo paylen is 17 so pad the skb
7631 * in order to meet this minimum size requirement.
7632 */
7633 if (skb_put_padto(skb, 17))
7634 return NETDEV_TX_OK;
7635
7636 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7637
7638 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7639 }
7640
7641 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7642 struct net_device *netdev)
7643 {
7644 return __ixgbe_xmit_frame(skb, netdev, NULL);
7645 }
7646
7647 /**
7648 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7649 * @netdev: network interface device structure
7650 * @p: pointer to an address structure
7651 *
7652 * Returns 0 on success, negative on failure
7653 **/
7654 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7655 {
7656 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7657 struct ixgbe_hw *hw = &adapter->hw;
7658 struct sockaddr *addr = p;
7659 int ret;
7660
7661 if (!is_valid_ether_addr(addr->sa_data))
7662 return -EADDRNOTAVAIL;
7663
7664 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7665 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7666 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7667
7668 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7669 return ret > 0 ? 0 : ret;
7670 }
7671
7672 static int
7673 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7674 {
7675 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7676 struct ixgbe_hw *hw = &adapter->hw;
7677 u16 value;
7678 int rc;
7679
7680 if (prtad != hw->phy.mdio.prtad)
7681 return -EINVAL;
7682 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7683 if (!rc)
7684 rc = value;
7685 return rc;
7686 }
7687
7688 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7689 u16 addr, u16 value)
7690 {
7691 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7692 struct ixgbe_hw *hw = &adapter->hw;
7693
7694 if (prtad != hw->phy.mdio.prtad)
7695 return -EINVAL;
7696 return hw->phy.ops.write_reg(hw, addr, devad, value);
7697 }
7698
7699 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7700 {
7701 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7702
7703 switch (cmd) {
7704 case SIOCSHWTSTAMP:
7705 return ixgbe_ptp_set_ts_config(adapter, req);
7706 case SIOCGHWTSTAMP:
7707 return ixgbe_ptp_get_ts_config(adapter, req);
7708 default:
7709 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7710 }
7711 }
7712
7713 /**
7714 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7715 * netdev->dev_addrs
7716 * @netdev: network interface device structure
7717 *
7718 * Returns non-zero on failure
7719 **/
7720 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7721 {
7722 int err = 0;
7723 struct ixgbe_adapter *adapter = netdev_priv(dev);
7724 struct ixgbe_hw *hw = &adapter->hw;
7725
7726 if (is_valid_ether_addr(hw->mac.san_addr)) {
7727 rtnl_lock();
7728 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
7729 rtnl_unlock();
7730
7731 /* update SAN MAC vmdq pool selection */
7732 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
7733 }
7734 return err;
7735 }
7736
7737 /**
7738 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7739 * netdev->dev_addrs
7740 * @netdev: network interface device structure
7741 *
7742 * Returns non-zero on failure
7743 **/
7744 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7745 {
7746 int err = 0;
7747 struct ixgbe_adapter *adapter = netdev_priv(dev);
7748 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7749
7750 if (is_valid_ether_addr(mac->san_addr)) {
7751 rtnl_lock();
7752 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7753 rtnl_unlock();
7754 }
7755 return err;
7756 }
7757
7758 #ifdef CONFIG_NET_POLL_CONTROLLER
7759 /*
7760 * Polling 'interrupt' - used by things like netconsole to send skbs
7761 * without having to re-enable interrupts. It's not called while
7762 * the interrupt routine is executing.
7763 */
7764 static void ixgbe_netpoll(struct net_device *netdev)
7765 {
7766 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7767 int i;
7768
7769 /* if interface is down do nothing */
7770 if (test_bit(__IXGBE_DOWN, &adapter->state))
7771 return;
7772
7773 /* loop through and schedule all active queues */
7774 for (i = 0; i < adapter->num_q_vectors; i++)
7775 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
7776 }
7777
7778 #endif
7779 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7780 struct rtnl_link_stats64 *stats)
7781 {
7782 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7783 int i;
7784
7785 rcu_read_lock();
7786 for (i = 0; i < adapter->num_rx_queues; i++) {
7787 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7788 u64 bytes, packets;
7789 unsigned int start;
7790
7791 if (ring) {
7792 do {
7793 start = u64_stats_fetch_begin_irq(&ring->syncp);
7794 packets = ring->stats.packets;
7795 bytes = ring->stats.bytes;
7796 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7797 stats->rx_packets += packets;
7798 stats->rx_bytes += bytes;
7799 }
7800 }
7801
7802 for (i = 0; i < adapter->num_tx_queues; i++) {
7803 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7804 u64 bytes, packets;
7805 unsigned int start;
7806
7807 if (ring) {
7808 do {
7809 start = u64_stats_fetch_begin_irq(&ring->syncp);
7810 packets = ring->stats.packets;
7811 bytes = ring->stats.bytes;
7812 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
7813 stats->tx_packets += packets;
7814 stats->tx_bytes += bytes;
7815 }
7816 }
7817 rcu_read_unlock();
7818 /* following stats updated by ixgbe_watchdog_task() */
7819 stats->multicast = netdev->stats.multicast;
7820 stats->rx_errors = netdev->stats.rx_errors;
7821 stats->rx_length_errors = netdev->stats.rx_length_errors;
7822 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7823 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7824 return stats;
7825 }
7826
7827 #ifdef CONFIG_IXGBE_DCB
7828 /**
7829 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7830 * @adapter: pointer to ixgbe_adapter
7831 * @tc: number of traffic classes currently enabled
7832 *
7833 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7834 * 802.1Q priority maps to a packet buffer that exists.
7835 */
7836 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7837 {
7838 struct ixgbe_hw *hw = &adapter->hw;
7839 u32 reg, rsave;
7840 int i;
7841
7842 /* 82598 have a static priority to TC mapping that can not
7843 * be changed so no validation is needed.
7844 */
7845 if (hw->mac.type == ixgbe_mac_82598EB)
7846 return;
7847
7848 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7849 rsave = reg;
7850
7851 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7852 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7853
7854 /* If up2tc is out of bounds default to zero */
7855 if (up2tc > tc)
7856 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7857 }
7858
7859 if (reg != rsave)
7860 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7861
7862 return;
7863 }
7864
7865 /**
7866 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7867 * @adapter: Pointer to adapter struct
7868 *
7869 * Populate the netdev user priority to tc map
7870 */
7871 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7872 {
7873 struct net_device *dev = adapter->netdev;
7874 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7875 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7876 u8 prio;
7877
7878 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7879 u8 tc = 0;
7880
7881 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7882 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7883 else if (ets)
7884 tc = ets->prio_tc[prio];
7885
7886 netdev_set_prio_tc_map(dev, prio, tc);
7887 }
7888 }
7889
7890 #endif /* CONFIG_IXGBE_DCB */
7891 /**
7892 * ixgbe_setup_tc - configure net_device for multiple traffic classes
7893 *
7894 * @netdev: net device to configure
7895 * @tc: number of traffic classes to enable
7896 */
7897 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7898 {
7899 struct ixgbe_adapter *adapter = netdev_priv(dev);
7900 struct ixgbe_hw *hw = &adapter->hw;
7901 bool pools;
7902
7903 /* Hardware supports up to 8 traffic classes */
7904 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
7905 return -EINVAL;
7906
7907 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
7908 return -EINVAL;
7909
7910 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7911 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7912 return -EBUSY;
7913
7914 /* Hardware has to reinitialize queues and interrupts to
7915 * match packet buffer alignment. Unfortunately, the
7916 * hardware is not flexible enough to do this dynamically.
7917 */
7918 if (netif_running(dev))
7919 ixgbe_close(dev);
7920 ixgbe_clear_interrupt_scheme(adapter);
7921
7922 #ifdef CONFIG_IXGBE_DCB
7923 if (tc) {
7924 netdev_set_num_tc(dev, tc);
7925 ixgbe_set_prio_tc_map(adapter);
7926
7927 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7928
7929 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7930 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
7931 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7932 }
7933 } else {
7934 netdev_reset_tc(dev);
7935
7936 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7937 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7938
7939 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7940
7941 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7942 adapter->dcb_cfg.pfc_mode_enable = false;
7943 }
7944
7945 ixgbe_validate_rtr(adapter, tc);
7946
7947 #endif /* CONFIG_IXGBE_DCB */
7948 ixgbe_init_interrupt_scheme(adapter);
7949
7950 if (netif_running(dev))
7951 return ixgbe_open(dev);
7952
7953 return 0;
7954 }
7955
7956 #ifdef CONFIG_PCI_IOV
7957 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7958 {
7959 struct net_device *netdev = adapter->netdev;
7960
7961 rtnl_lock();
7962 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
7963 rtnl_unlock();
7964 }
7965
7966 #endif
7967 void ixgbe_do_reset(struct net_device *netdev)
7968 {
7969 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7970
7971 if (netif_running(netdev))
7972 ixgbe_reinit_locked(adapter);
7973 else
7974 ixgbe_reset(adapter);
7975 }
7976
7977 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7978 netdev_features_t features)
7979 {
7980 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7981
7982 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7983 if (!(features & NETIF_F_RXCSUM))
7984 features &= ~NETIF_F_LRO;
7985
7986 /* Turn off LRO if not RSC capable */
7987 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7988 features &= ~NETIF_F_LRO;
7989
7990 return features;
7991 }
7992
7993 static int ixgbe_set_features(struct net_device *netdev,
7994 netdev_features_t features)
7995 {
7996 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7997 netdev_features_t changed = netdev->features ^ features;
7998 bool need_reset = false;
7999
8000 /* Make sure RSC matches LRO, reset if change */
8001 if (!(features & NETIF_F_LRO)) {
8002 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8003 need_reset = true;
8004 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8005 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8006 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8007 if (adapter->rx_itr_setting == 1 ||
8008 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8009 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8010 need_reset = true;
8011 } else if ((changed ^ features) & NETIF_F_LRO) {
8012 e_info(probe, "rx-usecs set too low, "
8013 "disabling RSC\n");
8014 }
8015 }
8016
8017 /*
8018 * Check if Flow Director n-tuple support was enabled or disabled. If
8019 * the state changed, we need to reset.
8020 */
8021 switch (features & NETIF_F_NTUPLE) {
8022 case NETIF_F_NTUPLE:
8023 /* turn off ATR, enable perfect filters and reset */
8024 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8025 need_reset = true;
8026
8027 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8028 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8029 break;
8030 default:
8031 /* turn off perfect filters, enable ATR and reset */
8032 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8033 need_reset = true;
8034
8035 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8036
8037 /* We cannot enable ATR if SR-IOV is enabled */
8038 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8039 break;
8040
8041 /* We cannot enable ATR if we have 2 or more traffic classes */
8042 if (netdev_get_num_tc(netdev) > 1)
8043 break;
8044
8045 /* We cannot enable ATR if RSS is disabled */
8046 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8047 break;
8048
8049 /* A sample rate of 0 indicates ATR disabled */
8050 if (!adapter->atr_sample_rate)
8051 break;
8052
8053 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8054 break;
8055 }
8056
8057 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8058 ixgbe_vlan_strip_enable(adapter);
8059 else
8060 ixgbe_vlan_strip_disable(adapter);
8061
8062 if (changed & NETIF_F_RXALL)
8063 need_reset = true;
8064
8065 netdev->features = features;
8066
8067 #ifdef CONFIG_IXGBE_VXLAN
8068 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8069 if (features & NETIF_F_RXCSUM)
8070 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8071 else
8072 ixgbe_clear_vxlan_port(adapter);
8073 }
8074 #endif /* CONFIG_IXGBE_VXLAN */
8075
8076 if (need_reset)
8077 ixgbe_do_reset(netdev);
8078
8079 return 0;
8080 }
8081
8082 #ifdef CONFIG_IXGBE_VXLAN
8083 /**
8084 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8085 * @dev: The port's netdev
8086 * @sa_family: Socket Family that VXLAN is notifiying us about
8087 * @port: New UDP port number that VXLAN started listening to
8088 **/
8089 static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8090 __be16 port)
8091 {
8092 struct ixgbe_adapter *adapter = netdev_priv(dev);
8093 struct ixgbe_hw *hw = &adapter->hw;
8094 u16 new_port = ntohs(port);
8095
8096 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8097 return;
8098
8099 if (sa_family == AF_INET6)
8100 return;
8101
8102 if (adapter->vxlan_port == new_port)
8103 return;
8104
8105 if (adapter->vxlan_port) {
8106 netdev_info(dev,
8107 "Hit Max num of VXLAN ports, not adding port %d\n",
8108 new_port);
8109 return;
8110 }
8111
8112 adapter->vxlan_port = new_port;
8113 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8114 }
8115
8116 /**
8117 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8118 * @dev: The port's netdev
8119 * @sa_family: Socket Family that VXLAN is notifying us about
8120 * @port: UDP port number that VXLAN stopped listening to
8121 **/
8122 static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8123 __be16 port)
8124 {
8125 struct ixgbe_adapter *adapter = netdev_priv(dev);
8126 u16 new_port = ntohs(port);
8127
8128 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8129 return;
8130
8131 if (sa_family == AF_INET6)
8132 return;
8133
8134 if (adapter->vxlan_port != new_port) {
8135 netdev_info(dev, "Port %d was not found, not deleting\n",
8136 new_port);
8137 return;
8138 }
8139
8140 ixgbe_clear_vxlan_port(adapter);
8141 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8142 }
8143 #endif /* CONFIG_IXGBE_VXLAN */
8144
8145 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8146 struct net_device *dev,
8147 const unsigned char *addr, u16 vid,
8148 u16 flags)
8149 {
8150 /* guarantee we can provide a unique filter for the unicast address */
8151 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
8152 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
8153 return -ENOMEM;
8154 }
8155
8156 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
8157 }
8158
8159 /**
8160 * ixgbe_configure_bridge_mode - set various bridge modes
8161 * @adapter - the private structure
8162 * @mode - requested bridge mode
8163 *
8164 * Configure some settings require for various bridge modes.
8165 **/
8166 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8167 __u16 mode)
8168 {
8169 struct ixgbe_hw *hw = &adapter->hw;
8170 unsigned int p, num_pools;
8171 u32 vmdctl;
8172
8173 switch (mode) {
8174 case BRIDGE_MODE_VEPA:
8175 /* disable Tx loopback, rely on switch hairpin mode */
8176 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
8177
8178 /* must enable Rx switching replication to allow multicast
8179 * packet reception on all VFs, and to enable source address
8180 * pruning.
8181 */
8182 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8183 vmdctl |= IXGBE_VT_CTL_REPLEN;
8184 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8185
8186 /* enable Rx source address pruning. Note, this requires
8187 * replication to be enabled or else it does nothing.
8188 */
8189 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8190 for (p = 0; p < num_pools; p++) {
8191 if (hw->mac.ops.set_source_address_pruning)
8192 hw->mac.ops.set_source_address_pruning(hw,
8193 true,
8194 p);
8195 }
8196 break;
8197 case BRIDGE_MODE_VEB:
8198 /* enable Tx loopback for internal VF/PF communication */
8199 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8200 IXGBE_PFDTXGSWC_VT_LBEN);
8201
8202 /* disable Rx switching replication unless we have SR-IOV
8203 * virtual functions
8204 */
8205 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8206 if (!adapter->num_vfs)
8207 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8208 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8209
8210 /* disable Rx source address pruning, since we don't expect to
8211 * be receiving external loopback of our transmitted frames.
8212 */
8213 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8214 for (p = 0; p < num_pools; p++) {
8215 if (hw->mac.ops.set_source_address_pruning)
8216 hw->mac.ops.set_source_address_pruning(hw,
8217 false,
8218 p);
8219 }
8220 break;
8221 default:
8222 return -EINVAL;
8223 }
8224
8225 adapter->bridge_mode = mode;
8226
8227 e_info(drv, "enabling bridge mode: %s\n",
8228 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8229
8230 return 0;
8231 }
8232
8233 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
8234 struct nlmsghdr *nlh, u16 flags)
8235 {
8236 struct ixgbe_adapter *adapter = netdev_priv(dev);
8237 struct nlattr *attr, *br_spec;
8238 int rem;
8239
8240 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8241 return -EOPNOTSUPP;
8242
8243 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8244 if (!br_spec)
8245 return -EINVAL;
8246
8247 nla_for_each_nested(attr, br_spec, rem) {
8248 int status;
8249 __u16 mode;
8250
8251 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8252 continue;
8253
8254 if (nla_len(attr) < sizeof(mode))
8255 return -EINVAL;
8256
8257 mode = nla_get_u16(attr);
8258 status = ixgbe_configure_bridge_mode(adapter, mode);
8259 if (status)
8260 return status;
8261
8262 break;
8263 }
8264
8265 return 0;
8266 }
8267
8268 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8269 struct net_device *dev,
8270 u32 filter_mask, int nlflags)
8271 {
8272 struct ixgbe_adapter *adapter = netdev_priv(dev);
8273
8274 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8275 return 0;
8276
8277 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
8278 adapter->bridge_mode, 0, 0, nlflags,
8279 filter_mask, NULL);
8280 }
8281
8282 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8283 {
8284 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8285 struct ixgbe_adapter *adapter = netdev_priv(pdev);
8286 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
8287 unsigned int limit;
8288 int pool, err;
8289
8290 /* Hardware has a limited number of available pools. Each VF, and the
8291 * PF require a pool. Check to ensure we don't attempt to use more
8292 * then the available number of pools.
8293 */
8294 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8295 return ERR_PTR(-EINVAL);
8296
8297 #ifdef CONFIG_RPS
8298 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8299 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8300 vdev->name);
8301 return ERR_PTR(-EINVAL);
8302 }
8303 #endif
8304 /* Check for hardware restriction on number of rx/tx queues */
8305 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
8306 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8307 netdev_info(pdev,
8308 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8309 pdev->name);
8310 return ERR_PTR(-EINVAL);
8311 }
8312
8313 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8314 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8315 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8316 return ERR_PTR(-EBUSY);
8317
8318 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
8319 if (!fwd_adapter)
8320 return ERR_PTR(-ENOMEM);
8321
8322 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8323 adapter->num_rx_pools++;
8324 set_bit(pool, &adapter->fwd_bitmask);
8325 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8326
8327 /* Enable VMDq flag so device will be set in VM mode */
8328 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
8329 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8330 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
8331
8332 /* Force reinit of ring allocation with VMDQ enabled */
8333 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8334 if (err)
8335 goto fwd_add_err;
8336 fwd_adapter->pool = pool;
8337 fwd_adapter->real_adapter = adapter;
8338 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8339 if (err)
8340 goto fwd_add_err;
8341 netif_tx_start_all_queues(vdev);
8342 return fwd_adapter;
8343 fwd_add_err:
8344 /* unwind counter and free adapter struct */
8345 netdev_info(pdev,
8346 "%s: dfwd hardware acceleration failed\n", vdev->name);
8347 clear_bit(pool, &adapter->fwd_bitmask);
8348 adapter->num_rx_pools--;
8349 kfree(fwd_adapter);
8350 return ERR_PTR(err);
8351 }
8352
8353 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8354 {
8355 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8356 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
8357 unsigned int limit;
8358
8359 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8360 adapter->num_rx_pools--;
8361
8362 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8363 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
8364 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8365 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8366 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8367 fwd_adapter->pool, adapter->num_rx_pools,
8368 fwd_adapter->rx_base_queue,
8369 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8370 adapter->fwd_bitmask);
8371 kfree(fwd_adapter);
8372 }
8373
8374 #define IXGBE_MAX_TUNNEL_HDR_LEN 80
8375 static netdev_features_t
8376 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8377 netdev_features_t features)
8378 {
8379 if (!skb->encapsulation)
8380 return features;
8381
8382 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8383 IXGBE_MAX_TUNNEL_HDR_LEN))
8384 return features & ~NETIF_F_ALL_CSUM;
8385
8386 return features;
8387 }
8388
8389 static const struct net_device_ops ixgbe_netdev_ops = {
8390 .ndo_open = ixgbe_open,
8391 .ndo_stop = ixgbe_close,
8392 .ndo_start_xmit = ixgbe_xmit_frame,
8393 .ndo_select_queue = ixgbe_select_queue,
8394 .ndo_set_rx_mode = ixgbe_set_rx_mode,
8395 .ndo_validate_addr = eth_validate_addr,
8396 .ndo_set_mac_address = ixgbe_set_mac,
8397 .ndo_change_mtu = ixgbe_change_mtu,
8398 .ndo_tx_timeout = ixgbe_tx_timeout,
8399 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8400 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
8401 .ndo_do_ioctl = ixgbe_ioctl,
8402 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8403 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
8404 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
8405 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
8406 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
8407 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
8408 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
8409 .ndo_get_stats64 = ixgbe_get_stats64,
8410 #ifdef CONFIG_IXGBE_DCB
8411 .ndo_setup_tc = ixgbe_setup_tc,
8412 #endif
8413 #ifdef CONFIG_NET_POLL_CONTROLLER
8414 .ndo_poll_controller = ixgbe_netpoll,
8415 #endif
8416 #ifdef CONFIG_NET_RX_BUSY_POLL
8417 .ndo_busy_poll = ixgbe_low_latency_recv,
8418 #endif
8419 #ifdef IXGBE_FCOE
8420 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
8421 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
8422 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8423 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8424 .ndo_fcoe_disable = ixgbe_fcoe_disable,
8425 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
8426 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
8427 #endif /* IXGBE_FCOE */
8428 .ndo_set_features = ixgbe_set_features,
8429 .ndo_fix_features = ixgbe_fix_features,
8430 .ndo_fdb_add = ixgbe_ndo_fdb_add,
8431 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8432 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
8433 .ndo_dfwd_add_station = ixgbe_fwd_add,
8434 .ndo_dfwd_del_station = ixgbe_fwd_del,
8435 #ifdef CONFIG_IXGBE_VXLAN
8436 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8437 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
8438 #endif /* CONFIG_IXGBE_VXLAN */
8439 .ndo_features_check = ixgbe_features_check,
8440 };
8441
8442 /**
8443 * ixgbe_enumerate_functions - Get the number of ports this device has
8444 * @adapter: adapter structure
8445 *
8446 * This function enumerates the phsyical functions co-located on a single slot,
8447 * in order to determine how many ports a device has. This is most useful in
8448 * determining the required GT/s of PCIe bandwidth necessary for optimal
8449 * performance.
8450 **/
8451 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8452 {
8453 struct pci_dev *entry, *pdev = adapter->pdev;
8454 int physfns = 0;
8455
8456 /* Some cards can not use the generic count PCIe functions method,
8457 * because they are behind a parent switch, so we hardcode these with
8458 * the correct number of functions.
8459 */
8460 if (ixgbe_pcie_from_parent(&adapter->hw))
8461 physfns = 4;
8462
8463 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8464 /* don't count virtual functions */
8465 if (entry->is_virtfn)
8466 continue;
8467
8468 /* When the devices on the bus don't all match our device ID,
8469 * we can't reliably determine the correct number of
8470 * functions. This can occur if a function has been direct
8471 * attached to a virtual machine using VT-d, for example. In
8472 * this case, simply return -1 to indicate this.
8473 */
8474 if ((entry->vendor != pdev->vendor) ||
8475 (entry->device != pdev->device))
8476 return -1;
8477
8478 physfns++;
8479 }
8480
8481 return physfns;
8482 }
8483
8484 /**
8485 * ixgbe_wol_supported - Check whether device supports WoL
8486 * @hw: hw specific details
8487 * @device_id: the device ID
8488 * @subdev_id: the subsystem device ID
8489 *
8490 * This function is used by probe and ethtool to determine
8491 * which devices have WoL support
8492 *
8493 **/
8494 int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8495 u16 subdevice_id)
8496 {
8497 struct ixgbe_hw *hw = &adapter->hw;
8498 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8499 int is_wol_supported = 0;
8500
8501 switch (device_id) {
8502 case IXGBE_DEV_ID_82599_SFP:
8503 /* Only these subdevices could supports WOL */
8504 switch (subdevice_id) {
8505 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8506 case IXGBE_SUBDEV_ID_82599_560FLR:
8507 /* only support first port */
8508 if (hw->bus.func != 0)
8509 break;
8510 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8511 case IXGBE_SUBDEV_ID_82599_SFP:
8512 case IXGBE_SUBDEV_ID_82599_RNDC:
8513 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
8514 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8515 is_wol_supported = 1;
8516 break;
8517 }
8518 break;
8519 case IXGBE_DEV_ID_82599EN_SFP:
8520 /* Only this subdevice supports WOL */
8521 switch (subdevice_id) {
8522 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8523 is_wol_supported = 1;
8524 break;
8525 }
8526 break;
8527 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8528 /* All except this subdevice support WOL */
8529 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8530 is_wol_supported = 1;
8531 break;
8532 case IXGBE_DEV_ID_82599_KX4:
8533 is_wol_supported = 1;
8534 break;
8535 case IXGBE_DEV_ID_X540T:
8536 case IXGBE_DEV_ID_X540T1:
8537 case IXGBE_DEV_ID_X550T:
8538 case IXGBE_DEV_ID_X550EM_X_KX4:
8539 case IXGBE_DEV_ID_X550EM_X_KR:
8540 case IXGBE_DEV_ID_X550EM_X_10G_T:
8541 /* check eeprom to see if enabled wol */
8542 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8543 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8544 (hw->bus.func == 0))) {
8545 is_wol_supported = 1;
8546 }
8547 break;
8548 }
8549
8550 return is_wol_supported;
8551 }
8552
8553 /**
8554 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8555 * @adapter: Pointer to adapter struct
8556 */
8557 static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8558 {
8559 #ifdef CONFIG_OF
8560 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8561 struct ixgbe_hw *hw = &adapter->hw;
8562 const unsigned char *addr;
8563
8564 addr = of_get_mac_address(dp);
8565 if (addr) {
8566 ether_addr_copy(hw->mac.perm_addr, addr);
8567 return;
8568 }
8569 #endif /* CONFIG_OF */
8570
8571 #ifdef CONFIG_SPARC
8572 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8573 #endif /* CONFIG_SPARC */
8574 }
8575
8576 /**
8577 * ixgbe_probe - Device Initialization Routine
8578 * @pdev: PCI device information struct
8579 * @ent: entry in ixgbe_pci_tbl
8580 *
8581 * Returns 0 on success, negative on failure
8582 *
8583 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8584 * The OS initialization, configuring of the adapter private structure,
8585 * and a hardware reset occur.
8586 **/
8587 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
8588 {
8589 struct net_device *netdev;
8590 struct ixgbe_adapter *adapter = NULL;
8591 struct ixgbe_hw *hw;
8592 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
8593 int i, err, pci_using_dac, expected_gts;
8594 unsigned int indices = MAX_TX_QUEUES;
8595 u8 part_str[IXGBE_PBANUM_LENGTH];
8596 bool disable_dev = false;
8597 #ifdef IXGBE_FCOE
8598 u16 device_caps;
8599 #endif
8600 u32 eec;
8601
8602 /* Catch broken hardware that put the wrong VF device ID in
8603 * the PCIe SR-IOV capability.
8604 */
8605 if (pdev->is_virtfn) {
8606 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8607 pci_name(pdev), pdev->vendor, pdev->device);
8608 return -EINVAL;
8609 }
8610
8611 err = pci_enable_device_mem(pdev);
8612 if (err)
8613 return err;
8614
8615 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
8616 pci_using_dac = 1;
8617 } else {
8618 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
8619 if (err) {
8620 dev_err(&pdev->dev,
8621 "No usable DMA configuration, aborting\n");
8622 goto err_dma;
8623 }
8624 pci_using_dac = 0;
8625 }
8626
8627 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
8628 IORESOURCE_MEM), ixgbe_driver_name);
8629 if (err) {
8630 dev_err(&pdev->dev,
8631 "pci_request_selected_regions failed 0x%x\n", err);
8632 goto err_pci_reg;
8633 }
8634
8635 pci_enable_pcie_error_reporting(pdev);
8636
8637 pci_set_master(pdev);
8638 pci_save_state(pdev);
8639
8640 if (ii->mac == ixgbe_mac_82598EB) {
8641 #ifdef CONFIG_IXGBE_DCB
8642 /* 8 TC w/ 4 queues per TC */
8643 indices = 4 * MAX_TRAFFIC_CLASS;
8644 #else
8645 indices = IXGBE_MAX_RSS_INDICES;
8646 #endif
8647 }
8648
8649 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
8650 if (!netdev) {
8651 err = -ENOMEM;
8652 goto err_alloc_etherdev;
8653 }
8654
8655 SET_NETDEV_DEV(netdev, &pdev->dev);
8656
8657 adapter = netdev_priv(netdev);
8658
8659 adapter->netdev = netdev;
8660 adapter->pdev = pdev;
8661 hw = &adapter->hw;
8662 hw->back = adapter;
8663 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
8664
8665 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
8666 pci_resource_len(pdev, 0));
8667 adapter->io_addr = hw->hw_addr;
8668 if (!hw->hw_addr) {
8669 err = -EIO;
8670 goto err_ioremap;
8671 }
8672
8673 netdev->netdev_ops = &ixgbe_netdev_ops;
8674 ixgbe_set_ethtool_ops(netdev);
8675 netdev->watchdog_timeo = 5 * HZ;
8676 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
8677
8678 /* Setup hw api */
8679 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
8680 hw->mac.type = ii->mac;
8681 hw->mvals = ii->mvals;
8682
8683 /* EEPROM */
8684 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8685 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
8686 if (ixgbe_removed(hw->hw_addr)) {
8687 err = -EIO;
8688 goto err_ioremap;
8689 }
8690 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8691 if (!(eec & (1 << 8)))
8692 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8693
8694 /* PHY */
8695 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
8696 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
8697 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8698 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8699 hw->phy.mdio.mmds = 0;
8700 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8701 hw->phy.mdio.dev = netdev;
8702 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8703 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
8704
8705 ii->get_invariants(hw);
8706
8707 /* setup the private structure */
8708 err = ixgbe_sw_init(adapter);
8709 if (err)
8710 goto err_sw_init;
8711
8712 /* Make it possible the adapter to be woken up via WOL */
8713 switch (adapter->hw.mac.type) {
8714 case ixgbe_mac_82599EB:
8715 case ixgbe_mac_X540:
8716 case ixgbe_mac_X550:
8717 case ixgbe_mac_X550EM_x:
8718 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
8719 break;
8720 default:
8721 break;
8722 }
8723
8724 /*
8725 * If there is a fan on this device and it has failed log the
8726 * failure.
8727 */
8728 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8729 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8730 if (esdp & IXGBE_ESDP_SDP1)
8731 e_crit(probe, "Fan has stopped, replace the adapter\n");
8732 }
8733
8734 if (allow_unsupported_sfp)
8735 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8736
8737 /* reset_hw fills in the perm_addr as well */
8738 hw->phy.reset_if_overtemp = true;
8739 err = hw->mac.ops.reset_hw(hw);
8740 hw->phy.reset_if_overtemp = false;
8741 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8742 err = 0;
8743 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
8744 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8745 e_dev_err("Reload the driver after installing a supported module.\n");
8746 goto err_sw_init;
8747 } else if (err) {
8748 e_dev_err("HW Init failed: %d\n", err);
8749 goto err_sw_init;
8750 }
8751
8752 #ifdef CONFIG_PCI_IOV
8753 /* SR-IOV not supported on the 82598 */
8754 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8755 goto skip_sriov;
8756 /* Mailbox */
8757 ixgbe_init_mbx_params_pf(hw);
8758 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
8759 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
8760 ixgbe_enable_sriov(adapter);
8761 skip_sriov:
8762
8763 #endif
8764 netdev->features = NETIF_F_SG |
8765 NETIF_F_IP_CSUM |
8766 NETIF_F_IPV6_CSUM |
8767 NETIF_F_HW_VLAN_CTAG_TX |
8768 NETIF_F_HW_VLAN_CTAG_RX |
8769 NETIF_F_TSO |
8770 NETIF_F_TSO6 |
8771 NETIF_F_RXHASH |
8772 NETIF_F_RXCSUM;
8773
8774 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
8775
8776 switch (adapter->hw.mac.type) {
8777 case ixgbe_mac_82599EB:
8778 case ixgbe_mac_X540:
8779 case ixgbe_mac_X550:
8780 case ixgbe_mac_X550EM_x:
8781 netdev->features |= NETIF_F_SCTP_CSUM;
8782 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8783 NETIF_F_NTUPLE;
8784 break;
8785 default:
8786 break;
8787 }
8788
8789 netdev->hw_features |= NETIF_F_RXALL;
8790 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
8791
8792 netdev->vlan_features |= NETIF_F_TSO;
8793 netdev->vlan_features |= NETIF_F_TSO6;
8794 netdev->vlan_features |= NETIF_F_IP_CSUM;
8795 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
8796 netdev->vlan_features |= NETIF_F_SG;
8797
8798 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8799 NETIF_F_IPV6_CSUM;
8800
8801 netdev->priv_flags |= IFF_UNICAST_FLT;
8802 netdev->priv_flags |= IFF_SUPP_NOFCS;
8803
8804 #ifdef CONFIG_IXGBE_VXLAN
8805 switch (adapter->hw.mac.type) {
8806 case ixgbe_mac_X550:
8807 case ixgbe_mac_X550EM_x:
8808 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8809 NETIF_F_IP_CSUM |
8810 NETIF_F_IPV6_CSUM;
8811 break;
8812 default:
8813 break;
8814 }
8815 #endif /* CONFIG_IXGBE_VXLAN */
8816
8817 #ifdef CONFIG_IXGBE_DCB
8818 netdev->dcbnl_ops = &dcbnl_ops;
8819 #endif
8820
8821 #ifdef IXGBE_FCOE
8822 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
8823 unsigned int fcoe_l;
8824
8825 if (hw->mac.ops.get_device_caps) {
8826 hw->mac.ops.get_device_caps(hw, &device_caps);
8827 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8828 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
8829 }
8830
8831
8832 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8833 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
8834
8835 netdev->features |= NETIF_F_FSO |
8836 NETIF_F_FCOE_CRC;
8837
8838 netdev->vlan_features |= NETIF_F_FSO |
8839 NETIF_F_FCOE_CRC |
8840 NETIF_F_FCOE_MTU;
8841 }
8842 #endif /* IXGBE_FCOE */
8843 if (pci_using_dac) {
8844 netdev->features |= NETIF_F_HIGHDMA;
8845 netdev->vlan_features |= NETIF_F_HIGHDMA;
8846 }
8847
8848 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8849 netdev->hw_features |= NETIF_F_LRO;
8850 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
8851 netdev->features |= NETIF_F_LRO;
8852
8853 /* make sure the EEPROM is good */
8854 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
8855 e_dev_err("The EEPROM Checksum Is Not Valid\n");
8856 err = -EIO;
8857 goto err_sw_init;
8858 }
8859
8860 ixgbe_get_platform_mac_addr(adapter);
8861
8862 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
8863
8864 if (!is_valid_ether_addr(netdev->dev_addr)) {
8865 e_dev_err("invalid MAC address\n");
8866 err = -EIO;
8867 goto err_sw_init;
8868 }
8869
8870 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8871
8872 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
8873 (unsigned long) adapter);
8874
8875 if (ixgbe_removed(hw->hw_addr)) {
8876 err = -EIO;
8877 goto err_sw_init;
8878 }
8879 INIT_WORK(&adapter->service_task, ixgbe_service_task);
8880 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
8881 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
8882
8883 err = ixgbe_init_interrupt_scheme(adapter);
8884 if (err)
8885 goto err_sw_init;
8886
8887 /* WOL not supported for all devices */
8888 adapter->wol = 0;
8889 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
8890 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
8891 pdev->subsystem_device);
8892 if (hw->wol_enabled)
8893 adapter->wol = IXGBE_WUFC_MAG;
8894
8895 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8896
8897 /* save off EEPROM version number */
8898 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8899 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8900
8901 /* pick up the PCI bus settings for reporting later */
8902 if (ixgbe_pcie_from_parent(hw))
8903 ixgbe_get_parent_bus_info(adapter);
8904 else
8905 hw->mac.ops.get_bus_info(hw);
8906
8907 /* calculate the expected PCIe bandwidth required for optimal
8908 * performance. Note that some older parts will never have enough
8909 * bandwidth due to being older generation PCIe parts. We clamp these
8910 * parts to ensure no warning is displayed if it can't be fixed.
8911 */
8912 switch (hw->mac.type) {
8913 case ixgbe_mac_82598EB:
8914 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8915 break;
8916 default:
8917 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8918 break;
8919 }
8920
8921 /* don't check link if we failed to enumerate functions */
8922 if (expected_gts > 0)
8923 ixgbe_check_minimum_link(adapter, expected_gts);
8924
8925 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
8926 if (err)
8927 strlcpy(part_str, "Unknown", sizeof(part_str));
8928 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8929 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8930 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8931 part_str);
8932 else
8933 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8934 hw->mac.type, hw->phy.type, part_str);
8935
8936 e_dev_info("%pM\n", netdev->dev_addr);
8937
8938 /* reset the hardware with the new settings */
8939 err = hw->mac.ops.start_hw(hw);
8940 if (err == IXGBE_ERR_EEPROM_VERSION) {
8941 /* We are running on a pre-production device, log a warning */
8942 e_dev_warn("This device is a pre-production adapter/LOM. "
8943 "Please be aware there may be issues associated "
8944 "with your hardware. If you are experiencing "
8945 "problems please contact your Intel or hardware "
8946 "representative who provided you with this "
8947 "hardware.\n");
8948 }
8949 strcpy(netdev->name, "eth%d");
8950 err = register_netdev(netdev);
8951 if (err)
8952 goto err_register;
8953
8954 pci_set_drvdata(pdev, adapter);
8955
8956 /* power down the optics for 82599 SFP+ fiber */
8957 if (hw->mac.ops.disable_tx_laser)
8958 hw->mac.ops.disable_tx_laser(hw);
8959
8960 /* carrier off reporting is important to ethtool even BEFORE open */
8961 netif_carrier_off(netdev);
8962
8963 #ifdef CONFIG_IXGBE_DCA
8964 if (dca_add_requester(&pdev->dev) == 0) {
8965 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
8966 ixgbe_setup_dca(adapter);
8967 }
8968 #endif
8969 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8970 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
8971 for (i = 0; i < adapter->num_vfs; i++)
8972 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8973 }
8974
8975 /* firmware requires driver version to be 0xFFFFFFFF
8976 * since os does not support feature
8977 */
8978 if (hw->mac.ops.set_fw_drv_ver)
8979 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8980 0xFF);
8981
8982 /* add san mac addr to netdev */
8983 ixgbe_add_sanmac_netdev(netdev);
8984
8985 e_dev_info("%s\n", ixgbe_default_device_descr);
8986
8987 #ifdef CONFIG_IXGBE_HWMON
8988 if (ixgbe_sysfs_init(adapter))
8989 e_err(probe, "failed to allocate sysfs resources\n");
8990 #endif /* CONFIG_IXGBE_HWMON */
8991
8992 ixgbe_dbg_adapter_init(adapter);
8993
8994 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8995 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
8996 hw->mac.ops.setup_link(hw,
8997 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8998 true);
8999
9000 return 0;
9001
9002 err_register:
9003 ixgbe_release_hw_control(adapter);
9004 ixgbe_clear_interrupt_scheme(adapter);
9005 err_sw_init:
9006 ixgbe_disable_sriov(adapter);
9007 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9008 iounmap(adapter->io_addr);
9009 kfree(adapter->mac_table);
9010 err_ioremap:
9011 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9012 free_netdev(netdev);
9013 err_alloc_etherdev:
9014 pci_release_selected_regions(pdev,
9015 pci_select_bars(pdev, IORESOURCE_MEM));
9016 err_pci_reg:
9017 err_dma:
9018 if (!adapter || disable_dev)
9019 pci_disable_device(pdev);
9020 return err;
9021 }
9022
9023 /**
9024 * ixgbe_remove - Device Removal Routine
9025 * @pdev: PCI device information struct
9026 *
9027 * ixgbe_remove is called by the PCI subsystem to alert the driver
9028 * that it should release a PCI device. The could be caused by a
9029 * Hot-Plug event, or because the driver is going to be removed from
9030 * memory.
9031 **/
9032 static void ixgbe_remove(struct pci_dev *pdev)
9033 {
9034 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9035 struct net_device *netdev;
9036 bool disable_dev;
9037
9038 /* if !adapter then we already cleaned up in probe */
9039 if (!adapter)
9040 return;
9041
9042 netdev = adapter->netdev;
9043 ixgbe_dbg_adapter_exit(adapter);
9044
9045 set_bit(__IXGBE_REMOVING, &adapter->state);
9046 cancel_work_sync(&adapter->service_task);
9047
9048
9049 #ifdef CONFIG_IXGBE_DCA
9050 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9051 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9052 dca_remove_requester(&pdev->dev);
9053 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9054 IXGBE_DCA_CTRL_DCA_DISABLE);
9055 }
9056
9057 #endif
9058 #ifdef CONFIG_IXGBE_HWMON
9059 ixgbe_sysfs_exit(adapter);
9060 #endif /* CONFIG_IXGBE_HWMON */
9061
9062 /* remove the added san mac */
9063 ixgbe_del_sanmac_netdev(netdev);
9064
9065 #ifdef CONFIG_PCI_IOV
9066 ixgbe_disable_sriov(adapter);
9067 #endif
9068 if (netdev->reg_state == NETREG_REGISTERED)
9069 unregister_netdev(netdev);
9070
9071 ixgbe_clear_interrupt_scheme(adapter);
9072
9073 ixgbe_release_hw_control(adapter);
9074
9075 #ifdef CONFIG_DCB
9076 kfree(adapter->ixgbe_ieee_pfc);
9077 kfree(adapter->ixgbe_ieee_ets);
9078
9079 #endif
9080 iounmap(adapter->io_addr);
9081 pci_release_selected_regions(pdev, pci_select_bars(pdev,
9082 IORESOURCE_MEM));
9083
9084 e_dev_info("complete\n");
9085
9086 kfree(adapter->mac_table);
9087 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9088 free_netdev(netdev);
9089
9090 pci_disable_pcie_error_reporting(pdev);
9091
9092 if (disable_dev)
9093 pci_disable_device(pdev);
9094 }
9095
9096 /**
9097 * ixgbe_io_error_detected - called when PCI error is detected
9098 * @pdev: Pointer to PCI device
9099 * @state: The current pci connection state
9100 *
9101 * This function is called after a PCI bus error affecting
9102 * this device has been detected.
9103 */
9104 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
9105 pci_channel_state_t state)
9106 {
9107 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9108 struct net_device *netdev = adapter->netdev;
9109
9110 #ifdef CONFIG_PCI_IOV
9111 struct ixgbe_hw *hw = &adapter->hw;
9112 struct pci_dev *bdev, *vfdev;
9113 u32 dw0, dw1, dw2, dw3;
9114 int vf, pos;
9115 u16 req_id, pf_func;
9116
9117 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9118 adapter->num_vfs == 0)
9119 goto skip_bad_vf_detection;
9120
9121 bdev = pdev->bus->self;
9122 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
9123 bdev = bdev->bus->self;
9124
9125 if (!bdev)
9126 goto skip_bad_vf_detection;
9127
9128 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9129 if (!pos)
9130 goto skip_bad_vf_detection;
9131
9132 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9133 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9134 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9135 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9136 if (ixgbe_removed(hw->hw_addr))
9137 goto skip_bad_vf_detection;
9138
9139 req_id = dw1 >> 16;
9140 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9141 if (!(req_id & 0x0080))
9142 goto skip_bad_vf_detection;
9143
9144 pf_func = req_id & 0x01;
9145 if ((pf_func & 1) == (pdev->devfn & 1)) {
9146 unsigned int device_id;
9147
9148 vf = (req_id & 0x7F) >> 1;
9149 e_dev_err("VF %d has caused a PCIe error\n", vf);
9150 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9151 "%8.8x\tdw3: %8.8x\n",
9152 dw0, dw1, dw2, dw3);
9153 switch (adapter->hw.mac.type) {
9154 case ixgbe_mac_82599EB:
9155 device_id = IXGBE_82599_VF_DEVICE_ID;
9156 break;
9157 case ixgbe_mac_X540:
9158 device_id = IXGBE_X540_VF_DEVICE_ID;
9159 break;
9160 case ixgbe_mac_X550:
9161 device_id = IXGBE_DEV_ID_X550_VF;
9162 break;
9163 case ixgbe_mac_X550EM_x:
9164 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9165 break;
9166 default:
9167 device_id = 0;
9168 break;
9169 }
9170
9171 /* Find the pci device of the offending VF */
9172 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
9173 while (vfdev) {
9174 if (vfdev->devfn == (req_id & 0xFF))
9175 break;
9176 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
9177 device_id, vfdev);
9178 }
9179 /*
9180 * There's a slim chance the VF could have been hot plugged,
9181 * so if it is no longer present we don't need to issue the
9182 * VFLR. Just clean up the AER in that case.
9183 */
9184 if (vfdev) {
9185 ixgbe_issue_vf_flr(adapter, vfdev);
9186 /* Free device reference count */
9187 pci_dev_put(vfdev);
9188 }
9189
9190 pci_cleanup_aer_uncorrect_error_status(pdev);
9191 }
9192
9193 /*
9194 * Even though the error may have occurred on the other port
9195 * we still need to increment the vf error reference count for
9196 * both ports because the I/O resume function will be called
9197 * for both of them.
9198 */
9199 adapter->vferr_refcount++;
9200
9201 return PCI_ERS_RESULT_RECOVERED;
9202
9203 skip_bad_vf_detection:
9204 #endif /* CONFIG_PCI_IOV */
9205 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9206 return PCI_ERS_RESULT_DISCONNECT;
9207
9208 rtnl_lock();
9209 netif_device_detach(netdev);
9210
9211 if (state == pci_channel_io_perm_failure) {
9212 rtnl_unlock();
9213 return PCI_ERS_RESULT_DISCONNECT;
9214 }
9215
9216 if (netif_running(netdev))
9217 ixgbe_down(adapter);
9218
9219 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9220 pci_disable_device(pdev);
9221 rtnl_unlock();
9222
9223 /* Request a slot reset. */
9224 return PCI_ERS_RESULT_NEED_RESET;
9225 }
9226
9227 /**
9228 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9229 * @pdev: Pointer to PCI device
9230 *
9231 * Restart the card from scratch, as if from a cold-boot.
9232 */
9233 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9234 {
9235 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9236 pci_ers_result_t result;
9237 int err;
9238
9239 if (pci_enable_device_mem(pdev)) {
9240 e_err(probe, "Cannot re-enable PCI device after reset.\n");
9241 result = PCI_ERS_RESULT_DISCONNECT;
9242 } else {
9243 smp_mb__before_atomic();
9244 clear_bit(__IXGBE_DISABLED, &adapter->state);
9245 adapter->hw.hw_addr = adapter->io_addr;
9246 pci_set_master(pdev);
9247 pci_restore_state(pdev);
9248 pci_save_state(pdev);
9249
9250 pci_wake_from_d3(pdev, false);
9251
9252 ixgbe_reset(adapter);
9253 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
9254 result = PCI_ERS_RESULT_RECOVERED;
9255 }
9256
9257 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9258 if (err) {
9259 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9260 "failed 0x%0x\n", err);
9261 /* non-fatal, continue */
9262 }
9263
9264 return result;
9265 }
9266
9267 /**
9268 * ixgbe_io_resume - called when traffic can start flowing again.
9269 * @pdev: Pointer to PCI device
9270 *
9271 * This callback is called when the error recovery driver tells us that
9272 * its OK to resume normal operation.
9273 */
9274 static void ixgbe_io_resume(struct pci_dev *pdev)
9275 {
9276 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9277 struct net_device *netdev = adapter->netdev;
9278
9279 #ifdef CONFIG_PCI_IOV
9280 if (adapter->vferr_refcount) {
9281 e_info(drv, "Resuming after VF err\n");
9282 adapter->vferr_refcount--;
9283 return;
9284 }
9285
9286 #endif
9287 if (netif_running(netdev))
9288 ixgbe_up(adapter);
9289
9290 netif_device_attach(netdev);
9291 }
9292
9293 static const struct pci_error_handlers ixgbe_err_handler = {
9294 .error_detected = ixgbe_io_error_detected,
9295 .slot_reset = ixgbe_io_slot_reset,
9296 .resume = ixgbe_io_resume,
9297 };
9298
9299 static struct pci_driver ixgbe_driver = {
9300 .name = ixgbe_driver_name,
9301 .id_table = ixgbe_pci_tbl,
9302 .probe = ixgbe_probe,
9303 .remove = ixgbe_remove,
9304 #ifdef CONFIG_PM
9305 .suspend = ixgbe_suspend,
9306 .resume = ixgbe_resume,
9307 #endif
9308 .shutdown = ixgbe_shutdown,
9309 .sriov_configure = ixgbe_pci_sriov_configure,
9310 .err_handler = &ixgbe_err_handler
9311 };
9312
9313 /**
9314 * ixgbe_init_module - Driver Registration Routine
9315 *
9316 * ixgbe_init_module is the first routine called when the driver is
9317 * loaded. All it does is register with the PCI subsystem.
9318 **/
9319 static int __init ixgbe_init_module(void)
9320 {
9321 int ret;
9322 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
9323 pr_info("%s\n", ixgbe_copyright);
9324
9325 ixgbe_dbg_init();
9326
9327 ret = pci_register_driver(&ixgbe_driver);
9328 if (ret) {
9329 ixgbe_dbg_exit();
9330 return ret;
9331 }
9332
9333 #ifdef CONFIG_IXGBE_DCA
9334 dca_register_notify(&dca_notifier);
9335 #endif
9336
9337 return 0;
9338 }
9339
9340 module_init(ixgbe_init_module);
9341
9342 /**
9343 * ixgbe_exit_module - Driver Exit Cleanup Routine
9344 *
9345 * ixgbe_exit_module is called just before the driver is removed
9346 * from memory.
9347 **/
9348 static void __exit ixgbe_exit_module(void)
9349 {
9350 #ifdef CONFIG_IXGBE_DCA
9351 dca_unregister_notify(&dca_notifier);
9352 #endif
9353 pci_unregister_driver(&ixgbe_driver);
9354
9355 ixgbe_dbg_exit();
9356 }
9357
9358 #ifdef CONFIG_IXGBE_DCA
9359 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
9360 void *p)
9361 {
9362 int ret_val;
9363
9364 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
9365 __ixgbe_notify_dca);
9366
9367 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9368 }
9369
9370 #endif /* CONFIG_IXGBE_DCA */
9371
9372 module_exit(ixgbe_exit_module);
9373
9374 /* ixgbe_main.c */
Linux kernel - Deliverables
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