drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28 #include "ixgbe.h"
  29 #include <linux/export.h>
  30 #include <linux/ptp_classify.h>
  31
  32 /*
  33  * The 82599 and the X540 do not have true 64bit nanosecond scale
  34  * counter registers. Instead, SYSTIME is defined by a fixed point
  35  * system which allows the user to define the scale counter increment
  36  * value at every level change of the oscillator driving the SYSTIME
  37  * value. For both devices the TIMINCA:IV field defines this
  38  * increment. On the X540 device, 31 bits are provided. However on the
  39  * 82599 only provides 24 bits. The time unit is determined by the
  40  * clock frequency of the oscillator in combination with the TIMINCA
  41  * register. When these devices link at 10Gb the oscillator has a
  42  * period of 6.4ns. In order to convert the scale counter into
  43  * nanoseconds the cyclecounter and timecounter structures are
  44  * used. The SYSTIME registers need to be converted to ns values by use
  45  * of only a right shift (division by power of 2). The following math
  46  * determines the largest incvalue that will fit into the available
  47  * bits in the TIMINCA register.
  48  *
  49  * PeriodWidth: Number of bits to store the clock period
  50  * MaxWidth: The maximum width value of the TIMINCA register
  51  * Period: The clock period for the oscillator
  52  * round(): discard the fractional portion of the calculation
  53  *
  54  * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
  55  *
  56  * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
  57  * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
  58  *
  59  * The period also changes based on the link speed:
  60  * At 10Gb link or no link, the period remains the same.
  61  * At 1Gb link, the period is multiplied by 10. (64ns)
  62  * At 100Mb link, the period is multiplied by 100. (640ns)
  63  *
  64  * The calculated value allows us to right shift the SYSTIME register
  65  * value in order to quickly convert it into a nanosecond clock,
  66  * while allowing for the maximum possible adjustment value.
  67  *
  68  * These diagrams are only for the 10Gb link period
  69  *
  70  *           SYSTIMEH            SYSTIMEL
  71  *       +--------------+  +--------------+
  72  * X540  |      32      |  | 1 | 3 |  28  |
  73  *       *--------------+  +--------------+
  74  *        \________ 36 bits ______/  fract
  75  *
  76  *       +--------------+  +--------------+
  77  * 82599 |      32      |  | 8 | 3 |  21  |
  78  *       *--------------+  +--------------+
  79  *        \________ 43 bits ______/  fract
  80  *
  81  * The 36 bit X540 SYSTIME overflows every
  82  *   2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
  83  *
  84  * The 43 bit 82599 SYSTIME overflows every
  85  *   2^43 * 10^-9 / 3600 = 2.4 hours
  86  */
  87 #define IXGBE_INCVAL_10GB 0x66666666
  88 #define IXGBE_INCVAL_1GB  0x40000000
  89 #define IXGBE_INCVAL_100  0x50000000
  90
  91 #define IXGBE_INCVAL_SHIFT_10GB  28
  92 #define IXGBE_INCVAL_SHIFT_1GB   24
  93 #define IXGBE_INCVAL_SHIFT_100   21
  94
  95 #define IXGBE_INCVAL_SHIFT_82599 7
  96 #define IXGBE_INCPER_SHIFT_82599 24
  97 #define IXGBE_MAX_TIMEADJ_VALUE  0x7FFFFFFFFFFFFFFFULL
  98
  99 #define IXGBE_OVERFLOW_PERIOD    (HZ * 30)
 100 #define IXGBE_PTP_TX_TIMEOUT     (HZ * 15)
 101
 102 #ifndef NSECS_PER_SEC
 103 #define NSECS_PER_SEC 1000000000ULL
 104 #endif
 105
 106 /**
 107  * ixgbe_ptp_setup_sdp
 108  * @hw: the hardware private structure
 109  *
 110  * this function enables or disables the clock out feature on SDP0 for
 111  * the X540 device. It will create a 1second periodic output that can
 112  * be used as the PPS (via an interrupt).
 113  *
 114  * It calculates when the systime will be on an exact second, and then
 115  * aligns the start of the PPS signal to that value. The shift is
 116  * necessary because it can change based on the link speed.
 117  */
 118 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
 119 {
 120         struct ixgbe_hw *hw = &adapter->hw;
 121         int shift = adapter->cc.shift;
 122         u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
 123         u64 ns = 0, clock_edge = 0;
 124
 125         if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
 126             (hw->mac.type == ixgbe_mac_X540)) {
 127
 128                 /* disable the pin first */
 129                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 130                 IXGBE_WRITE_FLUSH(hw);
 131
 132                 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
 133
 134                 /*
 135                  * enable the SDP0 pin as output, and connected to the
 136                  * native function for Timesync (ClockOut)
 137                  */
 138                 esdp |= (IXGBE_ESDP_SDP0_DIR |
 139                          IXGBE_ESDP_SDP0_NATIVE);
 140
 141                 /*
 142                  * enable the Clock Out feature on SDP0, and allow
 143                  * interrupts to occur when the pin changes
 144                  */
 145                 tsauxc = (IXGBE_TSAUXC_EN_CLK |
 146                           IXGBE_TSAUXC_SYNCLK |
 147                           IXGBE_TSAUXC_SDP0_INT);
 148
 149                 /* clock period (or pulse length) */
 150                 clktiml = (u32)(NSECS_PER_SEC << shift);
 151                 clktimh = (u32)((NSECS_PER_SEC << shift) >> 32);
 152
 153                 /*
 154                  * Account for the cyclecounter wrap-around value by
 155                  * using the converted ns value of the current time to
 156                  * check for when the next aligned second would occur.
 157                  */
 158                 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 159                 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 160                 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
 161
 162                 div_u64_rem(ns, NSECS_PER_SEC, &rem);
 163                 clock_edge += ((NSECS_PER_SEC - (u64)rem) << shift);
 164
 165                 /* specify the initial clock start time */
 166                 trgttiml = (u32)clock_edge;
 167                 trgttimh = (u32)(clock_edge >> 32);
 168
 169                 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
 170                 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
 171                 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
 172                 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
 173
 174                 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
 175                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
 176         } else {
 177                 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
 178         }
 179
 180         IXGBE_WRITE_FLUSH(hw);
 181 }
 182
 183 /**
 184  * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
 185  * @cc: the cyclecounter structure
 186  *
 187  * this function reads the cyclecounter registers and is called by the
 188  * cyclecounter structure used to construct a ns counter from the
 189  * arbitrary fixed point registers
 190  */
 191 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
 192 {
 193         struct ixgbe_adapter *adapter =
 194                 container_of(cc, struct ixgbe_adapter, cc);
 195         struct ixgbe_hw *hw = &adapter->hw;
 196         u64 stamp = 0;
 197
 198         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
 199         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
 200
 201         return stamp;
 202 }
 203
 204 /**
 205  * ixgbe_ptp_adjfreq
 206  * @ptp: the ptp clock structure
 207  * @ppb: parts per billion adjustment from base
 208  *
 209  * adjust the frequency of the ptp cycle counter by the
 210  * indicated ppb from the base frequency.
 211  */
 212 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 213 {
 214         struct ixgbe_adapter *adapter =
 215                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 216         struct ixgbe_hw *hw = &adapter->hw;
 217         u64 freq;
 218         u32 diff, incval;
 219         int neg_adj = 0;
 220
 221         if (ppb < 0) {
 222                 neg_adj = 1;
 223                 ppb = -ppb;
 224         }
 225
 226         smp_mb();
 227         incval = ACCESS_ONCE(adapter->base_incval);
 228
 229         freq = incval;
 230         freq *= ppb;
 231         diff = div_u64(freq, 1000000000ULL);
 232
 233         incval = neg_adj ? (incval - diff) : (incval + diff);
 234
 235         switch (hw->mac.type) {
 236         case ixgbe_mac_X540:
 237                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
 238                 break;
 239         case ixgbe_mac_82599EB:
 240                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 241                                 (1 << IXGBE_INCPER_SHIFT_82599) |
 242                                 incval);
 243                 break;
 244         default:
 245                 break;
 246         }
 247
 248         return 0;
 249 }
 250
 251 /**
 252  * ixgbe_ptp_adjtime
 253  * @ptp: the ptp clock structure
 254  * @delta: offset to adjust the cycle counter by
 255  *
 256  * adjust the timer by resetting the timecounter structure.
 257  */
 258 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
 259 {
 260         struct ixgbe_adapter *adapter =
 261                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 262         unsigned long flags;
 263         u64 now;
 264
 265         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 266
 267         now = timecounter_read(&adapter->tc);
 268         now += delta;
 269
 270         /* reset the timecounter */
 271         timecounter_init(&adapter->tc,
 272                          &adapter->cc,
 273                          now);
 274
 275         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 276
 277         ixgbe_ptp_setup_sdp(adapter);
 278
 279         return 0;
 280 }
 281
 282 /**
 283  * ixgbe_ptp_gettime
 284  * @ptp: the ptp clock structure
 285  * @ts: timespec structure to hold the current time value
 286  *
 287  * read the timecounter and return the correct value on ns,
 288  * after converting it into a struct timespec.
 289  */
 290 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 291 {
 292         struct ixgbe_adapter *adapter =
 293                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 294         u64 ns;
 295         u32 remainder;
 296         unsigned long flags;
 297
 298         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 299         ns = timecounter_read(&adapter->tc);
 300         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 301
 302         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
 303         ts->tv_nsec = remainder;
 304
 305         return 0;
 306 }
 307
 308 /**
 309  * ixgbe_ptp_settime
 310  * @ptp: the ptp clock structure
 311  * @ts: the timespec containing the new time for the cycle counter
 312  *
 313  * reset the timecounter to use a new base value instead of the kernel
 314  * wall timer value.
 315  */
 316 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
 317                              const struct timespec *ts)
 318 {
 319         struct ixgbe_adapter *adapter =
 320                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 321         u64 ns;
 322         unsigned long flags;
 323
 324         ns = ts->tv_sec * 1000000000ULL;
 325         ns += ts->tv_nsec;
 326
 327         /* reset the timecounter */
 328         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 329         timecounter_init(&adapter->tc, &adapter->cc, ns);
 330         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 331
 332         ixgbe_ptp_setup_sdp(adapter);
 333         return 0;
 334 }
 335
 336 /**
 337  * ixgbe_ptp_feature_enable
 338  * @ptp: the ptp clock structure
 339  * @rq: the requested feature to change
 340  * @on: whether to enable or disable the feature
 341  *
 342  * enable (or disable) ancillary features of the phc subsystem.
 343  * our driver only supports the PPS feature on the X540
 344  */
 345 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
 346                                     struct ptp_clock_request *rq, int on)
 347 {
 348         struct ixgbe_adapter *adapter =
 349                 container_of(ptp, struct ixgbe_adapter, ptp_caps);
 350
 351         /**
 352          * When PPS is enabled, unmask the interrupt for the ClockOut
 353          * feature, so that the interrupt handler can send the PPS
 354          * event when the clock SDP triggers. Clear mask when PPS is
 355          * disabled
 356          */
 357         if (rq->type == PTP_CLK_REQ_PPS) {
 358                 switch (adapter->hw.mac.type) {
 359                 case ixgbe_mac_X540:
 360                         if (on)
 361                                 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
 362                         else
 363                                 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
 364
 365                         ixgbe_ptp_setup_sdp(adapter);
 366                         return 0;
 367                 default:
 368                         break;
 369                 }
 370         }
 371
 372         return -ENOTSUPP;
 373 }
 374
 375 /**
 376  * ixgbe_ptp_check_pps_event
 377  * @adapter: the private adapter structure
 378  * @eicr: the interrupt cause register value
 379  *
 380  * This function is called by the interrupt routine when checking for
 381  * interrupts. It will check and handle a pps event.
 382  */
 383 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
 384 {
 385         struct ixgbe_hw *hw = &adapter->hw;
 386         struct ptp_clock_event event;
 387
 388         event.type = PTP_CLOCK_PPS;
 389
 390         /* this check is necessary in case the interrupt was enabled via some
 391          * alternative means (ex. debug_fs). Better to check here than
 392          * everywhere that calls this function.
 393          */
 394         if (!adapter->ptp_clock)
 395                 return;
 396
 397         switch (hw->mac.type) {
 398         case ixgbe_mac_X540:
 399                 ptp_clock_event(adapter->ptp_clock, &event);
 400                 break;
 401         default:
 402                 break;
 403         }
 404 }
 405
 406 /**
 407  * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
 408  * @adapter: private adapter struct
 409  *
 410  * this watchdog task periodically reads the timecounter
 411  * in order to prevent missing when the system time registers wrap
 412  * around. This needs to be run approximately twice a minute.
 413  */
 414 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
 415 {
 416         bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
 417                                              IXGBE_OVERFLOW_PERIOD);
 418         struct timespec ts;
 419
 420         if (timeout) {
 421                 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
 422                 adapter->last_overflow_check = jiffies;
 423         }
 424 }
 425
 426 /**
 427  * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
 428  * @adapter: private network adapter structure
 429  *
 430  * this watchdog task is scheduled to detect error case where hardware has
 431  * dropped an Rx packet that was timestamped when the ring is full. The
 432  * particular error is rare but leaves the device in a state unable to timestamp
 433  * any future packets.
 434  */
 435 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
 436 {
 437         struct ixgbe_hw *hw = &adapter->hw;
 438         u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 439         unsigned long rx_event;
 440
 441         /* if we don't have a valid timestamp in the registers, just update the
 442          * timeout counter and exit
 443          */
 444         if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
 445                 adapter->last_rx_ptp_check = jiffies;
 446                 return;
 447         }
 448
 449         /* determine the most recent watchdog or rx_timestamp event */
 450         rx_event = adapter->last_rx_ptp_check;
 451         if (time_after(adapter->last_rx_timestamp, rx_event))
 452                 rx_event = adapter->last_rx_timestamp;
 453
 454         /* only need to read the high RXSTMP register to clear the lock */
 455         if (time_is_before_jiffies(rx_event + 5*HZ)) {
 456                 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
 457                 adapter->last_rx_ptp_check = jiffies;
 458
 459                 e_warn(drv, "clearing RX Timestamp hang\n");
 460         }
 461 }
 462
 463 /**
 464  * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
 465  * @adapter: the private adapter struct
 466  *
 467  * if the timestamp is valid, we convert it into the timecounter ns
 468  * value, then store that result into the shhwtstamps structure which
 469  * is passed up the network stack
 470  */
 471 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
 472 {
 473         struct ixgbe_hw *hw = &adapter->hw;
 474         struct skb_shared_hwtstamps shhwtstamps;
 475         u64 regval = 0, ns;
 476         unsigned long flags;
 477
 478         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
 479         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
 480
 481         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 482         ns = timecounter_cyc2time(&adapter->tc, regval);
 483         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 484
 485         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 486         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 487         skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
 488
 489         dev_kfree_skb_any(adapter->ptp_tx_skb);
 490         adapter->ptp_tx_skb = NULL;
 491         clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
 492 }
 493
 494 /**
 495  * ixgbe_ptp_tx_hwtstamp_work
 496  * @work: pointer to the work struct
 497  *
 498  * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
 499  * timestamp has been taken for the current skb. It is necesary, because the
 500  * descriptor's "done" bit does not correlate with the timestamp event.
 501  */
 502 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
 503 {
 504         struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
 505                                                      ptp_tx_work);
 506         struct ixgbe_hw *hw = &adapter->hw;
 507         bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
 508                                               IXGBE_PTP_TX_TIMEOUT);
 509         u32 tsynctxctl;
 510
 511         if (timeout) {
 512                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 513                 adapter->ptp_tx_skb = NULL;
 514                 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
 515                 e_warn(drv, "clearing Tx Timestamp hang\n");
 516                 return;
 517         }
 518
 519         tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 520         if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID)
 521                 ixgbe_ptp_tx_hwtstamp(adapter);
 522         else
 523                 /* reschedule to keep checking if it's not available yet */
 524                 schedule_work(&adapter->ptp_tx_work);
 525 }
 526
 527 /**
 528  * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
 529  * @adapter: pointer to adapter struct
 530  * @skb: particular skb to send timestamp with
 531  *
 532  * if the timestamp is valid, we convert it into the timecounter ns
 533  * value, then store that result into the shhwtstamps structure which
 534  * is passed up the network stack
 535  */
 536 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb)
 537 {
 538         struct ixgbe_hw *hw = &adapter->hw;
 539         struct skb_shared_hwtstamps *shhwtstamps;
 540         u64 regval = 0, ns;
 541         u32 tsyncrxctl;
 542         unsigned long flags;
 543
 544         tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 545         if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
 546                 return;
 547
 548         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
 549         regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
 550
 551         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 552         ns = timecounter_cyc2time(&adapter->tc, regval);
 553         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 554
 555         shhwtstamps = skb_hwtstamps(skb);
 556         shhwtstamps->hwtstamp = ns_to_ktime(ns);
 557
 558         /* Update the last_rx_timestamp timer in order to enable watchdog check
 559          * for error case of latched timestamp on a dropped packet.
 560          */
 561         adapter->last_rx_timestamp = jiffies;
 562 }
 563
 564 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
 565 {
 566         struct hwtstamp_config *config = &adapter->tstamp_config;
 567
 568         return copy_to_user(ifr->ifr_data, config,
 569                             sizeof(*config)) ? -EFAULT : 0;
 570 }
 571
 572 /**
 573  * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
 574  * @adapter: the private ixgbe adapter structure
 575  * @config: the hwtstamp configuration requested
 576  *
 577  * Outgoing time stamping can be enabled and disabled. Play nice and
 578  * disable it when requested, although it shouldn't cause any overhead
 579  * when no packet needs it. At most one packet in the queue may be
 580  * marked for time stamping, otherwise it would be impossible to tell
 581  * for sure to which packet the hardware time stamp belongs.
 582  *
 583  * Incoming time stamping has to be configured via the hardware
 584  * filters. Not all combinations are supported, in particular event
 585  * type has to be specified. Matching the kind of event packet is
 586  * not supported, with the exception of "all V2 events regardless of
 587  * level 2 or 4".
 588  *
 589  * Since hardware always timestamps Path delay packets when timestamping V2
 590  * packets, regardless of the type specified in the register, only use V2
 591  * Event mode. This more accurately tells the user what the hardware is going
 592  * to do anyways.
 593  *
 594  * Note: this may modify the hwtstamp configuration towards a more general
 595  * mode, if required to support the specifically requested mode.
 596  */
 597 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
 598                                  struct hwtstamp_config *config)
 599 {
 600         struct ixgbe_hw *hw = &adapter->hw;
 601         u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
 602         u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
 603         u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
 604         bool is_l2 = false;
 605         u32 regval;
 606
 607         /* reserved for future extensions */
 608         if (config->flags)
 609                 return -EINVAL;
 610
 611         switch (config->tx_type) {
 612         case HWTSTAMP_TX_OFF:
 613                 tsync_tx_ctl = 0;
 614         case HWTSTAMP_TX_ON:
 615                 break;
 616         default:
 617                 return -ERANGE;
 618         }
 619
 620         switch (config->rx_filter) {
 621         case HWTSTAMP_FILTER_NONE:
 622                 tsync_rx_ctl = 0;
 623                 tsync_rx_mtrl = 0;
 624                 break;
 625         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 626                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
 627                 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
 628                 break;
 629         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 630                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
 631                 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
 632                 break;
 633         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 634         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 635         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 636         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 637         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 638         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 639         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 640         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 641         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 642                 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
 643                 is_l2 = true;
 644                 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 645                 break;
 646         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 647         case HWTSTAMP_FILTER_ALL:
 648         default:
 649                 /*
 650                  * register RXMTRL must be set in order to do V1 packets,
 651                  * therefore it is not possible to time stamp both V1 Sync and
 652                  * Delay_Req messages and hardware does not support
 653                  * timestamping all packets => return error
 654                  */
 655                 config->rx_filter = HWTSTAMP_FILTER_NONE;
 656                 return -ERANGE;
 657         }
 658
 659         if (hw->mac.type == ixgbe_mac_82598EB) {
 660                 if (tsync_rx_ctl | tsync_tx_ctl)
 661                         return -ERANGE;
 662                 return 0;
 663         }
 664
 665         /* define ethertype filter for timestamping L2 packets */
 666         if (is_l2)
 667                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
 668                                 (IXGBE_ETQF_FILTER_EN | /* enable filter */
 669                                  IXGBE_ETQF_1588 | /* enable timestamping */
 670                                  ETH_P_1588));     /* 1588 eth protocol type */
 671         else
 672                 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
 673
 674         /* enable/disable TX */
 675         regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
 676         regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
 677         regval |= tsync_tx_ctl;
 678         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
 679
 680         /* enable/disable RX */
 681         regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
 682         regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
 683         regval |= tsync_rx_ctl;
 684         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
 685
 686         /* define which PTP packets are time stamped */
 687         IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
 688
 689         IXGBE_WRITE_FLUSH(hw);
 690
 691         /* clear TX/RX time stamp registers, just to be sure */
 692         regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
 693         regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
 694
 695         return 0;
 696 }
 697
 698 /**
 699  * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
 700  * @adapter: pointer to adapter struct
 701  * @ifreq: ioctl data
 702  *
 703  * Set hardware to requested mode. If unsupported, return an error with no
 704  * changes. Otherwise, store the mode for future reference.
 705  */
 706 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
 707 {
 708         struct hwtstamp_config config;
 709         int err;
 710
 711         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 712                 return -EFAULT;
 713
 714         err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
 715         if (err)
 716                 return err;
 717
 718         /* save these settings for future reference */
 719         memcpy(&adapter->tstamp_config, &config,
 720                sizeof(adapter->tstamp_config));
 721
 722         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 723                 -EFAULT : 0;
 724 }
 725
 726 /**
 727  * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
 728  * @adapter: pointer to the adapter structure
 729  *
 730  * This function should be called to set the proper values for the TIMINCA
 731  * register and tell the cyclecounter structure what the tick rate of SYSTIME
 732  * is. It does not directly modify SYSTIME registers or the timecounter
 733  * structure. It should be called whenever a new TIMINCA value is necessary,
 734  * such as during initialization or when the link speed changes.
 735  */
 736 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
 737 {
 738         struct ixgbe_hw *hw = &adapter->hw;
 739         u32 incval = 0;
 740         u32 shift = 0;
 741         unsigned long flags;
 742
 743         /**
 744          * Scale the NIC cycle counter by a large factor so that
 745          * relatively small corrections to the frequency can be added
 746          * or subtracted. The drawbacks of a large factor include
 747          * (a) the clock register overflows more quickly, (b) the cycle
 748          * counter structure must be able to convert the systime value
 749          * to nanoseconds using only a multiplier and a right-shift,
 750          * and (c) the value must fit within the timinca register space
 751          * => math based on internal DMA clock rate and available bits
 752          *
 753          * Note that when there is no link, internal DMA clock is same as when
 754          * link speed is 10Gb. Set the registers correctly even when link is
 755          * down to preserve the clock setting
 756          */
 757         switch (adapter->link_speed) {
 758         case IXGBE_LINK_SPEED_100_FULL:
 759                 incval = IXGBE_INCVAL_100;
 760                 shift = IXGBE_INCVAL_SHIFT_100;
 761                 break;
 762         case IXGBE_LINK_SPEED_1GB_FULL:
 763                 incval = IXGBE_INCVAL_1GB;
 764                 shift = IXGBE_INCVAL_SHIFT_1GB;
 765                 break;
 766         case IXGBE_LINK_SPEED_10GB_FULL:
 767         default:
 768                 incval = IXGBE_INCVAL_10GB;
 769                 shift = IXGBE_INCVAL_SHIFT_10GB;
 770                 break;
 771         }
 772
 773         /**
 774          * Modify the calculated values to fit within the correct
 775          * number of bits specified by the hardware. The 82599 doesn't
 776          * have the same space as the X540, so bitshift the calculated
 777          * values to fit.
 778          */
 779         switch (hw->mac.type) {
 780         case ixgbe_mac_X540:
 781                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
 782                 break;
 783         case ixgbe_mac_82599EB:
 784                 incval >>= IXGBE_INCVAL_SHIFT_82599;
 785                 shift -= IXGBE_INCVAL_SHIFT_82599;
 786                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
 787                                 (1 << IXGBE_INCPER_SHIFT_82599) |
 788                                 incval);
 789                 break;
 790         default:
 791                 /* other devices aren't supported */
 792                 return;
 793         }
 794
 795         /* update the base incval used to calculate frequency adjustment */
 796         ACCESS_ONCE(adapter->base_incval) = incval;
 797         smp_mb();
 798
 799         /* need lock to prevent incorrect read while modifying cyclecounter */
 800         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 801
 802         memset(&adapter->cc, 0, sizeof(adapter->cc));
 803         adapter->cc.read = ixgbe_ptp_read;
 804         adapter->cc.mask = CLOCKSOURCE_MASK(64);
 805         adapter->cc.shift = shift;
 806         adapter->cc.mult = 1;
 807
 808         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 809 }
 810
 811 /**
 812  * ixgbe_ptp_reset
 813  * @adapter: the ixgbe private board structure
 814  *
 815  * When the MAC resets, all the hardware bits for timesync are reset. This
 816  * function is used to re-enable the device for PTP based on current settings.
 817  * We do lose the current clock time, so just reset the cyclecounter to the
 818  * system real clock time.
 819  *
 820  * This function will maintain hwtstamp_config settings, and resets the SDP
 821  * output if it was enabled.
 822  */
 823 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
 824 {
 825         struct ixgbe_hw *hw = &adapter->hw;
 826         unsigned long flags;
 827
 828         /* set SYSTIME registers to 0 just in case */
 829         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
 830         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
 831         IXGBE_WRITE_FLUSH(hw);
 832
 833         /* reset the hardware timestamping mode */
 834         ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
 835
 836         ixgbe_ptp_start_cyclecounter(adapter);
 837
 838         spin_lock_irqsave(&adapter->tmreg_lock, flags);
 839
 840         /* reset the ns time counter */
 841         timecounter_init(&adapter->tc, &adapter->cc,
 842                          ktime_to_ns(ktime_get_real()));
 843
 844         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
 845
 846         /*
 847          * Now that the shift has been calculated and the systime
 848          * registers reset, (re-)enable the Clock out feature
 849          */
 850         ixgbe_ptp_setup_sdp(adapter);
 851 }
 852
 853 /**
 854  * ixgbe_ptp_init
 855  * @adapter: the ixgbe private adapter structure
 856  *
 857  * This function performs the required steps for enabling ptp
 858  * support. If ptp support has already been loaded it simply calls the
 859  * cyclecounter init routine and exits.
 860  */
 861 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
 862 {
 863         struct net_device *netdev = adapter->netdev;
 864
 865         switch (adapter->hw.mac.type) {
 866         case ixgbe_mac_X540:
 867                 snprintf(adapter->ptp_caps.name,
 868                          sizeof(adapter->ptp_caps.name),
 869                          "%s", netdev->name);
 870                 adapter->ptp_caps.owner = THIS_MODULE;
 871                 adapter->ptp_caps.max_adj = 250000000;
 872                 adapter->ptp_caps.n_alarm = 0;
 873                 adapter->ptp_caps.n_ext_ts = 0;
 874                 adapter->ptp_caps.n_per_out = 0;
 875                 adapter->ptp_caps.pps = 1;
 876                 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
 877                 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
 878                 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
 879                 adapter->ptp_caps.settime = ixgbe_ptp_settime;
 880                 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
 881                 break;
 882         case ixgbe_mac_82599EB:
 883                 snprintf(adapter->ptp_caps.name,
 884                          sizeof(adapter->ptp_caps.name),
 885                          "%s", netdev->name);
 886                 adapter->ptp_caps.owner = THIS_MODULE;
 887                 adapter->ptp_caps.max_adj = 250000000;
 888                 adapter->ptp_caps.n_alarm = 0;
 889                 adapter->ptp_caps.n_ext_ts = 0;
 890                 adapter->ptp_caps.n_per_out = 0;
 891                 adapter->ptp_caps.pps = 0;
 892                 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
 893                 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
 894                 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
 895                 adapter->ptp_caps.settime = ixgbe_ptp_settime;
 896                 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
 897                 break;
 898         default:
 899                 adapter->ptp_clock = NULL;
 900                 return;
 901         }
 902
 903         spin_lock_init(&adapter->tmreg_lock);
 904         INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
 905
 906         adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
 907                                                 &adapter->pdev->dev);
 908         if (IS_ERR(adapter->ptp_clock)) {
 909                 adapter->ptp_clock = NULL;
 910                 e_dev_err("ptp_clock_register failed\n");
 911         } else
 912                 e_dev_info("registered PHC device on %s\n", netdev->name);
 913
 914         adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
 915         adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
 916         ixgbe_ptp_reset(adapter);
 917
 918         /* enter the IXGBE_PTP_RUNNING state */
 919         set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
 920
 921         return;
 922 }
 923
 924 /**
 925  * ixgbe_ptp_stop - disable ptp device and stop the overflow check
 926  * @adapter: pointer to adapter struct
 927  *
 928  * this function stops the ptp support, and cancels the delayed work.
 929  */
 930 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
 931 {
 932         /* Leave the IXGBE_PTP_RUNNING state. */
 933         if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
 934                 return;
 935
 936         /* stop the PPS signal */
 937         adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
 938         ixgbe_ptp_setup_sdp(adapter);
 939
 940         cancel_work_sync(&adapter->ptp_tx_work);
 941         if (adapter->ptp_tx_skb) {
 942                 dev_kfree_skb_any(adapter->ptp_tx_skb);
 943                 adapter->ptp_tx_skb = NULL;
 944                 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
 945         }
 946
 947         if (adapter->ptp_clock) {
 948                 ptp_clock_unregister(adapter->ptp_clock);
 949                 adapter->ptp_clock = NULL;
 950                 e_dev_info("removed PHC on %s\n",
 951                            adapter->netdev->name);
 952         }
 953 }