1 /*******************************************************************************
3 * Intel 10 Gigabit PCI Express Linux driver
4 * Copyright(c) 1999 - 2015 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
18 * Contact Information:
19 * Linux NICS <linux.nics@intel.com>
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 ******************************************************************************/
24 #include "ixgbe_x540.h"
25 #include "ixgbe_type.h"
26 #include "ixgbe_common.h"
27 #include "ixgbe_phy.h"
29 static s32
ixgbe_get_invariants_X550_x(struct ixgbe_hw
*hw
)
31 struct ixgbe_mac_info
*mac
= &hw
->mac
;
32 struct ixgbe_phy_info
*phy
= &hw
->phy
;
34 /* Start with X540 invariants, since so simular */
35 ixgbe_get_invariants_X540(hw
);
37 if (mac
->ops
.get_media_type(hw
) != ixgbe_media_type_copper
)
38 phy
->ops
.set_phy_power
= NULL
;
43 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
44 * @hw: pointer to hardware structure
46 static void ixgbe_setup_mux_ctl(struct ixgbe_hw
*hw
)
48 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
51 esdp
&= ~(IXGBE_ESDP_SDP1_NATIVE
| IXGBE_ESDP_SDP1
);
52 esdp
|= IXGBE_ESDP_SDP1_DIR
;
54 esdp
&= ~(IXGBE_ESDP_SDP0_NATIVE
| IXGBE_ESDP_SDP0_DIR
);
55 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp
);
56 IXGBE_WRITE_FLUSH(hw
);
59 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
60 * @hw: pointer to hardware structure
64 static s32
ixgbe_identify_phy_x550em(struct ixgbe_hw
*hw
)
66 switch (hw
->device_id
) {
67 case IXGBE_DEV_ID_X550EM_X_SFP
:
68 /* set up for CS4227 usage */
69 hw
->phy
.phy_semaphore_mask
= IXGBE_GSSR_SHARED_I2C_SM
;
70 ixgbe_setup_mux_ctl(hw
);
72 return ixgbe_identify_module_generic(hw
);
73 case IXGBE_DEV_ID_X550EM_X_KX4
:
74 hw
->phy
.type
= ixgbe_phy_x550em_kx4
;
76 case IXGBE_DEV_ID_X550EM_X_KR
:
77 hw
->phy
.type
= ixgbe_phy_x550em_kr
;
79 case IXGBE_DEV_ID_X550EM_X_1G_T
:
80 case IXGBE_DEV_ID_X550EM_X_10G_T
:
81 return ixgbe_identify_phy_generic(hw
);
88 static s32
ixgbe_read_phy_reg_x550em(struct ixgbe_hw
*hw
, u32 reg_addr
,
89 u32 device_type
, u16
*phy_data
)
91 return IXGBE_NOT_IMPLEMENTED
;
94 static s32
ixgbe_write_phy_reg_x550em(struct ixgbe_hw
*hw
, u32 reg_addr
,
95 u32 device_type
, u16 phy_data
)
97 return IXGBE_NOT_IMPLEMENTED
;
100 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
101 * @hw: pointer to hardware structure
103 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
104 * ixgbe_hw struct in order to set up EEPROM access.
106 static s32
ixgbe_init_eeprom_params_X550(struct ixgbe_hw
*hw
)
108 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
112 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
113 eeprom
->semaphore_delay
= 10;
114 eeprom
->type
= ixgbe_flash
;
116 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
117 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
118 IXGBE_EEC_SIZE_SHIFT
);
119 eeprom
->word_size
= 1 << (eeprom_size
+
120 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
122 hw_dbg(hw
, "Eeprom params: type = %d, size = %d\n",
123 eeprom
->type
, eeprom
->word_size
);
130 * ixgbe_iosf_wait - Wait for IOSF command completion
131 * @hw: pointer to hardware structure
132 * @ctrl: pointer to location to receive final IOSF control value
134 * Return: failing status on timeout
136 * Note: ctrl can be NULL if the IOSF control register value is not needed
138 static s32
ixgbe_iosf_wait(struct ixgbe_hw
*hw
, u32
*ctrl
)
142 /* Check every 10 usec to see if the address cycle completed.
143 * The SB IOSF BUSY bit will clear when the operation is
146 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
147 command
= IXGBE_READ_REG(hw
, IXGBE_SB_IOSF_INDIRECT_CTRL
);
148 if (!(command
& IXGBE_SB_IOSF_CTRL_BUSY
))
150 usleep_range(10, 20);
154 if (i
== IXGBE_MDIO_COMMAND_TIMEOUT
) {
155 hw_dbg(hw
, "IOSF wait timed out\n");
156 return IXGBE_ERR_PHY
;
162 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
164 * @hw: pointer to hardware structure
165 * @reg_addr: 32 bit PHY register to write
166 * @device_type: 3 bit device type
167 * @phy_data: Pointer to read data from the register
169 static s32
ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw
*hw
, u32 reg_addr
,
170 u32 device_type
, u32
*data
)
172 u32 gssr
= IXGBE_GSSR_PHY1_SM
| IXGBE_GSSR_PHY0_SM
;
176 ret
= hw
->mac
.ops
.acquire_swfw_sync(hw
, gssr
);
180 ret
= ixgbe_iosf_wait(hw
, NULL
);
184 command
= ((reg_addr
<< IXGBE_SB_IOSF_CTRL_ADDR_SHIFT
) |
185 (device_type
<< IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT
));
187 /* Write IOSF control register */
188 IXGBE_WRITE_REG(hw
, IXGBE_SB_IOSF_INDIRECT_CTRL
, command
);
190 ret
= ixgbe_iosf_wait(hw
, &command
);
192 if ((command
& IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK
) != 0) {
193 error
= (command
& IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK
) >>
194 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT
;
195 hw_dbg(hw
, "Failed to read, error %x\n", error
);
196 return IXGBE_ERR_PHY
;
200 *data
= IXGBE_READ_REG(hw
, IXGBE_SB_IOSF_INDIRECT_DATA
);
203 hw
->mac
.ops
.release_swfw_sync(hw
, gssr
);
207 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
208 * command assuming that the semaphore is already obtained.
209 * @hw: pointer to hardware structure
210 * @offset: offset of word in the EEPROM to read
211 * @data: word read from the EEPROM
213 * Reads a 16 bit word from the EEPROM using the hostif.
215 static s32
ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw
*hw
, u16 offset
,
219 struct ixgbe_hic_read_shadow_ram buffer
;
221 buffer
.hdr
.req
.cmd
= FW_READ_SHADOW_RAM_CMD
;
222 buffer
.hdr
.req
.buf_lenh
= 0;
223 buffer
.hdr
.req
.buf_lenl
= FW_READ_SHADOW_RAM_LEN
;
224 buffer
.hdr
.req
.checksum
= FW_DEFAULT_CHECKSUM
;
226 /* convert offset from words to bytes */
227 buffer
.address
= cpu_to_be32(offset
* 2);
229 buffer
.length
= cpu_to_be16(sizeof(u16
));
231 status
= ixgbe_host_interface_command(hw
, (u32
*)&buffer
,
233 IXGBE_HI_COMMAND_TIMEOUT
, false);
237 *data
= (u16
)IXGBE_READ_REG_ARRAY(hw
, IXGBE_FLEX_MNG
,
243 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
244 * @hw: pointer to hardware structure
245 * @offset: offset of word in the EEPROM to read
246 * @words: number of words
247 * @data: word(s) read from the EEPROM
249 * Reads a 16 bit word(s) from the EEPROM using the hostif.
251 static s32
ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw
*hw
,
252 u16 offset
, u16 words
, u16
*data
)
254 struct ixgbe_hic_read_shadow_ram buffer
;
255 u32 current_word
= 0;
260 /* Take semaphore for the entire operation. */
261 status
= hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
263 hw_dbg(hw
, "EEPROM read buffer - semaphore failed\n");
268 if (words
> FW_MAX_READ_BUFFER_SIZE
/ 2)
269 words_to_read
= FW_MAX_READ_BUFFER_SIZE
/ 2;
271 words_to_read
= words
;
273 buffer
.hdr
.req
.cmd
= FW_READ_SHADOW_RAM_CMD
;
274 buffer
.hdr
.req
.buf_lenh
= 0;
275 buffer
.hdr
.req
.buf_lenl
= FW_READ_SHADOW_RAM_LEN
;
276 buffer
.hdr
.req
.checksum
= FW_DEFAULT_CHECKSUM
;
278 /* convert offset from words to bytes */
279 buffer
.address
= cpu_to_be32((offset
+ current_word
) * 2);
280 buffer
.length
= cpu_to_be16(words_to_read
* 2);
282 status
= ixgbe_host_interface_command(hw
, (u32
*)&buffer
,
284 IXGBE_HI_COMMAND_TIMEOUT
,
287 hw_dbg(hw
, "Host interface command failed\n");
291 for (i
= 0; i
< words_to_read
; i
++) {
292 u32 reg
= IXGBE_FLEX_MNG
+ (FW_NVM_DATA_OFFSET
<< 2) +
294 u32 value
= IXGBE_READ_REG(hw
, reg
);
296 data
[current_word
] = (u16
)(value
& 0xffff);
299 if (i
< words_to_read
) {
301 data
[current_word
] = (u16
)(value
& 0xffff);
305 words
-= words_to_read
;
309 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
313 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
314 * @hw: pointer to hardware structure
315 * @ptr: pointer offset in eeprom
316 * @size: size of section pointed by ptr, if 0 first word will be used as size
317 * @csum: address of checksum to update
319 * Returns error status for any failure
321 static s32
ixgbe_checksum_ptr_x550(struct ixgbe_hw
*hw
, u16 ptr
,
322 u16 size
, u16
*csum
, u16
*buffer
,
327 u16 length
, bufsz
, i
, start
;
330 bufsz
= sizeof(buf
) / sizeof(buf
[0]);
332 /* Read a chunk at the pointer location */
334 status
= ixgbe_read_ee_hostif_buffer_X550(hw
, ptr
, bufsz
, buf
);
336 hw_dbg(hw
, "Failed to read EEPROM image\n");
341 if (buffer_size
< ptr
)
342 return IXGBE_ERR_PARAM
;
343 local_buffer
= &buffer
[ptr
];
351 length
= local_buffer
[0];
353 /* Skip pointer section if length is invalid. */
354 if (length
== 0xFFFF || length
== 0 ||
355 (ptr
+ length
) >= hw
->eeprom
.word_size
)
359 if (buffer
&& ((u32
)start
+ (u32
)length
> buffer_size
))
360 return IXGBE_ERR_PARAM
;
362 for (i
= start
; length
; i
++, length
--) {
363 if (i
== bufsz
&& !buffer
) {
369 /* Read a chunk at the pointer location */
370 status
= ixgbe_read_ee_hostif_buffer_X550(hw
, ptr
,
373 hw_dbg(hw
, "Failed to read EEPROM image\n");
377 *csum
+= local_buffer
[i
];
382 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
383 * @hw: pointer to hardware structure
384 * @buffer: pointer to buffer containing calculated checksum
385 * @buffer_size: size of buffer
387 * Returns a negative error code on error, or the 16-bit checksum
389 static s32
ixgbe_calc_checksum_X550(struct ixgbe_hw
*hw
, u16
*buffer
,
392 u16 eeprom_ptrs
[IXGBE_EEPROM_LAST_WORD
+ 1];
396 u16 pointer
, i
, size
;
398 hw
->eeprom
.ops
.init_params(hw
);
401 /* Read pointer area */
402 status
= ixgbe_read_ee_hostif_buffer_X550(hw
, 0,
403 IXGBE_EEPROM_LAST_WORD
+ 1,
406 hw_dbg(hw
, "Failed to read EEPROM image\n");
409 local_buffer
= eeprom_ptrs
;
411 if (buffer_size
< IXGBE_EEPROM_LAST_WORD
)
412 return IXGBE_ERR_PARAM
;
413 local_buffer
= buffer
;
416 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
417 * checksum word itself
419 for (i
= 0; i
<= IXGBE_EEPROM_LAST_WORD
; i
++)
420 if (i
!= IXGBE_EEPROM_CHECKSUM
)
421 checksum
+= local_buffer
[i
];
423 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
424 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
426 for (i
= IXGBE_PCIE_ANALOG_PTR_X550
; i
< IXGBE_FW_PTR
; i
++) {
427 if (i
== IXGBE_PHY_PTR
|| i
== IXGBE_OPTION_ROM_PTR
)
430 pointer
= local_buffer
[i
];
432 /* Skip pointer section if the pointer is invalid. */
433 if (pointer
== 0xFFFF || pointer
== 0 ||
434 pointer
>= hw
->eeprom
.word_size
)
438 case IXGBE_PCIE_GENERAL_PTR
:
439 size
= IXGBE_IXGBE_PCIE_GENERAL_SIZE
;
441 case IXGBE_PCIE_CONFIG0_PTR
:
442 case IXGBE_PCIE_CONFIG1_PTR
:
443 size
= IXGBE_PCIE_CONFIG_SIZE
;
450 status
= ixgbe_checksum_ptr_x550(hw
, pointer
, size
, &checksum
,
451 buffer
, buffer_size
);
456 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
458 return (s32
)checksum
;
461 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
462 * @hw: pointer to hardware structure
464 * Returns a negative error code on error, or the 16-bit checksum
466 static s32
ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw
*hw
)
468 return ixgbe_calc_checksum_X550(hw
, NULL
, 0);
471 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
472 * @hw: pointer to hardware structure
473 * @offset: offset of word in the EEPROM to read
474 * @data: word read from the EEPROM
476 * Reads a 16 bit word from the EEPROM using the hostif.
478 static s32
ixgbe_read_ee_hostif_X550(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
482 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) == 0) {
483 status
= ixgbe_read_ee_hostif_data_X550(hw
, offset
, data
);
484 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
486 status
= IXGBE_ERR_SWFW_SYNC
;
492 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
493 * @hw: pointer to hardware structure
494 * @checksum_val: calculated checksum
496 * Performs checksum calculation and validates the EEPROM checksum. If the
497 * caller does not need checksum_val, the value can be NULL.
499 static s32
ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw
*hw
,
504 u16 read_checksum
= 0;
506 /* Read the first word from the EEPROM. If this times out or fails, do
507 * not continue or we could be in for a very long wait while every
510 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
512 hw_dbg(hw
, "EEPROM read failed\n");
516 status
= hw
->eeprom
.ops
.calc_checksum(hw
);
520 checksum
= (u16
)(status
& 0xffff);
522 status
= ixgbe_read_ee_hostif_X550(hw
, IXGBE_EEPROM_CHECKSUM
,
527 /* Verify read checksum from EEPROM is the same as
528 * calculated checksum
530 if (read_checksum
!= checksum
) {
531 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
532 hw_dbg(hw
, "Invalid EEPROM checksum");
535 /* If the user cares, return the calculated checksum */
537 *checksum_val
= checksum
;
542 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
543 * @hw: pointer to hardware structure
544 * @offset: offset of word in the EEPROM to write
545 * @data: word write to the EEPROM
547 * Write a 16 bit word to the EEPROM using the hostif.
549 static s32
ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw
*hw
, u16 offset
,
553 struct ixgbe_hic_write_shadow_ram buffer
;
555 buffer
.hdr
.req
.cmd
= FW_WRITE_SHADOW_RAM_CMD
;
556 buffer
.hdr
.req
.buf_lenh
= 0;
557 buffer
.hdr
.req
.buf_lenl
= FW_WRITE_SHADOW_RAM_LEN
;
558 buffer
.hdr
.req
.checksum
= FW_DEFAULT_CHECKSUM
;
561 buffer
.length
= cpu_to_be16(sizeof(u16
));
563 buffer
.address
= cpu_to_be32(offset
* 2);
565 status
= ixgbe_host_interface_command(hw
, (u32
*)&buffer
,
567 IXGBE_HI_COMMAND_TIMEOUT
, false);
571 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
572 * @hw: pointer to hardware structure
573 * @offset: offset of word in the EEPROM to write
574 * @data: word write to the EEPROM
576 * Write a 16 bit word to the EEPROM using the hostif.
578 static s32
ixgbe_write_ee_hostif_X550(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
582 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) == 0) {
583 status
= ixgbe_write_ee_hostif_data_X550(hw
, offset
, data
);
584 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
586 hw_dbg(hw
, "write ee hostif failed to get semaphore");
587 status
= IXGBE_ERR_SWFW_SYNC
;
593 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
594 * @hw: pointer to hardware structure
596 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
598 static s32
ixgbe_update_flash_X550(struct ixgbe_hw
*hw
)
601 union ixgbe_hic_hdr2 buffer
;
603 buffer
.req
.cmd
= FW_SHADOW_RAM_DUMP_CMD
;
604 buffer
.req
.buf_lenh
= 0;
605 buffer
.req
.buf_lenl
= FW_SHADOW_RAM_DUMP_LEN
;
606 buffer
.req
.checksum
= FW_DEFAULT_CHECKSUM
;
608 status
= ixgbe_host_interface_command(hw
, (u32
*)&buffer
,
610 IXGBE_HI_COMMAND_TIMEOUT
, false);
614 /** ixgbe_disable_rx_x550 - Disable RX unit
616 * Enables the Rx DMA unit for x550
618 static void ixgbe_disable_rx_x550(struct ixgbe_hw
*hw
)
620 u32 rxctrl
, pfdtxgswc
;
622 struct ixgbe_hic_disable_rxen fw_cmd
;
624 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
625 if (rxctrl
& IXGBE_RXCTRL_RXEN
) {
626 pfdtxgswc
= IXGBE_READ_REG(hw
, IXGBE_PFDTXGSWC
);
627 if (pfdtxgswc
& IXGBE_PFDTXGSWC_VT_LBEN
) {
628 pfdtxgswc
&= ~IXGBE_PFDTXGSWC_VT_LBEN
;
629 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, pfdtxgswc
);
630 hw
->mac
.set_lben
= true;
632 hw
->mac
.set_lben
= false;
635 fw_cmd
.hdr
.cmd
= FW_DISABLE_RXEN_CMD
;
636 fw_cmd
.hdr
.buf_len
= FW_DISABLE_RXEN_LEN
;
637 fw_cmd
.hdr
.checksum
= FW_DEFAULT_CHECKSUM
;
638 fw_cmd
.port_number
= (u8
)hw
->bus
.lan_id
;
640 status
= ixgbe_host_interface_command(hw
, (u32
*)&fw_cmd
,
641 sizeof(struct ixgbe_hic_disable_rxen
),
642 IXGBE_HI_COMMAND_TIMEOUT
, true);
644 /* If we fail - disable RX using register write */
646 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
647 if (rxctrl
& IXGBE_RXCTRL_RXEN
) {
648 rxctrl
&= ~IXGBE_RXCTRL_RXEN
;
649 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
);
655 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
656 * @hw: pointer to hardware structure
658 * After writing EEPROM to shadow RAM using EEWR register, software calculates
659 * checksum and updates the EEPROM and instructs the hardware to update
662 static s32
ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw
*hw
)
667 /* Read the first word from the EEPROM. If this times out or fails, do
668 * not continue or we could be in for a very long wait while every
671 status
= ixgbe_read_ee_hostif_X550(hw
, 0, &checksum
);
673 hw_dbg(hw
, "EEPROM read failed\n");
677 status
= ixgbe_calc_eeprom_checksum_X550(hw
);
681 checksum
= (u16
)(status
& 0xffff);
683 status
= ixgbe_write_ee_hostif_X550(hw
, IXGBE_EEPROM_CHECKSUM
,
688 status
= ixgbe_update_flash_X550(hw
);
693 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
694 * @hw: pointer to hardware structure
695 * @offset: offset of word in the EEPROM to write
696 * @words: number of words
697 * @data: word(s) write to the EEPROM
700 * Write a 16 bit word(s) to the EEPROM using the hostif.
702 static s32
ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw
*hw
,
703 u16 offset
, u16 words
,
709 /* Take semaphore for the entire operation. */
710 status
= hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
712 hw_dbg(hw
, "EEPROM write buffer - semaphore failed\n");
716 for (i
= 0; i
< words
; i
++) {
717 status
= ixgbe_write_ee_hostif_data_X550(hw
, offset
+ i
,
720 hw_dbg(hw
, "Eeprom buffered write failed\n");
725 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
730 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
733 * @hw: pointer to hardware structure
734 * @reg_addr: 32 bit PHY register to write
735 * @device_type: 3 bit device type
736 * @data: Data to write to the register
738 static s32
ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw
*hw
, u32 reg_addr
,
739 u32 device_type
, u32 data
)
741 u32 gssr
= IXGBE_GSSR_PHY1_SM
| IXGBE_GSSR_PHY0_SM
;
745 ret
= hw
->mac
.ops
.acquire_swfw_sync(hw
, gssr
);
749 ret
= ixgbe_iosf_wait(hw
, NULL
);
753 command
= ((reg_addr
<< IXGBE_SB_IOSF_CTRL_ADDR_SHIFT
) |
754 (device_type
<< IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT
));
756 /* Write IOSF control register */
757 IXGBE_WRITE_REG(hw
, IXGBE_SB_IOSF_INDIRECT_CTRL
, command
);
759 /* Write IOSF data register */
760 IXGBE_WRITE_REG(hw
, IXGBE_SB_IOSF_INDIRECT_DATA
, data
);
762 ret
= ixgbe_iosf_wait(hw
, &command
);
764 if ((command
& IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK
) != 0) {
765 error
= (command
& IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK
) >>
766 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT
;
767 hw_dbg(hw
, "Failed to write, error %x\n", error
);
768 return IXGBE_ERR_PHY
;
772 hw
->mac
.ops
.release_swfw_sync(hw
, gssr
);
776 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
777 * @hw: pointer to hardware structure
778 * @speed: the link speed to force
780 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
781 * internal and external PHY at a specific speed, without autonegotiation.
783 static s32
ixgbe_setup_ixfi_x550em(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
)
788 /* Disable AN and force speed to 10G Serial. */
789 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
790 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
791 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
795 reg_val
&= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE
;
796 reg_val
&= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK
;
798 /* Select forced link speed for internal PHY. */
800 case IXGBE_LINK_SPEED_10GB_FULL
:
801 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G
;
803 case IXGBE_LINK_SPEED_1GB_FULL
:
804 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G
;
807 /* Other link speeds are not supported by internal KR PHY. */
808 return IXGBE_ERR_LINK_SETUP
;
811 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
812 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
813 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
817 /* Disable training protocol FSM. */
818 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
819 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw
->bus
.lan_id
),
820 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
824 reg_val
|= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL
;
825 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
826 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw
->bus
.lan_id
),
827 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
831 /* Disable Flex from training TXFFE. */
832 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
833 IXGBE_KRM_DSP_TXFFE_STATE_4(hw
->bus
.lan_id
),
834 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
838 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN
;
839 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN
;
840 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN
;
841 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
842 IXGBE_KRM_DSP_TXFFE_STATE_4(hw
->bus
.lan_id
),
843 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
847 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
848 IXGBE_KRM_DSP_TXFFE_STATE_5(hw
->bus
.lan_id
),
849 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
853 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN
;
854 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN
;
855 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN
;
856 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
857 IXGBE_KRM_DSP_TXFFE_STATE_5(hw
->bus
.lan_id
),
858 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
862 /* Enable override for coefficients. */
863 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
864 IXGBE_KRM_TX_COEFF_CTRL_1(hw
->bus
.lan_id
),
865 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
869 reg_val
|= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN
;
870 reg_val
|= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN
;
871 reg_val
|= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN
;
872 reg_val
|= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN
;
873 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
874 IXGBE_KRM_TX_COEFF_CTRL_1(hw
->bus
.lan_id
),
875 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
879 /* Toggle port SW reset by AN reset. */
880 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
881 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
882 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
886 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART
;
887 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
888 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
889 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
895 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
896 * @hw: pointer to hardware structure
897 * @speed: new link speed
898 * @autoneg_wait_to_complete: true when waiting for completion is needed
900 * Setup internal/external PHY link speed based on link speed, then set
901 * external PHY auto advertised link speed.
903 * Returns error status for any failure
905 static s32
ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw
*hw
,
906 ixgbe_link_speed speed
,
910 ixgbe_link_speed force_speed
;
912 /* Setup internal/external PHY link speed to iXFI (10G), unless
913 * only 1G is auto advertised then setup KX link.
915 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
916 force_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
918 force_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
920 /* If internal link mode is XFI, then setup XFI internal link. */
921 if (!(hw
->phy
.nw_mng_if_sel
& IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE
)) {
922 status
= ixgbe_setup_ixfi_x550em(hw
, &force_speed
);
928 return hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg_wait
);
931 /** ixgbe_check_link_t_X550em - Determine link and speed status
932 * @hw: pointer to hardware structure
933 * @speed: pointer to link speed
934 * @link_up: true when link is up
935 * @link_up_wait_to_complete: bool used to wait for link up or not
937 * Check that both the MAC and X557 external PHY have link.
939 static s32
ixgbe_check_link_t_X550em(struct ixgbe_hw
*hw
,
940 ixgbe_link_speed
*speed
,
942 bool link_up_wait_to_complete
)
947 if (hw
->mac
.ops
.get_media_type(hw
) != ixgbe_media_type_copper
)
948 return IXGBE_ERR_CONFIG
;
950 status
= ixgbe_check_mac_link_generic(hw
, speed
, link_up
,
951 link_up_wait_to_complete
);
953 /* If check link fails or MAC link is not up, then return */
954 if (status
|| !(*link_up
))
957 /* MAC link is up, so check external PHY link.
958 * Read this twice back to back to indicate current status.
960 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_STATUS
,
961 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
966 /* If external PHY link is not up, then indicate link not up */
967 if (!(autoneg_status
& IXGBE_MDIO_AUTO_NEG_LINK_STATUS
))
973 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
974 * @hw: pointer to hardware structure
976 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw
*hw
)
978 struct ixgbe_mac_info
*mac
= &hw
->mac
;
980 switch (mac
->ops
.get_media_type(hw
)) {
981 case ixgbe_media_type_fiber
:
982 /* CS4227 does not support autoneg, so disable the laser control
983 * functions for SFP+ fiber
985 mac
->ops
.disable_tx_laser
= NULL
;
986 mac
->ops
.enable_tx_laser
= NULL
;
987 mac
->ops
.flap_tx_laser
= NULL
;
989 case ixgbe_media_type_copper
:
990 mac
->ops
.setup_link
= ixgbe_setup_mac_link_t_X550em
;
991 mac
->ops
.check_link
= ixgbe_check_link_t_X550em
;
998 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
999 * @hw: pointer to hardware structure
1001 static s32
ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw
*hw
)
1004 u16 reg_slice
, edc_mode
;
1007 switch (hw
->phy
.sfp_type
) {
1008 case ixgbe_sfp_type_unknown
:
1010 case ixgbe_sfp_type_not_present
:
1011 return IXGBE_ERR_SFP_NOT_PRESENT
;
1012 case ixgbe_sfp_type_da_cu_core0
:
1013 case ixgbe_sfp_type_da_cu_core1
:
1014 setup_linear
= true;
1016 case ixgbe_sfp_type_srlr_core0
:
1017 case ixgbe_sfp_type_srlr_core1
:
1018 case ixgbe_sfp_type_da_act_lmt_core0
:
1019 case ixgbe_sfp_type_da_act_lmt_core1
:
1020 case ixgbe_sfp_type_1g_sx_core0
:
1021 case ixgbe_sfp_type_1g_sx_core1
:
1022 setup_linear
= false;
1025 return IXGBE_ERR_SFP_NOT_SUPPORTED
;
1028 ixgbe_init_mac_link_ops_X550em(hw
);
1029 hw
->phy
.ops
.reset
= NULL
;
1031 /* The CS4227 slice address is the base address + the port-pair reg
1032 * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0.
1034 reg_slice
= IXGBE_CS4227_SPARE24_LSB
+ (hw
->bus
.lan_id
<< 12);
1037 edc_mode
= (IXGBE_CS4227_EDC_MODE_CX1
<< 1) | 0x1;
1039 edc_mode
= (IXGBE_CS4227_EDC_MODE_SR
<< 1) | 0x1;
1041 /* Configure CS4227 for connection type. */
1042 ret_val
= hw
->phy
.ops
.write_i2c_combined(hw
, IXGBE_CS4227
, reg_slice
,
1046 ret_val
= hw
->phy
.ops
.write_i2c_combined(hw
, 0x80, reg_slice
,
1052 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1053 * @hw: pointer to hardware structure
1054 * @speed: pointer to link speed
1055 * @autoneg: true when autoneg or autotry is enabled
1057 static s32
ixgbe_get_link_capabilities_X550em(struct ixgbe_hw
*hw
,
1058 ixgbe_link_speed
*speed
,
1062 if (hw
->phy
.media_type
== ixgbe_media_type_fiber
) {
1063 /* CS4227 SFP must not enable auto-negotiation */
1066 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_sx_core0
||
1067 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_sx_core1
) {
1068 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
1072 /* Link capabilities are based on SFP */
1073 if (hw
->phy
.multispeed_fiber
)
1074 *speed
= IXGBE_LINK_SPEED_10GB_FULL
|
1075 IXGBE_LINK_SPEED_1GB_FULL
;
1077 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
1079 *speed
= IXGBE_LINK_SPEED_10GB_FULL
|
1080 IXGBE_LINK_SPEED_1GB_FULL
;
1087 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1088 * @hw: pointer to hardware structure
1089 * @lsc: pointer to boolean flag which indicates whether external Base T
1090 * PHY interrupt is lsc
1092 * Determime if external Base T PHY interrupt cause is high temperature
1093 * failure alarm or link status change.
1095 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1096 * failure alarm, else return PHY access status.
1098 static s32
ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw
*hw
, bool *lsc
)
1105 /* Vendor alarm triggered */
1106 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG
,
1107 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1110 if (status
|| !(reg
& IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN
))
1113 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1114 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG
,
1115 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1118 if (status
|| !(reg
& (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN
|
1119 IXGBE_MDIO_GLOBAL_ALARM_1_INT
)))
1122 /* High temperature failure alarm triggered */
1123 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_ALARM_1
,
1124 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1130 /* If high temperature failure, then return over temp error and exit */
1131 if (reg
& IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL
) {
1132 /* power down the PHY in case the PHY FW didn't already */
1133 ixgbe_set_copper_phy_power(hw
, false);
1134 return IXGBE_ERR_OVERTEMP
;
1137 /* Vendor alarm 2 triggered */
1138 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG
,
1139 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, ®
);
1141 if (status
|| !(reg
& IXGBE_MDIO_GLOBAL_STD_ALM2_INT
))
1144 /* link connect/disconnect event occurred */
1145 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2
,
1146 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, ®
);
1152 if (reg
& IXGBE_MDIO_AUTO_NEG_VEN_LSC
)
1159 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1160 * @hw: pointer to hardware structure
1162 * Enable link status change and temperature failure alarm for the external
1165 * Returns PHY access status
1167 static s32
ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw
*hw
)
1173 /* Clear interrupt flags */
1174 status
= ixgbe_get_lasi_ext_t_x550em(hw
, &lsc
);
1176 /* Enable link status change alarm */
1177 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK
,
1178 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, ®
);
1182 reg
|= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN
;
1184 status
= hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK
,
1185 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, reg
);
1189 /* Enables high temperature failure alarm */
1190 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_INT_MASK
,
1191 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1196 reg
|= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN
;
1198 status
= hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_GLOBAL_INT_MASK
,
1199 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1204 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1205 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK
,
1206 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1211 reg
|= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN
|
1212 IXGBE_MDIO_GLOBAL_ALARM_1_INT
);
1214 status
= hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK
,
1215 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1220 /* Enable chip-wide vendor alarm */
1221 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK
,
1222 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1227 reg
|= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN
;
1229 status
= hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK
,
1230 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1237 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1238 * @hw: pointer to hardware structure
1240 * Handle external Base T PHY interrupt. If high temperature
1241 * failure alarm then return error, else if link status change
1242 * then setup internal/external PHY link
1244 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1245 * failure alarm, else return PHY access status.
1247 static s32
ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw
*hw
)
1249 struct ixgbe_phy_info
*phy
= &hw
->phy
;
1253 status
= ixgbe_get_lasi_ext_t_x550em(hw
, &lsc
);
1258 return phy
->ops
.setup_internal_link(hw
);
1264 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1265 * @hw: pointer to hardware structure
1266 * @speed: link speed
1268 * Configures the integrated KR PHY.
1270 static s32
ixgbe_setup_kr_speed_x550em(struct ixgbe_hw
*hw
,
1271 ixgbe_link_speed speed
)
1276 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
1277 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1278 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
1282 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE
;
1283 reg_val
&= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ
|
1284 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC
);
1285 reg_val
&= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR
|
1286 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX
);
1288 /* Advertise 10G support. */
1289 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
1290 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR
;
1292 /* Advertise 1G support. */
1293 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
1294 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX
;
1296 /* Restart auto-negotiation. */
1297 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART
;
1298 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
1299 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1300 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
1305 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1306 * @hw: pointer to hardware structure
1308 * Configures the integrated KX4 PHY.
1310 static s32
ixgbe_setup_kx4_x550em(struct ixgbe_hw
*hw
)
1315 status
= ixgbe_read_iosf_sb_reg_x550(hw
, IXGBE_KX4_LINK_CNTL_1
,
1316 IXGBE_SB_IOSF_TARGET_KX4_PCS0
+
1317 hw
->bus
.lan_id
, ®_val
);
1321 reg_val
&= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4
|
1322 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX
);
1324 reg_val
|= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE
;
1326 /* Advertise 10G support. */
1327 if (hw
->phy
.autoneg_advertised
& IXGBE_LINK_SPEED_10GB_FULL
)
1328 reg_val
|= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4
;
1330 /* Advertise 1G support. */
1331 if (hw
->phy
.autoneg_advertised
& IXGBE_LINK_SPEED_1GB_FULL
)
1332 reg_val
|= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX
;
1334 /* Restart auto-negotiation. */
1335 reg_val
|= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART
;
1336 status
= ixgbe_write_iosf_sb_reg_x550(hw
, IXGBE_KX4_LINK_CNTL_1
,
1337 IXGBE_SB_IOSF_TARGET_KX4_PCS0
+
1338 hw
->bus
.lan_id
, reg_val
);
1343 /** ixgbe_setup_kr_x550em - Configure the KR PHY.
1344 * @hw: pointer to hardware structure
1346 * Configures the integrated KR PHY.
1348 static s32
ixgbe_setup_kr_x550em(struct ixgbe_hw
*hw
)
1350 return ixgbe_setup_kr_speed_x550em(hw
, hw
->phy
.autoneg_advertised
);
1353 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
1354 * @hw: address of hardware structure
1355 * @link_up: address of boolean to indicate link status
1357 * Returns error code if unable to get link status.
1359 static s32
ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw
*hw
, bool *link_up
)
1366 /* read this twice back to back to indicate current status */
1367 ret
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_STATUS
,
1368 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
1373 ret
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_STATUS
,
1374 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
1379 *link_up
= !!(autoneg_status
& IXGBE_MDIO_AUTO_NEG_LINK_STATUS
);
1384 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
1385 * @hw: point to hardware structure
1387 * Configures the link between the integrated KR PHY and the external X557 PHY
1388 * The driver will call this function when it gets a link status change
1389 * interrupt from the X557 PHY. This function configures the link speed
1390 * between the PHYs to match the link speed of the BASE-T link.
1392 * A return of a non-zero value indicates an error, and the base driver should
1393 * not report link up.
1395 static s32
ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw
*hw
)
1397 ixgbe_link_speed force_speed
;
1402 if (hw
->mac
.ops
.get_media_type(hw
) != ixgbe_media_type_copper
)
1403 return IXGBE_ERR_CONFIG
;
1405 /* If link is not up, then there is no setup necessary so return */
1406 status
= ixgbe_ext_phy_t_x550em_get_link(hw
, &link_up
);
1413 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT
,
1414 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
1419 /* If link is not still up, then no setup is necessary so return */
1420 status
= ixgbe_ext_phy_t_x550em_get_link(hw
, &link_up
);
1427 /* clear everything but the speed and duplex bits */
1428 speed
&= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK
;
1431 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL
:
1432 force_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
1434 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL
:
1435 force_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
1438 /* Internal PHY does not support anything else */
1439 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
1442 return ixgbe_setup_ixfi_x550em(hw
, &force_speed
);
1445 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
1446 * @hw: pointer to hardware structure
1448 static s32
ixgbe_reset_phy_t_X550em(struct ixgbe_hw
*hw
)
1452 status
= ixgbe_reset_phy_generic(hw
);
1457 /* Configure Link Status Alarm and Temperature Threshold interrupts */
1458 return ixgbe_enable_lasi_ext_t_x550em(hw
);
1461 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
1462 * @hw: pointer to hardware structure
1464 * Initialize any function pointers that were not able to be
1465 * set during init_shared_code because the PHY/SFP type was
1466 * not known. Perform the SFP init if necessary.
1468 static s32
ixgbe_init_phy_ops_X550em(struct ixgbe_hw
*hw
)
1470 struct ixgbe_phy_info
*phy
= &hw
->phy
;
1471 ixgbe_link_speed speed
;
1474 hw
->mac
.ops
.set_lan_id(hw
);
1476 if (hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) {
1477 phy
->phy_semaphore_mask
= IXGBE_GSSR_SHARED_I2C_SM
;
1478 ixgbe_setup_mux_ctl(hw
);
1480 /* Save NW management interface connected on board. This is used
1481 * to determine internal PHY mode.
1483 phy
->nw_mng_if_sel
= IXGBE_READ_REG(hw
, IXGBE_NW_MNG_IF_SEL
);
1485 /* If internal PHY mode is KR, then initialize KR link */
1486 if (phy
->nw_mng_if_sel
& IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE
) {
1487 speed
= IXGBE_LINK_SPEED_10GB_FULL
|
1488 IXGBE_LINK_SPEED_1GB_FULL
;
1489 ret_val
= ixgbe_setup_kr_speed_x550em(hw
, speed
);
1493 /* Identify the PHY or SFP module */
1494 ret_val
= phy
->ops
.identify(hw
);
1496 /* Setup function pointers based on detected hardware */
1497 ixgbe_init_mac_link_ops_X550em(hw
);
1498 if (phy
->sfp_type
!= ixgbe_sfp_type_unknown
)
1499 phy
->ops
.reset
= NULL
;
1501 /* Set functions pointers based on phy type */
1502 switch (hw
->phy
.type
) {
1503 case ixgbe_phy_x550em_kx4
:
1504 phy
->ops
.setup_link
= ixgbe_setup_kx4_x550em
;
1505 phy
->ops
.read_reg
= ixgbe_read_phy_reg_x550em
;
1506 phy
->ops
.write_reg
= ixgbe_write_phy_reg_x550em
;
1508 case ixgbe_phy_x550em_kr
:
1509 phy
->ops
.setup_link
= ixgbe_setup_kr_x550em
;
1510 phy
->ops
.read_reg
= ixgbe_read_phy_reg_x550em
;
1511 phy
->ops
.write_reg
= ixgbe_write_phy_reg_x550em
;
1513 case ixgbe_phy_x550em_ext_t
:
1514 /* Save NW management interface connected on board. This is used
1515 * to determine internal PHY mode
1517 phy
->nw_mng_if_sel
= IXGBE_READ_REG(hw
, IXGBE_NW_MNG_IF_SEL
);
1519 /* If internal link mode is XFI, then setup iXFI internal link,
1520 * else setup KR now.
1522 if (!(phy
->nw_mng_if_sel
& IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE
)) {
1523 phy
->ops
.setup_internal_link
=
1524 ixgbe_setup_internal_phy_t_x550em
;
1526 speed
= IXGBE_LINK_SPEED_10GB_FULL
|
1527 IXGBE_LINK_SPEED_1GB_FULL
;
1528 ret_val
= ixgbe_setup_kr_speed_x550em(hw
, speed
);
1531 phy
->ops
.handle_lasi
= ixgbe_handle_lasi_ext_t_x550em
;
1532 phy
->ops
.reset
= ixgbe_reset_phy_t_X550em
;
1541 /** ixgbe_get_media_type_X550em - Get media type
1542 * @hw: pointer to hardware structure
1544 * Returns the media type (fiber, copper, backplane)
1547 static enum ixgbe_media_type
ixgbe_get_media_type_X550em(struct ixgbe_hw
*hw
)
1549 enum ixgbe_media_type media_type
;
1551 /* Detect if there is a copper PHY attached. */
1552 switch (hw
->device_id
) {
1553 case IXGBE_DEV_ID_X550EM_X_KR
:
1554 case IXGBE_DEV_ID_X550EM_X_KX4
:
1555 media_type
= ixgbe_media_type_backplane
;
1557 case IXGBE_DEV_ID_X550EM_X_SFP
:
1558 media_type
= ixgbe_media_type_fiber
;
1560 case IXGBE_DEV_ID_X550EM_X_1G_T
:
1561 case IXGBE_DEV_ID_X550EM_X_10G_T
:
1562 media_type
= ixgbe_media_type_copper
;
1565 media_type
= ixgbe_media_type_unknown
;
1571 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
1572 ** @hw: pointer to hardware structure
1574 static s32
ixgbe_init_ext_t_x550em(struct ixgbe_hw
*hw
)
1579 status
= hw
->phy
.ops
.read_reg(hw
,
1580 IXGBE_MDIO_TX_VENDOR_ALARMS_3
,
1581 IXGBE_MDIO_PMA_PMD_DEV_TYPE
,
1586 /* If PHY FW reset completed bit is set then this is the first
1587 * SW instance after a power on so the PHY FW must be un-stalled.
1589 if (reg
& IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK
) {
1590 status
= hw
->phy
.ops
.read_reg(hw
,
1591 IXGBE_MDIO_GLOBAL_RES_PR_10
,
1592 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1597 reg
&= ~IXGBE_MDIO_POWER_UP_STALL
;
1599 status
= hw
->phy
.ops
.write_reg(hw
,
1600 IXGBE_MDIO_GLOBAL_RES_PR_10
,
1601 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1610 /** ixgbe_reset_hw_X550em - Perform hardware reset
1611 ** @hw: pointer to hardware structure
1613 ** Resets the hardware by resetting the transmit and receive units, masks
1614 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1617 static s32
ixgbe_reset_hw_X550em(struct ixgbe_hw
*hw
)
1619 ixgbe_link_speed link_speed
;
1624 bool link_up
= false;
1626 /* Call adapter stop to disable Tx/Rx and clear interrupts */
1627 status
= hw
->mac
.ops
.stop_adapter(hw
);
1631 /* flush pending Tx transactions */
1632 ixgbe_clear_tx_pending(hw
);
1634 /* PHY ops must be identified and initialized prior to reset */
1636 /* Identify PHY and related function pointers */
1637 status
= hw
->phy
.ops
.init(hw
);
1639 /* start the external PHY */
1640 if (hw
->phy
.type
== ixgbe_phy_x550em_ext_t
) {
1641 status
= ixgbe_init_ext_t_x550em(hw
);
1646 /* Setup SFP module if there is one present. */
1647 if (hw
->phy
.sfp_setup_needed
) {
1648 status
= hw
->mac
.ops
.setup_sfp(hw
);
1649 hw
->phy
.sfp_setup_needed
= false;
1653 if (!hw
->phy
.reset_disable
&& hw
->phy
.ops
.reset
)
1654 hw
->phy
.ops
.reset(hw
);
1657 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
1658 * If link reset is used when link is up, it might reset the PHY when
1659 * mng is using it. If link is down or the flag to force full link
1660 * reset is set, then perform link reset.
1662 ctrl
= IXGBE_CTRL_LNK_RST
;
1664 if (!hw
->force_full_reset
) {
1665 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
1667 ctrl
= IXGBE_CTRL_RST
;
1670 ctrl
|= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
1671 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
1672 IXGBE_WRITE_FLUSH(hw
);
1674 /* Poll for reset bit to self-clear meaning reset is complete */
1675 for (i
= 0; i
< 10; i
++) {
1677 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
1678 if (!(ctrl
& IXGBE_CTRL_RST_MASK
))
1682 if (ctrl
& IXGBE_CTRL_RST_MASK
) {
1683 status
= IXGBE_ERR_RESET_FAILED
;
1684 hw_dbg(hw
, "Reset polling failed to complete.\n");
1689 /* Double resets are required for recovery from certain error
1690 * clear the multicast table. Also reset num_rar_entries to 128,
1691 * since we modify this value when programming the SAN MAC address.
1693 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
1694 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
1698 /* Store the permanent mac address */
1699 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
1701 /* Store MAC address from RAR0, clear receive address registers, and
1702 * clear the multicast table. Also reset num_rar_entries to 128,
1703 * since we modify this value when programming the SAN MAC address.
1705 hw
->mac
.num_rar_entries
= 128;
1706 hw
->mac
.ops
.init_rx_addrs(hw
);
1708 if (hw
->device_id
== IXGBE_DEV_ID_X550EM_X_10G_T
) {
1709 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
1710 hlreg0
&= ~IXGBE_HLREG0_MDCSPD
;
1711 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
1714 if (hw
->device_id
== IXGBE_DEV_ID_X550EM_X_SFP
)
1715 ixgbe_setup_mux_ctl(hw
);
1720 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
1722 * @hw: pointer to hardware structure
1723 * @enable: enable or disable switch for Ethertype anti-spoofing
1724 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1726 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw
*hw
,
1727 bool enable
, int vf
)
1729 int vf_target_reg
= vf
>> 3;
1730 int vf_target_shift
= vf
% 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT
;
1733 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
1735 pfvfspoof
|= (1 << vf_target_shift
);
1737 pfvfspoof
&= ~(1 << vf_target_shift
);
1739 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);
1742 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
1743 * @hw: pointer to hardware structure
1744 * @enable: enable or disable source address pruning
1745 * @pool: Rx pool to set source address pruning for
1747 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw
*hw
,
1753 /* max rx pool is 63 */
1757 pfflp
= (u64
)IXGBE_READ_REG(hw
, IXGBE_PFFLPL
);
1758 pfflp
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_PFFLPH
) << 32;
1761 pfflp
|= (1ULL << pool
);
1763 pfflp
&= ~(1ULL << pool
);
1765 IXGBE_WRITE_REG(hw
, IXGBE_PFFLPL
, (u32
)pfflp
);
1766 IXGBE_WRITE_REG(hw
, IXGBE_PFFLPH
, (u32
)(pfflp
>> 32));
1769 #define X550_COMMON_MAC \
1770 .init_hw = &ixgbe_init_hw_generic, \
1771 .start_hw = &ixgbe_start_hw_X540, \
1772 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
1773 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
1774 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
1775 .get_device_caps = &ixgbe_get_device_caps_generic, \
1776 .stop_adapter = &ixgbe_stop_adapter_generic, \
1777 .get_bus_info = &ixgbe_get_bus_info_generic, \
1778 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
1779 .read_analog_reg8 = NULL, \
1780 .write_analog_reg8 = NULL, \
1781 .set_rxpba = &ixgbe_set_rxpba_generic, \
1782 .check_link = &ixgbe_check_mac_link_generic, \
1783 .led_on = &ixgbe_led_on_generic, \
1784 .led_off = &ixgbe_led_off_generic, \
1785 .blink_led_start = &ixgbe_blink_led_start_X540, \
1786 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
1787 .set_rar = &ixgbe_set_rar_generic, \
1788 .clear_rar = &ixgbe_clear_rar_generic, \
1789 .set_vmdq = &ixgbe_set_vmdq_generic, \
1790 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
1791 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
1792 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
1793 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
1794 .enable_mc = &ixgbe_enable_mc_generic, \
1795 .disable_mc = &ixgbe_disable_mc_generic, \
1796 .clear_vfta = &ixgbe_clear_vfta_generic, \
1797 .set_vfta = &ixgbe_set_vfta_generic, \
1798 .fc_enable = &ixgbe_fc_enable_generic, \
1799 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \
1800 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
1801 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
1802 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
1803 .set_source_address_pruning = \
1804 &ixgbe_set_source_address_pruning_X550, \
1805 .set_ethertype_anti_spoofing = \
1806 &ixgbe_set_ethertype_anti_spoofing_X550, \
1807 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540, \
1808 .release_swfw_sync = &ixgbe_release_swfw_sync_X540, \
1809 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
1810 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
1811 .get_thermal_sensor_data = NULL, \
1812 .init_thermal_sensor_thresh = NULL, \
1813 .prot_autoc_read = &prot_autoc_read_generic, \
1814 .prot_autoc_write = &prot_autoc_write_generic, \
1815 .enable_rx = &ixgbe_enable_rx_generic, \
1816 .disable_rx = &ixgbe_disable_rx_x550, \
1818 static struct ixgbe_mac_operations mac_ops_X550 = {
1820 .reset_hw
= &ixgbe_reset_hw_X540
,
1821 .get_media_type
= &ixgbe_get_media_type_X540
,
1822 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
1823 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
1824 .setup_link
= &ixgbe_setup_mac_link_X540
,
1825 .get_link_capabilities
= &ixgbe_get_copper_link_capabilities_generic
,
1829 static struct ixgbe_mac_operations mac_ops_X550EM_x
= {
1831 .reset_hw
= &ixgbe_reset_hw_X550em
,
1832 .get_media_type
= &ixgbe_get_media_type_X550em
,
1833 .get_san_mac_addr
= NULL
,
1834 .get_wwn_prefix
= NULL
,
1835 .setup_link
= NULL
, /* defined later */
1836 .get_link_capabilities
= &ixgbe_get_link_capabilities_X550em
,
1837 .setup_sfp
= ixgbe_setup_sfp_modules_X550em
,
1841 #define X550_COMMON_EEP \
1842 .read = &ixgbe_read_ee_hostif_X550, \
1843 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
1844 .write = &ixgbe_write_ee_hostif_X550, \
1845 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
1846 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
1847 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
1848 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
1850 static struct ixgbe_eeprom_operations eeprom_ops_X550 = {
1852 .init_params
= &ixgbe_init_eeprom_params_X550
,
1855 static struct ixgbe_eeprom_operations eeprom_ops_X550EM_x
= {
1857 .init_params
= &ixgbe_init_eeprom_params_X540
,
1860 #define X550_COMMON_PHY \
1861 .identify_sfp = &ixgbe_identify_module_generic, \
1863 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
1864 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
1865 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
1866 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
1867 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
1868 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
1869 .read_reg = &ixgbe_read_phy_reg_generic, \
1870 .write_reg = &ixgbe_write_phy_reg_generic, \
1871 .setup_link = &ixgbe_setup_phy_link_generic, \
1872 .set_phy_power = NULL, \
1873 .check_overtemp = &ixgbe_tn_check_overtemp, \
1874 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
1876 static struct ixgbe_phy_operations phy_ops_X550
= {
1879 .identify
= &ixgbe_identify_phy_generic
,
1880 .read_i2c_combined
= &ixgbe_read_i2c_combined_generic
,
1881 .write_i2c_combined
= &ixgbe_write_i2c_combined_generic
,
1884 static struct ixgbe_phy_operations phy_ops_X550EM_x
= {
1886 .init
= &ixgbe_init_phy_ops_X550em
,
1887 .identify
= &ixgbe_identify_phy_x550em
,
1890 static const u32 ixgbe_mvals_X550
[IXGBE_MVALS_IDX_LIMIT
] = {
1891 IXGBE_MVALS_INIT(X550
)
1894 static const u32 ixgbe_mvals_X550EM_x
[IXGBE_MVALS_IDX_LIMIT
] = {
1895 IXGBE_MVALS_INIT(X550EM_x
)
1898 struct ixgbe_info ixgbe_X550_info
= {
1899 .mac
= ixgbe_mac_X550
,
1900 .get_invariants
= &ixgbe_get_invariants_X540
,
1901 .mac_ops
= &mac_ops_X550
,
1902 .eeprom_ops
= &eeprom_ops_X550
,
1903 .phy_ops
= &phy_ops_X550
,
1904 .mbx_ops
= &mbx_ops_generic
,
1905 .mvals
= ixgbe_mvals_X550
,
1908 struct ixgbe_info ixgbe_X550EM_x_info
= {
1909 .mac
= ixgbe_mac_X550EM_x
,
1910 .get_invariants
= &ixgbe_get_invariants_X550_x
,
1911 .mac_ops
= &mac_ops_X550EM_x
,
1912 .eeprom_ops
= &eeprom_ops_X550EM_x
,
1913 .phy_ops
= &phy_ops_X550EM_x
,
1914 .mbx_ops
= &mbx_ops_generic
,
1915 .mvals
= ixgbe_mvals_X550EM_x
,