1 /*******************************************************************************
3 * Intel 10 Gigabit PCI Express Linux driver
4 * Copyright(c) 1999 - 2016 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
18 * Contact Information:
19 * Linux NICS <linux.nics@intel.com>
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 ******************************************************************************/
24 #include "ixgbe_x540.h"
25 #include "ixgbe_type.h"
26 #include "ixgbe_common.h"
27 #include "ixgbe_phy.h"
29 static s32
ixgbe_setup_kr_speed_x550em(struct ixgbe_hw
*, ixgbe_link_speed
);
30 static s32
ixgbe_setup_fc_x550em(struct ixgbe_hw
*);
32 static s32
ixgbe_get_invariants_X550_x(struct ixgbe_hw
*hw
)
34 struct ixgbe_mac_info
*mac
= &hw
->mac
;
35 struct ixgbe_phy_info
*phy
= &hw
->phy
;
37 /* Start with X540 invariants, since so simular */
38 ixgbe_get_invariants_X540(hw
);
40 if (mac
->ops
.get_media_type(hw
) != ixgbe_media_type_copper
)
41 phy
->ops
.set_phy_power
= NULL
;
46 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
47 * @hw: pointer to hardware structure
49 static void ixgbe_setup_mux_ctl(struct ixgbe_hw
*hw
)
51 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
54 esdp
&= ~(IXGBE_ESDP_SDP1_NATIVE
| IXGBE_ESDP_SDP1
);
55 esdp
|= IXGBE_ESDP_SDP1_DIR
;
57 esdp
&= ~(IXGBE_ESDP_SDP0_NATIVE
| IXGBE_ESDP_SDP0_DIR
);
58 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp
);
59 IXGBE_WRITE_FLUSH(hw
);
63 * ixgbe_read_cs4227 - Read CS4227 register
64 * @hw: pointer to hardware structure
65 * @reg: register number to write
66 * @value: pointer to receive value read
70 static s32
ixgbe_read_cs4227(struct ixgbe_hw
*hw
, u16 reg
, u16
*value
)
72 return hw
->phy
.ops
.read_i2c_combined_unlocked(hw
, IXGBE_CS4227
, reg
,
77 * ixgbe_write_cs4227 - Write CS4227 register
78 * @hw: pointer to hardware structure
79 * @reg: register number to write
80 * @value: value to write to register
84 static s32
ixgbe_write_cs4227(struct ixgbe_hw
*hw
, u16 reg
, u16 value
)
86 return hw
->phy
.ops
.write_i2c_combined_unlocked(hw
, IXGBE_CS4227
, reg
,
91 * ixgbe_read_pe - Read register from port expander
92 * @hw: pointer to hardware structure
93 * @reg: register number to read
94 * @value: pointer to receive read value
98 static s32
ixgbe_read_pe(struct ixgbe_hw
*hw
, u8 reg
, u8
*value
)
102 status
= ixgbe_read_i2c_byte_generic_unlocked(hw
, reg
, IXGBE_PE
, value
);
104 hw_err(hw
, "port expander access failed with %d\n", status
);
109 * ixgbe_write_pe - Write register to port expander
110 * @hw: pointer to hardware structure
111 * @reg: register number to write
112 * @value: value to write
114 * Returns status code
116 static s32
ixgbe_write_pe(struct ixgbe_hw
*hw
, u8 reg
, u8 value
)
120 status
= ixgbe_write_i2c_byte_generic_unlocked(hw
, reg
, IXGBE_PE
,
123 hw_err(hw
, "port expander access failed with %d\n", status
);
128 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
129 * @hw: pointer to hardware structure
131 * This function assumes that the caller has acquired the proper semaphore.
134 static s32
ixgbe_reset_cs4227(struct ixgbe_hw
*hw
)
141 /* Trigger hard reset. */
142 status
= ixgbe_read_pe(hw
, IXGBE_PE_OUTPUT
, ®
);
145 reg
|= IXGBE_PE_BIT1
;
146 status
= ixgbe_write_pe(hw
, IXGBE_PE_OUTPUT
, reg
);
150 status
= ixgbe_read_pe(hw
, IXGBE_PE_CONFIG
, ®
);
153 reg
&= ~IXGBE_PE_BIT1
;
154 status
= ixgbe_write_pe(hw
, IXGBE_PE_CONFIG
, reg
);
158 status
= ixgbe_read_pe(hw
, IXGBE_PE_OUTPUT
, ®
);
161 reg
&= ~IXGBE_PE_BIT1
;
162 status
= ixgbe_write_pe(hw
, IXGBE_PE_OUTPUT
, reg
);
166 usleep_range(IXGBE_CS4227_RESET_HOLD
, IXGBE_CS4227_RESET_HOLD
+ 100);
168 status
= ixgbe_read_pe(hw
, IXGBE_PE_OUTPUT
, ®
);
171 reg
|= IXGBE_PE_BIT1
;
172 status
= ixgbe_write_pe(hw
, IXGBE_PE_OUTPUT
, reg
);
176 /* Wait for the reset to complete. */
177 msleep(IXGBE_CS4227_RESET_DELAY
);
178 for (retry
= 0; retry
< IXGBE_CS4227_RETRIES
; retry
++) {
179 status
= ixgbe_read_cs4227(hw
, IXGBE_CS4227_EFUSE_STATUS
,
181 if (!status
&& value
== IXGBE_CS4227_EEPROM_LOAD_OK
)
183 msleep(IXGBE_CS4227_CHECK_DELAY
);
185 if (retry
== IXGBE_CS4227_RETRIES
) {
186 hw_err(hw
, "CS4227 reset did not complete\n");
187 return IXGBE_ERR_PHY
;
190 status
= ixgbe_read_cs4227(hw
, IXGBE_CS4227_EEPROM_STATUS
, &value
);
191 if (status
|| !(value
& IXGBE_CS4227_EEPROM_LOAD_OK
)) {
192 hw_err(hw
, "CS4227 EEPROM did not load successfully\n");
193 return IXGBE_ERR_PHY
;
200 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
201 * @hw: pointer to hardware structure
203 static void ixgbe_check_cs4227(struct ixgbe_hw
*hw
)
205 u32 swfw_mask
= hw
->phy
.phy_semaphore_mask
;
210 for (retry
= 0; retry
< IXGBE_CS4227_RETRIES
; retry
++) {
211 status
= hw
->mac
.ops
.acquire_swfw_sync(hw
, swfw_mask
);
213 hw_err(hw
, "semaphore failed with %d\n", status
);
214 msleep(IXGBE_CS4227_CHECK_DELAY
);
218 /* Get status of reset flow. */
219 status
= ixgbe_read_cs4227(hw
, IXGBE_CS4227_SCRATCH
, &value
);
220 if (!status
&& value
== IXGBE_CS4227_RESET_COMPLETE
)
223 if (status
|| value
!= IXGBE_CS4227_RESET_PENDING
)
226 /* Reset is pending. Wait and check again. */
227 hw
->mac
.ops
.release_swfw_sync(hw
, swfw_mask
);
228 msleep(IXGBE_CS4227_CHECK_DELAY
);
230 /* If still pending, assume other instance failed. */
231 if (retry
== IXGBE_CS4227_RETRIES
) {
232 status
= hw
->mac
.ops
.acquire_swfw_sync(hw
, swfw_mask
);
234 hw_err(hw
, "semaphore failed with %d\n", status
);
239 /* Reset the CS4227. */
240 status
= ixgbe_reset_cs4227(hw
);
242 hw_err(hw
, "CS4227 reset failed: %d", status
);
246 /* Reset takes so long, temporarily release semaphore in case the
247 * other driver instance is waiting for the reset indication.
249 ixgbe_write_cs4227(hw
, IXGBE_CS4227_SCRATCH
,
250 IXGBE_CS4227_RESET_PENDING
);
251 hw
->mac
.ops
.release_swfw_sync(hw
, swfw_mask
);
252 usleep_range(10000, 12000);
253 status
= hw
->mac
.ops
.acquire_swfw_sync(hw
, swfw_mask
);
255 hw_err(hw
, "semaphore failed with %d", status
);
259 /* Record completion for next time. */
260 status
= ixgbe_write_cs4227(hw
, IXGBE_CS4227_SCRATCH
,
261 IXGBE_CS4227_RESET_COMPLETE
);
264 hw
->mac
.ops
.release_swfw_sync(hw
, swfw_mask
);
265 msleep(hw
->eeprom
.semaphore_delay
);
268 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
269 * @hw: pointer to hardware structure
273 static s32
ixgbe_identify_phy_x550em(struct ixgbe_hw
*hw
)
275 switch (hw
->device_id
) {
276 case IXGBE_DEV_ID_X550EM_A_SFP
:
278 hw
->phy
.phy_semaphore_mask
= IXGBE_GSSR_PHY1_SM
;
280 hw
->phy
.phy_semaphore_mask
= IXGBE_GSSR_PHY0_SM
;
281 return ixgbe_identify_module_generic(hw
);
282 case IXGBE_DEV_ID_X550EM_X_SFP
:
283 /* set up for CS4227 usage */
284 hw
->phy
.phy_semaphore_mask
= IXGBE_GSSR_SHARED_I2C_SM
;
285 ixgbe_setup_mux_ctl(hw
);
286 ixgbe_check_cs4227(hw
);
288 case IXGBE_DEV_ID_X550EM_A_SFP_N
:
289 return ixgbe_identify_module_generic(hw
);
290 case IXGBE_DEV_ID_X550EM_X_KX4
:
291 hw
->phy
.type
= ixgbe_phy_x550em_kx4
;
293 case IXGBE_DEV_ID_X550EM_X_KR
:
294 case IXGBE_DEV_ID_X550EM_A_KR
:
295 case IXGBE_DEV_ID_X550EM_A_KR_L
:
296 hw
->phy
.type
= ixgbe_phy_x550em_kr
;
298 case IXGBE_DEV_ID_X550EM_A_10G_T
:
300 hw
->phy
.phy_semaphore_mask
= IXGBE_GSSR_PHY1_SM
;
302 hw
->phy
.phy_semaphore_mask
= IXGBE_GSSR_PHY0_SM
;
304 case IXGBE_DEV_ID_X550EM_X_1G_T
:
305 case IXGBE_DEV_ID_X550EM_X_10G_T
:
306 return ixgbe_identify_phy_generic(hw
);
313 static s32
ixgbe_read_phy_reg_x550em(struct ixgbe_hw
*hw
, u32 reg_addr
,
314 u32 device_type
, u16
*phy_data
)
316 return IXGBE_NOT_IMPLEMENTED
;
319 static s32
ixgbe_write_phy_reg_x550em(struct ixgbe_hw
*hw
, u32 reg_addr
,
320 u32 device_type
, u16 phy_data
)
322 return IXGBE_NOT_IMPLEMENTED
;
325 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
326 * @hw: pointer to hardware structure
328 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
329 * ixgbe_hw struct in order to set up EEPROM access.
331 static s32
ixgbe_init_eeprom_params_X550(struct ixgbe_hw
*hw
)
333 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
337 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
338 eeprom
->semaphore_delay
= 10;
339 eeprom
->type
= ixgbe_flash
;
341 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC(hw
));
342 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
343 IXGBE_EEC_SIZE_SHIFT
);
344 eeprom
->word_size
= BIT(eeprom_size
+
345 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
347 hw_dbg(hw
, "Eeprom params: type = %d, size = %d\n",
348 eeprom
->type
, eeprom
->word_size
);
355 * ixgbe_iosf_wait - Wait for IOSF command completion
356 * @hw: pointer to hardware structure
357 * @ctrl: pointer to location to receive final IOSF control value
359 * Return: failing status on timeout
361 * Note: ctrl can be NULL if the IOSF control register value is not needed
363 static s32
ixgbe_iosf_wait(struct ixgbe_hw
*hw
, u32
*ctrl
)
367 /* Check every 10 usec to see if the address cycle completed.
368 * The SB IOSF BUSY bit will clear when the operation is
371 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
372 command
= IXGBE_READ_REG(hw
, IXGBE_SB_IOSF_INDIRECT_CTRL
);
373 if (!(command
& IXGBE_SB_IOSF_CTRL_BUSY
))
379 if (i
== IXGBE_MDIO_COMMAND_TIMEOUT
) {
380 hw_dbg(hw
, "IOSF wait timed out\n");
381 return IXGBE_ERR_PHY
;
387 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
389 * @hw: pointer to hardware structure
390 * @reg_addr: 32 bit PHY register to write
391 * @device_type: 3 bit device type
392 * @phy_data: Pointer to read data from the register
394 static s32
ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw
*hw
, u32 reg_addr
,
395 u32 device_type
, u32
*data
)
397 u32 gssr
= IXGBE_GSSR_PHY1_SM
| IXGBE_GSSR_PHY0_SM
;
401 ret
= hw
->mac
.ops
.acquire_swfw_sync(hw
, gssr
);
405 ret
= ixgbe_iosf_wait(hw
, NULL
);
409 command
= ((reg_addr
<< IXGBE_SB_IOSF_CTRL_ADDR_SHIFT
) |
410 (device_type
<< IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT
));
412 /* Write IOSF control register */
413 IXGBE_WRITE_REG(hw
, IXGBE_SB_IOSF_INDIRECT_CTRL
, command
);
415 ret
= ixgbe_iosf_wait(hw
, &command
);
417 if ((command
& IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK
) != 0) {
418 error
= (command
& IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK
) >>
419 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT
;
420 hw_dbg(hw
, "Failed to read, error %x\n", error
);
421 return IXGBE_ERR_PHY
;
425 *data
= IXGBE_READ_REG(hw
, IXGBE_SB_IOSF_INDIRECT_DATA
);
428 hw
->mac
.ops
.release_swfw_sync(hw
, gssr
);
433 * ixgbe_get_phy_token - Get the token for shared PHY access
434 * @hw: Pointer to hardware structure
436 static s32
ixgbe_get_phy_token(struct ixgbe_hw
*hw
)
438 struct ixgbe_hic_phy_token_req token_cmd
;
441 token_cmd
.hdr
.cmd
= FW_PHY_TOKEN_REQ_CMD
;
442 token_cmd
.hdr
.buf_len
= FW_PHY_TOKEN_REQ_LEN
;
443 token_cmd
.hdr
.cmd_or_resp
.cmd_resv
= 0;
444 token_cmd
.hdr
.checksum
= FW_DEFAULT_CHECKSUM
;
445 token_cmd
.port_number
= hw
->bus
.lan_id
;
446 token_cmd
.command_type
= FW_PHY_TOKEN_REQ
;
448 status
= ixgbe_host_interface_command(hw
, &token_cmd
, sizeof(token_cmd
),
449 IXGBE_HI_COMMAND_TIMEOUT
,
453 if (token_cmd
.hdr
.cmd_or_resp
.ret_status
== FW_PHY_TOKEN_OK
)
455 if (token_cmd
.hdr
.cmd_or_resp
.ret_status
!= FW_PHY_TOKEN_RETRY
)
456 return IXGBE_ERR_FW_RESP_INVALID
;
458 return IXGBE_ERR_TOKEN_RETRY
;
462 * ixgbe_put_phy_token - Put the token for shared PHY access
463 * @hw: Pointer to hardware structure
465 static s32
ixgbe_put_phy_token(struct ixgbe_hw
*hw
)
467 struct ixgbe_hic_phy_token_req token_cmd
;
470 token_cmd
.hdr
.cmd
= FW_PHY_TOKEN_REQ_CMD
;
471 token_cmd
.hdr
.buf_len
= FW_PHY_TOKEN_REQ_LEN
;
472 token_cmd
.hdr
.cmd_or_resp
.cmd_resv
= 0;
473 token_cmd
.hdr
.checksum
= FW_DEFAULT_CHECKSUM
;
474 token_cmd
.port_number
= hw
->bus
.lan_id
;
475 token_cmd
.command_type
= FW_PHY_TOKEN_REL
;
477 status
= ixgbe_host_interface_command(hw
, &token_cmd
, sizeof(token_cmd
),
478 IXGBE_HI_COMMAND_TIMEOUT
,
482 if (token_cmd
.hdr
.cmd_or_resp
.ret_status
== FW_PHY_TOKEN_OK
)
484 return IXGBE_ERR_FW_RESP_INVALID
;
488 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
489 * @hw: pointer to hardware structure
490 * @reg_addr: 32 bit PHY register to write
491 * @device_type: 3 bit device type
492 * @data: Data to write to the register
494 static s32
ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw
*hw
, u32 reg_addr
,
495 __always_unused u32 device_type
,
498 struct ixgbe_hic_internal_phy_req write_cmd
;
500 memset(&write_cmd
, 0, sizeof(write_cmd
));
501 write_cmd
.hdr
.cmd
= FW_INT_PHY_REQ_CMD
;
502 write_cmd
.hdr
.buf_len
= FW_INT_PHY_REQ_LEN
;
503 write_cmd
.hdr
.checksum
= FW_DEFAULT_CHECKSUM
;
504 write_cmd
.port_number
= hw
->bus
.lan_id
;
505 write_cmd
.command_type
= FW_INT_PHY_REQ_WRITE
;
506 write_cmd
.address
= cpu_to_be16(reg_addr
);
507 write_cmd
.write_data
= cpu_to_be32(data
);
509 return ixgbe_host_interface_command(hw
, &write_cmd
, sizeof(write_cmd
),
510 IXGBE_HI_COMMAND_TIMEOUT
, false);
514 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
515 * @hw: pointer to hardware structure
516 * @reg_addr: 32 bit PHY register to write
517 * @device_type: 3 bit device type
518 * @data: Pointer to read data from the register
520 static s32
ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw
*hw
, u32 reg_addr
,
521 __always_unused u32 device_type
,
525 struct ixgbe_hic_internal_phy_req cmd
;
526 struct ixgbe_hic_internal_phy_resp rsp
;
530 memset(&hic
, 0, sizeof(hic
));
531 hic
.cmd
.hdr
.cmd
= FW_INT_PHY_REQ_CMD
;
532 hic
.cmd
.hdr
.buf_len
= FW_INT_PHY_REQ_LEN
;
533 hic
.cmd
.hdr
.checksum
= FW_DEFAULT_CHECKSUM
;
534 hic
.cmd
.port_number
= hw
->bus
.lan_id
;
535 hic
.cmd
.command_type
= FW_INT_PHY_REQ_READ
;
536 hic
.cmd
.address
= cpu_to_be16(reg_addr
);
538 status
= ixgbe_host_interface_command(hw
, &hic
.cmd
, sizeof(hic
.cmd
),
539 IXGBE_HI_COMMAND_TIMEOUT
, true);
541 /* Extract the register value from the response. */
542 *data
= be32_to_cpu(hic
.rsp
.read_data
);
547 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
548 * command assuming that the semaphore is already obtained.
549 * @hw: pointer to hardware structure
550 * @offset: offset of word in the EEPROM to read
551 * @data: word read from the EEPROM
553 * Reads a 16 bit word from the EEPROM using the hostif.
555 static s32
ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw
*hw
, u16 offset
,
559 struct ixgbe_hic_read_shadow_ram buffer
;
561 buffer
.hdr
.req
.cmd
= FW_READ_SHADOW_RAM_CMD
;
562 buffer
.hdr
.req
.buf_lenh
= 0;
563 buffer
.hdr
.req
.buf_lenl
= FW_READ_SHADOW_RAM_LEN
;
564 buffer
.hdr
.req
.checksum
= FW_DEFAULT_CHECKSUM
;
566 /* convert offset from words to bytes */
567 buffer
.address
= cpu_to_be32(offset
* 2);
569 buffer
.length
= cpu_to_be16(sizeof(u16
));
571 status
= ixgbe_host_interface_command(hw
, &buffer
, sizeof(buffer
),
572 IXGBE_HI_COMMAND_TIMEOUT
, false);
576 *data
= (u16
)IXGBE_READ_REG_ARRAY(hw
, IXGBE_FLEX_MNG
,
582 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
583 * @hw: pointer to hardware structure
584 * @offset: offset of word in the EEPROM to read
585 * @words: number of words
586 * @data: word(s) read from the EEPROM
588 * Reads a 16 bit word(s) from the EEPROM using the hostif.
590 static s32
ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw
*hw
,
591 u16 offset
, u16 words
, u16
*data
)
593 struct ixgbe_hic_read_shadow_ram buffer
;
594 u32 current_word
= 0;
599 /* Take semaphore for the entire operation. */
600 status
= hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
602 hw_dbg(hw
, "EEPROM read buffer - semaphore failed\n");
607 if (words
> FW_MAX_READ_BUFFER_SIZE
/ 2)
608 words_to_read
= FW_MAX_READ_BUFFER_SIZE
/ 2;
610 words_to_read
= words
;
612 buffer
.hdr
.req
.cmd
= FW_READ_SHADOW_RAM_CMD
;
613 buffer
.hdr
.req
.buf_lenh
= 0;
614 buffer
.hdr
.req
.buf_lenl
= FW_READ_SHADOW_RAM_LEN
;
615 buffer
.hdr
.req
.checksum
= FW_DEFAULT_CHECKSUM
;
617 /* convert offset from words to bytes */
618 buffer
.address
= cpu_to_be32((offset
+ current_word
) * 2);
619 buffer
.length
= cpu_to_be16(words_to_read
* 2);
621 status
= ixgbe_host_interface_command(hw
, &buffer
,
623 IXGBE_HI_COMMAND_TIMEOUT
,
626 hw_dbg(hw
, "Host interface command failed\n");
630 for (i
= 0; i
< words_to_read
; i
++) {
631 u32 reg
= IXGBE_FLEX_MNG
+ (FW_NVM_DATA_OFFSET
<< 2) +
633 u32 value
= IXGBE_READ_REG(hw
, reg
);
635 data
[current_word
] = (u16
)(value
& 0xffff);
638 if (i
< words_to_read
) {
640 data
[current_word
] = (u16
)(value
& 0xffff);
644 words
-= words_to_read
;
648 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
652 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
653 * @hw: pointer to hardware structure
654 * @ptr: pointer offset in eeprom
655 * @size: size of section pointed by ptr, if 0 first word will be used as size
656 * @csum: address of checksum to update
658 * Returns error status for any failure
660 static s32
ixgbe_checksum_ptr_x550(struct ixgbe_hw
*hw
, u16 ptr
,
661 u16 size
, u16
*csum
, u16
*buffer
,
666 u16 length
, bufsz
, i
, start
;
669 bufsz
= sizeof(buf
) / sizeof(buf
[0]);
671 /* Read a chunk at the pointer location */
673 status
= ixgbe_read_ee_hostif_buffer_X550(hw
, ptr
, bufsz
, buf
);
675 hw_dbg(hw
, "Failed to read EEPROM image\n");
680 if (buffer_size
< ptr
)
681 return IXGBE_ERR_PARAM
;
682 local_buffer
= &buffer
[ptr
];
690 length
= local_buffer
[0];
692 /* Skip pointer section if length is invalid. */
693 if (length
== 0xFFFF || length
== 0 ||
694 (ptr
+ length
) >= hw
->eeprom
.word_size
)
698 if (buffer
&& ((u32
)start
+ (u32
)length
> buffer_size
))
699 return IXGBE_ERR_PARAM
;
701 for (i
= start
; length
; i
++, length
--) {
702 if (i
== bufsz
&& !buffer
) {
708 /* Read a chunk at the pointer location */
709 status
= ixgbe_read_ee_hostif_buffer_X550(hw
, ptr
,
712 hw_dbg(hw
, "Failed to read EEPROM image\n");
716 *csum
+= local_buffer
[i
];
721 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
722 * @hw: pointer to hardware structure
723 * @buffer: pointer to buffer containing calculated checksum
724 * @buffer_size: size of buffer
726 * Returns a negative error code on error, or the 16-bit checksum
728 static s32
ixgbe_calc_checksum_X550(struct ixgbe_hw
*hw
, u16
*buffer
,
731 u16 eeprom_ptrs
[IXGBE_EEPROM_LAST_WORD
+ 1];
735 u16 pointer
, i
, size
;
737 hw
->eeprom
.ops
.init_params(hw
);
740 /* Read pointer area */
741 status
= ixgbe_read_ee_hostif_buffer_X550(hw
, 0,
742 IXGBE_EEPROM_LAST_WORD
+ 1,
745 hw_dbg(hw
, "Failed to read EEPROM image\n");
748 local_buffer
= eeprom_ptrs
;
750 if (buffer_size
< IXGBE_EEPROM_LAST_WORD
)
751 return IXGBE_ERR_PARAM
;
752 local_buffer
= buffer
;
755 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
756 * checksum word itself
758 for (i
= 0; i
<= IXGBE_EEPROM_LAST_WORD
; i
++)
759 if (i
!= IXGBE_EEPROM_CHECKSUM
)
760 checksum
+= local_buffer
[i
];
762 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
763 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
765 for (i
= IXGBE_PCIE_ANALOG_PTR_X550
; i
< IXGBE_FW_PTR
; i
++) {
766 if (i
== IXGBE_PHY_PTR
|| i
== IXGBE_OPTION_ROM_PTR
)
769 pointer
= local_buffer
[i
];
771 /* Skip pointer section if the pointer is invalid. */
772 if (pointer
== 0xFFFF || pointer
== 0 ||
773 pointer
>= hw
->eeprom
.word_size
)
777 case IXGBE_PCIE_GENERAL_PTR
:
778 size
= IXGBE_IXGBE_PCIE_GENERAL_SIZE
;
780 case IXGBE_PCIE_CONFIG0_PTR
:
781 case IXGBE_PCIE_CONFIG1_PTR
:
782 size
= IXGBE_PCIE_CONFIG_SIZE
;
789 status
= ixgbe_checksum_ptr_x550(hw
, pointer
, size
, &checksum
,
790 buffer
, buffer_size
);
795 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
797 return (s32
)checksum
;
800 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
801 * @hw: pointer to hardware structure
803 * Returns a negative error code on error, or the 16-bit checksum
805 static s32
ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw
*hw
)
807 return ixgbe_calc_checksum_X550(hw
, NULL
, 0);
810 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
811 * @hw: pointer to hardware structure
812 * @offset: offset of word in the EEPROM to read
813 * @data: word read from the EEPROM
815 * Reads a 16 bit word from the EEPROM using the hostif.
817 static s32
ixgbe_read_ee_hostif_X550(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
821 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) == 0) {
822 status
= ixgbe_read_ee_hostif_data_X550(hw
, offset
, data
);
823 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
825 status
= IXGBE_ERR_SWFW_SYNC
;
831 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
832 * @hw: pointer to hardware structure
833 * @checksum_val: calculated checksum
835 * Performs checksum calculation and validates the EEPROM checksum. If the
836 * caller does not need checksum_val, the value can be NULL.
838 static s32
ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw
*hw
,
843 u16 read_checksum
= 0;
845 /* Read the first word from the EEPROM. If this times out or fails, do
846 * not continue or we could be in for a very long wait while every
849 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
851 hw_dbg(hw
, "EEPROM read failed\n");
855 status
= hw
->eeprom
.ops
.calc_checksum(hw
);
859 checksum
= (u16
)(status
& 0xffff);
861 status
= ixgbe_read_ee_hostif_X550(hw
, IXGBE_EEPROM_CHECKSUM
,
866 /* Verify read checksum from EEPROM is the same as
867 * calculated checksum
869 if (read_checksum
!= checksum
) {
870 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
871 hw_dbg(hw
, "Invalid EEPROM checksum");
874 /* If the user cares, return the calculated checksum */
876 *checksum_val
= checksum
;
881 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
882 * @hw: pointer to hardware structure
883 * @offset: offset of word in the EEPROM to write
884 * @data: word write to the EEPROM
886 * Write a 16 bit word to the EEPROM using the hostif.
888 static s32
ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw
*hw
, u16 offset
,
892 struct ixgbe_hic_write_shadow_ram buffer
;
894 buffer
.hdr
.req
.cmd
= FW_WRITE_SHADOW_RAM_CMD
;
895 buffer
.hdr
.req
.buf_lenh
= 0;
896 buffer
.hdr
.req
.buf_lenl
= FW_WRITE_SHADOW_RAM_LEN
;
897 buffer
.hdr
.req
.checksum
= FW_DEFAULT_CHECKSUM
;
900 buffer
.length
= cpu_to_be16(sizeof(u16
));
902 buffer
.address
= cpu_to_be32(offset
* 2);
904 status
= ixgbe_host_interface_command(hw
, &buffer
, sizeof(buffer
),
905 IXGBE_HI_COMMAND_TIMEOUT
, false);
909 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
910 * @hw: pointer to hardware structure
911 * @offset: offset of word in the EEPROM to write
912 * @data: word write to the EEPROM
914 * Write a 16 bit word to the EEPROM using the hostif.
916 static s32
ixgbe_write_ee_hostif_X550(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
920 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) == 0) {
921 status
= ixgbe_write_ee_hostif_data_X550(hw
, offset
, data
);
922 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
924 hw_dbg(hw
, "write ee hostif failed to get semaphore");
925 status
= IXGBE_ERR_SWFW_SYNC
;
931 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
932 * @hw: pointer to hardware structure
934 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
936 static s32
ixgbe_update_flash_X550(struct ixgbe_hw
*hw
)
939 union ixgbe_hic_hdr2 buffer
;
941 buffer
.req
.cmd
= FW_SHADOW_RAM_DUMP_CMD
;
942 buffer
.req
.buf_lenh
= 0;
943 buffer
.req
.buf_lenl
= FW_SHADOW_RAM_DUMP_LEN
;
944 buffer
.req
.checksum
= FW_DEFAULT_CHECKSUM
;
946 status
= ixgbe_host_interface_command(hw
, &buffer
, sizeof(buffer
),
947 IXGBE_HI_COMMAND_TIMEOUT
, false);
952 * ixgbe_get_bus_info_X550em - Set PCI bus info
953 * @hw: pointer to hardware structure
955 * Sets bus link width and speed to unknown because X550em is
958 static s32
ixgbe_get_bus_info_X550em(struct ixgbe_hw
*hw
)
960 hw
->bus
.type
= ixgbe_bus_type_internal
;
961 hw
->bus
.width
= ixgbe_bus_width_unknown
;
962 hw
->bus
.speed
= ixgbe_bus_speed_unknown
;
964 hw
->mac
.ops
.set_lan_id(hw
);
969 /** ixgbe_disable_rx_x550 - Disable RX unit
971 * Enables the Rx DMA unit for x550
973 static void ixgbe_disable_rx_x550(struct ixgbe_hw
*hw
)
975 u32 rxctrl
, pfdtxgswc
;
977 struct ixgbe_hic_disable_rxen fw_cmd
;
979 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
980 if (rxctrl
& IXGBE_RXCTRL_RXEN
) {
981 pfdtxgswc
= IXGBE_READ_REG(hw
, IXGBE_PFDTXGSWC
);
982 if (pfdtxgswc
& IXGBE_PFDTXGSWC_VT_LBEN
) {
983 pfdtxgswc
&= ~IXGBE_PFDTXGSWC_VT_LBEN
;
984 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, pfdtxgswc
);
985 hw
->mac
.set_lben
= true;
987 hw
->mac
.set_lben
= false;
990 fw_cmd
.hdr
.cmd
= FW_DISABLE_RXEN_CMD
;
991 fw_cmd
.hdr
.buf_len
= FW_DISABLE_RXEN_LEN
;
992 fw_cmd
.hdr
.checksum
= FW_DEFAULT_CHECKSUM
;
993 fw_cmd
.port_number
= hw
->bus
.lan_id
;
995 status
= ixgbe_host_interface_command(hw
, &fw_cmd
,
996 sizeof(struct ixgbe_hic_disable_rxen
),
997 IXGBE_HI_COMMAND_TIMEOUT
, true);
999 /* If we fail - disable RX using register write */
1001 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
1002 if (rxctrl
& IXGBE_RXCTRL_RXEN
) {
1003 rxctrl
&= ~IXGBE_RXCTRL_RXEN
;
1004 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
);
1010 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1011 * @hw: pointer to hardware structure
1013 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1014 * checksum and updates the EEPROM and instructs the hardware to update
1017 static s32
ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw
*hw
)
1022 /* Read the first word from the EEPROM. If this times out or fails, do
1023 * not continue or we could be in for a very long wait while every
1026 status
= ixgbe_read_ee_hostif_X550(hw
, 0, &checksum
);
1028 hw_dbg(hw
, "EEPROM read failed\n");
1032 status
= ixgbe_calc_eeprom_checksum_X550(hw
);
1036 checksum
= (u16
)(status
& 0xffff);
1038 status
= ixgbe_write_ee_hostif_X550(hw
, IXGBE_EEPROM_CHECKSUM
,
1043 status
= ixgbe_update_flash_X550(hw
);
1048 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1049 * @hw: pointer to hardware structure
1050 * @offset: offset of word in the EEPROM to write
1051 * @words: number of words
1052 * @data: word(s) write to the EEPROM
1055 * Write a 16 bit word(s) to the EEPROM using the hostif.
1057 static s32
ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw
*hw
,
1058 u16 offset
, u16 words
,
1064 /* Take semaphore for the entire operation. */
1065 status
= hw
->mac
.ops
.acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1067 hw_dbg(hw
, "EEPROM write buffer - semaphore failed\n");
1071 for (i
= 0; i
< words
; i
++) {
1072 status
= ixgbe_write_ee_hostif_data_X550(hw
, offset
+ i
,
1075 hw_dbg(hw
, "Eeprom buffered write failed\n");
1080 hw
->mac
.ops
.release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1085 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1088 * @hw: pointer to hardware structure
1089 * @reg_addr: 32 bit PHY register to write
1090 * @device_type: 3 bit device type
1091 * @data: Data to write to the register
1093 static s32
ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw
*hw
, u32 reg_addr
,
1094 u32 device_type
, u32 data
)
1096 u32 gssr
= IXGBE_GSSR_PHY1_SM
| IXGBE_GSSR_PHY0_SM
;
1100 ret
= hw
->mac
.ops
.acquire_swfw_sync(hw
, gssr
);
1104 ret
= ixgbe_iosf_wait(hw
, NULL
);
1108 command
= ((reg_addr
<< IXGBE_SB_IOSF_CTRL_ADDR_SHIFT
) |
1109 (device_type
<< IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT
));
1111 /* Write IOSF control register */
1112 IXGBE_WRITE_REG(hw
, IXGBE_SB_IOSF_INDIRECT_CTRL
, command
);
1114 /* Write IOSF data register */
1115 IXGBE_WRITE_REG(hw
, IXGBE_SB_IOSF_INDIRECT_DATA
, data
);
1117 ret
= ixgbe_iosf_wait(hw
, &command
);
1119 if ((command
& IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK
) != 0) {
1120 error
= (command
& IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK
) >>
1121 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT
;
1122 hw_dbg(hw
, "Failed to write, error %x\n", error
);
1123 return IXGBE_ERR_PHY
;
1127 hw
->mac
.ops
.release_swfw_sync(hw
, gssr
);
1131 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1132 * @hw: pointer to hardware structure
1133 * @speed: the link speed to force
1135 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1136 * internal and external PHY at a specific speed, without autonegotiation.
1138 static s32
ixgbe_setup_ixfi_x550em(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
)
1143 /* Disable AN and force speed to 10G Serial. */
1144 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
1145 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1146 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
1150 reg_val
&= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE
;
1151 reg_val
&= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK
;
1153 /* Select forced link speed for internal PHY. */
1155 case IXGBE_LINK_SPEED_10GB_FULL
:
1156 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G
;
1158 case IXGBE_LINK_SPEED_1GB_FULL
:
1159 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G
;
1162 /* Other link speeds are not supported by internal KR PHY. */
1163 return IXGBE_ERR_LINK_SETUP
;
1166 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
1167 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1168 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
1172 /* Disable training protocol FSM. */
1173 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
1174 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw
->bus
.lan_id
),
1175 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
1179 reg_val
|= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL
;
1180 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
1181 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw
->bus
.lan_id
),
1182 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
1186 /* Disable Flex from training TXFFE. */
1187 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
1188 IXGBE_KRM_DSP_TXFFE_STATE_4(hw
->bus
.lan_id
),
1189 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
1193 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN
;
1194 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN
;
1195 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN
;
1196 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
1197 IXGBE_KRM_DSP_TXFFE_STATE_4(hw
->bus
.lan_id
),
1198 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
1202 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
1203 IXGBE_KRM_DSP_TXFFE_STATE_5(hw
->bus
.lan_id
),
1204 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
1208 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN
;
1209 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN
;
1210 reg_val
&= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN
;
1211 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
1212 IXGBE_KRM_DSP_TXFFE_STATE_5(hw
->bus
.lan_id
),
1213 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
1217 /* Enable override for coefficients. */
1218 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
1219 IXGBE_KRM_TX_COEFF_CTRL_1(hw
->bus
.lan_id
),
1220 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
1224 reg_val
|= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN
;
1225 reg_val
|= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN
;
1226 reg_val
|= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN
;
1227 reg_val
|= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN
;
1228 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
1229 IXGBE_KRM_TX_COEFF_CTRL_1(hw
->bus
.lan_id
),
1230 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
1234 /* Toggle port SW reset by AN reset. */
1235 status
= ixgbe_read_iosf_sb_reg_x550(hw
,
1236 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1237 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
1241 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART
;
1242 status
= ixgbe_write_iosf_sb_reg_x550(hw
,
1243 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1244 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
1250 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1251 * @hw: pointer to hardware structure
1252 * @linear: true if SFP module is linear
1254 static s32
ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw
*hw
, bool *linear
)
1256 switch (hw
->phy
.sfp_type
) {
1257 case ixgbe_sfp_type_not_present
:
1258 return IXGBE_ERR_SFP_NOT_PRESENT
;
1259 case ixgbe_sfp_type_da_cu_core0
:
1260 case ixgbe_sfp_type_da_cu_core1
:
1263 case ixgbe_sfp_type_srlr_core0
:
1264 case ixgbe_sfp_type_srlr_core1
:
1265 case ixgbe_sfp_type_da_act_lmt_core0
:
1266 case ixgbe_sfp_type_da_act_lmt_core1
:
1267 case ixgbe_sfp_type_1g_sx_core0
:
1268 case ixgbe_sfp_type_1g_sx_core1
:
1269 case ixgbe_sfp_type_1g_lx_core0
:
1270 case ixgbe_sfp_type_1g_lx_core1
:
1273 case ixgbe_sfp_type_unknown
:
1274 case ixgbe_sfp_type_1g_cu_core0
:
1275 case ixgbe_sfp_type_1g_cu_core1
:
1277 return IXGBE_ERR_SFP_NOT_SUPPORTED
;
1284 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1285 * @hw: pointer to hardware structure
1287 * Configures the extern PHY and the integrated KR PHY for SFP support.
1290 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw
*hw
,
1291 ixgbe_link_speed speed
,
1292 __always_unused
bool autoneg_wait_to_complete
)
1296 bool setup_linear
= false;
1298 /* Check if SFP module is supported and linear */
1299 status
= ixgbe_supported_sfp_modules_X550em(hw
, &setup_linear
);
1301 /* If no SFP module present, then return success. Return success since
1302 * there is no reason to configure CS4227 and SFP not present error is
1303 * not accepted in the setup MAC link flow.
1305 if (status
== IXGBE_ERR_SFP_NOT_PRESENT
)
1311 if (!(hw
->phy
.nw_mng_if_sel
& IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE
)) {
1312 /* Configure CS4227 LINE side to 10G SR. */
1313 slice
= IXGBE_CS4227_LINE_SPARE22_MSB
+ (hw
->bus
.lan_id
<< 12);
1314 value
= IXGBE_CS4227_SPEED_10G
;
1315 status
= ixgbe_write_i2c_combined_generic(hw
, IXGBE_CS4227
,
1320 slice
= IXGBE_CS4227_LINE_SPARE24_LSB
+ (hw
->bus
.lan_id
<< 12);
1321 value
= (IXGBE_CS4227_EDC_MODE_SR
<< 1) | 1;
1322 status
= ixgbe_write_i2c_combined_generic(hw
, IXGBE_CS4227
,
1327 /* Configure CS4227 for HOST connection rate then type. */
1328 slice
= IXGBE_CS4227_HOST_SPARE22_MSB
+ (hw
->bus
.lan_id
<< 12);
1329 value
= speed
& IXGBE_LINK_SPEED_10GB_FULL
?
1330 IXGBE_CS4227_SPEED_10G
: IXGBE_CS4227_SPEED_1G
;
1331 status
= ixgbe_write_i2c_combined_generic(hw
, IXGBE_CS4227
,
1336 slice
= IXGBE_CS4227_HOST_SPARE24_LSB
+ (hw
->bus
.lan_id
<< 12);
1338 value
= (IXGBE_CS4227_EDC_MODE_CX1
<< 1) | 1;
1340 value
= (IXGBE_CS4227_EDC_MODE_SR
<< 1) | 1;
1341 status
= ixgbe_write_i2c_combined_generic(hw
, IXGBE_CS4227
,
1346 /* Setup XFI internal link. */
1347 status
= ixgbe_setup_ixfi_x550em(hw
, &speed
);
1349 hw_dbg(hw
, "setup_ixfi failed with %d\n", status
);
1353 /* Configure internal PHY for KR/KX. */
1354 status
= ixgbe_setup_kr_speed_x550em(hw
, speed
);
1356 hw_dbg(hw
, "setup_kr_speed failed with %d\n", status
);
1360 /* Configure CS4227 LINE side to proper mode. */
1361 slice
= IXGBE_CS4227_LINE_SPARE24_LSB
+ (hw
->bus
.lan_id
<< 12);
1363 value
= (IXGBE_CS4227_EDC_MODE_CX1
<< 1) | 1;
1365 value
= (IXGBE_CS4227_EDC_MODE_SR
<< 1) | 1;
1366 status
= ixgbe_write_i2c_combined_generic(hw
, IXGBE_CS4227
,
1375 hw_dbg(hw
, "combined i2c access failed with %d\n", status
);
1380 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1381 * @hw: pointer to hardware structure
1383 * Configure the the integrated PHY for native SFP support.
1386 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw
*hw
, ixgbe_link_speed speed
,
1387 __always_unused
bool autoneg_wait_to_complete
)
1389 bool setup_linear
= false;
1393 /* Check if SFP module is supported and linear */
1394 rc
= ixgbe_supported_sfp_modules_X550em(hw
, &setup_linear
);
1396 /* If no SFP module present, then return success. Return success since
1397 * SFP not present error is not excepted in the setup MAC link flow.
1399 if (rc
== IXGBE_ERR_SFP_NOT_PRESENT
)
1405 /* Configure internal PHY for native SFI */
1406 rc
= hw
->mac
.ops
.read_iosf_sb_reg(hw
,
1407 IXGBE_KRM_AN_CNTL_8(hw
->bus
.lan_id
),
1408 IXGBE_SB_IOSF_TARGET_KR_PHY
,
1414 reg_phy_int
&= ~IXGBE_KRM_AN_CNTL_8_LIMITING
;
1415 reg_phy_int
|= IXGBE_KRM_AN_CNTL_8_LINEAR
;
1417 reg_phy_int
|= IXGBE_KRM_AN_CNTL_8_LIMITING
;
1418 reg_phy_int
&= ~IXGBE_KRM_AN_CNTL_8_LINEAR
;
1421 rc
= hw
->mac
.ops
.write_iosf_sb_reg(hw
,
1422 IXGBE_KRM_AN_CNTL_8(hw
->bus
.lan_id
),
1423 IXGBE_SB_IOSF_TARGET_KR_PHY
,
1428 /* Setup XFI/SFI internal link */
1429 return ixgbe_setup_ixfi_x550em(hw
, &speed
);
1433 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1434 * @hw: pointer to hardware structure
1436 * Configure the the integrated PHY for SFP support.
1439 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw
*hw
, ixgbe_link_speed speed
,
1440 __always_unused
bool autoneg_wait_to_complete
)
1442 u32 reg_slice
, slice_offset
;
1443 bool setup_linear
= false;
1447 /* Check if SFP module is supported and linear */
1448 rc
= ixgbe_supported_sfp_modules_X550em(hw
, &setup_linear
);
1450 /* If no SFP module present, then return success. Return success since
1451 * SFP not present error is not excepted in the setup MAC link flow.
1453 if (rc
== IXGBE_ERR_SFP_NOT_PRESENT
)
1459 /* Configure internal PHY for KR/KX. */
1460 ixgbe_setup_kr_speed_x550em(hw
, speed
);
1462 if (!hw
->phy
.mdio
.prtad
|| hw
->phy
.mdio
.prtad
== 0xFFFF)
1463 return IXGBE_ERR_PHY_ADDR_INVALID
;
1465 /* Get external PHY device id */
1466 rc
= hw
->phy
.ops
.read_reg(hw
, IXGBE_CS4227_GLOBAL_ID_MSB
,
1467 IXGBE_MDIO_ZERO_DEV_TYPE
, ®_phy_ext
);
1471 /* When configuring quad port CS4223, the MAC instance is part
1472 * of the slice offset.
1474 if (reg_phy_ext
== IXGBE_CS4223_PHY_ID
)
1475 slice_offset
= (hw
->bus
.lan_id
+
1476 (hw
->bus
.instance_id
<< 1)) << 12;
1478 slice_offset
= hw
->bus
.lan_id
<< 12;
1480 /* Configure CS4227/CS4223 LINE side to proper mode. */
1481 reg_slice
= IXGBE_CS4227_LINE_SPARE24_LSB
+ slice_offset
;
1483 reg_phy_ext
= (IXGBE_CS4227_EDC_MODE_CX1
<< 1) | 1;
1485 reg_phy_ext
= (IXGBE_CS4227_EDC_MODE_SR
<< 1) | 1;
1486 return hw
->phy
.ops
.write_reg(hw
, reg_slice
, IXGBE_MDIO_ZERO_DEV_TYPE
,
1491 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1492 * @hw: pointer to hardware structure
1493 * @speed: new link speed
1494 * @autoneg_wait_to_complete: true when waiting for completion is needed
1496 * Setup internal/external PHY link speed based on link speed, then set
1497 * external PHY auto advertised link speed.
1499 * Returns error status for any failure
1501 static s32
ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw
*hw
,
1502 ixgbe_link_speed speed
,
1506 ixgbe_link_speed force_speed
;
1508 /* Setup internal/external PHY link speed to iXFI (10G), unless
1509 * only 1G is auto advertised then setup KX link.
1511 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
1512 force_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
1514 force_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
1516 /* If internal link mode is XFI, then setup XFI internal link. */
1517 if (!(hw
->phy
.nw_mng_if_sel
& IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE
)) {
1518 status
= ixgbe_setup_ixfi_x550em(hw
, &force_speed
);
1524 return hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg_wait
);
1527 /** ixgbe_check_link_t_X550em - Determine link and speed status
1528 * @hw: pointer to hardware structure
1529 * @speed: pointer to link speed
1530 * @link_up: true when link is up
1531 * @link_up_wait_to_complete: bool used to wait for link up or not
1533 * Check that both the MAC and X557 external PHY have link.
1535 static s32
ixgbe_check_link_t_X550em(struct ixgbe_hw
*hw
,
1536 ixgbe_link_speed
*speed
,
1538 bool link_up_wait_to_complete
)
1543 if (hw
->mac
.ops
.get_media_type(hw
) != ixgbe_media_type_copper
)
1544 return IXGBE_ERR_CONFIG
;
1546 status
= ixgbe_check_mac_link_generic(hw
, speed
, link_up
,
1547 link_up_wait_to_complete
);
1549 /* If check link fails or MAC link is not up, then return */
1550 if (status
|| !(*link_up
))
1553 /* MAC link is up, so check external PHY link.
1554 * Read this twice back to back to indicate current status.
1556 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_STATUS
,
1557 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
1562 /* If external PHY link is not up, then indicate link not up */
1563 if (!(autoneg_status
& IXGBE_MDIO_AUTO_NEG_LINK_STATUS
))
1570 * ixgbe_setup_sgmii - Set up link for sgmii
1571 * @hw: pointer to hardware structure
1574 ixgbe_setup_sgmii(struct ixgbe_hw
*hw
, __always_unused ixgbe_link_speed speed
,
1575 __always_unused
bool autoneg_wait_to_complete
)
1577 struct ixgbe_mac_info
*mac
= &hw
->mac
;
1581 rc
= mac
->ops
.read_iosf_sb_reg(hw
,
1582 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1583 IXGBE_SB_IOSF_TARGET_KR_PHY
, &lval
);
1587 lval
&= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE
;
1588 lval
&= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK
;
1589 lval
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN
;
1590 lval
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN
;
1591 lval
|= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G
;
1592 rc
= mac
->ops
.write_iosf_sb_reg(hw
,
1593 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1594 IXGBE_SB_IOSF_TARGET_KR_PHY
, lval
);
1598 rc
= mac
->ops
.read_iosf_sb_reg(hw
,
1599 IXGBE_KRM_SGMII_CTRL(hw
->bus
.lan_id
),
1600 IXGBE_SB_IOSF_TARGET_KR_PHY
, &sval
);
1604 sval
|= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D
;
1605 sval
|= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D
;
1606 rc
= mac
->ops
.write_iosf_sb_reg(hw
,
1607 IXGBE_KRM_SGMII_CTRL(hw
->bus
.lan_id
),
1608 IXGBE_SB_IOSF_TARGET_KR_PHY
, sval
);
1612 lval
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART
;
1613 rc
= mac
->ops
.write_iosf_sb_reg(hw
,
1614 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1615 IXGBE_SB_IOSF_TARGET_KR_PHY
, lval
);
1620 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1621 * @hw: pointer to hardware structure
1623 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw
*hw
)
1625 struct ixgbe_mac_info
*mac
= &hw
->mac
;
1627 mac
->ops
.setup_fc
= ixgbe_setup_fc_x550em
;
1629 switch (mac
->ops
.get_media_type(hw
)) {
1630 case ixgbe_media_type_fiber
:
1631 /* CS4227 does not support autoneg, so disable the laser control
1632 * functions for SFP+ fiber
1634 mac
->ops
.disable_tx_laser
= NULL
;
1635 mac
->ops
.enable_tx_laser
= NULL
;
1636 mac
->ops
.flap_tx_laser
= NULL
;
1637 mac
->ops
.setup_link
= ixgbe_setup_mac_link_multispeed_fiber
;
1638 switch (hw
->device_id
) {
1639 case IXGBE_DEV_ID_X550EM_A_SFP_N
:
1640 mac
->ops
.setup_mac_link
= ixgbe_setup_mac_link_sfp_n
;
1642 case IXGBE_DEV_ID_X550EM_A_SFP
:
1643 mac
->ops
.setup_mac_link
=
1644 ixgbe_setup_mac_link_sfp_x550a
;
1647 mac
->ops
.setup_mac_link
=
1648 ixgbe_setup_mac_link_sfp_x550em
;
1651 mac
->ops
.set_rate_select_speed
=
1652 ixgbe_set_soft_rate_select_speed
;
1654 case ixgbe_media_type_copper
:
1655 mac
->ops
.setup_link
= ixgbe_setup_mac_link_t_X550em
;
1656 mac
->ops
.setup_fc
= ixgbe_setup_fc_generic
;
1657 mac
->ops
.check_link
= ixgbe_check_link_t_X550em
;
1659 case ixgbe_media_type_backplane
:
1660 if (hw
->device_id
== IXGBE_DEV_ID_X550EM_A_SGMII
||
1661 hw
->device_id
== IXGBE_DEV_ID_X550EM_A_SGMII_L
)
1662 mac
->ops
.setup_link
= ixgbe_setup_sgmii
;
1669 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1670 * @hw: pointer to hardware structure
1672 static s32
ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw
*hw
)
1677 /* Check if SFP module is supported */
1678 status
= ixgbe_supported_sfp_modules_X550em(hw
, &linear
);
1682 ixgbe_init_mac_link_ops_X550em(hw
);
1683 hw
->phy
.ops
.reset
= NULL
;
1688 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1689 * @hw: pointer to hardware structure
1690 * @speed: pointer to link speed
1691 * @autoneg: true when autoneg or autotry is enabled
1693 static s32
ixgbe_get_link_capabilities_X550em(struct ixgbe_hw
*hw
,
1694 ixgbe_link_speed
*speed
,
1698 if (hw
->phy
.media_type
== ixgbe_media_type_fiber
) {
1699 /* CS4227 SFP must not enable auto-negotiation */
1702 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_sx_core0
||
1703 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_sx_core1
) {
1704 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
1708 /* Link capabilities are based on SFP */
1709 if (hw
->phy
.multispeed_fiber
)
1710 *speed
= IXGBE_LINK_SPEED_10GB_FULL
|
1711 IXGBE_LINK_SPEED_1GB_FULL
;
1713 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
1715 *speed
= IXGBE_LINK_SPEED_10GB_FULL
|
1716 IXGBE_LINK_SPEED_1GB_FULL
;
1723 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1724 * @hw: pointer to hardware structure
1725 * @lsc: pointer to boolean flag which indicates whether external Base T
1726 * PHY interrupt is lsc
1728 * Determime if external Base T PHY interrupt cause is high temperature
1729 * failure alarm or link status change.
1731 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1732 * failure alarm, else return PHY access status.
1734 static s32
ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw
*hw
, bool *lsc
)
1741 /* Vendor alarm triggered */
1742 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG
,
1743 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1746 if (status
|| !(reg
& IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN
))
1749 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1750 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG
,
1751 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1754 if (status
|| !(reg
& (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN
|
1755 IXGBE_MDIO_GLOBAL_ALARM_1_INT
)))
1758 /* Global alarm triggered */
1759 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_ALARM_1
,
1760 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1766 /* If high temperature failure, then return over temp error and exit */
1767 if (reg
& IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL
) {
1768 /* power down the PHY in case the PHY FW didn't already */
1769 ixgbe_set_copper_phy_power(hw
, false);
1770 return IXGBE_ERR_OVERTEMP
;
1772 if (reg
& IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT
) {
1773 /* device fault alarm triggered */
1774 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_FAULT_MSG
,
1775 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1780 /* if device fault was due to high temp alarm handle and exit */
1781 if (reg
== IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP
) {
1782 /* power down the PHY in case the PHY FW didn't */
1783 ixgbe_set_copper_phy_power(hw
, false);
1784 return IXGBE_ERR_OVERTEMP
;
1788 /* Vendor alarm 2 triggered */
1789 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG
,
1790 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, ®
);
1792 if (status
|| !(reg
& IXGBE_MDIO_GLOBAL_STD_ALM2_INT
))
1795 /* link connect/disconnect event occurred */
1796 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2
,
1797 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, ®
);
1803 if (reg
& IXGBE_MDIO_AUTO_NEG_VEN_LSC
)
1810 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1811 * @hw: pointer to hardware structure
1813 * Enable link status change and temperature failure alarm for the external
1816 * Returns PHY access status
1818 static s32
ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw
*hw
)
1824 /* Clear interrupt flags */
1825 status
= ixgbe_get_lasi_ext_t_x550em(hw
, &lsc
);
1827 /* Enable link status change alarm */
1828 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK
,
1829 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, ®
);
1833 reg
|= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN
;
1835 status
= hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK
,
1836 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, reg
);
1840 /* Enable high temperature failure and global fault alarms */
1841 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_INT_MASK
,
1842 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1847 reg
|= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN
|
1848 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN
);
1850 status
= hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_GLOBAL_INT_MASK
,
1851 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1856 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1857 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK
,
1858 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1863 reg
|= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN
|
1864 IXGBE_MDIO_GLOBAL_ALARM_1_INT
);
1866 status
= hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK
,
1867 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1872 /* Enable chip-wide vendor alarm */
1873 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK
,
1874 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1879 reg
|= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN
;
1881 status
= hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK
,
1882 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
1889 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1890 * @hw: pointer to hardware structure
1892 * Handle external Base T PHY interrupt. If high temperature
1893 * failure alarm then return error, else if link status change
1894 * then setup internal/external PHY link
1896 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1897 * failure alarm, else return PHY access status.
1899 static s32
ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw
*hw
)
1901 struct ixgbe_phy_info
*phy
= &hw
->phy
;
1905 status
= ixgbe_get_lasi_ext_t_x550em(hw
, &lsc
);
1909 if (lsc
&& phy
->ops
.setup_internal_link
)
1910 return phy
->ops
.setup_internal_link(hw
);
1916 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1917 * @hw: pointer to hardware structure
1918 * @speed: link speed
1920 * Configures the integrated KR PHY.
1922 static s32
ixgbe_setup_kr_speed_x550em(struct ixgbe_hw
*hw
,
1923 ixgbe_link_speed speed
)
1928 status
= hw
->mac
.ops
.read_iosf_sb_reg(hw
,
1929 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1930 IXGBE_SB_IOSF_TARGET_KR_PHY
, ®_val
);
1934 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE
;
1935 reg_val
&= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ
|
1936 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC
);
1937 reg_val
&= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR
|
1938 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX
);
1940 /* Advertise 10G support. */
1941 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
1942 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR
;
1944 /* Advertise 1G support. */
1945 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
1946 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX
;
1948 /* Restart auto-negotiation. */
1949 reg_val
|= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART
;
1950 status
= hw
->mac
.ops
.write_iosf_sb_reg(hw
,
1951 IXGBE_KRM_LINK_CTRL_1(hw
->bus
.lan_id
),
1952 IXGBE_SB_IOSF_TARGET_KR_PHY
, reg_val
);
1957 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1958 * @hw: pointer to hardware structure
1960 * Configures the integrated KX4 PHY.
1962 static s32
ixgbe_setup_kx4_x550em(struct ixgbe_hw
*hw
)
1967 status
= hw
->mac
.ops
.read_iosf_sb_reg(hw
, IXGBE_KX4_LINK_CNTL_1
,
1968 IXGBE_SB_IOSF_TARGET_KX4_PCS0
+
1969 hw
->bus
.lan_id
, ®_val
);
1973 reg_val
&= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4
|
1974 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX
);
1976 reg_val
|= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE
;
1978 /* Advertise 10G support. */
1979 if (hw
->phy
.autoneg_advertised
& IXGBE_LINK_SPEED_10GB_FULL
)
1980 reg_val
|= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4
;
1982 /* Advertise 1G support. */
1983 if (hw
->phy
.autoneg_advertised
& IXGBE_LINK_SPEED_1GB_FULL
)
1984 reg_val
|= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX
;
1986 /* Restart auto-negotiation. */
1987 reg_val
|= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART
;
1988 status
= hw
->mac
.ops
.write_iosf_sb_reg(hw
, IXGBE_KX4_LINK_CNTL_1
,
1989 IXGBE_SB_IOSF_TARGET_KX4_PCS0
+
1990 hw
->bus
.lan_id
, reg_val
);
1996 * ixgbe_setup_kr_x550em - Configure the KR PHY
1997 * @hw: pointer to hardware structure
1999 * Configures the integrated KR PHY for X550EM_x.
2001 static s32
ixgbe_setup_kr_x550em(struct ixgbe_hw
*hw
)
2003 if (hw
->mac
.type
!= ixgbe_mac_X550EM_x
)
2006 return ixgbe_setup_kr_speed_x550em(hw
, hw
->phy
.autoneg_advertised
);
2009 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2010 * @hw: address of hardware structure
2011 * @link_up: address of boolean to indicate link status
2013 * Returns error code if unable to get link status.
2015 static s32
ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw
*hw
, bool *link_up
)
2022 /* read this twice back to back to indicate current status */
2023 ret
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_STATUS
,
2024 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
2029 ret
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_STATUS
,
2030 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
2035 *link_up
= !!(autoneg_status
& IXGBE_MDIO_AUTO_NEG_LINK_STATUS
);
2040 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2041 * @hw: point to hardware structure
2043 * Configures the link between the integrated KR PHY and the external X557 PHY
2044 * The driver will call this function when it gets a link status change
2045 * interrupt from the X557 PHY. This function configures the link speed
2046 * between the PHYs to match the link speed of the BASE-T link.
2048 * A return of a non-zero value indicates an error, and the base driver should
2049 * not report link up.
2051 static s32
ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw
*hw
)
2053 ixgbe_link_speed force_speed
;
2058 if (hw
->mac
.ops
.get_media_type(hw
) != ixgbe_media_type_copper
)
2059 return IXGBE_ERR_CONFIG
;
2061 if (hw
->phy
.nw_mng_if_sel
& IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE
) {
2062 speed
= IXGBE_LINK_SPEED_10GB_FULL
|
2063 IXGBE_LINK_SPEED_1GB_FULL
;
2064 return ixgbe_setup_kr_speed_x550em(hw
, speed
);
2067 /* If link is not up, then there is no setup necessary so return */
2068 status
= ixgbe_ext_phy_t_x550em_get_link(hw
, &link_up
);
2075 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT
,
2076 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
2081 /* If link is not still up, then no setup is necessary so return */
2082 status
= ixgbe_ext_phy_t_x550em_get_link(hw
, &link_up
);
2089 /* clear everything but the speed and duplex bits */
2090 speed
&= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK
;
2093 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL
:
2094 force_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
2096 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL
:
2097 force_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
2100 /* Internal PHY does not support anything else */
2101 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
2104 return ixgbe_setup_ixfi_x550em(hw
, &force_speed
);
2107 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2108 * @hw: pointer to hardware structure
2110 static s32
ixgbe_reset_phy_t_X550em(struct ixgbe_hw
*hw
)
2114 status
= ixgbe_reset_phy_generic(hw
);
2119 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2120 return ixgbe_enable_lasi_ext_t_x550em(hw
);
2124 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2125 * @hw: pointer to hardware structure
2126 * @led_idx: led number to turn on
2128 s32
ixgbe_led_on_t_x550em(struct ixgbe_hw
*hw
, u32 led_idx
)
2132 if (led_idx
>= IXGBE_X557_MAX_LED_INDEX
)
2133 return IXGBE_ERR_PARAM
;
2135 /* To turn on the LED, set mode to ON. */
2136 hw
->phy
.ops
.read_reg(hw
, IXGBE_X557_LED_PROVISIONING
+ led_idx
,
2137 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
, &phy_data
);
2138 phy_data
|= IXGBE_X557_LED_MANUAL_SET_MASK
;
2139 hw
->phy
.ops
.write_reg(hw
, IXGBE_X557_LED_PROVISIONING
+ led_idx
,
2140 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
, phy_data
);
2146 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2147 * @hw: pointer to hardware structure
2148 * @led_idx: led number to turn off
2150 s32
ixgbe_led_off_t_x550em(struct ixgbe_hw
*hw
, u32 led_idx
)
2154 if (led_idx
>= IXGBE_X557_MAX_LED_INDEX
)
2155 return IXGBE_ERR_PARAM
;
2157 /* To turn on the LED, set mode to ON. */
2158 hw
->phy
.ops
.read_reg(hw
, IXGBE_X557_LED_PROVISIONING
+ led_idx
,
2159 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
, &phy_data
);
2160 phy_data
&= ~IXGBE_X557_LED_MANUAL_SET_MASK
;
2161 hw
->phy
.ops
.write_reg(hw
, IXGBE_X557_LED_PROVISIONING
+ led_idx
,
2162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
, phy_data
);
2167 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2168 * @hw: pointer to hardware structure
2169 * @lcd_speed: pointer to lowest common link speed
2171 * Determine lowest common link speed with link partner.
2173 static s32
ixgbe_get_lcd_t_x550em(struct ixgbe_hw
*hw
,
2174 ixgbe_link_speed
*lcd_speed
)
2178 u16 word
= hw
->eeprom
.ctrl_word_3
;
2180 *lcd_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
2182 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_AUTO_NEG_LP_STATUS
,
2183 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
2188 /* If link partner advertised 1G, return 1G */
2189 if (an_lp_status
& IXGBE_AUTO_NEG_LP_1000BASE_CAP
) {
2190 *lcd_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
2194 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2195 if ((hw
->bus
.lan_id
&& (word
& NVM_INIT_CTRL_3_D10GMP_PORT1
)) ||
2196 (word
& NVM_INIT_CTRL_3_D10GMP_PORT0
))
2199 /* Link partner not capable of lower speeds, return 10G */
2200 *lcd_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
2205 * ixgbe_setup_fc_x550em - Set up flow control
2206 * @hw: pointer to hardware structure
2208 static s32
ixgbe_setup_fc_x550em(struct ixgbe_hw
*hw
)
2210 bool pause
, asm_dir
;
2214 /* Validate the requested mode */
2215 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
2216 hw_err(hw
, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2217 return IXGBE_ERR_INVALID_LINK_SETTINGS
;
2220 /* 10gig parts do not have a word in the EEPROM to determine the
2221 * default flow control setting, so we explicitly set it to full.
2223 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
2224 hw
->fc
.requested_mode
= ixgbe_fc_full
;
2226 /* Determine PAUSE and ASM_DIR bits. */
2227 switch (hw
->fc
.requested_mode
) {
2232 case ixgbe_fc_tx_pause
:
2236 case ixgbe_fc_rx_pause
:
2237 /* Rx Flow control is enabled and Tx Flow control is
2238 * disabled by software override. Since there really
2239 * isn't a way to advertise that we are capable of RX
2240 * Pause ONLY, we will advertise that we support both
2241 * symmetric and asymmetric Rx PAUSE, as such we fall
2242 * through to the fc_full statement. Later, we will
2243 * disable the adapter's ability to send PAUSE frames.
2251 hw_err(hw
, "Flow control param set incorrectly\n");
2252 return IXGBE_ERR_CONFIG
;
2255 if (hw
->device_id
!= IXGBE_DEV_ID_X550EM_X_KR
&&
2256 hw
->device_id
!= IXGBE_DEV_ID_X550EM_A_KR
&&
2257 hw
->device_id
!= IXGBE_DEV_ID_X550EM_A_KR_L
)
2260 rc
= hw
->mac
.ops
.read_iosf_sb_reg(hw
,
2261 IXGBE_KRM_AN_CNTL_1(hw
->bus
.lan_id
),
2262 IXGBE_SB_IOSF_TARGET_KR_PHY
,
2267 reg_val
&= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE
|
2268 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE
);
2270 reg_val
|= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE
;
2272 reg_val
|= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE
;
2273 rc
= hw
->mac
.ops
.write_iosf_sb_reg(hw
,
2274 IXGBE_KRM_AN_CNTL_1(hw
->bus
.lan_id
),
2275 IXGBE_SB_IOSF_TARGET_KR_PHY
,
2278 /* This device does not fully support AN. */
2279 hw
->fc
.disable_fc_autoneg
= true;
2284 /** ixgbe_enter_lplu_x550em - Transition to low power states
2285 * @hw: pointer to hardware structure
2287 * Configures Low Power Link Up on transition to low power states
2288 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
2289 * the X557 PHY immediately prior to entering LPLU.
2291 static s32
ixgbe_enter_lplu_t_x550em(struct ixgbe_hw
*hw
)
2293 u16 an_10g_cntl_reg
, autoneg_reg
, speed
;
2295 ixgbe_link_speed lcd_speed
;
2299 /* If blocked by MNG FW, then don't restart AN */
2300 if (ixgbe_check_reset_blocked(hw
))
2303 status
= ixgbe_ext_phy_t_x550em_get_link(hw
, &link_up
);
2307 status
= hw
->eeprom
.ops
.read(hw
, NVM_INIT_CTRL_3
,
2308 &hw
->eeprom
.ctrl_word_3
);
2312 /* If link is down, LPLU disabled in NVM, WoL disabled, or
2313 * manageability disabled, then force link down by entering
2316 if (!link_up
|| !(hw
->eeprom
.ctrl_word_3
& NVM_INIT_CTRL_3_LPLU
) ||
2317 !(hw
->wol_enabled
|| ixgbe_mng_present(hw
)))
2318 return ixgbe_set_copper_phy_power(hw
, false);
2321 status
= ixgbe_get_lcd_t_x550em(hw
, &lcd_speed
);
2325 /* If no valid LCD link speed, then force link down and exit. */
2326 if (lcd_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
2327 return ixgbe_set_copper_phy_power(hw
, false);
2329 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT
,
2330 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
2335 /* If no link now, speed is invalid so take link down */
2336 status
= ixgbe_ext_phy_t_x550em_get_link(hw
, &link_up
);
2338 return ixgbe_set_copper_phy_power(hw
, false);
2340 /* clear everything but the speed bits */
2341 speed
&= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK
;
2343 /* If current speed is already LCD, then exit. */
2344 if (((speed
== IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB
) &&
2345 (lcd_speed
== IXGBE_LINK_SPEED_1GB_FULL
)) ||
2346 ((speed
== IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB
) &&
2347 (lcd_speed
== IXGBE_LINK_SPEED_10GB_FULL
)))
2350 /* Clear AN completed indication */
2351 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM
,
2352 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
2357 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG
,
2358 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
2363 status
= hw
->phy
.ops
.read_reg(hw
,
2364 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG
,
2365 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
2370 save_autoneg
= hw
->phy
.autoneg_advertised
;
2372 /* Setup link at least common link speed */
2373 status
= hw
->mac
.ops
.setup_link(hw
, lcd_speed
, false);
2375 /* restore autoneg from before setting lplu speed */
2376 hw
->phy
.autoneg_advertised
= save_autoneg
;
2382 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2383 * @hw: pointer to hardware structure
2385 * Read NW_MNG_IF_SEL register and save field values.
2387 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw
*hw
)
2389 /* Save NW management interface connected on board. This is used
2390 * to determine internal PHY mode.
2392 hw
->phy
.nw_mng_if_sel
= IXGBE_READ_REG(hw
, IXGBE_NW_MNG_IF_SEL
);
2394 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2395 * PHY address. This register field was has only been used for X552.
2397 if (!hw
->phy
.nw_mng_if_sel
) {
2398 if (hw
->mac
.type
== ixgbe_mac_x550em_a
) {
2399 struct ixgbe_adapter
*adapter
= hw
->back
;
2401 e_warn(drv
, "nw_mng_if_sel not set\n");
2406 hw
->phy
.mdio
.prtad
= (hw
->phy
.nw_mng_if_sel
&
2407 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD
) >>
2408 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT
;
2411 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2412 * @hw: pointer to hardware structure
2414 * Initialize any function pointers that were not able to be
2415 * set during init_shared_code because the PHY/SFP type was
2416 * not known. Perform the SFP init if necessary.
2418 static s32
ixgbe_init_phy_ops_X550em(struct ixgbe_hw
*hw
)
2420 struct ixgbe_phy_info
*phy
= &hw
->phy
;
2423 hw
->mac
.ops
.set_lan_id(hw
);
2425 ixgbe_read_mng_if_sel_x550em(hw
);
2427 if (hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) {
2428 phy
->phy_semaphore_mask
= IXGBE_GSSR_SHARED_I2C_SM
;
2429 ixgbe_setup_mux_ctl(hw
);
2432 /* Identify the PHY or SFP module */
2433 ret_val
= phy
->ops
.identify(hw
);
2435 /* Setup function pointers based on detected hardware */
2436 ixgbe_init_mac_link_ops_X550em(hw
);
2437 if (phy
->sfp_type
!= ixgbe_sfp_type_unknown
)
2438 phy
->ops
.reset
= NULL
;
2440 /* Set functions pointers based on phy type */
2441 switch (hw
->phy
.type
) {
2442 case ixgbe_phy_x550em_kx4
:
2443 phy
->ops
.setup_link
= ixgbe_setup_kx4_x550em
;
2444 phy
->ops
.read_reg
= ixgbe_read_phy_reg_x550em
;
2445 phy
->ops
.write_reg
= ixgbe_write_phy_reg_x550em
;
2447 case ixgbe_phy_x550em_kr
:
2448 phy
->ops
.setup_link
= ixgbe_setup_kr_x550em
;
2449 phy
->ops
.read_reg
= ixgbe_read_phy_reg_x550em
;
2450 phy
->ops
.write_reg
= ixgbe_write_phy_reg_x550em
;
2452 case ixgbe_phy_x550em_ext_t
:
2453 /* Save NW management interface connected on board. This is used
2454 * to determine internal PHY mode
2456 phy
->nw_mng_if_sel
= IXGBE_READ_REG(hw
, IXGBE_NW_MNG_IF_SEL
);
2458 /* If internal link mode is XFI, then setup iXFI internal link,
2459 * else setup KR now.
2461 phy
->ops
.setup_internal_link
=
2462 ixgbe_setup_internal_phy_t_x550em
;
2464 /* setup SW LPLU only for first revision */
2465 if (hw
->mac
.type
== ixgbe_mac_X550EM_x
&&
2466 !(IXGBE_READ_REG(hw
, IXGBE_FUSES0_GROUP(0)) &
2467 IXGBE_FUSES0_REV_MASK
))
2468 phy
->ops
.enter_lplu
= ixgbe_enter_lplu_t_x550em
;
2470 phy
->ops
.handle_lasi
= ixgbe_handle_lasi_ext_t_x550em
;
2471 phy
->ops
.reset
= ixgbe_reset_phy_t_X550em
;
2480 /** ixgbe_get_media_type_X550em - Get media type
2481 * @hw: pointer to hardware structure
2483 * Returns the media type (fiber, copper, backplane)
2486 static enum ixgbe_media_type
ixgbe_get_media_type_X550em(struct ixgbe_hw
*hw
)
2488 enum ixgbe_media_type media_type
;
2490 /* Detect if there is a copper PHY attached. */
2491 switch (hw
->device_id
) {
2492 case IXGBE_DEV_ID_X550EM_A_SGMII
:
2493 case IXGBE_DEV_ID_X550EM_A_SGMII_L
:
2494 hw
->phy
.type
= ixgbe_phy_sgmii
;
2496 case IXGBE_DEV_ID_X550EM_X_KR
:
2497 case IXGBE_DEV_ID_X550EM_X_KX4
:
2498 case IXGBE_DEV_ID_X550EM_A_KR
:
2499 case IXGBE_DEV_ID_X550EM_A_KR_L
:
2500 media_type
= ixgbe_media_type_backplane
;
2502 case IXGBE_DEV_ID_X550EM_X_SFP
:
2503 case IXGBE_DEV_ID_X550EM_A_SFP
:
2504 case IXGBE_DEV_ID_X550EM_A_SFP_N
:
2505 media_type
= ixgbe_media_type_fiber
;
2507 case IXGBE_DEV_ID_X550EM_X_1G_T
:
2508 case IXGBE_DEV_ID_X550EM_X_10G_T
:
2509 case IXGBE_DEV_ID_X550EM_A_10G_T
:
2510 media_type
= ixgbe_media_type_copper
;
2513 media_type
= ixgbe_media_type_unknown
;
2519 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2520 ** @hw: pointer to hardware structure
2522 static s32
ixgbe_init_ext_t_x550em(struct ixgbe_hw
*hw
)
2527 status
= hw
->phy
.ops
.read_reg(hw
,
2528 IXGBE_MDIO_TX_VENDOR_ALARMS_3
,
2529 IXGBE_MDIO_PMA_PMD_DEV_TYPE
,
2534 /* If PHY FW reset completed bit is set then this is the first
2535 * SW instance after a power on so the PHY FW must be un-stalled.
2537 if (reg
& IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK
) {
2538 status
= hw
->phy
.ops
.read_reg(hw
,
2539 IXGBE_MDIO_GLOBAL_RES_PR_10
,
2540 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
2545 reg
&= ~IXGBE_MDIO_POWER_UP_STALL
;
2547 status
= hw
->phy
.ops
.write_reg(hw
,
2548 IXGBE_MDIO_GLOBAL_RES_PR_10
,
2549 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE
,
2559 * ixgbe_set_mdio_speed - Set MDIO clock speed
2560 * @hw: pointer to hardware structure
2562 static void ixgbe_set_mdio_speed(struct ixgbe_hw
*hw
)
2566 switch (hw
->device_id
) {
2567 case IXGBE_DEV_ID_X550EM_X_10G_T
:
2568 case IXGBE_DEV_ID_X550EM_A_SGMII
:
2569 case IXGBE_DEV_ID_X550EM_A_SGMII_L
:
2570 case IXGBE_DEV_ID_X550EM_A_10G_T
:
2571 case IXGBE_DEV_ID_X550EM_A_SFP
:
2572 /* Config MDIO clock speed before the first MDIO PHY access */
2573 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2574 hlreg0
&= ~IXGBE_HLREG0_MDCSPD
;
2575 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2582 /** ixgbe_reset_hw_X550em - Perform hardware reset
2583 ** @hw: pointer to hardware structure
2585 ** Resets the hardware by resetting the transmit and receive units, masks
2586 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2589 static s32
ixgbe_reset_hw_X550em(struct ixgbe_hw
*hw
)
2591 ixgbe_link_speed link_speed
;
2595 bool link_up
= false;
2597 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2598 status
= hw
->mac
.ops
.stop_adapter(hw
);
2602 /* flush pending Tx transactions */
2603 ixgbe_clear_tx_pending(hw
);
2605 /* PHY ops must be identified and initialized prior to reset */
2607 /* Identify PHY and related function pointers */
2608 status
= hw
->phy
.ops
.init(hw
);
2610 /* start the external PHY */
2611 if (hw
->phy
.type
== ixgbe_phy_x550em_ext_t
) {
2612 status
= ixgbe_init_ext_t_x550em(hw
);
2617 /* Setup SFP module if there is one present. */
2618 if (hw
->phy
.sfp_setup_needed
) {
2619 status
= hw
->mac
.ops
.setup_sfp(hw
);
2620 hw
->phy
.sfp_setup_needed
= false;
2624 if (!hw
->phy
.reset_disable
&& hw
->phy
.ops
.reset
)
2625 hw
->phy
.ops
.reset(hw
);
2628 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2629 * If link reset is used when link is up, it might reset the PHY when
2630 * mng is using it. If link is down or the flag to force full link
2631 * reset is set, then perform link reset.
2633 ctrl
= IXGBE_CTRL_LNK_RST
;
2635 if (!hw
->force_full_reset
) {
2636 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
2638 ctrl
= IXGBE_CTRL_RST
;
2641 ctrl
|= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
2642 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
2643 IXGBE_WRITE_FLUSH(hw
);
2644 usleep_range(1000, 1200);
2646 /* Poll for reset bit to self-clear meaning reset is complete */
2647 for (i
= 0; i
< 10; i
++) {
2648 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
2649 if (!(ctrl
& IXGBE_CTRL_RST_MASK
))
2654 if (ctrl
& IXGBE_CTRL_RST_MASK
) {
2655 status
= IXGBE_ERR_RESET_FAILED
;
2656 hw_dbg(hw
, "Reset polling failed to complete.\n");
2661 /* Double resets are required for recovery from certain error
2662 * clear the multicast table. Also reset num_rar_entries to 128,
2663 * since we modify this value when programming the SAN MAC address.
2665 if (hw
->mac
.flags
& IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
) {
2666 hw
->mac
.flags
&= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED
;
2670 /* Store the permanent mac address */
2671 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
2673 /* Store MAC address from RAR0, clear receive address registers, and
2674 * clear the multicast table. Also reset num_rar_entries to 128,
2675 * since we modify this value when programming the SAN MAC address.
2677 hw
->mac
.num_rar_entries
= 128;
2678 hw
->mac
.ops
.init_rx_addrs(hw
);
2680 ixgbe_set_mdio_speed(hw
);
2682 if (hw
->device_id
== IXGBE_DEV_ID_X550EM_X_SFP
)
2683 ixgbe_setup_mux_ctl(hw
);
2688 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2690 * @hw: pointer to hardware structure
2691 * @enable: enable or disable switch for Ethertype anti-spoofing
2692 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2694 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw
*hw
,
2695 bool enable
, int vf
)
2697 int vf_target_reg
= vf
>> 3;
2698 int vf_target_shift
= vf
% 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT
;
2701 pfvfspoof
= IXGBE_READ_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
));
2703 pfvfspoof
|= BIT(vf_target_shift
);
2705 pfvfspoof
&= ~BIT(vf_target_shift
);
2707 IXGBE_WRITE_REG(hw
, IXGBE_PFVFSPOOF(vf_target_reg
), pfvfspoof
);
2710 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2711 * @hw: pointer to hardware structure
2712 * @enable: enable or disable source address pruning
2713 * @pool: Rx pool to set source address pruning for
2715 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw
*hw
,
2721 /* max rx pool is 63 */
2725 pfflp
= (u64
)IXGBE_READ_REG(hw
, IXGBE_PFFLPL
);
2726 pfflp
|= (u64
)IXGBE_READ_REG(hw
, IXGBE_PFFLPH
) << 32;
2729 pfflp
|= (1ULL << pool
);
2731 pfflp
&= ~(1ULL << pool
);
2733 IXGBE_WRITE_REG(hw
, IXGBE_PFFLPL
, (u32
)pfflp
);
2734 IXGBE_WRITE_REG(hw
, IXGBE_PFFLPH
, (u32
)(pfflp
>> 32));
2738 * ixgbe_set_mux - Set mux for port 1 access with CS4227
2739 * @hw: pointer to hardware structure
2740 * @state: set mux if 1, clear if 0
2742 static void ixgbe_set_mux(struct ixgbe_hw
*hw
, u8 state
)
2746 if (!hw
->bus
.lan_id
)
2748 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
2750 esdp
|= IXGBE_ESDP_SDP1
;
2752 esdp
&= ~IXGBE_ESDP_SDP1
;
2753 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp
);
2754 IXGBE_WRITE_FLUSH(hw
);
2758 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2759 * @hw: pointer to hardware structure
2760 * @mask: Mask to specify which semaphore to acquire
2762 * Acquires the SWFW semaphore and sets the I2C MUX
2764 static s32
ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw
*hw
, u32 mask
)
2768 status
= ixgbe_acquire_swfw_sync_X540(hw
, mask
);
2772 if (mask
& IXGBE_GSSR_I2C_MASK
)
2773 ixgbe_set_mux(hw
, 1);
2779 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2780 * @hw: pointer to hardware structure
2781 * @mask: Mask to specify which semaphore to release
2783 * Releases the SWFW semaphore and sets the I2C MUX
2785 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw
*hw
, u32 mask
)
2787 if (mask
& IXGBE_GSSR_I2C_MASK
)
2788 ixgbe_set_mux(hw
, 0);
2790 ixgbe_release_swfw_sync_X540(hw
, mask
);
2794 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
2795 * @hw: pointer to hardware structure
2796 * @mask: Mask to specify which semaphore to acquire
2798 * Acquires the SWFW semaphore and get the shared PHY token as needed
2800 static s32
ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw
*hw
, u32 mask
)
2802 u32 hmask
= mask
& ~IXGBE_GSSR_TOKEN_SM
;
2803 int retries
= FW_PHY_TOKEN_RETRIES
;
2809 status
= ixgbe_acquire_swfw_sync_X540(hw
, hmask
);
2812 if (!(mask
& IXGBE_GSSR_TOKEN_SM
))
2815 status
= ixgbe_get_phy_token(hw
);
2819 ixgbe_release_swfw_sync_X540(hw
, hmask
);
2820 if (status
!= IXGBE_ERR_TOKEN_RETRY
)
2822 msleep(FW_PHY_TOKEN_DELAY
);
2829 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
2830 * @hw: pointer to hardware structure
2831 * @mask: Mask to specify which semaphore to release
2833 * Release the SWFW semaphore and puts the shared PHY token as needed
2835 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw
*hw
, u32 mask
)
2837 u32 hmask
= mask
& ~IXGBE_GSSR_TOKEN_SM
;
2839 if (mask
& IXGBE_GSSR_TOKEN_SM
)
2840 ixgbe_put_phy_token(hw
);
2843 ixgbe_release_swfw_sync_X540(hw
, hmask
);
2847 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
2848 * @hw: pointer to hardware structure
2849 * @reg_addr: 32 bit address of PHY register to read
2850 * @phy_data: Pointer to read data from PHY register
2852 * Reads a value from a specified PHY register using the SWFW lock and PHY
2853 * Token. The PHY Token is needed since the MDIO is shared between to MAC
2856 static s32
ixgbe_read_phy_reg_x550a(struct ixgbe_hw
*hw
, u32 reg_addr
,
2857 u32 device_type
, u16
*phy_data
)
2859 u32 mask
= hw
->phy
.phy_semaphore_mask
| IXGBE_GSSR_TOKEN_SM
;
2862 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, mask
))
2863 return IXGBE_ERR_SWFW_SYNC
;
2865 status
= hw
->phy
.ops
.read_reg_mdi(hw
, reg_addr
, device_type
, phy_data
);
2867 hw
->mac
.ops
.release_swfw_sync(hw
, mask
);
2873 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
2874 * @hw: pointer to hardware structure
2875 * @reg_addr: 32 bit PHY register to write
2876 * @device_type: 5 bit device type
2877 * @phy_data: Data to write to the PHY register
2879 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
2880 * The PHY Token is needed since the MDIO is shared between to MAC instances.
2882 static s32
ixgbe_write_phy_reg_x550a(struct ixgbe_hw
*hw
, u32 reg_addr
,
2883 u32 device_type
, u16 phy_data
)
2885 u32 mask
= hw
->phy
.phy_semaphore_mask
| IXGBE_GSSR_TOKEN_SM
;
2888 if (hw
->mac
.ops
.acquire_swfw_sync(hw
, mask
))
2889 return IXGBE_ERR_SWFW_SYNC
;
2891 status
= ixgbe_write_phy_reg_mdi(hw
, reg_addr
, device_type
, phy_data
);
2892 hw
->mac
.ops
.release_swfw_sync(hw
, mask
);
2897 #define X550_COMMON_MAC \
2898 .init_hw = &ixgbe_init_hw_generic, \
2899 .start_hw = &ixgbe_start_hw_X540, \
2900 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
2901 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
2902 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
2903 .get_device_caps = &ixgbe_get_device_caps_generic, \
2904 .stop_adapter = &ixgbe_stop_adapter_generic, \
2905 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
2906 .read_analog_reg8 = NULL, \
2907 .write_analog_reg8 = NULL, \
2908 .set_rxpba = &ixgbe_set_rxpba_generic, \
2909 .check_link = &ixgbe_check_mac_link_generic, \
2910 .blink_led_start = &ixgbe_blink_led_start_X540, \
2911 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
2912 .set_rar = &ixgbe_set_rar_generic, \
2913 .clear_rar = &ixgbe_clear_rar_generic, \
2914 .set_vmdq = &ixgbe_set_vmdq_generic, \
2915 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
2916 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
2917 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
2918 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
2919 .enable_mc = &ixgbe_enable_mc_generic, \
2920 .disable_mc = &ixgbe_disable_mc_generic, \
2921 .clear_vfta = &ixgbe_clear_vfta_generic, \
2922 .set_vfta = &ixgbe_set_vfta_generic, \
2923 .fc_enable = &ixgbe_fc_enable_generic, \
2924 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \
2925 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
2926 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
2927 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
2928 .set_source_address_pruning = \
2929 &ixgbe_set_source_address_pruning_X550, \
2930 .set_ethertype_anti_spoofing = \
2931 &ixgbe_set_ethertype_anti_spoofing_X550, \
2932 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
2933 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
2934 .get_thermal_sensor_data = NULL, \
2935 .init_thermal_sensor_thresh = NULL, \
2936 .enable_rx = &ixgbe_enable_rx_generic, \
2937 .disable_rx = &ixgbe_disable_rx_x550, \
2939 static const struct ixgbe_mac_operations mac_ops_X550 = {
2941 .led_on
= ixgbe_led_on_generic
,
2942 .led_off
= ixgbe_led_off_generic
,
2943 .reset_hw
= &ixgbe_reset_hw_X540
,
2944 .get_media_type
= &ixgbe_get_media_type_X540
,
2945 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
2946 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_generic
,
2947 .setup_link
= &ixgbe_setup_mac_link_X540
,
2948 .get_link_capabilities
= &ixgbe_get_copper_link_capabilities_generic
,
2949 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2951 .acquire_swfw_sync
= &ixgbe_acquire_swfw_sync_X540
,
2952 .release_swfw_sync
= &ixgbe_release_swfw_sync_X540
,
2953 .init_swfw_sync
= &ixgbe_init_swfw_sync_X540
,
2954 .prot_autoc_read
= prot_autoc_read_generic
,
2955 .prot_autoc_write
= prot_autoc_write_generic
,
2956 .setup_fc
= ixgbe_setup_fc_generic
,
2959 static const struct ixgbe_mac_operations mac_ops_X550EM_x
= {
2961 .led_on
= ixgbe_led_on_t_x550em
,
2962 .led_off
= ixgbe_led_off_t_x550em
,
2963 .reset_hw
= &ixgbe_reset_hw_X550em
,
2964 .get_media_type
= &ixgbe_get_media_type_X550em
,
2965 .get_san_mac_addr
= NULL
,
2966 .get_wwn_prefix
= NULL
,
2967 .setup_link
= &ixgbe_setup_mac_link_X540
,
2968 .get_link_capabilities
= &ixgbe_get_link_capabilities_X550em
,
2969 .get_bus_info
= &ixgbe_get_bus_info_X550em
,
2970 .setup_sfp
= ixgbe_setup_sfp_modules_X550em
,
2971 .acquire_swfw_sync
= &ixgbe_acquire_swfw_sync_X550em
,
2972 .release_swfw_sync
= &ixgbe_release_swfw_sync_X550em
,
2973 .init_swfw_sync
= &ixgbe_init_swfw_sync_X540
,
2974 .setup_fc
= NULL
, /* defined later */
2975 .read_iosf_sb_reg
= ixgbe_read_iosf_sb_reg_x550
,
2976 .write_iosf_sb_reg
= ixgbe_write_iosf_sb_reg_x550
,
2979 static struct ixgbe_mac_operations mac_ops_x550em_a
= {
2981 .led_on
= ixgbe_led_on_t_x550em
,
2982 .led_off
= ixgbe_led_off_t_x550em
,
2983 .reset_hw
= ixgbe_reset_hw_X550em
,
2984 .get_media_type
= ixgbe_get_media_type_X550em
,
2985 .get_san_mac_addr
= NULL
,
2986 .get_wwn_prefix
= NULL
,
2987 .setup_link
= NULL
, /* defined later */
2988 .get_link_capabilities
= ixgbe_get_link_capabilities_X550em
,
2989 .get_bus_info
= ixgbe_get_bus_info_X550em
,
2990 .setup_sfp
= ixgbe_setup_sfp_modules_X550em
,
2991 .acquire_swfw_sync
= ixgbe_acquire_swfw_sync_x550em_a
,
2992 .release_swfw_sync
= ixgbe_release_swfw_sync_x550em_a
,
2993 .setup_fc
= ixgbe_setup_fc_x550em
,
2994 .read_iosf_sb_reg
= ixgbe_read_iosf_sb_reg_x550a
,
2995 .write_iosf_sb_reg
= ixgbe_write_iosf_sb_reg_x550a
,
2998 #define X550_COMMON_EEP \
2999 .read = &ixgbe_read_ee_hostif_X550, \
3000 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3001 .write = &ixgbe_write_ee_hostif_X550, \
3002 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3003 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3004 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3005 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3007 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3009 .init_params
= &ixgbe_init_eeprom_params_X550
,
3012 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x
= {
3014 .init_params
= &ixgbe_init_eeprom_params_X540
,
3017 #define X550_COMMON_PHY \
3018 .identify_sfp = &ixgbe_identify_module_generic, \
3020 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3021 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3022 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3023 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3024 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3025 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3026 .setup_link = &ixgbe_setup_phy_link_generic, \
3027 .set_phy_power = NULL, \
3028 .check_overtemp = &ixgbe_tn_check_overtemp, \
3029 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
3031 static const struct ixgbe_phy_operations phy_ops_X550
= {
3034 .identify
= &ixgbe_identify_phy_generic
,
3035 .read_reg
= &ixgbe_read_phy_reg_generic
,
3036 .write_reg
= &ixgbe_write_phy_reg_generic
,
3039 static const struct ixgbe_phy_operations phy_ops_X550EM_x
= {
3041 .init
= &ixgbe_init_phy_ops_X550em
,
3042 .identify
= &ixgbe_identify_phy_x550em
,
3043 .read_reg
= &ixgbe_read_phy_reg_generic
,
3044 .write_reg
= &ixgbe_write_phy_reg_generic
,
3045 .read_i2c_combined
= &ixgbe_read_i2c_combined_generic
,
3046 .write_i2c_combined
= &ixgbe_write_i2c_combined_generic
,
3047 .read_i2c_combined_unlocked
= &ixgbe_read_i2c_combined_generic_unlocked
,
3048 .write_i2c_combined_unlocked
=
3049 &ixgbe_write_i2c_combined_generic_unlocked
,
3052 static const struct ixgbe_phy_operations phy_ops_x550em_a
= {
3054 .init
= &ixgbe_init_phy_ops_X550em
,
3055 .identify
= &ixgbe_identify_phy_x550em
,
3056 .read_reg
= &ixgbe_read_phy_reg_x550a
,
3057 .write_reg
= &ixgbe_write_phy_reg_x550a
,
3060 static const u32 ixgbe_mvals_X550
[IXGBE_MVALS_IDX_LIMIT
] = {
3061 IXGBE_MVALS_INIT(X550
)
3064 static const u32 ixgbe_mvals_X550EM_x
[IXGBE_MVALS_IDX_LIMIT
] = {
3065 IXGBE_MVALS_INIT(X550EM_x
)
3068 static const u32 ixgbe_mvals_x550em_a
[IXGBE_MVALS_IDX_LIMIT
] = {
3069 IXGBE_MVALS_INIT(X550EM_a
)
3072 const struct ixgbe_info ixgbe_X550_info
= {
3073 .mac
= ixgbe_mac_X550
,
3074 .get_invariants
= &ixgbe_get_invariants_X540
,
3075 .mac_ops
= &mac_ops_X550
,
3076 .eeprom_ops
= &eeprom_ops_X550
,
3077 .phy_ops
= &phy_ops_X550
,
3078 .mbx_ops
= &mbx_ops_generic
,
3079 .mvals
= ixgbe_mvals_X550
,
3082 const struct ixgbe_info ixgbe_X550EM_x_info
= {
3083 .mac
= ixgbe_mac_X550EM_x
,
3084 .get_invariants
= &ixgbe_get_invariants_X550_x
,
3085 .mac_ops
= &mac_ops_X550EM_x
,
3086 .eeprom_ops
= &eeprom_ops_X550EM_x
,
3087 .phy_ops
= &phy_ops_X550EM_x
,
3088 .mbx_ops
= &mbx_ops_generic
,
3089 .mvals
= ixgbe_mvals_X550EM_x
,
3092 const struct ixgbe_info ixgbe_x550em_a_info
= {
3093 .mac
= ixgbe_mac_x550em_a
,
3094 .get_invariants
= &ixgbe_get_invariants_X550_x
,
3095 .mac_ops
= &mac_ops_x550em_a
,
3096 .eeprom_ops
= &eeprom_ops_X550EM_x
,
3097 .phy_ops
= &phy_ops_x550em_a
,
3098 .mbx_ops
= &mbx_ops_generic
,
3099 .mvals
= ixgbe_mvals_x550em_a
,