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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[deliverable/linux.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
37 */
38
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40
41 #include <linux/init.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/in.h>
44 #include <linux/ip.h>
45 #include <net/tso.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
58 #include <linux/io.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
63 #include <linux/of.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
66 #include <linux/of_mdio.h>
67
68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
69 static char mv643xx_eth_driver_version[] = "1.4";
70
71
72 /*
73 * Registers shared between all ports.
74 */
75 #define PHY_ADDR 0x0000
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
81
82 /*
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
85 */
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define PORT_SERIAL_CONTROL1 0x004c
123 #define CLK125_BYPASS_EN 0x00000010
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
151
152 /*
153 * Misc per-port registers.
154 */
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
159
160
161 /*
162 * SDMA configuration register default value.
163 */
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
171 BLM_RX_NO_SWAP | \
172 BLM_TX_NO_SWAP | \
173 TX_BURST_SIZE_4_64BIT)
174 #else
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176 #endif
177
178
179 /*
180 * Misc definitions.
181 */
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 512
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
185
186 #define TSO_HEADER_SIZE 128
187
188 /*
189 * RX/TX descriptors.
190 */
191 #if defined(__BIG_ENDIAN)
192 struct rx_desc {
193 u16 byte_cnt; /* Descriptor buffer byte count */
194 u16 buf_size; /* Buffer size */
195 u32 cmd_sts; /* Descriptor command status */
196 u32 next_desc_ptr; /* Next descriptor pointer */
197 u32 buf_ptr; /* Descriptor buffer pointer */
198 };
199
200 struct tx_desc {
201 u16 byte_cnt; /* buffer byte count */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u32 cmd_sts; /* Command/status field */
204 u32 next_desc_ptr; /* Pointer to next descriptor */
205 u32 buf_ptr; /* pointer to buffer for this descriptor*/
206 };
207 #elif defined(__LITTLE_ENDIAN)
208 struct rx_desc {
209 u32 cmd_sts; /* Descriptor command status */
210 u16 buf_size; /* Buffer size */
211 u16 byte_cnt; /* Descriptor buffer byte count */
212 u32 buf_ptr; /* Descriptor buffer pointer */
213 u32 next_desc_ptr; /* Next descriptor pointer */
214 };
215
216 struct tx_desc {
217 u32 cmd_sts; /* Command/status field */
218 u16 l4i_chk; /* CPU provided TCP checksum */
219 u16 byte_cnt; /* buffer byte count */
220 u32 buf_ptr; /* pointer to buffer for this descriptor*/
221 u32 next_desc_ptr; /* Pointer to next descriptor */
222 };
223 #else
224 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
225 #endif
226
227 /* RX & TX descriptor command */
228 #define BUFFER_OWNED_BY_DMA 0x80000000
229
230 /* RX & TX descriptor status */
231 #define ERROR_SUMMARY 0x00000001
232
233 /* RX descriptor status */
234 #define LAYER_4_CHECKSUM_OK 0x40000000
235 #define RX_ENABLE_INTERRUPT 0x20000000
236 #define RX_FIRST_DESC 0x08000000
237 #define RX_LAST_DESC 0x04000000
238 #define RX_IP_HDR_OK 0x02000000
239 #define RX_PKT_IS_IPV4 0x01000000
240 #define RX_PKT_IS_ETHERNETV2 0x00800000
241 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
242 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
243 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
244
245 /* TX descriptor command */
246 #define TX_ENABLE_INTERRUPT 0x00800000
247 #define GEN_CRC 0x00400000
248 #define TX_FIRST_DESC 0x00200000
249 #define TX_LAST_DESC 0x00100000
250 #define ZERO_PADDING 0x00080000
251 #define GEN_IP_V4_CHECKSUM 0x00040000
252 #define GEN_TCP_UDP_CHECKSUM 0x00020000
253 #define UDP_FRAME 0x00010000
254 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
255 #define GEN_TCP_UDP_CHK_FULL 0x00000400
256 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
257
258 #define TX_IHL_SHIFT 11
259
260
261 /* global *******************************************************************/
262 struct mv643xx_eth_shared_private {
263 /*
264 * Ethernet controller base address.
265 */
266 void __iomem *base;
267
268 /*
269 * Per-port MBUS window access register value.
270 */
271 u32 win_protect;
272
273 /*
274 * Hardware-specific parameters.
275 */
276 int extended_rx_coal_limit;
277 int tx_bw_control;
278 int tx_csum_limit;
279 struct clk *clk;
280 };
281
282 #define TX_BW_CONTROL_ABSENT 0
283 #define TX_BW_CONTROL_OLD_LAYOUT 1
284 #define TX_BW_CONTROL_NEW_LAYOUT 2
285
286 static int mv643xx_eth_open(struct net_device *dev);
287 static int mv643xx_eth_stop(struct net_device *dev);
288
289
290 /* per-port *****************************************************************/
291 struct mib_counters {
292 u64 good_octets_received;
293 u32 bad_octets_received;
294 u32 internal_mac_transmit_err;
295 u32 good_frames_received;
296 u32 bad_frames_received;
297 u32 broadcast_frames_received;
298 u32 multicast_frames_received;
299 u32 frames_64_octets;
300 u32 frames_65_to_127_octets;
301 u32 frames_128_to_255_octets;
302 u32 frames_256_to_511_octets;
303 u32 frames_512_to_1023_octets;
304 u32 frames_1024_to_max_octets;
305 u64 good_octets_sent;
306 u32 good_frames_sent;
307 u32 excessive_collision;
308 u32 multicast_frames_sent;
309 u32 broadcast_frames_sent;
310 u32 unrec_mac_control_received;
311 u32 fc_sent;
312 u32 good_fc_received;
313 u32 bad_fc_received;
314 u32 undersize_received;
315 u32 fragments_received;
316 u32 oversize_received;
317 u32 jabber_received;
318 u32 mac_receive_error;
319 u32 bad_crc_event;
320 u32 collision;
321 u32 late_collision;
322 /* Non MIB hardware counters */
323 u32 rx_discard;
324 u32 rx_overrun;
325 };
326
327 struct rx_queue {
328 int index;
329
330 int rx_ring_size;
331
332 int rx_desc_count;
333 int rx_curr_desc;
334 int rx_used_desc;
335
336 struct rx_desc *rx_desc_area;
337 dma_addr_t rx_desc_dma;
338 int rx_desc_area_size;
339 struct sk_buff **rx_skb;
340 };
341
342 struct tx_queue {
343 int index;
344
345 int tx_ring_size;
346
347 int tx_desc_count;
348 int tx_curr_desc;
349 int tx_used_desc;
350
351 char *tso_hdrs;
352 dma_addr_t tso_hdrs_dma;
353
354 struct tx_desc *tx_desc_area;
355 dma_addr_t tx_desc_dma;
356 int tx_desc_area_size;
357
358 struct sk_buff_head tx_skb;
359
360 unsigned long tx_packets;
361 unsigned long tx_bytes;
362 unsigned long tx_dropped;
363 };
364
365 struct mv643xx_eth_private {
366 struct mv643xx_eth_shared_private *shared;
367 void __iomem *base;
368 int port_num;
369
370 struct net_device *dev;
371
372 struct phy_device *phy;
373
374 struct timer_list mib_counters_timer;
375 spinlock_t mib_counters_lock;
376 struct mib_counters mib_counters;
377
378 struct work_struct tx_timeout_task;
379
380 struct napi_struct napi;
381 u32 int_mask;
382 u8 oom;
383 u8 work_link;
384 u8 work_tx;
385 u8 work_tx_end;
386 u8 work_rx;
387 u8 work_rx_refill;
388
389 int skb_size;
390
391 /*
392 * RX state.
393 */
394 int rx_ring_size;
395 unsigned long rx_desc_sram_addr;
396 int rx_desc_sram_size;
397 int rxq_count;
398 struct timer_list rx_oom;
399 struct rx_queue rxq[8];
400
401 /*
402 * TX state.
403 */
404 int tx_ring_size;
405 unsigned long tx_desc_sram_addr;
406 int tx_desc_sram_size;
407 int txq_count;
408 struct tx_queue txq[8];
409
410 /*
411 * Hardware-specific parameters.
412 */
413 struct clk *clk;
414 unsigned int t_clk;
415 };
416
417
418 /* port register accessors **************************************************/
419 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
420 {
421 return readl(mp->shared->base + offset);
422 }
423
424 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
425 {
426 return readl(mp->base + offset);
427 }
428
429 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
430 {
431 writel(data, mp->shared->base + offset);
432 }
433
434 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
435 {
436 writel(data, mp->base + offset);
437 }
438
439
440 /* rxq/txq helper functions *************************************************/
441 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
442 {
443 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
444 }
445
446 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
447 {
448 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
449 }
450
451 static void rxq_enable(struct rx_queue *rxq)
452 {
453 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
454 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
455 }
456
457 static void rxq_disable(struct rx_queue *rxq)
458 {
459 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
460 u8 mask = 1 << rxq->index;
461
462 wrlp(mp, RXQ_COMMAND, mask << 8);
463 while (rdlp(mp, RXQ_COMMAND) & mask)
464 udelay(10);
465 }
466
467 static void txq_reset_hw_ptr(struct tx_queue *txq)
468 {
469 struct mv643xx_eth_private *mp = txq_to_mp(txq);
470 u32 addr;
471
472 addr = (u32)txq->tx_desc_dma;
473 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
474 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
475 }
476
477 static void txq_enable(struct tx_queue *txq)
478 {
479 struct mv643xx_eth_private *mp = txq_to_mp(txq);
480 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
481 }
482
483 static void txq_disable(struct tx_queue *txq)
484 {
485 struct mv643xx_eth_private *mp = txq_to_mp(txq);
486 u8 mask = 1 << txq->index;
487
488 wrlp(mp, TXQ_COMMAND, mask << 8);
489 while (rdlp(mp, TXQ_COMMAND) & mask)
490 udelay(10);
491 }
492
493 static void txq_maybe_wake(struct tx_queue *txq)
494 {
495 struct mv643xx_eth_private *mp = txq_to_mp(txq);
496 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
497
498 if (netif_tx_queue_stopped(nq)) {
499 __netif_tx_lock(nq, smp_processor_id());
500 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
501 netif_tx_wake_queue(nq);
502 __netif_tx_unlock(nq);
503 }
504 }
505
506 static int rxq_process(struct rx_queue *rxq, int budget)
507 {
508 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
509 struct net_device_stats *stats = &mp->dev->stats;
510 int rx;
511
512 rx = 0;
513 while (rx < budget && rxq->rx_desc_count) {
514 struct rx_desc *rx_desc;
515 unsigned int cmd_sts;
516 struct sk_buff *skb;
517 u16 byte_cnt;
518
519 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
520
521 cmd_sts = rx_desc->cmd_sts;
522 if (cmd_sts & BUFFER_OWNED_BY_DMA)
523 break;
524 rmb();
525
526 skb = rxq->rx_skb[rxq->rx_curr_desc];
527 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
528
529 rxq->rx_curr_desc++;
530 if (rxq->rx_curr_desc == rxq->rx_ring_size)
531 rxq->rx_curr_desc = 0;
532
533 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
534 rx_desc->buf_size, DMA_FROM_DEVICE);
535 rxq->rx_desc_count--;
536 rx++;
537
538 mp->work_rx_refill |= 1 << rxq->index;
539
540 byte_cnt = rx_desc->byte_cnt;
541
542 /*
543 * Update statistics.
544 *
545 * Note that the descriptor byte count includes 2 dummy
546 * bytes automatically inserted by the hardware at the
547 * start of the packet (which we don't count), and a 4
548 * byte CRC at the end of the packet (which we do count).
549 */
550 stats->rx_packets++;
551 stats->rx_bytes += byte_cnt - 2;
552
553 /*
554 * In case we received a packet without first / last bits
555 * on, or the error summary bit is set, the packet needs
556 * to be dropped.
557 */
558 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
559 != (RX_FIRST_DESC | RX_LAST_DESC))
560 goto err;
561
562 /*
563 * The -4 is for the CRC in the trailer of the
564 * received packet
565 */
566 skb_put(skb, byte_cnt - 2 - 4);
567
568 if (cmd_sts & LAYER_4_CHECKSUM_OK)
569 skb->ip_summed = CHECKSUM_UNNECESSARY;
570 skb->protocol = eth_type_trans(skb, mp->dev);
571
572 napi_gro_receive(&mp->napi, skb);
573
574 continue;
575
576 err:
577 stats->rx_dropped++;
578
579 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
580 (RX_FIRST_DESC | RX_LAST_DESC)) {
581 if (net_ratelimit())
582 netdev_err(mp->dev,
583 "received packet spanning multiple descriptors\n");
584 }
585
586 if (cmd_sts & ERROR_SUMMARY)
587 stats->rx_errors++;
588
589 dev_kfree_skb(skb);
590 }
591
592 if (rx < budget)
593 mp->work_rx &= ~(1 << rxq->index);
594
595 return rx;
596 }
597
598 static int rxq_refill(struct rx_queue *rxq, int budget)
599 {
600 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
601 int refilled;
602
603 refilled = 0;
604 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
605 struct sk_buff *skb;
606 int rx;
607 struct rx_desc *rx_desc;
608 int size;
609
610 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
611
612 if (skb == NULL) {
613 mp->oom = 1;
614 goto oom;
615 }
616
617 if (SKB_DMA_REALIGN)
618 skb_reserve(skb, SKB_DMA_REALIGN);
619
620 refilled++;
621 rxq->rx_desc_count++;
622
623 rx = rxq->rx_used_desc++;
624 if (rxq->rx_used_desc == rxq->rx_ring_size)
625 rxq->rx_used_desc = 0;
626
627 rx_desc = rxq->rx_desc_area + rx;
628
629 size = skb_end_pointer(skb) - skb->data;
630 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
631 skb->data, size,
632 DMA_FROM_DEVICE);
633 rx_desc->buf_size = size;
634 rxq->rx_skb[rx] = skb;
635 wmb();
636 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
637 wmb();
638
639 /*
640 * The hardware automatically prepends 2 bytes of
641 * dummy data to each received packet, so that the
642 * IP header ends up 16-byte aligned.
643 */
644 skb_reserve(skb, 2);
645 }
646
647 if (refilled < budget)
648 mp->work_rx_refill &= ~(1 << rxq->index);
649
650 oom:
651 return refilled;
652 }
653
654
655 /* tx ***********************************************************************/
656 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
657 {
658 int frag;
659
660 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
661 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
662
663 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
664 return 1;
665 }
666
667 return 0;
668 }
669
670 static inline __be16 sum16_as_be(__sum16 sum)
671 {
672 return (__force __be16)sum;
673 }
674
675 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
676 u16 *l4i_chk, u32 *command, int length)
677 {
678 int ret;
679 u32 cmd = 0;
680
681 if (skb->ip_summed == CHECKSUM_PARTIAL) {
682 int hdr_len;
683 int tag_bytes;
684
685 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
686 skb->protocol != htons(ETH_P_8021Q));
687
688 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
689 tag_bytes = hdr_len - ETH_HLEN;
690
691 if (length - hdr_len > mp->shared->tx_csum_limit ||
692 unlikely(tag_bytes & ~12)) {
693 ret = skb_checksum_help(skb);
694 if (!ret)
695 goto no_csum;
696 return ret;
697 }
698
699 if (tag_bytes & 4)
700 cmd |= MAC_HDR_EXTRA_4_BYTES;
701 if (tag_bytes & 8)
702 cmd |= MAC_HDR_EXTRA_8_BYTES;
703
704 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
705 GEN_IP_V4_CHECKSUM |
706 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
707
708 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
709 * it seems we don't need to pass the initial checksum. */
710 switch (ip_hdr(skb)->protocol) {
711 case IPPROTO_UDP:
712 cmd |= UDP_FRAME;
713 *l4i_chk = 0;
714 break;
715 case IPPROTO_TCP:
716 *l4i_chk = 0;
717 break;
718 default:
719 WARN(1, "protocol not supported");
720 }
721 } else {
722 no_csum:
723 /* Errata BTS #50, IHL must be 5 if no HW checksum */
724 cmd |= 5 << TX_IHL_SHIFT;
725 }
726 *command = cmd;
727 return 0;
728 }
729
730 static inline int
731 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
732 struct sk_buff *skb, char *data, int length,
733 bool last_tcp, bool is_last)
734 {
735 int tx_index;
736 u32 cmd_sts;
737 struct tx_desc *desc;
738
739 tx_index = txq->tx_curr_desc++;
740 if (txq->tx_curr_desc == txq->tx_ring_size)
741 txq->tx_curr_desc = 0;
742 desc = &txq->tx_desc_area[tx_index];
743
744 desc->l4i_chk = 0;
745 desc->byte_cnt = length;
746 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
747 length, DMA_TO_DEVICE);
748 if (unlikely(dma_mapping_error(dev->dev.parent, desc->buf_ptr))) {
749 WARN(1, "dma_map_single failed!\n");
750 return -ENOMEM;
751 }
752
753 cmd_sts = BUFFER_OWNED_BY_DMA;
754 if (last_tcp) {
755 /* last descriptor in the TCP packet */
756 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
757 /* last descriptor in SKB */
758 if (is_last)
759 cmd_sts |= TX_ENABLE_INTERRUPT;
760 }
761 desc->cmd_sts = cmd_sts;
762 return 0;
763 }
764
765 static inline void
766 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length)
767 {
768 struct mv643xx_eth_private *mp = txq_to_mp(txq);
769 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
770 int tx_index;
771 struct tx_desc *desc;
772 int ret;
773 u32 cmd_csum = 0;
774 u16 l4i_chk = 0;
775
776 tx_index = txq->tx_curr_desc;
777 desc = &txq->tx_desc_area[tx_index];
778
779 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
780 if (ret)
781 WARN(1, "failed to prepare checksum!");
782
783 /* Should we set this? Can't use the value from skb_tx_csum()
784 * as it's not the correct initial L4 checksum to use. */
785 desc->l4i_chk = 0;
786
787 desc->byte_cnt = hdr_len;
788 desc->buf_ptr = txq->tso_hdrs_dma +
789 txq->tx_curr_desc * TSO_HEADER_SIZE;
790 desc->cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
791 GEN_CRC;
792
793 txq->tx_curr_desc++;
794 if (txq->tx_curr_desc == txq->tx_ring_size)
795 txq->tx_curr_desc = 0;
796 }
797
798 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
799 struct net_device *dev)
800 {
801 struct mv643xx_eth_private *mp = txq_to_mp(txq);
802 int total_len, data_left, ret;
803 int desc_count = 0;
804 struct tso_t tso;
805 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
806
807 /* Count needed descriptors */
808 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
809 netdev_dbg(dev, "not enough descriptors for TSO!\n");
810 return -EBUSY;
811 }
812
813 /* Initialize the TSO handler, and prepare the first payload */
814 tso_start(skb, &tso);
815
816 total_len = skb->len - hdr_len;
817 while (total_len > 0) {
818 char *hdr;
819
820 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
821 total_len -= data_left;
822 desc_count++;
823
824 /* prepare packet headers: MAC + IP + TCP */
825 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
826 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
827 txq_put_hdr_tso(skb, txq, data_left);
828
829 while (data_left > 0) {
830 int size;
831 desc_count++;
832
833 size = min_t(int, tso.size, data_left);
834 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
835 size == data_left,
836 total_len == 0);
837 if (ret)
838 goto err_release;
839 data_left -= size;
840 tso_build_data(skb, &tso, size);
841 }
842 }
843
844 __skb_queue_tail(&txq->tx_skb, skb);
845 skb_tx_timestamp(skb);
846
847 /* clear TX_END status */
848 mp->work_tx_end &= ~(1 << txq->index);
849
850 /* ensure all descriptors are written before poking hardware */
851 wmb();
852 txq_enable(txq);
853 txq->tx_desc_count += desc_count;
854 return 0;
855 err_release:
856 /* TODO: Release all used data descriptors; header descriptors must not
857 * be DMA-unmapped.
858 */
859 return ret;
860 }
861
862 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
863 {
864 struct mv643xx_eth_private *mp = txq_to_mp(txq);
865 int nr_frags = skb_shinfo(skb)->nr_frags;
866 int frag;
867
868 for (frag = 0; frag < nr_frags; frag++) {
869 skb_frag_t *this_frag;
870 int tx_index;
871 struct tx_desc *desc;
872 void *addr;
873
874 this_frag = &skb_shinfo(skb)->frags[frag];
875 addr = page_address(this_frag->page.p) + this_frag->page_offset;
876 tx_index = txq->tx_curr_desc++;
877 if (txq->tx_curr_desc == txq->tx_ring_size)
878 txq->tx_curr_desc = 0;
879 desc = &txq->tx_desc_area[tx_index];
880
881 /*
882 * The last fragment will generate an interrupt
883 * which will free the skb on TX completion.
884 */
885 if (frag == nr_frags - 1) {
886 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
887 ZERO_PADDING | TX_LAST_DESC |
888 TX_ENABLE_INTERRUPT;
889 } else {
890 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
891 }
892
893 desc->l4i_chk = 0;
894 desc->byte_cnt = skb_frag_size(this_frag);
895 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, addr,
896 desc->byte_cnt, DMA_TO_DEVICE);
897 }
898 }
899
900 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
901 {
902 struct mv643xx_eth_private *mp = txq_to_mp(txq);
903 int nr_frags = skb_shinfo(skb)->nr_frags;
904 int tx_index;
905 struct tx_desc *desc;
906 u32 cmd_sts;
907 u16 l4i_chk;
908 int length, ret;
909
910 cmd_sts = 0;
911 l4i_chk = 0;
912
913 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
914 if (ret) {
915 dev_kfree_skb_any(skb);
916 return ret;
917 }
918 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
919
920 tx_index = txq->tx_curr_desc++;
921 if (txq->tx_curr_desc == txq->tx_ring_size)
922 txq->tx_curr_desc = 0;
923 desc = &txq->tx_desc_area[tx_index];
924
925 if (nr_frags) {
926 txq_submit_frag_skb(txq, skb);
927 length = skb_headlen(skb);
928 } else {
929 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
930 length = skb->len;
931 }
932
933 desc->l4i_chk = l4i_chk;
934 desc->byte_cnt = length;
935 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
936 length, DMA_TO_DEVICE);
937
938 __skb_queue_tail(&txq->tx_skb, skb);
939
940 skb_tx_timestamp(skb);
941
942 /* ensure all other descriptors are written before first cmd_sts */
943 wmb();
944 desc->cmd_sts = cmd_sts;
945
946 /* clear TX_END status */
947 mp->work_tx_end &= ~(1 << txq->index);
948
949 /* ensure all descriptors are written before poking hardware */
950 wmb();
951 txq_enable(txq);
952
953 txq->tx_desc_count += nr_frags + 1;
954
955 return 0;
956 }
957
958 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
959 {
960 struct mv643xx_eth_private *mp = netdev_priv(dev);
961 int length, queue, ret;
962 struct tx_queue *txq;
963 struct netdev_queue *nq;
964
965 queue = skb_get_queue_mapping(skb);
966 txq = mp->txq + queue;
967 nq = netdev_get_tx_queue(dev, queue);
968
969 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
970 txq->tx_dropped++;
971 netdev_printk(KERN_DEBUG, dev,
972 "failed to linearize skb with tiny unaligned fragment\n");
973 return NETDEV_TX_BUSY;
974 }
975
976 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
977 if (net_ratelimit())
978 netdev_err(dev, "tx queue full?!\n");
979 dev_kfree_skb_any(skb);
980 return NETDEV_TX_OK;
981 }
982
983 length = skb->len;
984
985 if (skb_is_gso(skb))
986 ret = txq_submit_tso(txq, skb, dev);
987 else
988 ret = txq_submit_skb(txq, skb);
989 if (!ret) {
990 int entries_left;
991
992 txq->tx_bytes += length;
993 txq->tx_packets++;
994
995 entries_left = txq->tx_ring_size - txq->tx_desc_count;
996 if (entries_left < MAX_SKB_FRAGS + 1)
997 netif_tx_stop_queue(nq);
998 } else if (ret == -EBUSY) {
999 return NETDEV_TX_BUSY;
1000 }
1001
1002 return NETDEV_TX_OK;
1003 }
1004
1005
1006 /* tx napi ******************************************************************/
1007 static void txq_kick(struct tx_queue *txq)
1008 {
1009 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1010 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1011 u32 hw_desc_ptr;
1012 u32 expected_ptr;
1013
1014 __netif_tx_lock(nq, smp_processor_id());
1015
1016 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1017 goto out;
1018
1019 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1020 expected_ptr = (u32)txq->tx_desc_dma +
1021 txq->tx_curr_desc * sizeof(struct tx_desc);
1022
1023 if (hw_desc_ptr != expected_ptr)
1024 txq_enable(txq);
1025
1026 out:
1027 __netif_tx_unlock(nq);
1028
1029 mp->work_tx_end &= ~(1 << txq->index);
1030 }
1031
1032 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1033 {
1034 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1035 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1036 int reclaimed;
1037
1038 __netif_tx_lock_bh(nq);
1039
1040 reclaimed = 0;
1041 while (reclaimed < budget && txq->tx_desc_count > 0) {
1042 int tx_index;
1043 struct tx_desc *desc;
1044 u32 cmd_sts;
1045 struct sk_buff *skb;
1046
1047 tx_index = txq->tx_used_desc;
1048 desc = &txq->tx_desc_area[tx_index];
1049 cmd_sts = desc->cmd_sts;
1050
1051 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1052 if (!force)
1053 break;
1054 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1055 }
1056
1057 txq->tx_used_desc = tx_index + 1;
1058 if (txq->tx_used_desc == txq->tx_ring_size)
1059 txq->tx_used_desc = 0;
1060
1061 reclaimed++;
1062 txq->tx_desc_count--;
1063
1064 skb = NULL;
1065 if (cmd_sts & TX_LAST_DESC)
1066 skb = __skb_dequeue(&txq->tx_skb);
1067
1068 if (cmd_sts & ERROR_SUMMARY) {
1069 netdev_info(mp->dev, "tx error\n");
1070 mp->dev->stats.tx_errors++;
1071 }
1072
1073 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
1074 desc->byte_cnt, DMA_TO_DEVICE);
1075 dev_kfree_skb(skb);
1076 }
1077
1078 __netif_tx_unlock_bh(nq);
1079
1080 if (reclaimed < budget)
1081 mp->work_tx &= ~(1 << txq->index);
1082
1083 return reclaimed;
1084 }
1085
1086
1087 /* tx rate control **********************************************************/
1088 /*
1089 * Set total maximum TX rate (shared by all TX queues for this port)
1090 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1091 */
1092 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1093 {
1094 int token_rate;
1095 int mtu;
1096 int bucket_size;
1097
1098 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1099 if (token_rate > 1023)
1100 token_rate = 1023;
1101
1102 mtu = (mp->dev->mtu + 255) >> 8;
1103 if (mtu > 63)
1104 mtu = 63;
1105
1106 bucket_size = (burst + 255) >> 8;
1107 if (bucket_size > 65535)
1108 bucket_size = 65535;
1109
1110 switch (mp->shared->tx_bw_control) {
1111 case TX_BW_CONTROL_OLD_LAYOUT:
1112 wrlp(mp, TX_BW_RATE, token_rate);
1113 wrlp(mp, TX_BW_MTU, mtu);
1114 wrlp(mp, TX_BW_BURST, bucket_size);
1115 break;
1116 case TX_BW_CONTROL_NEW_LAYOUT:
1117 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1118 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1119 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1120 break;
1121 }
1122 }
1123
1124 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1125 {
1126 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1127 int token_rate;
1128 int bucket_size;
1129
1130 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1131 if (token_rate > 1023)
1132 token_rate = 1023;
1133
1134 bucket_size = (burst + 255) >> 8;
1135 if (bucket_size > 65535)
1136 bucket_size = 65535;
1137
1138 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1139 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1140 }
1141
1142 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1143 {
1144 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1145 int off;
1146 u32 val;
1147
1148 /*
1149 * Turn on fixed priority mode.
1150 */
1151 off = 0;
1152 switch (mp->shared->tx_bw_control) {
1153 case TX_BW_CONTROL_OLD_LAYOUT:
1154 off = TXQ_FIX_PRIO_CONF;
1155 break;
1156 case TX_BW_CONTROL_NEW_LAYOUT:
1157 off = TXQ_FIX_PRIO_CONF_MOVED;
1158 break;
1159 }
1160
1161 if (off) {
1162 val = rdlp(mp, off);
1163 val |= 1 << txq->index;
1164 wrlp(mp, off, val);
1165 }
1166 }
1167
1168
1169 /* mii management interface *************************************************/
1170 static void mv643xx_adjust_pscr(struct mv643xx_eth_private *mp)
1171 {
1172 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1173 u32 autoneg_disable = FORCE_LINK_PASS |
1174 DISABLE_AUTO_NEG_SPEED_GMII |
1175 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1176 DISABLE_AUTO_NEG_FOR_DUPLEX;
1177
1178 if (mp->phy->autoneg == AUTONEG_ENABLE) {
1179 /* enable auto negotiation */
1180 pscr &= ~autoneg_disable;
1181 goto out_write;
1182 }
1183
1184 pscr |= autoneg_disable;
1185
1186 if (mp->phy->speed == SPEED_1000) {
1187 /* force gigabit, half duplex not supported */
1188 pscr |= SET_GMII_SPEED_TO_1000;
1189 pscr |= SET_FULL_DUPLEX_MODE;
1190 goto out_write;
1191 }
1192
1193 pscr &= ~SET_GMII_SPEED_TO_1000;
1194
1195 if (mp->phy->speed == SPEED_100)
1196 pscr |= SET_MII_SPEED_TO_100;
1197 else
1198 pscr &= ~SET_MII_SPEED_TO_100;
1199
1200 if (mp->phy->duplex == DUPLEX_FULL)
1201 pscr |= SET_FULL_DUPLEX_MODE;
1202 else
1203 pscr &= ~SET_FULL_DUPLEX_MODE;
1204
1205 out_write:
1206 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1207 }
1208
1209 /* statistics ***************************************************************/
1210 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1211 {
1212 struct mv643xx_eth_private *mp = netdev_priv(dev);
1213 struct net_device_stats *stats = &dev->stats;
1214 unsigned long tx_packets = 0;
1215 unsigned long tx_bytes = 0;
1216 unsigned long tx_dropped = 0;
1217 int i;
1218
1219 for (i = 0; i < mp->txq_count; i++) {
1220 struct tx_queue *txq = mp->txq + i;
1221
1222 tx_packets += txq->tx_packets;
1223 tx_bytes += txq->tx_bytes;
1224 tx_dropped += txq->tx_dropped;
1225 }
1226
1227 stats->tx_packets = tx_packets;
1228 stats->tx_bytes = tx_bytes;
1229 stats->tx_dropped = tx_dropped;
1230
1231 return stats;
1232 }
1233
1234 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1235 {
1236 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1237 }
1238
1239 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1240 {
1241 int i;
1242
1243 for (i = 0; i < 0x80; i += 4)
1244 mib_read(mp, i);
1245
1246 /* Clear non MIB hw counters also */
1247 rdlp(mp, RX_DISCARD_FRAME_CNT);
1248 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1249 }
1250
1251 static void mib_counters_update(struct mv643xx_eth_private *mp)
1252 {
1253 struct mib_counters *p = &mp->mib_counters;
1254
1255 spin_lock_bh(&mp->mib_counters_lock);
1256 p->good_octets_received += mib_read(mp, 0x00);
1257 p->bad_octets_received += mib_read(mp, 0x08);
1258 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1259 p->good_frames_received += mib_read(mp, 0x10);
1260 p->bad_frames_received += mib_read(mp, 0x14);
1261 p->broadcast_frames_received += mib_read(mp, 0x18);
1262 p->multicast_frames_received += mib_read(mp, 0x1c);
1263 p->frames_64_octets += mib_read(mp, 0x20);
1264 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1265 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1266 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1267 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1268 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1269 p->good_octets_sent += mib_read(mp, 0x38);
1270 p->good_frames_sent += mib_read(mp, 0x40);
1271 p->excessive_collision += mib_read(mp, 0x44);
1272 p->multicast_frames_sent += mib_read(mp, 0x48);
1273 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1274 p->unrec_mac_control_received += mib_read(mp, 0x50);
1275 p->fc_sent += mib_read(mp, 0x54);
1276 p->good_fc_received += mib_read(mp, 0x58);
1277 p->bad_fc_received += mib_read(mp, 0x5c);
1278 p->undersize_received += mib_read(mp, 0x60);
1279 p->fragments_received += mib_read(mp, 0x64);
1280 p->oversize_received += mib_read(mp, 0x68);
1281 p->jabber_received += mib_read(mp, 0x6c);
1282 p->mac_receive_error += mib_read(mp, 0x70);
1283 p->bad_crc_event += mib_read(mp, 0x74);
1284 p->collision += mib_read(mp, 0x78);
1285 p->late_collision += mib_read(mp, 0x7c);
1286 /* Non MIB hardware counters */
1287 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1288 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1289 spin_unlock_bh(&mp->mib_counters_lock);
1290 }
1291
1292 static void mib_counters_timer_wrapper(unsigned long _mp)
1293 {
1294 struct mv643xx_eth_private *mp = (void *)_mp;
1295 mib_counters_update(mp);
1296 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1297 }
1298
1299
1300 /* interrupt coalescing *****************************************************/
1301 /*
1302 * Hardware coalescing parameters are set in units of 64 t_clk
1303 * cycles. I.e.:
1304 *
1305 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1306 *
1307 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1308 *
1309 * In the ->set*() methods, we round the computed register value
1310 * to the nearest integer.
1311 */
1312 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1313 {
1314 u32 val = rdlp(mp, SDMA_CONFIG);
1315 u64 temp;
1316
1317 if (mp->shared->extended_rx_coal_limit)
1318 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1319 else
1320 temp = (val & 0x003fff00) >> 8;
1321
1322 temp *= 64000000;
1323 do_div(temp, mp->t_clk);
1324
1325 return (unsigned int)temp;
1326 }
1327
1328 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1329 {
1330 u64 temp;
1331 u32 val;
1332
1333 temp = (u64)usec * mp->t_clk;
1334 temp += 31999999;
1335 do_div(temp, 64000000);
1336
1337 val = rdlp(mp, SDMA_CONFIG);
1338 if (mp->shared->extended_rx_coal_limit) {
1339 if (temp > 0xffff)
1340 temp = 0xffff;
1341 val &= ~0x023fff80;
1342 val |= (temp & 0x8000) << 10;
1343 val |= (temp & 0x7fff) << 7;
1344 } else {
1345 if (temp > 0x3fff)
1346 temp = 0x3fff;
1347 val &= ~0x003fff00;
1348 val |= (temp & 0x3fff) << 8;
1349 }
1350 wrlp(mp, SDMA_CONFIG, val);
1351 }
1352
1353 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1354 {
1355 u64 temp;
1356
1357 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1358 temp *= 64000000;
1359 do_div(temp, mp->t_clk);
1360
1361 return (unsigned int)temp;
1362 }
1363
1364 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1365 {
1366 u64 temp;
1367
1368 temp = (u64)usec * mp->t_clk;
1369 temp += 31999999;
1370 do_div(temp, 64000000);
1371
1372 if (temp > 0x3fff)
1373 temp = 0x3fff;
1374
1375 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1376 }
1377
1378
1379 /* ethtool ******************************************************************/
1380 struct mv643xx_eth_stats {
1381 char stat_string[ETH_GSTRING_LEN];
1382 int sizeof_stat;
1383 int netdev_off;
1384 int mp_off;
1385 };
1386
1387 #define SSTAT(m) \
1388 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1389 offsetof(struct net_device, stats.m), -1 }
1390
1391 #define MIBSTAT(m) \
1392 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1393 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1394
1395 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1396 SSTAT(rx_packets),
1397 SSTAT(tx_packets),
1398 SSTAT(rx_bytes),
1399 SSTAT(tx_bytes),
1400 SSTAT(rx_errors),
1401 SSTAT(tx_errors),
1402 SSTAT(rx_dropped),
1403 SSTAT(tx_dropped),
1404 MIBSTAT(good_octets_received),
1405 MIBSTAT(bad_octets_received),
1406 MIBSTAT(internal_mac_transmit_err),
1407 MIBSTAT(good_frames_received),
1408 MIBSTAT(bad_frames_received),
1409 MIBSTAT(broadcast_frames_received),
1410 MIBSTAT(multicast_frames_received),
1411 MIBSTAT(frames_64_octets),
1412 MIBSTAT(frames_65_to_127_octets),
1413 MIBSTAT(frames_128_to_255_octets),
1414 MIBSTAT(frames_256_to_511_octets),
1415 MIBSTAT(frames_512_to_1023_octets),
1416 MIBSTAT(frames_1024_to_max_octets),
1417 MIBSTAT(good_octets_sent),
1418 MIBSTAT(good_frames_sent),
1419 MIBSTAT(excessive_collision),
1420 MIBSTAT(multicast_frames_sent),
1421 MIBSTAT(broadcast_frames_sent),
1422 MIBSTAT(unrec_mac_control_received),
1423 MIBSTAT(fc_sent),
1424 MIBSTAT(good_fc_received),
1425 MIBSTAT(bad_fc_received),
1426 MIBSTAT(undersize_received),
1427 MIBSTAT(fragments_received),
1428 MIBSTAT(oversize_received),
1429 MIBSTAT(jabber_received),
1430 MIBSTAT(mac_receive_error),
1431 MIBSTAT(bad_crc_event),
1432 MIBSTAT(collision),
1433 MIBSTAT(late_collision),
1434 MIBSTAT(rx_discard),
1435 MIBSTAT(rx_overrun),
1436 };
1437
1438 static int
1439 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1440 struct ethtool_cmd *cmd)
1441 {
1442 int err;
1443
1444 err = phy_read_status(mp->phy);
1445 if (err == 0)
1446 err = phy_ethtool_gset(mp->phy, cmd);
1447
1448 /*
1449 * The MAC does not support 1000baseT_Half.
1450 */
1451 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1452 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1453
1454 return err;
1455 }
1456
1457 static int
1458 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1459 struct ethtool_cmd *cmd)
1460 {
1461 u32 port_status;
1462
1463 port_status = rdlp(mp, PORT_STATUS);
1464
1465 cmd->supported = SUPPORTED_MII;
1466 cmd->advertising = ADVERTISED_MII;
1467 switch (port_status & PORT_SPEED_MASK) {
1468 case PORT_SPEED_10:
1469 ethtool_cmd_speed_set(cmd, SPEED_10);
1470 break;
1471 case PORT_SPEED_100:
1472 ethtool_cmd_speed_set(cmd, SPEED_100);
1473 break;
1474 case PORT_SPEED_1000:
1475 ethtool_cmd_speed_set(cmd, SPEED_1000);
1476 break;
1477 default:
1478 cmd->speed = -1;
1479 break;
1480 }
1481 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1482 cmd->port = PORT_MII;
1483 cmd->phy_address = 0;
1484 cmd->transceiver = XCVR_INTERNAL;
1485 cmd->autoneg = AUTONEG_DISABLE;
1486 cmd->maxtxpkt = 1;
1487 cmd->maxrxpkt = 1;
1488
1489 return 0;
1490 }
1491
1492 static void
1493 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1494 {
1495 struct mv643xx_eth_private *mp = netdev_priv(dev);
1496 wol->supported = 0;
1497 wol->wolopts = 0;
1498 if (mp->phy)
1499 phy_ethtool_get_wol(mp->phy, wol);
1500 }
1501
1502 static int
1503 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1504 {
1505 struct mv643xx_eth_private *mp = netdev_priv(dev);
1506 int err;
1507
1508 if (mp->phy == NULL)
1509 return -EOPNOTSUPP;
1510
1511 err = phy_ethtool_set_wol(mp->phy, wol);
1512 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1513 * this debugging hint is useful to have.
1514 */
1515 if (err == -EOPNOTSUPP)
1516 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1517 return err;
1518 }
1519
1520 static int
1521 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1522 {
1523 struct mv643xx_eth_private *mp = netdev_priv(dev);
1524
1525 if (mp->phy != NULL)
1526 return mv643xx_eth_get_settings_phy(mp, cmd);
1527 else
1528 return mv643xx_eth_get_settings_phyless(mp, cmd);
1529 }
1530
1531 static int
1532 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1533 {
1534 struct mv643xx_eth_private *mp = netdev_priv(dev);
1535 int ret;
1536
1537 if (mp->phy == NULL)
1538 return -EINVAL;
1539
1540 /*
1541 * The MAC does not support 1000baseT_Half.
1542 */
1543 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1544
1545 ret = phy_ethtool_sset(mp->phy, cmd);
1546 if (!ret)
1547 mv643xx_adjust_pscr(mp);
1548 return ret;
1549 }
1550
1551 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1552 struct ethtool_drvinfo *drvinfo)
1553 {
1554 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1555 sizeof(drvinfo->driver));
1556 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1557 sizeof(drvinfo->version));
1558 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1559 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1560 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1561 }
1562
1563 static int mv643xx_eth_nway_reset(struct net_device *dev)
1564 {
1565 struct mv643xx_eth_private *mp = netdev_priv(dev);
1566
1567 if (mp->phy == NULL)
1568 return -EINVAL;
1569
1570 return genphy_restart_aneg(mp->phy);
1571 }
1572
1573 static int
1574 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1575 {
1576 struct mv643xx_eth_private *mp = netdev_priv(dev);
1577
1578 ec->rx_coalesce_usecs = get_rx_coal(mp);
1579 ec->tx_coalesce_usecs = get_tx_coal(mp);
1580
1581 return 0;
1582 }
1583
1584 static int
1585 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1586 {
1587 struct mv643xx_eth_private *mp = netdev_priv(dev);
1588
1589 set_rx_coal(mp, ec->rx_coalesce_usecs);
1590 set_tx_coal(mp, ec->tx_coalesce_usecs);
1591
1592 return 0;
1593 }
1594
1595 static void
1596 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1597 {
1598 struct mv643xx_eth_private *mp = netdev_priv(dev);
1599
1600 er->rx_max_pending = 4096;
1601 er->tx_max_pending = 4096;
1602
1603 er->rx_pending = mp->rx_ring_size;
1604 er->tx_pending = mp->tx_ring_size;
1605 }
1606
1607 static int
1608 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1609 {
1610 struct mv643xx_eth_private *mp = netdev_priv(dev);
1611
1612 if (er->rx_mini_pending || er->rx_jumbo_pending)
1613 return -EINVAL;
1614
1615 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1616 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1617
1618 if (netif_running(dev)) {
1619 mv643xx_eth_stop(dev);
1620 if (mv643xx_eth_open(dev)) {
1621 netdev_err(dev,
1622 "fatal error on re-opening device after ring param change\n");
1623 return -ENOMEM;
1624 }
1625 }
1626
1627 return 0;
1628 }
1629
1630
1631 static int
1632 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1633 {
1634 struct mv643xx_eth_private *mp = netdev_priv(dev);
1635 bool rx_csum = features & NETIF_F_RXCSUM;
1636
1637 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1638
1639 return 0;
1640 }
1641
1642 static void mv643xx_eth_get_strings(struct net_device *dev,
1643 uint32_t stringset, uint8_t *data)
1644 {
1645 int i;
1646
1647 if (stringset == ETH_SS_STATS) {
1648 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1649 memcpy(data + i * ETH_GSTRING_LEN,
1650 mv643xx_eth_stats[i].stat_string,
1651 ETH_GSTRING_LEN);
1652 }
1653 }
1654 }
1655
1656 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1657 struct ethtool_stats *stats,
1658 uint64_t *data)
1659 {
1660 struct mv643xx_eth_private *mp = netdev_priv(dev);
1661 int i;
1662
1663 mv643xx_eth_get_stats(dev);
1664 mib_counters_update(mp);
1665
1666 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1667 const struct mv643xx_eth_stats *stat;
1668 void *p;
1669
1670 stat = mv643xx_eth_stats + i;
1671
1672 if (stat->netdev_off >= 0)
1673 p = ((void *)mp->dev) + stat->netdev_off;
1674 else
1675 p = ((void *)mp) + stat->mp_off;
1676
1677 data[i] = (stat->sizeof_stat == 8) ?
1678 *(uint64_t *)p : *(uint32_t *)p;
1679 }
1680 }
1681
1682 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1683 {
1684 if (sset == ETH_SS_STATS)
1685 return ARRAY_SIZE(mv643xx_eth_stats);
1686
1687 return -EOPNOTSUPP;
1688 }
1689
1690 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1691 .get_settings = mv643xx_eth_get_settings,
1692 .set_settings = mv643xx_eth_set_settings,
1693 .get_drvinfo = mv643xx_eth_get_drvinfo,
1694 .nway_reset = mv643xx_eth_nway_reset,
1695 .get_link = ethtool_op_get_link,
1696 .get_coalesce = mv643xx_eth_get_coalesce,
1697 .set_coalesce = mv643xx_eth_set_coalesce,
1698 .get_ringparam = mv643xx_eth_get_ringparam,
1699 .set_ringparam = mv643xx_eth_set_ringparam,
1700 .get_strings = mv643xx_eth_get_strings,
1701 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1702 .get_sset_count = mv643xx_eth_get_sset_count,
1703 .get_ts_info = ethtool_op_get_ts_info,
1704 .get_wol = mv643xx_eth_get_wol,
1705 .set_wol = mv643xx_eth_set_wol,
1706 };
1707
1708
1709 /* address handling *********************************************************/
1710 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1711 {
1712 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1713 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1714
1715 addr[0] = (mac_h >> 24) & 0xff;
1716 addr[1] = (mac_h >> 16) & 0xff;
1717 addr[2] = (mac_h >> 8) & 0xff;
1718 addr[3] = mac_h & 0xff;
1719 addr[4] = (mac_l >> 8) & 0xff;
1720 addr[5] = mac_l & 0xff;
1721 }
1722
1723 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1724 {
1725 wrlp(mp, MAC_ADDR_HIGH,
1726 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1727 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1728 }
1729
1730 static u32 uc_addr_filter_mask(struct net_device *dev)
1731 {
1732 struct netdev_hw_addr *ha;
1733 u32 nibbles;
1734
1735 if (dev->flags & IFF_PROMISC)
1736 return 0;
1737
1738 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1739 netdev_for_each_uc_addr(ha, dev) {
1740 if (memcmp(dev->dev_addr, ha->addr, 5))
1741 return 0;
1742 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1743 return 0;
1744
1745 nibbles |= 1 << (ha->addr[5] & 0x0f);
1746 }
1747
1748 return nibbles;
1749 }
1750
1751 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1752 {
1753 struct mv643xx_eth_private *mp = netdev_priv(dev);
1754 u32 port_config;
1755 u32 nibbles;
1756 int i;
1757
1758 uc_addr_set(mp, dev->dev_addr);
1759
1760 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1761
1762 nibbles = uc_addr_filter_mask(dev);
1763 if (!nibbles) {
1764 port_config |= UNICAST_PROMISCUOUS_MODE;
1765 nibbles = 0xffff;
1766 }
1767
1768 for (i = 0; i < 16; i += 4) {
1769 int off = UNICAST_TABLE(mp->port_num) + i;
1770 u32 v;
1771
1772 v = 0;
1773 if (nibbles & 1)
1774 v |= 0x00000001;
1775 if (nibbles & 2)
1776 v |= 0x00000100;
1777 if (nibbles & 4)
1778 v |= 0x00010000;
1779 if (nibbles & 8)
1780 v |= 0x01000000;
1781 nibbles >>= 4;
1782
1783 wrl(mp, off, v);
1784 }
1785
1786 wrlp(mp, PORT_CONFIG, port_config);
1787 }
1788
1789 static int addr_crc(unsigned char *addr)
1790 {
1791 int crc = 0;
1792 int i;
1793
1794 for (i = 0; i < 6; i++) {
1795 int j;
1796
1797 crc = (crc ^ addr[i]) << 8;
1798 for (j = 7; j >= 0; j--) {
1799 if (crc & (0x100 << j))
1800 crc ^= 0x107 << j;
1801 }
1802 }
1803
1804 return crc;
1805 }
1806
1807 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1808 {
1809 struct mv643xx_eth_private *mp = netdev_priv(dev);
1810 u32 *mc_spec;
1811 u32 *mc_other;
1812 struct netdev_hw_addr *ha;
1813 int i;
1814
1815 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1816 int port_num;
1817 u32 accept;
1818
1819 oom:
1820 port_num = mp->port_num;
1821 accept = 0x01010101;
1822 for (i = 0; i < 0x100; i += 4) {
1823 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1824 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1825 }
1826 return;
1827 }
1828
1829 mc_spec = kmalloc(0x200, GFP_ATOMIC);
1830 if (mc_spec == NULL)
1831 goto oom;
1832 mc_other = mc_spec + (0x100 >> 2);
1833
1834 memset(mc_spec, 0, 0x100);
1835 memset(mc_other, 0, 0x100);
1836
1837 netdev_for_each_mc_addr(ha, dev) {
1838 u8 *a = ha->addr;
1839 u32 *table;
1840 int entry;
1841
1842 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1843 table = mc_spec;
1844 entry = a[5];
1845 } else {
1846 table = mc_other;
1847 entry = addr_crc(a);
1848 }
1849
1850 table[entry >> 2] |= 1 << (8 * (entry & 3));
1851 }
1852
1853 for (i = 0; i < 0x100; i += 4) {
1854 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1855 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1856 }
1857
1858 kfree(mc_spec);
1859 }
1860
1861 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1862 {
1863 mv643xx_eth_program_unicast_filter(dev);
1864 mv643xx_eth_program_multicast_filter(dev);
1865 }
1866
1867 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1868 {
1869 struct sockaddr *sa = addr;
1870
1871 if (!is_valid_ether_addr(sa->sa_data))
1872 return -EADDRNOTAVAIL;
1873
1874 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1875
1876 netif_addr_lock_bh(dev);
1877 mv643xx_eth_program_unicast_filter(dev);
1878 netif_addr_unlock_bh(dev);
1879
1880 return 0;
1881 }
1882
1883
1884 /* rx/tx queue initialisation ***********************************************/
1885 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1886 {
1887 struct rx_queue *rxq = mp->rxq + index;
1888 struct rx_desc *rx_desc;
1889 int size;
1890 int i;
1891
1892 rxq->index = index;
1893
1894 rxq->rx_ring_size = mp->rx_ring_size;
1895
1896 rxq->rx_desc_count = 0;
1897 rxq->rx_curr_desc = 0;
1898 rxq->rx_used_desc = 0;
1899
1900 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1901
1902 if (index == 0 && size <= mp->rx_desc_sram_size) {
1903 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1904 mp->rx_desc_sram_size);
1905 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1906 } else {
1907 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1908 size, &rxq->rx_desc_dma,
1909 GFP_KERNEL);
1910 }
1911
1912 if (rxq->rx_desc_area == NULL) {
1913 netdev_err(mp->dev,
1914 "can't allocate rx ring (%d bytes)\n", size);
1915 goto out;
1916 }
1917 memset(rxq->rx_desc_area, 0, size);
1918
1919 rxq->rx_desc_area_size = size;
1920 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1921 GFP_KERNEL);
1922 if (rxq->rx_skb == NULL)
1923 goto out_free;
1924
1925 rx_desc = rxq->rx_desc_area;
1926 for (i = 0; i < rxq->rx_ring_size; i++) {
1927 int nexti;
1928
1929 nexti = i + 1;
1930 if (nexti == rxq->rx_ring_size)
1931 nexti = 0;
1932
1933 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1934 nexti * sizeof(struct rx_desc);
1935 }
1936
1937 return 0;
1938
1939
1940 out_free:
1941 if (index == 0 && size <= mp->rx_desc_sram_size)
1942 iounmap(rxq->rx_desc_area);
1943 else
1944 dma_free_coherent(mp->dev->dev.parent, size,
1945 rxq->rx_desc_area,
1946 rxq->rx_desc_dma);
1947
1948 out:
1949 return -ENOMEM;
1950 }
1951
1952 static void rxq_deinit(struct rx_queue *rxq)
1953 {
1954 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1955 int i;
1956
1957 rxq_disable(rxq);
1958
1959 for (i = 0; i < rxq->rx_ring_size; i++) {
1960 if (rxq->rx_skb[i]) {
1961 dev_kfree_skb(rxq->rx_skb[i]);
1962 rxq->rx_desc_count--;
1963 }
1964 }
1965
1966 if (rxq->rx_desc_count) {
1967 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
1968 rxq->rx_desc_count);
1969 }
1970
1971 if (rxq->index == 0 &&
1972 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1973 iounmap(rxq->rx_desc_area);
1974 else
1975 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
1976 rxq->rx_desc_area, rxq->rx_desc_dma);
1977
1978 kfree(rxq->rx_skb);
1979 }
1980
1981 static int txq_init(struct mv643xx_eth_private *mp, int index)
1982 {
1983 struct tx_queue *txq = mp->txq + index;
1984 struct tx_desc *tx_desc;
1985 int size;
1986 int i;
1987
1988 txq->index = index;
1989
1990 txq->tx_ring_size = mp->tx_ring_size;
1991
1992 txq->tx_desc_count = 0;
1993 txq->tx_curr_desc = 0;
1994 txq->tx_used_desc = 0;
1995
1996 size = txq->tx_ring_size * sizeof(struct tx_desc);
1997
1998 if (index == 0 && size <= mp->tx_desc_sram_size) {
1999 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2000 mp->tx_desc_sram_size);
2001 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2002 } else {
2003 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2004 size, &txq->tx_desc_dma,
2005 GFP_KERNEL);
2006 }
2007
2008 if (txq->tx_desc_area == NULL) {
2009 netdev_err(mp->dev,
2010 "can't allocate tx ring (%d bytes)\n", size);
2011 return -ENOMEM;
2012 }
2013 memset(txq->tx_desc_area, 0, size);
2014
2015 txq->tx_desc_area_size = size;
2016
2017 tx_desc = txq->tx_desc_area;
2018 for (i = 0; i < txq->tx_ring_size; i++) {
2019 struct tx_desc *txd = tx_desc + i;
2020 int nexti;
2021
2022 nexti = i + 1;
2023 if (nexti == txq->tx_ring_size)
2024 nexti = 0;
2025
2026 txd->cmd_sts = 0;
2027 txd->next_desc_ptr = txq->tx_desc_dma +
2028 nexti * sizeof(struct tx_desc);
2029 }
2030
2031 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2032 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2033 txq->tx_ring_size * TSO_HEADER_SIZE,
2034 &txq->tso_hdrs_dma, GFP_KERNEL);
2035 if (txq->tso_hdrs == NULL) {
2036 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2037 txq->tx_desc_area, txq->tx_desc_dma);
2038 return -ENOMEM;
2039 }
2040 skb_queue_head_init(&txq->tx_skb);
2041
2042 return 0;
2043 }
2044
2045 static void txq_deinit(struct tx_queue *txq)
2046 {
2047 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2048
2049 txq_disable(txq);
2050 txq_reclaim(txq, txq->tx_ring_size, 1);
2051
2052 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2053
2054 if (txq->index == 0 &&
2055 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2056 iounmap(txq->tx_desc_area);
2057 else
2058 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2059 txq->tx_desc_area, txq->tx_desc_dma);
2060 if (txq->tso_hdrs)
2061 dma_free_coherent(mp->dev->dev.parent,
2062 txq->tx_ring_size * TSO_HEADER_SIZE,
2063 txq->tso_hdrs, txq->tso_hdrs_dma);
2064 }
2065
2066
2067 /* netdev ops and related ***************************************************/
2068 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2069 {
2070 u32 int_cause;
2071 u32 int_cause_ext;
2072
2073 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2074 if (int_cause == 0)
2075 return 0;
2076
2077 int_cause_ext = 0;
2078 if (int_cause & INT_EXT) {
2079 int_cause &= ~INT_EXT;
2080 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2081 }
2082
2083 if (int_cause) {
2084 wrlp(mp, INT_CAUSE, ~int_cause);
2085 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2086 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2087 mp->work_rx |= (int_cause & INT_RX) >> 2;
2088 }
2089
2090 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2091 if (int_cause_ext) {
2092 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2093 if (int_cause_ext & INT_EXT_LINK_PHY)
2094 mp->work_link = 1;
2095 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2096 }
2097
2098 return 1;
2099 }
2100
2101 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2102 {
2103 struct net_device *dev = (struct net_device *)dev_id;
2104 struct mv643xx_eth_private *mp = netdev_priv(dev);
2105
2106 if (unlikely(!mv643xx_eth_collect_events(mp)))
2107 return IRQ_NONE;
2108
2109 wrlp(mp, INT_MASK, 0);
2110 napi_schedule(&mp->napi);
2111
2112 return IRQ_HANDLED;
2113 }
2114
2115 static void handle_link_event(struct mv643xx_eth_private *mp)
2116 {
2117 struct net_device *dev = mp->dev;
2118 u32 port_status;
2119 int speed;
2120 int duplex;
2121 int fc;
2122
2123 port_status = rdlp(mp, PORT_STATUS);
2124 if (!(port_status & LINK_UP)) {
2125 if (netif_carrier_ok(dev)) {
2126 int i;
2127
2128 netdev_info(dev, "link down\n");
2129
2130 netif_carrier_off(dev);
2131
2132 for (i = 0; i < mp->txq_count; i++) {
2133 struct tx_queue *txq = mp->txq + i;
2134
2135 txq_reclaim(txq, txq->tx_ring_size, 1);
2136 txq_reset_hw_ptr(txq);
2137 }
2138 }
2139 return;
2140 }
2141
2142 switch (port_status & PORT_SPEED_MASK) {
2143 case PORT_SPEED_10:
2144 speed = 10;
2145 break;
2146 case PORT_SPEED_100:
2147 speed = 100;
2148 break;
2149 case PORT_SPEED_1000:
2150 speed = 1000;
2151 break;
2152 default:
2153 speed = -1;
2154 break;
2155 }
2156 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2157 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2158
2159 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2160 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2161
2162 if (!netif_carrier_ok(dev))
2163 netif_carrier_on(dev);
2164 }
2165
2166 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2167 {
2168 struct mv643xx_eth_private *mp;
2169 int work_done;
2170
2171 mp = container_of(napi, struct mv643xx_eth_private, napi);
2172
2173 if (unlikely(mp->oom)) {
2174 mp->oom = 0;
2175 del_timer(&mp->rx_oom);
2176 }
2177
2178 work_done = 0;
2179 while (work_done < budget) {
2180 u8 queue_mask;
2181 int queue;
2182 int work_tbd;
2183
2184 if (mp->work_link) {
2185 mp->work_link = 0;
2186 handle_link_event(mp);
2187 work_done++;
2188 continue;
2189 }
2190
2191 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2192 if (likely(!mp->oom))
2193 queue_mask |= mp->work_rx_refill;
2194
2195 if (!queue_mask) {
2196 if (mv643xx_eth_collect_events(mp))
2197 continue;
2198 break;
2199 }
2200
2201 queue = fls(queue_mask) - 1;
2202 queue_mask = 1 << queue;
2203
2204 work_tbd = budget - work_done;
2205 if (work_tbd > 16)
2206 work_tbd = 16;
2207
2208 if (mp->work_tx_end & queue_mask) {
2209 txq_kick(mp->txq + queue);
2210 } else if (mp->work_tx & queue_mask) {
2211 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2212 txq_maybe_wake(mp->txq + queue);
2213 } else if (mp->work_rx & queue_mask) {
2214 work_done += rxq_process(mp->rxq + queue, work_tbd);
2215 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2216 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2217 } else {
2218 BUG();
2219 }
2220 }
2221
2222 if (work_done < budget) {
2223 if (mp->oom)
2224 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2225 napi_complete(napi);
2226 wrlp(mp, INT_MASK, mp->int_mask);
2227 }
2228
2229 return work_done;
2230 }
2231
2232 static inline void oom_timer_wrapper(unsigned long data)
2233 {
2234 struct mv643xx_eth_private *mp = (void *)data;
2235
2236 napi_schedule(&mp->napi);
2237 }
2238
2239 static void port_start(struct mv643xx_eth_private *mp)
2240 {
2241 u32 pscr;
2242 int i;
2243
2244 /*
2245 * Perform PHY reset, if there is a PHY.
2246 */
2247 if (mp->phy != NULL) {
2248 struct ethtool_cmd cmd;
2249
2250 mv643xx_eth_get_settings(mp->dev, &cmd);
2251 phy_init_hw(mp->phy);
2252 mv643xx_eth_set_settings(mp->dev, &cmd);
2253 phy_start(mp->phy);
2254 }
2255
2256 /*
2257 * Configure basic link parameters.
2258 */
2259 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2260
2261 pscr |= SERIAL_PORT_ENABLE;
2262 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2263
2264 pscr |= DO_NOT_FORCE_LINK_FAIL;
2265 if (mp->phy == NULL)
2266 pscr |= FORCE_LINK_PASS;
2267 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2268
2269 /*
2270 * Configure TX path and queues.
2271 */
2272 tx_set_rate(mp, 1000000000, 16777216);
2273 for (i = 0; i < mp->txq_count; i++) {
2274 struct tx_queue *txq = mp->txq + i;
2275
2276 txq_reset_hw_ptr(txq);
2277 txq_set_rate(txq, 1000000000, 16777216);
2278 txq_set_fixed_prio_mode(txq);
2279 }
2280
2281 /*
2282 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2283 * frames to RX queue #0, and include the pseudo-header when
2284 * calculating receive checksums.
2285 */
2286 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2287
2288 /*
2289 * Treat BPDUs as normal multicasts, and disable partition mode.
2290 */
2291 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2292
2293 /*
2294 * Add configured unicast addresses to address filter table.
2295 */
2296 mv643xx_eth_program_unicast_filter(mp->dev);
2297
2298 /*
2299 * Enable the receive queues.
2300 */
2301 for (i = 0; i < mp->rxq_count; i++) {
2302 struct rx_queue *rxq = mp->rxq + i;
2303 u32 addr;
2304
2305 addr = (u32)rxq->rx_desc_dma;
2306 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2307 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2308
2309 rxq_enable(rxq);
2310 }
2311 }
2312
2313 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2314 {
2315 int skb_size;
2316
2317 /*
2318 * Reserve 2+14 bytes for an ethernet header (the hardware
2319 * automatically prepends 2 bytes of dummy data to each
2320 * received packet), 16 bytes for up to four VLAN tags, and
2321 * 4 bytes for the trailing FCS -- 36 bytes total.
2322 */
2323 skb_size = mp->dev->mtu + 36;
2324
2325 /*
2326 * Make sure that the skb size is a multiple of 8 bytes, as
2327 * the lower three bits of the receive descriptor's buffer
2328 * size field are ignored by the hardware.
2329 */
2330 mp->skb_size = (skb_size + 7) & ~7;
2331
2332 /*
2333 * If NET_SKB_PAD is smaller than a cache line,
2334 * netdev_alloc_skb() will cause skb->data to be misaligned
2335 * to a cache line boundary. If this is the case, include
2336 * some extra space to allow re-aligning the data area.
2337 */
2338 mp->skb_size += SKB_DMA_REALIGN;
2339 }
2340
2341 static int mv643xx_eth_open(struct net_device *dev)
2342 {
2343 struct mv643xx_eth_private *mp = netdev_priv(dev);
2344 int err;
2345 int i;
2346
2347 wrlp(mp, INT_CAUSE, 0);
2348 wrlp(mp, INT_CAUSE_EXT, 0);
2349 rdlp(mp, INT_CAUSE_EXT);
2350
2351 err = request_irq(dev->irq, mv643xx_eth_irq,
2352 IRQF_SHARED, dev->name, dev);
2353 if (err) {
2354 netdev_err(dev, "can't assign irq\n");
2355 return -EAGAIN;
2356 }
2357
2358 mv643xx_eth_recalc_skb_size(mp);
2359
2360 napi_enable(&mp->napi);
2361
2362 mp->int_mask = INT_EXT;
2363
2364 for (i = 0; i < mp->rxq_count; i++) {
2365 err = rxq_init(mp, i);
2366 if (err) {
2367 while (--i >= 0)
2368 rxq_deinit(mp->rxq + i);
2369 goto out;
2370 }
2371
2372 rxq_refill(mp->rxq + i, INT_MAX);
2373 mp->int_mask |= INT_RX_0 << i;
2374 }
2375
2376 if (mp->oom) {
2377 mp->rx_oom.expires = jiffies + (HZ / 10);
2378 add_timer(&mp->rx_oom);
2379 }
2380
2381 for (i = 0; i < mp->txq_count; i++) {
2382 err = txq_init(mp, i);
2383 if (err) {
2384 while (--i >= 0)
2385 txq_deinit(mp->txq + i);
2386 goto out_free;
2387 }
2388 mp->int_mask |= INT_TX_END_0 << i;
2389 }
2390
2391 add_timer(&mp->mib_counters_timer);
2392 port_start(mp);
2393
2394 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2395 wrlp(mp, INT_MASK, mp->int_mask);
2396
2397 return 0;
2398
2399
2400 out_free:
2401 for (i = 0; i < mp->rxq_count; i++)
2402 rxq_deinit(mp->rxq + i);
2403 out:
2404 free_irq(dev->irq, dev);
2405
2406 return err;
2407 }
2408
2409 static void port_reset(struct mv643xx_eth_private *mp)
2410 {
2411 unsigned int data;
2412 int i;
2413
2414 for (i = 0; i < mp->rxq_count; i++)
2415 rxq_disable(mp->rxq + i);
2416 for (i = 0; i < mp->txq_count; i++)
2417 txq_disable(mp->txq + i);
2418
2419 while (1) {
2420 u32 ps = rdlp(mp, PORT_STATUS);
2421
2422 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2423 break;
2424 udelay(10);
2425 }
2426
2427 /* Reset the Enable bit in the Configuration Register */
2428 data = rdlp(mp, PORT_SERIAL_CONTROL);
2429 data &= ~(SERIAL_PORT_ENABLE |
2430 DO_NOT_FORCE_LINK_FAIL |
2431 FORCE_LINK_PASS);
2432 wrlp(mp, PORT_SERIAL_CONTROL, data);
2433 }
2434
2435 static int mv643xx_eth_stop(struct net_device *dev)
2436 {
2437 struct mv643xx_eth_private *mp = netdev_priv(dev);
2438 int i;
2439
2440 wrlp(mp, INT_MASK_EXT, 0x00000000);
2441 wrlp(mp, INT_MASK, 0x00000000);
2442 rdlp(mp, INT_MASK);
2443
2444 napi_disable(&mp->napi);
2445
2446 del_timer_sync(&mp->rx_oom);
2447
2448 netif_carrier_off(dev);
2449 if (mp->phy)
2450 phy_stop(mp->phy);
2451 free_irq(dev->irq, dev);
2452
2453 port_reset(mp);
2454 mv643xx_eth_get_stats(dev);
2455 mib_counters_update(mp);
2456 del_timer_sync(&mp->mib_counters_timer);
2457
2458 for (i = 0; i < mp->rxq_count; i++)
2459 rxq_deinit(mp->rxq + i);
2460 for (i = 0; i < mp->txq_count; i++)
2461 txq_deinit(mp->txq + i);
2462
2463 return 0;
2464 }
2465
2466 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2467 {
2468 struct mv643xx_eth_private *mp = netdev_priv(dev);
2469 int ret;
2470
2471 if (mp->phy == NULL)
2472 return -ENOTSUPP;
2473
2474 ret = phy_mii_ioctl(mp->phy, ifr, cmd);
2475 if (!ret)
2476 mv643xx_adjust_pscr(mp);
2477 return ret;
2478 }
2479
2480 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2481 {
2482 struct mv643xx_eth_private *mp = netdev_priv(dev);
2483
2484 if (new_mtu < 64 || new_mtu > 9500)
2485 return -EINVAL;
2486
2487 dev->mtu = new_mtu;
2488 mv643xx_eth_recalc_skb_size(mp);
2489 tx_set_rate(mp, 1000000000, 16777216);
2490
2491 if (!netif_running(dev))
2492 return 0;
2493
2494 /*
2495 * Stop and then re-open the interface. This will allocate RX
2496 * skbs of the new MTU.
2497 * There is a possible danger that the open will not succeed,
2498 * due to memory being full.
2499 */
2500 mv643xx_eth_stop(dev);
2501 if (mv643xx_eth_open(dev)) {
2502 netdev_err(dev,
2503 "fatal error on re-opening device after MTU change\n");
2504 }
2505
2506 return 0;
2507 }
2508
2509 static void tx_timeout_task(struct work_struct *ugly)
2510 {
2511 struct mv643xx_eth_private *mp;
2512
2513 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2514 if (netif_running(mp->dev)) {
2515 netif_tx_stop_all_queues(mp->dev);
2516 port_reset(mp);
2517 port_start(mp);
2518 netif_tx_wake_all_queues(mp->dev);
2519 }
2520 }
2521
2522 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2523 {
2524 struct mv643xx_eth_private *mp = netdev_priv(dev);
2525
2526 netdev_info(dev, "tx timeout\n");
2527
2528 schedule_work(&mp->tx_timeout_task);
2529 }
2530
2531 #ifdef CONFIG_NET_POLL_CONTROLLER
2532 static void mv643xx_eth_netpoll(struct net_device *dev)
2533 {
2534 struct mv643xx_eth_private *mp = netdev_priv(dev);
2535
2536 wrlp(mp, INT_MASK, 0x00000000);
2537 rdlp(mp, INT_MASK);
2538
2539 mv643xx_eth_irq(dev->irq, dev);
2540
2541 wrlp(mp, INT_MASK, mp->int_mask);
2542 }
2543 #endif
2544
2545
2546 /* platform glue ************************************************************/
2547 static void
2548 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2549 const struct mbus_dram_target_info *dram)
2550 {
2551 void __iomem *base = msp->base;
2552 u32 win_enable;
2553 u32 win_protect;
2554 int i;
2555
2556 for (i = 0; i < 6; i++) {
2557 writel(0, base + WINDOW_BASE(i));
2558 writel(0, base + WINDOW_SIZE(i));
2559 if (i < 4)
2560 writel(0, base + WINDOW_REMAP_HIGH(i));
2561 }
2562
2563 win_enable = 0x3f;
2564 win_protect = 0;
2565
2566 for (i = 0; i < dram->num_cs; i++) {
2567 const struct mbus_dram_window *cs = dram->cs + i;
2568
2569 writel((cs->base & 0xffff0000) |
2570 (cs->mbus_attr << 8) |
2571 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2572 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2573
2574 win_enable &= ~(1 << i);
2575 win_protect |= 3 << (2 * i);
2576 }
2577
2578 writel(win_enable, base + WINDOW_BAR_ENABLE);
2579 msp->win_protect = win_protect;
2580 }
2581
2582 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2583 {
2584 /*
2585 * Check whether we have a 14-bit coal limit field in bits
2586 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2587 * SDMA config register.
2588 */
2589 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2590 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2591 msp->extended_rx_coal_limit = 1;
2592 else
2593 msp->extended_rx_coal_limit = 0;
2594
2595 /*
2596 * Check whether the MAC supports TX rate control, and if
2597 * yes, whether its associated registers are in the old or
2598 * the new place.
2599 */
2600 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2601 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2602 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2603 } else {
2604 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2605 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2606 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2607 else
2608 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2609 }
2610 }
2611
2612 #if defined(CONFIG_OF)
2613 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2614 { .compatible = "marvell,orion-eth", },
2615 { .compatible = "marvell,kirkwood-eth", },
2616 { }
2617 };
2618 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2619 #endif
2620
2621 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2622 #define mv643xx_eth_property(_np, _name, _v) \
2623 do { \
2624 u32 tmp; \
2625 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2626 _v = tmp; \
2627 } while (0)
2628
2629 static struct platform_device *port_platdev[3];
2630
2631 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2632 struct device_node *pnp)
2633 {
2634 struct platform_device *ppdev;
2635 struct mv643xx_eth_platform_data ppd;
2636 struct resource res;
2637 const char *mac_addr;
2638 int ret;
2639 int dev_num = 0;
2640
2641 memset(&ppd, 0, sizeof(ppd));
2642 ppd.shared = pdev;
2643
2644 memset(&res, 0, sizeof(res));
2645 if (!of_irq_to_resource(pnp, 0, &res)) {
2646 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2647 return -EINVAL;
2648 }
2649
2650 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2651 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2652 return -EINVAL;
2653 }
2654
2655 if (ppd.port_number >= 3) {
2656 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2657 return -EINVAL;
2658 }
2659
2660 while (dev_num < 3 && port_platdev[dev_num])
2661 dev_num++;
2662
2663 if (dev_num == 3) {
2664 dev_err(&pdev->dev, "too many ports registered\n");
2665 return -EINVAL;
2666 }
2667
2668 mac_addr = of_get_mac_address(pnp);
2669 if (mac_addr)
2670 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2671
2672 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2673 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2674 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2675 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2676 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2677 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2678
2679 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2680 if (!ppd.phy_node) {
2681 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2682 of_property_read_u32(pnp, "speed", &ppd.speed);
2683 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2684 }
2685
2686 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2687 if (!ppdev)
2688 return -ENOMEM;
2689 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2690 ppdev->dev.of_node = pnp;
2691
2692 ret = platform_device_add_resources(ppdev, &res, 1);
2693 if (ret)
2694 goto port_err;
2695
2696 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2697 if (ret)
2698 goto port_err;
2699
2700 ret = platform_device_add(ppdev);
2701 if (ret)
2702 goto port_err;
2703
2704 port_platdev[dev_num] = ppdev;
2705
2706 return 0;
2707
2708 port_err:
2709 platform_device_put(ppdev);
2710 return ret;
2711 }
2712
2713 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2714 {
2715 struct mv643xx_eth_shared_platform_data *pd;
2716 struct device_node *pnp, *np = pdev->dev.of_node;
2717 int ret;
2718
2719 /* bail out if not registered from DT */
2720 if (!np)
2721 return 0;
2722
2723 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2724 if (!pd)
2725 return -ENOMEM;
2726 pdev->dev.platform_data = pd;
2727
2728 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2729
2730 for_each_available_child_of_node(np, pnp) {
2731 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2732 if (ret)
2733 return ret;
2734 }
2735 return 0;
2736 }
2737
2738 static void mv643xx_eth_shared_of_remove(void)
2739 {
2740 int n;
2741
2742 for (n = 0; n < 3; n++) {
2743 platform_device_del(port_platdev[n]);
2744 port_platdev[n] = NULL;
2745 }
2746 }
2747 #else
2748 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2749 {
2750 return 0;
2751 }
2752
2753 static inline void mv643xx_eth_shared_of_remove(void)
2754 {
2755 }
2756 #endif
2757
2758 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2759 {
2760 static int mv643xx_eth_version_printed;
2761 struct mv643xx_eth_shared_platform_data *pd;
2762 struct mv643xx_eth_shared_private *msp;
2763 const struct mbus_dram_target_info *dram;
2764 struct resource *res;
2765 int ret;
2766
2767 if (!mv643xx_eth_version_printed++)
2768 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2769 mv643xx_eth_driver_version);
2770
2771 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2772 if (res == NULL)
2773 return -EINVAL;
2774
2775 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2776 if (msp == NULL)
2777 return -ENOMEM;
2778 platform_set_drvdata(pdev, msp);
2779
2780 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2781 if (msp->base == NULL)
2782 return -ENOMEM;
2783
2784 msp->clk = devm_clk_get(&pdev->dev, NULL);
2785 if (!IS_ERR(msp->clk))
2786 clk_prepare_enable(msp->clk);
2787
2788 /*
2789 * (Re-)program MBUS remapping windows if we are asked to.
2790 */
2791 dram = mv_mbus_dram_info();
2792 if (dram)
2793 mv643xx_eth_conf_mbus_windows(msp, dram);
2794
2795 ret = mv643xx_eth_shared_of_probe(pdev);
2796 if (ret)
2797 return ret;
2798 pd = dev_get_platdata(&pdev->dev);
2799
2800 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2801 pd->tx_csum_limit : 9 * 1024;
2802 infer_hw_params(msp);
2803
2804 return 0;
2805 }
2806
2807 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2808 {
2809 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2810
2811 mv643xx_eth_shared_of_remove();
2812 if (!IS_ERR(msp->clk))
2813 clk_disable_unprepare(msp->clk);
2814 return 0;
2815 }
2816
2817 static struct platform_driver mv643xx_eth_shared_driver = {
2818 .probe = mv643xx_eth_shared_probe,
2819 .remove = mv643xx_eth_shared_remove,
2820 .driver = {
2821 .name = MV643XX_ETH_SHARED_NAME,
2822 .owner = THIS_MODULE,
2823 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2824 },
2825 };
2826
2827 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2828 {
2829 int addr_shift = 5 * mp->port_num;
2830 u32 data;
2831
2832 data = rdl(mp, PHY_ADDR);
2833 data &= ~(0x1f << addr_shift);
2834 data |= (phy_addr & 0x1f) << addr_shift;
2835 wrl(mp, PHY_ADDR, data);
2836 }
2837
2838 static int phy_addr_get(struct mv643xx_eth_private *mp)
2839 {
2840 unsigned int data;
2841
2842 data = rdl(mp, PHY_ADDR);
2843
2844 return (data >> (5 * mp->port_num)) & 0x1f;
2845 }
2846
2847 static void set_params(struct mv643xx_eth_private *mp,
2848 struct mv643xx_eth_platform_data *pd)
2849 {
2850 struct net_device *dev = mp->dev;
2851
2852 if (is_valid_ether_addr(pd->mac_addr))
2853 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2854 else
2855 uc_addr_get(mp, dev->dev_addr);
2856
2857 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2858 if (pd->rx_queue_size)
2859 mp->rx_ring_size = pd->rx_queue_size;
2860 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2861 mp->rx_desc_sram_size = pd->rx_sram_size;
2862
2863 mp->rxq_count = pd->rx_queue_count ? : 1;
2864
2865 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2866 if (pd->tx_queue_size)
2867 mp->tx_ring_size = pd->tx_queue_size;
2868 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2869 mp->tx_desc_sram_size = pd->tx_sram_size;
2870
2871 mp->txq_count = pd->tx_queue_count ? : 1;
2872 }
2873
2874 static void mv643xx_eth_adjust_link(struct net_device *dev)
2875 {
2876 struct mv643xx_eth_private *mp = netdev_priv(dev);
2877
2878 mv643xx_adjust_pscr(mp);
2879 }
2880
2881 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2882 int phy_addr)
2883 {
2884 struct phy_device *phydev;
2885 int start;
2886 int num;
2887 int i;
2888 char phy_id[MII_BUS_ID_SIZE + 3];
2889
2890 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2891 start = phy_addr_get(mp) & 0x1f;
2892 num = 32;
2893 } else {
2894 start = phy_addr & 0x1f;
2895 num = 1;
2896 }
2897
2898 /* Attempt to connect to the PHY using orion-mdio */
2899 phydev = ERR_PTR(-ENODEV);
2900 for (i = 0; i < num; i++) {
2901 int addr = (start + i) & 0x1f;
2902
2903 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2904 "orion-mdio-mii", addr);
2905
2906 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
2907 PHY_INTERFACE_MODE_GMII);
2908 if (!IS_ERR(phydev)) {
2909 phy_addr_set(mp, addr);
2910 break;
2911 }
2912 }
2913
2914 return phydev;
2915 }
2916
2917 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2918 {
2919 struct phy_device *phy = mp->phy;
2920
2921 if (speed == 0) {
2922 phy->autoneg = AUTONEG_ENABLE;
2923 phy->speed = 0;
2924 phy->duplex = 0;
2925 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2926 } else {
2927 phy->autoneg = AUTONEG_DISABLE;
2928 phy->advertising = 0;
2929 phy->speed = speed;
2930 phy->duplex = duplex;
2931 }
2932 phy_start_aneg(phy);
2933 }
2934
2935 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2936 {
2937 u32 pscr;
2938
2939 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2940 if (pscr & SERIAL_PORT_ENABLE) {
2941 pscr &= ~SERIAL_PORT_ENABLE;
2942 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2943 }
2944
2945 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2946 if (mp->phy == NULL) {
2947 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2948 if (speed == SPEED_1000)
2949 pscr |= SET_GMII_SPEED_TO_1000;
2950 else if (speed == SPEED_100)
2951 pscr |= SET_MII_SPEED_TO_100;
2952
2953 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2954
2955 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2956 if (duplex == DUPLEX_FULL)
2957 pscr |= SET_FULL_DUPLEX_MODE;
2958 }
2959
2960 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2961 }
2962
2963 static const struct net_device_ops mv643xx_eth_netdev_ops = {
2964 .ndo_open = mv643xx_eth_open,
2965 .ndo_stop = mv643xx_eth_stop,
2966 .ndo_start_xmit = mv643xx_eth_xmit,
2967 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2968 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
2969 .ndo_validate_addr = eth_validate_addr,
2970 .ndo_do_ioctl = mv643xx_eth_ioctl,
2971 .ndo_change_mtu = mv643xx_eth_change_mtu,
2972 .ndo_set_features = mv643xx_eth_set_features,
2973 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2974 .ndo_get_stats = mv643xx_eth_get_stats,
2975 #ifdef CONFIG_NET_POLL_CONTROLLER
2976 .ndo_poll_controller = mv643xx_eth_netpoll,
2977 #endif
2978 };
2979
2980 static int mv643xx_eth_probe(struct platform_device *pdev)
2981 {
2982 struct mv643xx_eth_platform_data *pd;
2983 struct mv643xx_eth_private *mp;
2984 struct net_device *dev;
2985 struct resource *res;
2986 int err;
2987
2988 pd = dev_get_platdata(&pdev->dev);
2989 if (pd == NULL) {
2990 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
2991 return -ENODEV;
2992 }
2993
2994 if (pd->shared == NULL) {
2995 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
2996 return -ENODEV;
2997 }
2998
2999 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3000 if (!dev)
3001 return -ENOMEM;
3002
3003 mp = netdev_priv(dev);
3004 platform_set_drvdata(pdev, mp);
3005
3006 mp->shared = platform_get_drvdata(pd->shared);
3007 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3008 mp->port_num = pd->port_number;
3009
3010 mp->dev = dev;
3011
3012 /* Kirkwood resets some registers on gated clocks. Especially
3013 * CLK125_BYPASS_EN must be cleared but is not available on
3014 * all other SoCs/System Controllers using this driver.
3015 */
3016 if (of_device_is_compatible(pdev->dev.of_node,
3017 "marvell,kirkwood-eth-port"))
3018 wrlp(mp, PORT_SERIAL_CONTROL1,
3019 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3020
3021 /*
3022 * Start with a default rate, and if there is a clock, allow
3023 * it to override the default.
3024 */
3025 mp->t_clk = 133000000;
3026 mp->clk = devm_clk_get(&pdev->dev, NULL);
3027 if (!IS_ERR(mp->clk)) {
3028 clk_prepare_enable(mp->clk);
3029 mp->t_clk = clk_get_rate(mp->clk);
3030 } else if (!IS_ERR(mp->shared->clk)) {
3031 mp->t_clk = clk_get_rate(mp->shared->clk);
3032 }
3033
3034 set_params(mp, pd);
3035 netif_set_real_num_tx_queues(dev, mp->txq_count);
3036 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3037
3038 err = 0;
3039 if (pd->phy_node) {
3040 mp->phy = of_phy_connect(mp->dev, pd->phy_node,
3041 mv643xx_eth_adjust_link, 0,
3042 PHY_INTERFACE_MODE_GMII);
3043 if (!mp->phy)
3044 err = -ENODEV;
3045 else
3046 phy_addr_set(mp, mp->phy->addr);
3047 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3048 mp->phy = phy_scan(mp, pd->phy_addr);
3049
3050 if (IS_ERR(mp->phy))
3051 err = PTR_ERR(mp->phy);
3052 else
3053 phy_init(mp, pd->speed, pd->duplex);
3054 }
3055 if (err == -ENODEV) {
3056 err = -EPROBE_DEFER;
3057 goto out;
3058 }
3059 if (err)
3060 goto out;
3061
3062 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3063
3064 init_pscr(mp, pd->speed, pd->duplex);
3065
3066
3067 mib_counters_clear(mp);
3068
3069 init_timer(&mp->mib_counters_timer);
3070 mp->mib_counters_timer.data = (unsigned long)mp;
3071 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
3072 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3073
3074 spin_lock_init(&mp->mib_counters_lock);
3075
3076 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3077
3078 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3079
3080 init_timer(&mp->rx_oom);
3081 mp->rx_oom.data = (unsigned long)mp;
3082 mp->rx_oom.function = oom_timer_wrapper;
3083
3084
3085 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3086 BUG_ON(!res);
3087 dev->irq = res->start;
3088
3089 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3090
3091 dev->watchdog_timeo = 2 * HZ;
3092 dev->base_addr = 0;
3093
3094 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3095 dev->vlan_features = dev->features;
3096
3097 dev->features |= NETIF_F_RXCSUM;
3098 dev->hw_features = dev->features;
3099
3100 dev->priv_flags |= IFF_UNICAST_FLT;
3101
3102 SET_NETDEV_DEV(dev, &pdev->dev);
3103
3104 if (mp->shared->win_protect)
3105 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3106
3107 netif_carrier_off(dev);
3108
3109 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3110
3111 set_rx_coal(mp, 250);
3112 set_tx_coal(mp, 0);
3113
3114 err = register_netdev(dev);
3115 if (err)
3116 goto out;
3117
3118 netdev_notice(dev, "port %d with MAC address %pM\n",
3119 mp->port_num, dev->dev_addr);
3120
3121 if (mp->tx_desc_sram_size > 0)
3122 netdev_notice(dev, "configured with sram\n");
3123
3124 return 0;
3125
3126 out:
3127 if (!IS_ERR(mp->clk))
3128 clk_disable_unprepare(mp->clk);
3129 free_netdev(dev);
3130
3131 return err;
3132 }
3133
3134 static int mv643xx_eth_remove(struct platform_device *pdev)
3135 {
3136 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3137
3138 unregister_netdev(mp->dev);
3139 if (mp->phy != NULL)
3140 phy_disconnect(mp->phy);
3141 cancel_work_sync(&mp->tx_timeout_task);
3142
3143 if (!IS_ERR(mp->clk))
3144 clk_disable_unprepare(mp->clk);
3145
3146 free_netdev(mp->dev);
3147
3148 return 0;
3149 }
3150
3151 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3152 {
3153 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3154
3155 /* Mask all interrupts on ethernet port */
3156 wrlp(mp, INT_MASK, 0);
3157 rdlp(mp, INT_MASK);
3158
3159 if (netif_running(mp->dev))
3160 port_reset(mp);
3161 }
3162
3163 static struct platform_driver mv643xx_eth_driver = {
3164 .probe = mv643xx_eth_probe,
3165 .remove = mv643xx_eth_remove,
3166 .shutdown = mv643xx_eth_shutdown,
3167 .driver = {
3168 .name = MV643XX_ETH_NAME,
3169 .owner = THIS_MODULE,
3170 },
3171 };
3172
3173 static int __init mv643xx_eth_init_module(void)
3174 {
3175 int rc;
3176
3177 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3178 if (!rc) {
3179 rc = platform_driver_register(&mv643xx_eth_driver);
3180 if (rc)
3181 platform_driver_unregister(&mv643xx_eth_shared_driver);
3182 }
3183
3184 return rc;
3185 }
3186 module_init(mv643xx_eth_init_module);
3187
3188 static void __exit mv643xx_eth_cleanup_module(void)
3189 {
3190 platform_driver_unregister(&mv643xx_eth_driver);
3191 platform_driver_unregister(&mv643xx_eth_shared_driver);
3192 }
3193 module_exit(mv643xx_eth_cleanup_module);
3194
3195 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3196 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3197 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3198 MODULE_LICENSE("GPL");
3199 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3200 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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