2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/hardirq.h>
38 #include <linux/export.h>
40 #include <linux/mlx4/cmd.h>
41 #include <linux/mlx4/cq.h>
46 #define MLX4_CQ_STATUS_OK ( 0 << 28)
47 #define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
48 #define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
49 #define MLX4_CQ_FLAG_CC ( 1 << 18)
50 #define MLX4_CQ_FLAG_OI ( 1 << 17)
51 #define MLX4_CQ_STATE_ARMED ( 9 << 8)
52 #define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
53 #define MLX4_EQ_STATE_FIRED (10 << 8)
55 void mlx4_cq_completion(struct mlx4_dev
*dev
, u32 cqn
)
59 cq
= radix_tree_lookup(&mlx4_priv(dev
)->cq_table
.tree
,
60 cqn
& (dev
->caps
.num_cqs
- 1));
62 mlx4_dbg(dev
, "Completion event for bogus CQ %08x\n", cqn
);
71 void mlx4_cq_event(struct mlx4_dev
*dev
, u32 cqn
, int event_type
)
73 struct mlx4_cq_table
*cq_table
= &mlx4_priv(dev
)->cq_table
;
76 spin_lock(&cq_table
->lock
);
78 cq
= radix_tree_lookup(&cq_table
->tree
, cqn
& (dev
->caps
.num_cqs
- 1));
80 atomic_inc(&cq
->refcount
);
82 spin_unlock(&cq_table
->lock
);
85 mlx4_warn(dev
, "Async event for bogus CQ %08x\n", cqn
);
89 cq
->event(cq
, event_type
);
91 if (atomic_dec_and_test(&cq
->refcount
))
95 static int mlx4_SW2HW_CQ(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
98 return mlx4_cmd(dev
, mailbox
->dma
, cq_num
, 0,
99 MLX4_CMD_SW2HW_CQ
, MLX4_CMD_TIME_CLASS_A
,
103 static int mlx4_MODIFY_CQ(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
104 int cq_num
, u32 opmod
)
106 return mlx4_cmd(dev
, mailbox
->dma
, cq_num
, opmod
, MLX4_CMD_MODIFY_CQ
,
107 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
110 static int mlx4_HW2SW_CQ(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
113 return mlx4_cmd_box(dev
, 0, mailbox
? mailbox
->dma
: 0,
114 cq_num
, mailbox
? 0 : 1, MLX4_CMD_HW2SW_CQ
,
115 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
118 int mlx4_cq_modify(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
,
119 u16 count
, u16 period
)
121 struct mlx4_cmd_mailbox
*mailbox
;
122 struct mlx4_cq_context
*cq_context
;
125 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
127 return PTR_ERR(mailbox
);
129 cq_context
= mailbox
->buf
;
130 cq_context
->cq_max_count
= cpu_to_be16(count
);
131 cq_context
->cq_period
= cpu_to_be16(period
);
133 err
= mlx4_MODIFY_CQ(dev
, mailbox
, cq
->cqn
, 1);
135 mlx4_free_cmd_mailbox(dev
, mailbox
);
138 EXPORT_SYMBOL_GPL(mlx4_cq_modify
);
140 int mlx4_cq_resize(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
,
141 int entries
, struct mlx4_mtt
*mtt
)
143 struct mlx4_cmd_mailbox
*mailbox
;
144 struct mlx4_cq_context
*cq_context
;
148 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
150 return PTR_ERR(mailbox
);
152 cq_context
= mailbox
->buf
;
153 cq_context
->logsize_usrpage
= cpu_to_be32(ilog2(entries
) << 24);
154 cq_context
->log_page_size
= mtt
->page_shift
- 12;
155 mtt_addr
= mlx4_mtt_addr(dev
, mtt
);
156 cq_context
->mtt_base_addr_h
= mtt_addr
>> 32;
157 cq_context
->mtt_base_addr_l
= cpu_to_be32(mtt_addr
& 0xffffffff);
159 err
= mlx4_MODIFY_CQ(dev
, mailbox
, cq
->cqn
, 0);
161 mlx4_free_cmd_mailbox(dev
, mailbox
);
164 EXPORT_SYMBOL_GPL(mlx4_cq_resize
);
166 int __mlx4_cq_alloc_icm(struct mlx4_dev
*dev
, int *cqn
)
168 struct mlx4_priv
*priv
= mlx4_priv(dev
);
169 struct mlx4_cq_table
*cq_table
= &priv
->cq_table
;
172 *cqn
= mlx4_bitmap_alloc(&cq_table
->bitmap
);
176 err
= mlx4_table_get(dev
, &cq_table
->table
, *cqn
);
180 err
= mlx4_table_get(dev
, &cq_table
->cmpt_table
, *cqn
);
186 mlx4_table_put(dev
, &cq_table
->table
, *cqn
);
189 mlx4_bitmap_free(&cq_table
->bitmap
, *cqn
, MLX4_NO_RR
);
193 static int mlx4_cq_alloc_icm(struct mlx4_dev
*dev
, int *cqn
)
198 if (mlx4_is_mfunc(dev
)) {
199 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_CQ
,
200 RES_OP_RESERVE_AND_MAP
, MLX4_CMD_ALLOC_RES
,
201 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
205 *cqn
= get_param_l(&out_param
);
209 return __mlx4_cq_alloc_icm(dev
, cqn
);
212 void __mlx4_cq_free_icm(struct mlx4_dev
*dev
, int cqn
)
214 struct mlx4_priv
*priv
= mlx4_priv(dev
);
215 struct mlx4_cq_table
*cq_table
= &priv
->cq_table
;
217 mlx4_table_put(dev
, &cq_table
->cmpt_table
, cqn
);
218 mlx4_table_put(dev
, &cq_table
->table
, cqn
);
219 mlx4_bitmap_free(&cq_table
->bitmap
, cqn
, MLX4_NO_RR
);
222 static void mlx4_cq_free_icm(struct mlx4_dev
*dev
, int cqn
)
227 if (mlx4_is_mfunc(dev
)) {
228 set_param_l(&in_param
, cqn
);
229 err
= mlx4_cmd(dev
, in_param
, RES_CQ
, RES_OP_RESERVE_AND_MAP
,
231 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
233 mlx4_warn(dev
, "Failed freeing cq:%d\n", cqn
);
235 __mlx4_cq_free_icm(dev
, cqn
);
238 int mlx4_cq_alloc(struct mlx4_dev
*dev
, int nent
,
239 struct mlx4_mtt
*mtt
, struct mlx4_uar
*uar
, u64 db_rec
,
240 struct mlx4_cq
*cq
, unsigned vector
, int collapsed
,
243 struct mlx4_priv
*priv
= mlx4_priv(dev
);
244 struct mlx4_cq_table
*cq_table
= &priv
->cq_table
;
245 struct mlx4_cmd_mailbox
*mailbox
;
246 struct mlx4_cq_context
*cq_context
;
250 if (vector
> dev
->caps
.num_comp_vectors
+ dev
->caps
.comp_pool
)
255 err
= mlx4_cq_alloc_icm(dev
, &cq
->cqn
);
259 spin_lock_irq(&cq_table
->lock
);
260 err
= radix_tree_insert(&cq_table
->tree
, cq
->cqn
, cq
);
261 spin_unlock_irq(&cq_table
->lock
);
265 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
266 if (IS_ERR(mailbox
)) {
267 err
= PTR_ERR(mailbox
);
271 cq_context
= mailbox
->buf
;
272 cq_context
->flags
= cpu_to_be32(!!collapsed
<< 18);
274 cq_context
->flags
|= cpu_to_be32(1 << 19);
276 cq_context
->logsize_usrpage
= cpu_to_be32((ilog2(nent
) << 24) | uar
->index
);
277 cq_context
->comp_eqn
= priv
->eq_table
.eq
[vector
].eqn
;
278 cq_context
->log_page_size
= mtt
->page_shift
- MLX4_ICM_PAGE_SHIFT
;
280 mtt_addr
= mlx4_mtt_addr(dev
, mtt
);
281 cq_context
->mtt_base_addr_h
= mtt_addr
>> 32;
282 cq_context
->mtt_base_addr_l
= cpu_to_be32(mtt_addr
& 0xffffffff);
283 cq_context
->db_rec_addr
= cpu_to_be64(db_rec
);
285 err
= mlx4_SW2HW_CQ(dev
, mailbox
, cq
->cqn
);
286 mlx4_free_cmd_mailbox(dev
, mailbox
);
293 atomic_set(&cq
->refcount
, 1);
294 init_completion(&cq
->free
);
296 cq
->irq
= priv
->eq_table
.eq
[cq
->vector
].irq
;
297 cq
->irq_affinity_change
= false;
302 spin_lock_irq(&cq_table
->lock
);
303 radix_tree_delete(&cq_table
->tree
, cq
->cqn
);
304 spin_unlock_irq(&cq_table
->lock
);
307 mlx4_cq_free_icm(dev
, cq
->cqn
);
311 EXPORT_SYMBOL_GPL(mlx4_cq_alloc
);
313 void mlx4_cq_free(struct mlx4_dev
*dev
, struct mlx4_cq
*cq
)
315 struct mlx4_priv
*priv
= mlx4_priv(dev
);
316 struct mlx4_cq_table
*cq_table
= &priv
->cq_table
;
319 err
= mlx4_HW2SW_CQ(dev
, NULL
, cq
->cqn
);
321 mlx4_warn(dev
, "HW2SW_CQ failed (%d) for CQN %06x\n", err
, cq
->cqn
);
323 synchronize_irq(priv
->eq_table
.eq
[cq
->vector
].irq
);
325 spin_lock_irq(&cq_table
->lock
);
326 radix_tree_delete(&cq_table
->tree
, cq
->cqn
);
327 spin_unlock_irq(&cq_table
->lock
);
329 if (atomic_dec_and_test(&cq
->refcount
))
331 wait_for_completion(&cq
->free
);
333 mlx4_cq_free_icm(dev
, cq
->cqn
);
335 EXPORT_SYMBOL_GPL(mlx4_cq_free
);
337 int mlx4_init_cq_table(struct mlx4_dev
*dev
)
339 struct mlx4_cq_table
*cq_table
= &mlx4_priv(dev
)->cq_table
;
342 spin_lock_init(&cq_table
->lock
);
343 INIT_RADIX_TREE(&cq_table
->tree
, GFP_ATOMIC
);
344 if (mlx4_is_slave(dev
))
347 err
= mlx4_bitmap_init(&cq_table
->bitmap
, dev
->caps
.num_cqs
,
348 dev
->caps
.num_cqs
- 1, dev
->caps
.reserved_cqs
, 0);
355 void mlx4_cleanup_cq_table(struct mlx4_dev
*dev
)
357 if (mlx4_is_slave(dev
))
359 /* Nothing to do to clean up radix_tree */
360 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->cq_table
.bitmap
);
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