projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
net/mlx4_core: Support more than 64 VFs
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/etherdevice.h>
36 #include <linux/mlx4/cmd.h>
37 #include <linux/module.h>
38 #include <linux/cache.h>
39
40 #include "fw.h"
41 #include "icm.h"
42
43 enum {
44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 };
48
49 extern void __buggy_use_of_MLX4_GET(void);
50 extern void __buggy_use_of_MLX4_PUT(void);
51
52 static bool enable_qos;
53 module_param(enable_qos, bool, 0444);
54 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
56 #define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68 #define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
80 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 {
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
86 [ 3] = "XRC transport",
87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
94 [12] = "Dual Port Different Protocol (DPDP) support",
95 [15] = "Big LSO headers",
96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
103 [25] = "Router support",
104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
106 [34] = "FCS header control",
107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
112 [53] = "Port ETS Scheduler support",
113 [55] = "Port link type sensing support",
114 [59] = "Port management change event support",
115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
122 if (fname[i] && (flags & (1LL << i)))
123 mlx4_dbg(dev, " %s\n", fname[i]);
124 }
125
126 static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127 {
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
131 [2] = "RSS XOR Hash Function support",
132 [3] = "Device managed flow steering support",
133 [4] = "Automatic MAC reassignment support",
134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support",
138 [9] = "Device managed flow steering IPoIB support",
139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
140 [11] = "MAD DEMUX (Secure-Host) support",
141 [12] = "Large cache line (>64B) CQE stride support",
142 [13] = "Large cache line (>64B) EQE stride support",
143 [14] = "Ethernet protocol control support",
144 [15] = "Ethernet Backplane autoneg support",
145 [16] = "CONFIG DEV support",
146 [17] = "Asymmetric EQs support",
147 [18] = "More than 80 VFs support"
148 };
149 int i;
150
151 for (i = 0; i < ARRAY_SIZE(fname); ++i)
152 if (fname[i] && (flags & (1LL << i)))
153 mlx4_dbg(dev, " %s\n", fname[i]);
154 }
155
156 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
157 {
158 struct mlx4_cmd_mailbox *mailbox;
159 u32 *inbox;
160 int err = 0;
161
162 #define MOD_STAT_CFG_IN_SIZE 0x100
163
164 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
165 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
166
167 mailbox = mlx4_alloc_cmd_mailbox(dev);
168 if (IS_ERR(mailbox))
169 return PTR_ERR(mailbox);
170 inbox = mailbox->buf;
171
172 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
173 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
174
175 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
176 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
177
178 mlx4_free_cmd_mailbox(dev, mailbox);
179 return err;
180 }
181
182 int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
183 {
184 struct mlx4_cmd_mailbox *mailbox;
185 u32 *outbox;
186 u8 in_modifier;
187 u8 field;
188 u16 field16;
189 int err;
190
191 #define QUERY_FUNC_BUS_OFFSET 0x00
192 #define QUERY_FUNC_DEVICE_OFFSET 0x01
193 #define QUERY_FUNC_FUNCTION_OFFSET 0x01
194 #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
195 #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
196 #define QUERY_FUNC_MAX_EQ_OFFSET 0x06
197 #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
198
199 mailbox = mlx4_alloc_cmd_mailbox(dev);
200 if (IS_ERR(mailbox))
201 return PTR_ERR(mailbox);
202 outbox = mailbox->buf;
203
204 in_modifier = slave;
205
206 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
207 MLX4_CMD_QUERY_FUNC,
208 MLX4_CMD_TIME_CLASS_A,
209 MLX4_CMD_NATIVE);
210 if (err)
211 goto out;
212
213 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
214 func->bus = field & 0xf;
215 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
216 func->device = field & 0xf1;
217 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
218 func->function = field & 0x7;
219 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
220 func->physical_function = field & 0xf;
221 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
222 func->rsvd_eqs = field16 & 0xffff;
223 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
224 func->max_eq = field16 & 0xffff;
225 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
226 func->rsvd_uars = field & 0x0f;
227
228 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
229 func->bus, func->device, func->function, func->physical_function,
230 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
231
232 out:
233 mlx4_free_cmd_mailbox(dev, mailbox);
234 return err;
235 }
236
237 int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
238 struct mlx4_vhcr *vhcr,
239 struct mlx4_cmd_mailbox *inbox,
240 struct mlx4_cmd_mailbox *outbox,
241 struct mlx4_cmd_info *cmd)
242 {
243 struct mlx4_priv *priv = mlx4_priv(dev);
244 u8 field, port;
245 u32 size, proxy_qp, qkey;
246 int err = 0;
247 struct mlx4_func func;
248
249 #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
250 #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
251 #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
252 #define QUERY_FUNC_CAP_FMR_OFFSET 0x8
253 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
254 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
255 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
256 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
257 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
258 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
259 #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
260 #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
261
262 #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
263 #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
264 #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
265 #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
266 #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
267 #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
268
269 #define QUERY_FUNC_CAP_FMR_FLAG 0x80
270 #define QUERY_FUNC_CAP_FLAG_RDMA 0x40
271 #define QUERY_FUNC_CAP_FLAG_ETH 0x80
272 #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
273
274 /* when opcode modifier = 1 */
275 #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
276 #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
277 #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
278 #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
279
280 #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
281 #define QUERY_FUNC_CAP_QP0_PROXY 0x14
282 #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
283 #define QUERY_FUNC_CAP_QP1_PROXY 0x1c
284 #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
285
286 #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
287 #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
288 #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
289 #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
290
291 #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
292 #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
293
294 if (vhcr->op_modifier == 1) {
295 struct mlx4_active_ports actv_ports =
296 mlx4_get_active_ports(dev, slave);
297 int converted_port = mlx4_slave_convert_port(
298 dev, slave, vhcr->in_modifier);
299
300 if (converted_port < 0)
301 return -EINVAL;
302
303 vhcr->in_modifier = converted_port;
304 /* phys-port = logical-port */
305 field = vhcr->in_modifier -
306 find_first_bit(actv_ports.ports, dev->caps.num_ports);
307 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
308
309 port = vhcr->in_modifier;
310 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
311
312 /* Set nic_info bit to mark new fields support */
313 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
314
315 if (mlx4_vf_smi_enabled(dev, slave, port) &&
316 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
317 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
318 MLX4_PUT(outbox->buf, qkey,
319 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
320 }
321 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
322
323 /* size is now the QP number */
324 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
325 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
326
327 size += 2;
328 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
329
330 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
331 proxy_qp += 2;
332 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
333
334 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
335 QUERY_FUNC_CAP_PHYS_PORT_ID);
336
337 } else if (vhcr->op_modifier == 0) {
338 struct mlx4_active_ports actv_ports =
339 mlx4_get_active_ports(dev, slave);
340 /* enable rdma and ethernet interfaces, and new quota locations */
341 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
342 QUERY_FUNC_CAP_FLAG_QUOTAS);
343 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
344
345 field = min(
346 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
347 dev->caps.num_ports);
348 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
349
350 size = dev->caps.function_caps; /* set PF behaviours */
351 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
352
353 field = 0; /* protected FMR support not available as yet */
354 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
355
356 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
357 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
358 size = dev->caps.num_qps;
359 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
360
361 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
362 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
363 size = dev->caps.num_srqs;
364 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
365
366 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
367 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
368 size = dev->caps.num_cqs;
369 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
370
371 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
372 mlx4_QUERY_FUNC(dev, &func, slave)) {
373 size = vhcr->in_modifier &
374 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
375 dev->caps.num_eqs :
376 rounddown_pow_of_two(dev->caps.num_eqs);
377 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
378 size = dev->caps.reserved_eqs;
379 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
380 } else {
381 size = vhcr->in_modifier &
382 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
383 func.max_eq :
384 rounddown_pow_of_two(func.max_eq);
385 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
386 size = func.rsvd_eqs;
387 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
388 }
389
390 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
391 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
392 size = dev->caps.num_mpts;
393 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
394
395 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
396 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
397 size = dev->caps.num_mtts;
398 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
399
400 size = dev->caps.num_mgms + dev->caps.num_amgms;
401 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
402 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
403
404 } else
405 err = -EINVAL;
406
407 return err;
408 }
409
410 int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
411 struct mlx4_func_cap *func_cap)
412 {
413 struct mlx4_cmd_mailbox *mailbox;
414 u32 *outbox;
415 u8 field, op_modifier;
416 u32 size, qkey;
417 int err = 0, quotas = 0;
418 u32 in_modifier;
419
420 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
421 in_modifier = op_modifier ? gen_or_port :
422 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
423
424 mailbox = mlx4_alloc_cmd_mailbox(dev);
425 if (IS_ERR(mailbox))
426 return PTR_ERR(mailbox);
427
428 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
429 MLX4_CMD_QUERY_FUNC_CAP,
430 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
431 if (err)
432 goto out;
433
434 outbox = mailbox->buf;
435
436 if (!op_modifier) {
437 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
438 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
439 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
440 err = -EPROTONOSUPPORT;
441 goto out;
442 }
443 func_cap->flags = field;
444 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
445
446 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
447 func_cap->num_ports = field;
448
449 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
450 func_cap->pf_context_behaviour = size;
451
452 if (quotas) {
453 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
454 func_cap->qp_quota = size & 0xFFFFFF;
455
456 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
457 func_cap->srq_quota = size & 0xFFFFFF;
458
459 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
460 func_cap->cq_quota = size & 0xFFFFFF;
461
462 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
463 func_cap->mpt_quota = size & 0xFFFFFF;
464
465 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
466 func_cap->mtt_quota = size & 0xFFFFFF;
467
468 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
469 func_cap->mcg_quota = size & 0xFFFFFF;
470
471 } else {
472 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
473 func_cap->qp_quota = size & 0xFFFFFF;
474
475 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
476 func_cap->srq_quota = size & 0xFFFFFF;
477
478 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
479 func_cap->cq_quota = size & 0xFFFFFF;
480
481 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
482 func_cap->mpt_quota = size & 0xFFFFFF;
483
484 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
485 func_cap->mtt_quota = size & 0xFFFFFF;
486
487 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
488 func_cap->mcg_quota = size & 0xFFFFFF;
489 }
490 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
491 func_cap->max_eq = size & 0xFFFFFF;
492
493 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
494 func_cap->reserved_eq = size & 0xFFFFFF;
495
496 goto out;
497 }
498
499 /* logical port query */
500 if (gen_or_port > dev->caps.num_ports) {
501 err = -EINVAL;
502 goto out;
503 }
504
505 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
506 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
507 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
508 mlx4_err(dev, "VLAN is enforced on this port\n");
509 err = -EPROTONOSUPPORT;
510 goto out;
511 }
512
513 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
514 mlx4_err(dev, "Force mac is enabled on this port\n");
515 err = -EPROTONOSUPPORT;
516 goto out;
517 }
518 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
519 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
520 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
521 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
522 err = -EPROTONOSUPPORT;
523 goto out;
524 }
525 }
526
527 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
528 func_cap->physical_port = field;
529 if (func_cap->physical_port != gen_or_port) {
530 err = -ENOSYS;
531 goto out;
532 }
533
534 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
535 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
536 func_cap->qp0_qkey = qkey;
537 } else {
538 func_cap->qp0_qkey = 0;
539 }
540
541 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
542 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
543
544 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
545 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
546
547 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
548 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
549
550 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
551 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
552
553 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
554 MLX4_GET(func_cap->phys_port_id, outbox,
555 QUERY_FUNC_CAP_PHYS_PORT_ID);
556
557 /* All other resources are allocated by the master, but we still report
558 * 'num' and 'reserved' capabilities as follows:
559 * - num remains the maximum resource index
560 * - 'num - reserved' is the total available objects of a resource, but
561 * resource indices may be less than 'reserved'
562 * TODO: set per-resource quotas */
563
564 out:
565 mlx4_free_cmd_mailbox(dev, mailbox);
566
567 return err;
568 }
569
570 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
571 {
572 struct mlx4_cmd_mailbox *mailbox;
573 u32 *outbox;
574 u8 field;
575 u32 field32, flags, ext_flags;
576 u16 size;
577 u16 stat_rate;
578 int err;
579 int i;
580
581 #define QUERY_DEV_CAP_OUT_SIZE 0x100
582 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
583 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
584 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
585 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
586 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
587 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
588 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
589 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
590 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
591 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
592 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
593 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
594 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
595 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
596 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
597 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
598 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
599 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
600 #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
601 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
602 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
603 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
604 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
605 #define QUERY_DEV_CAP_RSS_OFFSET 0x2e
606 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
607 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
608 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
609 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
610 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
611 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
612 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
613 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
614 #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
615 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
616 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
617 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
618 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
619 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
620 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
621 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
622 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
623 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
624 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
625 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
626 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
627 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
628 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
629 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
630 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
631 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
632 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
633 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
634 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
635 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
636 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
637 #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
638 #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
639 #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
640 #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
641 #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
642 #define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
643 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
644 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
645 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
646 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
647 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
648 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
649 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
650 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
651 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
652 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
653 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
654 #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
655 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
656 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
657 #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
658 #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
659 #define QUERY_DEV_CAP_VXLAN 0x9e
660 #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
661
662 dev_cap->flags2 = 0;
663 mailbox = mlx4_alloc_cmd_mailbox(dev);
664 if (IS_ERR(mailbox))
665 return PTR_ERR(mailbox);
666 outbox = mailbox->buf;
667
668 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
669 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
670 if (err)
671 goto out;
672
673 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
674 dev_cap->reserved_qps = 1 << (field & 0xf);
675 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
676 dev_cap->max_qps = 1 << (field & 0x1f);
677 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
678 dev_cap->reserved_srqs = 1 << (field >> 4);
679 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
680 dev_cap->max_srqs = 1 << (field & 0x1f);
681 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
682 dev_cap->max_cq_sz = 1 << field;
683 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
684 dev_cap->reserved_cqs = 1 << (field & 0xf);
685 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
686 dev_cap->max_cqs = 1 << (field & 0x1f);
687 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
688 dev_cap->max_mpts = 1 << (field & 0x3f);
689 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
690 dev_cap->reserved_eqs = 1 << (field & 0xf);
691 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
692 dev_cap->max_eqs = 1 << (field & 0xf);
693 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
694 dev_cap->reserved_mtts = 1 << (field >> 4);
695 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
696 dev_cap->max_mrw_sz = 1 << field;
697 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
698 dev_cap->reserved_mrws = 1 << (field & 0xf);
699 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
700 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
701 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
702 dev_cap->num_sys_eqs = size & 0xfff;
703 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
704 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
705 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
706 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
707 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
708 field &= 0x1f;
709 if (!field)
710 dev_cap->max_gso_sz = 0;
711 else
712 dev_cap->max_gso_sz = 1 << field;
713
714 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
715 if (field & 0x20)
716 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
717 if (field & 0x10)
718 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
719 field &= 0xf;
720 if (field) {
721 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
722 dev_cap->max_rss_tbl_sz = 1 << field;
723 } else
724 dev_cap->max_rss_tbl_sz = 0;
725 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
726 dev_cap->max_rdma_global = 1 << (field & 0x3f);
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
728 dev_cap->local_ca_ack_delay = field & 0x1f;
729 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
730 dev_cap->num_ports = field & 0xf;
731 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
732 dev_cap->max_msg_sz = 1 << (field & 0x1f);
733 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
734 if (field & 0x80)
735 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
736 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
737 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
738 if (field & 0x80)
739 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
740 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
741 dev_cap->fs_max_num_qp_per_entry = field;
742 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
743 dev_cap->stat_rate_support = stat_rate;
744 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
745 if (field & 0x80)
746 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
747 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
748 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
749 dev_cap->flags = flags | (u64)ext_flags << 32;
750 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
751 dev_cap->reserved_uars = field >> 4;
752 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
753 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
754 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
755 dev_cap->min_page_sz = 1 << field;
756
757 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
758 if (field & 0x80) {
759 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
760 dev_cap->bf_reg_size = 1 << (field & 0x1f);
761 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
762 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
763 field = 3;
764 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
765 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
766 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
767 } else {
768 dev_cap->bf_reg_size = 0;
769 mlx4_dbg(dev, "BlueFlame not available\n");
770 }
771
772 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
773 dev_cap->max_sq_sg = field;
774 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
775 dev_cap->max_sq_desc_sz = size;
776
777 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
778 dev_cap->max_qp_per_mcg = 1 << field;
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
780 dev_cap->reserved_mgms = field & 0xf;
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
782 dev_cap->max_mcgs = 1 << field;
783 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
784 dev_cap->reserved_pds = field >> 4;
785 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
786 dev_cap->max_pds = 1 << (field & 0x3f);
787 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
788 dev_cap->reserved_xrcds = field >> 4;
789 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
790 dev_cap->max_xrcds = 1 << (field & 0x1f);
791
792 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
793 dev_cap->rdmarc_entry_sz = size;
794 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
795 dev_cap->qpc_entry_sz = size;
796 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
797 dev_cap->aux_entry_sz = size;
798 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
799 dev_cap->altc_entry_sz = size;
800 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
801 dev_cap->eqc_entry_sz = size;
802 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
803 dev_cap->cqc_entry_sz = size;
804 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
805 dev_cap->srq_entry_sz = size;
806 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
807 dev_cap->cmpt_entry_sz = size;
808 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
809 dev_cap->mtt_entry_sz = size;
810 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
811 dev_cap->dmpt_entry_sz = size;
812
813 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
814 dev_cap->max_srq_sz = 1 << field;
815 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
816 dev_cap->max_qp_sz = 1 << field;
817 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
818 dev_cap->resize_srq = field & 1;
819 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
820 dev_cap->max_rq_sg = field;
821 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
822 dev_cap->max_rq_desc_sz = size;
823 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
824 if (field & (1 << 5))
825 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
826 if (field & (1 << 6))
827 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
828 if (field & (1 << 7))
829 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
830 MLX4_GET(dev_cap->bmme_flags, outbox,
831 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
832 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
833 if (field & 0x20)
834 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
835 MLX4_GET(dev_cap->reserved_lkey, outbox,
836 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
837 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
838 if (field32 & (1 << 0))
839 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
840 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
841 if (field & 1<<6)
842 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
843 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
844 if (field & 1<<3)
845 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
846 MLX4_GET(dev_cap->max_icm_sz, outbox,
847 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
848 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
849 MLX4_GET(dev_cap->max_counters, outbox,
850 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
851
852 MLX4_GET(field32, outbox,
853 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
854 if (field32 & (1 << 0))
855 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
856
857 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
858 if (field32 & (1 << 16))
859 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
860 if (field32 & (1 << 26))
861 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
862 if (field32 & (1 << 20))
863 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
864 if (field32 & (1 << 21))
865 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
866
867 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
868 for (i = 1; i <= dev_cap->num_ports; ++i) {
869 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
870 dev_cap->max_vl[i] = field >> 4;
871 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
872 dev_cap->ib_mtu[i] = field >> 4;
873 dev_cap->max_port_width[i] = field & 0xf;
874 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
875 dev_cap->max_gids[i] = 1 << (field & 0xf);
876 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
877 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
878 }
879 } else {
880 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
881 #define QUERY_PORT_MTU_OFFSET 0x01
882 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
883 #define QUERY_PORT_WIDTH_OFFSET 0x06
884 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
885 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
886 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
887 #define QUERY_PORT_MAC_OFFSET 0x10
888 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
889 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
890 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
891
892 for (i = 1; i <= dev_cap->num_ports; ++i) {
893 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
894 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
895 if (err)
896 goto out;
897
898 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
899 dev_cap->supported_port_types[i] = field & 3;
900 dev_cap->suggested_type[i] = (field >> 3) & 1;
901 dev_cap->default_sense[i] = (field >> 4) & 1;
902 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
903 dev_cap->ib_mtu[i] = field & 0xf;
904 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
905 dev_cap->max_port_width[i] = field & 0xf;
906 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
907 dev_cap->max_gids[i] = 1 << (field >> 4);
908 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
909 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
910 dev_cap->max_vl[i] = field & 0xf;
911 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
912 dev_cap->log_max_macs[i] = field & 0xf;
913 dev_cap->log_max_vlans[i] = field >> 4;
914 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
915 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
916 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
917 dev_cap->trans_type[i] = field32 >> 24;
918 dev_cap->vendor_oui[i] = field32 & 0xffffff;
919 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
920 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
921 }
922 }
923
924 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
925 dev_cap->bmme_flags, dev_cap->reserved_lkey);
926
927 /*
928 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
929 * we can't use any EQs whose doorbell falls on that page,
930 * even if the EQ itself isn't reserved.
931 */
932 if (dev_cap->num_sys_eqs == 0)
933 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
934 dev_cap->reserved_eqs);
935 else
936 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
937
938 mlx4_dbg(dev, "Max ICM size %lld MB\n",
939 (unsigned long long) dev_cap->max_icm_sz >> 20);
940 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
941 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
942 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
943 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
944 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
945 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
946 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
947 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
948 dev_cap->eqc_entry_sz);
949 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
950 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
951 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
952 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
953 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
954 dev_cap->max_pds, dev_cap->reserved_mgms);
955 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
956 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
957 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
958 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
959 dev_cap->max_port_width[1]);
960 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
961 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
962 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
963 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
964 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
965 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
966 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
967
968 dump_dev_cap_flags(dev, dev_cap->flags);
969 dump_dev_cap_flags2(dev, dev_cap->flags2);
970
971 out:
972 mlx4_free_cmd_mailbox(dev, mailbox);
973 return err;
974 }
975
976 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
977 struct mlx4_vhcr *vhcr,
978 struct mlx4_cmd_mailbox *inbox,
979 struct mlx4_cmd_mailbox *outbox,
980 struct mlx4_cmd_info *cmd)
981 {
982 u64 flags;
983 int err = 0;
984 u8 field;
985 u32 bmme_flags;
986 int real_port;
987 int slave_port;
988 int first_port;
989 struct mlx4_active_ports actv_ports;
990
991 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
992 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
993 if (err)
994 return err;
995
996 /* add port mng change event capability and disable mw type 1
997 * unconditionally to slaves
998 */
999 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1000 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
1001 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
1002 actv_ports = mlx4_get_active_ports(dev, slave);
1003 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1004 for (slave_port = 0, real_port = first_port;
1005 real_port < first_port +
1006 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1007 ++real_port, ++slave_port) {
1008 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1009 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1010 else
1011 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1012 }
1013 for (; slave_port < dev->caps.num_ports; ++slave_port)
1014 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1015 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1016
1017 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1018 field &= ~0x0F;
1019 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1020 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1021
1022 /* For guests, disable timestamp */
1023 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1024 field &= 0x7f;
1025 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1026
1027 /* For guests, disable vxlan tunneling */
1028 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
1029 field &= 0xf7;
1030 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1031
1032 /* For guests, report Blueflame disabled */
1033 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1034 field &= 0x7f;
1035 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1036
1037 /* For guests, disable mw type 2 */
1038 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1039 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1040 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1041
1042 /* turn off device-managed steering capability if not enabled */
1043 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1044 MLX4_GET(field, outbox->buf,
1045 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1046 field &= 0x7f;
1047 MLX4_PUT(outbox->buf, field,
1048 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1049 }
1050
1051 /* turn off ipoib managed steering for guests */
1052 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1053 field &= ~0x80;
1054 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1055
1056 return 0;
1057 }
1058
1059 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1060 struct mlx4_vhcr *vhcr,
1061 struct mlx4_cmd_mailbox *inbox,
1062 struct mlx4_cmd_mailbox *outbox,
1063 struct mlx4_cmd_info *cmd)
1064 {
1065 struct mlx4_priv *priv = mlx4_priv(dev);
1066 u64 def_mac;
1067 u8 port_type;
1068 u16 short_field;
1069 int err;
1070 int admin_link_state;
1071 int port = mlx4_slave_convert_port(dev, slave,
1072 vhcr->in_modifier & 0xFF);
1073
1074 #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
1075 #define MLX4_PORT_LINK_UP_MASK 0x80
1076 #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1077 #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
1078
1079 if (port < 0)
1080 return -EINVAL;
1081
1082 /* Protect against untrusted guests: enforce that this is the
1083 * QUERY_PORT general query.
1084 */
1085 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1086 return -EINVAL;
1087
1088 vhcr->in_modifier = port;
1089
1090 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1091 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1092 MLX4_CMD_NATIVE);
1093
1094 if (!err && dev->caps.function != slave) {
1095 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
1096 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1097
1098 /* get port type - currently only eth is enabled */
1099 MLX4_GET(port_type, outbox->buf,
1100 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1101
1102 /* No link sensing allowed */
1103 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1104 /* set port type to currently operating port type */
1105 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
1106
1107 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1108 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1109 port_type |= MLX4_PORT_LINK_UP_MASK;
1110 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1111 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1112
1113 MLX4_PUT(outbox->buf, port_type,
1114 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1115
1116 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
1117 short_field = mlx4_get_slave_num_gids(dev, slave, port);
1118 else
1119 short_field = 1; /* slave max gids */
1120 MLX4_PUT(outbox->buf, short_field,
1121 QUERY_PORT_CUR_MAX_GID_OFFSET);
1122
1123 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1124 MLX4_PUT(outbox->buf, short_field,
1125 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1126 }
1127
1128 return err;
1129 }
1130
1131 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1132 int *gid_tbl_len, int *pkey_tbl_len)
1133 {
1134 struct mlx4_cmd_mailbox *mailbox;
1135 u32 *outbox;
1136 u16 field;
1137 int err;
1138
1139 mailbox = mlx4_alloc_cmd_mailbox(dev);
1140 if (IS_ERR(mailbox))
1141 return PTR_ERR(mailbox);
1142
1143 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1144 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1145 MLX4_CMD_WRAPPED);
1146 if (err)
1147 goto out;
1148
1149 outbox = mailbox->buf;
1150
1151 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1152 *gid_tbl_len = field;
1153
1154 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1155 *pkey_tbl_len = field;
1156
1157 out:
1158 mlx4_free_cmd_mailbox(dev, mailbox);
1159 return err;
1160 }
1161 EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1162
1163 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1164 {
1165 struct mlx4_cmd_mailbox *mailbox;
1166 struct mlx4_icm_iter iter;
1167 __be64 *pages;
1168 int lg;
1169 int nent = 0;
1170 int i;
1171 int err = 0;
1172 int ts = 0, tc = 0;
1173
1174 mailbox = mlx4_alloc_cmd_mailbox(dev);
1175 if (IS_ERR(mailbox))
1176 return PTR_ERR(mailbox);
1177 pages = mailbox->buf;
1178
1179 for (mlx4_icm_first(icm, &iter);
1180 !mlx4_icm_last(&iter);
1181 mlx4_icm_next(&iter)) {
1182 /*
1183 * We have to pass pages that are aligned to their
1184 * size, so find the least significant 1 in the
1185 * address or size and use that as our log2 size.
1186 */
1187 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1188 if (lg < MLX4_ICM_PAGE_SHIFT) {
1189 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1190 MLX4_ICM_PAGE_SIZE,
1191 (unsigned long long) mlx4_icm_addr(&iter),
1192 mlx4_icm_size(&iter));
1193 err = -EINVAL;
1194 goto out;
1195 }
1196
1197 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1198 if (virt != -1) {
1199 pages[nent * 2] = cpu_to_be64(virt);
1200 virt += 1 << lg;
1201 }
1202
1203 pages[nent * 2 + 1] =
1204 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1205 (lg - MLX4_ICM_PAGE_SHIFT));
1206 ts += 1 << (lg - 10);
1207 ++tc;
1208
1209 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1210 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1211 MLX4_CMD_TIME_CLASS_B,
1212 MLX4_CMD_NATIVE);
1213 if (err)
1214 goto out;
1215 nent = 0;
1216 }
1217 }
1218 }
1219
1220 if (nent)
1221 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1222 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1223 if (err)
1224 goto out;
1225
1226 switch (op) {
1227 case MLX4_CMD_MAP_FA:
1228 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
1229 break;
1230 case MLX4_CMD_MAP_ICM_AUX:
1231 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
1232 break;
1233 case MLX4_CMD_MAP_ICM:
1234 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1235 tc, ts, (unsigned long long) virt - (ts << 10));
1236 break;
1237 }
1238
1239 out:
1240 mlx4_free_cmd_mailbox(dev, mailbox);
1241 return err;
1242 }
1243
1244 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1245 {
1246 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1247 }
1248
1249 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1250 {
1251 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1252 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1253 }
1254
1255
1256 int mlx4_RUN_FW(struct mlx4_dev *dev)
1257 {
1258 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1259 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1260 }
1261
1262 int mlx4_QUERY_FW(struct mlx4_dev *dev)
1263 {
1264 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1265 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1266 struct mlx4_cmd_mailbox *mailbox;
1267 u32 *outbox;
1268 int err = 0;
1269 u64 fw_ver;
1270 u16 cmd_if_rev;
1271 u8 lg;
1272
1273 #define QUERY_FW_OUT_SIZE 0x100
1274 #define QUERY_FW_VER_OFFSET 0x00
1275 #define QUERY_FW_PPF_ID 0x09
1276 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
1277 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
1278 #define QUERY_FW_ERR_START_OFFSET 0x30
1279 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
1280 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
1281
1282 #define QUERY_FW_SIZE_OFFSET 0x00
1283 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1284 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1285
1286 #define QUERY_FW_COMM_BASE_OFFSET 0x40
1287 #define QUERY_FW_COMM_BAR_OFFSET 0x48
1288
1289 #define QUERY_FW_CLOCK_OFFSET 0x50
1290 #define QUERY_FW_CLOCK_BAR 0x58
1291
1292 mailbox = mlx4_alloc_cmd_mailbox(dev);
1293 if (IS_ERR(mailbox))
1294 return PTR_ERR(mailbox);
1295 outbox = mailbox->buf;
1296
1297 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1298 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1299 if (err)
1300 goto out;
1301
1302 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1303 /*
1304 * FW subminor version is at more significant bits than minor
1305 * version, so swap here.
1306 */
1307 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1308 ((fw_ver & 0xffff0000ull) >> 16) |
1309 ((fw_ver & 0x0000ffffull) << 16);
1310
1311 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1312 dev->caps.function = lg;
1313
1314 if (mlx4_is_slave(dev))
1315 goto out;
1316
1317
1318 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1319 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1320 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1321 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
1322 cmd_if_rev);
1323 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1324 (int) (dev->caps.fw_ver >> 32),
1325 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1326 (int) dev->caps.fw_ver & 0xffff);
1327 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
1328 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
1329 err = -ENODEV;
1330 goto out;
1331 }
1332
1333 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1334 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1335
1336 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1337 cmd->max_cmds = 1 << lg;
1338
1339 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
1340 (int) (dev->caps.fw_ver >> 32),
1341 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1342 (int) dev->caps.fw_ver & 0xffff,
1343 cmd_if_rev, cmd->max_cmds);
1344
1345 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1346 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1347 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1348 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1349
1350 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1351 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1352
1353 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1354 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1355 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1356 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1357
1358 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1359 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1360 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1361 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1362 fw->comm_bar, fw->comm_base);
1363 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1364
1365 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1366 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1367 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1368 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1369 fw->clock_bar, fw->clock_offset);
1370
1371 /*
1372 * Round up number of system pages needed in case
1373 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1374 */
1375 fw->fw_pages =
1376 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1377 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1378
1379 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1380 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1381
1382 out:
1383 mlx4_free_cmd_mailbox(dev, mailbox);
1384 return err;
1385 }
1386
1387 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1388 struct mlx4_vhcr *vhcr,
1389 struct mlx4_cmd_mailbox *inbox,
1390 struct mlx4_cmd_mailbox *outbox,
1391 struct mlx4_cmd_info *cmd)
1392 {
1393 u8 *outbuf;
1394 int err;
1395
1396 outbuf = outbox->buf;
1397 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1398 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1399 if (err)
1400 return err;
1401
1402 /* for slaves, set pci PPF ID to invalid and zero out everything
1403 * else except FW version */
1404 outbuf[0] = outbuf[1] = 0;
1405 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
1406 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1407
1408 return 0;
1409 }
1410
1411 static void get_board_id(void *vsd, char *board_id)
1412 {
1413 int i;
1414
1415 #define VSD_OFFSET_SIG1 0x00
1416 #define VSD_OFFSET_SIG2 0xde
1417 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1418 #define VSD_OFFSET_TS_BOARD_ID 0x20
1419
1420 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1421
1422 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1423
1424 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1425 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1426 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1427 } else {
1428 /*
1429 * The board ID is a string but the firmware byte
1430 * swaps each 4-byte word before passing it back to
1431 * us. Therefore we need to swab it before printing.
1432 */
1433 for (i = 0; i < 4; ++i)
1434 ((u32 *) board_id)[i] =
1435 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1436 }
1437 }
1438
1439 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1440 {
1441 struct mlx4_cmd_mailbox *mailbox;
1442 u32 *outbox;
1443 int err;
1444
1445 #define QUERY_ADAPTER_OUT_SIZE 0x100
1446 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1447 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1448
1449 mailbox = mlx4_alloc_cmd_mailbox(dev);
1450 if (IS_ERR(mailbox))
1451 return PTR_ERR(mailbox);
1452 outbox = mailbox->buf;
1453
1454 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
1455 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1456 if (err)
1457 goto out;
1458
1459 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1460
1461 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1462 adapter->board_id);
1463
1464 out:
1465 mlx4_free_cmd_mailbox(dev, mailbox);
1466 return err;
1467 }
1468
1469 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1470 {
1471 struct mlx4_cmd_mailbox *mailbox;
1472 __be32 *inbox;
1473 int err;
1474
1475 #define INIT_HCA_IN_SIZE 0x200
1476 #define INIT_HCA_VERSION_OFFSET 0x000
1477 #define INIT_HCA_VERSION 2
1478 #define INIT_HCA_VXLAN_OFFSET 0x0c
1479 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
1480 #define INIT_HCA_FLAGS_OFFSET 0x014
1481 #define INIT_HCA_QPC_OFFSET 0x020
1482 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1483 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1484 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1485 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1486 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1487 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1488 #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
1489 #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
1490 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1491 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1492 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1493 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1494 #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
1495 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1496 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1497 #define INIT_HCA_MCAST_OFFSET 0x0c0
1498 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1499 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1500 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1501 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
1502 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1503 #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1504 #define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1505 #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1506 #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1507 #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1508 #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1509 #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1510 #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1511 #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
1512 #define INIT_HCA_TPT_OFFSET 0x0f0
1513 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1514 #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
1515 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1516 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1517 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1518 #define INIT_HCA_UAR_OFFSET 0x120
1519 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1520 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1521
1522 mailbox = mlx4_alloc_cmd_mailbox(dev);
1523 if (IS_ERR(mailbox))
1524 return PTR_ERR(mailbox);
1525 inbox = mailbox->buf;
1526
1527 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1528
1529 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1530 (ilog2(cache_line_size()) - 4) << 5;
1531
1532 #if defined(__LITTLE_ENDIAN)
1533 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1534 #elif defined(__BIG_ENDIAN)
1535 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1536 #else
1537 #error Host endianness not defined
1538 #endif
1539 /* Check port for UD address vector: */
1540 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1541
1542 /* Enable IPoIB checksumming if we can: */
1543 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1544 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1545
1546 /* Enable QoS support if module parameter set */
1547 if (enable_qos)
1548 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1549
1550 /* enable counters */
1551 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1552 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1553
1554 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1555 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1556 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1557 dev->caps.eqe_size = 64;
1558 dev->caps.eqe_factor = 1;
1559 } else {
1560 dev->caps.eqe_size = 32;
1561 dev->caps.eqe_factor = 0;
1562 }
1563
1564 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1565 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1566 dev->caps.cqe_size = 64;
1567 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1568 } else {
1569 dev->caps.cqe_size = 32;
1570 }
1571
1572 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1573 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1574 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1575 dev->caps.eqe_size = cache_line_size();
1576 dev->caps.cqe_size = cache_line_size();
1577 dev->caps.eqe_factor = 0;
1578 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1579 (ilog2(dev->caps.eqe_size) - 5)),
1580 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1581
1582 /* User still need to know to support CQE > 32B */
1583 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1584 }
1585
1586 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1587
1588 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1589 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1590 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1591 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1592 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1593 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1594 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1595 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1596 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1597 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1598 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
1599 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1600 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1601
1602 /* steering attributes */
1603 if (dev->caps.steering_mode ==
1604 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1605 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1606 cpu_to_be32(1 <<
1607 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1608
1609 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1610 MLX4_PUT(inbox, param->log_mc_entry_sz,
1611 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1612 MLX4_PUT(inbox, param->log_mc_table_sz,
1613 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1614 /* Enable Ethernet flow steering
1615 * with udp unicast and tcp unicast
1616 */
1617 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1618 INIT_HCA_FS_ETH_BITS_OFFSET);
1619 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1620 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1621 /* Enable IPoIB flow steering
1622 * with udp unicast and tcp unicast
1623 */
1624 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1625 INIT_HCA_FS_IB_BITS_OFFSET);
1626 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1627 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1628 } else {
1629 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1630 MLX4_PUT(inbox, param->log_mc_entry_sz,
1631 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1632 MLX4_PUT(inbox, param->log_mc_hash_sz,
1633 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1634 MLX4_PUT(inbox, param->log_mc_table_sz,
1635 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1636 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1637 MLX4_PUT(inbox, (u8) (1 << 3),
1638 INIT_HCA_UC_STEERING_OFFSET);
1639 }
1640
1641 /* TPT attributes */
1642
1643 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1644 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
1645 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1646 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1647 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1648
1649 /* UAR attributes */
1650
1651 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1652 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1653
1654 /* set parser VXLAN attributes */
1655 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1656 u8 parser_params = 0;
1657 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1658 }
1659
1660 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1661 MLX4_CMD_NATIVE);
1662
1663 if (err)
1664 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1665
1666 mlx4_free_cmd_mailbox(dev, mailbox);
1667 return err;
1668 }
1669
1670 int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1671 struct mlx4_init_hca_param *param)
1672 {
1673 struct mlx4_cmd_mailbox *mailbox;
1674 __be32 *outbox;
1675 u32 dword_field;
1676 int err;
1677 u8 byte_field;
1678
1679 #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1680 #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
1681
1682 mailbox = mlx4_alloc_cmd_mailbox(dev);
1683 if (IS_ERR(mailbox))
1684 return PTR_ERR(mailbox);
1685 outbox = mailbox->buf;
1686
1687 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1688 MLX4_CMD_QUERY_HCA,
1689 MLX4_CMD_TIME_CLASS_B,
1690 !mlx4_is_slave(dev));
1691 if (err)
1692 goto out;
1693
1694 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1695 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1696
1697 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1698
1699 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1700 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1701 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1702 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1703 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1704 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1705 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1706 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1707 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1708 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1709 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
1710 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1711 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1712
1713 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1714 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1715 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1716 } else {
1717 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1718 if (byte_field & 0x8)
1719 param->steering_mode = MLX4_STEERING_MODE_B0;
1720 else
1721 param->steering_mode = MLX4_STEERING_MODE_A0;
1722 }
1723 /* steering attributes */
1724 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
1725 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1726 MLX4_GET(param->log_mc_entry_sz, outbox,
1727 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1728 MLX4_GET(param->log_mc_table_sz, outbox,
1729 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1730 } else {
1731 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1732 MLX4_GET(param->log_mc_entry_sz, outbox,
1733 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1734 MLX4_GET(param->log_mc_hash_sz, outbox,
1735 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1736 MLX4_GET(param->log_mc_table_sz, outbox,
1737 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1738 }
1739
1740 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1741 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1742 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1743 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1744 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1745 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1746
1747 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1748 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1749 if (byte_field) {
1750 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1751 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1752 param->cqe_size = 1 << ((byte_field &
1753 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1754 param->eqe_size = 1 << (((byte_field &
1755 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1756 }
1757
1758 /* TPT attributes */
1759
1760 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1761 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
1762 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1763 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1764 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1765
1766 /* UAR attributes */
1767
1768 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1769 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1770
1771 out:
1772 mlx4_free_cmd_mailbox(dev, mailbox);
1773
1774 return err;
1775 }
1776
1777 /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1778 * and real QP0 are active, so that the paravirtualized QP0 is ready
1779 * to operate */
1780 static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1781 {
1782 struct mlx4_priv *priv = mlx4_priv(dev);
1783 /* irrelevant if not infiniband */
1784 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1785 priv->mfunc.master.qp0_state[port].qp0_active)
1786 return 1;
1787 return 0;
1788 }
1789
1790 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1791 struct mlx4_vhcr *vhcr,
1792 struct mlx4_cmd_mailbox *inbox,
1793 struct mlx4_cmd_mailbox *outbox,
1794 struct mlx4_cmd_info *cmd)
1795 {
1796 struct mlx4_priv *priv = mlx4_priv(dev);
1797 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
1798 int err;
1799
1800 if (port < 0)
1801 return -EINVAL;
1802
1803 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1804 return 0;
1805
1806 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1807 /* Enable port only if it was previously disabled */
1808 if (!priv->mfunc.master.init_port_ref[port]) {
1809 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1810 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1811 if (err)
1812 return err;
1813 }
1814 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1815 } else {
1816 if (slave == mlx4_master_func_num(dev)) {
1817 if (check_qp0_state(dev, slave, port) &&
1818 !priv->mfunc.master.qp0_state[port].port_active) {
1819 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1820 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1821 if (err)
1822 return err;
1823 priv->mfunc.master.qp0_state[port].port_active = 1;
1824 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1825 }
1826 } else
1827 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1828 }
1829 ++priv->mfunc.master.init_port_ref[port];
1830 return 0;
1831 }
1832
1833 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
1834 {
1835 struct mlx4_cmd_mailbox *mailbox;
1836 u32 *inbox;
1837 int err;
1838 u32 flags;
1839 u16 field;
1840
1841 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1842 #define INIT_PORT_IN_SIZE 256
1843 #define INIT_PORT_FLAGS_OFFSET 0x00
1844 #define INIT_PORT_FLAG_SIG (1 << 18)
1845 #define INIT_PORT_FLAG_NG (1 << 17)
1846 #define INIT_PORT_FLAG_G0 (1 << 16)
1847 #define INIT_PORT_VL_SHIFT 4
1848 #define INIT_PORT_PORT_WIDTH_SHIFT 8
1849 #define INIT_PORT_MTU_OFFSET 0x04
1850 #define INIT_PORT_MAX_GID_OFFSET 0x06
1851 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1852 #define INIT_PORT_GUID0_OFFSET 0x10
1853 #define INIT_PORT_NODE_GUID_OFFSET 0x18
1854 #define INIT_PORT_SI_GUID_OFFSET 0x20
1855
1856 mailbox = mlx4_alloc_cmd_mailbox(dev);
1857 if (IS_ERR(mailbox))
1858 return PTR_ERR(mailbox);
1859 inbox = mailbox->buf;
1860
1861 flags = 0;
1862 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1863 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1864 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
1865
1866 field = 128 << dev->caps.ib_mtu_cap[port];
1867 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1868 field = dev->caps.gid_table_len[port];
1869 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1870 field = dev->caps.pkey_table_len[port];
1871 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
1872
1873 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
1874 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1875
1876 mlx4_free_cmd_mailbox(dev, mailbox);
1877 } else
1878 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1879 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1880
1881 return err;
1882 }
1883 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1884
1885 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1886 struct mlx4_vhcr *vhcr,
1887 struct mlx4_cmd_mailbox *inbox,
1888 struct mlx4_cmd_mailbox *outbox,
1889 struct mlx4_cmd_info *cmd)
1890 {
1891 struct mlx4_priv *priv = mlx4_priv(dev);
1892 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
1893 int err;
1894
1895 if (port < 0)
1896 return -EINVAL;
1897
1898 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1899 (1 << port)))
1900 return 0;
1901
1902 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1903 if (priv->mfunc.master.init_port_ref[port] == 1) {
1904 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1905 1000, MLX4_CMD_NATIVE);
1906 if (err)
1907 return err;
1908 }
1909 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1910 } else {
1911 /* infiniband port */
1912 if (slave == mlx4_master_func_num(dev)) {
1913 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1914 priv->mfunc.master.qp0_state[port].port_active) {
1915 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1916 1000, MLX4_CMD_NATIVE);
1917 if (err)
1918 return err;
1919 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1920 priv->mfunc.master.qp0_state[port].port_active = 0;
1921 }
1922 } else
1923 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1924 }
1925 --priv->mfunc.master.init_port_ref[port];
1926 return 0;
1927 }
1928
1929 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1930 {
1931 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1932 MLX4_CMD_WRAPPED);
1933 }
1934 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1935
1936 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1937 {
1938 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1939 MLX4_CMD_NATIVE);
1940 }
1941
1942 struct mlx4_config_dev {
1943 __be32 update_flags;
1944 __be32 rsvd1[3];
1945 __be16 vxlan_udp_dport;
1946 __be16 rsvd2;
1947 __be32 rsvd3[27];
1948 __be16 rsvd4;
1949 u8 rsvd5;
1950 u8 rx_checksum_val;
1951 };
1952
1953 #define MLX4_VXLAN_UDP_DPORT (1 << 0)
1954
1955 static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
1956 {
1957 int err;
1958 struct mlx4_cmd_mailbox *mailbox;
1959
1960 mailbox = mlx4_alloc_cmd_mailbox(dev);
1961 if (IS_ERR(mailbox))
1962 return PTR_ERR(mailbox);
1963
1964 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1965
1966 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1967 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1968
1969 mlx4_free_cmd_mailbox(dev, mailbox);
1970 return err;
1971 }
1972
1973 static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
1974 {
1975 int err;
1976 struct mlx4_cmd_mailbox *mailbox;
1977
1978 mailbox = mlx4_alloc_cmd_mailbox(dev);
1979 if (IS_ERR(mailbox))
1980 return PTR_ERR(mailbox);
1981
1982 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
1983 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1984
1985 if (!err)
1986 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
1987
1988 mlx4_free_cmd_mailbox(dev, mailbox);
1989 return err;
1990 }
1991
1992 /* Conversion between the HW values and the actual functionality.
1993 * The value represented by the array index,
1994 * and the functionality determined by the flags.
1995 */
1996 static const u8 config_dev_csum_flags[] = {
1997 [0] = 0,
1998 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
1999 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2000 MLX4_RX_CSUM_MODE_L4,
2001 [3] = MLX4_RX_CSUM_MODE_L4 |
2002 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2003 MLX4_RX_CSUM_MODE_MULTI_VLAN
2004 };
2005
2006 int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2007 struct mlx4_config_dev_params *params)
2008 {
2009 struct mlx4_config_dev config_dev;
2010 int err;
2011 u8 csum_mask;
2012
2013 #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2014 #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2015 #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2016
2017 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2018 return -ENOTSUPP;
2019
2020 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2021 if (err)
2022 return err;
2023
2024 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2025 CONFIG_DEV_RX_CSUM_MODE_MASK;
2026
2027 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2028 return -EINVAL;
2029 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2030
2031 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2032 CONFIG_DEV_RX_CSUM_MODE_MASK;
2033
2034 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2035 return -EINVAL;
2036 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2037
2038 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2039
2040 return 0;
2041 }
2042 EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2043
2044 int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2045 {
2046 struct mlx4_config_dev config_dev;
2047
2048 memset(&config_dev, 0, sizeof(config_dev));
2049 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2050 config_dev.vxlan_udp_dport = udp_port;
2051
2052 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2053 }
2054 EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2055
2056
2057 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2058 {
2059 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2060 MLX4_CMD_SET_ICM_SIZE,
2061 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2062 if (ret)
2063 return ret;
2064
2065 /*
2066 * Round up number of system pages needed in case
2067 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2068 */
2069 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2070 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2071
2072 return 0;
2073 }
2074
2075 int mlx4_NOP(struct mlx4_dev *dev)
2076 {
2077 /* Input modifier of 0x1f means "finish as soon as possible." */
2078 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
2079 }
2080
2081 int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2082 {
2083 u8 port;
2084 u32 *outbox;
2085 struct mlx4_cmd_mailbox *mailbox;
2086 u32 in_mod;
2087 u32 guid_hi, guid_lo;
2088 int err, ret = 0;
2089 #define MOD_STAT_CFG_PORT_OFFSET 8
2090 #define MOD_STAT_CFG_GUID_H 0X14
2091 #define MOD_STAT_CFG_GUID_L 0X1c
2092
2093 mailbox = mlx4_alloc_cmd_mailbox(dev);
2094 if (IS_ERR(mailbox))
2095 return PTR_ERR(mailbox);
2096 outbox = mailbox->buf;
2097
2098 for (port = 1; port <= dev->caps.num_ports; port++) {
2099 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2100 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2101 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2102 MLX4_CMD_NATIVE);
2103 if (err) {
2104 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2105 port);
2106 ret = err;
2107 } else {
2108 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2109 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2110 dev->caps.phys_port_id[port] = (u64)guid_lo |
2111 (u64)guid_hi << 32;
2112 }
2113 }
2114 mlx4_free_cmd_mailbox(dev, mailbox);
2115 return ret;
2116 }
2117
2118 #define MLX4_WOL_SETUP_MODE (5 << 28)
2119 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2120 {
2121 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2122
2123 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
2124 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2125 MLX4_CMD_NATIVE);
2126 }
2127 EXPORT_SYMBOL_GPL(mlx4_wol_read);
2128
2129 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2130 {
2131 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2132
2133 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
2134 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2135 }
2136 EXPORT_SYMBOL_GPL(mlx4_wol_write);
2137
2138 enum {
2139 ADD_TO_MCG = 0x26,
2140 };
2141
2142
2143 void mlx4_opreq_action(struct work_struct *work)
2144 {
2145 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2146 opreq_task);
2147 struct mlx4_dev *dev = &priv->dev;
2148 int num_tasks = atomic_read(&priv->opreq_count);
2149 struct mlx4_cmd_mailbox *mailbox;
2150 struct mlx4_mgm *mgm;
2151 u32 *outbox;
2152 u32 modifier;
2153 u16 token;
2154 u16 type;
2155 int err;
2156 u32 num_qps;
2157 struct mlx4_qp qp;
2158 int i;
2159 u8 rem_mcg;
2160 u8 prot;
2161
2162 #define GET_OP_REQ_MODIFIER_OFFSET 0x08
2163 #define GET_OP_REQ_TOKEN_OFFSET 0x14
2164 #define GET_OP_REQ_TYPE_OFFSET 0x1a
2165 #define GET_OP_REQ_DATA_OFFSET 0x20
2166
2167 mailbox = mlx4_alloc_cmd_mailbox(dev);
2168 if (IS_ERR(mailbox)) {
2169 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2170 return;
2171 }
2172 outbox = mailbox->buf;
2173
2174 while (num_tasks) {
2175 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2176 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2177 MLX4_CMD_NATIVE);
2178 if (err) {
2179 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
2180 err);
2181 return;
2182 }
2183 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2184 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2185 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
2186 type &= 0xfff;
2187
2188 switch (type) {
2189 case ADD_TO_MCG:
2190 if (dev->caps.steering_mode ==
2191 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2192 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2193 err = EPERM;
2194 break;
2195 }
2196 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2197 GET_OP_REQ_DATA_OFFSET);
2198 num_qps = be32_to_cpu(mgm->members_count) &
2199 MGM_QPN_MASK;
2200 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2201 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2202
2203 for (i = 0; i < num_qps; i++) {
2204 qp.qpn = be32_to_cpu(mgm->qp[i]);
2205 if (rem_mcg)
2206 err = mlx4_multicast_detach(dev, &qp,
2207 mgm->gid,
2208 prot, 0);
2209 else
2210 err = mlx4_multicast_attach(dev, &qp,
2211 mgm->gid,
2212 mgm->gid[5]
2213 , 0, prot,
2214 NULL);
2215 if (err)
2216 break;
2217 }
2218 break;
2219 default:
2220 mlx4_warn(dev, "Bad type for required operation\n");
2221 err = EINVAL;
2222 break;
2223 }
2224 err = mlx4_cmd(dev, 0, ((u32) err |
2225 (__force u32)cpu_to_be32(token) << 16),
2226 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2227 MLX4_CMD_NATIVE);
2228 if (err) {
2229 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2230 err);
2231 goto out;
2232 }
2233 memset(outbox, 0, 0xffc);
2234 num_tasks = atomic_dec_return(&priv->opreq_count);
2235 }
2236
2237 out:
2238 mlx4_free_cmd_mailbox(dev, mailbox);
2239 }
2240
2241 static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2242 struct mlx4_cmd_mailbox *mailbox)
2243 {
2244 #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2245 #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2246 #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2247 #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2248
2249 u32 set_attr_mask, getresp_attr_mask;
2250 u32 trap_attr_mask, traprepress_attr_mask;
2251
2252 MLX4_GET(set_attr_mask, mailbox->buf,
2253 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2254 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2255 set_attr_mask);
2256
2257 MLX4_GET(getresp_attr_mask, mailbox->buf,
2258 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2259 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2260 getresp_attr_mask);
2261
2262 MLX4_GET(trap_attr_mask, mailbox->buf,
2263 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2264 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2265 trap_attr_mask);
2266
2267 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2268 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2269 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2270 traprepress_attr_mask);
2271
2272 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2273 traprepress_attr_mask)
2274 return 1;
2275
2276 return 0;
2277 }
2278
2279 int mlx4_config_mad_demux(struct mlx4_dev *dev)
2280 {
2281 struct mlx4_cmd_mailbox *mailbox;
2282 int secure_host_active;
2283 int err;
2284
2285 /* Check if mad_demux is supported */
2286 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2287 return 0;
2288
2289 mailbox = mlx4_alloc_cmd_mailbox(dev);
2290 if (IS_ERR(mailbox)) {
2291 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2292 return -ENOMEM;
2293 }
2294
2295 /* Query mad_demux to find out which MADs are handled by internal sma */
2296 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2297 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2298 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2299 if (err) {
2300 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2301 err);
2302 goto out;
2303 }
2304
2305 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2306
2307 /* Config mad_demux to handle all MADs returned by the query above */
2308 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2309 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2310 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2311 if (err) {
2312 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2313 goto out;
2314 }
2315
2316 if (secure_host_active)
2317 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2318 out:
2319 mlx4_free_cmd_mailbox(dev, mailbox);
2320 return err;
2321 }
2322
2323 /* Access Reg commands */
2324 enum mlx4_access_reg_masks {
2325 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2326 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2327 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2328 };
2329
2330 struct mlx4_access_reg {
2331 __be16 constant1;
2332 u8 status;
2333 u8 resrvd1;
2334 __be16 reg_id;
2335 u8 method;
2336 u8 constant2;
2337 __be32 resrvd2[2];
2338 __be16 len_const;
2339 __be16 resrvd3;
2340 #define MLX4_ACCESS_REG_HEADER_SIZE (20)
2341 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2342 } __attribute__((__packed__));
2343
2344 /**
2345 * mlx4_ACCESS_REG - Generic access reg command.
2346 * @dev: mlx4_dev.
2347 * @reg_id: register ID to access.
2348 * @method: Access method Read/Write.
2349 * @reg_len: register length to Read/Write in bytes.
2350 * @reg_data: reg_data pointer to Read/Write From/To.
2351 *
2352 * Access ConnectX registers FW command.
2353 * Returns 0 on success and copies outbox mlx4_access_reg data
2354 * field into reg_data or a negative error code.
2355 */
2356 static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2357 enum mlx4_access_reg_method method,
2358 u16 reg_len, void *reg_data)
2359 {
2360 struct mlx4_cmd_mailbox *inbox, *outbox;
2361 struct mlx4_access_reg *inbuf, *outbuf;
2362 int err;
2363
2364 inbox = mlx4_alloc_cmd_mailbox(dev);
2365 if (IS_ERR(inbox))
2366 return PTR_ERR(inbox);
2367
2368 outbox = mlx4_alloc_cmd_mailbox(dev);
2369 if (IS_ERR(outbox)) {
2370 mlx4_free_cmd_mailbox(dev, inbox);
2371 return PTR_ERR(outbox);
2372 }
2373
2374 inbuf = inbox->buf;
2375 outbuf = outbox->buf;
2376
2377 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2378 inbuf->constant2 = 0x1;
2379 inbuf->reg_id = cpu_to_be16(reg_id);
2380 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2381
2382 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2383 inbuf->len_const =
2384 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2385 ((0x3) << 12));
2386
2387 memcpy(inbuf->reg_data, reg_data, reg_len);
2388 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2389 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2390 MLX4_CMD_WRAPPED);
2391 if (err)
2392 goto out;
2393
2394 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2395 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2396 mlx4_err(dev,
2397 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2398 reg_id, err);
2399 goto out;
2400 }
2401
2402 memcpy(reg_data, outbuf->reg_data, reg_len);
2403 out:
2404 mlx4_free_cmd_mailbox(dev, inbox);
2405 mlx4_free_cmd_mailbox(dev, outbox);
2406 return err;
2407 }
2408
2409 /* ConnectX registers IDs */
2410 enum mlx4_reg_id {
2411 MLX4_REG_ID_PTYS = 0x5004,
2412 };
2413
2414 /**
2415 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2416 * register
2417 * @dev: mlx4_dev.
2418 * @method: Access method Read/Write.
2419 * @ptys_reg: PTYS register data pointer.
2420 *
2421 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2422 * configuration
2423 * Returns 0 on success or a negative error code.
2424 */
2425 int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2426 enum mlx4_access_reg_method method,
2427 struct mlx4_ptys_reg *ptys_reg)
2428 {
2429 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2430 method, sizeof(*ptys_reg), ptys_reg);
2431 }
2432 EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
2433
2434 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2435 struct mlx4_vhcr *vhcr,
2436 struct mlx4_cmd_mailbox *inbox,
2437 struct mlx4_cmd_mailbox *outbox,
2438 struct mlx4_cmd_info *cmd)
2439 {
2440 struct mlx4_access_reg *inbuf = inbox->buf;
2441 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2442 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2443
2444 if (slave != mlx4_master_func_num(dev) &&
2445 method == MLX4_ACCESS_REG_WRITE)
2446 return -EPERM;
2447
2448 if (reg_id == MLX4_REG_ID_PTYS) {
2449 struct mlx4_ptys_reg *ptys_reg =
2450 (struct mlx4_ptys_reg *)inbuf->reg_data;
2451
2452 ptys_reg->local_port =
2453 mlx4_slave_convert_port(dev, slave,
2454 ptys_reg->local_port);
2455 }
2456
2457 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2458 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2459 MLX4_CMD_NATIVE);
2460 }
Linux kernel - Deliverables
This page took 0.146948 seconds and 5 git commands to generate.