2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
42 #include <linux/io-mapping.h>
43 #include <linux/delay.h>
44 #include <linux/netdevice.h>
45 #include <linux/kmod.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/doorbell.h>
54 MODULE_AUTHOR("Roland Dreier");
55 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
56 MODULE_LICENSE("Dual BSD/GPL");
57 MODULE_VERSION(DRV_VERSION
);
59 struct workqueue_struct
*mlx4_wq
;
61 #ifdef CONFIG_MLX4_DEBUG
63 int mlx4_debug_level
= 0;
64 module_param_named(debug_level
, mlx4_debug_level
, int, 0644);
65 MODULE_PARM_DESC(debug_level
, "Enable debug tracing if > 0");
67 #endif /* CONFIG_MLX4_DEBUG */
72 module_param(msi_x
, int, 0444);
73 MODULE_PARM_DESC(msi_x
, "attempt to use MSI-X if nonzero");
75 #else /* CONFIG_PCI_MSI */
79 #endif /* CONFIG_PCI_MSI */
82 module_param(num_vfs
, int, 0444);
83 MODULE_PARM_DESC(num_vfs
, "enable #num_vfs functions if num_vfs > 0");
86 module_param(probe_vf
, int, 0644);
87 MODULE_PARM_DESC(probe_vf
, "number of vfs to probe by pf driver (num_vfs > 0)");
89 int mlx4_log_num_mgm_entry_size
= MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
90 module_param_named(log_num_mgm_entry_size
,
91 mlx4_log_num_mgm_entry_size
, int, 0444);
92 MODULE_PARM_DESC(log_num_mgm_entry_size
, "log mgm size, that defines the num"
93 " of qp per mcg, for example:"
94 " 10 gives 248.range: 7 <="
95 " log_num_mgm_entry_size <= 12."
96 " To activate device managed"
97 " flow steering when available, set to -1");
99 static bool enable_64b_cqe_eqe
= true;
100 module_param(enable_64b_cqe_eqe
, bool, 0444);
101 MODULE_PARM_DESC(enable_64b_cqe_eqe
,
102 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
104 #define HCA_GLOBAL_CAP_MASK 0
106 #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
108 static char mlx4_version
[] =
109 DRV_NAME
": Mellanox ConnectX core driver v"
110 DRV_VERSION
" (" DRV_RELDATE
")\n";
112 static struct mlx4_profile default_profile
= {
115 .rdmarc_per_qp
= 1 << 4,
119 .num_mtt
= 1 << 20, /* It is really num mtt segements */
122 static int log_num_mac
= 7;
123 module_param_named(log_num_mac
, log_num_mac
, int, 0444);
124 MODULE_PARM_DESC(log_num_mac
, "Log2 max number of MACs per ETH port (1-7)");
126 static int log_num_vlan
;
127 module_param_named(log_num_vlan
, log_num_vlan
, int, 0444);
128 MODULE_PARM_DESC(log_num_vlan
, "Log2 max number of VLANs per ETH port (0-7)");
129 /* Log2 max number of VLANs per ETH port (0-7) */
130 #define MLX4_LOG_NUM_VLANS 7
132 static bool use_prio
;
133 module_param_named(use_prio
, use_prio
, bool, 0444);
134 MODULE_PARM_DESC(use_prio
, "Enable steering by VLAN priority on ETH ports "
137 int log_mtts_per_seg
= ilog2(MLX4_MTT_ENTRY_PER_SEG
);
138 module_param_named(log_mtts_per_seg
, log_mtts_per_seg
, int, 0444);
139 MODULE_PARM_DESC(log_mtts_per_seg
, "Log2 number of MTT entries per segment (1-7)");
141 static int port_type_array
[2] = {MLX4_PORT_TYPE_NONE
, MLX4_PORT_TYPE_NONE
};
142 static int arr_argc
= 2;
143 module_param_array(port_type_array
, int, &arr_argc
, 0444);
144 MODULE_PARM_DESC(port_type_array
, "Array of port types: HW_DEFAULT (0) is default "
145 "1 for IB, 2 for Ethernet");
147 struct mlx4_port_config
{
148 struct list_head list
;
149 enum mlx4_port_type port_type
[MLX4_MAX_PORTS
+ 1];
150 struct pci_dev
*pdev
;
153 static atomic_t pf_loading
= ATOMIC_INIT(0);
155 int mlx4_check_port_params(struct mlx4_dev
*dev
,
156 enum mlx4_port_type
*port_type
)
160 for (i
= 0; i
< dev
->caps
.num_ports
- 1; i
++) {
161 if (port_type
[i
] != port_type
[i
+ 1]) {
162 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
)) {
163 mlx4_err(dev
, "Only same port types supported "
164 "on this HCA, aborting.\n");
170 for (i
= 0; i
< dev
->caps
.num_ports
; i
++) {
171 if (!(port_type
[i
] & dev
->caps
.supported_type
[i
+1])) {
172 mlx4_err(dev
, "Requested port type for port %d is not "
173 "supported on this HCA\n", i
+ 1);
180 static void mlx4_set_port_mask(struct mlx4_dev
*dev
)
184 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
)
185 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
188 static int mlx4_dev_cap(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
)
193 err
= mlx4_QUERY_DEV_CAP(dev
, dev_cap
);
195 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
199 if (dev_cap
->min_page_sz
> PAGE_SIZE
) {
200 mlx4_err(dev
, "HCA minimum page size of %d bigger than "
201 "kernel PAGE_SIZE of %ld, aborting.\n",
202 dev_cap
->min_page_sz
, PAGE_SIZE
);
205 if (dev_cap
->num_ports
> MLX4_MAX_PORTS
) {
206 mlx4_err(dev
, "HCA has %d ports, but we only support %d, "
208 dev_cap
->num_ports
, MLX4_MAX_PORTS
);
212 if (dev_cap
->uar_size
> pci_resource_len(dev
->pdev
, 2)) {
213 mlx4_err(dev
, "HCA reported UAR size of 0x%x bigger than "
214 "PCI resource 2 size of 0x%llx, aborting.\n",
216 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
220 dev
->caps
.num_ports
= dev_cap
->num_ports
;
221 dev
->phys_caps
.num_phys_eqs
= MLX4_MAX_EQ_NUM
;
222 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
223 dev
->caps
.vl_cap
[i
] = dev_cap
->max_vl
[i
];
224 dev
->caps
.ib_mtu_cap
[i
] = dev_cap
->ib_mtu
[i
];
225 dev
->phys_caps
.gid_phys_table_len
[i
] = dev_cap
->max_gids
[i
];
226 dev
->phys_caps
.pkey_phys_table_len
[i
] = dev_cap
->max_pkeys
[i
];
227 /* set gid and pkey table operating lengths by default
228 * to non-sriov values */
229 dev
->caps
.gid_table_len
[i
] = dev_cap
->max_gids
[i
];
230 dev
->caps
.pkey_table_len
[i
] = dev_cap
->max_pkeys
[i
];
231 dev
->caps
.port_width_cap
[i
] = dev_cap
->max_port_width
[i
];
232 dev
->caps
.eth_mtu_cap
[i
] = dev_cap
->eth_mtu
[i
];
233 dev
->caps
.def_mac
[i
] = dev_cap
->def_mac
[i
];
234 dev
->caps
.supported_type
[i
] = dev_cap
->supported_port_types
[i
];
235 dev
->caps
.suggested_type
[i
] = dev_cap
->suggested_type
[i
];
236 dev
->caps
.default_sense
[i
] = dev_cap
->default_sense
[i
];
237 dev
->caps
.trans_type
[i
] = dev_cap
->trans_type
[i
];
238 dev
->caps
.vendor_oui
[i
] = dev_cap
->vendor_oui
[i
];
239 dev
->caps
.wavelength
[i
] = dev_cap
->wavelength
[i
];
240 dev
->caps
.trans_code
[i
] = dev_cap
->trans_code
[i
];
243 dev
->caps
.uar_page_size
= PAGE_SIZE
;
244 dev
->caps
.num_uars
= dev_cap
->uar_size
/ PAGE_SIZE
;
245 dev
->caps
.local_ca_ack_delay
= dev_cap
->local_ca_ack_delay
;
246 dev
->caps
.bf_reg_size
= dev_cap
->bf_reg_size
;
247 dev
->caps
.bf_regs_per_page
= dev_cap
->bf_regs_per_page
;
248 dev
->caps
.max_sq_sg
= dev_cap
->max_sq_sg
;
249 dev
->caps
.max_rq_sg
= dev_cap
->max_rq_sg
;
250 dev
->caps
.max_wqes
= dev_cap
->max_qp_sz
;
251 dev
->caps
.max_qp_init_rdma
= dev_cap
->max_requester_per_qp
;
252 dev
->caps
.max_srq_wqes
= dev_cap
->max_srq_sz
;
253 dev
->caps
.max_srq_sge
= dev_cap
->max_rq_sg
- 1;
254 dev
->caps
.reserved_srqs
= dev_cap
->reserved_srqs
;
255 dev
->caps
.max_sq_desc_sz
= dev_cap
->max_sq_desc_sz
;
256 dev
->caps
.max_rq_desc_sz
= dev_cap
->max_rq_desc_sz
;
258 * Subtract 1 from the limit because we need to allocate a
259 * spare CQE so the HCA HW can tell the difference between an
260 * empty CQ and a full CQ.
262 dev
->caps
.max_cqes
= dev_cap
->max_cq_sz
- 1;
263 dev
->caps
.reserved_cqs
= dev_cap
->reserved_cqs
;
264 dev
->caps
.reserved_eqs
= dev_cap
->reserved_eqs
;
265 dev
->caps
.reserved_mtts
= dev_cap
->reserved_mtts
;
266 dev
->caps
.reserved_mrws
= dev_cap
->reserved_mrws
;
268 /* The first 128 UARs are used for EQ doorbells */
269 dev
->caps
.reserved_uars
= max_t(int, 128, dev_cap
->reserved_uars
);
270 dev
->caps
.reserved_pds
= dev_cap
->reserved_pds
;
271 dev
->caps
.reserved_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
272 dev_cap
->reserved_xrcds
: 0;
273 dev
->caps
.max_xrcds
= (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_XRC
) ?
274 dev_cap
->max_xrcds
: 0;
275 dev
->caps
.mtt_entry_sz
= dev_cap
->mtt_entry_sz
;
277 dev
->caps
.max_msg_sz
= dev_cap
->max_msg_sz
;
278 dev
->caps
.page_size_cap
= ~(u32
) (dev_cap
->min_page_sz
- 1);
279 dev
->caps
.flags
= dev_cap
->flags
;
280 dev
->caps
.flags2
= dev_cap
->flags2
;
281 dev
->caps
.bmme_flags
= dev_cap
->bmme_flags
;
282 dev
->caps
.reserved_lkey
= dev_cap
->reserved_lkey
;
283 dev
->caps
.stat_rate_support
= dev_cap
->stat_rate_support
;
284 dev
->caps
.max_gso_sz
= dev_cap
->max_gso_sz
;
285 dev
->caps
.max_rss_tbl_sz
= dev_cap
->max_rss_tbl_sz
;
287 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
288 if (mlx4_priv(dev
)->pci_dev_data
& MLX4_PCI_DEV_FORCE_SENSE_PORT
)
289 dev
->caps
.flags
|= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
290 /* Don't do sense port on multifunction devices (for now at least) */
291 if (mlx4_is_mfunc(dev
))
292 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
;
294 dev
->caps
.log_num_macs
= log_num_mac
;
295 dev
->caps
.log_num_vlans
= MLX4_LOG_NUM_VLANS
;
296 dev
->caps
.log_num_prios
= use_prio
? 3 : 0;
298 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
299 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_NONE
;
300 if (dev
->caps
.supported_type
[i
]) {
301 /* if only ETH is supported - assign ETH */
302 if (dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_ETH
)
303 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_ETH
;
304 /* if only IB is supported, assign IB */
305 else if (dev
->caps
.supported_type
[i
] ==
307 dev
->caps
.port_type
[i
] = MLX4_PORT_TYPE_IB
;
309 /* if IB and ETH are supported, we set the port
310 * type according to user selection of port type;
311 * if user selected none, take the FW hint */
312 if (port_type_array
[i
- 1] == MLX4_PORT_TYPE_NONE
)
313 dev
->caps
.port_type
[i
] = dev
->caps
.suggested_type
[i
] ?
314 MLX4_PORT_TYPE_ETH
: MLX4_PORT_TYPE_IB
;
316 dev
->caps
.port_type
[i
] = port_type_array
[i
- 1];
320 * Link sensing is allowed on the port if 3 conditions are true:
321 * 1. Both protocols are supported on the port.
322 * 2. Different types are supported on the port
323 * 3. FW declared that it supports link sensing
325 mlx4_priv(dev
)->sense
.sense_allowed
[i
] =
326 ((dev
->caps
.supported_type
[i
] == MLX4_PORT_TYPE_AUTO
) &&
327 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
328 (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
));
331 * If "default_sense" bit is set, we move the port to "AUTO" mode
332 * and perform sense_port FW command to try and set the correct
333 * port type from beginning
335 if (mlx4_priv(dev
)->sense
.sense_allowed
[i
] && dev
->caps
.default_sense
[i
]) {
336 enum mlx4_port_type sensed_port
= MLX4_PORT_TYPE_NONE
;
337 dev
->caps
.possible_type
[i
] = MLX4_PORT_TYPE_AUTO
;
338 mlx4_SENSE_PORT(dev
, i
, &sensed_port
);
339 if (sensed_port
!= MLX4_PORT_TYPE_NONE
)
340 dev
->caps
.port_type
[i
] = sensed_port
;
342 dev
->caps
.possible_type
[i
] = dev
->caps
.port_type
[i
];
345 if (dev
->caps
.log_num_macs
> dev_cap
->log_max_macs
[i
]) {
346 dev
->caps
.log_num_macs
= dev_cap
->log_max_macs
[i
];
347 mlx4_warn(dev
, "Requested number of MACs is too much "
348 "for port %d, reducing to %d.\n",
349 i
, 1 << dev
->caps
.log_num_macs
);
351 if (dev
->caps
.log_num_vlans
> dev_cap
->log_max_vlans
[i
]) {
352 dev
->caps
.log_num_vlans
= dev_cap
->log_max_vlans
[i
];
353 mlx4_warn(dev
, "Requested number of VLANs is too much "
354 "for port %d, reducing to %d.\n",
355 i
, 1 << dev
->caps
.log_num_vlans
);
359 dev
->caps
.max_counters
= 1 << ilog2(dev_cap
->max_counters
);
361 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] = dev_cap
->reserved_qps
;
362 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] =
363 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] =
364 (1 << dev
->caps
.log_num_macs
) *
365 (1 << dev
->caps
.log_num_vlans
) *
366 (1 << dev
->caps
.log_num_prios
) *
368 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
] = MLX4_NUM_FEXCH
;
370 dev
->caps
.reserved_qps
= dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
] +
371 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_ETH_ADDR
] +
372 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_ADDR
] +
373 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FC_EXCH
];
375 dev
->caps
.sqp_demux
= (mlx4_is_master(dev
)) ? MLX4_MAX_NUM_SLAVES
: 0;
377 if (!enable_64b_cqe_eqe
&& !mlx4_is_slave(dev
)) {
379 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) {
380 mlx4_warn(dev
, "64B EQEs/CQEs supported by the device but not enabled\n");
381 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_CQE
;
382 dev
->caps
.flags
&= ~MLX4_DEV_CAP_FLAG_64B_EQE
;
386 if ((dev
->caps
.flags
&
387 (MLX4_DEV_CAP_FLAG_64B_CQE
| MLX4_DEV_CAP_FLAG_64B_EQE
)) &&
389 dev
->caps
.function_caps
|= MLX4_FUNC_CAP_64B_EQE_CQE
;
394 static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev
*dev
,
395 enum pci_bus_speed
*speed
,
396 enum pcie_link_width
*width
)
398 u32 lnkcap1
, lnkcap2
;
401 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
403 *speed
= PCI_SPEED_UNKNOWN
;
404 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
406 err1
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP
, &lnkcap1
);
407 err2
= pcie_capability_read_dword(dev
->pdev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
408 if (!err2
&& lnkcap2
) { /* PCIe r3.0-compliant */
409 if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_8_0GB
)
410 *speed
= PCIE_SPEED_8_0GT
;
411 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_5_0GB
)
412 *speed
= PCIE_SPEED_5_0GT
;
413 else if (lnkcap2
& PCI_EXP_LNKCAP2_SLS_2_5GB
)
414 *speed
= PCIE_SPEED_2_5GT
;
417 *width
= (lnkcap1
& PCI_EXP_LNKCAP_MLW
) >> PCIE_MLW_CAP_SHIFT
;
418 if (!lnkcap2
) { /* pre-r3.0 */
419 if (lnkcap1
& PCI_EXP_LNKCAP_SLS_5_0GB
)
420 *speed
= PCIE_SPEED_5_0GT
;
421 else if (lnkcap1
& PCI_EXP_LNKCAP_SLS_2_5GB
)
422 *speed
= PCIE_SPEED_2_5GT
;
426 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
) {
428 err2
? err2
: -EINVAL
;
433 static void mlx4_check_pcie_caps(struct mlx4_dev
*dev
)
435 enum pcie_link_width width
, width_cap
;
436 enum pci_bus_speed speed
, speed_cap
;
439 #define PCIE_SPEED_STR(speed) \
440 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
441 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
442 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
445 err
= mlx4_get_pcie_dev_link_caps(dev
, &speed_cap
, &width_cap
);
448 "Unable to determine PCIe device BW capabilities\n");
452 err
= pcie_get_minimum_link(dev
->pdev
, &speed
, &width
);
453 if (err
|| speed
== PCI_SPEED_UNKNOWN
||
454 width
== PCIE_LNK_WIDTH_UNKNOWN
) {
456 "Unable to determine PCI device chain minimum BW\n");
460 if (width
!= width_cap
|| speed
!= speed_cap
)
462 "PCIe BW is different than device's capability\n");
464 mlx4_info(dev
, "PCIe link speed is %s, device supports %s\n",
465 PCIE_SPEED_STR(speed
), PCIE_SPEED_STR(speed_cap
));
466 mlx4_info(dev
, "PCIe link width is x%d, device supports x%d\n",
471 /*The function checks if there are live vf, return the num of them*/
472 static int mlx4_how_many_lives_vf(struct mlx4_dev
*dev
)
474 struct mlx4_priv
*priv
= mlx4_priv(dev
);
475 struct mlx4_slave_state
*s_state
;
479 for (i
= 1/*the ppf is 0*/; i
< dev
->num_slaves
; ++i
) {
480 s_state
= &priv
->mfunc
.master
.slave_state
[i
];
481 if (s_state
->active
&& s_state
->last_cmd
!=
482 MLX4_COMM_CMD_RESET
) {
483 mlx4_warn(dev
, "%s: slave: %d is still active\n",
491 int mlx4_get_parav_qkey(struct mlx4_dev
*dev
, u32 qpn
, u32
*qkey
)
493 u32 qk
= MLX4_RESERVED_QKEY_BASE
;
495 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
+ 8 * MLX4_MFUNC_MAX
||
496 qpn
< dev
->phys_caps
.base_proxy_sqpn
)
499 if (qpn
>= dev
->phys_caps
.base_tunnel_sqpn
)
501 qk
+= qpn
- dev
->phys_caps
.base_tunnel_sqpn
;
503 qk
+= qpn
- dev
->phys_caps
.base_proxy_sqpn
;
507 EXPORT_SYMBOL(mlx4_get_parav_qkey
);
509 void mlx4_sync_pkey_table(struct mlx4_dev
*dev
, int slave
, int port
, int i
, int val
)
511 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
513 if (!mlx4_is_master(dev
))
516 priv
->virt2phys_pkey
[slave
][port
- 1][i
] = val
;
518 EXPORT_SYMBOL(mlx4_sync_pkey_table
);
520 void mlx4_put_slave_node_guid(struct mlx4_dev
*dev
, int slave
, __be64 guid
)
522 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
524 if (!mlx4_is_master(dev
))
527 priv
->slave_node_guids
[slave
] = guid
;
529 EXPORT_SYMBOL(mlx4_put_slave_node_guid
);
531 __be64
mlx4_get_slave_node_guid(struct mlx4_dev
*dev
, int slave
)
533 struct mlx4_priv
*priv
= container_of(dev
, struct mlx4_priv
, dev
);
535 if (!mlx4_is_master(dev
))
538 return priv
->slave_node_guids
[slave
];
540 EXPORT_SYMBOL(mlx4_get_slave_node_guid
);
542 int mlx4_is_slave_active(struct mlx4_dev
*dev
, int slave
)
544 struct mlx4_priv
*priv
= mlx4_priv(dev
);
545 struct mlx4_slave_state
*s_slave
;
547 if (!mlx4_is_master(dev
))
550 s_slave
= &priv
->mfunc
.master
.slave_state
[slave
];
551 return !!s_slave
->active
;
553 EXPORT_SYMBOL(mlx4_is_slave_active
);
555 static void slave_adjust_steering_mode(struct mlx4_dev
*dev
,
556 struct mlx4_dev_cap
*dev_cap
,
557 struct mlx4_init_hca_param
*hca_param
)
559 dev
->caps
.steering_mode
= hca_param
->steering_mode
;
560 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
) {
561 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
562 dev
->caps
.fs_log_max_ucast_qp_range_size
=
563 dev_cap
->fs_log_max_ucast_qp_range_size
;
565 dev
->caps
.num_qp_per_mgm
=
566 4 * ((1 << hca_param
->log_mc_entry_sz
)/16 - 2);
568 mlx4_dbg(dev
, "Steering mode is: %s\n",
569 mlx4_steering_mode_str(dev
->caps
.steering_mode
));
572 static int mlx4_slave_cap(struct mlx4_dev
*dev
)
576 struct mlx4_dev_cap dev_cap
;
577 struct mlx4_func_cap func_cap
;
578 struct mlx4_init_hca_param hca_param
;
581 memset(&hca_param
, 0, sizeof(hca_param
));
582 err
= mlx4_QUERY_HCA(dev
, &hca_param
);
584 mlx4_err(dev
, "QUERY_HCA command failed, aborting.\n");
588 /*fail if the hca has an unknown capability */
589 if ((hca_param
.global_caps
| HCA_GLOBAL_CAP_MASK
) !=
590 HCA_GLOBAL_CAP_MASK
) {
591 mlx4_err(dev
, "Unknown hca global capabilities\n");
595 mlx4_log_num_mgm_entry_size
= hca_param
.log_mc_entry_sz
;
597 dev
->caps
.hca_core_clock
= hca_param
.hca_core_clock
;
599 memset(&dev_cap
, 0, sizeof(dev_cap
));
600 dev
->caps
.max_qp_dest_rdma
= 1 << hca_param
.log_rd_per_qp
;
601 err
= mlx4_dev_cap(dev
, &dev_cap
);
603 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
607 err
= mlx4_QUERY_FW(dev
);
609 mlx4_err(dev
, "QUERY_FW command failed: could not get FW version.\n");
611 page_size
= ~dev
->caps
.page_size_cap
+ 1;
612 mlx4_warn(dev
, "HCA minimum page size:%d\n", page_size
);
613 if (page_size
> PAGE_SIZE
) {
614 mlx4_err(dev
, "HCA minimum page size of %d bigger than "
615 "kernel PAGE_SIZE of %ld, aborting.\n",
616 page_size
, PAGE_SIZE
);
620 /* slave gets uar page size from QUERY_HCA fw command */
621 dev
->caps
.uar_page_size
= 1 << (hca_param
.uar_page_sz
+ 12);
623 /* TODO: relax this assumption */
624 if (dev
->caps
.uar_page_size
!= PAGE_SIZE
) {
625 mlx4_err(dev
, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
626 dev
->caps
.uar_page_size
, PAGE_SIZE
);
630 memset(&func_cap
, 0, sizeof(func_cap
));
631 err
= mlx4_QUERY_FUNC_CAP(dev
, 0, &func_cap
);
633 mlx4_err(dev
, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
638 if ((func_cap
.pf_context_behaviour
| PF_CONTEXT_BEHAVIOUR_MASK
) !=
639 PF_CONTEXT_BEHAVIOUR_MASK
) {
640 mlx4_err(dev
, "Unknown pf context behaviour\n");
644 dev
->caps
.num_ports
= func_cap
.num_ports
;
645 dev
->quotas
.qp
= func_cap
.qp_quota
;
646 dev
->quotas
.srq
= func_cap
.srq_quota
;
647 dev
->quotas
.cq
= func_cap
.cq_quota
;
648 dev
->quotas
.mpt
= func_cap
.mpt_quota
;
649 dev
->quotas
.mtt
= func_cap
.mtt_quota
;
650 dev
->caps
.num_qps
= 1 << hca_param
.log_num_qps
;
651 dev
->caps
.num_srqs
= 1 << hca_param
.log_num_srqs
;
652 dev
->caps
.num_cqs
= 1 << hca_param
.log_num_cqs
;
653 dev
->caps
.num_mpts
= 1 << hca_param
.log_mpt_sz
;
654 dev
->caps
.num_eqs
= func_cap
.max_eq
;
655 dev
->caps
.reserved_eqs
= func_cap
.reserved_eq
;
656 dev
->caps
.num_pds
= MLX4_NUM_PDS
;
657 dev
->caps
.num_mgms
= 0;
658 dev
->caps
.num_amgms
= 0;
660 if (dev
->caps
.num_ports
> MLX4_MAX_PORTS
) {
661 mlx4_err(dev
, "HCA has %d ports, but we only support %d, "
662 "aborting.\n", dev
->caps
.num_ports
, MLX4_MAX_PORTS
);
666 dev
->caps
.qp0_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
667 dev
->caps
.qp0_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
668 dev
->caps
.qp1_tunnel
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
669 dev
->caps
.qp1_proxy
= kcalloc(dev
->caps
.num_ports
, sizeof (u32
), GFP_KERNEL
);
671 if (!dev
->caps
.qp0_tunnel
|| !dev
->caps
.qp0_proxy
||
672 !dev
->caps
.qp1_tunnel
|| !dev
->caps
.qp1_proxy
) {
677 for (i
= 1; i
<= dev
->caps
.num_ports
; ++i
) {
678 err
= mlx4_QUERY_FUNC_CAP(dev
, (u32
) i
, &func_cap
);
680 mlx4_err(dev
, "QUERY_FUNC_CAP port command failed for"
681 " port %d, aborting (%d).\n", i
, err
);
684 dev
->caps
.qp0_tunnel
[i
- 1] = func_cap
.qp0_tunnel_qpn
;
685 dev
->caps
.qp0_proxy
[i
- 1] = func_cap
.qp0_proxy_qpn
;
686 dev
->caps
.qp1_tunnel
[i
- 1] = func_cap
.qp1_tunnel_qpn
;
687 dev
->caps
.qp1_proxy
[i
- 1] = func_cap
.qp1_proxy_qpn
;
688 dev
->caps
.port_mask
[i
] = dev
->caps
.port_type
[i
];
689 dev
->caps
.phys_port_id
[i
] = func_cap
.phys_port_id
;
690 if (mlx4_get_slave_pkey_gid_tbl_len(dev
, i
,
691 &dev
->caps
.gid_table_len
[i
],
692 &dev
->caps
.pkey_table_len
[i
]))
696 if (dev
->caps
.uar_page_size
* (dev
->caps
.num_uars
-
697 dev
->caps
.reserved_uars
) >
698 pci_resource_len(dev
->pdev
, 2)) {
699 mlx4_err(dev
, "HCA reported UAR region size of 0x%x bigger than "
700 "PCI resource 2 size of 0x%llx, aborting.\n",
701 dev
->caps
.uar_page_size
* dev
->caps
.num_uars
,
702 (unsigned long long) pci_resource_len(dev
->pdev
, 2));
706 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_EQE_ENABLED
) {
707 dev
->caps
.eqe_size
= 64;
708 dev
->caps
.eqe_factor
= 1;
710 dev
->caps
.eqe_size
= 32;
711 dev
->caps
.eqe_factor
= 0;
714 if (hca_param
.dev_cap_enabled
& MLX4_DEV_CAP_64B_CQE_ENABLED
) {
715 dev
->caps
.cqe_size
= 64;
716 dev
->caps
.userspace_caps
|= MLX4_USER_DEV_CAP_64B_CQE
;
718 dev
->caps
.cqe_size
= 32;
721 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
722 mlx4_warn(dev
, "Timestamping is not supported in slave mode.\n");
724 slave_adjust_steering_mode(dev
, &dev_cap
, &hca_param
);
729 kfree(dev
->caps
.qp0_tunnel
);
730 kfree(dev
->caps
.qp0_proxy
);
731 kfree(dev
->caps
.qp1_tunnel
);
732 kfree(dev
->caps
.qp1_proxy
);
733 dev
->caps
.qp0_tunnel
= dev
->caps
.qp0_proxy
=
734 dev
->caps
.qp1_tunnel
= dev
->caps
.qp1_proxy
= NULL
;
739 static void mlx4_request_modules(struct mlx4_dev
*dev
)
742 int has_ib_port
= false;
743 int has_eth_port
= false;
744 #define EN_DRV_NAME "mlx4_en"
745 #define IB_DRV_NAME "mlx4_ib"
747 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
748 if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_IB
)
750 else if (dev
->caps
.port_type
[port
] == MLX4_PORT_TYPE_ETH
)
754 if (has_ib_port
|| (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_IBOE
))
755 request_module_nowait(IB_DRV_NAME
);
757 request_module_nowait(EN_DRV_NAME
);
761 * Change the port configuration of the device.
762 * Every user of this function must hold the port mutex.
764 int mlx4_change_port_types(struct mlx4_dev
*dev
,
765 enum mlx4_port_type
*port_types
)
771 for (port
= 0; port
< dev
->caps
.num_ports
; port
++) {
772 /* Change the port type only if the new type is different
773 * from the current, and not set to Auto */
774 if (port_types
[port
] != dev
->caps
.port_type
[port
+ 1])
778 mlx4_unregister_device(dev
);
779 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
780 mlx4_CLOSE_PORT(dev
, port
);
781 dev
->caps
.port_type
[port
] = port_types
[port
- 1];
782 err
= mlx4_SET_PORT(dev
, port
, -1);
784 mlx4_err(dev
, "Failed to set port %d, "
789 mlx4_set_port_mask(dev
);
790 err
= mlx4_register_device(dev
);
792 mlx4_err(dev
, "Failed to register device\n");
795 mlx4_request_modules(dev
);
802 static ssize_t
show_port_type(struct device
*dev
,
803 struct device_attribute
*attr
,
806 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
808 struct mlx4_dev
*mdev
= info
->dev
;
812 (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_IB
) ?
814 if (mdev
->caps
.possible_type
[info
->port
] == MLX4_PORT_TYPE_AUTO
)
815 sprintf(buf
, "auto (%s)\n", type
);
817 sprintf(buf
, "%s\n", type
);
822 static ssize_t
set_port_type(struct device
*dev
,
823 struct device_attribute
*attr
,
824 const char *buf
, size_t count
)
826 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
828 struct mlx4_dev
*mdev
= info
->dev
;
829 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
830 enum mlx4_port_type types
[MLX4_MAX_PORTS
];
831 enum mlx4_port_type new_types
[MLX4_MAX_PORTS
];
835 if (!strcmp(buf
, "ib\n"))
836 info
->tmp_type
= MLX4_PORT_TYPE_IB
;
837 else if (!strcmp(buf
, "eth\n"))
838 info
->tmp_type
= MLX4_PORT_TYPE_ETH
;
839 else if (!strcmp(buf
, "auto\n"))
840 info
->tmp_type
= MLX4_PORT_TYPE_AUTO
;
842 mlx4_err(mdev
, "%s is not supported port type\n", buf
);
846 mlx4_stop_sense(mdev
);
847 mutex_lock(&priv
->port_mutex
);
848 /* Possible type is always the one that was delivered */
849 mdev
->caps
.possible_type
[info
->port
] = info
->tmp_type
;
851 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++) {
852 types
[i
] = priv
->port
[i
+1].tmp_type
? priv
->port
[i
+1].tmp_type
:
853 mdev
->caps
.possible_type
[i
+1];
854 if (types
[i
] == MLX4_PORT_TYPE_AUTO
)
855 types
[i
] = mdev
->caps
.port_type
[i
+1];
858 if (!(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_DPDP
) &&
859 !(mdev
->caps
.flags
& MLX4_DEV_CAP_FLAG_SENSE_SUPPORT
)) {
860 for (i
= 1; i
<= mdev
->caps
.num_ports
; i
++) {
861 if (mdev
->caps
.possible_type
[i
] == MLX4_PORT_TYPE_AUTO
) {
862 mdev
->caps
.possible_type
[i
] = mdev
->caps
.port_type
[i
];
868 mlx4_err(mdev
, "Auto sensing is not supported on this HCA. "
869 "Set only 'eth' or 'ib' for both ports "
870 "(should be the same)\n");
874 mlx4_do_sense_ports(mdev
, new_types
, types
);
876 err
= mlx4_check_port_params(mdev
, new_types
);
880 /* We are about to apply the changes after the configuration
881 * was verified, no need to remember the temporary types
883 for (i
= 0; i
< mdev
->caps
.num_ports
; i
++)
884 priv
->port
[i
+ 1].tmp_type
= 0;
886 err
= mlx4_change_port_types(mdev
, new_types
);
889 mlx4_start_sense(mdev
);
890 mutex_unlock(&priv
->port_mutex
);
891 return err
? err
: count
;
902 static inline int int_to_ibta_mtu(int mtu
)
905 case 256: return IB_MTU_256
;
906 case 512: return IB_MTU_512
;
907 case 1024: return IB_MTU_1024
;
908 case 2048: return IB_MTU_2048
;
909 case 4096: return IB_MTU_4096
;
914 static inline int ibta_mtu_to_int(enum ibta_mtu mtu
)
917 case IB_MTU_256
: return 256;
918 case IB_MTU_512
: return 512;
919 case IB_MTU_1024
: return 1024;
920 case IB_MTU_2048
: return 2048;
921 case IB_MTU_4096
: return 4096;
926 static ssize_t
show_port_ib_mtu(struct device
*dev
,
927 struct device_attribute
*attr
,
930 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
932 struct mlx4_dev
*mdev
= info
->dev
;
934 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
)
935 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
938 ibta_mtu_to_int(mdev
->caps
.port_ib_mtu
[info
->port
]));
942 static ssize_t
set_port_ib_mtu(struct device
*dev
,
943 struct device_attribute
*attr
,
944 const char *buf
, size_t count
)
946 struct mlx4_port_info
*info
= container_of(attr
, struct mlx4_port_info
,
948 struct mlx4_dev
*mdev
= info
->dev
;
949 struct mlx4_priv
*priv
= mlx4_priv(mdev
);
950 int err
, port
, mtu
, ibta_mtu
= -1;
952 if (mdev
->caps
.port_type
[info
->port
] == MLX4_PORT_TYPE_ETH
) {
953 mlx4_warn(mdev
, "port level mtu is only used for IB ports\n");
957 err
= kstrtoint(buf
, 0, &mtu
);
959 ibta_mtu
= int_to_ibta_mtu(mtu
);
961 if (err
|| ibta_mtu
< 0) {
962 mlx4_err(mdev
, "%s is invalid IBTA mtu\n", buf
);
966 mdev
->caps
.port_ib_mtu
[info
->port
] = ibta_mtu
;
968 mlx4_stop_sense(mdev
);
969 mutex_lock(&priv
->port_mutex
);
970 mlx4_unregister_device(mdev
);
971 for (port
= 1; port
<= mdev
->caps
.num_ports
; port
++) {
972 mlx4_CLOSE_PORT(mdev
, port
);
973 err
= mlx4_SET_PORT(mdev
, port
, -1);
975 mlx4_err(mdev
, "Failed to set port %d, "
980 err
= mlx4_register_device(mdev
);
982 mutex_unlock(&priv
->port_mutex
);
983 mlx4_start_sense(mdev
);
984 return err
? err
: count
;
987 static int mlx4_load_fw(struct mlx4_dev
*dev
)
989 struct mlx4_priv
*priv
= mlx4_priv(dev
);
992 priv
->fw
.fw_icm
= mlx4_alloc_icm(dev
, priv
->fw
.fw_pages
,
993 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
994 if (!priv
->fw
.fw_icm
) {
995 mlx4_err(dev
, "Couldn't allocate FW area, aborting.\n");
999 err
= mlx4_MAP_FA(dev
, priv
->fw
.fw_icm
);
1001 mlx4_err(dev
, "MAP_FA command failed, aborting.\n");
1005 err
= mlx4_RUN_FW(dev
);
1007 mlx4_err(dev
, "RUN_FW command failed, aborting.\n");
1017 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1021 static int mlx4_init_cmpt_table(struct mlx4_dev
*dev
, u64 cmpt_base
,
1024 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1028 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.cmpt_table
,
1030 ((u64
) (MLX4_CMPT_TYPE_QP
*
1031 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1032 cmpt_entry_sz
, dev
->caps
.num_qps
,
1033 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1038 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.cmpt_table
,
1040 ((u64
) (MLX4_CMPT_TYPE_SRQ
*
1041 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1042 cmpt_entry_sz
, dev
->caps
.num_srqs
,
1043 dev
->caps
.reserved_srqs
, 0, 0);
1047 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.cmpt_table
,
1049 ((u64
) (MLX4_CMPT_TYPE_CQ
*
1050 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1051 cmpt_entry_sz
, dev
->caps
.num_cqs
,
1052 dev
->caps
.reserved_cqs
, 0, 0);
1056 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1058 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.cmpt_table
,
1060 ((u64
) (MLX4_CMPT_TYPE_EQ
*
1061 cmpt_entry_sz
) << MLX4_CMPT_SHIFT
),
1062 cmpt_entry_sz
, num_eqs
, num_eqs
, 0, 0);
1069 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1072 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1075 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1081 static int mlx4_init_icm(struct mlx4_dev
*dev
, struct mlx4_dev_cap
*dev_cap
,
1082 struct mlx4_init_hca_param
*init_hca
, u64 icm_size
)
1084 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1089 err
= mlx4_SET_ICM_SIZE(dev
, icm_size
, &aux_pages
);
1091 mlx4_err(dev
, "SET_ICM_SIZE command failed, aborting.\n");
1095 mlx4_dbg(dev
, "%lld KB of HCA context requires %lld KB aux memory.\n",
1096 (unsigned long long) icm_size
>> 10,
1097 (unsigned long long) aux_pages
<< 2);
1099 priv
->fw
.aux_icm
= mlx4_alloc_icm(dev
, aux_pages
,
1100 GFP_HIGHUSER
| __GFP_NOWARN
, 0);
1101 if (!priv
->fw
.aux_icm
) {
1102 mlx4_err(dev
, "Couldn't allocate aux memory, aborting.\n");
1106 err
= mlx4_MAP_ICM_AUX(dev
, priv
->fw
.aux_icm
);
1108 mlx4_err(dev
, "MAP_ICM_AUX command failed, aborting.\n");
1112 err
= mlx4_init_cmpt_table(dev
, init_hca
->cmpt_base
, dev_cap
->cmpt_entry_sz
);
1114 mlx4_err(dev
, "Failed to map cMPT context memory, aborting.\n");
1119 num_eqs
= (mlx4_is_master(dev
)) ? dev
->phys_caps
.num_phys_eqs
:
1121 err
= mlx4_init_icm_table(dev
, &priv
->eq_table
.table
,
1122 init_hca
->eqc_base
, dev_cap
->eqc_entry_sz
,
1123 num_eqs
, num_eqs
, 0, 0);
1125 mlx4_err(dev
, "Failed to map EQ context memory, aborting.\n");
1126 goto err_unmap_cmpt
;
1130 * Reserved MTT entries must be aligned up to a cacheline
1131 * boundary, since the FW will write to them, while the driver
1132 * writes to all other MTT entries. (The variable
1133 * dev->caps.mtt_entry_sz below is really the MTT segment
1134 * size, not the raw entry size)
1136 dev
->caps
.reserved_mtts
=
1137 ALIGN(dev
->caps
.reserved_mtts
* dev
->caps
.mtt_entry_sz
,
1138 dma_get_cache_alignment()) / dev
->caps
.mtt_entry_sz
;
1140 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.mtt_table
,
1142 dev
->caps
.mtt_entry_sz
,
1144 dev
->caps
.reserved_mtts
, 1, 0);
1146 mlx4_err(dev
, "Failed to map MTT context memory, aborting.\n");
1150 err
= mlx4_init_icm_table(dev
, &priv
->mr_table
.dmpt_table
,
1151 init_hca
->dmpt_base
,
1152 dev_cap
->dmpt_entry_sz
,
1154 dev
->caps
.reserved_mrws
, 1, 1);
1156 mlx4_err(dev
, "Failed to map dMPT context memory, aborting.\n");
1160 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.qp_table
,
1162 dev_cap
->qpc_entry_sz
,
1164 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1167 mlx4_err(dev
, "Failed to map QP context memory, aborting.\n");
1168 goto err_unmap_dmpt
;
1171 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.auxc_table
,
1172 init_hca
->auxc_base
,
1173 dev_cap
->aux_entry_sz
,
1175 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1178 mlx4_err(dev
, "Failed to map AUXC context memory, aborting.\n");
1182 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.altc_table
,
1183 init_hca
->altc_base
,
1184 dev_cap
->altc_entry_sz
,
1186 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1189 mlx4_err(dev
, "Failed to map ALTC context memory, aborting.\n");
1190 goto err_unmap_auxc
;
1193 err
= mlx4_init_icm_table(dev
, &priv
->qp_table
.rdmarc_table
,
1194 init_hca
->rdmarc_base
,
1195 dev_cap
->rdmarc_entry_sz
<< priv
->qp_table
.rdmarc_shift
,
1197 dev
->caps
.reserved_qps_cnt
[MLX4_QP_REGION_FW
],
1200 mlx4_err(dev
, "Failed to map RDMARC context memory, aborting\n");
1201 goto err_unmap_altc
;
1204 err
= mlx4_init_icm_table(dev
, &priv
->cq_table
.table
,
1206 dev_cap
->cqc_entry_sz
,
1208 dev
->caps
.reserved_cqs
, 0, 0);
1210 mlx4_err(dev
, "Failed to map CQ context memory, aborting.\n");
1211 goto err_unmap_rdmarc
;
1214 err
= mlx4_init_icm_table(dev
, &priv
->srq_table
.table
,
1215 init_hca
->srqc_base
,
1216 dev_cap
->srq_entry_sz
,
1218 dev
->caps
.reserved_srqs
, 0, 0);
1220 mlx4_err(dev
, "Failed to map SRQ context memory, aborting.\n");
1225 * For flow steering device managed mode it is required to use
1226 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1227 * required, but for simplicity just map the whole multicast
1228 * group table now. The table isn't very big and it's a lot
1229 * easier than trying to track ref counts.
1231 err
= mlx4_init_icm_table(dev
, &priv
->mcg_table
.table
,
1233 mlx4_get_mgm_entry_size(dev
),
1234 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1235 dev
->caps
.num_mgms
+ dev
->caps
.num_amgms
,
1238 mlx4_err(dev
, "Failed to map MCG context memory, aborting.\n");
1245 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1248 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1251 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1254 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1257 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1260 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1263 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1266 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1269 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1272 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1273 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1274 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1275 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1278 mlx4_UNMAP_ICM_AUX(dev
);
1281 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1286 static void mlx4_free_icms(struct mlx4_dev
*dev
)
1288 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1290 mlx4_cleanup_icm_table(dev
, &priv
->mcg_table
.table
);
1291 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.table
);
1292 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.table
);
1293 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.rdmarc_table
);
1294 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.altc_table
);
1295 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.auxc_table
);
1296 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.qp_table
);
1297 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.dmpt_table
);
1298 mlx4_cleanup_icm_table(dev
, &priv
->mr_table
.mtt_table
);
1299 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.table
);
1300 mlx4_cleanup_icm_table(dev
, &priv
->eq_table
.cmpt_table
);
1301 mlx4_cleanup_icm_table(dev
, &priv
->cq_table
.cmpt_table
);
1302 mlx4_cleanup_icm_table(dev
, &priv
->srq_table
.cmpt_table
);
1303 mlx4_cleanup_icm_table(dev
, &priv
->qp_table
.cmpt_table
);
1305 mlx4_UNMAP_ICM_AUX(dev
);
1306 mlx4_free_icm(dev
, priv
->fw
.aux_icm
, 0);
1309 static void mlx4_slave_exit(struct mlx4_dev
*dev
)
1311 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1313 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1314 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, MLX4_COMM_TIME
))
1315 mlx4_warn(dev
, "Failed to close slave function.\n");
1316 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1319 static int map_bf_area(struct mlx4_dev
*dev
)
1321 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1322 resource_size_t bf_start
;
1323 resource_size_t bf_len
;
1326 if (!dev
->caps
.bf_reg_size
)
1329 bf_start
= pci_resource_start(dev
->pdev
, 2) +
1330 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1331 bf_len
= pci_resource_len(dev
->pdev
, 2) -
1332 (dev
->caps
.num_uars
<< PAGE_SHIFT
);
1333 priv
->bf_mapping
= io_mapping_create_wc(bf_start
, bf_len
);
1334 if (!priv
->bf_mapping
)
1340 static void unmap_bf_area(struct mlx4_dev
*dev
)
1342 if (mlx4_priv(dev
)->bf_mapping
)
1343 io_mapping_free(mlx4_priv(dev
)->bf_mapping
);
1346 cycle_t
mlx4_read_clock(struct mlx4_dev
*dev
)
1348 u32 clockhi
, clocklo
, clockhi1
;
1351 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1353 for (i
= 0; i
< 10; i
++) {
1354 clockhi
= swab32(readl(priv
->clock_mapping
));
1355 clocklo
= swab32(readl(priv
->clock_mapping
+ 4));
1356 clockhi1
= swab32(readl(priv
->clock_mapping
));
1357 if (clockhi
== clockhi1
)
1361 cycles
= (u64
) clockhi
<< 32 | (u64
) clocklo
;
1365 EXPORT_SYMBOL_GPL(mlx4_read_clock
);
1368 static int map_internal_clock(struct mlx4_dev
*dev
)
1370 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1372 priv
->clock_mapping
=
1373 ioremap(pci_resource_start(dev
->pdev
, priv
->fw
.clock_bar
) +
1374 priv
->fw
.clock_offset
, MLX4_CLOCK_SIZE
);
1376 if (!priv
->clock_mapping
)
1382 static void unmap_internal_clock(struct mlx4_dev
*dev
)
1384 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1386 if (priv
->clock_mapping
)
1387 iounmap(priv
->clock_mapping
);
1390 static void mlx4_close_hca(struct mlx4_dev
*dev
)
1392 unmap_internal_clock(dev
);
1394 if (mlx4_is_slave(dev
))
1395 mlx4_slave_exit(dev
);
1397 mlx4_CLOSE_HCA(dev
, 0);
1398 mlx4_free_icms(dev
);
1400 mlx4_free_icm(dev
, mlx4_priv(dev
)->fw
.fw_icm
, 0);
1404 static int mlx4_init_slave(struct mlx4_dev
*dev
)
1406 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1407 u64 dma
= (u64
) priv
->mfunc
.vhcr_dma
;
1408 int ret_from_reset
= 0;
1410 u32 cmd_channel_ver
;
1412 if (atomic_read(&pf_loading
)) {
1413 mlx4_warn(dev
, "PF is not ready. Deferring probe\n");
1414 return -EPROBE_DEFER
;
1417 mutex_lock(&priv
->cmd
.slave_cmd_mutex
);
1418 priv
->cmd
.max_cmds
= 1;
1419 mlx4_warn(dev
, "Sending reset\n");
1420 ret_from_reset
= mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0,
1422 /* if we are in the middle of flr the slave will try
1423 * NUM_OF_RESET_RETRIES times before leaving.*/
1424 if (ret_from_reset
) {
1425 if (MLX4_DELAY_RESET_SLAVE
== ret_from_reset
) {
1426 mlx4_warn(dev
, "slave is currently in the "
1427 "middle of FLR. Deferring probe.\n");
1428 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1429 return -EPROBE_DEFER
;
1434 /* check the driver version - the slave I/F revision
1435 * must match the master's */
1436 slave_read
= swab32(readl(&priv
->mfunc
.comm
->slave_read
));
1437 cmd_channel_ver
= mlx4_comm_get_version();
1439 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver
) !=
1440 MLX4_COMM_GET_IF_REV(slave_read
)) {
1441 mlx4_err(dev
, "slave driver version is not supported"
1442 " by the master\n");
1446 mlx4_warn(dev
, "Sending vhcr0\n");
1447 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR0
, dma
>> 48,
1450 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR1
, dma
>> 32,
1453 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR2
, dma
>> 16,
1456 if (mlx4_comm_cmd(dev
, MLX4_COMM_CMD_VHCR_EN
, dma
, MLX4_COMM_TIME
))
1459 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1463 mlx4_comm_cmd(dev
, MLX4_COMM_CMD_RESET
, 0, 0);
1464 mutex_unlock(&priv
->cmd
.slave_cmd_mutex
);
1468 static void mlx4_parav_master_pf_caps(struct mlx4_dev
*dev
)
1472 for (i
= 1; i
<= dev
->caps
.num_ports
; i
++) {
1473 dev
->caps
.gid_table_len
[i
] = 1;
1474 dev
->caps
.pkey_table_len
[i
] =
1475 dev
->phys_caps
.pkey_phys_table_len
[i
] - 1;
1479 static int choose_log_fs_mgm_entry_size(int qp_per_entry
)
1481 int i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
;
1483 for (i
= MLX4_MIN_MGM_LOG_ENTRY_SIZE
; i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
;
1485 if (qp_per_entry
<= 4 * ((1 << i
) / 16 - 2))
1489 return (i
<= MLX4_MAX_MGM_LOG_ENTRY_SIZE
) ? i
: -1;
1492 static void choose_steering_mode(struct mlx4_dev
*dev
,
1493 struct mlx4_dev_cap
*dev_cap
)
1495 if (mlx4_log_num_mgm_entry_size
== -1 &&
1496 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_FS_EN
&&
1497 (!mlx4_is_mfunc(dev
) ||
1498 (dev_cap
->fs_max_num_qp_per_entry
>= (num_vfs
+ 1))) &&
1499 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
) >=
1500 MLX4_MIN_MGM_LOG_ENTRY_SIZE
) {
1501 dev
->oper_log_mgm_entry_size
=
1502 choose_log_fs_mgm_entry_size(dev_cap
->fs_max_num_qp_per_entry
);
1503 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_DEVICE_MANAGED
;
1504 dev
->caps
.num_qp_per_mgm
= dev_cap
->fs_max_num_qp_per_entry
;
1505 dev
->caps
.fs_log_max_ucast_qp_range_size
=
1506 dev_cap
->fs_log_max_ucast_qp_range_size
;
1508 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
&&
1509 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1510 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_B0
;
1512 dev
->caps
.steering_mode
= MLX4_STEERING_MODE_A0
;
1514 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_UC_STEER
||
1515 dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
)
1516 mlx4_warn(dev
, "Must have both UC_STEER and MC_STEER flags "
1517 "set to use B0 steering. Falling back to A0 steering mode.\n");
1519 dev
->oper_log_mgm_entry_size
=
1520 mlx4_log_num_mgm_entry_size
> 0 ?
1521 mlx4_log_num_mgm_entry_size
:
1522 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE
;
1523 dev
->caps
.num_qp_per_mgm
= mlx4_get_qp_per_mgm(dev
);
1525 mlx4_dbg(dev
, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1526 "modparam log_num_mgm_entry_size = %d\n",
1527 mlx4_steering_mode_str(dev
->caps
.steering_mode
),
1528 dev
->oper_log_mgm_entry_size
,
1529 mlx4_log_num_mgm_entry_size
);
1532 static void choose_tunnel_offload_mode(struct mlx4_dev
*dev
,
1533 struct mlx4_dev_cap
*dev_cap
)
1535 if (dev
->caps
.steering_mode
== MLX4_STEERING_MODE_DEVICE_MANAGED
&&
1536 dev_cap
->flags2
& MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
)
1537 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
;
1539 dev
->caps
.tunnel_offload_mode
= MLX4_TUNNEL_OFFLOAD_MODE_NONE
;
1541 mlx4_dbg(dev
, "Tunneling offload mode is: %s\n", (dev
->caps
.tunnel_offload_mode
1542 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN
) ? "vxlan" : "none");
1545 static int mlx4_init_hca(struct mlx4_dev
*dev
)
1547 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1548 struct mlx4_adapter adapter
;
1549 struct mlx4_dev_cap dev_cap
;
1550 struct mlx4_mod_stat_cfg mlx4_cfg
;
1551 struct mlx4_profile profile
;
1552 struct mlx4_init_hca_param init_hca
;
1556 if (!mlx4_is_slave(dev
)) {
1557 err
= mlx4_QUERY_FW(dev
);
1560 mlx4_info(dev
, "non-primary physical function, skipping.\n");
1562 mlx4_err(dev
, "QUERY_FW command failed, aborting.\n");
1566 err
= mlx4_load_fw(dev
);
1568 mlx4_err(dev
, "Failed to start FW, aborting.\n");
1572 mlx4_cfg
.log_pg_sz_m
= 1;
1573 mlx4_cfg
.log_pg_sz
= 0;
1574 err
= mlx4_MOD_STAT_CFG(dev
, &mlx4_cfg
);
1576 mlx4_warn(dev
, "Failed to override log_pg_sz parameter\n");
1578 err
= mlx4_dev_cap(dev
, &dev_cap
);
1580 mlx4_err(dev
, "QUERY_DEV_CAP command failed, aborting.\n");
1584 choose_steering_mode(dev
, &dev_cap
);
1585 choose_tunnel_offload_mode(dev
, &dev_cap
);
1587 err
= mlx4_get_phys_port_id(dev
);
1589 mlx4_err(dev
, "Fail to get physical port id\n");
1591 if (mlx4_is_master(dev
))
1592 mlx4_parav_master_pf_caps(dev
);
1594 profile
= default_profile
;
1595 if (dev
->caps
.steering_mode
==
1596 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1597 profile
.num_mcg
= MLX4_FS_NUM_MCG
;
1599 icm_size
= mlx4_make_profile(dev
, &profile
, &dev_cap
,
1601 if ((long long) icm_size
< 0) {
1606 dev
->caps
.max_fmr_maps
= (1 << (32 - ilog2(dev
->caps
.num_mpts
))) - 1;
1608 init_hca
.log_uar_sz
= ilog2(dev
->caps
.num_uars
);
1609 init_hca
.uar_page_sz
= PAGE_SHIFT
- 12;
1610 init_hca
.mw_enabled
= 0;
1611 if (dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_MEM_WINDOW
||
1612 dev
->caps
.bmme_flags
& MLX4_BMME_FLAG_TYPE_2_WIN
)
1613 init_hca
.mw_enabled
= INIT_HCA_TPT_MW_ENABLE
;
1615 err
= mlx4_init_icm(dev
, &dev_cap
, &init_hca
, icm_size
);
1619 err
= mlx4_INIT_HCA(dev
, &init_hca
);
1621 mlx4_err(dev
, "INIT_HCA command failed, aborting.\n");
1625 * If TS is supported by FW
1626 * read HCA frequency by QUERY_HCA command
1628 if (dev
->caps
.flags2
& MLX4_DEV_CAP_FLAG2_TS
) {
1629 memset(&init_hca
, 0, sizeof(init_hca
));
1630 err
= mlx4_QUERY_HCA(dev
, &init_hca
);
1632 mlx4_err(dev
, "QUERY_HCA command failed, disable timestamp.\n");
1633 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1635 dev
->caps
.hca_core_clock
=
1636 init_hca
.hca_core_clock
;
1639 /* In case we got HCA frequency 0 - disable timestamping
1640 * to avoid dividing by zero
1642 if (!dev
->caps
.hca_core_clock
) {
1643 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1645 "HCA frequency is 0. Timestamping is not supported.");
1646 } else if (map_internal_clock(dev
)) {
1648 * Map internal clock,
1649 * in case of failure disable timestamping
1651 dev
->caps
.flags2
&= ~MLX4_DEV_CAP_FLAG2_TS
;
1652 mlx4_err(dev
, "Failed to map internal clock. Timestamping is not supported.\n");
1656 err
= mlx4_init_slave(dev
);
1658 if (err
!= -EPROBE_DEFER
)
1659 mlx4_err(dev
, "Failed to initialize slave\n");
1663 err
= mlx4_slave_cap(dev
);
1665 mlx4_err(dev
, "Failed to obtain slave caps\n");
1670 if (map_bf_area(dev
))
1671 mlx4_dbg(dev
, "Failed to map blue flame area\n");
1673 /*Only the master set the ports, all the rest got it from it.*/
1674 if (!mlx4_is_slave(dev
))
1675 mlx4_set_port_mask(dev
);
1677 err
= mlx4_QUERY_ADAPTER(dev
, &adapter
);
1679 mlx4_err(dev
, "QUERY_ADAPTER command failed, aborting.\n");
1683 priv
->eq_table
.inta_pin
= adapter
.inta_pin
;
1684 memcpy(dev
->board_id
, adapter
.board_id
, sizeof dev
->board_id
);
1689 unmap_internal_clock(dev
);
1693 if (mlx4_is_slave(dev
))
1694 mlx4_slave_exit(dev
);
1696 mlx4_CLOSE_HCA(dev
, 0);
1699 if (!mlx4_is_slave(dev
))
1700 mlx4_free_icms(dev
);
1703 if (!mlx4_is_slave(dev
)) {
1705 mlx4_free_icm(dev
, priv
->fw
.fw_icm
, 0);
1710 static int mlx4_init_counters_table(struct mlx4_dev
*dev
)
1712 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1715 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1718 nent
= dev
->caps
.max_counters
;
1719 return mlx4_bitmap_init(&priv
->counters_bitmap
, nent
, nent
- 1, 0, 0);
1722 static void mlx4_cleanup_counters_table(struct mlx4_dev
*dev
)
1724 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->counters_bitmap
);
1727 int __mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1729 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1731 if (!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_COUNTERS
))
1734 *idx
= mlx4_bitmap_alloc(&priv
->counters_bitmap
);
1741 int mlx4_counter_alloc(struct mlx4_dev
*dev
, u32
*idx
)
1746 if (mlx4_is_mfunc(dev
)) {
1747 err
= mlx4_cmd_imm(dev
, 0, &out_param
, RES_COUNTER
,
1748 RES_OP_RESERVE
, MLX4_CMD_ALLOC_RES
,
1749 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_WRAPPED
);
1751 *idx
= get_param_l(&out_param
);
1755 return __mlx4_counter_alloc(dev
, idx
);
1757 EXPORT_SYMBOL_GPL(mlx4_counter_alloc
);
1759 void __mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1761 mlx4_bitmap_free(&mlx4_priv(dev
)->counters_bitmap
, idx
, MLX4_USE_RR
);
1765 void mlx4_counter_free(struct mlx4_dev
*dev
, u32 idx
)
1769 if (mlx4_is_mfunc(dev
)) {
1770 set_param_l(&in_param
, idx
);
1771 mlx4_cmd(dev
, in_param
, RES_COUNTER
, RES_OP_RESERVE
,
1772 MLX4_CMD_FREE_RES
, MLX4_CMD_TIME_CLASS_A
,
1776 __mlx4_counter_free(dev
, idx
);
1778 EXPORT_SYMBOL_GPL(mlx4_counter_free
);
1780 static int mlx4_setup_hca(struct mlx4_dev
*dev
)
1782 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1785 __be32 ib_port_default_caps
;
1787 err
= mlx4_init_uar_table(dev
);
1789 mlx4_err(dev
, "Failed to initialize "
1790 "user access region table, aborting.\n");
1794 err
= mlx4_uar_alloc(dev
, &priv
->driver_uar
);
1796 mlx4_err(dev
, "Failed to allocate driver access region, "
1798 goto err_uar_table_free
;
1801 priv
->kar
= ioremap((phys_addr_t
) priv
->driver_uar
.pfn
<< PAGE_SHIFT
, PAGE_SIZE
);
1803 mlx4_err(dev
, "Couldn't map kernel access region, "
1809 err
= mlx4_init_pd_table(dev
);
1811 mlx4_err(dev
, "Failed to initialize "
1812 "protection domain table, aborting.\n");
1816 err
= mlx4_init_xrcd_table(dev
);
1818 mlx4_err(dev
, "Failed to initialize "
1819 "reliable connection domain table, aborting.\n");
1820 goto err_pd_table_free
;
1823 err
= mlx4_init_mr_table(dev
);
1825 mlx4_err(dev
, "Failed to initialize "
1826 "memory region table, aborting.\n");
1827 goto err_xrcd_table_free
;
1830 if (!mlx4_is_slave(dev
)) {
1831 err
= mlx4_init_mcg_table(dev
);
1833 mlx4_err(dev
, "Failed to initialize multicast group table, aborting.\n");
1834 goto err_mr_table_free
;
1838 err
= mlx4_init_eq_table(dev
);
1840 mlx4_err(dev
, "Failed to initialize "
1841 "event queue table, aborting.\n");
1842 goto err_mcg_table_free
;
1845 err
= mlx4_cmd_use_events(dev
);
1847 mlx4_err(dev
, "Failed to switch to event-driven "
1848 "firmware commands, aborting.\n");
1849 goto err_eq_table_free
;
1852 err
= mlx4_NOP(dev
);
1854 if (dev
->flags
& MLX4_FLAG_MSI_X
) {
1855 mlx4_warn(dev
, "NOP command failed to generate MSI-X "
1856 "interrupt IRQ %d).\n",
1857 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1858 mlx4_warn(dev
, "Trying again without MSI-X.\n");
1860 mlx4_err(dev
, "NOP command failed to generate interrupt "
1861 "(IRQ %d), aborting.\n",
1862 priv
->eq_table
.eq
[dev
->caps
.num_comp_vectors
].irq
);
1863 mlx4_err(dev
, "BIOS or ACPI interrupt routing problem?\n");
1869 mlx4_dbg(dev
, "NOP command IRQ test passed\n");
1871 err
= mlx4_init_cq_table(dev
);
1873 mlx4_err(dev
, "Failed to initialize "
1874 "completion queue table, aborting.\n");
1878 err
= mlx4_init_srq_table(dev
);
1880 mlx4_err(dev
, "Failed to initialize "
1881 "shared receive queue table, aborting.\n");
1882 goto err_cq_table_free
;
1885 err
= mlx4_init_qp_table(dev
);
1887 mlx4_err(dev
, "Failed to initialize "
1888 "queue pair table, aborting.\n");
1889 goto err_srq_table_free
;
1892 err
= mlx4_init_counters_table(dev
);
1893 if (err
&& err
!= -ENOENT
) {
1894 mlx4_err(dev
, "Failed to initialize counters table, aborting.\n");
1895 goto err_qp_table_free
;
1898 if (!mlx4_is_slave(dev
)) {
1899 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
1900 ib_port_default_caps
= 0;
1901 err
= mlx4_get_port_ib_caps(dev
, port
,
1902 &ib_port_default_caps
);
1904 mlx4_warn(dev
, "failed to get port %d default "
1905 "ib capabilities (%d). Continuing "
1906 "with caps = 0\n", port
, err
);
1907 dev
->caps
.ib_port_def_cap
[port
] = ib_port_default_caps
;
1909 /* initialize per-slave default ib port capabilities */
1910 if (mlx4_is_master(dev
)) {
1912 for (i
= 0; i
< dev
->num_slaves
; i
++) {
1913 if (i
== mlx4_master_func_num(dev
))
1915 priv
->mfunc
.master
.slave_state
[i
].ib_cap_mask
[port
] =
1916 ib_port_default_caps
;
1920 if (mlx4_is_mfunc(dev
))
1921 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_2048
;
1923 dev
->caps
.port_ib_mtu
[port
] = IB_MTU_4096
;
1925 err
= mlx4_SET_PORT(dev
, port
, mlx4_is_master(dev
) ?
1926 dev
->caps
.pkey_table_len
[port
] : -1);
1928 mlx4_err(dev
, "Failed to set port %d, aborting\n",
1930 goto err_counters_table_free
;
1937 err_counters_table_free
:
1938 mlx4_cleanup_counters_table(dev
);
1941 mlx4_cleanup_qp_table(dev
);
1944 mlx4_cleanup_srq_table(dev
);
1947 mlx4_cleanup_cq_table(dev
);
1950 mlx4_cmd_use_polling(dev
);
1953 mlx4_cleanup_eq_table(dev
);
1956 if (!mlx4_is_slave(dev
))
1957 mlx4_cleanup_mcg_table(dev
);
1960 mlx4_cleanup_mr_table(dev
);
1962 err_xrcd_table_free
:
1963 mlx4_cleanup_xrcd_table(dev
);
1966 mlx4_cleanup_pd_table(dev
);
1972 mlx4_uar_free(dev
, &priv
->driver_uar
);
1975 mlx4_cleanup_uar_table(dev
);
1979 static void mlx4_enable_msi_x(struct mlx4_dev
*dev
)
1981 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1982 struct msix_entry
*entries
;
1983 int nreq
= min_t(int, dev
->caps
.num_ports
*
1984 min_t(int, netif_get_num_default_rss_queues() + 1,
1985 MAX_MSIX_P_PORT
) + MSIX_LEGACY_SZ
, MAX_MSIX
);
1990 nreq
= min_t(int, dev
->caps
.num_eqs
- dev
->caps
.reserved_eqs
,
1993 entries
= kcalloc(nreq
, sizeof *entries
, GFP_KERNEL
);
1997 for (i
= 0; i
< nreq
; ++i
)
1998 entries
[i
].entry
= i
;
2001 err
= pci_enable_msix(dev
->pdev
, entries
, nreq
);
2003 /* Try again if at least 2 vectors are available */
2005 mlx4_info(dev
, "Requested %d vectors, "
2006 "but only %d MSI-X vectors available, "
2007 "trying again\n", nreq
, err
);
2016 MSIX_LEGACY_SZ
+ dev
->caps
.num_ports
* MIN_MSIX_P_PORT
) {
2017 /*Working in legacy mode , all EQ's shared*/
2018 dev
->caps
.comp_pool
= 0;
2019 dev
->caps
.num_comp_vectors
= nreq
- 1;
2021 dev
->caps
.comp_pool
= nreq
- MSIX_LEGACY_SZ
;
2022 dev
->caps
.num_comp_vectors
= MSIX_LEGACY_SZ
- 1;
2024 for (i
= 0; i
< nreq
; ++i
)
2025 priv
->eq_table
.eq
[i
].irq
= entries
[i
].vector
;
2027 dev
->flags
|= MLX4_FLAG_MSI_X
;
2034 dev
->caps
.num_comp_vectors
= 1;
2035 dev
->caps
.comp_pool
= 0;
2037 for (i
= 0; i
< 2; ++i
)
2038 priv
->eq_table
.eq
[i
].irq
= dev
->pdev
->irq
;
2041 static int mlx4_init_port_info(struct mlx4_dev
*dev
, int port
)
2043 struct mlx4_port_info
*info
= &mlx4_priv(dev
)->port
[port
];
2048 if (!mlx4_is_slave(dev
)) {
2049 mlx4_init_mac_table(dev
, &info
->mac_table
);
2050 mlx4_init_vlan_table(dev
, &info
->vlan_table
);
2051 info
->base_qpn
= mlx4_get_base_qpn(dev
, port
);
2054 sprintf(info
->dev_name
, "mlx4_port%d", port
);
2055 info
->port_attr
.attr
.name
= info
->dev_name
;
2056 if (mlx4_is_mfunc(dev
))
2057 info
->port_attr
.attr
.mode
= S_IRUGO
;
2059 info
->port_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2060 info
->port_attr
.store
= set_port_type
;
2062 info
->port_attr
.show
= show_port_type
;
2063 sysfs_attr_init(&info
->port_attr
.attr
);
2065 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_attr
);
2067 mlx4_err(dev
, "Failed to create file for port %d\n", port
);
2071 sprintf(info
->dev_mtu_name
, "mlx4_port%d_mtu", port
);
2072 info
->port_mtu_attr
.attr
.name
= info
->dev_mtu_name
;
2073 if (mlx4_is_mfunc(dev
))
2074 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
;
2076 info
->port_mtu_attr
.attr
.mode
= S_IRUGO
| S_IWUSR
;
2077 info
->port_mtu_attr
.store
= set_port_ib_mtu
;
2079 info
->port_mtu_attr
.show
= show_port_ib_mtu
;
2080 sysfs_attr_init(&info
->port_mtu_attr
.attr
);
2082 err
= device_create_file(&dev
->pdev
->dev
, &info
->port_mtu_attr
);
2084 mlx4_err(dev
, "Failed to create mtu file for port %d\n", port
);
2085 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2092 static void mlx4_cleanup_port_info(struct mlx4_port_info
*info
)
2097 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_attr
);
2098 device_remove_file(&info
->dev
->pdev
->dev
, &info
->port_mtu_attr
);
2101 static int mlx4_init_steering(struct mlx4_dev
*dev
)
2103 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2104 int num_entries
= dev
->caps
.num_ports
;
2107 priv
->steer
= kzalloc(sizeof(struct mlx4_steer
) * num_entries
, GFP_KERNEL
);
2111 for (i
= 0; i
< num_entries
; i
++)
2112 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2113 INIT_LIST_HEAD(&priv
->steer
[i
].promisc_qps
[j
]);
2114 INIT_LIST_HEAD(&priv
->steer
[i
].steer_entries
[j
]);
2119 static void mlx4_clear_steering(struct mlx4_dev
*dev
)
2121 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2122 struct mlx4_steer_index
*entry
, *tmp_entry
;
2123 struct mlx4_promisc_qp
*pqp
, *tmp_pqp
;
2124 int num_entries
= dev
->caps
.num_ports
;
2127 for (i
= 0; i
< num_entries
; i
++) {
2128 for (j
= 0; j
< MLX4_NUM_STEERS
; j
++) {
2129 list_for_each_entry_safe(pqp
, tmp_pqp
,
2130 &priv
->steer
[i
].promisc_qps
[j
],
2132 list_del(&pqp
->list
);
2135 list_for_each_entry_safe(entry
, tmp_entry
,
2136 &priv
->steer
[i
].steer_entries
[j
],
2138 list_del(&entry
->list
);
2139 list_for_each_entry_safe(pqp
, tmp_pqp
,
2142 list_del(&pqp
->list
);
2152 static int extended_func_num(struct pci_dev
*pdev
)
2154 return PCI_SLOT(pdev
->devfn
) * 8 + PCI_FUNC(pdev
->devfn
);
2157 #define MLX4_OWNER_BASE 0x8069c
2158 #define MLX4_OWNER_SIZE 4
2160 static int mlx4_get_ownership(struct mlx4_dev
*dev
)
2162 void __iomem
*owner
;
2165 if (pci_channel_offline(dev
->pdev
))
2168 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2171 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2180 static void mlx4_free_ownership(struct mlx4_dev
*dev
)
2182 void __iomem
*owner
;
2184 if (pci_channel_offline(dev
->pdev
))
2187 owner
= ioremap(pci_resource_start(dev
->pdev
, 0) + MLX4_OWNER_BASE
,
2190 mlx4_err(dev
, "Failed to obtain ownership bit\n");
2198 static int __mlx4_init_one(struct pci_dev
*pdev
, int pci_dev_data
)
2200 struct mlx4_priv
*priv
;
2201 struct mlx4_dev
*dev
;
2205 pr_info(DRV_NAME
": Initializing %s\n", pci_name(pdev
));
2207 err
= pci_enable_device(pdev
);
2209 dev_err(&pdev
->dev
, "Cannot enable PCI device, "
2214 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2215 * per port, we must limit the number of VFs to 63 (since their are
2218 if (num_vfs
>= MLX4_MAX_NUM_VF
) {
2220 "Requested more VF's (%d) than allowed (%d)\n",
2221 num_vfs
, MLX4_MAX_NUM_VF
- 1);
2226 pr_err("num_vfs module parameter cannot be negative\n");
2232 if (!(pci_dev_data
& MLX4_PCI_DEV_IS_VF
) &&
2233 !(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2234 dev_err(&pdev
->dev
, "Missing DCS, aborting."
2235 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2236 pci_dev_data
, pci_resource_flags(pdev
, 0));
2238 goto err_disable_pdev
;
2240 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
2241 dev_err(&pdev
->dev
, "Missing UAR, aborting.\n");
2243 goto err_disable_pdev
;
2246 err
= pci_request_regions(pdev
, DRV_NAME
);
2248 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
2249 goto err_disable_pdev
;
2252 pci_set_master(pdev
);
2254 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
2256 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask.\n");
2257 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
2259 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting.\n");
2260 goto err_release_regions
;
2263 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
2265 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit "
2266 "consistent PCI DMA mask.\n");
2267 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
2269 dev_err(&pdev
->dev
, "Can't set consistent PCI DMA mask, "
2271 goto err_release_regions
;
2275 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2276 dma_set_max_seg_size(&pdev
->dev
, 1024 * 1024 * 1024);
2278 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
2281 goto err_release_regions
;
2286 INIT_LIST_HEAD(&priv
->ctx_list
);
2287 spin_lock_init(&priv
->ctx_lock
);
2289 mutex_init(&priv
->port_mutex
);
2291 INIT_LIST_HEAD(&priv
->pgdir_list
);
2292 mutex_init(&priv
->pgdir_mutex
);
2294 INIT_LIST_HEAD(&priv
->bf_list
);
2295 mutex_init(&priv
->bf_mutex
);
2297 dev
->rev_id
= pdev
->revision
;
2298 dev
->numa_node
= dev_to_node(&pdev
->dev
);
2299 /* Detect if this device is a virtual function */
2300 if (pci_dev_data
& MLX4_PCI_DEV_IS_VF
) {
2301 /* When acting as pf, we normally skip vfs unless explicitly
2302 * requested to probe them. */
2303 if (num_vfs
&& extended_func_num(pdev
) > probe_vf
) {
2304 mlx4_warn(dev
, "Skipping virtual function:%d\n",
2305 extended_func_num(pdev
));
2309 mlx4_warn(dev
, "Detected virtual function - running in slave mode\n");
2310 dev
->flags
|= MLX4_FLAG_SLAVE
;
2312 /* We reset the device and enable SRIOV only for physical
2313 * devices. Try to claim ownership on the device;
2314 * if already taken, skip -- do not allow multiple PFs */
2315 err
= mlx4_get_ownership(dev
);
2320 mlx4_warn(dev
, "Multiple PFs not yet supported."
2328 mlx4_warn(dev
, "Enabling SR-IOV with %d VFs\n", num_vfs
);
2330 atomic_inc(&pf_loading
);
2331 err
= pci_enable_sriov(pdev
, num_vfs
);
2332 atomic_dec(&pf_loading
);
2335 mlx4_err(dev
, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2339 mlx4_warn(dev
, "Running in master mode\n");
2340 dev
->flags
|= MLX4_FLAG_SRIOV
|
2342 dev
->num_vfs
= num_vfs
;
2346 atomic_set(&priv
->opreq_count
, 0);
2347 INIT_WORK(&priv
->opreq_task
, mlx4_opreq_action
);
2350 * Now reset the HCA before we touch the PCI capabilities or
2351 * attempt a firmware command, since a boot ROM may have left
2352 * the HCA in an undefined state.
2354 err
= mlx4_reset(dev
);
2356 mlx4_err(dev
, "Failed to reset HCA, aborting.\n");
2362 err
= mlx4_cmd_init(dev
);
2364 mlx4_err(dev
, "Failed to init command interface, aborting.\n");
2368 /* In slave functions, the communication channel must be initialized
2369 * before posting commands. Also, init num_slaves before calling
2371 if (mlx4_is_mfunc(dev
)) {
2372 if (mlx4_is_master(dev
))
2373 dev
->num_slaves
= MLX4_MAX_NUM_SLAVES
;
2375 dev
->num_slaves
= 0;
2376 err
= mlx4_multi_func_init(dev
);
2378 mlx4_err(dev
, "Failed to init slave mfunc"
2379 " interface, aborting.\n");
2385 err
= mlx4_init_hca(dev
);
2387 if (err
== -EACCES
) {
2388 /* Not primary Physical function
2389 * Running in slave mode */
2390 mlx4_cmd_cleanup(dev
);
2391 dev
->flags
|= MLX4_FLAG_SLAVE
;
2392 dev
->flags
&= ~MLX4_FLAG_MASTER
;
2398 /* check if the device is functioning at its maximum possible speed.
2399 * No return code for this call, just warn the user in case of PCI
2400 * express device capabilities are under-satisfied by the bus.
2402 mlx4_check_pcie_caps(dev
);
2404 /* In master functions, the communication channel must be initialized
2405 * after obtaining its address from fw */
2406 if (mlx4_is_master(dev
)) {
2407 err
= mlx4_multi_func_init(dev
);
2409 mlx4_err(dev
, "Failed to init master mfunc"
2410 "interface, aborting.\n");
2415 err
= mlx4_alloc_eq_table(dev
);
2417 goto err_master_mfunc
;
2419 priv
->msix_ctl
.pool_bm
= 0;
2420 mutex_init(&priv
->msix_ctl
.pool_lock
);
2422 mlx4_enable_msi_x(dev
);
2423 if ((mlx4_is_mfunc(dev
)) &&
2424 !(dev
->flags
& MLX4_FLAG_MSI_X
)) {
2426 mlx4_err(dev
, "INTx is not supported in multi-function mode."
2431 if (!mlx4_is_slave(dev
)) {
2432 err
= mlx4_init_steering(dev
);
2437 err
= mlx4_setup_hca(dev
);
2438 if (err
== -EBUSY
&& (dev
->flags
& MLX4_FLAG_MSI_X
) &&
2439 !mlx4_is_mfunc(dev
)) {
2440 dev
->flags
&= ~MLX4_FLAG_MSI_X
;
2441 dev
->caps
.num_comp_vectors
= 1;
2442 dev
->caps
.comp_pool
= 0;
2443 pci_disable_msix(pdev
);
2444 err
= mlx4_setup_hca(dev
);
2450 mlx4_init_quotas(dev
);
2452 for (port
= 1; port
<= dev
->caps
.num_ports
; port
++) {
2453 err
= mlx4_init_port_info(dev
, port
);
2458 err
= mlx4_register_device(dev
);
2462 mlx4_request_modules(dev
);
2464 mlx4_sense_init(dev
);
2465 mlx4_start_sense(dev
);
2467 priv
->pci_dev_data
= pci_dev_data
;
2468 pci_set_drvdata(pdev
, dev
);
2473 for (--port
; port
>= 1; --port
)
2474 mlx4_cleanup_port_info(&priv
->port
[port
]);
2476 mlx4_cleanup_counters_table(dev
);
2477 mlx4_cleanup_qp_table(dev
);
2478 mlx4_cleanup_srq_table(dev
);
2479 mlx4_cleanup_cq_table(dev
);
2480 mlx4_cmd_use_polling(dev
);
2481 mlx4_cleanup_eq_table(dev
);
2482 mlx4_cleanup_mcg_table(dev
);
2483 mlx4_cleanup_mr_table(dev
);
2484 mlx4_cleanup_xrcd_table(dev
);
2485 mlx4_cleanup_pd_table(dev
);
2486 mlx4_cleanup_uar_table(dev
);
2489 if (!mlx4_is_slave(dev
))
2490 mlx4_clear_steering(dev
);
2493 mlx4_free_eq_table(dev
);
2496 if (mlx4_is_master(dev
))
2497 mlx4_multi_func_cleanup(dev
);
2500 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2501 pci_disable_msix(pdev
);
2503 mlx4_close_hca(dev
);
2506 if (mlx4_is_slave(dev
))
2507 mlx4_multi_func_cleanup(dev
);
2510 mlx4_cmd_cleanup(dev
);
2513 if (dev
->flags
& MLX4_FLAG_SRIOV
)
2514 pci_disable_sriov(pdev
);
2517 if (!mlx4_is_slave(dev
))
2518 mlx4_free_ownership(dev
);
2523 err_release_regions
:
2524 pci_release_regions(pdev
);
2527 pci_disable_device(pdev
);
2528 pci_set_drvdata(pdev
, NULL
);
2532 static int mlx4_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2534 printk_once(KERN_INFO
"%s", mlx4_version
);
2536 return __mlx4_init_one(pdev
, id
->driver_data
);
2539 static void mlx4_remove_one(struct pci_dev
*pdev
)
2541 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2542 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2546 /* in SRIOV it is not allowed to unload the pf's
2547 * driver while there are alive vf's */
2548 if (mlx4_is_master(dev
)) {
2549 if (mlx4_how_many_lives_vf(dev
))
2550 printk(KERN_ERR
"Removing PF when there are assigned VF's !!!\n");
2552 mlx4_stop_sense(dev
);
2553 mlx4_unregister_device(dev
);
2555 for (p
= 1; p
<= dev
->caps
.num_ports
; p
++) {
2556 mlx4_cleanup_port_info(&priv
->port
[p
]);
2557 mlx4_CLOSE_PORT(dev
, p
);
2560 if (mlx4_is_master(dev
))
2561 mlx4_free_resource_tracker(dev
,
2562 RES_TR_FREE_SLAVES_ONLY
);
2564 mlx4_cleanup_counters_table(dev
);
2565 mlx4_cleanup_qp_table(dev
);
2566 mlx4_cleanup_srq_table(dev
);
2567 mlx4_cleanup_cq_table(dev
);
2568 mlx4_cmd_use_polling(dev
);
2569 mlx4_cleanup_eq_table(dev
);
2570 mlx4_cleanup_mcg_table(dev
);
2571 mlx4_cleanup_mr_table(dev
);
2572 mlx4_cleanup_xrcd_table(dev
);
2573 mlx4_cleanup_pd_table(dev
);
2575 if (mlx4_is_master(dev
))
2576 mlx4_free_resource_tracker(dev
,
2577 RES_TR_FREE_STRUCTS_ONLY
);
2580 mlx4_uar_free(dev
, &priv
->driver_uar
);
2581 mlx4_cleanup_uar_table(dev
);
2582 if (!mlx4_is_slave(dev
))
2583 mlx4_clear_steering(dev
);
2584 mlx4_free_eq_table(dev
);
2585 if (mlx4_is_master(dev
))
2586 mlx4_multi_func_cleanup(dev
);
2587 mlx4_close_hca(dev
);
2588 if (mlx4_is_slave(dev
))
2589 mlx4_multi_func_cleanup(dev
);
2590 mlx4_cmd_cleanup(dev
);
2592 if (dev
->flags
& MLX4_FLAG_MSI_X
)
2593 pci_disable_msix(pdev
);
2594 if (dev
->flags
& MLX4_FLAG_SRIOV
) {
2595 mlx4_warn(dev
, "Disabling SR-IOV\n");
2596 pci_disable_sriov(pdev
);
2599 if (!mlx4_is_slave(dev
))
2600 mlx4_free_ownership(dev
);
2602 kfree(dev
->caps
.qp0_tunnel
);
2603 kfree(dev
->caps
.qp0_proxy
);
2604 kfree(dev
->caps
.qp1_tunnel
);
2605 kfree(dev
->caps
.qp1_proxy
);
2608 pci_release_regions(pdev
);
2609 pci_disable_device(pdev
);
2610 pci_set_drvdata(pdev
, NULL
);
2614 int mlx4_restart_one(struct pci_dev
*pdev
)
2616 struct mlx4_dev
*dev
= pci_get_drvdata(pdev
);
2617 struct mlx4_priv
*priv
= mlx4_priv(dev
);
2620 pci_dev_data
= priv
->pci_dev_data
;
2621 mlx4_remove_one(pdev
);
2622 return __mlx4_init_one(pdev
, pci_dev_data
);
2625 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table
) = {
2626 /* MT25408 "Hermon" SDR */
2627 { PCI_VDEVICE(MELLANOX
, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2628 /* MT25408 "Hermon" DDR */
2629 { PCI_VDEVICE(MELLANOX
, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2630 /* MT25408 "Hermon" QDR */
2631 { PCI_VDEVICE(MELLANOX
, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2632 /* MT25408 "Hermon" DDR PCIe gen2 */
2633 { PCI_VDEVICE(MELLANOX
, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2634 /* MT25408 "Hermon" QDR PCIe gen2 */
2635 { PCI_VDEVICE(MELLANOX
, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2636 /* MT25408 "Hermon" EN 10GigE */
2637 { PCI_VDEVICE(MELLANOX
, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2638 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
2639 { PCI_VDEVICE(MELLANOX
, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2640 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
2641 { PCI_VDEVICE(MELLANOX
, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2642 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
2643 { PCI_VDEVICE(MELLANOX
, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2644 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
2645 { PCI_VDEVICE(MELLANOX
, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2646 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
2647 { PCI_VDEVICE(MELLANOX
, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2648 /* MT26478 ConnectX2 40GigE PCIe gen2 */
2649 { PCI_VDEVICE(MELLANOX
, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT
},
2650 /* MT25400 Family [ConnectX-2 Virtual Function] */
2651 { PCI_VDEVICE(MELLANOX
, 0x1002), MLX4_PCI_DEV_IS_VF
},
2652 /* MT27500 Family [ConnectX-3] */
2653 { PCI_VDEVICE(MELLANOX
, 0x1003), 0 },
2654 /* MT27500 Family [ConnectX-3 Virtual Function] */
2655 { PCI_VDEVICE(MELLANOX
, 0x1004), MLX4_PCI_DEV_IS_VF
},
2656 { PCI_VDEVICE(MELLANOX
, 0x1005), 0 }, /* MT27510 Family */
2657 { PCI_VDEVICE(MELLANOX
, 0x1006), 0 }, /* MT27511 Family */
2658 { PCI_VDEVICE(MELLANOX
, 0x1007), 0 }, /* MT27520 Family */
2659 { PCI_VDEVICE(MELLANOX
, 0x1008), 0 }, /* MT27521 Family */
2660 { PCI_VDEVICE(MELLANOX
, 0x1009), 0 }, /* MT27530 Family */
2661 { PCI_VDEVICE(MELLANOX
, 0x100a), 0 }, /* MT27531 Family */
2662 { PCI_VDEVICE(MELLANOX
, 0x100b), 0 }, /* MT27540 Family */
2663 { PCI_VDEVICE(MELLANOX
, 0x100c), 0 }, /* MT27541 Family */
2664 { PCI_VDEVICE(MELLANOX
, 0x100d), 0 }, /* MT27550 Family */
2665 { PCI_VDEVICE(MELLANOX
, 0x100e), 0 }, /* MT27551 Family */
2666 { PCI_VDEVICE(MELLANOX
, 0x100f), 0 }, /* MT27560 Family */
2667 { PCI_VDEVICE(MELLANOX
, 0x1010), 0 }, /* MT27561 Family */
2671 MODULE_DEVICE_TABLE(pci
, mlx4_pci_table
);
2673 static pci_ers_result_t
mlx4_pci_err_detected(struct pci_dev
*pdev
,
2674 pci_channel_state_t state
)
2676 mlx4_remove_one(pdev
);
2678 return state
== pci_channel_io_perm_failure
?
2679 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
2682 static pci_ers_result_t
mlx4_pci_slot_reset(struct pci_dev
*pdev
)
2684 int ret
= __mlx4_init_one(pdev
, 0);
2686 return ret
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
2689 static const struct pci_error_handlers mlx4_err_handler
= {
2690 .error_detected
= mlx4_pci_err_detected
,
2691 .slot_reset
= mlx4_pci_slot_reset
,
2694 static struct pci_driver mlx4_driver
= {
2696 .id_table
= mlx4_pci_table
,
2697 .probe
= mlx4_init_one
,
2698 .shutdown
= mlx4_remove_one
,
2699 .remove
= mlx4_remove_one
,
2700 .err_handler
= &mlx4_err_handler
,
2703 static int __init
mlx4_verify_params(void)
2705 if ((log_num_mac
< 0) || (log_num_mac
> 7)) {
2706 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac
);
2710 if (log_num_vlan
!= 0)
2711 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2712 MLX4_LOG_NUM_VLANS
);
2714 if ((log_mtts_per_seg
< 1) || (log_mtts_per_seg
> 7)) {
2715 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg
);
2719 /* Check if module param for ports type has legal combination */
2720 if (port_type_array
[0] == false && port_type_array
[1] == true) {
2721 printk(KERN_WARNING
"Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2722 port_type_array
[0] = true;
2725 if (mlx4_log_num_mgm_entry_size
!= -1 &&
2726 (mlx4_log_num_mgm_entry_size
< MLX4_MIN_MGM_LOG_ENTRY_SIZE
||
2727 mlx4_log_num_mgm_entry_size
> MLX4_MAX_MGM_LOG_ENTRY_SIZE
)) {
2728 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2729 "in legal range (-1 or %d..%d)\n",
2730 mlx4_log_num_mgm_entry_size
,
2731 MLX4_MIN_MGM_LOG_ENTRY_SIZE
,
2732 MLX4_MAX_MGM_LOG_ENTRY_SIZE
);
2739 static int __init
mlx4_init(void)
2743 if (mlx4_verify_params())
2748 mlx4_wq
= create_singlethread_workqueue("mlx4");
2752 ret
= pci_register_driver(&mlx4_driver
);
2754 destroy_workqueue(mlx4_wq
);
2755 return ret
< 0 ? ret
: 0;
2758 static void __exit
mlx4_cleanup(void)
2760 pci_unregister_driver(&mlx4_driver
);
2761 destroy_workqueue(mlx4_wq
);
2764 module_init(mlx4_init
);
2765 module_exit(mlx4_cleanup
);