2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/string.h>
35 #include <linux/etherdevice.h>
37 #include <linux/mlx4/cmd.h>
38 #include <linux/export.h>
42 static const u8 zero_gid
[16]; /* automatically initialized to 0 */
44 int mlx4_get_mgm_entry_size(struct mlx4_dev
*dev
)
46 return 1 << dev
->oper_log_mgm_entry_size
;
49 int mlx4_get_qp_per_mgm(struct mlx4_dev
*dev
)
51 return 4 * (mlx4_get_mgm_entry_size(dev
) / 16 - 2);
54 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev
*dev
,
55 struct mlx4_cmd_mailbox
*mailbox
,
62 err
= mlx4_cmd_imm(dev
, mailbox
->dma
, &imm
, size
, 0,
63 MLX4_QP_FLOW_STEERING_ATTACH
, MLX4_CMD_TIME_CLASS_A
,
72 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev
*dev
, u64 regid
)
76 err
= mlx4_cmd(dev
, regid
, 0, 0,
77 MLX4_QP_FLOW_STEERING_DETACH
, MLX4_CMD_TIME_CLASS_A
,
83 static int mlx4_READ_ENTRY(struct mlx4_dev
*dev
, int index
,
84 struct mlx4_cmd_mailbox
*mailbox
)
86 return mlx4_cmd_box(dev
, 0, mailbox
->dma
, index
, 0, MLX4_CMD_READ_MCG
,
87 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
90 static int mlx4_WRITE_ENTRY(struct mlx4_dev
*dev
, int index
,
91 struct mlx4_cmd_mailbox
*mailbox
)
93 return mlx4_cmd(dev
, mailbox
->dma
, index
, 0, MLX4_CMD_WRITE_MCG
,
94 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
97 static int mlx4_WRITE_PROMISC(struct mlx4_dev
*dev
, u8 port
, u8 steer
,
98 struct mlx4_cmd_mailbox
*mailbox
)
102 in_mod
= (u32
) port
<< 16 | steer
<< 1;
103 return mlx4_cmd(dev
, mailbox
->dma
, in_mod
, 0x1,
104 MLX4_CMD_WRITE_MCG
, MLX4_CMD_TIME_CLASS_A
,
108 static int mlx4_GID_HASH(struct mlx4_dev
*dev
, struct mlx4_cmd_mailbox
*mailbox
,
109 u16
*hash
, u8 op_mod
)
114 err
= mlx4_cmd_imm(dev
, mailbox
->dma
, &imm
, 0, op_mod
,
115 MLX4_CMD_MGID_HASH
, MLX4_CMD_TIME_CLASS_A
,
124 static struct mlx4_promisc_qp
*get_promisc_qp(struct mlx4_dev
*dev
, u8 port
,
125 enum mlx4_steer_type steer
,
128 struct mlx4_steer
*s_steer
;
129 struct mlx4_promisc_qp
*pqp
;
131 if (port
< 1 || port
> dev
->caps
.num_ports
)
134 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
136 list_for_each_entry(pqp
, &s_steer
->promisc_qps
[steer
], list
) {
145 * Add new entry to steering data structure.
146 * All promisc QPs should be added as well
148 static int new_steering_entry(struct mlx4_dev
*dev
, u8 port
,
149 enum mlx4_steer_type steer
,
150 unsigned int index
, u32 qpn
)
152 struct mlx4_steer
*s_steer
;
153 struct mlx4_cmd_mailbox
*mailbox
;
154 struct mlx4_mgm
*mgm
;
156 struct mlx4_steer_index
*new_entry
;
157 struct mlx4_promisc_qp
*pqp
;
158 struct mlx4_promisc_qp
*dqp
= NULL
;
162 if (port
< 1 || port
> dev
->caps
.num_ports
)
165 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
166 new_entry
= kzalloc(sizeof *new_entry
, GFP_KERNEL
);
170 INIT_LIST_HEAD(&new_entry
->duplicates
);
171 new_entry
->index
= index
;
172 list_add_tail(&new_entry
->list
, &s_steer
->steer_entries
[steer
]);
174 /* If the given qpn is also a promisc qp,
175 * it should be inserted to duplicates list
177 pqp
= get_promisc_qp(dev
, port
, steer
, qpn
);
179 dqp
= kmalloc(sizeof *dqp
, GFP_KERNEL
);
185 list_add_tail(&dqp
->list
, &new_entry
->duplicates
);
188 /* if no promisc qps for this vep, we are done */
189 if (list_empty(&s_steer
->promisc_qps
[steer
]))
192 /* now need to add all the promisc qps to the new
193 * steering entry, as they should also receive the packets
194 * destined to this address */
195 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
196 if (IS_ERR(mailbox
)) {
202 err
= mlx4_READ_ENTRY(dev
, index
, mailbox
);
206 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
207 prot
= be32_to_cpu(mgm
->members_count
) >> 30;
208 list_for_each_entry(pqp
, &s_steer
->promisc_qps
[steer
], list
) {
209 /* don't add already existing qpn */
212 if (members_count
== dev
->caps
.num_qp_per_mgm
) {
219 mgm
->qp
[members_count
++] = cpu_to_be32(pqp
->qpn
& MGM_QPN_MASK
);
221 /* update the qps count and update the entry with all the promisc qps*/
222 mgm
->members_count
= cpu_to_be32(members_count
| (prot
<< 30));
223 err
= mlx4_WRITE_ENTRY(dev
, index
, mailbox
);
226 mlx4_free_cmd_mailbox(dev
, mailbox
);
231 list_del(&dqp
->list
);
234 list_del(&new_entry
->list
);
239 /* update the data structures with existing steering entry */
240 static int existing_steering_entry(struct mlx4_dev
*dev
, u8 port
,
241 enum mlx4_steer_type steer
,
242 unsigned int index
, u32 qpn
)
244 struct mlx4_steer
*s_steer
;
245 struct mlx4_steer_index
*tmp_entry
, *entry
= NULL
;
246 struct mlx4_promisc_qp
*pqp
;
247 struct mlx4_promisc_qp
*dqp
;
249 if (port
< 1 || port
> dev
->caps
.num_ports
)
252 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
254 pqp
= get_promisc_qp(dev
, port
, steer
, qpn
);
256 return 0; /* nothing to do */
258 list_for_each_entry(tmp_entry
, &s_steer
->steer_entries
[steer
], list
) {
259 if (tmp_entry
->index
== index
) {
264 if (unlikely(!entry
)) {
265 mlx4_warn(dev
, "Steering entry at index %x is not registered\n", index
);
269 /* the given qpn is listed as a promisc qpn
270 * we need to add it as a duplicate to this entry
271 * for future references */
272 list_for_each_entry(dqp
, &entry
->duplicates
, list
) {
274 return 0; /* qp is already duplicated */
277 /* add the qp as a duplicate on this index */
278 dqp
= kmalloc(sizeof *dqp
, GFP_KERNEL
);
282 list_add_tail(&dqp
->list
, &entry
->duplicates
);
287 /* Check whether a qpn is a duplicate on steering entry
288 * If so, it should not be removed from mgm */
289 static bool check_duplicate_entry(struct mlx4_dev
*dev
, u8 port
,
290 enum mlx4_steer_type steer
,
291 unsigned int index
, u32 qpn
)
293 struct mlx4_steer
*s_steer
;
294 struct mlx4_steer_index
*tmp_entry
, *entry
= NULL
;
295 struct mlx4_promisc_qp
*dqp
, *tmp_dqp
;
297 if (port
< 1 || port
> dev
->caps
.num_ports
)
300 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
302 /* if qp is not promisc, it cannot be duplicated */
303 if (!get_promisc_qp(dev
, port
, steer
, qpn
))
306 /* The qp is promisc qp so it is a duplicate on this index
307 * Find the index entry, and remove the duplicate */
308 list_for_each_entry(tmp_entry
, &s_steer
->steer_entries
[steer
], list
) {
309 if (tmp_entry
->index
== index
) {
314 if (unlikely(!entry
)) {
315 mlx4_warn(dev
, "Steering entry for index %x is not registered\n", index
);
318 list_for_each_entry_safe(dqp
, tmp_dqp
, &entry
->duplicates
, list
) {
319 if (dqp
->qpn
== qpn
) {
320 list_del(&dqp
->list
);
327 /* Returns true if all the QPs != tqpn contained in this entry
328 * are Promisc QPs. Returns false otherwise.
330 static bool promisc_steering_entry(struct mlx4_dev
*dev
, u8 port
,
331 enum mlx4_steer_type steer
,
332 unsigned int index
, u32 tqpn
,
335 struct mlx4_cmd_mailbox
*mailbox
;
336 struct mlx4_mgm
*mgm
;
341 if (port
< 1 || port
> dev
->caps
.num_ports
)
344 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
349 if (mlx4_READ_ENTRY(dev
, index
, mailbox
))
351 m_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
353 *members_count
= m_count
;
355 for (i
= 0; i
< m_count
; i
++) {
356 u32 qpn
= be32_to_cpu(mgm
->qp
[i
]) & MGM_QPN_MASK
;
357 if (!get_promisc_qp(dev
, port
, steer
, qpn
) && qpn
!= tqpn
) {
358 /* the qp is not promisc, the entry can't be removed */
364 mlx4_free_cmd_mailbox(dev
, mailbox
);
368 /* IF a steering entry contains only promisc QPs, it can be removed. */
369 static bool can_remove_steering_entry(struct mlx4_dev
*dev
, u8 port
,
370 enum mlx4_steer_type steer
,
371 unsigned int index
, u32 tqpn
)
373 struct mlx4_steer
*s_steer
;
374 struct mlx4_steer_index
*entry
= NULL
, *tmp_entry
;
378 if (port
< 1 || port
> dev
->caps
.num_ports
)
381 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
383 if (!promisc_steering_entry(dev
, port
, steer
, index
,
384 tqpn
, &members_count
))
387 /* All the qps currently registered for this entry are promiscuous,
388 * Checking for duplicates */
390 list_for_each_entry_safe(entry
, tmp_entry
, &s_steer
->steer_entries
[steer
], list
) {
391 if (entry
->index
== index
) {
392 if (list_empty(&entry
->duplicates
) ||
393 members_count
== 1) {
394 struct mlx4_promisc_qp
*pqp
, *tmp_pqp
;
395 /* If there is only 1 entry in duplicates then
396 * this is the QP we want to delete, going over
397 * the list and deleting the entry.
399 list_del(&entry
->list
);
400 list_for_each_entry_safe(pqp
, tmp_pqp
,
403 list_del(&pqp
->list
);
408 /* This entry contains duplicates so it shouldn't be removed */
419 static int add_promisc_qp(struct mlx4_dev
*dev
, u8 port
,
420 enum mlx4_steer_type steer
, u32 qpn
)
422 struct mlx4_steer
*s_steer
;
423 struct mlx4_cmd_mailbox
*mailbox
;
424 struct mlx4_mgm
*mgm
;
425 struct mlx4_steer_index
*entry
;
426 struct mlx4_promisc_qp
*pqp
;
427 struct mlx4_promisc_qp
*dqp
;
433 struct mlx4_priv
*priv
= mlx4_priv(dev
);
435 if (port
< 1 || port
> dev
->caps
.num_ports
)
438 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
440 mutex_lock(&priv
->mcg_table
.mutex
);
442 if (get_promisc_qp(dev
, port
, steer
, qpn
)) {
443 err
= 0; /* Noting to do, already exists */
447 pqp
= kmalloc(sizeof *pqp
, GFP_KERNEL
);
454 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
455 if (IS_ERR(mailbox
)) {
461 if (!(mlx4_is_mfunc(dev
) && steer
== MLX4_UC_STEER
)) {
462 /* The promisc QP needs to be added for each one of the steering
463 * entries. If it already exists, needs to be added as
464 * a duplicate for this entry.
466 list_for_each_entry(entry
,
467 &s_steer
->steer_entries
[steer
],
469 err
= mlx4_READ_ENTRY(dev
, entry
->index
, mailbox
);
473 members_count
= be32_to_cpu(mgm
->members_count
) &
475 prot
= be32_to_cpu(mgm
->members_count
) >> 30;
477 for (i
= 0; i
< members_count
; i
++) {
478 if ((be32_to_cpu(mgm
->qp
[i
]) &
479 MGM_QPN_MASK
) == qpn
) {
480 /* Entry already exists.
483 dqp
= kmalloc(sizeof(*dqp
), GFP_KERNEL
);
489 list_add_tail(&dqp
->list
,
495 /* Need to add the qpn to mgm */
497 dev
->caps
.num_qp_per_mgm
) {
502 mgm
->qp
[members_count
++] =
503 cpu_to_be32(qpn
& MGM_QPN_MASK
);
505 cpu_to_be32(members_count
|
507 err
= mlx4_WRITE_ENTRY(dev
, entry
->index
,
515 /* add the new qpn to list of promisc qps */
516 list_add_tail(&pqp
->list
, &s_steer
->promisc_qps
[steer
]);
517 /* now need to add all the promisc qps to default entry */
518 memset(mgm
, 0, sizeof *mgm
);
520 list_for_each_entry(dqp
, &s_steer
->promisc_qps
[steer
], list
) {
521 if (members_count
== dev
->caps
.num_qp_per_mgm
) {
526 mgm
->qp
[members_count
++] = cpu_to_be32(dqp
->qpn
& MGM_QPN_MASK
);
528 mgm
->members_count
= cpu_to_be32(members_count
| MLX4_PROT_ETH
<< 30);
530 err
= mlx4_WRITE_PROMISC(dev
, port
, steer
, mailbox
);
534 mlx4_free_cmd_mailbox(dev
, mailbox
);
535 mutex_unlock(&priv
->mcg_table
.mutex
);
539 list_del(&pqp
->list
);
541 mlx4_free_cmd_mailbox(dev
, mailbox
);
545 mutex_unlock(&priv
->mcg_table
.mutex
);
549 static int remove_promisc_qp(struct mlx4_dev
*dev
, u8 port
,
550 enum mlx4_steer_type steer
, u32 qpn
)
552 struct mlx4_priv
*priv
= mlx4_priv(dev
);
553 struct mlx4_steer
*s_steer
;
554 struct mlx4_cmd_mailbox
*mailbox
;
555 struct mlx4_mgm
*mgm
;
556 struct mlx4_steer_index
*entry
, *tmp_entry
;
557 struct mlx4_promisc_qp
*pqp
;
558 struct mlx4_promisc_qp
*dqp
;
561 bool back_to_list
= false;
565 if (port
< 1 || port
> dev
->caps
.num_ports
)
568 s_steer
= &mlx4_priv(dev
)->steer
[port
- 1];
569 mutex_lock(&priv
->mcg_table
.mutex
);
571 pqp
= get_promisc_qp(dev
, port
, steer
, qpn
);
572 if (unlikely(!pqp
)) {
573 mlx4_warn(dev
, "QP %x is not promiscuous QP\n", qpn
);
579 /*remove from list of promisc qps */
580 list_del(&pqp
->list
);
582 /* set the default entry not to include the removed one */
583 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
584 if (IS_ERR(mailbox
)) {
591 list_for_each_entry(dqp
, &s_steer
->promisc_qps
[steer
], list
)
592 mgm
->qp
[members_count
++] = cpu_to_be32(dqp
->qpn
& MGM_QPN_MASK
);
593 mgm
->members_count
= cpu_to_be32(members_count
| MLX4_PROT_ETH
<< 30);
595 err
= mlx4_WRITE_PROMISC(dev
, port
, steer
, mailbox
);
599 if (!(mlx4_is_mfunc(dev
) && steer
== MLX4_UC_STEER
)) {
600 /* Remove the QP from all the steering entries */
601 list_for_each_entry_safe(entry
, tmp_entry
,
602 &s_steer
->steer_entries
[steer
],
605 list_for_each_entry(dqp
, &entry
->duplicates
, list
) {
606 if (dqp
->qpn
== qpn
) {
612 /* A duplicate, no need to change the MGM,
613 * only update the duplicates list
615 list_del(&dqp
->list
);
620 err
= mlx4_READ_ENTRY(dev
,
626 be32_to_cpu(mgm
->members_count
) &
628 if (!members_count
) {
629 mlx4_warn(dev
, "QP %06x wasn't found in entry %x mcount=0. deleting entry...\n",
631 list_del(&entry
->list
);
636 for (i
= 0; i
< members_count
; ++i
)
637 if ((be32_to_cpu(mgm
->qp
[i
]) &
638 MGM_QPN_MASK
) == qpn
) {
644 mlx4_err(dev
, "QP %06x wasn't found in entry %d\n",
650 /* Copy the last QP in this MGM
653 mgm
->qp
[loc
] = mgm
->qp
[members_count
- 1];
654 mgm
->qp
[members_count
- 1] = 0;
656 cpu_to_be32(--members_count
|
657 (MLX4_PROT_ETH
<< 30));
659 err
= mlx4_WRITE_ENTRY(dev
,
669 mlx4_free_cmd_mailbox(dev
, mailbox
);
672 list_add_tail(&pqp
->list
, &s_steer
->promisc_qps
[steer
]);
676 mutex_unlock(&priv
->mcg_table
.mutex
);
681 * Caller must hold MCG table semaphore. gid and mgm parameters must
682 * be properly aligned for command interface.
684 * Returns 0 unless a firmware command error occurs.
686 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
687 * and *mgm holds MGM entry.
689 * if GID is found in AMGM, *index = index in AMGM, *prev = index of
690 * previous entry in hash chain and *mgm holds AMGM entry.
692 * If no AMGM exists for given gid, *index = -1, *prev = index of last
693 * entry in hash chain and *mgm holds end of hash chain.
695 static int find_entry(struct mlx4_dev
*dev
, u8 port
,
696 u8
*gid
, enum mlx4_protocol prot
,
697 struct mlx4_cmd_mailbox
*mgm_mailbox
,
698 int *prev
, int *index
)
700 struct mlx4_cmd_mailbox
*mailbox
;
701 struct mlx4_mgm
*mgm
= mgm_mailbox
->buf
;
705 u8 op_mod
= (prot
== MLX4_PROT_ETH
) ?
706 !!(dev
->caps
.flags
& MLX4_DEV_CAP_FLAG_VEP_MC_STEER
) : 0;
708 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
713 memcpy(mgid
, gid
, 16);
715 err
= mlx4_GID_HASH(dev
, mailbox
, &hash
, op_mod
);
716 mlx4_free_cmd_mailbox(dev
, mailbox
);
721 mlx4_dbg(dev
, "Hash for %pI6 is %04x\n", gid
, hash
);
727 err
= mlx4_READ_ENTRY(dev
, *index
, mgm_mailbox
);
731 if (!(be32_to_cpu(mgm
->members_count
) & 0xffffff)) {
732 if (*index
!= hash
) {
733 mlx4_err(dev
, "Found zero MGID in AMGM\n");
739 if (!memcmp(mgm
->gid
, gid
, 16) &&
740 be32_to_cpu(mgm
->members_count
) >> 30 == prot
)
744 *index
= be32_to_cpu(mgm
->next_gid_index
) >> 6;
751 static const u8 __promisc_mode
[] = {
752 [MLX4_FS_REGULAR
] = 0x0,
753 [MLX4_FS_ALL_DEFAULT
] = 0x1,
754 [MLX4_FS_MC_DEFAULT
] = 0x3,
755 [MLX4_FS_MIRROR_RX_PORT
] = 0x4,
756 [MLX4_FS_MIRROR_SX_PORT
] = 0x5,
757 [MLX4_FS_UC_SNIFFER
] = 0x6,
758 [MLX4_FS_MC_SNIFFER
] = 0x7,
761 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev
*dev
,
762 enum mlx4_net_trans_promisc_mode flow_type
)
764 if (flow_type
>= MLX4_FS_MODE_NUM
) {
765 mlx4_err(dev
, "Invalid flow type. type = %d\n", flow_type
);
768 return __promisc_mode
[flow_type
];
770 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode
);
772 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule
*ctrl
,
773 struct mlx4_net_trans_rule_hw_ctrl
*hw
)
777 flags
= ctrl
->queue_mode
== MLX4_NET_TRANS_Q_LIFO
? 1 : 0;
778 flags
|= ctrl
->exclusive
? (1 << 2) : 0;
779 flags
|= ctrl
->allow_loopback
? (1 << 3) : 0;
782 hw
->type
= __promisc_mode
[ctrl
->promisc_mode
];
783 hw
->prio
= cpu_to_be16(ctrl
->priority
);
784 hw
->port
= ctrl
->port
;
785 hw
->qpn
= cpu_to_be32(ctrl
->qpn
);
788 const u16 __sw_id_hw
[] = {
789 [MLX4_NET_TRANS_RULE_ID_ETH
] = 0xE001,
790 [MLX4_NET_TRANS_RULE_ID_IB
] = 0xE005,
791 [MLX4_NET_TRANS_RULE_ID_IPV6
] = 0xE003,
792 [MLX4_NET_TRANS_RULE_ID_IPV4
] = 0xE002,
793 [MLX4_NET_TRANS_RULE_ID_TCP
] = 0xE004,
794 [MLX4_NET_TRANS_RULE_ID_UDP
] = 0xE006,
795 [MLX4_NET_TRANS_RULE_ID_VXLAN
] = 0xE008
798 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev
*dev
,
799 enum mlx4_net_trans_rule_id id
)
801 if (id
>= MLX4_NET_TRANS_RULE_NUM
) {
802 mlx4_err(dev
, "Invalid network rule id. id = %d\n", id
);
805 return __sw_id_hw
[id
];
807 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id
);
809 static const int __rule_hw_sz
[] = {
810 [MLX4_NET_TRANS_RULE_ID_ETH
] =
811 sizeof(struct mlx4_net_trans_rule_hw_eth
),
812 [MLX4_NET_TRANS_RULE_ID_IB
] =
813 sizeof(struct mlx4_net_trans_rule_hw_ib
),
814 [MLX4_NET_TRANS_RULE_ID_IPV6
] = 0,
815 [MLX4_NET_TRANS_RULE_ID_IPV4
] =
816 sizeof(struct mlx4_net_trans_rule_hw_ipv4
),
817 [MLX4_NET_TRANS_RULE_ID_TCP
] =
818 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp
),
819 [MLX4_NET_TRANS_RULE_ID_UDP
] =
820 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp
),
821 [MLX4_NET_TRANS_RULE_ID_VXLAN
] =
822 sizeof(struct mlx4_net_trans_rule_hw_vxlan
)
825 int mlx4_hw_rule_sz(struct mlx4_dev
*dev
,
826 enum mlx4_net_trans_rule_id id
)
828 if (id
>= MLX4_NET_TRANS_RULE_NUM
) {
829 mlx4_err(dev
, "Invalid network rule id. id = %d\n", id
);
833 return __rule_hw_sz
[id
];
835 EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz
);
837 static int parse_trans_rule(struct mlx4_dev
*dev
, struct mlx4_spec_list
*spec
,
838 struct _rule_hw
*rule_hw
)
840 if (mlx4_hw_rule_sz(dev
, spec
->id
) < 0)
842 memset(rule_hw
, 0, mlx4_hw_rule_sz(dev
, spec
->id
));
843 rule_hw
->id
= cpu_to_be16(__sw_id_hw
[spec
->id
]);
844 rule_hw
->size
= mlx4_hw_rule_sz(dev
, spec
->id
) >> 2;
847 case MLX4_NET_TRANS_RULE_ID_ETH
:
848 memcpy(rule_hw
->eth
.dst_mac
, spec
->eth
.dst_mac
, ETH_ALEN
);
849 memcpy(rule_hw
->eth
.dst_mac_msk
, spec
->eth
.dst_mac_msk
,
851 memcpy(rule_hw
->eth
.src_mac
, spec
->eth
.src_mac
, ETH_ALEN
);
852 memcpy(rule_hw
->eth
.src_mac_msk
, spec
->eth
.src_mac_msk
,
854 if (spec
->eth
.ether_type_enable
) {
855 rule_hw
->eth
.ether_type_enable
= 1;
856 rule_hw
->eth
.ether_type
= spec
->eth
.ether_type
;
858 rule_hw
->eth
.vlan_tag
= spec
->eth
.vlan_id
;
859 rule_hw
->eth
.vlan_tag_msk
= spec
->eth
.vlan_id_msk
;
862 case MLX4_NET_TRANS_RULE_ID_IB
:
863 rule_hw
->ib
.l3_qpn
= spec
->ib
.l3_qpn
;
864 rule_hw
->ib
.qpn_mask
= spec
->ib
.qpn_msk
;
865 memcpy(&rule_hw
->ib
.dst_gid
, &spec
->ib
.dst_gid
, 16);
866 memcpy(&rule_hw
->ib
.dst_gid_msk
, &spec
->ib
.dst_gid_msk
, 16);
869 case MLX4_NET_TRANS_RULE_ID_IPV6
:
872 case MLX4_NET_TRANS_RULE_ID_IPV4
:
873 rule_hw
->ipv4
.src_ip
= spec
->ipv4
.src_ip
;
874 rule_hw
->ipv4
.src_ip_msk
= spec
->ipv4
.src_ip_msk
;
875 rule_hw
->ipv4
.dst_ip
= spec
->ipv4
.dst_ip
;
876 rule_hw
->ipv4
.dst_ip_msk
= spec
->ipv4
.dst_ip_msk
;
879 case MLX4_NET_TRANS_RULE_ID_TCP
:
880 case MLX4_NET_TRANS_RULE_ID_UDP
:
881 rule_hw
->tcp_udp
.dst_port
= spec
->tcp_udp
.dst_port
;
882 rule_hw
->tcp_udp
.dst_port_msk
= spec
->tcp_udp
.dst_port_msk
;
883 rule_hw
->tcp_udp
.src_port
= spec
->tcp_udp
.src_port
;
884 rule_hw
->tcp_udp
.src_port_msk
= spec
->tcp_udp
.src_port_msk
;
887 case MLX4_NET_TRANS_RULE_ID_VXLAN
:
889 cpu_to_be32(be32_to_cpu(spec
->vxlan
.vni
) << 8);
890 rule_hw
->vxlan
.vni_mask
=
891 cpu_to_be32(be32_to_cpu(spec
->vxlan
.vni_mask
) << 8);
898 return __rule_hw_sz
[spec
->id
];
901 static void mlx4_err_rule(struct mlx4_dev
*dev
, char *str
,
902 struct mlx4_net_trans_rule
*rule
)
905 struct mlx4_spec_list
*cur
;
909 mlx4_err(dev
, "%s", str
);
910 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
911 "port = %d prio = 0x%x qp = 0x%x ",
912 rule
->port
, rule
->priority
, rule
->qpn
);
914 list_for_each_entry(cur
, &rule
->list
, list
) {
916 case MLX4_NET_TRANS_RULE_ID_ETH
:
917 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
918 "dmac = %pM ", &cur
->eth
.dst_mac
);
919 if (cur
->eth
.ether_type
)
920 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
922 be16_to_cpu(cur
->eth
.ether_type
));
923 if (cur
->eth
.vlan_id
)
924 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
926 be16_to_cpu(cur
->eth
.vlan_id
));
929 case MLX4_NET_TRANS_RULE_ID_IPV4
:
930 if (cur
->ipv4
.src_ip
)
931 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
934 if (cur
->ipv4
.dst_ip
)
935 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
940 case MLX4_NET_TRANS_RULE_ID_TCP
:
941 case MLX4_NET_TRANS_RULE_ID_UDP
:
942 if (cur
->tcp_udp
.src_port
)
943 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
945 be16_to_cpu(cur
->tcp_udp
.src_port
));
946 if (cur
->tcp_udp
.dst_port
)
947 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
949 be16_to_cpu(cur
->tcp_udp
.dst_port
));
952 case MLX4_NET_TRANS_RULE_ID_IB
:
953 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
954 "dst-gid = %pI6\n", cur
->ib
.dst_gid
);
955 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
956 "dst-gid-mask = %pI6\n",
957 cur
->ib
.dst_gid_msk
);
960 case MLX4_NET_TRANS_RULE_ID_VXLAN
:
961 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
,
962 "VNID = %d ", be32_to_cpu(cur
->vxlan
.vni
));
964 case MLX4_NET_TRANS_RULE_ID_IPV6
:
971 len
+= snprintf(buf
+ len
, BUF_SIZE
- len
, "\n");
972 mlx4_err(dev
, "%s", buf
);
975 mlx4_err(dev
, "Network rule error message was truncated, print buffer is too small\n");
978 int mlx4_flow_attach(struct mlx4_dev
*dev
,
979 struct mlx4_net_trans_rule
*rule
, u64
*reg_id
)
981 struct mlx4_cmd_mailbox
*mailbox
;
982 struct mlx4_spec_list
*cur
;
986 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
988 return PTR_ERR(mailbox
);
990 trans_rule_ctrl_to_hw(rule
, mailbox
->buf
);
992 size
+= sizeof(struct mlx4_net_trans_rule_hw_ctrl
);
994 list_for_each_entry(cur
, &rule
->list
, list
) {
995 ret
= parse_trans_rule(dev
, cur
, mailbox
->buf
+ size
);
997 mlx4_free_cmd_mailbox(dev
, mailbox
);
1003 ret
= mlx4_QP_FLOW_STEERING_ATTACH(dev
, mailbox
, size
>> 2, reg_id
);
1004 if (ret
== -ENOMEM
) {
1006 "mcg table is full. Fail to register network rule\n",
1009 if (ret
== -ENXIO
) {
1010 if (dev
->caps
.steering_mode
!= MLX4_STEERING_MODE_DEVICE_MANAGED
)
1012 "DMFS is not enabled, "
1013 "failed to register network rule.\n",
1017 "Rule exceeds the dmfs_high_rate_mode limitations, "
1018 "failed to register network rule.\n",
1022 mlx4_err_rule(dev
, "Fail to register network rule.\n", rule
);
1026 mlx4_free_cmd_mailbox(dev
, mailbox
);
1030 EXPORT_SYMBOL_GPL(mlx4_flow_attach
);
1032 int mlx4_flow_detach(struct mlx4_dev
*dev
, u64 reg_id
)
1036 err
= mlx4_QP_FLOW_STEERING_DETACH(dev
, reg_id
);
1038 mlx4_err(dev
, "Fail to detach network rule. registration id = 0x%llx\n",
1042 EXPORT_SYMBOL_GPL(mlx4_flow_detach
);
1044 int mlx4_tunnel_steer_add(struct mlx4_dev
*dev
, unsigned char *addr
,
1045 int port
, int qpn
, u16 prio
, u64
*reg_id
)
1048 struct mlx4_spec_list spec_eth_outer
= { {NULL
} };
1049 struct mlx4_spec_list spec_vxlan
= { {NULL
} };
1050 struct mlx4_spec_list spec_eth_inner
= { {NULL
} };
1052 struct mlx4_net_trans_rule rule
= {
1053 .queue_mode
= MLX4_NET_TRANS_Q_FIFO
,
1055 .allow_loopback
= 1,
1056 .promisc_mode
= MLX4_FS_REGULAR
,
1059 __be64 mac_mask
= cpu_to_be64(MLX4_MAC_MASK
<< 16);
1063 rule
.priority
= prio
;
1064 INIT_LIST_HEAD(&rule
.list
);
1066 spec_eth_outer
.id
= MLX4_NET_TRANS_RULE_ID_ETH
;
1067 memcpy(spec_eth_outer
.eth
.dst_mac
, addr
, ETH_ALEN
);
1068 memcpy(spec_eth_outer
.eth
.dst_mac_msk
, &mac_mask
, ETH_ALEN
);
1070 spec_vxlan
.id
= MLX4_NET_TRANS_RULE_ID_VXLAN
; /* any vxlan header */
1071 spec_eth_inner
.id
= MLX4_NET_TRANS_RULE_ID_ETH
; /* any inner eth header */
1073 list_add_tail(&spec_eth_outer
.list
, &rule
.list
);
1074 list_add_tail(&spec_vxlan
.list
, &rule
.list
);
1075 list_add_tail(&spec_eth_inner
.list
, &rule
.list
);
1077 err
= mlx4_flow_attach(dev
, &rule
, reg_id
);
1080 EXPORT_SYMBOL(mlx4_tunnel_steer_add
);
1082 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev
*dev
, u32 min_range_qpn
,
1088 in_param
= ((u64
) min_range_qpn
) << 32;
1089 in_param
|= ((u64
) max_range_qpn
) & 0xFFFFFFFF;
1091 err
= mlx4_cmd(dev
, in_param
, 0, 0,
1092 MLX4_FLOW_STEERING_IB_UC_QP_RANGE
,
1093 MLX4_CMD_TIME_CLASS_A
, MLX4_CMD_NATIVE
);
1097 EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE
);
1099 int mlx4_qp_attach_common(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1100 int block_mcast_loopback
, enum mlx4_protocol prot
,
1101 enum mlx4_steer_type steer
)
1103 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1104 struct mlx4_cmd_mailbox
*mailbox
;
1105 struct mlx4_mgm
*mgm
;
1114 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1115 if (IS_ERR(mailbox
))
1116 return PTR_ERR(mailbox
);
1119 mutex_lock(&priv
->mcg_table
.mutex
);
1120 err
= find_entry(dev
, port
, gid
, prot
,
1121 mailbox
, &prev
, &index
);
1126 if (!(be32_to_cpu(mgm
->members_count
) & 0xffffff)) {
1128 memcpy(mgm
->gid
, gid
, 16);
1133 index
= mlx4_bitmap_alloc(&priv
->mcg_table
.bitmap
);
1135 mlx4_err(dev
, "No AMGM entries left\n");
1139 index
+= dev
->caps
.num_mgms
;
1142 memset(mgm
, 0, sizeof *mgm
);
1143 memcpy(mgm
->gid
, gid
, 16);
1146 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
1147 if (members_count
== dev
->caps
.num_qp_per_mgm
) {
1148 mlx4_err(dev
, "MGM at index %x is full\n", index
);
1153 for (i
= 0; i
< members_count
; ++i
)
1154 if ((be32_to_cpu(mgm
->qp
[i
]) & MGM_QPN_MASK
) == qp
->qpn
) {
1155 mlx4_dbg(dev
, "QP %06x already a member of MGM\n", qp
->qpn
);
1160 if (block_mcast_loopback
)
1161 mgm
->qp
[members_count
++] = cpu_to_be32((qp
->qpn
& MGM_QPN_MASK
) |
1162 (1U << MGM_BLCK_LB_BIT
));
1164 mgm
->qp
[members_count
++] = cpu_to_be32(qp
->qpn
& MGM_QPN_MASK
);
1166 mgm
->members_count
= cpu_to_be32(members_count
| (u32
) prot
<< 30);
1168 err
= mlx4_WRITE_ENTRY(dev
, index
, mailbox
);
1175 err
= mlx4_READ_ENTRY(dev
, prev
, mailbox
);
1179 mgm
->next_gid_index
= cpu_to_be32(index
<< 6);
1181 err
= mlx4_WRITE_ENTRY(dev
, prev
, mailbox
);
1186 if (prot
== MLX4_PROT_ETH
) {
1187 /* manage the steering entry for promisc mode */
1189 err
= new_steering_entry(dev
, port
, steer
,
1192 err
= existing_steering_entry(dev
, port
, steer
,
1195 if (err
&& link
&& index
!= -1) {
1196 if (index
< dev
->caps
.num_mgms
)
1197 mlx4_warn(dev
, "Got AMGM index %d < %d\n",
1198 index
, dev
->caps
.num_mgms
);
1200 mlx4_bitmap_free(&priv
->mcg_table
.bitmap
,
1201 index
- dev
->caps
.num_mgms
, MLX4_USE_RR
);
1203 mutex_unlock(&priv
->mcg_table
.mutex
);
1205 mlx4_free_cmd_mailbox(dev
, mailbox
);
1209 int mlx4_qp_detach_common(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1210 enum mlx4_protocol prot
, enum mlx4_steer_type steer
)
1212 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1213 struct mlx4_cmd_mailbox
*mailbox
;
1214 struct mlx4_mgm
*mgm
;
1220 bool removed_entry
= false;
1222 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1223 if (IS_ERR(mailbox
))
1224 return PTR_ERR(mailbox
);
1227 mutex_lock(&priv
->mcg_table
.mutex
);
1229 err
= find_entry(dev
, port
, gid
, prot
,
1230 mailbox
, &prev
, &index
);
1235 mlx4_err(dev
, "MGID %pI6 not found\n", gid
);
1240 /* If this QP is also a promisc QP, it shouldn't be removed only if
1241 * at least one none promisc QP is also attached to this MCG
1243 if (prot
== MLX4_PROT_ETH
&&
1244 check_duplicate_entry(dev
, port
, steer
, index
, qp
->qpn
) &&
1245 !promisc_steering_entry(dev
, port
, steer
, index
, qp
->qpn
, NULL
))
1248 members_count
= be32_to_cpu(mgm
->members_count
) & 0xffffff;
1249 for (i
= 0; i
< members_count
; ++i
)
1250 if ((be32_to_cpu(mgm
->qp
[i
]) & MGM_QPN_MASK
) == qp
->qpn
) {
1256 mlx4_err(dev
, "QP %06x not found in MGM\n", qp
->qpn
);
1261 /* copy the last QP in this MGM over removed QP */
1262 mgm
->qp
[loc
] = mgm
->qp
[members_count
- 1];
1263 mgm
->qp
[members_count
- 1] = 0;
1264 mgm
->members_count
= cpu_to_be32(--members_count
| (u32
) prot
<< 30);
1266 if (prot
== MLX4_PROT_ETH
)
1267 removed_entry
= can_remove_steering_entry(dev
, port
, steer
,
1269 if (members_count
&& (prot
!= MLX4_PROT_ETH
|| !removed_entry
)) {
1270 err
= mlx4_WRITE_ENTRY(dev
, index
, mailbox
);
1274 /* We are going to delete the entry, members count should be 0 */
1275 mgm
->members_count
= cpu_to_be32((u32
) prot
<< 30);
1278 /* Remove entry from MGM */
1279 int amgm_index
= be32_to_cpu(mgm
->next_gid_index
) >> 6;
1281 err
= mlx4_READ_ENTRY(dev
, amgm_index
, mailbox
);
1285 memset(mgm
->gid
, 0, 16);
1287 err
= mlx4_WRITE_ENTRY(dev
, index
, mailbox
);
1292 if (amgm_index
< dev
->caps
.num_mgms
)
1293 mlx4_warn(dev
, "MGM entry %d had AMGM index %d < %d\n",
1294 index
, amgm_index
, dev
->caps
.num_mgms
);
1296 mlx4_bitmap_free(&priv
->mcg_table
.bitmap
,
1297 amgm_index
- dev
->caps
.num_mgms
, MLX4_USE_RR
);
1300 /* Remove entry from AMGM */
1301 int cur_next_index
= be32_to_cpu(mgm
->next_gid_index
) >> 6;
1302 err
= mlx4_READ_ENTRY(dev
, prev
, mailbox
);
1306 mgm
->next_gid_index
= cpu_to_be32(cur_next_index
<< 6);
1308 err
= mlx4_WRITE_ENTRY(dev
, prev
, mailbox
);
1312 if (index
< dev
->caps
.num_mgms
)
1313 mlx4_warn(dev
, "entry %d had next AMGM index %d < %d\n",
1314 prev
, index
, dev
->caps
.num_mgms
);
1316 mlx4_bitmap_free(&priv
->mcg_table
.bitmap
,
1317 index
- dev
->caps
.num_mgms
, MLX4_USE_RR
);
1321 mutex_unlock(&priv
->mcg_table
.mutex
);
1323 mlx4_free_cmd_mailbox(dev
, mailbox
);
1324 if (err
&& dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)
1325 /* In case device is under an error, return success as a closing command */
1330 static int mlx4_QP_ATTACH(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
,
1331 u8 gid
[16], u8 attach
, u8 block_loopback
,
1332 enum mlx4_protocol prot
)
1334 struct mlx4_cmd_mailbox
*mailbox
;
1338 if (!mlx4_is_mfunc(dev
))
1341 mailbox
= mlx4_alloc_cmd_mailbox(dev
);
1342 if (IS_ERR(mailbox
))
1343 return PTR_ERR(mailbox
);
1345 memcpy(mailbox
->buf
, gid
, 16);
1347 qpn
|= (prot
<< 28);
1348 if (attach
&& block_loopback
)
1351 err
= mlx4_cmd(dev
, mailbox
->dma
, qpn
, attach
,
1352 MLX4_CMD_QP_ATTACH
, MLX4_CMD_TIME_CLASS_A
,
1355 mlx4_free_cmd_mailbox(dev
, mailbox
);
1356 if (err
&& !attach
&&
1357 dev
->persist
->state
& MLX4_DEVICE_STATE_INTERNAL_ERROR
)
1362 int mlx4_trans_to_dmfs_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
,
1363 u8 gid
[16], u8 port
,
1364 int block_mcast_loopback
,
1365 enum mlx4_protocol prot
, u64
*reg_id
)
1367 struct mlx4_spec_list spec
= { {NULL
} };
1368 __be64 mac_mask
= cpu_to_be64(MLX4_MAC_MASK
<< 16);
1370 struct mlx4_net_trans_rule rule
= {
1371 .queue_mode
= MLX4_NET_TRANS_Q_FIFO
,
1373 .promisc_mode
= MLX4_FS_REGULAR
,
1374 .priority
= MLX4_DOMAIN_NIC
,
1377 rule
.allow_loopback
= !block_mcast_loopback
;
1380 INIT_LIST_HEAD(&rule
.list
);
1384 spec
.id
= MLX4_NET_TRANS_RULE_ID_ETH
;
1385 memcpy(spec
.eth
.dst_mac
, &gid
[10], ETH_ALEN
);
1386 memcpy(spec
.eth
.dst_mac_msk
, &mac_mask
, ETH_ALEN
);
1389 case MLX4_PROT_IB_IPV6
:
1390 spec
.id
= MLX4_NET_TRANS_RULE_ID_IB
;
1391 memcpy(spec
.ib
.dst_gid
, gid
, 16);
1392 memset(&spec
.ib
.dst_gid_msk
, 0xff, 16);
1397 list_add_tail(&spec
.list
, &rule
.list
);
1399 return mlx4_flow_attach(dev
, &rule
, reg_id
);
1402 int mlx4_multicast_attach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1403 u8 port
, int block_mcast_loopback
,
1404 enum mlx4_protocol prot
, u64
*reg_id
)
1406 switch (dev
->caps
.steering_mode
) {
1407 case MLX4_STEERING_MODE_A0
:
1408 if (prot
== MLX4_PROT_ETH
)
1411 case MLX4_STEERING_MODE_B0
:
1412 if (prot
== MLX4_PROT_ETH
)
1413 gid
[7] |= (MLX4_MC_STEER
<< 1);
1415 if (mlx4_is_mfunc(dev
))
1416 return mlx4_QP_ATTACH(dev
, qp
, gid
, 1,
1417 block_mcast_loopback
, prot
);
1418 return mlx4_qp_attach_common(dev
, qp
, gid
,
1419 block_mcast_loopback
, prot
,
1422 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
1423 return mlx4_trans_to_dmfs_attach(dev
, qp
, gid
, port
,
1424 block_mcast_loopback
,
1430 EXPORT_SYMBOL_GPL(mlx4_multicast_attach
);
1432 int mlx4_multicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
, u8 gid
[16],
1433 enum mlx4_protocol prot
, u64 reg_id
)
1435 switch (dev
->caps
.steering_mode
) {
1436 case MLX4_STEERING_MODE_A0
:
1437 if (prot
== MLX4_PROT_ETH
)
1440 case MLX4_STEERING_MODE_B0
:
1441 if (prot
== MLX4_PROT_ETH
)
1442 gid
[7] |= (MLX4_MC_STEER
<< 1);
1444 if (mlx4_is_mfunc(dev
))
1445 return mlx4_QP_ATTACH(dev
, qp
, gid
, 0, 0, prot
);
1447 return mlx4_qp_detach_common(dev
, qp
, gid
, prot
,
1450 case MLX4_STEERING_MODE_DEVICE_MANAGED
:
1451 return mlx4_flow_detach(dev
, reg_id
);
1457 EXPORT_SYMBOL_GPL(mlx4_multicast_detach
);
1459 int mlx4_flow_steer_promisc_add(struct mlx4_dev
*dev
, u8 port
,
1460 u32 qpn
, enum mlx4_net_trans_promisc_mode mode
)
1462 struct mlx4_net_trans_rule rule
;
1466 case MLX4_FS_ALL_DEFAULT
:
1467 regid_p
= &dev
->regid_promisc_array
[port
];
1469 case MLX4_FS_MC_DEFAULT
:
1470 regid_p
= &dev
->regid_allmulti_array
[port
];
1479 rule
.promisc_mode
= mode
;
1482 INIT_LIST_HEAD(&rule
.list
);
1483 mlx4_err(dev
, "going promisc on %x\n", port
);
1485 return mlx4_flow_attach(dev
, &rule
, regid_p
);
1487 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add
);
1489 int mlx4_flow_steer_promisc_remove(struct mlx4_dev
*dev
, u8 port
,
1490 enum mlx4_net_trans_promisc_mode mode
)
1496 case MLX4_FS_ALL_DEFAULT
:
1497 regid_p
= &dev
->regid_promisc_array
[port
];
1499 case MLX4_FS_MC_DEFAULT
:
1500 regid_p
= &dev
->regid_allmulti_array
[port
];
1509 ret
= mlx4_flow_detach(dev
, *regid_p
);
1515 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove
);
1517 int mlx4_unicast_attach(struct mlx4_dev
*dev
,
1518 struct mlx4_qp
*qp
, u8 gid
[16],
1519 int block_mcast_loopback
, enum mlx4_protocol prot
)
1521 if (prot
== MLX4_PROT_ETH
)
1522 gid
[7] |= (MLX4_UC_STEER
<< 1);
1524 if (mlx4_is_mfunc(dev
))
1525 return mlx4_QP_ATTACH(dev
, qp
, gid
, 1,
1526 block_mcast_loopback
, prot
);
1528 return mlx4_qp_attach_common(dev
, qp
, gid
, block_mcast_loopback
,
1529 prot
, MLX4_UC_STEER
);
1531 EXPORT_SYMBOL_GPL(mlx4_unicast_attach
);
1533 int mlx4_unicast_detach(struct mlx4_dev
*dev
, struct mlx4_qp
*qp
,
1534 u8 gid
[16], enum mlx4_protocol prot
)
1536 if (prot
== MLX4_PROT_ETH
)
1537 gid
[7] |= (MLX4_UC_STEER
<< 1);
1539 if (mlx4_is_mfunc(dev
))
1540 return mlx4_QP_ATTACH(dev
, qp
, gid
, 0, 0, prot
);
1542 return mlx4_qp_detach_common(dev
, qp
, gid
, prot
, MLX4_UC_STEER
);
1544 EXPORT_SYMBOL_GPL(mlx4_unicast_detach
);
1546 int mlx4_PROMISC_wrapper(struct mlx4_dev
*dev
, int slave
,
1547 struct mlx4_vhcr
*vhcr
,
1548 struct mlx4_cmd_mailbox
*inbox
,
1549 struct mlx4_cmd_mailbox
*outbox
,
1550 struct mlx4_cmd_info
*cmd
)
1552 u32 qpn
= (u32
) vhcr
->in_param
& 0xffffffff;
1553 int port
= mlx4_slave_convert_port(dev
, slave
, vhcr
->in_param
>> 62);
1554 enum mlx4_steer_type steer
= vhcr
->in_modifier
;
1559 /* Promiscuous unicast is not allowed in mfunc */
1560 if (mlx4_is_mfunc(dev
) && steer
== MLX4_UC_STEER
)
1563 if (vhcr
->op_modifier
)
1564 return add_promisc_qp(dev
, port
, steer
, qpn
);
1566 return remove_promisc_qp(dev
, port
, steer
, qpn
);
1569 static int mlx4_PROMISC(struct mlx4_dev
*dev
, u32 qpn
,
1570 enum mlx4_steer_type steer
, u8 add
, u8 port
)
1572 return mlx4_cmd(dev
, (u64
) qpn
| (u64
) port
<< 62, (u32
) steer
, add
,
1573 MLX4_CMD_PROMISC
, MLX4_CMD_TIME_CLASS_A
,
1577 int mlx4_multicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
)
1579 if (mlx4_is_mfunc(dev
))
1580 return mlx4_PROMISC(dev
, qpn
, MLX4_MC_STEER
, 1, port
);
1582 return add_promisc_qp(dev
, port
, MLX4_MC_STEER
, qpn
);
1584 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add
);
1586 int mlx4_multicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
)
1588 if (mlx4_is_mfunc(dev
))
1589 return mlx4_PROMISC(dev
, qpn
, MLX4_MC_STEER
, 0, port
);
1591 return remove_promisc_qp(dev
, port
, MLX4_MC_STEER
, qpn
);
1593 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove
);
1595 int mlx4_unicast_promisc_add(struct mlx4_dev
*dev
, u32 qpn
, u8 port
)
1597 if (mlx4_is_mfunc(dev
))
1598 return mlx4_PROMISC(dev
, qpn
, MLX4_UC_STEER
, 1, port
);
1600 return add_promisc_qp(dev
, port
, MLX4_UC_STEER
, qpn
);
1602 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add
);
1604 int mlx4_unicast_promisc_remove(struct mlx4_dev
*dev
, u32 qpn
, u8 port
)
1606 if (mlx4_is_mfunc(dev
))
1607 return mlx4_PROMISC(dev
, qpn
, MLX4_UC_STEER
, 0, port
);
1609 return remove_promisc_qp(dev
, port
, MLX4_UC_STEER
, qpn
);
1611 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove
);
1613 int mlx4_init_mcg_table(struct mlx4_dev
*dev
)
1615 struct mlx4_priv
*priv
= mlx4_priv(dev
);
1618 /* No need for mcg_table when fw managed the mcg table*/
1619 if (dev
->caps
.steering_mode
==
1620 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1622 err
= mlx4_bitmap_init(&priv
->mcg_table
.bitmap
, dev
->caps
.num_amgms
,
1623 dev
->caps
.num_amgms
- 1, 0, 0);
1627 mutex_init(&priv
->mcg_table
.mutex
);
1632 void mlx4_cleanup_mcg_table(struct mlx4_dev
*dev
)
1634 if (dev
->caps
.steering_mode
!=
1635 MLX4_STEERING_MODE_DEVICE_MANAGED
)
1636 mlx4_bitmap_cleanup(&mlx4_priv(dev
)->mcg_table
.bitmap
);