2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
45 #include "mlx5_core.h"
59 LONG_LIST_SIZE
= (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE
) * 8 + 16 +
60 MLX5_CMD_DATA_BLOCK_SIZE
,
61 MED_LIST_SIZE
= 16 + MLX5_CMD_DATA_BLOCK_SIZE
,
65 MLX5_CMD_DELIVERY_STAT_OK
= 0x0,
66 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR
= 0x1,
67 MLX5_CMD_DELIVERY_STAT_TOK_ERR
= 0x2,
68 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR
= 0x3,
69 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR
= 0x4,
70 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR
= 0x5,
71 MLX5_CMD_DELIVERY_STAT_FW_ERR
= 0x6,
72 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR
= 0x7,
73 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR
= 0x8,
74 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR
= 0x9,
75 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR
= 0x10,
78 static struct mlx5_cmd_work_ent
*alloc_cmd(struct mlx5_cmd
*cmd
,
79 struct mlx5_cmd_msg
*in
,
80 struct mlx5_cmd_msg
*out
,
81 void *uout
, int uout_size
,
83 void *context
, int page_queue
)
85 gfp_t alloc_flags
= cbk
? GFP_ATOMIC
: GFP_KERNEL
;
86 struct mlx5_cmd_work_ent
*ent
;
88 ent
= kzalloc(sizeof(*ent
), alloc_flags
);
90 return ERR_PTR(-ENOMEM
);
95 ent
->uout_size
= uout_size
;
97 ent
->context
= context
;
99 ent
->page_queue
= page_queue
;
104 static u8
alloc_token(struct mlx5_cmd
*cmd
)
108 spin_lock(&cmd
->token_lock
);
113 spin_unlock(&cmd
->token_lock
);
118 static int alloc_ent(struct mlx5_cmd
*cmd
)
123 spin_lock_irqsave(&cmd
->alloc_lock
, flags
);
124 ret
= find_first_bit(&cmd
->bitmask
, cmd
->max_reg_cmds
);
125 if (ret
< cmd
->max_reg_cmds
)
126 clear_bit(ret
, &cmd
->bitmask
);
127 spin_unlock_irqrestore(&cmd
->alloc_lock
, flags
);
129 return ret
< cmd
->max_reg_cmds
? ret
: -ENOMEM
;
132 static void free_ent(struct mlx5_cmd
*cmd
, int idx
)
136 spin_lock_irqsave(&cmd
->alloc_lock
, flags
);
137 set_bit(idx
, &cmd
->bitmask
);
138 spin_unlock_irqrestore(&cmd
->alloc_lock
, flags
);
141 static struct mlx5_cmd_layout
*get_inst(struct mlx5_cmd
*cmd
, int idx
)
143 return cmd
->cmd_buf
+ (idx
<< cmd
->log_stride
);
146 static u8
xor8_buf(void *buf
, int len
)
152 for (i
= 0; i
< len
; i
++)
158 static int verify_block_sig(struct mlx5_cmd_prot_block
*block
)
160 if (xor8_buf(block
->rsvd0
, sizeof(*block
) - sizeof(block
->data
) - 1) != 0xff)
163 if (xor8_buf(block
, sizeof(*block
)) != 0xff)
169 static void calc_block_sig(struct mlx5_cmd_prot_block
*block
, u8 token
,
172 block
->token
= token
;
174 block
->ctrl_sig
= ~xor8_buf(block
->rsvd0
, sizeof(*block
) -
175 sizeof(block
->data
) - 2);
176 block
->sig
= ~xor8_buf(block
, sizeof(*block
) - 1);
180 static void calc_chain_sig(struct mlx5_cmd_msg
*msg
, u8 token
, int csum
)
182 struct mlx5_cmd_mailbox
*next
= msg
->next
;
185 calc_block_sig(next
->buf
, token
, csum
);
190 static void set_signature(struct mlx5_cmd_work_ent
*ent
, int csum
)
192 ent
->lay
->sig
= ~xor8_buf(ent
->lay
, sizeof(*ent
->lay
));
193 calc_chain_sig(ent
->in
, ent
->token
, csum
);
194 calc_chain_sig(ent
->out
, ent
->token
, csum
);
197 static void poll_timeout(struct mlx5_cmd_work_ent
*ent
)
199 unsigned long poll_end
= jiffies
+ msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC
+ 1000);
203 own
= ent
->lay
->status_own
;
204 if (!(own
& CMD_OWNER_HW
)) {
208 usleep_range(5000, 10000);
209 } while (time_before(jiffies
, poll_end
));
211 ent
->ret
= -ETIMEDOUT
;
214 static void free_cmd(struct mlx5_cmd_work_ent
*ent
)
220 static int verify_signature(struct mlx5_cmd_work_ent
*ent
)
222 struct mlx5_cmd_mailbox
*next
= ent
->out
->next
;
226 sig
= xor8_buf(ent
->lay
, sizeof(*ent
->lay
));
231 err
= verify_block_sig(next
->buf
);
241 static void dump_buf(void *buf
, int size
, int data_only
, int offset
)
246 for (i
= 0; i
< size
; i
+= 16) {
247 pr_debug("%03x: %08x %08x %08x %08x\n", offset
, be32_to_cpu(p
[0]),
248 be32_to_cpu(p
[1]), be32_to_cpu(p
[2]),
258 MLX5_DRIVER_STATUS_ABORTED
= 0xfe,
259 MLX5_DRIVER_SYND
= 0xbadd00de,
262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev
*dev
, u16 op
,
263 u32
*synd
, u8
*status
)
269 case MLX5_CMD_OP_TEARDOWN_HCA
:
270 case MLX5_CMD_OP_DISABLE_HCA
:
271 case MLX5_CMD_OP_MANAGE_PAGES
:
272 case MLX5_CMD_OP_DESTROY_MKEY
:
273 case MLX5_CMD_OP_DESTROY_EQ
:
274 case MLX5_CMD_OP_DESTROY_CQ
:
275 case MLX5_CMD_OP_DESTROY_QP
:
276 case MLX5_CMD_OP_DESTROY_PSV
:
277 case MLX5_CMD_OP_DESTROY_SRQ
:
278 case MLX5_CMD_OP_DESTROY_XRC_SRQ
:
279 case MLX5_CMD_OP_DESTROY_DCT
:
280 case MLX5_CMD_OP_DEALLOC_Q_COUNTER
:
281 case MLX5_CMD_OP_DEALLOC_PD
:
282 case MLX5_CMD_OP_DEALLOC_UAR
:
283 case MLX5_CMD_OP_DETTACH_FROM_MCG
:
284 case MLX5_CMD_OP_DEALLOC_XRCD
:
285 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN
:
286 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT
:
287 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY
:
288 case MLX5_CMD_OP_DESTROY_TIR
:
289 case MLX5_CMD_OP_DESTROY_SQ
:
290 case MLX5_CMD_OP_DESTROY_RQ
:
291 case MLX5_CMD_OP_DESTROY_RMP
:
292 case MLX5_CMD_OP_DESTROY_TIS
:
293 case MLX5_CMD_OP_DESTROY_RQT
:
294 case MLX5_CMD_OP_DESTROY_FLOW_TABLE
:
295 case MLX5_CMD_OP_DESTROY_FLOW_GROUP
:
296 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY
:
297 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER
:
298 return MLX5_CMD_STAT_OK
;
300 case MLX5_CMD_OP_QUERY_HCA_CAP
:
301 case MLX5_CMD_OP_QUERY_ADAPTER
:
302 case MLX5_CMD_OP_INIT_HCA
:
303 case MLX5_CMD_OP_ENABLE_HCA
:
304 case MLX5_CMD_OP_QUERY_PAGES
:
305 case MLX5_CMD_OP_SET_HCA_CAP
:
306 case MLX5_CMD_OP_QUERY_ISSI
:
307 case MLX5_CMD_OP_SET_ISSI
:
308 case MLX5_CMD_OP_CREATE_MKEY
:
309 case MLX5_CMD_OP_QUERY_MKEY
:
310 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS
:
311 case MLX5_CMD_OP_PAGE_FAULT_RESUME
:
312 case MLX5_CMD_OP_CREATE_EQ
:
313 case MLX5_CMD_OP_QUERY_EQ
:
314 case MLX5_CMD_OP_GEN_EQE
:
315 case MLX5_CMD_OP_CREATE_CQ
:
316 case MLX5_CMD_OP_QUERY_CQ
:
317 case MLX5_CMD_OP_MODIFY_CQ
:
318 case MLX5_CMD_OP_CREATE_QP
:
319 case MLX5_CMD_OP_RST2INIT_QP
:
320 case MLX5_CMD_OP_INIT2RTR_QP
:
321 case MLX5_CMD_OP_RTR2RTS_QP
:
322 case MLX5_CMD_OP_RTS2RTS_QP
:
323 case MLX5_CMD_OP_SQERR2RTS_QP
:
324 case MLX5_CMD_OP_2ERR_QP
:
325 case MLX5_CMD_OP_2RST_QP
:
326 case MLX5_CMD_OP_QUERY_QP
:
327 case MLX5_CMD_OP_SQD_RTS_QP
:
328 case MLX5_CMD_OP_INIT2INIT_QP
:
329 case MLX5_CMD_OP_CREATE_PSV
:
330 case MLX5_CMD_OP_CREATE_SRQ
:
331 case MLX5_CMD_OP_QUERY_SRQ
:
332 case MLX5_CMD_OP_ARM_RQ
:
333 case MLX5_CMD_OP_CREATE_XRC_SRQ
:
334 case MLX5_CMD_OP_QUERY_XRC_SRQ
:
335 case MLX5_CMD_OP_ARM_XRC_SRQ
:
336 case MLX5_CMD_OP_CREATE_DCT
:
337 case MLX5_CMD_OP_DRAIN_DCT
:
338 case MLX5_CMD_OP_QUERY_DCT
:
339 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION
:
340 case MLX5_CMD_OP_QUERY_VPORT_STATE
:
341 case MLX5_CMD_OP_MODIFY_VPORT_STATE
:
342 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT
:
343 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT
:
344 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT
:
345 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT
:
346 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS
:
347 case MLX5_CMD_OP_SET_ROCE_ADDRESS
:
348 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT
:
349 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT
:
350 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID
:
351 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY
:
352 case MLX5_CMD_OP_QUERY_VPORT_COUNTER
:
353 case MLX5_CMD_OP_ALLOC_Q_COUNTER
:
354 case MLX5_CMD_OP_QUERY_Q_COUNTER
:
355 case MLX5_CMD_OP_ALLOC_PD
:
356 case MLX5_CMD_OP_ALLOC_UAR
:
357 case MLX5_CMD_OP_CONFIG_INT_MODERATION
:
358 case MLX5_CMD_OP_ACCESS_REG
:
359 case MLX5_CMD_OP_ATTACH_TO_MCG
:
360 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG
:
361 case MLX5_CMD_OP_MAD_IFC
:
362 case MLX5_CMD_OP_QUERY_MAD_DEMUX
:
363 case MLX5_CMD_OP_SET_MAD_DEMUX
:
364 case MLX5_CMD_OP_NOP
:
365 case MLX5_CMD_OP_ALLOC_XRCD
:
366 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN
:
367 case MLX5_CMD_OP_QUERY_CONG_STATUS
:
368 case MLX5_CMD_OP_MODIFY_CONG_STATUS
:
369 case MLX5_CMD_OP_QUERY_CONG_PARAMS
:
370 case MLX5_CMD_OP_MODIFY_CONG_PARAMS
:
371 case MLX5_CMD_OP_QUERY_CONG_STATISTICS
:
372 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT
:
373 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY
:
374 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY
:
375 case MLX5_CMD_OP_CREATE_TIR
:
376 case MLX5_CMD_OP_MODIFY_TIR
:
377 case MLX5_CMD_OP_QUERY_TIR
:
378 case MLX5_CMD_OP_CREATE_SQ
:
379 case MLX5_CMD_OP_MODIFY_SQ
:
380 case MLX5_CMD_OP_QUERY_SQ
:
381 case MLX5_CMD_OP_CREATE_RQ
:
382 case MLX5_CMD_OP_MODIFY_RQ
:
383 case MLX5_CMD_OP_QUERY_RQ
:
384 case MLX5_CMD_OP_CREATE_RMP
:
385 case MLX5_CMD_OP_MODIFY_RMP
:
386 case MLX5_CMD_OP_QUERY_RMP
:
387 case MLX5_CMD_OP_CREATE_TIS
:
388 case MLX5_CMD_OP_MODIFY_TIS
:
389 case MLX5_CMD_OP_QUERY_TIS
:
390 case MLX5_CMD_OP_CREATE_RQT
:
391 case MLX5_CMD_OP_MODIFY_RQT
:
392 case MLX5_CMD_OP_QUERY_RQT
:
393 case MLX5_CMD_OP_CREATE_FLOW_TABLE
:
394 case MLX5_CMD_OP_QUERY_FLOW_TABLE
:
395 case MLX5_CMD_OP_CREATE_FLOW_GROUP
:
396 case MLX5_CMD_OP_QUERY_FLOW_GROUP
:
397 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY
:
398 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY
:
399 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER
:
400 case MLX5_CMD_OP_QUERY_FLOW_COUNTER
:
401 *status
= MLX5_DRIVER_STATUS_ABORTED
;
402 *synd
= MLX5_DRIVER_SYND
;
405 mlx5_core_err(dev
, "Unknown FW command (%d)\n", op
);
410 const char *mlx5_command_str(int command
)
412 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
415 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP
);
416 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER
);
417 MLX5_COMMAND_STR_CASE(INIT_HCA
);
418 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA
);
419 MLX5_COMMAND_STR_CASE(ENABLE_HCA
);
420 MLX5_COMMAND_STR_CASE(DISABLE_HCA
);
421 MLX5_COMMAND_STR_CASE(QUERY_PAGES
);
422 MLX5_COMMAND_STR_CASE(MANAGE_PAGES
);
423 MLX5_COMMAND_STR_CASE(SET_HCA_CAP
);
424 MLX5_COMMAND_STR_CASE(QUERY_ISSI
);
425 MLX5_COMMAND_STR_CASE(SET_ISSI
);
426 MLX5_COMMAND_STR_CASE(CREATE_MKEY
);
427 MLX5_COMMAND_STR_CASE(QUERY_MKEY
);
428 MLX5_COMMAND_STR_CASE(DESTROY_MKEY
);
429 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS
);
430 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME
);
431 MLX5_COMMAND_STR_CASE(CREATE_EQ
);
432 MLX5_COMMAND_STR_CASE(DESTROY_EQ
);
433 MLX5_COMMAND_STR_CASE(QUERY_EQ
);
434 MLX5_COMMAND_STR_CASE(GEN_EQE
);
435 MLX5_COMMAND_STR_CASE(CREATE_CQ
);
436 MLX5_COMMAND_STR_CASE(DESTROY_CQ
);
437 MLX5_COMMAND_STR_CASE(QUERY_CQ
);
438 MLX5_COMMAND_STR_CASE(MODIFY_CQ
);
439 MLX5_COMMAND_STR_CASE(CREATE_QP
);
440 MLX5_COMMAND_STR_CASE(DESTROY_QP
);
441 MLX5_COMMAND_STR_CASE(RST2INIT_QP
);
442 MLX5_COMMAND_STR_CASE(INIT2RTR_QP
);
443 MLX5_COMMAND_STR_CASE(RTR2RTS_QP
);
444 MLX5_COMMAND_STR_CASE(RTS2RTS_QP
);
445 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP
);
446 MLX5_COMMAND_STR_CASE(2ERR_QP
);
447 MLX5_COMMAND_STR_CASE(2RST_QP
);
448 MLX5_COMMAND_STR_CASE(QUERY_QP
);
449 MLX5_COMMAND_STR_CASE(SQD_RTS_QP
);
450 MLX5_COMMAND_STR_CASE(INIT2INIT_QP
);
451 MLX5_COMMAND_STR_CASE(CREATE_PSV
);
452 MLX5_COMMAND_STR_CASE(DESTROY_PSV
);
453 MLX5_COMMAND_STR_CASE(CREATE_SRQ
);
454 MLX5_COMMAND_STR_CASE(DESTROY_SRQ
);
455 MLX5_COMMAND_STR_CASE(QUERY_SRQ
);
456 MLX5_COMMAND_STR_CASE(ARM_RQ
);
457 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ
);
458 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ
);
459 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ
);
460 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ
);
461 MLX5_COMMAND_STR_CASE(CREATE_DCT
);
462 MLX5_COMMAND_STR_CASE(DESTROY_DCT
);
463 MLX5_COMMAND_STR_CASE(DRAIN_DCT
);
464 MLX5_COMMAND_STR_CASE(QUERY_DCT
);
465 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION
);
466 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE
);
467 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE
);
468 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT
);
469 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT
);
470 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT
);
471 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT
);
472 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS
);
473 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS
);
474 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT
);
475 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT
);
476 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID
);
477 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY
);
478 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER
);
479 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER
);
480 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER
);
481 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER
);
482 MLX5_COMMAND_STR_CASE(ALLOC_PD
);
483 MLX5_COMMAND_STR_CASE(DEALLOC_PD
);
484 MLX5_COMMAND_STR_CASE(ALLOC_UAR
);
485 MLX5_COMMAND_STR_CASE(DEALLOC_UAR
);
486 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION
);
487 MLX5_COMMAND_STR_CASE(ACCESS_REG
);
488 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG
);
489 MLX5_COMMAND_STR_CASE(DETTACH_FROM_MCG
);
490 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG
);
491 MLX5_COMMAND_STR_CASE(MAD_IFC
);
492 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX
);
493 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX
);
494 MLX5_COMMAND_STR_CASE(NOP
);
495 MLX5_COMMAND_STR_CASE(ALLOC_XRCD
);
496 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD
);
497 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN
);
498 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN
);
499 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS
);
500 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS
);
501 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS
);
502 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS
);
503 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS
);
504 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT
);
505 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT
);
506 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY
);
507 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY
);
508 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY
);
509 MLX5_COMMAND_STR_CASE(SET_WOL_ROL
);
510 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL
);
511 MLX5_COMMAND_STR_CASE(CREATE_TIR
);
512 MLX5_COMMAND_STR_CASE(MODIFY_TIR
);
513 MLX5_COMMAND_STR_CASE(DESTROY_TIR
);
514 MLX5_COMMAND_STR_CASE(QUERY_TIR
);
515 MLX5_COMMAND_STR_CASE(CREATE_SQ
);
516 MLX5_COMMAND_STR_CASE(MODIFY_SQ
);
517 MLX5_COMMAND_STR_CASE(DESTROY_SQ
);
518 MLX5_COMMAND_STR_CASE(QUERY_SQ
);
519 MLX5_COMMAND_STR_CASE(CREATE_RQ
);
520 MLX5_COMMAND_STR_CASE(MODIFY_RQ
);
521 MLX5_COMMAND_STR_CASE(DESTROY_RQ
);
522 MLX5_COMMAND_STR_CASE(QUERY_RQ
);
523 MLX5_COMMAND_STR_CASE(CREATE_RMP
);
524 MLX5_COMMAND_STR_CASE(MODIFY_RMP
);
525 MLX5_COMMAND_STR_CASE(DESTROY_RMP
);
526 MLX5_COMMAND_STR_CASE(QUERY_RMP
);
527 MLX5_COMMAND_STR_CASE(CREATE_TIS
);
528 MLX5_COMMAND_STR_CASE(MODIFY_TIS
);
529 MLX5_COMMAND_STR_CASE(DESTROY_TIS
);
530 MLX5_COMMAND_STR_CASE(QUERY_TIS
);
531 MLX5_COMMAND_STR_CASE(CREATE_RQT
);
532 MLX5_COMMAND_STR_CASE(MODIFY_RQT
);
533 MLX5_COMMAND_STR_CASE(DESTROY_RQT
);
534 MLX5_COMMAND_STR_CASE(QUERY_RQT
);
535 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT
);
536 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE
);
537 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE
);
538 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE
);
539 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP
);
540 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP
);
541 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP
);
542 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY
);
543 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY
);
544 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY
);
545 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER
);
546 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER
);
547 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER
);
548 default: return "unknown command opcode";
552 static void dump_command(struct mlx5_core_dev
*dev
,
553 struct mlx5_cmd_work_ent
*ent
, int input
)
555 u16 op
= be16_to_cpu(((struct mlx5_inbox_hdr
*)(ent
->lay
->in
))->opcode
);
556 struct mlx5_cmd_msg
*msg
= input
? ent
->in
: ent
->out
;
557 struct mlx5_cmd_mailbox
*next
= msg
->next
;
562 data_only
= !!(mlx5_core_debug_mask
& (1 << MLX5_CMD_DATA
));
565 mlx5_core_dbg_mask(dev
, 1 << MLX5_CMD_DATA
,
566 "dump command data %s(0x%x) %s\n",
567 mlx5_command_str(op
), op
,
568 input
? "INPUT" : "OUTPUT");
570 mlx5_core_dbg(dev
, "dump command %s(0x%x) %s\n",
571 mlx5_command_str(op
), op
,
572 input
? "INPUT" : "OUTPUT");
576 dump_buf(ent
->lay
->in
, sizeof(ent
->lay
->in
), 1, offset
);
577 offset
+= sizeof(ent
->lay
->in
);
579 dump_buf(ent
->lay
->out
, sizeof(ent
->lay
->out
), 1, offset
);
580 offset
+= sizeof(ent
->lay
->out
);
583 dump_buf(ent
->lay
, sizeof(*ent
->lay
), 0, offset
);
584 offset
+= sizeof(*ent
->lay
);
587 while (next
&& offset
< msg
->len
) {
589 dump_len
= min_t(int, MLX5_CMD_DATA_BLOCK_SIZE
, msg
->len
- offset
);
590 dump_buf(next
->buf
, dump_len
, 1, offset
);
591 offset
+= MLX5_CMD_DATA_BLOCK_SIZE
;
593 mlx5_core_dbg(dev
, "command block:\n");
594 dump_buf(next
->buf
, sizeof(struct mlx5_cmd_prot_block
), 0, offset
);
595 offset
+= sizeof(struct mlx5_cmd_prot_block
);
604 static void cmd_work_handler(struct work_struct
*work
)
606 struct mlx5_cmd_work_ent
*ent
= container_of(work
, struct mlx5_cmd_work_ent
, work
);
607 struct mlx5_cmd
*cmd
= ent
->cmd
;
608 struct mlx5_core_dev
*dev
= container_of(cmd
, struct mlx5_core_dev
, cmd
);
609 struct mlx5_cmd_layout
*lay
;
610 struct semaphore
*sem
;
613 sem
= ent
->page_queue
? &cmd
->pages_sem
: &cmd
->sem
;
615 if (!ent
->page_queue
) {
616 ent
->idx
= alloc_ent(cmd
);
618 mlx5_core_err(dev
, "failed to allocate command entry\n");
623 ent
->idx
= cmd
->max_reg_cmds
;
624 spin_lock_irqsave(&cmd
->alloc_lock
, flags
);
625 clear_bit(ent
->idx
, &cmd
->bitmask
);
626 spin_unlock_irqrestore(&cmd
->alloc_lock
, flags
);
629 ent
->token
= alloc_token(cmd
);
630 cmd
->ent_arr
[ent
->idx
] = ent
;
631 lay
= get_inst(cmd
, ent
->idx
);
633 memset(lay
, 0, sizeof(*lay
));
634 memcpy(lay
->in
, ent
->in
->first
.data
, sizeof(lay
->in
));
635 ent
->op
= be32_to_cpu(lay
->in
[0]) >> 16;
637 lay
->in_ptr
= cpu_to_be64(ent
->in
->next
->dma
);
638 lay
->inlen
= cpu_to_be32(ent
->in
->len
);
640 lay
->out_ptr
= cpu_to_be64(ent
->out
->next
->dma
);
641 lay
->outlen
= cpu_to_be32(ent
->out
->len
);
642 lay
->type
= MLX5_PCI_CMD_XPORT
;
643 lay
->token
= ent
->token
;
644 lay
->status_own
= CMD_OWNER_HW
;
645 set_signature(ent
, !cmd
->checksum_disabled
);
646 dump_command(dev
, ent
, 1);
647 ent
->ts1
= ktime_get_ns();
649 /* ring doorbell after the descriptor is valid */
650 mlx5_core_dbg(dev
, "writing 0x%x to command doorbell\n", 1 << ent
->idx
);
652 iowrite32be(1 << ent
->idx
, &dev
->iseg
->cmd_dbell
);
654 /* if not in polling don't use ent after this point */
655 if (cmd
->mode
== CMD_MODE_POLLING
) {
657 /* make sure we read the descriptor after ownership is SW */
659 mlx5_cmd_comp_handler(dev
, 1UL << ent
->idx
);
663 static const char *deliv_status_to_str(u8 status
)
666 case MLX5_CMD_DELIVERY_STAT_OK
:
668 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR
:
669 return "signature error";
670 case MLX5_CMD_DELIVERY_STAT_TOK_ERR
:
671 return "token error";
672 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR
:
673 return "bad block number";
674 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR
:
675 return "output pointer not aligned to block size";
676 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR
:
677 return "input pointer not aligned to block size";
678 case MLX5_CMD_DELIVERY_STAT_FW_ERR
:
679 return "firmware internal error";
680 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR
:
681 return "command input length error";
682 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR
:
683 return "command ouput length error";
684 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR
:
685 return "reserved fields not cleared";
686 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR
:
687 return "bad command descriptor type";
689 return "unknown status code";
693 static u16
msg_to_opcode(struct mlx5_cmd_msg
*in
)
695 struct mlx5_inbox_hdr
*hdr
= (struct mlx5_inbox_hdr
*)(in
->first
.data
);
697 return be16_to_cpu(hdr
->opcode
);
700 static int wait_func(struct mlx5_core_dev
*dev
, struct mlx5_cmd_work_ent
*ent
)
702 unsigned long timeout
= msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC
);
703 struct mlx5_cmd
*cmd
= &dev
->cmd
;
706 if (cmd
->mode
== CMD_MODE_POLLING
) {
707 wait_for_completion(&ent
->done
);
710 if (!wait_for_completion_timeout(&ent
->done
, timeout
))
715 if (err
== -ETIMEDOUT
) {
716 mlx5_core_warn(dev
, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
717 mlx5_command_str(msg_to_opcode(ent
->in
)),
718 msg_to_opcode(ent
->in
));
720 mlx5_core_dbg(dev
, "err %d, delivery status %s(%d)\n",
721 err
, deliv_status_to_str(ent
->status
), ent
->status
);
726 static __be32
*get_synd_ptr(struct mlx5_outbox_hdr
*out
)
728 return &out
->syndrome
;
731 static u8
*get_status_ptr(struct mlx5_outbox_hdr
*out
)
737 * 1. Callback functions may not sleep
738 * 2. page queue commands do not support asynchrous completion
740 static int mlx5_cmd_invoke(struct mlx5_core_dev
*dev
, struct mlx5_cmd_msg
*in
,
741 struct mlx5_cmd_msg
*out
, void *uout
, int uout_size
,
742 mlx5_cmd_cbk_t callback
,
743 void *context
, int page_queue
, u8
*status
)
745 struct mlx5_cmd
*cmd
= &dev
->cmd
;
746 struct mlx5_cmd_work_ent
*ent
;
747 struct mlx5_cmd_stats
*stats
;
752 if (callback
&& page_queue
)
755 ent
= alloc_cmd(cmd
, in
, out
, uout
, uout_size
, callback
, context
,
761 init_completion(&ent
->done
);
763 INIT_WORK(&ent
->work
, cmd_work_handler
);
765 cmd_work_handler(&ent
->work
);
766 } else if (!queue_work(cmd
->wq
, &ent
->work
)) {
767 mlx5_core_warn(dev
, "failed to queue work\n");
773 err
= wait_func(dev
, ent
);
774 if (err
== -ETIMEDOUT
)
777 ds
= ent
->ts2
- ent
->ts1
;
778 op
= be16_to_cpu(((struct mlx5_inbox_hdr
*)in
->first
.data
)->opcode
);
779 if (op
< ARRAY_SIZE(cmd
->stats
)) {
780 stats
= &cmd
->stats
[op
];
781 spin_lock_irq(&stats
->lock
);
784 spin_unlock_irq(&stats
->lock
);
786 mlx5_core_dbg_mask(dev
, 1 << MLX5_CMD_TIME
,
787 "fw exec time for %s is %lld nsec\n",
788 mlx5_command_str(op
), ds
);
789 *status
= ent
->status
;
801 static ssize_t
dbg_write(struct file
*filp
, const char __user
*buf
,
802 size_t count
, loff_t
*pos
)
804 struct mlx5_core_dev
*dev
= filp
->private_data
;
805 struct mlx5_cmd_debug
*dbg
= &dev
->cmd
.dbg
;
809 if (!dbg
->in_msg
|| !dbg
->out_msg
)
812 if (copy_from_user(lbuf
, buf
, sizeof(lbuf
)))
815 lbuf
[sizeof(lbuf
) - 1] = 0;
817 if (strcmp(lbuf
, "go"))
820 err
= mlx5_cmd_exec(dev
, dbg
->in_msg
, dbg
->inlen
, dbg
->out_msg
, dbg
->outlen
);
822 return err
? err
: count
;
826 static const struct file_operations fops
= {
827 .owner
= THIS_MODULE
,
832 static int mlx5_copy_to_msg(struct mlx5_cmd_msg
*to
, void *from
, int size
)
834 struct mlx5_cmd_prot_block
*block
;
835 struct mlx5_cmd_mailbox
*next
;
841 copy
= min_t(int, size
, sizeof(to
->first
.data
));
842 memcpy(to
->first
.data
, from
, copy
);
853 copy
= min_t(int, size
, MLX5_CMD_DATA_BLOCK_SIZE
);
855 memcpy(block
->data
, from
, copy
);
864 static int mlx5_copy_from_msg(void *to
, struct mlx5_cmd_msg
*from
, int size
)
866 struct mlx5_cmd_prot_block
*block
;
867 struct mlx5_cmd_mailbox
*next
;
873 copy
= min_t(int, size
, sizeof(from
->first
.data
));
874 memcpy(to
, from
->first
.data
, copy
);
885 copy
= min_t(int, size
, MLX5_CMD_DATA_BLOCK_SIZE
);
888 memcpy(to
, block
->data
, copy
);
897 static struct mlx5_cmd_mailbox
*alloc_cmd_box(struct mlx5_core_dev
*dev
,
900 struct mlx5_cmd_mailbox
*mailbox
;
902 mailbox
= kmalloc(sizeof(*mailbox
), flags
);
904 return ERR_PTR(-ENOMEM
);
906 mailbox
->buf
= pci_pool_alloc(dev
->cmd
.pool
, flags
,
909 mlx5_core_dbg(dev
, "failed allocation\n");
911 return ERR_PTR(-ENOMEM
);
913 memset(mailbox
->buf
, 0, sizeof(struct mlx5_cmd_prot_block
));
914 mailbox
->next
= NULL
;
919 static void free_cmd_box(struct mlx5_core_dev
*dev
,
920 struct mlx5_cmd_mailbox
*mailbox
)
922 pci_pool_free(dev
->cmd
.pool
, mailbox
->buf
, mailbox
->dma
);
926 static struct mlx5_cmd_msg
*mlx5_alloc_cmd_msg(struct mlx5_core_dev
*dev
,
927 gfp_t flags
, int size
)
929 struct mlx5_cmd_mailbox
*tmp
, *head
= NULL
;
930 struct mlx5_cmd_prot_block
*block
;
931 struct mlx5_cmd_msg
*msg
;
937 msg
= kzalloc(sizeof(*msg
), flags
);
939 return ERR_PTR(-ENOMEM
);
941 blen
= size
- min_t(int, sizeof(msg
->first
.data
), size
);
942 n
= (blen
+ MLX5_CMD_DATA_BLOCK_SIZE
- 1) / MLX5_CMD_DATA_BLOCK_SIZE
;
944 for (i
= 0; i
< n
; i
++) {
945 tmp
= alloc_cmd_box(dev
, flags
);
947 mlx5_core_warn(dev
, "failed allocating block\n");
954 block
->next
= cpu_to_be64(tmp
->next
? tmp
->next
->dma
: 0);
955 block
->block_num
= cpu_to_be32(n
- i
- 1);
965 free_cmd_box(dev
, head
);
973 static void mlx5_free_cmd_msg(struct mlx5_core_dev
*dev
,
974 struct mlx5_cmd_msg
*msg
)
976 struct mlx5_cmd_mailbox
*head
= msg
->next
;
977 struct mlx5_cmd_mailbox
*next
;
981 free_cmd_box(dev
, head
);
987 static ssize_t
data_write(struct file
*filp
, const char __user
*buf
,
988 size_t count
, loff_t
*pos
)
990 struct mlx5_core_dev
*dev
= filp
->private_data
;
991 struct mlx5_cmd_debug
*dbg
= &dev
->cmd
.dbg
;
1002 ptr
= kzalloc(count
, GFP_KERNEL
);
1006 if (copy_from_user(ptr
, buf
, count
)) {
1022 static ssize_t
data_read(struct file
*filp
, char __user
*buf
, size_t count
,
1025 struct mlx5_core_dev
*dev
= filp
->private_data
;
1026 struct mlx5_cmd_debug
*dbg
= &dev
->cmd
.dbg
;
1035 copy
= min_t(int, count
, dbg
->outlen
);
1036 if (copy_to_user(buf
, dbg
->out_msg
, copy
))
1044 static const struct file_operations dfops
= {
1045 .owner
= THIS_MODULE
,
1046 .open
= simple_open
,
1047 .write
= data_write
,
1051 static ssize_t
outlen_read(struct file
*filp
, char __user
*buf
, size_t count
,
1054 struct mlx5_core_dev
*dev
= filp
->private_data
;
1055 struct mlx5_cmd_debug
*dbg
= &dev
->cmd
.dbg
;
1062 err
= snprintf(outlen
, sizeof(outlen
), "%d", dbg
->outlen
);
1066 if (copy_to_user(buf
, &outlen
, err
))
1074 static ssize_t
outlen_write(struct file
*filp
, const char __user
*buf
,
1075 size_t count
, loff_t
*pos
)
1077 struct mlx5_core_dev
*dev
= filp
->private_data
;
1078 struct mlx5_cmd_debug
*dbg
= &dev
->cmd
.dbg
;
1084 if (*pos
!= 0 || count
> 6)
1087 kfree(dbg
->out_msg
);
1088 dbg
->out_msg
= NULL
;
1091 if (copy_from_user(outlen_str
, buf
, count
))
1096 err
= sscanf(outlen_str
, "%d", &outlen
);
1100 ptr
= kzalloc(outlen
, GFP_KERNEL
);
1105 dbg
->outlen
= outlen
;
1112 static const struct file_operations olfops
= {
1113 .owner
= THIS_MODULE
,
1114 .open
= simple_open
,
1115 .write
= outlen_write
,
1116 .read
= outlen_read
,
1119 static void set_wqname(struct mlx5_core_dev
*dev
)
1121 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1123 snprintf(cmd
->wq_name
, sizeof(cmd
->wq_name
), "mlx5_cmd_%s",
1124 dev_name(&dev
->pdev
->dev
));
1127 static void clean_debug_files(struct mlx5_core_dev
*dev
)
1129 struct mlx5_cmd_debug
*dbg
= &dev
->cmd
.dbg
;
1131 if (!mlx5_debugfs_root
)
1134 mlx5_cmdif_debugfs_cleanup(dev
);
1135 debugfs_remove_recursive(dbg
->dbg_root
);
1138 static int create_debugfs_files(struct mlx5_core_dev
*dev
)
1140 struct mlx5_cmd_debug
*dbg
= &dev
->cmd
.dbg
;
1143 if (!mlx5_debugfs_root
)
1146 dbg
->dbg_root
= debugfs_create_dir("cmd", dev
->priv
.dbg_root
);
1150 dbg
->dbg_in
= debugfs_create_file("in", 0400, dbg
->dbg_root
,
1155 dbg
->dbg_out
= debugfs_create_file("out", 0200, dbg
->dbg_root
,
1160 dbg
->dbg_outlen
= debugfs_create_file("out_len", 0600, dbg
->dbg_root
,
1162 if (!dbg
->dbg_outlen
)
1165 dbg
->dbg_status
= debugfs_create_u8("status", 0600, dbg
->dbg_root
,
1167 if (!dbg
->dbg_status
)
1170 dbg
->dbg_run
= debugfs_create_file("run", 0200, dbg
->dbg_root
, dev
, &fops
);
1174 mlx5_cmdif_debugfs_init(dev
);
1179 clean_debug_files(dev
);
1183 void mlx5_cmd_use_events(struct mlx5_core_dev
*dev
)
1185 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1188 for (i
= 0; i
< cmd
->max_reg_cmds
; i
++)
1191 down(&cmd
->pages_sem
);
1193 flush_workqueue(cmd
->wq
);
1195 cmd
->mode
= CMD_MODE_EVENTS
;
1197 up(&cmd
->pages_sem
);
1198 for (i
= 0; i
< cmd
->max_reg_cmds
; i
++)
1202 void mlx5_cmd_use_polling(struct mlx5_core_dev
*dev
)
1204 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1207 for (i
= 0; i
< cmd
->max_reg_cmds
; i
++)
1210 down(&cmd
->pages_sem
);
1212 flush_workqueue(cmd
->wq
);
1213 cmd
->mode
= CMD_MODE_POLLING
;
1215 up(&cmd
->pages_sem
);
1216 for (i
= 0; i
< cmd
->max_reg_cmds
; i
++)
1220 static void free_msg(struct mlx5_core_dev
*dev
, struct mlx5_cmd_msg
*msg
)
1222 unsigned long flags
;
1225 spin_lock_irqsave(&msg
->cache
->lock
, flags
);
1226 list_add_tail(&msg
->list
, &msg
->cache
->head
);
1227 spin_unlock_irqrestore(&msg
->cache
->lock
, flags
);
1229 mlx5_free_cmd_msg(dev
, msg
);
1233 void mlx5_cmd_comp_handler(struct mlx5_core_dev
*dev
, u64 vec
)
1235 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1236 struct mlx5_cmd_work_ent
*ent
;
1237 mlx5_cmd_cbk_t callback
;
1242 struct mlx5_cmd_stats
*stats
;
1243 unsigned long flags
;
1244 unsigned long vector
;
1246 /* there can be at most 32 command queues */
1247 vector
= vec
& 0xffffffff;
1248 for (i
= 0; i
< (1 << cmd
->log_sz
); i
++) {
1249 if (test_bit(i
, &vector
)) {
1250 struct semaphore
*sem
;
1252 ent
= cmd
->ent_arr
[i
];
1253 if (ent
->page_queue
)
1254 sem
= &cmd
->pages_sem
;
1257 ent
->ts2
= ktime_get_ns();
1258 memcpy(ent
->out
->first
.data
, ent
->lay
->out
, sizeof(ent
->lay
->out
));
1259 dump_command(dev
, ent
, 0);
1261 if (!cmd
->checksum_disabled
)
1262 ent
->ret
= verify_signature(ent
);
1265 if (vec
& MLX5_TRIGGERED_CMD_COMP
)
1266 ent
->status
= MLX5_DRIVER_STATUS_ABORTED
;
1268 ent
->status
= ent
->lay
->status_own
>> 1;
1270 mlx5_core_dbg(dev
, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1271 ent
->ret
, deliv_status_to_str(ent
->status
), ent
->status
);
1273 free_ent(cmd
, ent
->idx
);
1275 if (ent
->callback
) {
1276 ds
= ent
->ts2
- ent
->ts1
;
1277 if (ent
->op
< ARRAY_SIZE(cmd
->stats
)) {
1278 stats
= &cmd
->stats
[ent
->op
];
1279 spin_lock_irqsave(&stats
->lock
, flags
);
1282 spin_unlock_irqrestore(&stats
->lock
, flags
);
1285 callback
= ent
->callback
;
1286 context
= ent
->context
;
1289 err
= mlx5_copy_from_msg(ent
->uout
,
1293 mlx5_free_cmd_msg(dev
, ent
->out
);
1294 free_msg(dev
, ent
->in
);
1296 err
= err
? err
: ent
->status
;
1298 callback(err
, context
);
1300 complete(&ent
->done
);
1306 EXPORT_SYMBOL(mlx5_cmd_comp_handler
);
1308 static int status_to_err(u8 status
)
1310 return status
? -1 : 0; /* TBD more meaningful codes */
1313 static struct mlx5_cmd_msg
*alloc_msg(struct mlx5_core_dev
*dev
, int in_size
,
1316 struct mlx5_cmd_msg
*msg
= ERR_PTR(-ENOMEM
);
1317 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1318 struct cache_ent
*ent
= NULL
;
1320 if (in_size
> MED_LIST_SIZE
&& in_size
<= LONG_LIST_SIZE
)
1321 ent
= &cmd
->cache
.large
;
1322 else if (in_size
> 16 && in_size
<= MED_LIST_SIZE
)
1323 ent
= &cmd
->cache
.med
;
1326 spin_lock_irq(&ent
->lock
);
1327 if (!list_empty(&ent
->head
)) {
1328 msg
= list_entry(ent
->head
.next
, typeof(*msg
), list
);
1329 /* For cached lists, we must explicitly state what is
1333 list_del(&msg
->list
);
1335 spin_unlock_irq(&ent
->lock
);
1339 msg
= mlx5_alloc_cmd_msg(dev
, gfp
, in_size
);
1344 static u16
opcode_from_in(struct mlx5_inbox_hdr
*in
)
1346 return be16_to_cpu(in
->opcode
);
1349 static int is_manage_pages(struct mlx5_inbox_hdr
*in
)
1351 return be16_to_cpu(in
->opcode
) == MLX5_CMD_OP_MANAGE_PAGES
;
1354 static int cmd_exec(struct mlx5_core_dev
*dev
, void *in
, int in_size
, void *out
,
1355 int out_size
, mlx5_cmd_cbk_t callback
, void *context
)
1357 struct mlx5_cmd_msg
*inb
;
1358 struct mlx5_cmd_msg
*outb
;
1365 if (pci_channel_offline(dev
->pdev
) ||
1366 dev
->state
== MLX5_DEVICE_STATE_INTERNAL_ERROR
) {
1367 err
= mlx5_internal_err_ret_value(dev
, opcode_from_in(in
), &drv_synd
, &status
);
1368 *get_synd_ptr(out
) = cpu_to_be32(drv_synd
);
1369 *get_status_ptr(out
) = status
;
1373 pages_queue
= is_manage_pages(in
);
1374 gfp
= callback
? GFP_ATOMIC
: GFP_KERNEL
;
1376 inb
= alloc_msg(dev
, in_size
, gfp
);
1382 err
= mlx5_copy_to_msg(inb
, in
, in_size
);
1384 mlx5_core_warn(dev
, "err %d\n", err
);
1388 outb
= mlx5_alloc_cmd_msg(dev
, gfp
, out_size
);
1390 err
= PTR_ERR(outb
);
1394 err
= mlx5_cmd_invoke(dev
, inb
, outb
, out
, out_size
, callback
, context
,
1395 pages_queue
, &status
);
1399 mlx5_core_dbg(dev
, "err %d, status %d\n", err
, status
);
1401 err
= status_to_err(status
);
1406 err
= mlx5_copy_from_msg(out
, outb
, out_size
);
1410 mlx5_free_cmd_msg(dev
, outb
);
1418 int mlx5_cmd_exec(struct mlx5_core_dev
*dev
, void *in
, int in_size
, void *out
,
1421 return cmd_exec(dev
, in
, in_size
, out
, out_size
, NULL
, NULL
);
1423 EXPORT_SYMBOL(mlx5_cmd_exec
);
1425 int mlx5_cmd_exec_cb(struct mlx5_core_dev
*dev
, void *in
, int in_size
,
1426 void *out
, int out_size
, mlx5_cmd_cbk_t callback
,
1429 return cmd_exec(dev
, in
, in_size
, out
, out_size
, callback
, context
);
1431 EXPORT_SYMBOL(mlx5_cmd_exec_cb
);
1433 static void destroy_msg_cache(struct mlx5_core_dev
*dev
)
1435 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1436 struct mlx5_cmd_msg
*msg
;
1437 struct mlx5_cmd_msg
*n
;
1439 list_for_each_entry_safe(msg
, n
, &cmd
->cache
.large
.head
, list
) {
1440 list_del(&msg
->list
);
1441 mlx5_free_cmd_msg(dev
, msg
);
1444 list_for_each_entry_safe(msg
, n
, &cmd
->cache
.med
.head
, list
) {
1445 list_del(&msg
->list
);
1446 mlx5_free_cmd_msg(dev
, msg
);
1450 static int create_msg_cache(struct mlx5_core_dev
*dev
)
1452 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1453 struct mlx5_cmd_msg
*msg
;
1457 spin_lock_init(&cmd
->cache
.large
.lock
);
1458 INIT_LIST_HEAD(&cmd
->cache
.large
.head
);
1459 spin_lock_init(&cmd
->cache
.med
.lock
);
1460 INIT_LIST_HEAD(&cmd
->cache
.med
.head
);
1462 for (i
= 0; i
< NUM_LONG_LISTS
; i
++) {
1463 msg
= mlx5_alloc_cmd_msg(dev
, GFP_KERNEL
, LONG_LIST_SIZE
);
1468 msg
->cache
= &cmd
->cache
.large
;
1469 list_add_tail(&msg
->list
, &cmd
->cache
.large
.head
);
1472 for (i
= 0; i
< NUM_MED_LISTS
; i
++) {
1473 msg
= mlx5_alloc_cmd_msg(dev
, GFP_KERNEL
, MED_LIST_SIZE
);
1478 msg
->cache
= &cmd
->cache
.med
;
1479 list_add_tail(&msg
->list
, &cmd
->cache
.med
.head
);
1485 destroy_msg_cache(dev
);
1489 static int alloc_cmd_page(struct mlx5_core_dev
*dev
, struct mlx5_cmd
*cmd
)
1491 struct device
*ddev
= &dev
->pdev
->dev
;
1493 cmd
->cmd_alloc_buf
= dma_zalloc_coherent(ddev
, MLX5_ADAPTER_PAGE_SIZE
,
1494 &cmd
->alloc_dma
, GFP_KERNEL
);
1495 if (!cmd
->cmd_alloc_buf
)
1498 /* make sure it is aligned to 4K */
1499 if (!((uintptr_t)cmd
->cmd_alloc_buf
& (MLX5_ADAPTER_PAGE_SIZE
- 1))) {
1500 cmd
->cmd_buf
= cmd
->cmd_alloc_buf
;
1501 cmd
->dma
= cmd
->alloc_dma
;
1502 cmd
->alloc_size
= MLX5_ADAPTER_PAGE_SIZE
;
1506 dma_free_coherent(ddev
, MLX5_ADAPTER_PAGE_SIZE
, cmd
->cmd_alloc_buf
,
1508 cmd
->cmd_alloc_buf
= dma_zalloc_coherent(ddev
,
1509 2 * MLX5_ADAPTER_PAGE_SIZE
- 1,
1510 &cmd
->alloc_dma
, GFP_KERNEL
);
1511 if (!cmd
->cmd_alloc_buf
)
1514 cmd
->cmd_buf
= PTR_ALIGN(cmd
->cmd_alloc_buf
, MLX5_ADAPTER_PAGE_SIZE
);
1515 cmd
->dma
= ALIGN(cmd
->alloc_dma
, MLX5_ADAPTER_PAGE_SIZE
);
1516 cmd
->alloc_size
= 2 * MLX5_ADAPTER_PAGE_SIZE
- 1;
1520 static void free_cmd_page(struct mlx5_core_dev
*dev
, struct mlx5_cmd
*cmd
)
1522 struct device
*ddev
= &dev
->pdev
->dev
;
1524 dma_free_coherent(ddev
, cmd
->alloc_size
, cmd
->cmd_alloc_buf
,
1528 int mlx5_cmd_init(struct mlx5_core_dev
*dev
)
1530 int size
= sizeof(struct mlx5_cmd_prot_block
);
1531 int align
= roundup_pow_of_two(size
);
1532 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1538 memset(cmd
, 0, sizeof(*cmd
));
1539 cmd_if_rev
= cmdif_rev(dev
);
1540 if (cmd_if_rev
!= CMD_IF_REV
) {
1541 dev_err(&dev
->pdev
->dev
,
1542 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1543 CMD_IF_REV
, cmd_if_rev
);
1547 cmd
->pool
= pci_pool_create("mlx5_cmd", dev
->pdev
, size
, align
, 0);
1551 err
= alloc_cmd_page(dev
, cmd
);
1555 cmd_l
= ioread32be(&dev
->iseg
->cmdq_addr_l_sz
) & 0xff;
1556 cmd
->log_sz
= cmd_l
>> 4 & 0xf;
1557 cmd
->log_stride
= cmd_l
& 0xf;
1558 if (1 << cmd
->log_sz
> MLX5_MAX_COMMANDS
) {
1559 dev_err(&dev
->pdev
->dev
, "firmware reports too many outstanding commands %d\n",
1565 if (cmd
->log_sz
+ cmd
->log_stride
> MLX5_ADAPTER_PAGE_SHIFT
) {
1566 dev_err(&dev
->pdev
->dev
, "command queue size overflow\n");
1571 cmd
->checksum_disabled
= 1;
1572 cmd
->max_reg_cmds
= (1 << cmd
->log_sz
) - 1;
1573 cmd
->bitmask
= (1 << cmd
->max_reg_cmds
) - 1;
1575 cmd
->cmdif_rev
= ioread32be(&dev
->iseg
->cmdif_rev_fw_sub
) >> 16;
1576 if (cmd
->cmdif_rev
> CMD_IF_REV
) {
1577 dev_err(&dev
->pdev
->dev
, "driver does not support command interface version. driver %d, firmware %d\n",
1578 CMD_IF_REV
, cmd
->cmdif_rev
);
1583 spin_lock_init(&cmd
->alloc_lock
);
1584 spin_lock_init(&cmd
->token_lock
);
1585 for (i
= 0; i
< ARRAY_SIZE(cmd
->stats
); i
++)
1586 spin_lock_init(&cmd
->stats
[i
].lock
);
1588 sema_init(&cmd
->sem
, cmd
->max_reg_cmds
);
1589 sema_init(&cmd
->pages_sem
, 1);
1591 cmd_h
= (u32
)((u64
)(cmd
->dma
) >> 32);
1592 cmd_l
= (u32
)(cmd
->dma
);
1593 if (cmd_l
& 0xfff) {
1594 dev_err(&dev
->pdev
->dev
, "invalid command queue address\n");
1599 iowrite32be(cmd_h
, &dev
->iseg
->cmdq_addr_h
);
1600 iowrite32be(cmd_l
, &dev
->iseg
->cmdq_addr_l_sz
);
1602 /* Make sure firmware sees the complete address before we proceed */
1605 mlx5_core_dbg(dev
, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd
->dma
));
1607 cmd
->mode
= CMD_MODE_POLLING
;
1609 err
= create_msg_cache(dev
);
1611 dev_err(&dev
->pdev
->dev
, "failed to create command cache\n");
1616 cmd
->wq
= create_singlethread_workqueue(cmd
->wq_name
);
1618 dev_err(&dev
->pdev
->dev
, "failed to create command workqueue\n");
1623 err
= create_debugfs_files(dev
);
1632 destroy_workqueue(cmd
->wq
);
1635 destroy_msg_cache(dev
);
1638 free_cmd_page(dev
, cmd
);
1641 pci_pool_destroy(cmd
->pool
);
1645 EXPORT_SYMBOL(mlx5_cmd_init
);
1647 void mlx5_cmd_cleanup(struct mlx5_core_dev
*dev
)
1649 struct mlx5_cmd
*cmd
= &dev
->cmd
;
1651 clean_debug_files(dev
);
1652 destroy_workqueue(cmd
->wq
);
1653 destroy_msg_cache(dev
);
1654 free_cmd_page(dev
, cmd
);
1655 pci_pool_destroy(cmd
->pool
);
1657 EXPORT_SYMBOL(mlx5_cmd_cleanup
);
1659 static const char *cmd_status_str(u8 status
)
1662 case MLX5_CMD_STAT_OK
:
1664 case MLX5_CMD_STAT_INT_ERR
:
1665 return "internal error";
1666 case MLX5_CMD_STAT_BAD_OP_ERR
:
1667 return "bad operation";
1668 case MLX5_CMD_STAT_BAD_PARAM_ERR
:
1669 return "bad parameter";
1670 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR
:
1671 return "bad system state";
1672 case MLX5_CMD_STAT_BAD_RES_ERR
:
1673 return "bad resource";
1674 case MLX5_CMD_STAT_RES_BUSY
:
1675 return "resource busy";
1676 case MLX5_CMD_STAT_LIM_ERR
:
1677 return "limits exceeded";
1678 case MLX5_CMD_STAT_BAD_RES_STATE_ERR
:
1679 return "bad resource state";
1680 case MLX5_CMD_STAT_IX_ERR
:
1682 case MLX5_CMD_STAT_NO_RES_ERR
:
1683 return "no resources";
1684 case MLX5_CMD_STAT_BAD_INP_LEN_ERR
:
1685 return "bad input length";
1686 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR
:
1687 return "bad output length";
1688 case MLX5_CMD_STAT_BAD_QP_STATE_ERR
:
1689 return "bad QP state";
1690 case MLX5_CMD_STAT_BAD_PKT_ERR
:
1691 return "bad packet (discarded)";
1692 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR
:
1693 return "bad size too many outstanding CQEs";
1695 return "unknown status";
1699 static int cmd_status_to_err(u8 status
)
1702 case MLX5_CMD_STAT_OK
: return 0;
1703 case MLX5_CMD_STAT_INT_ERR
: return -EIO
;
1704 case MLX5_CMD_STAT_BAD_OP_ERR
: return -EINVAL
;
1705 case MLX5_CMD_STAT_BAD_PARAM_ERR
: return -EINVAL
;
1706 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR
: return -EIO
;
1707 case MLX5_CMD_STAT_BAD_RES_ERR
: return -EINVAL
;
1708 case MLX5_CMD_STAT_RES_BUSY
: return -EBUSY
;
1709 case MLX5_CMD_STAT_LIM_ERR
: return -ENOMEM
;
1710 case MLX5_CMD_STAT_BAD_RES_STATE_ERR
: return -EINVAL
;
1711 case MLX5_CMD_STAT_IX_ERR
: return -EINVAL
;
1712 case MLX5_CMD_STAT_NO_RES_ERR
: return -EAGAIN
;
1713 case MLX5_CMD_STAT_BAD_INP_LEN_ERR
: return -EIO
;
1714 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR
: return -EIO
;
1715 case MLX5_CMD_STAT_BAD_QP_STATE_ERR
: return -EINVAL
;
1716 case MLX5_CMD_STAT_BAD_PKT_ERR
: return -EINVAL
;
1717 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR
: return -EINVAL
;
1718 default: return -EIO
;
1722 /* this will be available till all the commands use set/get macros */
1723 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr
*hdr
)
1728 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1729 cmd_status_str(hdr
->status
), hdr
->status
,
1730 be32_to_cpu(hdr
->syndrome
));
1732 return cmd_status_to_err(hdr
->status
);
1735 int mlx5_cmd_status_to_err_v2(void *ptr
)
1740 status
= be32_to_cpu(*(__be32
*)ptr
) >> 24;
1744 syndrome
= be32_to_cpu(*(__be32
*)(ptr
+ 4));
1746 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1747 cmd_status_str(status
), status
, syndrome
);
1749 return cmd_status_to_err(status
);