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[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en.h
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include "wq.h"
48 #include "mlx5_core.h"
49 #include "en_stats.h"
50
51 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
52
53 #define MLX5E_MAX_NUM_TC 8
54
55 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
56 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
58
59 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
60 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
62
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
66
67 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_LOG_WQE_SZ 17
70 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
71 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
72 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
73 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
74 MLX5_MPWRQ_WQE_PAGE_ORDER)
75 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
76 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
77 #define MLX5_UMR_ALIGN (2048)
78 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
79
80 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
81 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
83 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
85 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
87 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
88
89 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
90 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
91 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
92 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
93 #define MLX5E_TX_CQ_POLL_BUDGET 128
94 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
95 #define MLX5E_SQ_BF_BUDGET 16
96
97 #define MLX5E_NUM_MAIN_GROUPS 9
98
99 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
100 {
101 switch (wq_type) {
102 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
103 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
104 wq_size / 2);
105 default:
106 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
107 wq_size / 2);
108 }
109 }
110
111 static inline int mlx5_min_log_rq_size(int wq_type)
112 {
113 switch (wq_type) {
114 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
115 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
116 default:
117 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
118 }
119 }
120
121 static inline int mlx5_max_log_rq_size(int wq_type)
122 {
123 switch (wq_type) {
124 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
125 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
126 default:
127 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
128 }
129 }
130
131 struct mlx5e_tx_wqe {
132 struct mlx5_wqe_ctrl_seg ctrl;
133 struct mlx5_wqe_eth_seg eth;
134 };
135
136 struct mlx5e_rx_wqe {
137 struct mlx5_wqe_srq_next_seg next;
138 struct mlx5_wqe_data_seg data;
139 };
140
141 struct mlx5e_umr_wqe {
142 struct mlx5_wqe_ctrl_seg ctrl;
143 struct mlx5_wqe_umr_ctrl_seg uctrl;
144 struct mlx5_mkey_seg mkc;
145 struct mlx5_wqe_data_seg data;
146 };
147
148 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
149 "rx_cqe_moder",
150 };
151
152 enum mlx5e_priv_flag {
153 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
154 };
155
156 #define MLX5E_SET_PRIV_FLAG(priv, pflag, enable) \
157 do { \
158 if (enable) \
159 priv->pflags |= pflag; \
160 else \
161 priv->pflags &= ~pflag; \
162 } while (0)
163
164 #ifdef CONFIG_MLX5_CORE_EN_DCB
165 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
166 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
167 #endif
168
169 struct mlx5e_cq_moder {
170 u16 usec;
171 u16 pkts;
172 };
173
174 struct mlx5e_params {
175 u8 log_sq_size;
176 u8 rq_wq_type;
177 u8 mpwqe_log_stride_sz;
178 u8 mpwqe_log_num_strides;
179 u8 log_rq_size;
180 u16 num_channels;
181 u8 num_tc;
182 u8 rx_cq_period_mode;
183 bool rx_cqe_compress_admin;
184 bool rx_cqe_compress;
185 struct mlx5e_cq_moder rx_cq_moderation;
186 struct mlx5e_cq_moder tx_cq_moderation;
187 u16 min_rx_wqes;
188 bool lro_en;
189 u32 lro_wqe_sz;
190 u16 tx_max_inline;
191 u8 rss_hfunc;
192 u8 toeplitz_hash_key[40];
193 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
194 bool vlan_strip_disable;
195 #ifdef CONFIG_MLX5_CORE_EN_DCB
196 struct ieee_ets ets;
197 #endif
198 bool rx_am_enabled;
199 };
200
201 struct mlx5e_tstamp {
202 rwlock_t lock;
203 struct cyclecounter cycles;
204 struct timecounter clock;
205 struct hwtstamp_config hwtstamp_config;
206 u32 nominal_c_mult;
207 unsigned long overflow_period;
208 struct delayed_work overflow_work;
209 struct mlx5_core_dev *mdev;
210 struct ptp_clock *ptp;
211 struct ptp_clock_info ptp_info;
212 };
213
214 enum {
215 MLX5E_RQ_STATE_POST_WQES_ENABLE,
216 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
217 MLX5E_RQ_STATE_AM,
218 };
219
220 struct mlx5e_cq {
221 /* data path - accessed per cqe */
222 struct mlx5_cqwq wq;
223
224 /* data path - accessed per napi poll */
225 u16 event_ctr;
226 struct napi_struct *napi;
227 struct mlx5_core_cq mcq;
228 struct mlx5e_channel *channel;
229 struct mlx5e_priv *priv;
230
231 /* cqe decompression */
232 struct mlx5_cqe64 title;
233 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
234 u8 mini_arr_idx;
235 u16 decmprs_left;
236 u16 decmprs_wqe_counter;
237
238 /* control */
239 struct mlx5_wq_ctrl wq_ctrl;
240 } ____cacheline_aligned_in_smp;
241
242 struct mlx5e_rq;
243 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
244 struct mlx5_cqe64 *cqe);
245 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
246 u16 ix);
247
248 struct mlx5e_dma_info {
249 struct page *page;
250 dma_addr_t addr;
251 };
252
253 struct mlx5e_rx_am_stats {
254 int ppms; /* packets per msec */
255 int epms; /* events per msec */
256 };
257
258 struct mlx5e_rx_am_sample {
259 ktime_t time;
260 unsigned int pkt_ctr;
261 u16 event_ctr;
262 };
263
264 struct mlx5e_rx_am { /* Adaptive Moderation */
265 u8 state;
266 struct mlx5e_rx_am_stats prev_stats;
267 struct mlx5e_rx_am_sample start_sample;
268 struct work_struct work;
269 u8 profile_ix;
270 u8 mode;
271 u8 tune_state;
272 u8 steps_right;
273 u8 steps_left;
274 u8 tired;
275 };
276
277 struct mlx5e_rq {
278 /* data path */
279 struct mlx5_wq_ll wq;
280 u32 wqe_sz;
281 struct sk_buff **skb;
282 struct mlx5e_mpw_info *wqe_info;
283 __be32 mkey_be;
284 __be32 umr_mkey_be;
285
286 struct device *pdev;
287 struct net_device *netdev;
288 struct mlx5e_tstamp *tstamp;
289 struct mlx5e_rq_stats stats;
290 struct mlx5e_cq cq;
291 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
292 mlx5e_fp_alloc_wqe alloc_wqe;
293
294 unsigned long state;
295 int ix;
296
297 struct mlx5e_rx_am am; /* Adaptive Moderation */
298
299 /* control */
300 struct mlx5_wq_ctrl wq_ctrl;
301 u8 wq_type;
302 u32 mpwqe_stride_sz;
303 u32 mpwqe_num_strides;
304 u32 rqn;
305 struct mlx5e_channel *channel;
306 struct mlx5e_priv *priv;
307 } ____cacheline_aligned_in_smp;
308
309 struct mlx5e_umr_dma_info {
310 __be64 *mtt;
311 __be64 *mtt_no_align;
312 dma_addr_t mtt_addr;
313 struct mlx5e_dma_info *dma_info;
314 };
315
316 struct mlx5e_mpw_info {
317 union {
318 struct mlx5e_dma_info dma_info;
319 struct mlx5e_umr_dma_info umr;
320 };
321 u16 consumed_strides;
322 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
323
324 void (*dma_pre_sync)(struct device *pdev,
325 struct mlx5e_mpw_info *wi,
326 u32 wqe_offset, u32 len);
327 void (*add_skb_frag)(struct mlx5e_rq *rq,
328 struct sk_buff *skb,
329 struct mlx5e_mpw_info *wi,
330 u32 page_idx, u32 frag_offset, u32 len);
331 void (*copy_skb_header)(struct device *pdev,
332 struct sk_buff *skb,
333 struct mlx5e_mpw_info *wi,
334 u32 page_idx, u32 offset,
335 u32 headlen);
336 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
337 };
338
339 struct mlx5e_tx_wqe_info {
340 u32 num_bytes;
341 u8 num_wqebbs;
342 u8 num_dma;
343 };
344
345 enum mlx5e_dma_map_type {
346 MLX5E_DMA_MAP_SINGLE,
347 MLX5E_DMA_MAP_PAGE
348 };
349
350 struct mlx5e_sq_dma {
351 dma_addr_t addr;
352 u32 size;
353 enum mlx5e_dma_map_type type;
354 };
355
356 enum {
357 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
358 MLX5E_SQ_STATE_BF_ENABLE,
359 };
360
361 struct mlx5e_ico_wqe_info {
362 u8 opcode;
363 u8 num_wqebbs;
364 };
365
366 struct mlx5e_sq {
367 /* data path */
368
369 /* dirtied @completion */
370 u16 cc;
371 u32 dma_fifo_cc;
372
373 /* dirtied @xmit */
374 u16 pc ____cacheline_aligned_in_smp;
375 u32 dma_fifo_pc;
376 u16 bf_offset;
377 u16 prev_cc;
378 u8 bf_budget;
379 struct mlx5e_sq_stats stats;
380
381 struct mlx5e_cq cq;
382
383 /* pointers to per packet info: write@xmit, read@completion */
384 struct sk_buff **skb;
385 struct mlx5e_sq_dma *dma_fifo;
386 struct mlx5e_tx_wqe_info *wqe_info;
387
388 /* read only */
389 struct mlx5_wq_cyc wq;
390 u32 dma_fifo_mask;
391 void __iomem *uar_map;
392 struct netdev_queue *txq;
393 u32 sqn;
394 u16 bf_buf_size;
395 u16 max_inline;
396 u16 edge;
397 struct device *pdev;
398 struct mlx5e_tstamp *tstamp;
399 __be32 mkey_be;
400 unsigned long state;
401
402 /* control path */
403 struct mlx5_wq_ctrl wq_ctrl;
404 struct mlx5_uar uar;
405 struct mlx5e_channel *channel;
406 int tc;
407 struct mlx5e_ico_wqe_info *ico_wqe_info;
408 u32 rate_limit;
409 } ____cacheline_aligned_in_smp;
410
411 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
412 {
413 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
414 (sq->cc == sq->pc));
415 }
416
417 enum channel_flags {
418 MLX5E_CHANNEL_NAPI_SCHED = 1,
419 };
420
421 struct mlx5e_channel {
422 /* data path */
423 struct mlx5e_rq rq;
424 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
425 struct mlx5e_sq icosq; /* internal control operations */
426 struct napi_struct napi;
427 struct device *pdev;
428 struct net_device *netdev;
429 __be32 mkey_be;
430 u8 num_tc;
431 unsigned long flags;
432
433 /* control */
434 struct mlx5e_priv *priv;
435 int ix;
436 int cpu;
437 };
438
439 enum mlx5e_traffic_types {
440 MLX5E_TT_IPV4_TCP,
441 MLX5E_TT_IPV6_TCP,
442 MLX5E_TT_IPV4_UDP,
443 MLX5E_TT_IPV6_UDP,
444 MLX5E_TT_IPV4_IPSEC_AH,
445 MLX5E_TT_IPV6_IPSEC_AH,
446 MLX5E_TT_IPV4_IPSEC_ESP,
447 MLX5E_TT_IPV6_IPSEC_ESP,
448 MLX5E_TT_IPV4,
449 MLX5E_TT_IPV6,
450 MLX5E_TT_ANY,
451 MLX5E_NUM_TT,
452 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
453 };
454
455 enum {
456 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
457 MLX5E_STATE_OPENED,
458 MLX5E_STATE_DESTROYING,
459 };
460
461 struct mlx5e_vxlan_db {
462 spinlock_t lock; /* protect vxlan table */
463 struct radix_tree_root tree;
464 };
465
466 struct mlx5e_l2_rule {
467 u8 addr[ETH_ALEN + 2];
468 struct mlx5_flow_rule *rule;
469 };
470
471 struct mlx5e_flow_table {
472 int num_groups;
473 struct mlx5_flow_table *t;
474 struct mlx5_flow_group **g;
475 };
476
477 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
478
479 struct mlx5e_tc_table {
480 struct mlx5_flow_table *t;
481
482 struct rhashtable_params ht_params;
483 struct rhashtable ht;
484 };
485
486 struct mlx5e_vlan_table {
487 struct mlx5e_flow_table ft;
488 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
489 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
490 struct mlx5_flow_rule *untagged_rule;
491 struct mlx5_flow_rule *any_vlan_rule;
492 bool filter_disabled;
493 };
494
495 struct mlx5e_l2_table {
496 struct mlx5e_flow_table ft;
497 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
498 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
499 struct mlx5e_l2_rule broadcast;
500 struct mlx5e_l2_rule allmulti;
501 struct mlx5e_l2_rule promisc;
502 bool broadcast_enabled;
503 bool allmulti_enabled;
504 bool promisc_enabled;
505 };
506
507 /* L3/L4 traffic type classifier */
508 struct mlx5e_ttc_table {
509 struct mlx5e_flow_table ft;
510 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
511 };
512
513 #define ARFS_HASH_SHIFT BITS_PER_BYTE
514 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
515 struct arfs_table {
516 struct mlx5e_flow_table ft;
517 struct mlx5_flow_rule *default_rule;
518 struct hlist_head rules_hash[ARFS_HASH_SIZE];
519 };
520
521 enum arfs_type {
522 ARFS_IPV4_TCP,
523 ARFS_IPV6_TCP,
524 ARFS_IPV4_UDP,
525 ARFS_IPV6_UDP,
526 ARFS_NUM_TYPES,
527 };
528
529 struct mlx5e_arfs_tables {
530 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
531 /* Protect aRFS rules list */
532 spinlock_t arfs_lock;
533 struct list_head rules;
534 int last_filter_id;
535 struct workqueue_struct *wq;
536 };
537
538 /* NIC prio FTS */
539 enum {
540 MLX5E_VLAN_FT_LEVEL = 0,
541 MLX5E_L2_FT_LEVEL,
542 MLX5E_TTC_FT_LEVEL,
543 MLX5E_ARFS_FT_LEVEL
544 };
545
546 struct mlx5e_flow_steering {
547 struct mlx5_flow_namespace *ns;
548 struct mlx5e_tc_table tc;
549 struct mlx5e_vlan_table vlan;
550 struct mlx5e_l2_table l2;
551 struct mlx5e_ttc_table ttc;
552 struct mlx5e_arfs_tables arfs;
553 };
554
555 struct mlx5e_direct_tir {
556 u32 tirn;
557 u32 rqtn;
558 };
559
560 enum {
561 MLX5E_TC_PRIO = 0,
562 MLX5E_NIC_PRIO
563 };
564
565 struct mlx5e_priv {
566 /* priv data path fields - start */
567 struct mlx5e_sq **txq_to_sq_map;
568 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
569 /* priv data path fields - end */
570
571 unsigned long state;
572 struct mutex state_lock; /* Protects Interface state */
573 struct mlx5_uar cq_uar;
574 u32 pdn;
575 u32 tdn;
576 struct mlx5_core_mkey mkey;
577 struct mlx5_core_mkey umr_mkey;
578 struct mlx5e_rq drop_rq;
579
580 struct mlx5e_channel **channel;
581 u32 tisn[MLX5E_MAX_NUM_TC];
582 u32 indir_rqtn;
583 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
584 struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
585 u32 tx_rates[MLX5E_MAX_NUM_SQS];
586
587 struct mlx5e_flow_steering fs;
588 struct mlx5e_vxlan_db vxlan;
589
590 struct mlx5e_params params;
591 struct workqueue_struct *wq;
592 struct work_struct update_carrier_work;
593 struct work_struct set_rx_mode_work;
594 struct delayed_work update_stats_work;
595
596 u32 pflags;
597 struct mlx5_core_dev *mdev;
598 struct net_device *netdev;
599 struct mlx5e_stats stats;
600 struct mlx5e_tstamp tstamp;
601 u16 q_counter;
602 };
603
604 enum mlx5e_link_mode {
605 MLX5E_1000BASE_CX_SGMII = 0,
606 MLX5E_1000BASE_KX = 1,
607 MLX5E_10GBASE_CX4 = 2,
608 MLX5E_10GBASE_KX4 = 3,
609 MLX5E_10GBASE_KR = 4,
610 MLX5E_20GBASE_KR2 = 5,
611 MLX5E_40GBASE_CR4 = 6,
612 MLX5E_40GBASE_KR4 = 7,
613 MLX5E_56GBASE_R4 = 8,
614 MLX5E_10GBASE_CR = 12,
615 MLX5E_10GBASE_SR = 13,
616 MLX5E_10GBASE_ER = 14,
617 MLX5E_40GBASE_SR4 = 15,
618 MLX5E_40GBASE_LR4 = 16,
619 MLX5E_100GBASE_CR4 = 20,
620 MLX5E_100GBASE_SR4 = 21,
621 MLX5E_100GBASE_KR4 = 22,
622 MLX5E_100GBASE_LR4 = 23,
623 MLX5E_100BASE_TX = 24,
624 MLX5E_1000BASE_T = 25,
625 MLX5E_10GBASE_T = 26,
626 MLX5E_25GBASE_CR = 27,
627 MLX5E_25GBASE_KR = 28,
628 MLX5E_25GBASE_SR = 29,
629 MLX5E_50GBASE_CR2 = 30,
630 MLX5E_50GBASE_KR2 = 31,
631 MLX5E_LINK_MODES_NUMBER,
632 };
633
634 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
635
636 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
637 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
638 void *accel_priv, select_queue_fallback_t fallback);
639 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
640
641 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
642 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
643 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
644 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
645 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
646
647 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
648 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
649 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
650 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
651 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
652 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
653 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
654 struct mlx5_cqe64 *cqe,
655 u16 byte_cnt,
656 struct mlx5e_mpw_info *wi,
657 struct sk_buff *skb);
658 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
659 struct mlx5_cqe64 *cqe,
660 u16 byte_cnt,
661 struct mlx5e_mpw_info *wi,
662 struct sk_buff *skb);
663 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
664 struct mlx5e_mpw_info *wi);
665 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
666 struct mlx5e_mpw_info *wi);
667 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
668
669 void mlx5e_rx_am(struct mlx5e_rq *rq);
670 void mlx5e_rx_am_work(struct work_struct *work);
671 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
672
673 void mlx5e_update_stats(struct mlx5e_priv *priv);
674
675 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
676 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
677 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
678 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
679 void mlx5e_set_rx_mode_work(struct work_struct *work);
680
681 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
682 struct skb_shared_hwtstamps *hwts);
683 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
684 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
685 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
686 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
687 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
688
689 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
690 u16 vid);
691 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
692 u16 vid);
693 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
694 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
695
696 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
697
698 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
699 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
700
701 int mlx5e_open_locked(struct net_device *netdev);
702 int mlx5e_close_locked(struct net_device *netdev);
703 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
704 u32 *indirection_rqt, int len,
705 int num_channels);
706 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
707
708 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
709 u8 cq_period_mode);
710
711 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
712 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
713 {
714 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
715
716 /* ensure wqe is visible to device before updating doorbell record */
717 dma_wmb();
718
719 *sq->wq.db = cpu_to_be32(sq->pc);
720
721 /* ensure doorbell record is visible to device before ringing the
722 * doorbell
723 */
724 wmb();
725 if (bf_sz)
726 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
727 else
728 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
729 /* flush the write-combining mapped buffer */
730 wmb();
731
732 sq->bf_offset ^= sq->bf_buf_size;
733 }
734
735 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
736 {
737 struct mlx5_core_cq *mcq;
738
739 mcq = &cq->mcq;
740 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
741 }
742
743 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
744 {
745 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
746 MLX5E_MAX_NUM_CHANNELS);
747 }
748
749 static inline int mlx5e_get_mtt_octw(int npages)
750 {
751 return ALIGN(npages, 8) / 2;
752 }
753
754 extern const struct ethtool_ops mlx5e_ethtool_ops;
755 #ifdef CONFIG_MLX5_CORE_EN_DCB
756 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
757 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
758 #endif
759
760 #ifndef CONFIG_RFS_ACCEL
761 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
762 {
763 return 0;
764 }
765
766 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
767
768 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
769 {
770 return -ENOTSUPP;
771 }
772
773 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
774 {
775 return -ENOTSUPP;
776 }
777 #else
778 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
779 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
780 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
781 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
782 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
783 u16 rxq_index, u32 flow_id);
784 #endif
785
786 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
787
788 #endif /* __MLX5_EN_H__ */
Linux kernel - Deliverables
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